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* i965/wm/gen6: Refactor state setupTopi Pohjolainen2015-05-072-45/+77
| | | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Remove unused variablesAnuj Phogat2015-05-071-2/+0
| | | | | Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Change the order of conditions tested in ifAnuj Phogat2015-05-071-3/+4
| | | | | | | | Reduces the number of conditions tested in if to one in case of non-integer formats. Makes no functional changes. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* nir: Allow feq/fne/ieq/ine to be optimized with inot.Matt Turner2015-05-071-0/+4
| | | | | | | | instructions in affected programs: 380 -> 376 (-1.05%) helped: 2 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
* nir: Recognize (a < c || b < c) as min(a, b) < c.Matt Turner2015-05-071-0/+2
| | | | | | | | | | | | | | ... and (a >= c) || (b >= c) as max(a, b) >= c. Similar to commit 97e6c1b9. total instructions in shared programs: 6182276 -> 6182180 (-0.00%) instructions in affected programs: 6400 -> 6304 (-1.50%) helped: 68 HURT: 4 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
* nir: Recognize trivial min/max.Matt Turner2015-05-071-0/+6
| | | | | | | No changes, but does prevent some regressions in the next commit. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
* nir: Recognize i2b(b2i(x)) as x.Matt Turner2015-05-071-0/+1
| | | | | | | | | | Helps the same set of programs as the previous commit. instructions in affected programs: 4490 -> 4346 (-3.21%) helped: 8 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
* nir: Recognize imul(b2i(a), b2i(b)) as a logical AND.Matt Turner2015-05-071-0/+1
| | | | | | | | | | | | Four shaders in Unreal 4's Sun Temple are helped, and gain SIMD16 because we avoid an integer multiplication. instructions in affected programs: 2353 -> 2245 (-4.59%) helped: 4 GAINED: 4 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
* i965/sync: Implement DRI2_Fence extensionChad Versace2015-05-074-41/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync. Below is the difference in piglit results, before and after this patch. No regressions and several tests improve from 'skip' to 'pass'. Out of EGL_KHR_fence_sync tests, two of the multithreaded tests skip; all other tests pass. cmdline: piglit run -p gbm -t sync tests/quick.py mesa: master@1ac7db0 piglit: 4069bec hw: Ivybridge | before after ------+------------- pass | 32 46 fail | 0 0 crash | 0 0 skip | 35 21 total | 67 67 v2: - Set fence->signalled = true in brw_fence_has_completed() too. Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'Chad Versace2015-05-072-28/+31
| | | | | | | | | | | | | | | | | | I'm about to implement DRI2_Fenc in intel_syncobj.c. To prevent madness, we need to prefix functions for GL_ARB_sync with 'gl' and functions for DRI2_Fence with 'dri'. Otherwise, the file will become a jumble of similiarly named functions. For example: old-name: intel_client_wait_sync() new-name: intel_gl_client_wait_sync() soon-to-come: intel_dri_client_wait_sync() I wrote this renaming commit separately from the commit that implements DRI2_Fence because I wanted the latter diff to be reviewable. Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i915/sync: Return early when calloc failsChad Versace2015-05-071-0/+2
| | | | | Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/sync: Return NULL when calloc failsChad Versace2015-05-071-0/+2
| | | | | Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i915/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
| | | | | | | | | Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that. Bug found by code inspection. Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
| | | | | | | | | Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that. Bug found by code inspection. Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* egl/dri2: Fix codestyle in a commentChad Versace2015-05-071-1/+2
| | | | Pointed out by Kenneth Graunke. Trivial fix.
* glx: report which DRI version is used when in verbose debug modeMartin Peres2015-05-072-0/+4
| | | | | | | | This should make it more obvious in bug reports while also removing any sort of guesswork for developers. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
* glapi: Add positional argument specifier.Vinson Lee2015-05-061-1/+1
| | | | | | | | | | | | | | | | | Fix build error introduced with commit 1c5a57a "glapi/es3.1: Add support for GLES versions > 3.0" with Python < 2.7. File "src/mapi/glapi/gen/gl_genexec.py", line 230, in <module> printer.Print(api) File "src/mapi/glapi/gen/gl_XML.py", line 120, in Print self.printBody(api) File "src/mapi/glapi/gen/gl_genexec.py", line 187, in printBody condition_parts.append('(ctx->API == API_OPENGLES2 && ctx->Version >= {})'.format(int(f.api_map['es2'] * 10))) ValueError: zero length field name in format Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* nv50/ir: add SHL to the list of U32 opcodesIlia Mirkin2015-05-061-0/+1
| | | | | | | | Having the wrong inferred type prevents a number of optimizations, including constant propagation (since float immediates work differently than integer immediates). Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* i965: Sort extension enable listsIan Romanick2015-05-061-33/+42
| | | | | | | Sort by GEN, then sort by extension name. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* r600g: Fix Clang return-type build error.Vinson Lee2015-05-061-1/+1
| | | | | | | | | | | | | | Fix Clang return-type error introduced with commit 96f164f6f047833091eb98a73aa80c31dc94f962 "gallium: make pipe_context::begin_query return a boolean". CC r600_query.lo r600_query.c:443:3: error: non-void function 'r600_begin_query' should return a value [-Wreturn-type] return; ^ Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* i965/fs: Allow copy propagation on ATTR file registers.Kenneth Graunke2015-05-061-1/+4
| | | | | | | | | | | | | | | | | | | | | | This especially helps with NIR because we currently emit MOVs at the top of the shader to copy from various ATTR registers to a giant VGRF array of all inputs. (This could potentially be done better, but since there's only ever one write to each register, it should be trivial to copy propagate away...) With NIR - only vertex shaders: total instructions in shared programs: 3129373 -> 2889581 (-7.66%) instructions in affected programs: 3119717 -> 2879925 (-7.69%) helped: 20833 Without NIR - only vertex shaders: total instructions in shared programs: 2745901 -> 2724483 (-0.78%) instructions in affected programs: 693426 -> 672008 (-3.09%) helped: 3516 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
* i965/fs_inst: Get rid of the effective_width fieldJason Ekstrand2015-05-063-37/+3
| | | | | | | | The effective_width field was an ill-concieved hack to get around issues in the LOAD_PAYLOAD instruction. Now that the LOAD_PAYLOAD instruction is far more sane, this field can die. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs: Rework the fs_visitor LOAD_PAYLOAD instructionJason Ekstrand2015-05-064-236/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly reworked instruction is far more straightforward than the original. Before, the LOAD_PAYLOAD instruction was lowered by a the complicated and broken-by-design pile of heuristics to try and guess force_writemask_all, exec_size, and a number of other factors on the sources. Instead, we use the header_size on the instruction to denote which sources are "header sources". Header sources are required to be a single physical hardware register that is copied verbatim. The registers that follow are considered the actual payload registers and have a width that correspond's to the LOAD_PAYLOAD's exec_size and are treated as being per-channel. This gives us a fairly straightforward lowering: 1) All header sources are copied directly using force_writemask_all and, since they are guaranteed to be a single register, there are no force_sechalf issues. 2) All non-header sources are copied using the exact same force_sechalf and force_writemask_all modifiers as the LOAD_PAYLOAD operation itself. 3) In order to accommodate older gens that need interleaved colors, lower_load_payload detects when the destination is a COMPR4 register and automatically interleaves the non-header sources. The lower_load_payload pass does the right thing here regardless of whether or not the hardware actually supports COMPR4. This patch commit itself is made up of a bunch of smaller changes squashed together. Individual change descriptions follow: i965/fs: Rework fs_visitor::LOAD_PAYLOAD We rework LOAD_PAYLOAD to verify that all of the sources that count as headers are, indeed, exactly one register and that all of the non-header sources match the destination width. We then take the exec_size for LOAD_PAYLOAD directly from the destination width. i965/fs: Make destinations of load_payload have the appropreate width i965/fs: Rework fs_visitor::lower_load_payload v2: Don't allow the saturate flag on LOAD_PAYLOAD instructions i965/fs_cse: Support the new-style LOAD_PAYLOAD i965/fs_inst::is_copy_payload: Support the new-style LOAD_PAYLOAD i965/fs: Simplify setup_color_payload Previously, setup_color_payload was a a big helper function that did a lot of gen-specific special casing for setting up the color sources of the LOAD_PAYLOAD instruction. Now that lower_load_payload is much more sane, most of that complexity isn't needed anymore. Instead, we can do a simple fixup pass for color clamps and then just stash sources directly in the LOAD_PAYLOAD. We can trust lower_load_payload to do the right thing with respect to COMPR4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs: Make LOAD_PAYLOAD take a header sizeJason Ekstrand2015-05-064-12/+20
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs: Make emit_single_fb_write take an explicit exec_sizeJason Ekstrand2015-05-062-8/+10
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs_inst: Add an is_copy_payload helperJason Ekstrand2015-05-064-35/+25
| | | | | | | | | | This commit adds a new is_copy_payload helper to fs_inst that takes the place of the similarly named functions in cse and register coalesce. The two is_copy_payload functions in CSE and register coalesce were subtly different and potentially subtly broken. The new version unifies the two and should be more correct. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Change header_present to header_size in backend_instructionJason Ekstrand2015-05-069-52/+56
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs_cse: Factor out code to create copy instructionsJason Ekstrand2015-05-061-37/+38
| | | | | | | | v2: Get rid of the block parameter and make src a const reference Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs: Make half(fs_reg, unsigned) handle register files more explicitlyJason Ekstrand2015-05-061-5/+16
| | | | | | | | | Previously, we had a special case for uniforms and immediates and then a bunch of asserts for various other pessimal things. This commit changes it so that it explicitly does something on each register file. Some of them are disallowed and others are treated properly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs: Fix passing an immediate to half().Francisco Jerez2015-05-061-2/+2
| | | | | | | Immediates are generally uniform, they yield the same value to both halves of any instruction. Reviewed-by: Matt Turner <mattst88@gmail.com>
* swrast: Build fix for darwinJeremy Huddleston Sequoia2015-05-061-0/+16
| | | | | | | | | | | Fixes regression from commit 64b1dc44495890cbc2c7c5509cb830264020998c Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90147 Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com> Reviewed-by: Brian Paul <brianp@vmware.com> CC: Emil Velikov <emil.l.velikov@gmail.com> CC: jon.turney@dronecode.org.uk CC: ionic@macports.org
* egl/dri2: Check return value of __DRI2fence::create_fence()Chad Versace2015-05-061-0/+7
| | | | | | If it returns NULL, then return early with an error. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* draw: (trivial) fix out-of-bounds vector initializationRoland Scheidegger2015-05-061-1/+1
| | | | | | | | | | | | Was off-by-one. llvm says inserting an element with an index higher than the number of elements yields undefined results. Previously such inserts were ignored but as of llvm revision 235854 the vector gets replaced with undef, causing failures. This fixes piglit gl-3.2-layered-rendering-gl-layer, as mentioned in https://llvm.org/bugs/show_bug.cgi?id=23424. Reviewed-by: Brian Paul <brianp@vmware.com> Cc: mesa-stable@lists.freedesktop.org
* main/queryobj: add GL_QUERY_TARGET support to GetQueryObjectiv()Martin Peres2015-05-061-0/+12
| | | | | | | | This was missing from my patchset to support the query-related entry points of Direct State Access. Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
* ilo: silence a compiler warningChia-I Wu2015-05-061-1/+1
| | | | | | | | Silence ilo_query.c:120:7: warning: 'return' with no value, in function returning non-void since commit 96f164f6.
* mesa: support compute stage in _mesa_program_resource_propTapani Pälli2015-05-061-6/+16
| | | | | | | | | | Increases pass rate of ES31-CTS.*program_interface_query* tests when run with MESA_EXTENSION_OVERRIDE='GL_ARB_compute_shader'. Many of the negative tests that happen to use compute stage in queries start passing. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
* glsl: mark special built-in inputs referenced by vertex stageTapani Pälli2015-05-061-1/+6
| | | | | | | | | | | | | | | Refactoring done on active attribute queries did not take in to account special built-in inputs for the vertex stage. This commit sets them referenced by vertex stage so that they get enumerated properly. Fixes Piglit test 'get-active-attrib-returns-all-inputs' failure. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90243 Acked-by: Jose Fonseca <jfonseca@vmware.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-By: Martin Peres <martin.peres@linux.intel.com>
* relnotes: Note support for viewport arrays on i965/Gen6.Chris Forbes2015-05-061-0/+1
| | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
* i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_indexChris Forbes2015-05-061-8/+8
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6: Upload all the SF viewportsChris Forbes2015-05-062-12/+19
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6: Upload all the clip viewportsChris Forbes2015-05-061-19/+21
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-062-3/+3
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* st/mesa: fix pipe_query_result result initializerBrian Paul2015-05-051-1/+1
| | | | | | Fixes MSVC build error. Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* st/mesa: fix st_NewPerfMonitor() declarationBrian Paul2015-05-051-1/+1
| | | | | | Was missing the context parameter. Fixes MSVC warning. Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* glsl: add parens in shader_integer_mix() to silence compiler warningBrian Paul2015-05-051-1/+1
| | | | | | | | Silences gcc warning: builtin_functions.cpp:204:23: warning: suggest parentheses around '&&' within '||' [-Wparentheses] Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* st/mesa: also try PIPE_FORMAT_R10G10B10A2_UNORM for GL_RGB10Brian Paul2015-05-051-1/+1
| | | | Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: all queries use an unsigned 64-bits integer by defaultSamuel Pitoiset2015-05-061-5/+7
| | | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Martin Peres <martin.peres@free.fr>
* nvc0: make begin_query return false when all MP counters are usedSamuel Pitoiset2015-05-061-5/+8
| | | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Martin Peres <martin.peres@free.fr>
* docs: mark GL_AMD_performance_monitor on nvc0 for the 10.6.0 releaseSamuel Pitoiset2015-05-061-0/+1
| | | | | | | | Other drivers which want to enable this extension must expose groups of GPU hardware performance counters. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr>
* nvc0: define driver-specific query groupsSamuel Pitoiset2015-05-063-0/+76
| | | | | | | | This patch defines "Driver statistics" and "MP counters" groups, but only the latter will be exposed through GL_AMD_performance_monitor. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr>
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