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path: root/src/compiler/nir/nir_opcodes.py
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* nir: fix definition of pack_uvec2_to_uintIlia Mirkin2016-09-061-1/+1
| | | | | | | | | Found by inspection. Untested beyond compilation. This also matches the logic used in nir_lower_alu_to_scalar. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Cc: mesa-stable@lists.freedesktop.org
* nir: handle double-precision in fsign, fsat, fnot and frcpIago Toral Quiroga2016-05-231-4/+9
| | | | | | | | I think these are not strictly necessary since the floats in them should be automatically promoted to doubles when operated with double sources, but it makes things more explicit at least. Reviewed-by: Matt Turner <mattst88@gmail.com>
* nir: handle double-precision in fabs, frsq and fsqrtIago Toral Quiroga2016-05-231-3/+3
| | | | Reviewed-by: Matt Turner <mattst88@gmail.com>
* nir: fix comment typo about f2d/d2fRob Clark2016-05-151-2/+2
| | | | | Signed-off-by: Rob Clark <robclark@freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* nir/opcodes: Make ldexp take an explicitly 32-bit intJason Ekstrand2016-04-281-1/+1
| | | | | | | | | There is no sense in having the double version of ldexp take a 64-bit integer. Instead, let's just take a 32-bit int all the time. This also matches what GLSL does where both variants of ldexp take a regular integer for the exponent argument. Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
* nir/opcodes: Simplify the expressions for [un]pack_doubleJason Ekstrand2016-04-281-61/+8
| | | | | | | | | | The new expressions are more explicit in terms of where the bits go so it's a little easier to tell what's going on. This is the way GLSL specifies things so it's a bit easier to verify too. It also has the benifit that the new expressions easily vectorize so we can constant-fold vector forms of the _split versions correctly. Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
* nir: Add more modulus opcodesJason Ekstrand2016-04-131-1/+15
| | | | | | | These are all needed for SPIR-V Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* nir: add split versions of (un)pack_double_2x32Connor Abbott2016-04-111-0/+36
| | | | | | | | v2 (Sam): - Use uint64 instead of float64 for sources and destinations. (Connor) Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: add support for (un)pack_double_2x32Connor Abbott2016-04-111-0/+29
| | | | | | | | v2 (Sam): - Use uint64 instead of float64 for sources and destinations. (Connor) Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: add i2d and u2d opcodesIago Toral Quiroga2016-04-111-0/+2
| | | | | | | v2: - Assert supports_int and don't fallback to nir_fmov (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: add d2i, d2u, d2b opcodesIago Toral Quiroga2016-04-111-0/+3
| | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: add support for d2f and f2dConnor Abbott2016-04-111-0/+3
| | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir: Add an opcode for stomping a 32-bit value to 16-bit precisionJason Ekstrand2016-04-011-0/+1
| | | | | | This correlates directly to the SPIR-V opcode OpQuantizeToF16 Reviewed-by: Rob Clark <robdclark@gmail.com>
* nir: update opcode definitions for different bit sizesConnor Abbott2016-03-171-67/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some opcodes need explicit bitsizes, and sometimes we need to use the double version when constant folding. v2: fix output type for u2f (Iago) v3: do not change vecN opcodes to be float. The next commit will add infrastructure to enable 64-bit integer constant folding so this is isn't really necessary. Also, that created problems with source modifiers in some cases (Iago) v4 (Jason): - do not change bcsel to work in terms of floats - leave ldexp generic Squashed changes to handle different bit sizes when constant folding since otherwise we would break the build. v2: - Use the bit-size information from the opcode information if defined (Iago) - Use helpers to get type size and base type of nir_alu_type enum (Sam) - Do not fallback to sized types to guess bit-size information. (Jason) Squashed changes in i965 and gallium/nir drivers to support sized types. These functions should only see sized types, but we can't make that change until we make sure that nir uses the sized versions in all the relevant places. A later commit will address this. Signed-off-by: Iago Toral Quiroga <itoral@igalia.com> Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: Add lowering support for packing opcodes.Matt Turner2016-02-011-0/+10
| | | | Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: Add opcodes to extract bytes or words.Matt Turner2016-02-011-0/+9
| | | | | | The uint versions zero extend while the int versions sign extend. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: Make argument order of unop_convert match binop_convert.Matt Turner2016-02-011-10/+10
| | | | | | Strangely the return and parameter types were reversed. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* nir: move to compiler/Emil Velikov2016-01-261-0/+668
Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: Matt Turner <mattst88@gmail.com> Acked-by: Jose Fonseca <jfonseca@vmware.com>
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