summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/radeon/r600_pipe_common.c
Commit message (Collapse)AuthorAgeFilesLines
...
* gallium/radeon: implement randomized SDMA texture copy testing (v2)Marek Olšák2016-05-101-0/+2
| | | | | | | | | | | v2: - adjustments for exercising all important SDMA code paths - decrease the probability of getting huge sizes (faster testing) - increase the probability of getting power-of-two dimensions - change the memory cap to 128MB (faster testing) - better detect which engine has been used Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: use gart_page_size instead of hardcoded 4096Marek Olšák2016-05-101-3/+7
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: remove tile_mode_array_valid flagsMarek Olšák2016-05-021-2/+0
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: add the size only once in r600_context_add_resource_sizeMarek Olšák2016-04-281-5/+3
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: rework clear_buffer flagsMarek Olšák2016-04-281-2/+2
| | | | | | | | | Changes: - don't flush DB for fast color clears - don't flush any caches for initial clears - remove the flag from si_copy_buffer, always assume shader coherency Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*Marek Olšák2016-04-221-6/+6
| | | | Acked-by: Jose Fonseca <jfonseca@vmware.com>
* radeonsi: enable TGSI support cap for compute shadersBas Nieuwenhuizen2016-04-191-5/+16
| | | | | | | | | | | | v2: Use chip_class instead of family. v3: Check kernel version for SI. v4: Preemptively allow amdgpu winsys for SI. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: Create CE IB.Bas Nieuwenhuizen2016-04-191-0/+1
| | | | | | | | | | | | | | | | | | | Based on work by Marek Olšák. v2: Add preamble IB. Leaves the load packet in the space calculation as the radeon winsys might not be able to support a premable. The added space calculation may look expensive, but is converted to a constant with (at least) -O2 and -O3. v3: - Fix code style. - Remove needed space for vertex buffer descriptors. - Fail when the preamble cannot be created. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: add an env variable to force a level of aniso filteringMarek Olšák2016-04-131-0/+7
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move scissor and viewport states into gallium/radeonMarek Olšák2016-04-121-0/+1
| | | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Grigori Goronzy <greg@chown.ath.cx> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: allow clearing buffers >= 4 GBMarek Olšák2016-04-121-1/+1
| | | | | | | Only CMASK and DCC clears can use this, because only textures can be so large. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: merge timer and non-timer query listsMarek Olšák2016-04-121-14/+4
| | | | | | | All of them are paused only between IBs. Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium: distinguish between shader IR in get_compute_paramBas Nieuwenhuizen2016-04-021-1/+2
| | | | | | | | | | | | | For radeonsi, native and TGSI use different compilers and this results in different limits for different IR's. The set we strictly need for radeonsi is only the MAX_BLOCK_SIZE and MAX_THREADS_PER_BLOCK params, but I added a few others as shader related that seemed like they would also typically depend on the compiler. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Dave Airlie <airlied@redhat.com>
* radeonsi: add support for Polaris (v2)Sonny Jiang2016-03-241-0/+9
| | | | | | | | | v2: Polaris chips should be defined after Stoney Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> (v1) Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1) Signed-off-by: Leo Liu <leo.liu@amd.com> (v2 diff) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2 diff)
* gallium/radeon: remove old CS tracingMarek Olšák2016-03-201-19/+2
| | | | | | | | | | | | | | Cons: - it was only integrated in r600g - it doesn't work with GPUVM - it records buffer contents at the end of IBs instead of at the beginning, so the replay isn't exact - it lacks an IB parser and user-friendliness A better solution is apitrace in combination with gallium/ddebug, which has a complete IB parser and can pinpoint hanging CP packets. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: enable compiling one variant per shaderMarek Olšák2016-02-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Shader stats from VERDE: Default scheduler: Totals: SGPRS: 491272 -> 488672 (-0.53 %) VGPRS: 289980 -> 311093 (7.28 %) Code Size: 11091656 -> 11219948 (1.16 %) bytes LDS: 97 -> 97 (0.00 %) blocks Scratch: 1732608 -> 2246656 (29.67 %) bytes per wave Max Waves: 78063 -> 77352 (-0.91 %) Wait states: 0 -> 0 (0.00 %) Looking at some of the worst regressions, I get: - The VGPR increase seems to be caused by the fact that if PS has used less than 16 VGPRs, now it will always use 16 VGPRs and sometimes even 20. However, the wave count remains at 10 if VGPRs <= 24, so no harm there. - The scratch increase seems to be caused by SGPR spilling. The unnecessary SGPR spilling has been an ongoing issue with the compiler and it's completely fixable by rematerializing s_loads or reordering instructions. SI scheduler: Totals: SGPRS: 374848 -> 374576 (-0.07 %) VGPRS: 284456 -> 307515 (8.11 %) Code Size: 11433068 -> 11535452 (0.90 %) bytes LDS: 97 -> 97 (0.00 %) blocks Scratch: 509952 -> 522240 (2.41 %) bytes per wave Max Waves: 79456 -> 78217 (-1.56 %) Wait states: 0 -> 0 (0.00 %) VGPRs - same story as before. The SI scheduler doesn't spill SGPRs so much and generally spills way less than the default scheduler. (522240 spills vs 2246656 spills) Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: drop support for LLVM 3.5Marek Olšák2016-02-111-6/+1
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> v2: adjust the comment in the amdgpu winsys
* gallium/radeon: implement query_memory_info (v2)Marek Olšák2016-02-051-0/+37
| | | | | | | v2: don't use DIV_ROUND_UP (no so useful) also return eviction stats Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* gallium/radeon: remove radeon_info::r600_tiling_configMarek Olšák2016-02-051-1/+0
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsysMarek Olšák2016-02-051-56/+1
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: set num_banks in the winsysMarek Olšák2016-02-051-25/+1
| | | | | | | amdgpu doesn't have to set this, because radeonsi gets it from tile mode arrays by default. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: just get num_tile_pipes from the winsysMarek Olšák2016-02-051-34/+0
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: rename & reorder members of radeon_infoMarek Olšák2016-02-051-20/+26
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: Allow dumping LLVM IR before optimization passesNicolai Hähnle2016-02-051-0/+1
| | | | | | | | | | | | | | Set R600_DEBUG=preoptir to dump the LLVM IR before optimization passes, to allow diagnosing problems caused by optimization passes. Note that in order to compile the resulting IR with llc, you will first have to run at least the mem2reg pass, e.g. opt -mem2reg -S < shader.ll | llc -march=amdgcn -mcpu=bonaire Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (original patch) Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (w/ debug flag) Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: Add option for SI schedulerAxel Davy2016-01-281-0/+1
| | | | | | | | | | Add a debug option to select the LLVM SI Machine Scheduler. R600_DEBUG=sisched Signed-off-by: Axel Davy <axel.davy@ens.fr> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* r600,compute: Plug few memory leaksJan Vesely2016-01-261-0/+20
| | | | | | | | | | | v2: drop inline keyword drop radeon_llvm_dispose_kernel_module wrapper v3: move definitions to .c file use in radeonsi Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: rename max_compute_units -> num_good_compute_unitsMarek Olšák2016-01-221-2/+2
| | | | | | radeon sets this correctly, but not amdgpu Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFERNicolai Hähnle2016-01-141-0/+1
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: r600_can_dump_shader should get TGSI processor type directlyMarek Olšák2016-01-031-6/+2
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: implement set_debug_callbackNicolai Hähnle2016-01-021-0/+12
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* u_upload_mgr: allow specifying PIPE_USAGE_* for the upload bufferMarek Olšák2016-01-021-1/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* u_upload_mgr: remove alignment parameter from u_upload_createMarek Olšák2016-01-021-1/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* u_upload_mgr: pass alignment to u_upload_alloc manuallyMarek Olšák2016-01-021-1/+1
| | | | | | | | | | The fixed alignment of u_upload_mgr will go away. This is the first step. The motivation is that one u_upload_mgr can have multiple users, each allocating from the same buffer, but requiring a different alignment. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: remove radeon_winsys_cs_handleMarek Olšák2015-12-111-1/+1
| | | | | | | | "radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf". Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: implement RB+ for Stoney (v2)Marek Olšák2015-12-111-0/+1
| | | | | | v2: fix dual source blending Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* gallium/drivers: Sanitize NULL checks into canonical formEdward O'Callaghan2015-12-061-1/+1
| | | | | | | | | | Use NULL tests of the form `if (ptr)' or `if (!ptr)'. They do not depend on the definition of the symbol NULL. Further, they provide the opportunity for the accidental assignment, are clear and succinct. Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: fix Fiji for LLVM <= 3.7Marek Olšák2015-12-031-1/+2
| | | | | Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: fix occlusion queries on FijiMarek Olšák2015-12-031-2/+2
| | | | Tested.
* gallium/radeon: remove DBG_TEXMIPMarek Olšák2015-12-031-1/+0
| | | | | | we don't need 2 flags for dumping texture info Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeon: only suspend queries on flush if they haven't been suspended yetNicolai Hähnle2015-11-281-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Non-timer queries are suspended during blits. When the blits end, the queries are resumed, but this resume operation itself might run out of CS space and trigger a flush. When this happens, we must prevent a duplicate suspend during preflush suspend, and we must also prevent a duplicate resume when the CS flush returns back to the original resume operation. This fixes a regression that was introduced by: commit 8a125afa6e88a3eeddba8c7fdc1a75c9b99d5489 Author: Nicolai Hähnle <nhaehnle@gmail.com> Date: Wed Nov 18 18:40:22 2015 +0100 radeon: ensure that timing/profiling queries are suspended on flush The queries_suspended_for_flush flag is redundant because suspended queries are not removed from their respective linked list. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reported-by: Axel Davy <axel.davy@ens.fr> Cc: "11.1" <mesa-stable@lists.freedesktop.org> Tested-by: Axel Davy <axel.davy@ens.fr> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: implement AMD_performance_monitor for CIK+Nicolai Hähnle2015-11-251-0/+1
| | | | | | | | | | | | | | | | | | Expose most of the performance counter groups that are exposed by Catalyst. Ideally, the driver will work with GPUPerfStudio at some point, but we are not quite there yet. In any case, this is the reason for grouping multiple instances of hardware blocks in the way it is implemented. The counters can also be shown using the Gallium HUD. If one is interested to see how work is distributed across multiple shader engines, one can set the environment variable RADEON_PC_SEPARATE_SE=1 to obtain finer-grained performance counter groups. Part of the implementation is in radeon because an implementation for older hardware would largely follow along the same lines, but exposing a different set of blocks which are programmed slightly differently. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeon: ensure that timing/profiling queries are suspended on flushNicolai Hähnle2015-11-201-7/+6
| | | | | | | The queries_suspended_for_flush flag is redundant because suspended queries are not removed from their respective linked list. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeon: move get_driver_query_info to r600_query.cNicolai Hähnle2015-11-181-45/+1
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: atomize render condition (SET_PREDICATION)Marek Olšák2015-11-131-6/+0
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: simplify restoring render condition after flushMarek Olšák2015-11-131-17/+5
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: inline the r600_rings structureMarek Olšák2015-11-131-17/+17
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: remove the IB flushing flagMarek Olšák2015-11-131-7/+2
| | | | | | | Not needed anymore. A similar flag will be introduced in the next commit, which will be private in radeonsi. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: move GFX/DMA flushing from add_to_buffer_list to need_cs_spaceMarek Olšák2015-11-131-0/+4
| | | | | | | | need_cs_space isn't invoked so often and is called before all commands too. This is a lot cleaner. The code in radeon_add_to_buffer_list always seemed dodgy to me. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: allow returning SDMA fences from pipe->flushMarek Olšák2015-11-041-8/+56
| | | | | | | pipe->flush never returned SDMA fences. This fixes it. This is only an issue on amdgpu where fences can signal out of order. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: always return the last SDMA fence on SDMA flush if neededMarek Olšák2015-11-041-4/+7
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
generated by cgit v1.1 at 2024-05-20 12:12:32 +0000