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* radeonsi: remove si_shader::ps_input_interpolateMarek Olšák2016-02-091-1/+0
| | | | | | tgsi_shader_info has this too. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move BCOLOR PS input locations after all other inputsMarek Olšák2016-02-091-2/+0
| | | | | | | | | | | | | | | | BCOLOR inputs were immediately after COLOR inputs. Thus, all following inputs were offset by 1 if color_two_side was enabled, and not offset if it was not enabled, which is a variation that's problematic if we want to have 1 variant per shader and the variant doesn't care about color_two_side (that should be handled by other bytecode attached at the beginning). Instead, move BCOLOR inputs after all other inputs, so BCOLOR0 is at location "num_inputs" if it's present. BCOLOR1 is next. This also allows removing si_shader::nparam and si_shader::ps_input_param_offset, which are useless now. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* r600,compute: Plug few memory leaksJan Vesely2016-01-261-1/+0
| | | | | | | | | | | v2: drop inline keyword drop radeon_llvm_dispose_kernel_module wrapper v3: move definitions to .c file use in radeonsi Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: move is_gs_copy_shader to si_shader_contextNicolai Hähnle2016-01-251-1/+0
| | | | | | | | It is only used during shader creation now, so no need to keep it around afterwards. Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: disable SPI color outputs the shader doesn't writeMarek Olšák2016-01-221-0/+4
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: add shader conversion code for all SPI color formatsMarek Olšák2016-01-221-0/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: use SPI_SHADER_COL_FORMAT fields instead of export_16bpcMarek Olšák2016-01-221-1/+1
| | | | | | | | | | | | | This does change the behavior slightly: If a shader writes COLOR[i] and that color buffer isn't bound, the shader will export MRT_NULL instead and discard the IR tree that calculates the output. The only exception is alpha-to-coverage, which requires an alpha export. v2: - update a comment about 16BPC - account for MRTZ when when fixing alpha-test/kill Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: adjust the parameters of si_shader_dumpMarek Olšák2016-01-071-5/+2
| | | | | | | The function will be extended to dump all binaries shaders will consist of, so si_shader* makes sense here. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: inline si_shader_binary_readMarek Olšák2016-01-071-2/+0
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move si_shader_dump call out of si_shader_binary_readMarek Olšák2016-01-071-5/+7
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: add si_shader_destroy_binaryMarek Olšák2016-01-071-0/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: don't pass si_shader to si_compile_llvmMarek Olšák2016-01-071-3/+7
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: don't pass si_shader to si_shader_binary_readMarek Olšák2016-01-071-2/+5
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: don't pass si_shader to si_shader_binary_read_configMarek Olšák2016-01-071-1/+2
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: add struct si_shader_configMarek Olšák2016-01-071-10/+13
| | | | | | | There will be 1 config per variant, which will be a union of configs from {prolog, main, epilog}. For now, just add the structure. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: set SPI color formats and CB_SHADER_MASK outside of compilationMarek Olšák2016-01-071-2/+0
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: determine SPI_SHADER_Z_FORMAT outside of shader compilationMarek Olšák2016-01-071-1/+0
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: determine DB_SHADER_CONTROL outside of shader compilationMarek Olšák2016-01-071-1/+4
| | | | | | | because the API pixel shader binary will not emulate alpha test one day, so the KILL_ENABLE bit must be determined elsewhere. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: remove unused parameter from si_shader_binary_read_configMarek Olšák2016-01-031-3/+2
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move si_shader_binary_upload out of si_shader_binary_readMarek Olšák2016-01-031-2/+2
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: pass TGSI processor type to si_shader_binary_read for dumpingMarek Olšák2016-01-031-1/+1
| | | | | | | the parameter will be used later Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: pass TGSI processor type to si_compile_llvm for dumpingMarek Olšák2016-01-031-1/+1
| | | | | | | the parameter will be used later Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: rename shader parameter definitions and variables for more clarityMarek Olšák2016-01-031-8/+8
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: pass pipe_debug_callback down into si_shader_binary_read (v2)Nicolai Hähnle2016-01-021-3/+6
| | | | | | | This will allow us to send shader debug info. Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: use tgsi_shader_info::colors_writtenMarek Olšák2015-12-111-1/+0
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}Tom Stellard2015-11-251-2/+2
| | | | | | In the future, these will be used by other shaders types. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: remove dead code after ES-GS linkage changeMarek Olšák2015-11-131-1/+0
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: link ES-GS just like LS-HSMarek Olšák2015-11-131-12/+9
| | | | | | | | | | | | This reduces the shader key for ES. Use a fixed attrib location based on (semantic name, index). The ESGS item size is determined by the physical index of the highest ES output, so it's almost always larger than before, but I think that shouldn't matter as long as the ESGS ring buffer is large enough. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: calculate optimal GS ring sizes to fix GS hangs on TongaMarek Olšák2015-11-131-0/+1
| | | | | | | | | | | | | | I discovered that increasing the ESGS ring size fixes GS hangs on Tonga, so let's do it properly. There is now a separate init_config_gs_rings state that is not immutable, because GS rings are resized when needed. This also saves some memory. Most apps won't need more than 1MB per ring per shader engine. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: calculate ESGS_RING_ITEMSIZE in create_shaderMarek Olšák2015-11-131-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move maximum gs stream calculation into create_shaderMarek Olšák2015-11-131-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: clean up small duplication in si_shader_gsMarek Olšák2015-11-131-1/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: fix the export_prim_id field size in the shader keyMarek Olšák2015-10-201-2/+2
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: support thread-safe shaders shared by multiple contextsMarek Olšák2015-10-201-14/+17
| | | | | | | | | | | | The "current" shader pointer is moved from the CSO to the context, so that the CSO is mostly immutable. The only drawback is that the "current" pointer isn't saved when unbinding a shader and it must be looked up when the shader is bound again. This is also a prerequisite for multithreaded shader compilation. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: implement vertex color clampingMarek Olšák2015-10-171-2/+6
| | | | | | This is only supported in the compatibility profile (without GS and tess). Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: implement fragment color clampingMarek Olšák2015-10-171-0/+1
| | | | | | using the shader key for now. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: remove an unused ctx parameter in si_shader_destroyMarek Olšák2015-10-171-1/+1
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: do force_persample_interp in shaders for non-trivial casesMarek Olšák2015-10-031-18/+31
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: don't rebind GSVS ring buffers every draw call using GSMarek Olšák2015-09-011-0/+1
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* radeonsi: optimize scissor statesMarek Olšák2015-09-011-1/+3
| | | | | | | | | - convert 16 states to 1 atom - only emit 1 scissor if VIEWPORT_INDEX isn't written - use only one packet when emitting consecutive scissors Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* radeonsi: fix a Unigine Heaven hang when drirc is missingMarek Olšák2015-09-011-0/+1
| | | | | | Cc: 10.6 11.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* radeonsi: allow si_dump_key to write to a fileMarek Olšák2015-08-261-0/+1
| | | | | Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: add support for gl_PrimitiveID in the fragment shaderMarek Olšák2015-08-131-0/+12
| | | | | | | | | | It must be obtained from the VS. The GS scenario A must be enabled for PrimID to be generated for the VS. + 4 piglits Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: split out interpolation input selectionDave Airlie2015-07-251-1/+1
| | | | | | | | | | | This is prep work for using it in the interpolation code later. Also add storage for the input interpolation mode so we can pick it up later. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* radeonsi: add tessellation shader statesMarek Olšák2015-07-231-0/+3
| | | | | | ls_rsrc# will be emitted as part of the derived tessellation state Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: update si_get_vs_info and si_get_vs_state for tessellationMarek Olšák2015-07-231-2/+8
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: add shader code generation for tessellationMarek Olšák2015-07-231-5/+104
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: make ES2GS offset sgpr location dynamicMarek Olšák2015-07-231-3/+0
| | | | | | It will have a different location in the tessellation evaluation shader. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: upload shader rodata after updating scratch relocationsMarek Olšák2015-07-231-0/+1
| | | | | | Cc: 10.5 10.6 <mesa-stable@lists.freedesktop.org> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: remove redundant parameter in si_shader_binary_readMarek Olšák2015-07-231-2/+1
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
generated by cgit v1.1 at 2025-07-25 08:46:18 +0000