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* svga: add SVGA3d_vgpu10_TransferFromBuffer()Charmaine Lee2016-09-173-0/+51
| | | | | | Also add the corresponding dump function to dump the TransferFromBuffer command. Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: single sample surface can be created as non-multisamples surfaceCharmaine Lee2016-09-172-2/+6
| | | | | | | | | With this patch, single sample surface will be created as non-multisamples surface. Tested with piglit, glretrace. Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: fix memory leak with sampler stateCharmaine Lee2016-09-171-3/+0
| | | | | | | | | | | This patch fixes a memory leak with sampler state when piglit is run with HW version 11. Sampler state clean up was incorrectly skipped in svga_cleanup_sampler_state() for vgpu9. Tested with piglit. Reviewed-by: Neha Bhende <bhenden@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: fix prim type check/assignment in translate_indices()Brian Paul2016-09-171-2/+2
| | | | | | | | Left over test code spotted by Sinclair. Tested with piglit, Google Earth, Lightsmark, Heaven4, glretraces, etc. Reviewed-by: Sinclair Yeh <syeh@vmware.com>
* svga: use SVGA3D_QUERYTYPE_MAX for svga query type checkCharmaine Lee2016-09-171-3/+3
| | | | | | | | | Use SVGA3D_QUERYTYPE_MAX instead of SVGA_QUERY_MAX for svga query type check. Tested with various OpenGL apps with GALLIUM_HUD set. Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: split the num-resources-mapped hud to textures & buffersCharmaine Lee2016-09-175-12/+26
| | | | | | | | Replace the num-resources-mapped hud with num-textures-mapped and num-buffers-mapped, so we can differentiate the map counts for these two different resources. Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: change svga hud defines to enumsCharmaine Lee2016-09-171-22/+25
| | | | | | This will make it easier to add new hud types. Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: implement an index buffer translation cacheBrian Paul2016-09-175-6/+84
| | | | | | | | | | | | | | | Some OpenGL apps, like Cinebench R15, have many glDrawElements(GL_QUADS) calls. Since we don't directly support quads we have to convert these calls into GL_TRIANGLES which involves generating a new index buffer. This patch saves the new/translated index buffer in the hope that it can be reused for a later draw call. Cinebench R15 increases by about 20% with this change. The NobelClinician Viewer app also hits this code. Tested with full piglit run. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: try to emit fewer buffer rebind commandsBrian Paul2016-09-175-5/+60
| | | | | | | | | | | | | | | | | If a consecutive sequence of drawing commands references the same vertex/index buffers, there should be no need to rebind the surfaces for the second and subsequent drawing commands. Apps that use multiple display lists benefit from this since the vertex data for several display lists is often stored in one buffer. In the case of the legacy E&S Glaze demo, this reduces the size of our command buffers from 91KB to 44KB. One WSI Fusion trace shows a 33% reduction in command buffer sizes. Tested with full piglit run. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: reduce unmapping/remapping of the default constant bufferBrian Paul2016-09-173-6/+40
| | | | | | | | | | | | | | | Previously, every time we put shader constants into the default constant buffer we called u_upload_alloc(), which mapped the buffer, and u_upload_unmap(). We had to unmap the buffer before calling svga_buffer_handle() to get the winsys handle for the buffer. But we really only need to do that the first time we reference the const buffer. Now we try to keep the upload manager's buffer mapped until we fill it or flush the command buffer. v2: add additional comment on the buffer unmapping code in svga_context_flush(), per Charmaine. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: optimize memcpy() in svga_buffer_update_hw()Brian Paul2016-09-171-1/+8
| | | | | | | When we migrate a buffer from sw/malloc storage to a hardware buffer, don't memcpy the whole buffer, just copy the part we've written to. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: Use comparison between svga texture types to use PredCopyRegion commandNeha Bhende2016-09-171-6/+9
| | | | | | | | | | | | | | PredCopyRegion support copy between same type of textures. Instead of comparing src and dst pipe texture type, compare svga texture type which can avoid some software fallback. for example, it avoids a software blit with the Redway3D Aston demo. Tested piglit tests on VGPU9 and VGPU10 on GL/DX11Renderer, Redway3D Aston demo v2: some nit pick suggested by Charmaine. Reviewed-by: Charmaine Lee <charmainel@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: Add function svga_resource_type()Neha Bhende2016-09-172-19/+21
| | | | | | | This function returns svga texture type for corresponding pipe texture. Reviewed-by: Charmaine Lee <charmainel@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* nvc0/ir: fix subops for IMADSamuel Pitoiset2016-09-171-4/+6
| | | | | | | | | Offset was wrong, it's at bit 8, not 4. Also, uses subr instead of sub when src2 has neg. Similar to GK110 now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org
* nvc0/ir: fix comments about instructions infoSamuel Pitoiset2016-09-171-2/+3
| | | | | | | | | The comment for the commutative flags was wrong because OP_MUL is before OP_MAD. While we are at it add missing opcodes, and fix the comment about the short forms. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
* radeonsi/compute: Use the HSA abi for non-TGSI compute shaders v3Tom Stellard2016-09-162-18/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches non-TGSI compute shaders over to using the HSA ABI described here: https://github.com/RadeonOpenCompute/ROCm-Docs/blob/master/AMDGPU-ABI.md The HSA ABI provides a much cleaner interface for compute shaders and allows us to share more code in the compiler with the HSA stack. The main changes in this patch are: - We now pass the scratch buffer resource into the shader via user sgprs rather than using relocations. - Grid/Block sizes are now passed to the shader via the dispatch packet rather than at the beginning of the kernel arguments. Typically for HSA, the CP firmware will create the dispatch packet and set up the user sgprs automatically. However, in Mesa we let the driver do this work. The main reason for this is that I haven't researched how to get the CP to do all these things, and I'm not sure if it is supported for all GPUs. v2: - Add comments explaining why we are setting certain bits of the scratch resource descriptor. v3: - Use amdgcn-mesa-mesa3d triple instead of amdgcn--mesa3d. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/compute: Add some more debug printfsTom Stellard2016-09-161-0/+3
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* nir: Add a flag to lower_io to force "sample" interpolationJason Ekstrand2016-09-151-1/+1
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* nir: Report progress from nir_lower_phis_to_scalar.Kenneth Graunke2016-09-142-3/+2
| | | | | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* nir: Report progress from nir_lower_alu_to_scalar.Kenneth Graunke2016-09-142-2/+2
| | | | | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* radeonsi: reload PS inputs with direct indexing at each use (v2)Marek Olšák2016-09-143-22/+41
| | | | | | | | | | | | | | | | | | | | | The LLVM compiler can CSE interp intrinsics thanks to LLVMReadNoneAttribute. 26011 shaders in 14651 tests Totals: SGPRS: 1146340 -> 1132676 (-1.19 %) VGPRS: 727371 -> 711730 (-2.15 %) Spilled SGPRs: 2218 -> 2078 (-6.31 %) Spilled VGPRs: 369 -> 369 (0.00 %) Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread Code Size: 35841268 -> 36009732 (0.47 %) bytes LDS: 767 -> 767 (0.00 %) blocks Max Waves: 222559 -> 224779 (1.00 %) Wait states: 0 -> 0 (0.00 %) v2: don't call load_input for fragment shaders in emit_declaration Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: get rid of constant buffer preloadingMarek Olšák2016-09-141-24/+14
| | | | | | | | | | | | | | | | | 26011 shaders in 14651 tests Totals: SGPRS: 1152636 -> 1146340 (-0.55 %) VGPRS: 728198 -> 727371 (-0.11 %) Spilled SGPRs: 3776 -> 2218 (-41.26 %) Spilled VGPRs: 369 -> 369 (0.00 %) Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread Code Size: 35835152 -> 35841268 (0.02 %) bytes LDS: 767 -> 767 (0.00 %) blocks Max Waves: 222372 -> 222559 (0.08 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
* radeonsi: get rid of img/buf/sampler descriptor preloading (v2)Marek Olšák2016-09-141-132/+47
| | | | | | | | | | | | | | | | | | 26011 shaders in 14651 tests Totals: SGPRS: 1251920 -> 1152636 (-7.93 %) VGPRS: 728421 -> 728198 (-0.03 %) Spilled SGPRs: 16644 -> 3776 (-77.31 %) Spilled VGPRs: 369 -> 369 (0.00 %) Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread Code Size: 36001064 -> 35835152 (-0.46 %) bytes LDS: 767 -> 767 (0.00 %) blocks Max Waves: 222221 -> 222372 (0.07 %) Wait states: 0 -> 0 (0.00 %) v2: merge codepaths where possible Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: rename get_sampler_desc -> load_sampler_descMarek Olšák2016-09-141-11/+11
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
* radeonsi: cosmetic changes in si_shader.cMarek Olšák2016-09-141-3/+5
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
* radeonsi: load streamout buffer descriptors before use (v2)Marek Olšák2016-09-141-33/+14
| | | | | | v2: inline the code and remove the conditional that's a no-op now Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* vc4: Implement job shufflingEric Anholt2016-09-148-194/+333
| | | | | | | | | | | | | | | Track rendering to each FBO independently and flush rendering only when necessary. This lets us avoid the overhead of storing and loading the frame when an application momentarily switches to rendering to some other texture in order to continue rendering the main scene. Improves glmark -b desktop:effect=shadow:windows=4 by 27% Improves glmark -b desktop:blur-radius=5:effect=blur:passes=1:separable=true:windows=4 by 17% While I haven't tested other apps, this should help X rendering a lot, and I've heard GLBenchmark needed it too.
* vc4: Handle resolve skipping at job submit time.Eric Anholt2016-09-143-31/+37
| | | | | | This is done in vc4_flush currently, but I'm going to make the job always track the surfaces it might be rendering to instead of putting in the destinations at flush time.
* vc4: Move the render job state into a separate structure.Eric Anholt2016-09-1412-255/+287
| | | | | This is a preparation step for having multiple jobs being queued up at the same time.
* vc4: Always unref the current job surfaces at job reset time.Eric Anholt2016-09-143-36/+21
| | | | | Drops some tricky logic in vc4_flush() trying to update the pointers, and fixes a broken lack of unref for MSAA surfaces at context destroy time.
* vc4: Move job-submit skip cases to vc4_job_submit().Eric Anholt2016-09-142-12/+12
| | | | For calling job_submit() directly, I need the skipping here.
* vc4: Move bin CL trailer to job_submit() time.Eric Anholt2016-09-142-11/+14
| | | | | To implement job shuffling, I want to be able to call submit() on specific jobs, turning vc4_flush() into the context's flush-all-jobs hook.
* vc4: Simplify the DISCARD_RANGE handlingEric Anholt2016-09-141-12/+15
| | | | | | | It's really just an upgrade to attempting WHOLE_RESOURCE. Pulling the logic out caught two bugs in it: We would try to do so on cubemaps (even though we're only mapping 1 of the 6 slices), and we would break persistent coherent mappings by trying to reallocate when we shouldn't.
* vc4: Fix incorrect clearing of Z/stencil when cleared separately.Eric Anholt2016-09-143-15/+38
| | | | | | | | | | | | | | | | | The clear of Z or stencil will end up clearing the other as well, instead of masking. There's no way around this that I know of, so if we are clearing just one then we need to draw a quad. Fixes a regression in the job-shuffling code, where the clear values move to the job and don't just have the last clear's value laying around when you do glClear(DEPTH) and then glClear(STENCIL) separately (ext_framebuffer_multisample-clear 4 depth)). This causes regressions in ext_framebuffer_multisample/multisample-blit depth and ext_framebuffer_multisample/no-color depth, but these were formerly false positives due to the reference image also being black. Now the reference and test images are both being drawn, and it looks like there's an incorrect resolve of depth during blitting to an MSAA FBO.
* radeonsi: fix FP64 UBO loads with indirect uniform block indexingMarek Olšák2016-09-131-2/+1
| | | | | | | No known tests. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: clean up CP DMA emit codeMarek Olšák2016-09-131-84/+60
| | | | | | | | Unify the clear and copy paths, clean up the definitions. It looks more like a rework. It's a preparation for GDS support, which might or might not come. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: print the IB and buffer list in VM fault reportsMarek Olšák2016-09-131-1/+2
| | | | | | This is a fallout from reworking the debug flags. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: add sampler view BOs to the BO list lastMarek Olšák2016-09-131-7/+10
| | | | | | | | | If si_sampler_view_add_buffer ends up flushing, then the code in begin_new_cs would previously have added the buffer(s) for whatever was previously bound to that slot. Now it would add only the new buffer. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: export SampleMask from pixel shaders at full rateMarek Olšák2016-09-133-16/+56
| | | | | | | Heaven and Valley write gl_SampleMask and not Z. Use 16_ABGR instead of 32_ABGR if Z isn't written. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: set new r600_resource fields correctly in other places tooMarek Olšák2016-09-131-0/+11
| | | | | | | | | | | | | This was missed in: commit 0d2e43fcb1198a6e67c85feadb1ca8c360ddc284 Author: Marek Olšák <marek.olsak@amd.com> Date: Thu Aug 18 16:30:00 2016 +0200 gallium/radeon: derive buffer placement and flags only at initialization Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* ddebug: dump shader buffers and imagesMarek Olšák2016-09-131-3/+27
| | | | | | this was unimplemented Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* ddebug: fix a crash in resource_get_handleMarek Olšák2016-09-131-1/+1
| | | | | | broken recently Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeon: Don't check DCC on pipe buffersJan Vesely2016-09-131-3/+4
| | | | | | | | | Fixes segfaults in EG compute since: commit 21de3be8e62b2b093569a99550e6356ed2f106b4 radeonsi: fix texture format reinterpretation with DCC Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* android: add support for libmesa_amdgpu_addrlibMauro Rossi2016-09-132-1/+5
| | | | | | | | | | | Android porting of the following commits: f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place." 69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code" This patch fixes android building errors Reviewed-by: Dave Airlie <airlied@redhat.com>
* radeonsi: don't preload constants at the beginning of shadersMarek Olšák2016-09-121-20/+11
| | | | | | | | | | | | | | | | | | | | | | LLVM can CSE the loads, thus we can always re-load constants before each use. The decrease in SGPR spilling is huge. The best improvements are the dumbest ones. 26011 shaders in 14651 tests Totals: SGPRS: 1453346 -> 1251920 (-13.86 %) VGPRS: 742576 -> 728421 (-1.91 %) Spilled SGPRs: 52298 -> 16644 (-68.17 %) Spilled VGPRs: 397 -> 369 (-7.05 %) Scratch VGPRs: 1372 -> 1344 (-2.04 %) dwords per thread Code Size: 36136488 -> 36001064 (-0.37 %) bytes LDS: 767 -> 767 (0.00 %) blocks Max Waves: 219315 -> 222221 (1.33 %) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: remove amdgpu_cs_lookup_bufferNicolai Hähnle2016-09-121-0/+3
| | | | | | | The radeonsi driver doesn't and shouldn't care about the buffer index. Only the virtual addresses matter. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: page alignment for buffers is unnecessaryNicolai Hähnle2016-09-121-4/+1
| | | | | | In some places (e.g. shader program pointers) we require 256 bytes alignment. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* freedreno/a3xx: disable filtering for texture buffers and int texturesIlia Mirkin2016-09-111-0/+2
| | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* gm107/ir: allow indirect inputs to be loaded by frag shaderIlia Mirkin2016-09-102-5/+21
| | | | | | | | | Looks like the GM107 IPA op does not allow a separate offset when using an indirect register. Instead we must use AL2P like we do for indirect vertex operations on Kepler+. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
* gm107/ir: AL2P writes to a predicate registerIlia Mirkin2016-09-101-0/+1
| | | | | | | | | | | We have to force it to write to predicate 7 (aka PT) in order for it not to mess up another predicate. Unclear what would be returned in the predicate, perhaps an error code for out-of-bounds requests. Blob doesn't seem to check it. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Cc: mesa-stable@lists.freedesktop.org