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* winsys/amdgpu: add guard pages when R600_DEBUG=check_vm is enabledNicolai Hähnle2016-06-243-2/+8
| | | | | | This should help flush out GPU VM faults. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/u_queue: allow the execute function to differ per jobMarek Olšák2016-06-242-2/+3
| | | | | | so that independent types of jobs can use the same queue. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/u_queue: add an option to name threadsMarek Olšák2016-06-241-1/+1
| | | | | | | | for debugging v2: correct the snprintf use Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/u_queue: add an option to have multiple worker threadsMarek Olšák2016-06-243-4/+4
| | | | | | | | independent jobs don't have to be stuck on only one thread v2: use CALLOC & FREE Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/u_queue: use a ring instead of a stackMarek Olšák2016-06-241-1/+1
| | | | | | | | and allow specifying its size in util_queue_init. v2: use CALLOC & FREE Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/util: import the multithreaded job queue from amdgpu winsys (v2)Marek Olšák2016-06-154-83/+18
| | | | | | v2: rename the event to util_queue_fence Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: add micro_tile_mode to radeon_surfMarek Olšák2016-06-141-0/+15
| | | | | | for easier access Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* Android: move libdrm settings to top-level Android.common.mkRob Herring2016-06-131-1/+1
| | | | | | | | | | | | | | Fix warnings like these due to HAVE_LIBDRM being inconsistently defined: external/libdrm/include/drm/drm.h:839:30: warning: redefinition of typedef 'drm_clip_rect_t' is a C11 feature [-Wtypedef-redefinition] typedef struct drm_clip_rect drm_clip_rect_t; HAVE_LIBDRM needs to be set project wide to fix this. This change also harmlessly links libdrm with everything, but simplifies the makefiles a bit. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Emil Velikov <emil.velikov@collabora.com>
* winsys/amdgpu: enable DCC for mipmapped texturesMarek Olšák2016-06-081-6/+23
| | | | | | | | Also add dcc_fast_clear_size for clearing only the necessary subset of DCC. For no AA, it's equal to the size of the whole DCC level. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* radeonsi: add per-level dcc_enabled flagsMarek Olšák2016-06-081-3/+7
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* gallium/radeon: don't allocate DCC for non-renderable texture formatsMarek Olšák2016-06-081-0/+1
| | | | | | | | | | | R9G9B9E5 is the only uncompressed one hopefully. This fixes incorrect rendering not discovered (due to a lack of tests) until DCC mipmapping was enabled. Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* winsys/amdgpu: decay max_ib_size over timeNicolai Hähnle2016-06-011-0/+2
| | | | | | So that memory use will eventually decrease again after a temporary peak. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: implement IB chaining on the gfx ringNicolai Hähnle2016-06-012-18/+109
| | | | | | As a consequence, CE IB size never triggers a flush anymore. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: consolidate IB size management in amdgpu_ib_finalizeNicolai Hähnle2016-06-011-9/+9
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeon/winsys: introduce radeon_winsys_cs_chunkNicolai Hähnle2016-06-011-24/+29
| | | | | | | We will chain multiple chunks together and will keep pointers to the older chunks to support IB dumping. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: start with smaller IBs, growing as necessaryNicolai Hähnle2016-06-012-10/+71
| | | | | | | | | | | | | | | | | This avoids allocating giant IBs from the outset, especially for CE and DMA. Since we now limit max_dw only by the size that the buffer happens to be (which, due to the buffer cache, can be even larger than the rounded-up size we request), the new function amdgpu_ib_max_submit_dwords controls when we submit an IB. With this change, we effectively never flush prematurely due to the CE IB, after an initial warm-up phase. v2: - clean up buffer_size calculation Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add amdgpu_ib and amdgpu_cs_from_ib helper functionsNicolai Hähnle2016-06-012-7/+37
| | | | | | | The latter function allows getting the containing amdgpu_cs from any IB (including non-main ones). Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: extract IB big buffer allocation for re-useNicolai Hähnle2016-06-011-17/+29
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add IB buffer in amdgpu_get_new_ibNicolai Hähnle2016-06-011-121/+113
| | | | | | | Adding the buffer when we start using it for the IB makes the logic for chaining a bit simpler. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeon/winsys: add cs_check_spaceNicolai Hähnle2016-06-011-0/+7
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: simplify interface of amdgpu_get_new_ibNicolai Hähnle2016-06-012-14/+14
| | | | | | We'll want to have an amdgpu_cs pointer for future changes. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add amdgpu_cs_has_user_fenceNicolai Hähnle2016-06-011-4/+8
| | | | | | v2: style change Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: set flags correctly when allocating depth-stencil buffersMarek Olšák2016-06-011-2/+8
| | | | | | This mimics Vulkan. It also documents how to fix stencil texturing. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: add back multithreaded command submissionMarek Olšák2016-05-266-131/+341
| | | | | | | | | | | | | | | Ported from the initial amdgpu winsys from the private AMD branch. The thread creates the buffer list, submits IBs, and cleans up the submission context, which can also destroy buffers. 3-5% reduction in CPU overhead is expected for apps submitting a lot of IBs per frame. This is most visible with DMA IBs. v2: use a semaphore instead of a busy loop in amdgpu_ws_queue_cs add another amdgpu_cs_sync_flush call into amdgpu_bo_map Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: don't set PB_USAGE in winsysesMarek Olšák2016-05-191-2/+0
| | | | | | There is no point. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: cleanup error handling in amdgpu_ctx_createNicolai Hähnle2016-05-171-9/+14
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: avoid ioctl call when fence_wait is called without timeoutNicolai Hähnle2016-05-171-3/+10
| | | | | | When user fences are used, we don't need the kernel for polling. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* Treewide: Remove Elements() macroJan Vesely2016-05-171-4/+4
| | | | | Signed-off-by: Jan Vesely <jano.vesely@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* gallium/radeon: add a heuristic for better (S)DMA performanceMarek Olšák2016-05-101-0/+8
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: align alignments for better buffer reuseMarek Olšák2016-05-101-0/+1
| | | | | | | | It's for the buffer cache. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: use gart_page_size instead of hardcoded 4096Marek Olšák2016-05-101-3/+4
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: move gart_page_size to struct radeon_winsysMarek Olšák2016-05-103-10/+9
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: remove tile_mode_array_valid flagsMarek Olšák2016-05-021-2/+0
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: pass PIPE_CONFIG to addrlib on texture importMarek Olšák2016-05-022-0/+2
| | | | | | | This hasn't been needed, but I think we should set it. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: read NUM_BANKS from buffer metadataMarek Olšák2016-05-022-21/+2
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: add radeon_surf::macro_tile_indexMarek Olšák2016-05-021-0/+3
| | | | | | | for indexing cik_macrotile_mode_array Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: count buffer size only onceMarek Olšák2016-05-021-2/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: loosen up requirements for how much memory IBs can useMarek Olšák2016-05-021-4/+10
| | | | | | | ported from winsys/radeon. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: drop support for LINEAR_GENERAL layoutMarek Olšák2016-04-281-6/+0
| | | | | | | Unused. All texture imports use LINEAR_ALIGNED regardless of what the DDX does. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* winsys/radeon: remove use_reusable_pool parameter from buffer_createNicolai Hähnle2016-04-272-10/+6
| | | | | | All callers set this parameter to true. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium: Remove every double semi-colonJakob Sinclair2016-04-262-2/+2
| | | | | | Signed-off-by: Jakob Sinclair <sinclair.jakob@openmailbox.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* winsys/amdgpu: Silence possibly uninitialized variable warning.Bas Nieuwenhuizen2016-04-211-0/+3
| | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: fix preamble IB sizeThomas Hindoe Paaboel Andersen2016-04-211-0/+1
| | | | | | | | | The missing break caused the IB size to be overwritten with the size of IB_CONST. This was introduced in: 7201230582e060aa2eb79c825d3188b437ef7bb8 Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: Enlarge const IB size.Bas Nieuwenhuizen2016-04-191-8/+20
| | | | | | | | | | | | Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. v2: Add preamble IB. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: Add support for const IB.Marek Olšák2016-04-192-5/+94
| | | | | | v2: Use the correct IB to update request (Bas Nieuwenhuizen) v3: Add preamble IB. (Bas Nieuwenhuizen) Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: split IB data into a new structure in preparation for CEMarek Olšák2016-04-194-47/+48
| | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* gallium/radeon: move ring_type into winsysesMarek Olšák2016-04-192-4/+5
| | | | | | Not used by drivers. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* gallium/radeon: relax requirements on VRAM placements on APUsMarek Olšák2016-04-121-0/+4
| | | | | | | This makes Tonga with vramlimit=128 2x faster in Heaven. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* winsys/amdgpu: remove hack for low VRAM configurationMarek Olšák2016-04-121-10/+0
| | | | | | | A better solution will be used. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* winsys/amdgpu: add support for 64-bit buffer sizesMarek Olšák2016-04-122-15/+16
| | | | | | v2: fail in radeon_winsys_bo_create if size > 32 bits Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
generated by cgit v1.1 at 2025-08-17 22:31:41 +0000