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* radeonsi: implement TC-compatible HTILEMarek Olšák2016-10-131-4/+53
| | | | | | | | | | | | | | | | | | | | | so that decompress blits aren't needed and depth texturing needs less memory bandwidth. Z16 and Z24 are promoted to Z32_FLOAT by the driver, because TC-compatible HTILE only supports Z32_FLOAT. This doubles memory footprint for Z16. The format promotion is not visible to state trackers. This is part of TC-compatible renderbuffer compression, which has 3 parts: DCC, HTILE, FMASK. Only TC-compatible FMASK compression is missing now. I don't see a measurable increase in performance though. (I tested Talos Principle and DiRT: Showdown, the latter is improved by 0.5%, which is almost noise, and it originally used layered Z16, so at least we know that Z16 promoted to Z32F isn't slower now) Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: fix infinite loop w/ RADEON_NOOP=1 caused by unsubmitted fencesMarek Olšák2016-10-121-2/+5
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon/winsyses: set reasonable max_alloc_sizeMarek Olšák2016-10-051-2/+2
| | | | | | | | | | which is returned for GL_MAX_TEXTURE_BUFFER_SIZE. It doesn't have any other use at the moment. Bigger allocations are not rejected. This fixes GL45-CTS.texture_buffer.texture_buffer_max_size on Bonaire. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon/winsyses: add radeon_winsys::min_alloc_sizeNicolai Hähnle2016-09-291-0/+2
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon/winsyses: reduce the number of pb_cache bucketsNicolai Hähnle2016-09-271-4/+2
| | | | | | | Small buffers are now handled via the slabs code, so separate buckets in pb_cache have become redundant. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: enable buffer allocation from slabsNicolai Hähnle2016-09-274-0/+201
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add fence and buffer list logic for slab allocated buffersNicolai Hähnle2016-09-272-45/+149
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add slab entry structures to amdgpu_winsys_boNicolai Hähnle2016-09-273-36/+74
| | | | | | Already adjust amdgpu_bo_map/unmap accordingly. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: do not synchronize unsynchronized buffersNicolai Hähnle2016-09-273-45/+118
| | | | | | | | | | | | | | | | | | | | When a buffer is added to a CS without the SYNCHRONIZED usage flag, we now no longer add a dependency on the buffer's fence(s). However, we still need to add a fence to the buffer during flush, so that cache reclaim works correctly (and in the hypothetical case that the buffer is later added to a CS _with_ the SYNCHRONIZED flag). It is now possible that the submissions refererring to a buffer are no longer linearly ordered, and so we may have to keep multiple fences around. We keep the fences in a FIFO. It should usually stay quite short (# of contexts * 2, for gfx + dma rings). While we're at it, extract amdgpu_add_fence_dependency for a single buffer, which will make adding the distinction between real buffer and slab cases easier. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: add RADEON_FLAG_HANDLENicolai Hähnle2016-09-271-0/+3
| | | | | | | | | | | | | | | | When passed to winsys->buffer_create, this flag will indicate that we require a buffer that maps 1:1 with a kernel buffer handle. This is currently set for all textures, since textures can potentially be exported to other processes. This is not a huge loss, since the main purpose of this patch series is to deal with applications that allocate many small buffers. A hypothetical application with tons of tiny textures might still benefit from not setting this flag, but that's not a use case I'm worried about just now. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: don't assume GTT if the VRAM flag isn't setMarek Olšák2016-09-131-3/+3
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* android: add support for libmesa_amdgpu_addrlibMauro Rossi2016-09-131-4/+5
| | | | | | | | | | | Android porting of the following commits: f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place." 69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code" This patch fixes android building errors Reviewed-by: Dave Airlie <airlied@redhat.com>
* winsys/amdgpu: remove amdgpu_cs_lookup_bufferNicolai Hähnle2016-09-121-9/+0
| | | | | | | The radeonsi driver doesn't and shouldn't care about the buffer index. Only the virtual addresses matter. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: remove unused field domains from amdgpu_cs_bufferNicolai Hähnle2016-09-122-37/+17
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: remove initial buffer list allocationNicolai Hähnle2016-09-121-20/+0
| | | | | | It's really not necessary. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: extract adding a new buffer list entry into its own functionNicolai Hähnle2016-09-121-43/+70
| | | | | | | While at it, try to be a little more robust in the face of memory allocation failure. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: use only one fence per BONicolai Hähnle2016-09-123-68/+56
| | | | | | | | | | | The fence that is added to the BO during flush is guaranteed to be signaled after all the fences that were in the fences array of the BO before the flush, because those fences are added as dependencies for the submission (and all this happens atomically under the bo_fence_lock). Therefore, keeping only the last fence around is sufficient. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add do_winsys_deinit functionNicolai Hähnle2016-09-121-2/+7
| | | | | | | The idea is to have matching init/deinit functions so that deinit can be re-used for cleanup in the error path of amdgpu_winsys_create. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: clean up error paths in amdgpu_winsys_createNicolai Hähnle2016-09-121-7/+5
| | | | | | | No need to call pb_cache_deinit, because the cache hasn't been initialized at that point. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon/winsyses: remove #includes of pb_bufmgr.hNicolai Hähnle2016-09-121-1/+0
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: replace OUT_CS with radeon_emitMarek Olšák2016-09-091-14/+12
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon/winsyses: fix counting mapped memoryMarek Olšák2016-09-071-0/+8
| | | | | | Not all buffers are unmapped explicitly. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-0623-21944/+3
| | | | | Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move sid.h/r600d_common.h to a common place.Dave Airlie2016-09-061-1/+1
| | | | | | | | | | Step one to merging radv would be to move some files around. This only adds the include path to r600/radeonsi, because later we want to avoid having to add it to the generic target paths. Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: disable IB chaining on SIMarek Olšák2016-08-261-5/+6
| | | | | Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* winsys/amdgpu: finish up SI addrlib integrationMarek Olšák2016-08-261-5/+25
| | | | Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
* winsys/amdgpu: initial SI supportRonie Salgado2016-08-263-6/+46
| | | | | Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
* gallium/radeon: add a driver query for AMDGPU_INFO_NUM_EVICTIONSMarek Olšák2016-08-261-0/+7
| | | | | | If the kernel driver doesn't support it, it returns 0. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* winsys/amdgpu: track the amount of mapped memoryMarek Olšák2016-08-104-1/+24
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: don't try to unmap userptr buffersMarek Olšák2016-08-101-0/+3
| | | | | | no app calls this AFAIK Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: query ME/PFP/CE firmware versionsNicolai Hähnle2016-08-081-0/+22
| | | | | | | The radeon kernel module doesn't have the firmware query interface, so the corresponding values will remain 0. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: implement cs_get_next_fenceMarek Olšák2016-08-062-4/+35
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: move radeon_winsys::cs_memory_below_limit to driversMarek Olšák2016-08-061-18/+0
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: inline radeon_winsys::query_memory_usageMarek Olšák2016-08-061-6/+0
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon/winsyses: expose per-IB used_vram and used_gart to driversMarek Olšák2016-08-062-11/+8
| | | | | | The following patches will use this. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon/winsyses: print CS submission error numberMarek Olšák2016-08-061-1/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: use pb_cache buckets for fewer pb_cache missesMarek Olšák2016-07-191-6/+21
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/pb_cache: divide the cache into buckets for reducing cache missesMarek Olšák2016-07-191-2/+2
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/u_queue: add optional cleanup callbackRob Clark2016-07-161-1/+1
| | | | | | | | | | | | Adds a second optional cleanup callback, called after the fence is signaled. This is needed if, for example, the queue has the last reference to the object that embeds the util_queue_fence. In this case we cannot drop the ref in the main callback, since that would result in the fence being destroyed before it is signaled. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: return an error on IB submission failuresMarek Olšák2016-07-142-1/+9
| | | | Reviewed-by: Christian König <christian.koenig@amd.com>
* gallium/radeon: add a return value to cs_flushMarek Olšák2016-07-141-3/+4
| | | | | | Required by our UVD code. Reviewed-by: Christian König <christian.koenig@amd.com>
* radeonsi: just save buffer sizes instead of buffers while recording IBsMarek Olšák2016-07-131-1/+1
| | | | | | whole buffer objects are not needed Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: avoid flushed depth when possibleNicolai Hähnle2016-07-061-3/+8
| | | | | | | If a depth/stencil texture has no mipmaps, we can always get a layout that is compatible with DB and TC. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: add depth/stencil_adjusted output to surface computationNicolai Hähnle2016-07-061-0/+4
| | | | | | | | | | | This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga, though it's basically a function of the memory configuration so could affect other parts as well. Fixes piglit "unaligned-blit * stencil downsample" and various "fbo-depth-array *stencil*" tests. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon/winsyses: remove unused stencil_offsetNicolai Hähnle2016-07-061-2/+0
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: add and use radeon_info::max_alloc_size (v2)Marek Olšák2016-07-051-0/+2
| | | | | | | | | | v2: - squashed the patches - use INT_MAX - clamp max_const_buffer_size - check the DRM version in radeon Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Vedran Miletić <vedran@miletic.net>
* radeon uvd add uvd fw version for amdgpusonjiang2016-06-291-1/+10
| | | | | | | Signed-off-by: sonjiang <sonny.jiang@amd.com> Cc: "12.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* radeonsi: always calculate DCC info even if it's not used immediatelyMarek Olšák2016-06-291-1/+0
| | | | | | for a later use Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> falseMarek Olšák2016-06-254-37/+38
| | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Vedran Miletić <vedran@miletic.net> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: add guard pages when R600_DEBUG=check_vm is enabledNicolai Hähnle2016-06-243-2/+8
| | | | | | This should help flush out GPU VM faults. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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