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* radeonsi: add support for Polaris (v2)Sonny Jiang2016-03-241-0/+8
| | | | | | | | | v2: Polaris chips should be defined after Stoney Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> (v1) Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1) Signed-off-by: Leo Liu <leo.liu@amd.com> (v2 diff) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2 diff)
* winsys/amdgpu: addrlib - add Polaris support (v2)Sonny Jiang2016-03-243-2/+18
| | | | | | | | v2: fix indentation as noted by Michel Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: remove old CS tracingMarek Olšák2016-03-201-4/+2
| | | | | | | | | | | | | | Cons: - it was only integrated in r600g - it doesn't work with GPUVM - it records buffer contents at the end of IBs instead of at the beginning, so the replay isn't exact - it lacks an IB parser and user-friendliness A better solution is apitrace in combination with gallium/ddebug, which has a complete IB parser and can pinpoint hanging CP packets. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeon/winsys: add layer support for BO exportChristian König2016-03-171-0/+2
| | | | | | | Add layer support to export individual array layers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeon/winsys: add offset support for BO import/exportChristian König2016-03-171-3/+6
| | | | | | | Add offset support to handle NV12 offsets as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/winsys/drm: add offset to struct winsys_handleChristian König2016-03-171-0/+1
| | | | | | | We are going to need this for EGL_EXT_image_dma_buf_import. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu/addrlib: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-2/+2
| | | | | Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: get PCI infoMarek Olšák2016-03-091-2/+15
| | | | | | | | | This will be queried by the OpenCL stack using an interop call. I have tested that the values match lspci. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: allow drivers to set/get opaque metadataMarek Olšák2016-03-091-0/+5
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: rename winsys buffer_get/set_tiling to buffer_get/set_metadataMarek Olšák2016-03-091-6/+6
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: remove rcs parameter from radeon_winsys::buffer_set_tilingMarek Olšák2016-03-091-1/+0
| | | | | | | | This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags in IBs. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: use a structure for passing tiling flags from/to winsysMarek Olšák2016-03-091-38/+21
| | | | | | | and call it radeon_bo_metadata Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: enlarge buffer_indices_hashlistBas Nieuwenhuizen2016-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | Enlarge the buffer hashlist to prevent large numbers of misses due to adding more buffers than can be cached in the hashlist. The game I tested had CS's with up to 1500 buffers and the overhead of amdgpu_lookup_buffer for various sizes was: 4096 1.97% (new value) 2048 4.37% 1024 6.92% 512 9.47% (old value) (percentage of CPU usage in render thread as determined by perf) The time spent in amdgpu_add_buffer self is ~4.2% in all cases and for 4096 the time needed to clear the hashlist is still < 0.10%, so I am not expecting significant regressions. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: drop support for LLVM 3.5Marek Olšák2016-02-111-3/+2
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> v2: adjust the comment in the amdgpu winsys
* gallium/radeon: remove radeon_info::r600_tiling_configMarek Olšák2016-02-051-15/+0
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsysMarek Olšák2016-02-051-0/+1
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: add an assertion to cik_get_num_tile_pipes (v2)Marek Olšák2016-02-051-1/+4
| | | | | | | v2: print an error to stderr Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: remove an r600-only settingMarek Olšák2016-02-051-1/+0
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: rename & reorder members of radeon_infoMarek Olšák2016-02-051-8/+8
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*Michel Dänzer2016-01-291-10/+9
| | | | | | | | | | | In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created in VRAM if they get evicted to GTT. In general there's no need to restrict any of the flags to any particular domains. Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESSMichel Dänzer2016-01-291-0/+2
| | | | | | | | | | | | | | | | Failing to do this was resulting in the kernel driver unnecessarily leaving open the possibility of CPU access to tiled BOs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862 (This change shouldn't be backported to stable branches, because released versions of xf86-video-amdgpu unnecessarily try to map the front buffer) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* winsys/amdgpu: optionally use buffer lists with all allocated buffersMarek Olšák2016-01-235-3/+61
| | | | | | | Set RADEON_ALL_BOS=1 to use it. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: compute num_good_compute_units correctlyMarek Olšák2016-01-221-10/+5
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: rename max_compute_units -> num_good_compute_unitsMarek Olšák2016-01-221-3/+3
| | | | | | radeon sets this correctly, but not amdgpu Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: do not reallocate user memory buffersNicolai Hähnle2016-01-141-0/+6
| | | | | | | | | The whole point of AMD_pinned_memory is that applications don't have to map buffers via OpenGL - but they're still allowed to, so make sure we don't break the link between buffer object and user memory unless explicitly instructed to. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: clear the buffer cache on mmap failure and try againMarek Olšák2015-12-111-0/+5
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: clear the buffer cache on allocation failure and try againMarek Olšák2015-12-111-2/+7
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: remove radeon_winsys_cs_handleMarek Olšák2015-12-112-20/+11
| | | | | | | | "radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf". Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: don't use the "rws" abbreviation for amdgpu_winsysMarek Olšák2015-12-114-20/+20
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: use pb_cache instead of pb_cache_managerMarek Olšák2015-12-114-173/+78
| | | | | | | | This is a prerequisite for the removal of radeon_winsys_cs_handle. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: addrlib - port a Fiji bug fixSonny Jiang2015-12-072-1/+46
| | | | | | | | | | Fiji: Fixed tiled resource failures Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> v2: fix a compile failure (typo) - Marek
* winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatibleSonny Jiang2015-12-072-2/+5
| | | | | | Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: addrlib - port fix error for workaround for 1D tilingSonny Jiang2015-12-071-1/+1
| | | | | | Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: Make use of ARRAY_SIZE macroEdward O'Callaghan2015-12-061-4/+2
| | | | | Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: remove the dcc_enable surface flagMarek Olšák2015-10-271-7/+6
| | | | | | dcc_size is sufficient and doesn't need a further comment in my opinion. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: Allocate buffers for DCC.Bas Nieuwenhuizen2015-10-241-5/+42
| | | | | | | | | | | As the alignment requirements can be 32 KiB or more, also adding an aligned buffer creation function. DCC is disabled for textures that can be shared as sharing the DCC buffers has not been implemented yet. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: add support for Stoney asics (v3)Samuel Li2015-10-232-3/+11
| | | | | | | | | | | v2 (agd): rebase on mesa master, split pci ids to separate commit v3 (agd): use carrizo for llvm processor name for llvm 3.7 and older Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Samuel Li <samuel.li@amd.com> Cc: mesa-stable@lists.freedesktop.org
* winsys/amdgpu: add winsys function cs_get_buffer_listMarek Olšák2015-10-032-0/+20
| | | | | | For debugging. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: stop using "reloc" in a few placesMarek Olšák2015-10-032-29/+29
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: tell the winsys the exact resource binding typesMarek Olšák2015-10-031-4/+4
| | | | | | | Use the priority flags and expand them. This information will be used for debugging. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: calculate the maximum number of compute unitsMarek Olšák2015-09-101-2/+13
| | | | | | | Required for register spilling. Cc: 11.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* winsys/amdgpu: remove exported buffers from the cacheMarek Olšák2015-09-031-0/+3
| | | | | Cc: 11.0 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* winsys/amdgpu: remove IB padding for SIMarek Olšák2015-09-011-17/+5
| | | | | | | SI is unsupported by amdgpu Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* winsys/amdgpu: use small IBs for better performance on VIMarek Olšák2015-09-011-7/+9
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* gallium/radeon: read_registers should return bool meaning success or failureMarek Olšák2015-08-261-3/+3
| | | | | Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* winsys/amdgpu: automake: remove missing headersEmil Velikov2015-08-221-2/+0
| | | | | | | The files are not referenced in any other place in whole of mesa. They are likely remnants of the early development stage. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
* android: fix cflags and includes for amdgpu winsysMauro Rossi2015-08-221-0/+10
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
* winsys/amdgpu: fix the type of memory usage countersMarek Olšák2015-08-191-2/+2
| | | | | | | | | If the 32-bit types overflowed, the driver could submit an IB that uses much more memory than is available. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeon/vce: disable VCE dual instance for harvest partLeo Liu2015-08-141-0/+1
| | | | | | Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* radeonsi: add support for FIJI (v4)Alex Deucher2015-08-141-0/+4
| | | | | | | | | | | | v2: incorporate comments from Marek v3: add missing fiji case in winsys init use tonga raster config (double check this) v4: rebase on harvest patch Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v3) Reviewed-by: Christian König <christian.koenig@amd.com> (v3) Reviewed-by: David Zhang <david1.zhang@amd.com> (v3) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.1 at 2025-08-18 08:27:43 +0000