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* winsys/amdgpu: add amdgpu_ib and amdgpu_cs_from_ib helper functionsNicolai Hähnle2016-06-012-7/+37
| | | | | | | The latter function allows getting the containing amdgpu_cs from any IB (including non-main ones). Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: extract IB big buffer allocation for re-useNicolai Hähnle2016-06-011-17/+29
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add IB buffer in amdgpu_get_new_ibNicolai Hähnle2016-06-011-121/+113
| | | | | | | Adding the buffer when we start using it for the IB makes the logic for chaining a bit simpler. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeon/winsys: add cs_check_spaceNicolai Hähnle2016-06-012-0/+14
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: simplify interface of amdgpu_get_new_ibNicolai Hähnle2016-06-012-14/+14
| | | | | | We'll want to have an amdgpu_cs pointer for future changes. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: add amdgpu_cs_has_user_fenceNicolai Hähnle2016-06-011-4/+8
| | | | | | v2: style change Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: set flags correctly when allocating depth-stencil buffersMarek Olšák2016-06-011-2/+8
| | | | | | This mimics Vulkan. It also documents how to fix stencil texturing. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium: push offset down to driverStanimir Varbanov2016-05-306-0/+38
| | | | | | | | | | | | | Push offset down to drivers when importing dmabuf. This is needed to more fully support EGL_EXT_image_dma_buf_import when a non-zero offset is specified. Tesing has been done for freedreno, and compile tested following gallium drivers: nouveau,svga,virgl,r600,r300,radeonsi,swrast,i915,ilo Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
* winsys/amdgpu: add back multithreaded command submissionMarek Olšák2016-05-266-131/+341
| | | | | | | | | | | | | | | Ported from the initial amdgpu winsys from the private AMD branch. The thread creates the buffer list, submits IBs, and cleans up the submission context, which can also destroy buffers. 3-5% reduction in CPU overhead is expected for apps submitting a lot of IBs per frame. This is most visible with DMA IBs. v2: use a semaphore instead of a busy loop in amdgpu_ws_queue_cs add another amdgpu_cs_sync_flush call into amdgpu_bo_map Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: don't set PB_USAGE in winsysesMarek Olšák2016-05-192-4/+0
| | | | | | There is no point. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: cleanup error handling in amdgpu_ctx_createNicolai Hähnle2016-05-171-9/+14
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: avoid ioctl call when fence_wait is called without timeoutNicolai Hähnle2016-05-171-3/+10
| | | | | | When user fences are used, we don't need the kernel for polling. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* Treewide: Remove Elements() macroJan Vesely2016-05-172-8/+8
| | | | | Signed-off-by: Jan Vesely <jano.vesely@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* gallium/radeon: add a heuristic for better (S)DMA performanceMarek Olšák2016-05-102-0/+16
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: align alignments for better buffer reuseMarek Olšák2016-05-102-0/+2
| | | | | | | | It's for the buffer cache. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: use gart_page_size instead of hardcoded 4096Marek Olšák2016-05-102-4/+5
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/radeon: use gart_page_size instead of private size_alignMarek Olšák2016-05-103-14/+11
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: move gart_page_size to struct radeon_winsysMarek Olšák2016-05-103-10/+9
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: remove stencil_tile_split from metadataMarek Olšák2016-05-021-4/+0
| | | | | | | | this is a leftover from the days when depth-stencil buffers were allocated by the DDX Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: remove tile_mode_array_valid flagsMarek Olšák2016-05-022-4/+0
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: pass PIPE_CONFIG to addrlib on texture importMarek Olšák2016-05-022-0/+2
| | | | | | | This hasn't been needed, but I think we should set it. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: read NUM_BANKS from buffer metadataMarek Olšák2016-05-022-21/+2
| | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: add radeon_surf::macro_tile_indexMarek Olšák2016-05-022-0/+19
| | | | | | | for indexing cik_macrotile_mode_array Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: drop support for kernels lacking tile mode array queriesMarek Olšák2016-05-021-6/+14
| | | | | | | | | | This will allow us to simplify a lot of code around tiling. Kernel 3.10 is required for SI support. Kernel 3.13 is required for CIK support. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: count buffer size only onceMarek Olšák2016-05-021-2/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: count buffer size only onceMarek Olšák2016-05-021-2/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: loosen up requirements for how much memory IBs can useMarek Olšák2016-05-021-4/+10
| | | | | | | ported from winsys/radeon. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/sw/xlib: use correct free function for xlib_dt->dataJose Fonseca2016-05-011-1/+1
| | | | | | | Analogous to previous commit. Cc: "11.2 11.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
* winsys/sw/dri: use correct free function for dri_sw_dt->dataWuZhen2016-05-011-1/+1
| | | | | | | | | | | align_malloc() is used to allocate dri_sw_dt->data, thus we should not be using FREE() but align_free(). Cc: "11.2 11.1" <mesa-stable@lists.freedesktop.org> Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw> [Emil Velikov: tweak commit summary/shortlog] Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
* winsys/radeon: enlarge buffer_indices_hashlistBas Nieuwenhuizen2016-04-281-1/+1
| | | | | | | | | Enlarge the buffer hashlist to prevent large numbers of misses due to adding more buffers than can be cached in the hashlist. Ported from winsys/amdgpu: 6373845d985d65c00f7c62b793e67ae5106eabff Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* gallium/radeon: drop support for LINEAR_GENERAL layoutMarek Olšák2016-04-281-6/+0
| | | | | | | Unused. All texture imports use LINEAR_ALIGNED regardless of what the DDX does. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* winsys/radeon: remove use_reusable_pool parameter from buffer_createNicolai Hähnle2016-04-274-18/+11
| | | | | | All callers set this parameter to true. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium: Remove every double semi-colonJakob Sinclair2016-04-262-2/+2
| | | | | | Signed-off-by: Jakob Sinclair <sinclair.jakob@openmailbox.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* scons: Whenever possible decide what to do based on platform and not compiler.Jose Fonseca2016-04-261-6/+4
| | | | | | | | | | Because compilers like GCC and Clang are effectively available everywhere so their presence/absence is seldom conclusive. Furthermore, all compilers we use now have stdint.h. Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* winsys/amdgpu: Silence possibly uninitialized variable warning.Bas Nieuwenhuizen2016-04-211-0/+3
| | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: fix preamble IB sizeThomas Hindoe Paaboel Andersen2016-04-211-0/+1
| | | | | | | | | The missing break caused the IB size to be overwritten with the size of IB_CONST. This was introduced in: 7201230582e060aa2eb79c825d3188b437ef7bb8 Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: Enlarge const IB size.Bas Nieuwenhuizen2016-04-191-8/+20
| | | | | | | | | | | | Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. v2: Add preamble IB. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: Add support for const IB.Marek Olšák2016-04-192-5/+94
| | | | | | v2: Use the correct IB to update request (Bas Nieuwenhuizen) v3: Add preamble IB. (Bas Nieuwenhuizen) Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: split IB data into a new structure in preparation for CEMarek Olšák2016-04-194-47/+48
| | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* gallium/radeon: move ring_type into winsysesMarek Olšák2016-04-194-9/+11
| | | | | | Not used by drivers. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* gallium/radeon: relax requirements on VRAM placements on APUsMarek Olšák2016-04-122-0/+28
| | | | | | | This makes Tonga with vramlimit=128 2x faster in Heaven. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* winsys/amdgpu: remove hack for low VRAM configurationMarek Olšák2016-04-121-10/+0
| | | | | | | A better solution will be used. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* winsys/radeon: fix printing allocation failuresMarek Olšák2016-04-121-4/+4
| | | | | | print as unsigned instead of signed Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* winsys/amdgpu: add support for 64-bit buffer sizesMarek Olšák2016-04-123-17/+22
| | | | | | v2: fail in radeon_winsys_bo_create if size > 32 bits Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* pb_buffer: switch pb_buffer::size to 64 bitsMarek Olšák2016-04-123-6/+8
| | | | | | being able to allocate more than 4 GB may be useful Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: add support for Polaris (v2)Sonny Jiang2016-03-241-0/+8
| | | | | | | | | v2: Polaris chips should be defined after Stoney Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> (v1) Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1) Signed-off-by: Leo Liu <leo.liu@amd.com> (v2 diff) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2 diff)
* winsys/amdgpu: addrlib - add Polaris support (v2)Sonny Jiang2016-03-243-2/+18
| | | | | | | | v2: fix indentation as noted by Michel Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: remove old CS tracingMarek Olšák2016-03-207-392/+4
| | | | | | | | | | | | | | Cons: - it was only integrated in r600g - it doesn't work with GPUVM - it records buffer contents at the end of IBs instead of at the beginning, so the replay isn't exact - it lacks an IB parser and user-friendliness A better solution is apitrace in combination with gallium/ddebug, which has a complete IB parser and can pinpoint hanging CP packets. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeon/winsys: add layer support for BO exportChristian König2016-03-172-0/+5
| | | | | | | Add layer support to export individual array layers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeon/winsys: add offset support for BO import/exportChristian König2016-03-172-6/+12
| | | | | | | Add offset support to handle NV12 offsets as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
generated by cgit v1.1 at 2025-08-18 10:53:35 +0000