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* radeonsi: remove an unused ctx parameter in si_shader_destroyMarek Olšák2015-10-174-6/+6
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: print export_prim_id from the shader keyMarek Olšák2015-10-171-0/+2
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: disable NaNs for LS and HSMarek Olšák2015-10-171-2/+4
| | | | | | | They're disabled for all other shaders except compute, but I forgot to do this for tess stages. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: clean up si_llvm_init_export_argsMarek Olšák2015-10-171-42/+35
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* tgsi: move pipe_shader_from_tgsi_processor function to utilMarek Olšák2015-10-172-24/+24
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/hud: fix possible NULL pointer dereferenceMarek Olšák2015-10-171-0/+3
| | | | Trivial.
* scons: fix MSVC, MinGW buildBrian Paul2015-10-174-2/+21
| | | | Duplicate the glsl_types_hack.cpp work-around from the libgl-xlib target.
* nvc0: add support for performance monitoring metrics on FermiSamuel Pitoiset2015-10-174-3/+500
| | | | | | | | | As explained in the CUDA toolkit documentation, "a metric is a characteristic of an application that is calculated from one or more event values." Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* glsl: (mostly) remove libglsl_utilRob Clark2015-10-164-5/+1
| | | | | | | | | | | Now that NIR does not depend on glsl, we can (mostly[*]) get rid of the libglsl_util hack. [*] glsl_compiler is the one remaining user of libglsl_util Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Rob Clark <robclark@freedesktop.org>
* nir: remove dependency on glslRob Clark2015-10-162-0/+6
| | | | | | | | | | | | | | | Move glsl_types into NIR, now that the dependency on glsl_symbol_table has been split out. Possibly makes sense to rename things at this point, but if we do that I'd like to keep it split out into a separate patch to make git history easier to follow (IMHO). v2: fix android build v3: I f***ing hate scons.. but at least it builds Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Rob Clark <robclark@freedesktop.org>
* tgsi: initialize ctx.file in tgsi_dump_instruction()Brian Paul2015-10-161-0/+1
| | | | | Fixes segfault because of uninitialized file pointer. Trivial.
* nvc0: add a note about MP counters on GF100/GF110Samuel Pitoiset2015-10-161-0/+5
| | | | | | | | | MP counters on GF100/GF110 (compute capability 2.0) are buggy because there is a context-switch problem that we need to fix. Results might be wrong sometimes, be careful! Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: add MP counters variants for GF100/GF110Samuel Pitoiset2015-10-162-77/+483
| | | | | | | | | GF100 and GF110 chipsets are compute capability 2.0, while the other Fermi chipsets are compute capability 2.1. That's why, some MP counters are different between these chipsets and we need to handle variants. Signed-off-by: Samuel Pitoiet <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: move SW/HW queries info to their respective filesSamuel Pitoiset2015-10-167-178/+228
| | | | | | | This will help for handling HW SM queries variants on Fermi. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: enable compute support by default on FermiSamuel Pitoiset2015-10-162-8/+2
| | | | | | | | | | Compute support was not enabled by default because weird effects on 3D state happened, but I can't reproduce them anymore. This also enables MP performance counters by default on Fermi. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: allow only one active query for the MP counters groupSamuel Pitoiset2015-10-161-11/+9
| | | | | | | | | | | | | | Because we can't expose the number of hardware counters needed for each different query, we don't want to allow more than one active query simultaneously to avoid failure when the maximum number of counters is reached. Note that these groups of GPU counters are currently only used by AMD_performance_monitor. Like for Kepler, this limits the maximum number of active queries to 1 on Fermi. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: read MP counters of all GPCs on FermiSamuel Pitoiset2015-10-161-1/+1
| | | | | | | | | | | | When a card has more than one GPC, the grid used by the compute kernel which reads MP performance counters seems to be too small. The consequence is that the kernel is not launched on all TPCs. Increasing the grid size using the number of GPCs now launches enough blocks and we can read MP performance counters of all TPCs. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: store the number of GPCs to nvc0_screenSamuel Pitoiset2015-10-162-0/+2
| | | | | | | | | | | | NOUVEAU_GETPARAM_GRAPH_UNITS param returns the number of GPCs, the total number of TPCs and the number of ROP units. Note that when the DRM version is too old the default number of GPCs is fixed to 4. This will be used to launch the compute kernel which is used to read MP performance counters over all GPCs. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: fix unaligned mem access when reading MP counters on FermiSamuel Pitoiset2015-10-161-6/+12
| | | | | | | | | | | | | Memory access have to be aligned to 128-bits. Note that this doesn't happen when the card only has TPC. This patch fixes the following dmesg fail: gr: GPC0/TPC1/MP trap: global 00000004 [MULTIPLE_WARP_ERRORS] warp 000f [UNALIGNED_MEM_ACCESS] Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: fix monitoring multiple MP counters queries on FermiSamuel Pitoiset2015-10-161-76/+87
| | | | | | | | | For strange reasons, the signal id depends on the slot selected on Fermi but not on Kepler. Fortunately, the signal ids are just offseted by the slot id! Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: fix queries which use multiple MP counters on FermiSamuel Pitoiset2015-10-161-47/+81
| | | | | | | | | | | | | | Queries which use more than one MP counters was misconfigured and computing the final result was also wrong because sources need to be configured on different hardware counters instead. According to the blob, computing the result is now as follows: FOR i..n val += ctr[i] * pow(2, i) Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: allow to use 8 MP counters on FermiSamuel Pitoiset2015-10-162-19/+13
| | | | | | | | On Fermi, we have one domain of 8 MP counters while we have two domains of 4 MP counters on Kepler. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: fix sequence field init for MP counters on FermiSamuel Pitoiset2015-10-161-2/+4
| | | | | | | | Sequence fields are located at MP[i] + 0x20 in the buffer object. This is used to check if result is available for MP[i]. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: correctly enable the MP counters' multiplexer on FermiSamuel Pitoiset2015-10-161-4/+1
| | | | | | | | | Writing 0x408000 to 0x419e00 (like on Kepler) has no effect on Fermi because we only have one domain of 8 counters. Instead, we have to write 0x80000000. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: rip off the kepler MP-enabling logic from the Fermi codepathSamuel Pitoiset2015-10-161-7/+1
| | | | | | | | Writing 0x1fcb to 0x419eac is definitely not related to MP counters and has no effect on Fermi (although this enables MP counters on Kepler). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: split out begin_query() hook used by MP countersSamuel Pitoiset2015-10-161-24/+84
| | | | | | | | | The way we configure MP performance counters is going to pretty different between Fermi and Kepler. Having two separate functions is much better. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0: remove useless call to query_get_cfg() in nvc0_hw_sm_query_end()Samuel Pitoiset2015-10-161-3/+1
| | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* svga: only count hardware buffer mappings for HUDBrian Paul2015-10-162-1/+3
| | | | | | Don't count client memory buffer mappings since they're basically free. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: add new GALLIUM_HUD queriesNeha Bhende2015-10-1616-38/+196
| | | | | | | | | | | | | | | | | | Add new GALLIUM_HUD queries for: num-shaders num-resources num-state-objects num-validations map-buffer-time num-surface-views num-resources-mapped num-flushes Most of this patch was originally written by Neha. Additional clean-ups and num-flushes counter added by Brian Paul. Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: use new svga_new_shader_variant() functionBrian Paul2015-10-164-2/+12
| | | | | | To simplify upcoming new HUD shader count implementation. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: pass context to svga_tgsi_vgpu9_translate()Brian Paul2015-10-164-4/+8
| | | | | | Will be used for upcoming change. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* svga: remove svga_tgsi_vgpu9_translate() call in GS pathBrian Paul2015-10-161-7/+3
| | | | | | We can never have geometry shaders with vgpu9. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
* freedreno: add debug option to dirty state after drawRob Clark2015-10-153-2/+7
| | | | | | Similar to "dclear", "ddraw" will mark all state dirty after each draw. Signed-off-by: Rob Clark <robclark@freedesktop.org>
* freedreno/a3xx: cache-flush is needed after MEM_WRITERob Clark2015-10-153-5/+14
| | | | | | | | Otherwise the mem2gmem blit would see potentially bogus texture coordinates. Fixes an issue that shows up with glamor. CC: "11.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Rob Clark <robclark@freedesktop.org>
* gallium/util: fix debug_get_flags_option on 32-bit harderRob Clark2015-10-151-3/+3
| | | | | | | | (yes, we want PRI?64, but we want the x version rather than the u version) Signed-off-by: Rob Clark <robclark@freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* nv30: include the header of ffs prototypeChih-Wei Huang2015-10-151-0/+1
| | | | | | | | It fixes a building error of the android 6.0 64-bit target. Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org
* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
| | | | | | | | Note Android version before Lollipop is not supported. Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org
* r600/vce: enable VCE for trinity/richlandChristian König2015-10-131-1/+21
| | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* r600/uvd: disable UVD tiling by defaultChristian König2015-10-131-3/+5
| | | | | | | It has only minimal advantages for post processing and doesn't work with VCE. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* r600g: Enable GL_ARB_gpu_shader5 extensionGlenn Kennard2015-10-131-1/+1
| | | | | Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* r600g/sb: SB support for UBO indexingGlenn Kennard2015-10-1311-27/+140
| | | | | Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* r600g/sb: Support gs5 sampler indexing (v2)Glenn Kennard2015-10-139-25/+195
| | | | | | | [airlied: v2 cayman fixups] Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* nouveau: avoid double-emitting fenceIlia Mirkin2015-10-121-1/+5
| | | | | | | | | | | The act of ensuring that there is space can cause a flush to happen, which will emit the current screen fence. If that is the fence we're trying to wait on, then it will have been emitted as a result of doing the PUSH_SPACE. Don't attempt to emit it a second time. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Fixes: 8053c9208f (nouveau: avoid emitting new fences unnecessarily) Cc: mesa-stable@lists.freedesktop.org
* u_vbuf: fix vb slot assignment for translated buffersNicolai Hähnle2015-10-121-0/+1
| | | | | | | | | | | Vertex attributes of different categories (constant/per-instance/ per-vertex) go into different buffers for translation, and this is now properly reflected in the vertex buffers passed to the driver. Fixes e.g. piglit's point-vertex-id divisor test. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* ilo: improve Gen8 defines based on its PRMsChia-I Wu2015-10-1213-121/+399
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* nv50,nvc0: don't base decisions on available pushbuf spaceIlia Mirkin2015-10-113-35/+10
| | | | | | | | | | | | We still have to push everything out, might as well kick earlier and flip pushbufs when we know we'll need it. This resolves some issues with the new policy of making sure that we always leave a bit of room at the end for fences. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence) Cc: mesa-stable@lists.freedesktop.org
* nouveau: avoid emitting new fences unnecessarilyIlia Mirkin2015-10-111-3/+9
| | | | | | | | | | | | | | | | | | | | Right now we emit on every kick, but this is only necessary if something will ever be able to observe that the fence completed. If there are no refs, leave the fence alone and emit it another day. This also happens to work around an issue for the kick handler -- a kick can be a result of e.g. nouveau_bo_wait or explicit kick, or it can be due to lack of space in the pushbuf. We want the emit to happen in the current batch, so we want there to always be enough space. However an explicit kick could take the reserved space for the implicitly-triggered kick's fence emission if it happened right after. With the new mechanism, hopefully there's no way to cause two fences to be emitted into the same reserved space. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence) Cc: mesa-stable@lists.freedesktop.org
* nvc0: make use of NVC0_COMPUTE_CLASS for GF110Samuel Pitoiset2015-10-101-5/+2
| | | | | | | | | | In theory, GF110+ should also support NVC8_COMPUTE_CLASS but, in practice, a ILLEGAL_CLASS dmesg fail appears when using it. This fixes compute support and MP performance counters on GF110. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* tgsi: (trivial) kill c99-ism.Roland Scheidegger2015-10-091-2/+3
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* tgsi/scan: add info about declared samplers (v2)Marek Olšák2015-10-092-0/+3
| | | | v2: get it from declarations, not instructions
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