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* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-081-14/+14
| | | | | | | | | | With the exception of gen8, the sole user of the workaround bo are for emitting pipe controls. Move it out of the purview of the batchbuffer and into the pipecontrol. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
* i965: Query whether we have kernel support for the TIMESTAMP register onceChris Wilson2015-07-081-5/+1
| | | | | | | | | | | | | | | | Move the query for the TIMESTAMP register from context init to the screen, so that it is only queried once for all contexts. On 32bit systems, some old kernels trigger a hw bug resulting in the TIMESTAMP register being shifted and the low 32bits always zero. Detect this by repeating the read a few times and check the register is incrementing every 80ns as expected and not stuck on zero (as would be the case with the buggy kernel/hw.). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Martin Peres <martin.peres@linux.intel.com> Reviewed-by: Martin Peres <martin.peres@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-3/+3
| | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: enable ARB_framebuffer_no_attachments for Gen7+Kevin Rogovin2015-06-171-0/+1
| | | | | | | Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
* Revert "i965: Enable ARB_direct_state_access"Ian Romanick2015-05-281-1/+0
| | | | | | | This reverts commit a57feba0a35de35728269aeb26b039e4f2393d69. Acked-by: Fredrik Höglund <fredrik@kde.org> Cc: "10.6" <mesa-stable@lists.freedesktop.org>
* i965: Enable ARB_direct_state_accessFredrik Höglund2015-05-141-0/+1
| | | | | Signed-off-by: Fredrik Höglund <fredrik@kde.org> Reviewed-by: Adam Jackson <ajax@redhat.com>
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously whenever a primitive is drawn the driver would call _mesa_check_conditional_render which blocks waiting for the result of the query to determine whether to render. On Gen7+ there is a bit in the 3DPRIMITIVE command which can be used to disable the primitive based on the value of a state bit. This state bit can be set based on whether two registers have different values using the MI_PREDICATE command. We can load these two registers with the pixel count values stored in the query begin and end to implement conditional rendering without stalling. Unfortunately these two source registers were not in the whitelist of available registers in the kernel driver until v3.19. This patch uses the command parser version from intel_screen to detect whether to attempt to set the predicate data registers. The predicate enable bit is currently only used for drawing 3D primitives. For blits, clears, bitmaps, copypixels and drawpixels it still causes a stall. For most of these it would probably just work to call the new brw_check_conditional_render function instead of _mesa_check_conditional_render because they already work in terms of rendering primitives. However it's a bit trickier for blits because it can use the BLT ring or the blorp codepath. I think these operations are less useful for conditional rendering than rendering primitives so it might be best to leave it for a later patch. v2: Use the command parser version to detect whether we can write to the predicate data registers instead of trying to execute a register load command. v3: Simple rebase v4: Changes suggested by Kenneth Graunke: Split the load_64bit_register function out to a separate patch so it can be a shared public function. Avoid calling _mesa_check_conditional_render if we've already determined that there's no query object. Some styling fixes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Sort extension enable listsIan Romanick2015-05-061-33/+42
| | | | | | | Sort by GEN, then sort by extension name. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_indexChris Forbes2015-05-061-8/+8
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Enable ARB_gpu_shader5 on Gen8+.Matt Turner2015-04-271-6/+2
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Implement support for ARB_clip_control.Mathias Fröhlich2015-04-051-0/+1
| | | | | | | | | | | | | Switch between the two clip space definitions already available in hardware. Update winding order dependent state according to the clip control state. This change did not introduce new piglit quick.test regressions on an Ivybridge Mobile and a GM45 Express chipset. Also it enables and passes the clip-control and clip-control-depth-precision tests on these two chipsets. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
* i965: implement ARB_pipeline_statistics_queryBen Widawsky2015-02-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE: The implementation was initially one patch, this. All the history is kept here, even though all the core mesa changes were moved to the parent of this patch. This patch implements ARB_pipeline_statistics_query. This addition to GL does not add a new API. Instead, it adds new tokens to the existing query APIs. The work to hook up the new tokens is trivial due to it's similarity to the previous work done for the query APIs. I've implemented all the new tokens to some degree, but have stubbed out the untested ones at the entry point for Begin(). Doing this should allow the remainder of the code to be left in. The new tokens give GL clients a way to obtain stats about the GL pipeline. Generally, you get the number of things going in, invocations, and number of things coming out, primitives, of the various stages. There are two immediate uses for this, performance information, and debugging various types of misrendering. I doubt one can use these for debugging very complex applications, but for piglit tests, it should be quite useful. Tessellation shaders, and compute shaders are not addressed in this patch because there is no upstream implementation. I've implemented how I believe tessellation shader stats will work for Intel hardware (though there is a bit of ambiguity). Compute shaders are a bit more interesting though, and I don't yet know what we'll do there. For the lazy, here is a link to the relevant part of the spec: https://www.opengl.org/registry/specs/ARB/pipeline_statistics_query.txt Running the piglit tests http://lists.freedesktop.org/archives/piglit/2014-November/013321.html (http://cgit.freedesktop.org/~bwidawsk/piglit/log/?h=pipe_stats) yield the following results: > piglit-run.py -t stats tests/all.py output/pipeline_stats > [5/5] pass: 5 Running Test(s): 5 v2: - Don't allow pipeline_stats to be per stream (Ilia). This may (not sure) be needed for AMD_transform_feedback4, which we do not support. > If AMD_transform_feedback4 is supported then GEOMETRY_SHADER_PRIMITIVES_- > EMITTED_ARB counts primitives emitted to any of the vertex streams for > which STREAM_RASTERIZATION_AMD is enabled. - Remove comment from GL3.txt because it is only used for extensions that are part of required versions (Ilia) - Move the new tokens to a new XML doc instead of using the main GL4x.xml (Ilia) - Add a fallthrough comment (Ilia) - Only divide PS invocations by 4 on HSW+ (Ben) v3: - Add ARB_pipeline_statistics_query to relnotes.html - Add ARB_pipeline_statistics_query.xml to the Makefile.am, and master XML (Ilia) - Correct extension number (Ilia) - Add link to xml in the main GL API xml (Ilia) - remove special GS case from gen6_end_query (Ian) - Make lookup table static so gcc doesn't initialized it on every call (Ian) - Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian) - Core mesa parts moved into a prep patch (Ilia) v4: - Change to 10.6 relnotes since we missed 10.5 window - Moved compute shader stuff into the switch statement (Jordan) - Jordan: Add compute shader support v5: - Fixed relnote style (Ilia) v6: - Rebased on master which beat me to adding the first relnotes - essentially this undoes v5 (which had a typo anyway) - Some code style fixes (Ken) - Remove some excess comments (Ken) - Unify tessellation failure style - unreachable (Ken) - Fix workaround comment for PS invocations (Ken) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6+: enable EXT_polygon_offset_clampIlia Mirkin2015-02-021-0/+1
| | | | | | | Replace the hard-coded 0's with the context clamp value. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* Mesa: Advertise GL_OES_texture_*float* extensions support with i965.Kalyan Kondapally2015-01-291-0/+5
| | | | | | | | | This patch advertises support for GL_OES_texture_*float* extensions when using i965 drivers. Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com> Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
* i965: Cache register write capability checks.Kenneth Graunke2014-12-241-0/+12
| | | | | | | | | | | | | | | | | | | Our ability to perform register writes depends on the hardware and kernel version. It shouldn't ever change on a per-context basis, so we only need to check once. Checking introduces a synchronization point between the CPU and GPU: even though we submit very few GPU commands, the GPU might be busy doing other work, which could cause us to stall for a while. On an idle i7 4750HQ, this improves performance in OglDrvCtx (a context creation microbenchmark) by 6.14748% +/- 1.6837% (n=20). With Unigine Valley running in the background (to keep the GPU busy), it improves performance in OglDrvCtx by 2290.92% +/- 29.5274% (n=5). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Fix register write checks.Kenneth Graunke2014-10-101-0/+2
| | | | | | | | | | | | | When mapping the buffer a second time, we need to use the new pointer, not the one from the previous mapping. Otherwise, we will most likely crash. Apparently, we've just been getting lucky and getting the same bo->virtual pointer in both cases. libdrm probably has a hand in that. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Cc: mesa-stable@lists.freedesktop.org
* i965: Enable EXT_framebuffer_multisample_blit_scaled for gen8Anuj Phogat2014-10-011-2/+1
| | | | | Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965/gen6: Enable GL 3.3 and GLSL 3.30Chris Forbes2014-09-201-3/+1
| | | | | | | | | | | | Tested on my snb-gt2: 4 tests skip->pass in spec/EXT_texture_array 51 tests skip->pass in spec.glsl-3.30 4 tests skip->pass in spec/!OpenGL 3.3 No regressions; no skip->fail changes. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965/gen6: enable GLSL 1.50, OpenGL 3.2 and GL_AMD_vertex_shader_layeredSamuel Iglesias Gonsalvez2014-09-191-2/+2
| | | | | | | | | | | | | | | | Geometry shaders was the only thing we needed to enable GLSL 1.50 and OpenGL 3.2 in gen6. v2: Layered clears do not work properly in gen6 with OpenGL 3.2. Kenneth and Jordan realized that for this to work we also need GL_AMD_vertex_shader_layered (which requires OpenGL 3.2, so it could not be enabled before this patch), so we agreed to enable this together with OpenGL 3.2 in this patch. Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Enable ARB_conditional_render_inverted on Gen6+.Chris Forbes2014-08-201-0/+1
| | | | | | | | The extension requires GL 3.0, so enable on just the generations exposing that. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* i965: Enable ARB_gpu_shader5 on Gen7Chris Forbes2014-08-151-0/+3
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Enable ARB_derivative_control on Gen7+.Chris Forbes2014-08-151-0/+1
| | | | | | | | | | The extension says GL 4.0 is required. We'll meet the spirit of that restriction by enabling on just those generations which will soon support GL 4.0 (Gen7+), although it's technically supportable on all generations. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Enable the GL_ARB_texture_compression_bptc extensionNeil Roberts2014-08-121-0/+2
| | | | | | | Enables the BPTC extension on Gen>=7 and adds the necessary format mappings to get the right surface type value. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* mesa: make _mesa_override_glsl_version context-independentMarek Olšák2014-08-111-1/+1
| | | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* i965: Add support for ARB_copy_imageJason Ekstrand2014-08-111-0/+1
| | | | | | | | | | | | | | | | | This, together with the meta path, provides a complete implemetation of ARB_copy_image. v2: Add a fallback memcpy path for when the texture is too big for the blitter v3: Properly support copying between two places on the same texture in the memcpy fallback v4: Properly handle blit between the same two images in the fallback path v5: Properly handle blit between the same two compressed images in the fallback path v6: Fix a typo in a comment Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Neil Roberts <neil@linux.intel.com>
* meta: Add a meta implementation of GL_ARB_clear_textureNeil Roberts2014-07-231-0/+1
| | | | | | | | | | | | | | | | | | | | Adds an implementation of the ClearTexSubImage driver entry point that tries to set up an FBO to render to the texture and then calls glClearBuffer with a scissor to perform the actual clear. If an FBO can't be created for the texture then it will fall back to using _mesa_store_ClearTexSubImage. When used in combination with _mesa_store_ClearTexSubImage this should provide an implementation that works for all DRI-based drivers. However as this has only been tested with the i965 driver it is currently only enabled there. v2: Only enable the extension for the i965 driver instead of all DRI drivers. Remove an unnecessary goto. Don't require GL_ARB_framebuffer_object. Add some more comments. v3: Use glClearBuffer* to avoid having to modify glClearColor and friends. Handle sRGB textures. Explicitly disable dithering. Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
* i965: expose AMD_vertex_shader_viewport_index on gen7+Ilia Mirkin2014-07-021-1/+3
| | | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* Remove the ATI_envmap_bumpmap extensionJason Ekstrand2014-06-301-1/+0
| | | | | | | | | | | As far as I can tell, the Intel mesa driver is the only driver in the world still supporting this legacy extension. If someone wants to do bump mapping, they can use shaders. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1] Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2] Reviewed-by: Ian Romanick <idr@freedesktop.org> [v3]
* i965/cs: Use override structure rather than separate env varJordan Justen2014-06-161-3/+0
| | | | | | | | | | | | In 25268b93, we added a new environment variable (INTEL_COMPUTE_SHADER) to allow some constant values to be upgraded for the ARB_compute_shader extension. Now, we can look to see if the extension was enabled via the MESA_EXTENSION_OVERRIDE environment variable. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* Enable GL_ARB_explicit_uniform_location in the drivers.Tapani Pälli2014-06-161-0/+1
| | | | | | | v2: enable also for i915 (Ian) Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
* mesa: Disable GL_EXT_framebuffer_multisample_blit_scaled on Broadwell.Kenneth Graunke2014-05-191-1/+2
| | | | | | | | | It's not properly implemented in the meta code, and we don't have time to fix it for 10.2. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Cc: "10.2" <mesa-stable@lists.freedesktop.org>
* i965: Enable GL_ARB_texture_view on Broadwell.Kenneth Graunke2014-05-071-4/+1
| | | | | | | | | This is a port of commit c9c08867ed07ceb10b67ffac5f0a33812710a5e8. A tiny bit of extra work was necessary to not break stencil texturing. Cc: "10.2" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* i965: Enable INTEL_performance_query for Gen5+.Petri Latvala2014-05-021-1/+3
| | | | | Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* mesa: Remove support for desktop OpenGL GL_EXT_separate_shader_objectsIan Romanick2014-05-021-1/+0
| | | | | | | | | | | | | | | | I don't know of any applications that actually use it. Now that Mesa supports GL_ARB_separate_shader_objects in all drivers, this extension is just cruft. The entrypoints for the extension remain in the XML. This is done so that a new libGL will continue to provide dispatch support for old drivers that try to expose this extension. Future patches will add OpenGL ES GL_EXT_separate_shader_objects, but that's a different thing. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Enable ARB_texture_view on Gen7Chris Forbes2014-04-101-0/+4
| | | | | | | | | V4: Don't enable this for Gen8 yet -- that still needs wired up. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net>
* i965: Stop advertising GL_MESA_ycbcr_texture.Kenneth Graunke2014-04-091-1/+0
| | | | | | | | | | | | | | | | | The "new" fragment shader backend has never supported the necessary color conversion code for this to work. We began using the new backend in Mesa 7.10 for GLSL (commit a81d423d93f22a948f3aa4bf73, October 2010), and for ARB_fragment_program in Mesa 9.1 (commit 97615b2d8c7c3cea6fd3a4, August 2012). I haven't heard any complaints, so I don't think anyone will miss this feature. I believe mplayer used it at one point, but these days defaults to other paths anyway. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Enable ARB_vertex_type_10f_11f_11f_rev for Gen4/5 also.Chris Forbes2014-03-221-1/+1
| | | | | | | Tested on ILK and CTG (with the GL3isms taken out of the piglits). Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Add support for GL_ARB_buffer_storage.Eric Anholt2014-03-141-0/+1
| | | | | | | | | | | | It turns out we can allow COHERENT storage/mappings all the time, regardless of LLC vs non-LLC. It just means never using temporary mappings to avoid GPU stalls, and on non-LLC we have to use the GTT intead of CPU mappings. If we were to use CPU maps on non-LLC (which might be useful if apps end up using buffer_storage on PBO reads, to avoid WC read slowness), those would be PERSISTENT but not COHERENT, but doing that would require us driving the clflushes from userspace somehow. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Implement ARB_stencil_texturing on Gen8+.Kenneth Graunke2014-03-041-0/+4
| | | | | | | | | | | | | | | | | | | | On earlier hardware, we had to implement math in the shader to translate Y-tiled or untiled coordinates to W-tiled coordinates (which is what BLORP does today in order to texture from stencil buffers). On Broadwell, we can simply state that it's W-tiled in SURFACE_STATE, and adjust the pitch. This is much easier. In the surface state code, I chose to handle the "should we sample depth or stencil?" question separately from the setup for sampling from stencil. This should make it work with the BindRenderbufferTexImage hook as well, and hopefully be reusable for GL_ARB_texture_stencil8 someday. v2: Update docs/GL3.txt (caught by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* mesa: GL_ARB_half_float_pixel is not optionalIan Romanick2014-02-111-1/+0
| | | | | | | | | | | | | | | | | Almost every driver already supported it. All current and future Gallium drivers always support it, and most existing classic drivers support it. This only changes radeon and nouveau. This extension only adds data types that can be passed to, for example, glTexImage2D. It does not add internal formats. Since you can already pass GL_FLOAT to glTexImage2D this shouldn't pose any additional issues with those drivers. Note that r200 and i915 already supported this extension, and they don't support floating-point textures either. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Enable ARB_texture_gather for one component on Gen6.Chris Forbes2014-02-081-1/+1
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/cs: Allow ARB_compute_shader to be enabled via env var.Paul Berry2014-02-051-0/+3
| | | | | | | | | | This will allow testing of compute shader functionality before it is completed. To enable ARB_compute_shader functionality in the i965 driver, set INTEL_COMPUTE_SHADER=1. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* mesa: GL_EXT_framebuffer_blit is not optionalIan Romanick2014-01-271-1/+0
| | | | | | | | | Every driver supports it. All current and future Gallium drivers always support it, and all existing classic drivers support it. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Enable ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-201-0/+6
| | | | | | | | | | | | | v2 (idr): Only enable the extension on GEN7+ w/core profile because it requires geometry shaders. v3 (idr): Add some casting to fix setting of ViewportBounds.Min. Negating an unsigned value, then casting to float doesn't do what you might think it does. Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/alanh@tungstengraphics.com/alanh@vmware.com/ s/jens@tungstengraphics.com/jowen@vmware.com/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g s/keithw\?@tungstengraphics.com/keithw@vmware.com/g s/michel@tungstengraphics.com/daenzer@vmware.com/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/zack@tungstengraphics.com/zackr@vmware.com/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <brianp@vmware.com>
* mesa: GL_EXT_packed_depth_stencil is not optionalIan Romanick2013-12-201-1/+0
| | | | | | | | Every driver supports it. All current and future Gallium drivers always support it, and all existing classic drivers support it. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-5/+5
| | | | | | | Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Use a single enable for GL_EXT_texture_array and GL_MESA_texture_arrayIan Romanick2013-12-041-1/+0
| | | | | | | | | | | Every driver that enables one also enables the other. The difference between the two is MESA adds support for fixed-function and assembly fragment shaders, but EXT only adds support for GLSL. The MESA extension was created back when Mesa did not support GLSL. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* i965: Skip the register write check on Broadwell.Kenneth Graunke2013-12-021-1/+5
| | | | | | | | | MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code doesn't work. But supposedly Broadwell has a register whitelist and just works out of the box anyway, so there's no need to check. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Enable ARB_draw_indirect (and ARB_multi_draw_indirect) on Gen7+Chris Forbes2013-11-251-0/+1
| | | | | | | | | | | .. and mark them off on the extensions list as done. V2: Enable only if pipelined register writes work. V3: Also update relnotes Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
generated by cgit v1.1 at 2024-08-03 06:22:47 +0000