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* intel: Request DRI2 buffers for separate stencil and hizChad Versace2011-06-083-14/+444
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When it is sensible to do so, 1) intelCreateBuffer() now attaches separate depth and stencil buffers to the framebuffer it creates. 2) intel_update_renderbuffers() requests for the framebuffer a separate stencil buffer (DRI2BufferStencil). The criteria for "sensible" is: - The GLX config has nonzero depth and stencil bits. - The hardware supports separate stencil. - The X driver supports separate stencil, or its support has not yet been determined. If the hardware supports hiz too, then intel_update_renderbuffers() also requests DRI2BufferHiz. If after requesting DRI2BufferStencil we determine that X driver did not actually support separate stencil, we clean up the mistake and never ask for DRI2BufferStencil again. CC: Ian Romanick <idr@freedesktop.org> CC: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* intel: Add assertions to intelCreateBuffer()Chad Versace2011-06-081-3/+12
| | | | | | | | | | | | | | | Assert that the GLX config has an expected depth/stencil bit combination: one of d24/s8, d16/s0, d0/s0. These are the only depth/stencil configurations that we advertise. Remove the check for software stencil, because given the assertions' constraints the check always fails. CC: Ian Romanick <idr@freedesktop.org> CC: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* intel: Refactor intel_update_renderbuffers()Chad Versace2011-06-081-111/+212
| | | | | | | | | | | | | | | | | | | | | | Extract the code that queries DRI2 to obtain the DRIdrawable's buffers into intel_query_dri2_buffers_no_separate_stencil(). Extract the code that assigns the DRI buffer's DRM region to the corresponding renderbuffer into intel_process_dri2_buffer_no_separate_stencil(). Rationale --------- The next commit enables intel_update_renderbuffers() to query for separate stencil and hiz buffers. Without separating the separate-stencil and no-separate-stencil paths, intel_update_renderbuffers() degenerates into an impenetrable labyrinth of if-trees. CC: Ian Romanick <idr@freedesktop.org> CC: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* intel: Add function intel_renderbuffer_set_hiz_region()Chad Versace2011-06-082-0/+17
| | | | | | | | | | | It's the analog of intel_renderbuffer_set_region(), but for the hiz region of course. CC: Ian Romanick <idr@freedesktop.org> CC: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* intel/intel_context.c: Remove unused functionsChad Versace2011-06-081-48/+0
| | | | | | | | | | | Remove functions intel_override_hiz() and intel_override_separate_stencil(). They are now located in intel_screen.c. CC: Ian Romanick <idr@freedesktop.org> CC: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* intel: Add flags to intel_screen for hiz and separate stencilChad Versace2011-06-083-7/+73
| | | | | | | | | | | | | | | | | | | | | Add the fields below to intel_screen. The expression in parens is the value to which intelInitScreen2() currently sets the field. GLboolean hw_has_separate_stencil (true iff gen >= 7) GLboolean hw_must_use_separate_stencil (true iff gen >= 7) GLboolean hw_has_hiz (always false) enum intel_dri2_has_hiz dri2_has_hiz (INTEL_DRI2_HAS_HIZ_UNKNOWN) The analogous fields in intel_context now inherit their values from intel_screen. When hiz and separate stencil become completely implemented for a given chipset, then the respective fields need to be enabled. CC: Ian Romanick <idr@freedesktop.org> CC: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* intel: Define enum intel_dri2_has_hizChad Versace2011-06-081-0/+56
| | | | | | | | | | | | | ... which indicates if the X driver supports DRI2BufferHiz and DRI2BufferStencil. I'm placing this in its own commit due to the large comment block. CC: Ian Romanick <idr@freedesktop.org> CC: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* intel: Define span functions for S8 renderbuffersChad Versace2011-06-081-0/+64
| | | | | | | | | Since the stencil buffer is interleaved, the generic Mesa renderbuffer accessors do not suffice. Custom span functions are necessary. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chad Versace <chad@chad-versace.us>
* i965/brw: Emit state for hiz and separate stencil buffersChad Versace2011-06-082-9/+107
| | | | | | | | | | When emitting 3DSTATE_DEPTH_BUFFER, also emit 3DSTATE_HIER_DEPTH_BUFFER if there is a hiz buffer. Ditto for 3DSTATE_STENCIL_BUFFER and a separate stencil buffer. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad@chad-versace.us>
* osmesa: Fix missing symbols when GLX_INDIRECT_RENDERING is defined.Jeremy Huddleston2011-06-071-0/+28
| | | | | | | | | When GLX_INDIRECT_RENDERING is defined, some symbols are used in libglapi.a but are not defined. Define them through the help of glapitemp.h. Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com> Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
* mga: enable GL_ARB_vertex_array_object extensionNicolas Kaiser2011-06-071-0/+2
| | | | | | | Tested on a Matrox G550 AGP. Signed-off-by: Nicolas Kaiser <nikai@nikai.net> Signed-off-by: Brian Paul <brianp@vmware.com>
* intel: Update intel-decode.c from intel-gpu-tools.Eric Anholt2011-06-072-88/+785
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* intel: Implement glFinish() correctly by waiting on all previous rendering.Eric Anholt2011-06-073-16/+13
| | | | | Before, we were waiting for (most of) the current framebuffer to be done, which is not quite the same thing.
* radeon: Use pciid list to generate PCI_CHIP_<FAMILY>_<ID> definesBenjamin Franzke2011-06-071-491/+9
| | | | Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
* i965: Fix flipped GT1 vs GT2 URB VS entry count limits.Eric Anholt2011-06-071-2/+2
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* i965: Update SURFACE_STATE dumping for Ivybridge.Kenneth Graunke2011-06-061-3/+43
| | | | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Update SAMPLER_STATE dumping for Ivybridge.Kenneth Graunke2011-06-061-1/+53
| | | | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Update SF_CLIP_VIEWPORT state dumping for Ivybridge.Kenneth Graunke2011-06-061-2/+38
| | | | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* dri/nouveau: fix gnome-shell segfaultBen Skeggs2011-06-061-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* meta: Don't do sRGB encode for framebuffer blits on sRGB-enabled framebuffers.Eric Anholt2011-06-051-0/+6
| | | | | | | Fixes fbo-srgb-blit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35373 Reviewed-by: Brian Paul <brianp@vmware.com>
* meta: Don't do srgb to linear decode when blitting srgb textures.Eric Anholt2011-06-051-0/+10
| | | | | | Fixes the GL_SRGB8_ALPHA8 -> GL_RGBA8 blits in fbo-srgb-blit.c Reviewed-by: Brian Paul <brianp@vmware.com>
* i965: Drop remaining strict conformance fallback for GL_POINT_SMOOTH.Eric Anholt2011-06-031-30/+0
| | | | | We actually could do this in hardware in the fragment shader using gl_PointCoord and the point's size.
* i965: Drop strict conformance fallback for GL_LINE_STIPPLE.Eric Anholt2011-06-031-18/+0
| | | | | | We implement line stipples, just not *quite* correctly. We have a piglit testcase to use when we want to fix it, if we do. Until then, don't lie to our test suites.
* i965: Drop strict conformance fallback for GL_LINE_SMOOTH.Eric Anholt2011-06-031-9/+0
| | | | | | | | | | We do have hardware antialised lines. If we care, we should actually fix them to be conformant (or as close as possible) instead of using this knob to fool testcases using swrast. For some interesting reading on the state of GL_*_SMOOTH across several drivers, see: http://homepage.mac.com/arekkusu/bugs/invariance/HWAA.html
* i965: Drop strict conformance fallback for GL_POLYGON_SMOOTH.Eric Anholt2011-06-031-6/+0
| | | | | | From my reading of the GL 2.1 spec, no antialiasing is strictly conformant for polygon smoothing. Yes, it's absurd, but then, hardware doesn't support this so maybe it's not so absurd.
* i965: Drop INTEL_CONFORMANCE=2 fallback code.Eric Anholt2011-06-031-3/+0
| | | | | This was just a duplicate of no_rast=true driconf option, which is relatively standard across drivers.
* dri: add missing files from 873379a8818eed9ab16c24728b7091a3a3705c5bBrian Paul2011-06-022-0/+112
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* dri/nouveau: Fix build with --enable-shared-dricore.Johannes Obermayr2011-06-0217-140/+56
| | | | | | | | | - Based on the work of Себастьян Gliţa Κατινα <cglita@yahoo.com> - Split Makefile.template into Makefile.defines and Makefile.targets - Adapt other drivers to new situation - Fixes https://bugs.freedesktop.org/show_bug.cgi?id=35441 Signed-off-by: Brian Paul <brianp@vmware.com>
* r300: remove MIN3 macro, already defined in macros.hBrian Paul2011-06-021-1/+0
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* i965: Raise const.MaxTextureLevels to 14 (8192)Chris Wilson2011-06-021-3/+3
| | | | | | | Mesa now limits, by default, the max number of texture levels to 15 so we can now support the architectural maximum for gen4-6 of 14. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* r600c: add support for llanoAlex Deucher2011-05-316-1/+98
| | | | Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
* i965/fs: Use the embedded compare in SEL on gen6+.Eric Anholt2011-05-312-16/+30
| | | | | | | | | | | This avoids the extra CMP and the predication on SEL, so in addition to one less instruction, it makes scheduling less constrained. Improves glbenchmark Egypt performance 0.6% +/- 0.2% (n=3). Reduces FS instruction count across affected shaders in shader-db by 1.3% without regressing any. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Remove brw_surface_state struct that is now unused.Eric Anholt2011-05-311-74/+0
| | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Switch brw_state_dump to using bitshifting for surface state.Eric Anholt2011-05-312-9/+17
| | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Replace struct with bit shifting for WM null surfaces.Eric Anholt2011-05-311-13/+13
| | | | | | | | | Reduces compiled size of brw_wm_surface_state.o another 1.9%. Overall, this brw_wm_surface_state reduction series cuts firefox-talos-gfx runtime by 0.68% +/- 0.42% (n=6). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Replace struct with bit shifting for WM pull constant surfaces.Eric Anholt2011-05-312-35/+17
| | | | | | This reduces compiled size (4.7% of brw_wm_surface_state.o). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Replace struct with bit shifting for WM render target surfaces.Eric Anholt2011-05-312-31/+45
| | | | | | This massively reduces compiled size (6.7% of brw_wm_surface_state.o). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Replace structs with bitfield shifting for WM texture surfaces.Eric Anholt2011-05-311-32/+35
| | | | | | This massively reduces compiled size (4.9% of brw_wm_surface_state.o). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Add defines for surface state setup using bitfield shifting.Eric Anholt2011-05-311-1/+33
| | | | | | | It turns out that gcc is just awful at generating code for brw_structs.h style state setup, and using bitshifting on u32s generates better code while being similarly readable (and more verifiable compared to the specs, using the INTEL_MASK macro).
* i965: Don't compute brw->wm.input_size_masks when it's unused.Eric Anholt2011-05-311-1/+11
| | | | | | | | It's only used in the old fragment program path, to avoid projection when w is always 1. We do want to do this in the new path pre-gen6 too, but we'll probably do it through the ir. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Drop a gratuitous "if" that the compiler didn't eliminate at -O2.Eric Anholt2011-05-311-10/+8
| | | | | | | | Oddly, this increases compiled code size. (marking the 'if' as likely also increases code size, but not as much). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Move prepare_wm_surfaces texobj declarations inside of _ReallyEnabled.Eric Anholt2011-05-311-2/+3
| | | | | | | | Interestingly, the compiler wasn't doing this for us at -O2, so we were doing the computation for every non-_ReallyEnabled unit. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* intel: Remove unused NO_TILE macroIan Romanick2011-05-311-3/+0
| | | | Reviewed-by: Eric Anholt <eric@anholt.net>
* r300g: Fix non-dri buildsTom Stellard2011-05-282-1/+7
| | | | | This is just a temporary solution for now until there is a better way to share code between mesa and gallium.
* i965/fs: Fix up for 8752764076e5b3f052a57e0134424a37bf2e9164.Eric Anholt2011-05-272-4/+4
| | | | I failed to commit and squash before pushing.
* i965/fs: Do a FS compile up front at link time to produce link errors.Eric Anholt2011-05-275-27/+142
| | | | | | At glLinkShaders time, a fail() call in FS compile in 8-wide (the one that's required to succeed, though we may relax that at some point for pre-Ironlake performance) will now report out as a link error.
* i965/fs: Split the GLSL IR -> FS LIR visitor to brw_fs_visitor.cpp.Eric Anholt2011-05-274-1679/+1736
| | | | | | | | | We now have: brw_fs.cpp handles calling out to everything and optimization. brw_fs_visitor.cpp handles translating to our LIR. brw_fs_emit.cpp handles emitting from our LIR to native code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs: Split the BRW native code emit to brw_fs_emit.cppEric Anholt2011-05-273-839/+876
| | | | | | | This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Move a couple of GLSL IR -> BRW helper functions to brw_shader.cpp.Eric Anholt2011-05-273-49/+76
| | | | | | These will be used by the VS backend as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Move non-FS-specific shader support to brw_shader.cpp.Eric Anholt2011-05-273-100/+129
| | | | | | | These only existed in brw_fs.cpp because it was the only .cpp file in the area when I wrote them. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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