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* anv: automake: build with -BsymbolicEmil Velikov2016-08-181-0/+1
| | | | | | | | | Explicitly suggested in the Loader interface version 2 section, but it's good idea either way. It essentially, ensures that our symbols are not interposed. Cc: "12.0" <mesa-stable@lists.freedesktop.org> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* anv: automake: use VISIBILITY_CFLAGS to restrict symbol visibilityEmil Velikov2016-08-182-3/+7
| | | | | | | | | | | Hide the internal symbols and annotate the vk_icdGetInstanceProcAddr as public since the loader needs it (since v1 of the loader interface). v2: Add VISIBILITY_CFLAGS to AM_CFLAGS (Ken) Cc: "12.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1) Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* anv: remove internal 'validate' layerEmil Velikov2016-08-182-110/+11
| | | | | | | | | | | Presently the layer has only a single entry point. As mentioned by Jason the function does not validate anything that isn't checked elsewhere, thus we can drop the whole thing. Cc: "12.0" <mesa-stable@lists.freedesktop.org> Cc: Jason Ekstrand <jason@jlekstrand.net> Suggested-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* nir/search: Extend 'a@bool' to handle a couple of system values.Kenneth Graunke2016-08-181-0/+7
| | | | | | | | | | | | | | load_front_face and load_helper_invocation produce booleans. On Broadwell: total instructions in shared programs: 11638956 -> 11638011 (-0.01%) instructions in affected programs: 115093 -> 114148 (-0.82%) helped: 628 HURT: 14 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir/search: Fold src_is_bool()/alu_instr_is_bool() into src_is_type().Kenneth Graunke2016-08-181-31/+19
| | | | | | | | | | | | I don't want src_is_bool() and src_is_type(x, nir_type_bool) to behave differently. Having the logic spread out over three functions makes it harder to decide where to put new logic, as well. So, combine them all. It's a bit simpler because there's now only one recursive function rather than a pair of mutually recursive functions. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* nir/search: Introduce a src_is_type() helper for 'a@type' handling.Kenneth Graunke2016-08-181-13/+29
| | | | | | | | | | | | Currently, 'a@type' can only match if 'a' is produced by an ALU instruction. This is rather limited - there are other cases we can easily detect which we should handle. Extending the code in-place would be fairly messy, so we introduce a new src_is_type() helper. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Fix barrier count shift in scalar TCS backend.Kenneth Graunke2016-08-181-1/+1
| | | | | | | | | | | | The "Barrier Count" field goes in 14:9 of m0.2. The vec4 backend correctly shifts by 9, but the scalar backend only shifted by 8. It's not like this changed - I think I just made a typo when writing the original scalar TCS backend code. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
* i965: Fix execution size of scalar TCS barrier setup code.Kenneth Graunke2016-08-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the scalar TCS backend was generating: mov(8) g17<1>UD 0x00000000UD { align1 WE_all 1Q compacted }; and(8) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1Q }; shl(8) g17.2<1>UD g17.2<8,8,1>UD 0x0000000bUD { align1 WE_all 1Q }; or(8) g17.2<1>UD g17.2<8,8,1>UD 0x00008200UD { align1 WE_all 1Q }; send(8) null<1>UW g17<8,8,1>UD gateway (barrier msg) mlen 1 rlen 0 { align1 WE_all 1Q }; This is rubbish - g17.2<8,8,1>UD spans two registers, and is an illegal region. Not to mention it clobbers 8 channels of data when we only wanted to touch m0.2. Instead, we want: mov(8) g17<1>UD 0x00000000UD { align1 WE_all 1Q compacted }; and(1) g17.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all }; shl(1) g17.2<1>UD g17.2<0,1,0>UD 0x0000000bUD { align1 WE_all }; or(1) g17.2<1>UD g17.2<0,1,0>UD 0x00008200UD { align1 WE_all }; send(8) null<1>UW g17<8,8,1>UD gateway (barrier msg) mlen 1 rlen 0 { align1 WE_all 1Q }; Using component() accomplishes this. Fixes GL44-CTS.tessellation_shader.tessellation_shader_tc_barriers. barrier_guarded_read_write_calls on Skylake. Probably fixes other barrier issues on Gen8+. v2: Use a group(1, 0) builder so inst->exec_size is set correctly (thanks to Francisco Jerez for catching that it was incorrect). Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v1] Reviewed-by: Francisco Jerez <currojerez@riseup.net>
* i965: Implement the WaPreventHSTessLevelsInterference workaround.Kenneth Graunke2016-08-186-3/+175
| | | | | | | | | | | Fixes several GL44-CTS.tessellation_shader (and GL45 and ES31) subcases: - vertex_spacing - tessellation_shader_point_mode.points_verification - tessellation_shader_quads_tessellation.inner_tessellation_level_rounding Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
* nir/builder: Add bany_inequal and bany helpers.Kenneth Graunke2016-08-181-0/+19
| | | | | | | | | | The first simply picks the bany_inequal[234] opcodes based on the SSA def's number of components. The latter implicitly compares with zero to achieve the same semantics of GLSL's any(). Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
* mesa: Fix uf10_to_f32() scale factor in the E == 0 and M != 0 case.Kenneth Graunke2016-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GL_EXT_packed_float, 2.1.B Unsigned 10-Bit Floating-Point Numbers: 0.0, if E == 0 and M == 0, 2^-14 * (M / 32), if E == 0 and M != 0, 2^(E-15) * (1 + M/32), if 0 < E < 31, INF, if E == 31 and M == 0, or NaN, if E == 31 and M != 0, In the second case (E == 0 and M != 0), we were multiplying the mantissa by 2^-20, when we should have been multiplying by 2^-19 (which is 2^(-14 + -5), or 2^-14 * 2^-5, or 2^-14 / 32). The previous section defines the formula for 11-bit numbers, which is: 2^-14 * (M / 64), if E == 0 and M != 0, In other words, we had accidentally copy and pasted the 11-bit code to the 10-bit case, and neglected to change the exponent. Fixes dEQP-GLES3.functional.pbo.renderbuffer.r11f_g11f_b10f_triangles when run with surface dimensions of 1536x1152 or 1920x1080. Cc: mesa-stable@lists.freedesktop.org References: https://code.google.com/p/chrome-os-partner/issues/detail?id=56244 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com> Reviewed-by: Antia Puentes <apuentes@igalia.com>
* swr: [rasterizer core] only use Viewport/Scissors during SwrDraw* operationsTim Rowley2016-08-1712-415/+400
| | | | | | | | | | | Add explicit rects for: - SwrClearRenderTarget - SwrDiscardRect - SwrInvalidateTiles - SwrStoreTiles Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer common] reorder SWR_FORMAT_INFOTim Rowley2016-08-172-825/+1433
| | | | Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] make dirtytile list point directly to macrotilequeuesTim Rowley2016-08-173-14/+15
| | | | | | Speeds up high geometry HPC workloads. Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] portability - remove use of INT64Tim Rowley2016-08-171-2/+2
| | | | Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] viewport transform disabled fixTim Rowley2016-08-171-4/+11
| | | | | | | When viewport transform is disabled (ie. screen space coords are passed in directly), the W component should be interpreted as RHW. Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] clamp scissor rects to current tile rectTim Rowley2016-08-171-0/+18
| | | | Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] align stats structuresTim Rowley2016-08-171-2/+2
| | | | Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] use AVX2 permute to simplify PaTriListTim Rowley2016-08-171-1/+35
| | | | Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] move some global variables to SWR_CONTEXTTim Rowley2016-08-172-9/+9
| | | | Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer core] change scale on VP matrix element gathersTim Rowley2016-08-171-6/+6
| | | | | | | Was 1, which led to pulling denorms for non-zero indices. Changed to sizeof(float). Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* swr: [rasterizer] implementing native AVX-512 simd16 intrinsicsTim Rowley2016-08-172-84/+265
| | | | Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
* i965/blorp: Use nir_alu_type for the texture data typeJason Ekstrand2016-08-172-27/+16
| | | | | | This lets us remove the brw_reg.h include Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: brw_blorp_blit.cpp -> blorp_blit.cJason Ekstrand2016-08-172-6/+6
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: brw_blorp_clear.cpp -> blorp_clear.cJason Ekstrand2016-08-172-5/+1
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Split brw_blorp.c/h into multiple filesJason Ekstrand2016-08-1711-1373/+1495
| | | | | | | | | | | This mega-commit pulls most of the i965-specific bits of blorp into the brw_blorp.c/h files which now contain nothing but i965 wrappers around "core blorp" calls. The "core blorp" api is moved into blorp.h and the internal blorp data structures are moved into blorp_priv.h. The new file blorp.c is created to house "core blorp" internals which are pulled from the old brw_blorp.c Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Factor the guts of blorp_hiz_exec into a helperJason Ekstrand2016-08-171-18/+25
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Break the guts of do_single_blorp_clear into two helpersJason Ekstrand2016-08-171-64/+111
| | | | | | | | The helpers are completely miptree-unaware and each fairly cleanly do a single thing. This does come at the downside of not doing proper debug reporting on whether or not we're doing replicated clears. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/meta_util: Convert get_fast_clear_rect to take an isl_surfJason Ekstrand2016-08-173-14/+17
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/clear: Move isl_surf setup higher in the functionJason Ekstrand2016-08-171-10/+10
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Refactor fast-clear logic a bitJason Ekstrand2016-08-171-12/+13
| | | | | | | | | This pulls the mcs allocation into the if statement where we initially determine that we are doing a fast clear and moves the programming of wm_inputs and figuring out the fast clear rect into it's own if statement. The next commit will put code inbetween the two. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/clear: Stop stomping the destination formatJason Ekstrand2016-08-171-3/+1
| | | | | | | The blorp_surface_info_init call above should set the format for us and stomping it later does nothing whatsoever. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/meta_util: Only modify the input parameters in get_fast_clear_rectJason Ekstrand2016-08-173-13/+4
| | | | | | | | We had another inline copy of brw_meta_get_buffer_rect embedded in get_fast_clear_rect for no good reason. This lets us get rid of the gl_frameuffer parameter to get_fast_clear_rect. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Stop calling brw_meta_get_buffer_rectJason Ekstrand2016-08-173-24/+0
| | | | | | | | We already have an inlined version of the function slightly higher up in do_single_blorp_clear and all calling it does is stomp the values with the same thing. We might as well just get rid of it. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Pull the guts of resolve_color into a miptree-agnostic helperJason Ekstrand2016-08-171-18/+25
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/meta_util: Convert get_resolve_rect to use ISLJason Ekstrand2016-08-173-28/+28
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Make the guts of brw_blorp_blit_miptrees miptree-unawareJason Ekstrand2016-08-172-19/+53
| | | | | | | | | Now that we have the brw_blorp_surf struct, we can start to make bits of blorp completely miptree-unaware. To start things off, we split the guts of brw_blorp_blit_miptrees into a brw_blorp_blit function which knows nothing about miptrees. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add a new brw_blorp_surf intermediate structJason Ekstrand2016-08-174-99/+188
| | | | | | | | At the moment, this seems to make all of the interfaces messier rather than clener. However, it does provide a representation of a surface that simultaneously contains everything and is completely unaware of miptrees. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use the isl_surf for more params setupJason Ekstrand2016-08-171-58/+21
| | | | | | | | The isl_surf munging doesn't happen until fairly late in the blorp_blit function. We can use the isl_surf for the vast majority if not all of our params setup. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Do gen6 stencil offsets up-frontJason Ekstrand2016-08-173-86/+34
| | | | | | | | This keeps all of the nastyness of gen6 stencil on the i965 side of the API line and lets us delete that nasty hand-rolled ISL-based offset path that we were using for ALL_SLICES_AT_EACH_LOD. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Set up HiZ surfaces up-frontJason Ekstrand2016-08-174-32/+65
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i964/blorp: Set up most aux surfaces up-frontJason Ekstrand2016-08-172-23/+28
| | | | | | | | | This commit also adds support for an offset for aux surfaces. In GL, this only gets used for HiZ on SNB at the moment. However, in Vulkan, all aux surfaces are at a non-zero offset and that is likely to happen in GL eventually. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Stop using the miptree in state setup for tex/rt surfacesJason Ekstrand2016-08-176-50/+45
| | | | | | | | | | This commit movies us from a miptree model to a surf+bo+offset model. In the GL driver, miptrees are almost always at the start of the bo so the offset is zero but we don't want to always make that assumption. In the sort term, gen6 stencil and HiZ will be at an offset but, in the long term, any Vulkan surface is liable to be at a non-zero offset. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/blit: Move format work-arounds before surface_info_initJason Ekstrand2016-08-171-11/+12
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Add real support for HiZJason Ekstrand2016-08-171-13/+28
| | | | | | | | The previous HiZ support was bogus because all of get_aux_isl_surf looked at mt->mcs_mt directly. For HiZ buffers, you need to look at either mt->hiz_buf or mt->hiz_buf->mt. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl/state: Only set clear color if aux is usedJason Ekstrand2016-08-171-25/+27
| | | | | | | Otherwise, the clear color will get ignored. This prevents assertion errors if clear color is set to something invalid and aux is not used. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Use the isl helpers for creating aux surfacesJason Ekstrand2016-08-171-46/+9
| | | | | | | | | | | In order for the calculations of things such as fast clear rectangles to work, we need more details of the auxiliary surface to be correct. In particular, we need to be able to trust the width and height fields. (These are not necessarily what you want coming out of the miptree.) The only values state setup really cares about are the row and array pitch and those we can safely stomp from the miptree. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Add helpers for creating different types of aux surfacesJason Ekstrand2016-08-172-0/+136
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Use mcs_mt->qpitch for aux surfacesJason Ekstrand2016-08-171-1/+2
| | | | | | | At one point, we were doing this correctly. It must have gotten lost in one of the many rebases. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/miptree: Allow get_aux_isl_surf when there is no aux surfaceJason Ekstrand2016-08-171-1/+2
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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