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* gallium: use enums in p_shader_tokens.h (v2)Marek Olšák2016-04-221-139/+164
| | | | | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1) Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1) Acked-by: Jose Fonseca <jfonseca@vmware.com> (v1) v2: name enums
* gallium: use enums in p_defines.h (v2)Marek Olšák2016-04-221-173/+205
| | | | | | | | | | and remove number assignments which are consecutive Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1) Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1) Acked-by: Jose Fonseca <jfonseca@vmware.com> (v1) v2: name enums
* radeonsi: remove the shader parameter from si_set_ring_bufferMarek Olšák2016-04-223-15/+11
| | | | | | | | not used anymore this is a follow-up to the RW buffer cleanup. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* radeonsi: decrease GS copy shader user SGPRs to 2Marek Olšák2016-04-222-3/+3
| | | | | | | | const buffers are no longer used since the clip plane const buffer was moved to RW buffers Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: shorten slot masks to 32 bitsMarek Olšák2016-04-224-63/+61
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: clean up shader resource limit definitionsMarek Olšák2016-04-223-23/+12
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move default tess level constant buffer to RW buffersMarek Olšák2016-04-225-10/+35
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move sample positions constant buffer to RW buffersMarek Olšák2016-04-223-4/+5
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move clip plane constant buffer to RW buffersMarek Olšák2016-04-224-14/+12
| | | | | Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: rework polygon stippling to use constant buffer instead of textureMarek Olšák2016-04-226-101/+55
| | | | | | | | | add it to the RW_BUFFERS descriptor array now the slot masks don't have to have 64 bits Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: generalize si_set_constant_bufferMarek Olšák2016-04-221-10/+17
| | | | | | | this will be used in the next commit Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: make RW buffer descriptor array global, not per shader stageMarek Olšák2016-04-222-51/+43
| | | | | | | v2: also simplify invalidation of RW buffer bindings (squashed) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: rename and rearrange RW buffer slotsMarek Olšák2016-04-224-30/+39
| | | | | | | | | - use an enum - use a unique slot number regardless of the shader stage (the per-stage slots will go away for RW buffers) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallivm: fix bogus argument order to lp_build_sample_mipmap functionRoland Scheidegger2016-04-211-2/+2
| | | | | | | | | | | | | | | Screwed up since 0753b135f6e83b171d8a1b08aea967374f3542bc. (Only an issue with different min/mag filters, and then only in some cases, which is probably why it went unnoticed for quite a while. The effect should have simply been nearest mip filter instead of linear, iff min was nearest, mag was linear, and all pixels hit the mignifying path.) Fixes a bunch of dEQP failures. Reviewed-by: Jose Fonseca <jfonseca@vmware.com> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
* i965: Fix clear code for ignoring colormask for XRGB formats on Gen9+.Kenneth Graunke2016-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | In commit cda886a4851ab767fba40e8474d6fa8190347e4f, Neil made us stop advertising RGBX formats on Gen9+, as the hardware apparently no longer has working fast clear support for those formats. Instead, we just fall back to RGBA formats, and use SCS to override alpha to 1.0. This is fine, but had one unintended side effect: it made us fall back to slow clears when the color mask disables alpha. Normally, we ignore the color mask for non-existent channels. This includes alpha for XRGB formats as writing garbage to the X channel is harmless. But, now that we use RGBA, we think there's a real alpha channel, and can't do the optimization. To hack around this, check if _BaseFormat is GL_RGB and ignore alpha. Improves WebGL Aquarium performance on Skylake GT3e by about 50% by letting it use repclears instead of slow clears. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* i965/blorp: Improve precission of blitting coordinates when clippingIago Toral Quiroga2016-04-211-61/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | We do this in two steps: first we clip the dst rect and adjust the src rect accordingly. Then we do it the other way around. In both passes the adjustment part involves multiplying by a scale factor that can lead to a small precision loss. This is breaking a few dEQP tests. Specifically, the problem happens when we need to clip the same coordinate twice. For example, if srcX0 and dstX0 need both to be clipped we want to avoid the situation where we clip srcX0 first, then adjust dstX0 accordingly but then we realize that the resulting dstX0 still needs to be clipped, so we clip dstX0 and adjust srcX0 again. Each of these two passes can lead to precission loss. What we want to do here is detect the rect that leads to the largest clip (accounting for the scale factor involved), clip that rect and adjust the other one. With this we ensure that the adjusted coordinate does not need to be clipped again and we can skip a second pass, improving precision. Fixes the following 4 dEQP tests: dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_x_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_x_linear dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_x_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_x_linear Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Mark Janes <mark.a.janes@intel.com>
* radeonsi: Add config parameter to si_shader_apply_scratch_relocs.Bas Nieuwenhuizen2016-04-214-3/+5
| | | | | | | shader->config is not updated for compute kernels. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* glsl: Relax GLSL 1.10 float suffix error to a warning.Matt Turner2016-04-211-2/+2
| | | | | | | | | | | | Float suffixes are allowed in all subsequent GLSL specifications, and it's obvious what the user meant if they specify one. Accept it with a warning to avoid breaking applications, like Planeshift (although it looks like between 0.6.1 and 0.6.3 they might have removed the suffixes from their shaders). Reviewed-by: Lars Hamre <chemecse@gmail.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/fs: Readd opt_drop_redundant_mov_to_flags().Matt Turner2016-04-212-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b449366587b5f3f64c6fb45fe22c39e4bc8a4309. I removed the pass thinking that it was now not useful, but that was not true. I believe I ran shader-db on HSW and saw no results, but HSW does not use the unlit centroid workaround code and as a result does not emit redundant MOV_DISPATCH_TO_FLAGS instructions. On IVB, the shader-db results are: total instructions in shared programs: 6650806 -> 6646303 (-0.07%) instructions in affected programs: 106893 -> 102390 (-4.21%) helped: 793 total cycles in shared programs: 56195538 -> 56103720 (-0.16%) cycles in affected programs: 873048 -> 781230 (-10.52%) helped: 553 HURT: 209 On SNB, the shader-db results are: total instructions in shared programs: 7173074 -> 7168541 (-0.06%) instructions in affected programs: 119757 -> 115224 (-3.79%) helped: 799 total cycles in shared programs: 98128032 -> 98072938 (-0.06%) cycles in affected programs: 1437104 -> 1382010 (-3.83%) helped: 454 HURT: 237 Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* i965/blorp: Do not emit pma stall on gen9+Topi Pohjolainen2016-04-211-1/+3
| | | | | | | This was left out from the original gen8 upload introduction. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* swr: add PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT to get_paramTim Rowley2016-04-211-0/+1
| | | | Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* i965: automake: remove gratuitous "+" during variable assignmentEmil Velikov2016-04-211-2/+2
| | | | | | | There is not initial assignment, thus appending to it does not work. Fixes: b27c85c4c08 "i965: add build rule for brw_nir_trig_workarounds.c" Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* gbm: add GBM_FORMAT_XBGR8888 format supportRob Herring2016-04-211-0/+7
| | | | | | | | | Add GBM_FORMAT_XBGR8888/__DRI_IMAGE_FORMAT_XBGR8888 format support which is needed for Android. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* st/dri: add 32-bit RGBX/RGBA formatsRob Herring2016-04-212-0/+10
| | | | | | | | Add support for 32-bit RGBX/RGBA formats which are preferred for Android. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* dri/common: add MESA_FORMAT_R8G8B8{A8, X8}_UNORM formats as supported configsRob Herring2016-04-211-0/+10
| | | | | | | | | Add MESA_FORMAT_R8G8B8A8_UNORM and MESA_FORMAT_R8G8B8X8_UNORM formats as these are the preferred formats for Android. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: add build rule for brw_nir_trig_workarounds.c on AndroidRob Herring2016-04-214-2/+49
| | | | | | | | | | | Commit bfd17c76c126 ("i965: Port INTEL_PRECISE_TRIG=1 to NIR.") added a generated file brw_nir_trig_workarounds.c which broke the Android build. Add the necessary makefiles to the Android build. Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Chih-Wei Huang <cwhuang@linux.org.tw> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* glsl: android: add back missing generated glcpp include pathRob Herring2016-04-211-0/+1
| | | | | | | | | | Commit 4db8f15a2576 ("glsl: move the android build scripts a level up") dropped a generated include path for glcpp. Add it back adjusting for the new location. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Chih-Wei Huang <cwhuang@linux.org.tw> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* loader: add a libdrm case for loader_get_device_name_for_fdJonathan Gray2016-04-211-1/+25
| | | | | | | | | Use dev_node_from_fd() with HAVE_LIBDRM to provide an implmentation of loader_get_device_name_for_fd() for non-linux systems that use libdrm but don't have udev or sysfs. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* i965/tiled_memcpy: don't unconditionally use __builtin_bswap32Jonathan Gray2016-04-211-1/+14
| | | | | | | | | | Use the defines Mesa configure sets to indicate presence of the bswap32 builtins. This lets i965 work on OpenBSD again after the changes that were made in 0a5d8d9af42fd77fce1492d55f958da97816961a. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* egl/x11: authenticate before doing chipset id ioctlsJonathan Gray2016-04-211-54/+56
| | | | | | | | | | | | | | For systems without udev or sysfs that use drm ioctls in the loader drm authentication must take place earlier or the loader will fail "MESA-LOADER: failed to get param for i915". Patch from Mark Kettenis. Cc: "11.2 11.1" <mesa-stable@lists.freedesktop.org> Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Jonathan Gray <jsg@jsg.id.au> [Emil Velikov: remove gratuitous white-space] Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
* gallium/radeon: Silence possibly uninitialized variable warning.Bas Nieuwenhuizen2016-04-211-1/+1
| | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: Silence possibly uninitialized variable warning.Bas Nieuwenhuizen2016-04-211-0/+3
| | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: Enable loading into CE RAM.Bas Nieuwenhuizen2016-04-213-0/+14
| | | | | | | | | | We need to enable a bit in the CONTEXT_CONTROL packet for the loads to work. v2: Style issues. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: Use defines for CONTEXT_CONTROL instead of magic values.Bas Nieuwenhuizen2016-04-212-2/+5
| | | | | | | | v2: Use field names provided by Nicolai. v3: Updated to use CONTEXT_CONTROL prefix. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* winsys/amdgpu: fix preamble IB sizeThomas Hindoe Paaboel Andersen2016-04-211-0/+1
| | | | | | | | | The missing break caused the IB size to be overwritten with the size of IB_CONST. This was introduced in: 7201230582e060aa2eb79c825d3188b437ef7bb8 Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* i965/blorp: Reduce the urb size requirement for vertex bufferTopi Pohjolainen2016-04-211-5/+4
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Reduce the size of vertex bufferTopi Pohjolainen2016-04-211-12/+19
| | | | | | | | | | | Previously the vertex buffer consisted of eight floats per vertex of which six where constants. These can be as easily provided by vertex fetcher as it is capable of filling vertex elements with constant one and zero. This reduces the size of the vertex buffer from 3 * 8 * 4 = 96 to 3 * 2 * 4 = 24 bytes. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Do not tricker urb re-configuration unnecessarilyTopi Pohjolainen2016-04-212-1/+5
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Skip re-emitting urb config whenever possibleTopi Pohjolainen2016-04-211-0/+15
| | | | | | | | | | | Otherwise clearing with blorp will regress performance in some synthetic test cases. v2: Used vsize >= 2 instead of vsize > 0, and updated the comment. Review by Ken in one of the earlier patches revealed this. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Prepare to switch from compute pipelineTopi Pohjolainen2016-04-211-0/+2
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Skip uploading state/options not needed for clearsTopi Pohjolainen2016-04-213-17/+37
| | | | | | | | | In case there is no source it means the program does a simple clear or a resolve. In such case there is no need to program sampling state or enable pixel kill in fragment shader. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Re-introduce clear programsTopi Pohjolainen2016-04-215-4/+473
| | | | | | | This partially reverts 2f28a0dc23165123cf1e8b5942acad37878edd8a Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/meta: Move check for srgb into is_color_fast_clear_compatible()Topi Pohjolainen2016-04-212-17/+19
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/meta: Expose check for fast clear compatibilityTopi Pohjolainen2016-04-212-20/+25
| | | | | | | Also add the additional render format check to the same utility. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/meta: Expose fast clear value setupTopi Pohjolainen2016-04-212-5/+10
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/meta: Expose non-fast clear rectangle calculationTopi Pohjolainen2016-04-212-10/+21
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/meta: Expose resolve clear rectangle calculationTopi Pohjolainen2016-04-212-7/+15
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/meta: Expose fast clear rectangle calculationTopi Pohjolainen2016-04-212-19/+33
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Declare input to mcs alignment calculation constantTopi Pohjolainen2016-04-212-2/+2
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Switch the order of render and texture targetsTopi Pohjolainen2016-04-212-1/+5
| | | | | | | | On gen8 color resolving won't work anymore if the target isn't the first entry in the binding table. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
generated by cgit v1.1 at 2024-09-22 18:28:52 +0000