From b214af38b9f5c1422d53f6477483dec984c14952 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 23 Oct 2016 15:29:18 +0200 Subject: gallium/radeon: fix incorrect bpe use in si_set_optimal_micro_tile_mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Oh my god, I wonder what catastrophic issues this was causing on SI. Cc: 13.0 Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Nicolai Hähnle (cherry picked from commit 8a21f52d73936e23a314a288a36782a698c7c1b9) --- src/gallium/drivers/radeon/r600_texture.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 625d091..b57cc92 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -2442,29 +2442,29 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen, switch (rtex->last_msaa_resolve_target_micro_mode) { case 0: /* displayable */ switch (rtex->surface.bpe) { - case 8: + case 1: rtex->surface.tiling_index[0] = 10; break; - case 16: + case 2: rtex->surface.tiling_index[0] = 11; break; - default: /* 32, 64 */ + default: /* 4, 8 */ rtex->surface.tiling_index[0] = 12; break; } break; case 1: /* thin */ switch (rtex->surface.bpe) { - case 8: + case 1: rtex->surface.tiling_index[0] = 14; break; - case 16: + case 2: rtex->surface.tiling_index[0] = 15; break; - case 32: + case 4: rtex->surface.tiling_index[0] = 16; break; - default: /* 64, 128 */ + default: /* 8, 16 */ rtex->surface.tiling_index[0] = 17; break; } -- cgit v1.1