From 40e1f7e09bf1bc9b8ed6f847562bbb7154025420 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 10 Oct 2016 18:51:24 +0200 Subject: radeonsi: use TC write-back instead of full cache invalidation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'src/gallium/drivers/radeonsi/si_state.c') diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 34f3ed7..ad65fc2 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3397,21 +3397,15 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) * L1 isn't used. */ if (sctx->screen->b.chip_class <= CIK) - sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } if (flags & PIPE_BARRIER_FRAMEBUFFER) sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; if (flags & (PIPE_BARRIER_FRAMEBUFFER | - PIPE_BARRIER_INDIRECT_BUFFER)) { - /* Not sure if INV_GLOBAL_L2 is the best thing here. - * - * We need to make sure that TC L1 & L2 are written back to - * memory, because CB fetches don't consider TC, but there's - * no need to invalidate any TC cache lines. */ - sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; - } + PIPE_BARRIER_INDIRECT_BUFFER)) + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) -- cgit v1.1