From 28d0d0c5b4ba9e636b540fafa3b9b2157e848757 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 24 Jun 2016 02:17:38 +0200 Subject: radeonsi: fix fractional odd tessellation spacing for Polaris MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ported from Vulkan (and no source explains why this is needed) Cc: 12.0 Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state_draw.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/gallium/drivers/radeonsi/si_state_draw.c') diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 712e3df..717149b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -438,6 +438,25 @@ static void si_emit_draw_registers(struct si_context *sctx, unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim); unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0; + /* Polaris needs different VTX_REUSE_DEPTH settings depending on + * whether the "fractional odd" tessellation spacing is used. + */ + if (sctx->b.family >= CHIP_POLARIS10) { + struct si_shader_selector *tes = sctx->tes_shader.cso; + unsigned vtx_reuse_depth = 30; + + if (tes && + tes->info.properties[TGSI_PROPERTY_TES_SPACING] == + PIPE_TESS_SPACING_FRACTIONAL_ODD) + vtx_reuse_depth = 14; + + if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) { + radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, + vtx_reuse_depth); + sctx->last_vtx_reuse_depth = vtx_reuse_depth; + } + } + if (sctx->tes_shader.cso) si_emit_derived_tess_state(sctx, info, &num_patches); -- cgit v1.1