From e6893b99adcd6d9fb1bd49067883f66cc5603fe7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Mon, 12 Aug 2013 16:07:08 +0300 Subject: i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IVB/BYT also has the same L3 cacheability control in MOCS as HSW, so let's make use of it. pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most other things show less gains/no regressions, except furmark which loses some 10 points. I didn't have a BYT at hand for testing. v2: Don't check (brw->gen == 7) in gen7 functions. (chadv) Signed-off-by: Ville Syrjälä Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965/brw_draw_upload.c') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 158c9e5..390b4a3 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -659,7 +659,7 @@ static void brw_emit_vertices(struct brw_context *brw) if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; - if (brw->is_haswell) + if (brw->gen == 7) dw0 |= GEN7_MOCS_L3 << 16; OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT)); -- cgit v1.1