From 61d0b9f52c6be4a4a64c30ea3a2a93ef8260c67b Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 26 Jul 2012 11:41:26 -0700 Subject: intel: Make the length for PIPE_CONTROL explicit. PIPE_CONTROL has variable length, depending upon generation and whether we want to do 32-bit or 64-bit data writes. Make it explicit, rather than hiding a length of 4 in the #define for _3DSTATE_PIPE_CONTROL. Generated by s/3DSTATE_PIPE_CONTROL/3DSTATE_PIPE_CONTROL | (4 - 2)/g. This is equivalent since the #define used to have | 2 in it. A grep through the sources shows that all instances have been converted, so it's safe to remove the | 2 from the #define. Signed-off-by: Daniel Vetter Signed-off-by: Kenneth Graunke Reviewed-by: Daniel Vetter Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965/gen6_vs_state.c') diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 3392a9f..c562cc7 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -216,7 +216,7 @@ upload_vs_state(struct brw_context *brw) intel_emit_post_sync_nonzero_flush(intel); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_STATE_CACHE_INVALIDATE); -- cgit v1.1