From f11c1feaf7a92d5109bcc86efaefec3a0193766a Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 4 Nov 2013 16:55:26 -0800 Subject: i965: Introduce an OUT_RELOC64 macro. Broadwell uses 48-bit addresses. The first DWord is the low 32 bits, and the second DWord is the high 16 bits. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.c') diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index c420ab9..59d03f6 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -397,6 +397,30 @@ intel_batchbuffer_emit_reloc(struct brw_context *brw, return true; } +bool +intel_batchbuffer_emit_reloc64(struct brw_context *brw, + drm_intel_bo *buffer, + uint32_t read_domains, uint32_t write_domain, + uint32_t delta) +{ + int ret = drm_intel_bo_emit_reloc(brw->batch.bo, 4*brw->batch.used, + buffer, delta, + read_domains, write_domain); + assert(ret == 0); + (void) ret; + + /* Using the old buffer offset, write in what the right data would be, in + * case the buffer doesn't move and we can short-circuit the relocation + * processing in the kernel + */ + uint64_t offset = buffer->offset64 + delta; + intel_batchbuffer_emit_dword(brw, offset); + intel_batchbuffer_emit_dword(brw, offset >> 32); + + return true; +} + + void intel_batchbuffer_data(struct brw_context *brw, const void *data, GLuint bytes, enum brw_gpu_ring ring) -- cgit v1.1