From 7a0fd3ca1d436591117d451ecee209a4cdb65aef Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 17 Mar 2014 13:53:44 -0700 Subject: i965: Allocate register sets at screen creation, not context creation. Register sets depend on the particular hardware generation, but don't depend on anything in the actual OpenGL context. Computing them is fairly expensive, and they take up a large amount of memory. Putting them in the screen allows us to compute/allocate them once for all contexts, saving both time and space. Improves the performance of a context creation/destruction microbenchmark by about 3x on my Haswell i7-4750HQ. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/intel_screen.h | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'src/mesa/drivers/dri/i965/intel_screen.h') diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h index b08cb68..0969021 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.h +++ b/src/mesa/drivers/dri/i965/intel_screen.h @@ -62,6 +62,44 @@ struct intel_screen */ unsigned program_id; + struct { + struct ra_regs *regs; + + /** + * Array of the ra classes for the unaligned contiguous register + * block sizes used. + */ + int *classes; + + /** + * Mapping for register-allocated objects in *regs to the first + * GRF for that object. + */ + uint8_t *ra_reg_to_grf; + } vec4_reg_set; + + struct { + struct ra_regs *regs; + + /** + * Array of the ra classes for the unaligned contiguous register + * block sizes used, indexed by register size. + */ + int classes[16]; + + /** + * Mapping for register-allocated objects in *regs to the first + * GRF for that object. + */ + uint8_t *ra_reg_to_grf; + + /** + * ra class for the aligned pairs we use for PLN, which doesn't + * appear in *classes. + */ + int aligned_pairs_class; + } wm_reg_sets[2]; + /** * Configuration cache with default values for all contexts */ -- cgit v1.1