From a55da73be46b4576015417b2dff71a719bc8b797 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 6 Mar 2015 00:43:28 -0800 Subject: nir: Try to make sense of the nir_shader_compiler_options code. The code in glsl_to_nir is entirely dead, as we translate from GLSL to NIR at link time, when there isn't a _mesa_glsl_parse_state to pass, so every caller passes NULL. glsl_to_nir seems like the wrong place to try and create the shader compiler options structure anyway - tgsi_to_nir, prog_to_nir, and other translators all would have to duplicate that code. The driver should set this up once with whatever settings it wants, and pass it in. Eric also added a NirOptions field to ctx->Const.ShaderCompilerOptions[] and left a comment saying: "The memory for the options is expected to be kept in a single static copy by the driver." This suggests the plan was to do exactly that. That pointer was not marked const, however, and the dead code used a mix of static structures and ralloced ones. This patch deletes the dead code in glsl_to_nir, instead making it take the shader compiler options as a mandatory argument. It creates an (empty) options struct in the i965 driver, and makes NirOptions point to that. It marks the pointer const so that we can actually do so without generating "discards const qualifier" compiler warnings. Signed-off-by: Kenneth Graunke Acked-by: Jason Ekstrand Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_context.c | 5 +++++ src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 972e458..8141b45 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -68,6 +68,8 @@ #include "tnl/t_pipeline.h" #include "util/ralloc.h" +#include "glsl/nir/nir.h" + /*************************************** * Mesa's Driver Functions ***************************************/ @@ -549,6 +551,8 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxInputComponents = 128; } + static const nir_shader_compiler_options nir_options = {}; + /* We want the GLSL compiler to emit code that uses condition codes */ for (int i = 0; i < MESA_SHADER_STAGES; i++) { ctx->Const.ShaderCompilerOptions[i].MaxIfDepth = brw->gen < 6 ? 16 : UINT_MAX; @@ -562,6 +566,7 @@ brw_initialize_context_constants(struct brw_context *brw) (i == MESA_SHADER_FRAGMENT); ctx->Const.ShaderCompilerOptions[i].EmitNoIndirectUniform = false; ctx->Const.ShaderCompilerOptions[i].LowerClipDistance = true; + ctx->Const.ShaderCompilerOptions[i].NirOptions = &nir_options; } ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = true; diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index a0300aa..e24bf92 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -82,9 +82,12 @@ count_nir_instrs(nir_shader *nir) void fs_visitor::emit_nir_code() { + const nir_shader_compiler_options *options = + ctx->Const.ShaderCompilerOptions[stage].NirOptions; + /* first, lower the GLSL IR shader to NIR */ lower_output_reads(shader->base.ir); - nir_shader *nir = glsl_to_nir(shader->base.ir, NULL, true); + nir_shader *nir = glsl_to_nir(shader->base.ir, true, options); nir_validate_shader(nir); nir_lower_global_vars_to_local(nir); -- cgit v1.1