From d43e16b1638cdadc7fcff2007b106e2a559dae7d Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 5 Nov 2015 16:37:47 -0800 Subject: i965/fs: Use regs_read/written for post-RA scheduling in calculate_deps Previously, we were assuming that everything read/wrote exactly 1 logical GRF (1 in SIMD8 and 2 in SIMD16). This isn't actually true. In particular, the PLN instruction reads 2 logical registers in one of the components. This commit changes post-RA scheduling to use regs_read and regs_written instead so that we add enough dependencies. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92770 Reviewed-by: Matt Turner Reviewed-by: Connor Abbott --- src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index 88c45f7..d21bc67 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -927,7 +927,6 @@ fs_instruction_scheduler::calculate_deps() * granular level. */ schedule_node *last_fixed_grf_write = NULL; - int reg_width = v->dispatch_width / 8; /* The last instruction always needs to still be the last * instruction. Either it's flow control (IF, ELSE, ENDIF, DO, @@ -964,10 +963,7 @@ fs_instruction_scheduler::calculate_deps() (inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE)) { if (post_reg_alloc) { - int size = reg_width; - if (inst->src[i].fixed_hw_reg.vstride == BRW_VERTICAL_STRIDE_0) - size = 1; - for (int r = 0; r < size; r++) + for (int r = 0; r < inst->regs_read(i); r++) add_dep(last_grf_write[inst->src[i].fixed_hw_reg.nr + r], n); } else { add_dep(last_fixed_grf_write, n); @@ -1031,7 +1027,7 @@ fs_instruction_scheduler::calculate_deps() } else if (inst->dst.file == HW_REG && inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) { if (post_reg_alloc) { - for (int r = 0; r < reg_width; r++) + for (int r = 0; r < inst->regs_written; r++) last_grf_write[inst->dst.fixed_hw_reg.nr + r] = n; } else { last_fixed_grf_write = n; @@ -1093,10 +1089,7 @@ fs_instruction_scheduler::calculate_deps() (inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE)) { if (post_reg_alloc) { - int size = reg_width; - if (inst->src[i].fixed_hw_reg.vstride == BRW_VERTICAL_STRIDE_0) - size = 1; - for (int r = 0; r < size; r++) + for (int r = 0; r < inst->regs_read(i); r++) add_dep(n, last_grf_write[inst->src[i].fixed_hw_reg.nr + r], 0); } else { add_dep(n, last_fixed_grf_write, 0); @@ -1159,7 +1152,7 @@ fs_instruction_scheduler::calculate_deps() } else if (inst->dst.file == HW_REG && inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) { if (post_reg_alloc) { - for (int r = 0; r < reg_width; r++) + for (int r = 0; r < inst->regs_written; r++) last_grf_write[inst->dst.fixed_hw_reg.nr + r] = n; } else { last_fixed_grf_write = n; -- cgit v1.1