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authorUpstream <upstream-import@none>1970-01-12 13:46:40 +0000
committerUpstream <upstream-import@none>1970-01-12 13:46:40 +0000
commit413f05aaf54fa08c0ae7e997327a4f4a473c0a8d (patch)
tree642d637ab01ee6c54ca27d1fa96cf92a32df8053 /target-sparc
downloadexternal_qemu-413f05aaf54fa08c0ae7e997327a4f4a473c0a8d.zip
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external/qemu 0.8.2
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/cpu.h277
-rw-r--r--target-sparc/exec.h104
-rw-r--r--target-sparc/fbranch_template.h89
-rw-r--r--target-sparc/fop_template.h81
-rw-r--r--target-sparc/helper.c589
-rw-r--r--target-sparc/op.c1597
-rw-r--r--target-sparc/op_helper.c918
-rw-r--r--target-sparc/op_mem.h114
-rw-r--r--target-sparc/op_template.h48
-rw-r--r--target-sparc/translate.c2845
10 files changed, 6662 insertions, 0 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
new file mode 100644
index 0000000..8cbf0b2
--- /dev/null
+++ b/target-sparc/cpu.h
@@ -0,0 +1,277 @@
+#ifndef CPU_SPARC_H
+#define CPU_SPARC_H
+
+#include "config.h"
+
+#if !defined(TARGET_SPARC64)
+#define TARGET_LONG_BITS 32
+#define TARGET_FPREGS 32
+#define TARGET_PAGE_BITS 12 /* 4k */
+#else
+#define TARGET_LONG_BITS 64
+#define TARGET_FPREGS 64
+#define TARGET_PAGE_BITS 12 /* XXX */
+#endif
+
+#include "cpu-defs.h"
+
+#include "softfloat.h"
+
+#define TARGET_HAS_ICE 1
+
+/*#define EXCP_INTERRUPT 0x100*/
+
+/* trap definitions */
+#ifndef TARGET_SPARC64
+#define TT_TFAULT 0x01
+#define TT_ILL_INSN 0x02
+#define TT_PRIV_INSN 0x03
+#define TT_NFPU_INSN 0x04
+#define TT_WIN_OVF 0x05
+#define TT_WIN_UNF 0x06
+#define TT_FP_EXCP 0x08
+#define TT_DFAULT 0x09
+#define TT_EXTINT 0x10
+#define TT_DIV_ZERO 0x2a
+#define TT_TRAP 0x80
+#else
+#define TT_TFAULT 0x08
+#define TT_TMISS 0x09
+#define TT_ILL_INSN 0x10
+#define TT_PRIV_INSN 0x11
+#define TT_NFPU_INSN 0x20
+#define TT_FP_EXCP 0x21
+#define TT_CLRWIN 0x24
+#define TT_DIV_ZERO 0x28
+#define TT_DFAULT 0x30
+#define TT_DMISS 0x31
+#define TT_DPROT 0x32
+#define TT_PRIV_ACT 0x37
+#define TT_EXTINT 0x40
+#define TT_SPILL 0x80
+#define TT_FILL 0xc0
+#define TT_WOTHER 0x10
+#define TT_TRAP 0x100
+#endif
+
+#define PSR_NEG (1<<23)
+#define PSR_ZERO (1<<22)
+#define PSR_OVF (1<<21)
+#define PSR_CARRY (1<<20)
+#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
+#define PSR_EF (1<<12)
+#define PSR_PIL 0xf00
+#define PSR_S (1<<7)
+#define PSR_PS (1<<6)
+#define PSR_ET (1<<5)
+#define PSR_CWP 0x1f
+
+/* Trap base register */
+#define TBR_BASE_MASK 0xfffff000
+
+#if defined(TARGET_SPARC64)
+#define PS_IG (1<<11)
+#define PS_MG (1<<10)
+#define PS_RED (1<<5)
+#define PS_PEF (1<<4)
+#define PS_AM (1<<3)
+#define PS_PRIV (1<<2)
+#define PS_IE (1<<1)
+#define PS_AG (1<<0)
+
+#define FPRS_FEF (1<<2)
+#endif
+
+/* Fcc */
+#define FSR_RD1 (1<<31)
+#define FSR_RD0 (1<<30)
+#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
+#define FSR_RD_NEAREST 0
+#define FSR_RD_ZERO FSR_RD0
+#define FSR_RD_POS FSR_RD1
+#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
+
+#define FSR_NVM (1<<27)
+#define FSR_OFM (1<<26)
+#define FSR_UFM (1<<25)
+#define FSR_DZM (1<<24)
+#define FSR_NXM (1<<23)
+#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
+
+#define FSR_NVA (1<<9)
+#define FSR_OFA (1<<8)
+#define FSR_UFA (1<<7)
+#define FSR_DZA (1<<6)
+#define FSR_NXA (1<<5)
+#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
+
+#define FSR_NVC (1<<4)
+#define FSR_OFC (1<<3)
+#define FSR_UFC (1<<2)
+#define FSR_DZC (1<<1)
+#define FSR_NXC (1<<0)
+#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
+
+#define FSR_FTT2 (1<<16)
+#define FSR_FTT1 (1<<15)
+#define FSR_FTT0 (1<<14)
+#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+#define FSR_FTT_IEEE_EXCP (1 << 14)
+#define FSR_FTT_UNIMPFPOP (3 << 14)
+#define FSR_FTT_INVAL_FPR (6 << 14)
+
+#define FSR_FCC1 (1<<11)
+#define FSR_FCC0 (1<<10)
+
+/* MMU */
+#define MMU_E (1<<0)
+#define MMU_NF (1<<1)
+
+#define PTE_ENTRYTYPE_MASK 3
+#define PTE_ACCESS_MASK 0x1c
+#define PTE_ACCESS_SHIFT 2
+#define PTE_PPN_SHIFT 7
+#define PTE_ADDR_MASK 0xffffff00
+
+#define PG_ACCESSED_BIT 5
+#define PG_MODIFIED_BIT 6
+#define PG_CACHE_BIT 7
+
+#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
+#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
+#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
+
+/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
+#define NWINDOWS 8
+
+typedef struct CPUSPARCState {
+ target_ulong gregs[8]; /* general registers */
+ target_ulong *regwptr; /* pointer to current register window */
+ float32 fpr[TARGET_FPREGS]; /* floating point registers */
+ target_ulong pc; /* program counter */
+ target_ulong npc; /* next program counter */
+ target_ulong y; /* multiply/divide register */
+ uint32_t psr; /* processor state register */
+ target_ulong fsr; /* FPU state register */
+ uint32_t cwp; /* index of current register window (extracted
+ from PSR) */
+ uint32_t wim; /* window invalid mask */
+ target_ulong tbr; /* trap base register */
+ int psrs; /* supervisor mode (extracted from PSR) */
+ int psrps; /* previous supervisor mode */
+ int psret; /* enable traps */
+ uint32_t psrpil; /* interrupt level */
+ int psref; /* enable fpu */
+ jmp_buf jmp_env;
+ int user_mode_only;
+ int exception_index;
+ int interrupt_index;
+ int interrupt_request;
+ int halted;
+ /* NOTE: we allow 8 more registers to handle wrapping */
+ target_ulong regbase[NWINDOWS * 16 + 8];
+
+ CPU_COMMON
+
+ /* MMU regs */
+#if defined(TARGET_SPARC64)
+ uint64_t lsu;
+#define DMMU_E 0x8
+#define IMMU_E 0x4
+ uint64_t immuregs[16];
+ uint64_t dmmuregs[16];
+ uint64_t itlb_tag[64];
+ uint64_t itlb_tte[64];
+ uint64_t dtlb_tag[64];
+ uint64_t dtlb_tte[64];
+#else
+ uint32_t mmuregs[16];
+#endif
+ /* temporary float registers */
+ float32 ft0, ft1;
+ float64 dt0, dt1;
+ float_status fp_status;
+#if defined(TARGET_SPARC64)
+#define MAXTL 4
+ uint64_t t0, t1, t2;
+ uint64_t tpc[MAXTL];
+ uint64_t tnpc[MAXTL];
+ uint64_t tstate[MAXTL];
+ uint32_t tt[MAXTL];
+ uint32_t xcc; /* Extended integer condition codes */
+ uint32_t asi;
+ uint32_t pstate;
+ uint32_t tl;
+ uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
+ uint64_t agregs[8]; /* alternate general registers */
+ uint64_t bgregs[8]; /* backup for normal global registers */
+ uint64_t igregs[8]; /* interrupt general registers */
+ uint64_t mgregs[8]; /* mmu general registers */
+ uint64_t version;
+ uint64_t fprs;
+ uint64_t tick_cmpr, stick_cmpr;
+ uint64_t gsr;
+#endif
+#if !defined(TARGET_SPARC64) && !defined(reg_T2)
+ target_ulong t2;
+#endif
+} CPUSPARCState;
+#if defined(TARGET_SPARC64)
+#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
+#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
+ env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
+ } while (0)
+#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
+#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
+ env->fsr = _tmp & 0x3fcfc1c3ffULL; \
+ } while (0)
+// Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
+#define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \
+ (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
+#else
+#define GET_FSR32(env) (env->fsr)
+#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
+ env->fsr = _tmp & 0xcfc1ffff; \
+ } while (0)
+#endif
+
+CPUSPARCState *cpu_sparc_init(void);
+int cpu_sparc_exec(CPUSPARCState *s);
+int cpu_sparc_close(CPUSPARCState *s);
+
+/* Fake impl 0, version 4 */
+#define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \
+ (env->psref? PSR_EF : 0) | \
+ (env->psrpil << 8) | \
+ (env->psrs? PSR_S : 0) | \
+ (env->psrps? PSR_PS : 0) | \
+ (env->psret? PSR_ET : 0) | env->cwp)
+
+#ifndef NO_CPU_IO_DEFS
+void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
+#endif
+
+#define PUT_PSR(env, val) do { int _tmp = val; \
+ env->psr = _tmp & PSR_ICC; \
+ env->psref = (_tmp & PSR_EF)? 1 : 0; \
+ env->psrpil = (_tmp & PSR_PIL) >> 8; \
+ env->psrs = (_tmp & PSR_S)? 1 : 0; \
+ env->psrps = (_tmp & PSR_PS)? 1 : 0; \
+ env->psret = (_tmp & PSR_ET)? 1 : 0; \
+ cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
+ } while (0)
+
+#ifdef TARGET_SPARC64
+#define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
+#define PUT_CCR(env, val) do { int _tmp = val; \
+ env->xcc = _tmp >> 4; \
+ env->psr = (_tmp & 0xf) << 20; \
+ } while (0)
+#endif
+
+struct siginfo;
+int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
+
+#include "cpu-all.h"
+
+#endif
diff --git a/target-sparc/exec.h b/target-sparc/exec.h
new file mode 100644
index 0000000..1b67ef4
--- /dev/null
+++ b/target-sparc/exec.h
@@ -0,0 +1,104 @@
+#ifndef EXEC_SPARC_H
+#define EXEC_SPARC_H 1
+#include "dyngen-exec.h"
+#include "config.h"
+
+register struct CPUSPARCState *env asm(AREG0);
+#ifdef TARGET_SPARC64
+#define T0 (env->t0)
+#define T1 (env->t1)
+#define T2 (env->t2)
+#define REGWPTR env->regwptr
+#else
+register uint32_t T0 asm(AREG1);
+register uint32_t T1 asm(AREG2);
+
+#undef REG_REGWPTR // Broken
+#ifdef REG_REGWPTR
+register uint32_t *REGWPTR asm(AREG3);
+#define reg_REGWPTR
+
+#ifdef AREG4
+register uint32_t T2 asm(AREG4);
+#define reg_T2
+#else
+#define T2 (env->t2)
+#endif
+
+#else
+#define REGWPTR env->regwptr
+register uint32_t T2 asm(AREG3);
+#define reg_T2
+#endif
+#endif
+
+#define FT0 (env->ft0)
+#define FT1 (env->ft1)
+#define DT0 (env->dt0)
+#define DT1 (env->dt1)
+
+#include "cpu.h"
+#include "exec-all.h"
+
+void cpu_lock(void);
+void cpu_unlock(void);
+void cpu_loop_exit(void);
+void helper_flush(target_ulong addr);
+void helper_ld_asi(int asi, int size, int sign);
+void helper_st_asi(int asi, int size, int sign);
+void helper_rett(void);
+void helper_ldfsr(void);
+void set_cwp(int new_cwp);
+void do_fitos(void);
+void do_fitod(void);
+void do_fabss(void);
+void do_fsqrts(void);
+void do_fsqrtd(void);
+void do_fcmps(void);
+void do_fcmpd(void);
+#ifdef TARGET_SPARC64
+void do_fabsd(void);
+void do_fcmps_fcc1(void);
+void do_fcmpd_fcc1(void);
+void do_fcmps_fcc2(void);
+void do_fcmpd_fcc2(void);
+void do_fcmps_fcc3(void);
+void do_fcmpd_fcc3(void);
+void do_popc();
+void do_wrpstate();
+void do_done();
+void do_retry();
+#endif
+void do_ldd_kernel(target_ulong addr);
+void do_ldd_user(target_ulong addr);
+void do_ldd_raw(target_ulong addr);
+void do_interrupt(int intno);
+void raise_exception(int tt);
+void memcpy32(target_ulong *dst, const target_ulong *src);
+target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev);
+void dump_mmu(CPUState *env);
+void helper_debug();
+void do_wrpsr();
+void do_rdpsr();
+
+/* XXX: move that to a generic header */
+#if !defined(CONFIG_USER_ONLY)
+#include "softmmu_exec.h"
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+static inline void env_to_regs(void)
+{
+#if defined(reg_REGWPTR)
+ REGWPTR = env->regbase + (env->cwp * 16);
+ env->regwptr = REGWPTR;
+#endif
+}
+
+static inline void regs_to_env(void)
+{
+}
+
+int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu);
+
+#endif
diff --git a/target-sparc/fbranch_template.h b/target-sparc/fbranch_template.h
new file mode 100644
index 0000000..e6bf9a2
--- /dev/null
+++ b/target-sparc/fbranch_template.h
@@ -0,0 +1,89 @@
+/* FCC1:FCC0: 0 =, 1 <, 2 >, 3 u */
+
+void OPPROTO glue(op_eval_fbne, FCC)(void)
+{
+// !0
+ T2 = FFLAG_SET(FSR_FCC0) | FFLAG_SET(FSR_FCC1); /* L or G or U */
+}
+
+void OPPROTO glue(op_eval_fblg, FCC)(void)
+{
+// 1 or 2
+ T2 = FFLAG_SET(FSR_FCC0) ^ FFLAG_SET(FSR_FCC1);
+}
+
+void OPPROTO glue(op_eval_fbul, FCC)(void)
+{
+// 1 or 3
+ T2 = FFLAG_SET(FSR_FCC0);
+}
+
+void OPPROTO glue(op_eval_fbl, FCC)(void)
+{
+// 1
+ T2 = FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1);
+}
+
+void OPPROTO glue(op_eval_fbug, FCC)(void)
+{
+// 2 or 3
+ T2 = FFLAG_SET(FSR_FCC1);
+}
+
+void OPPROTO glue(op_eval_fbg, FCC)(void)
+{
+// 2
+ T2 = !FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1);
+}
+
+void OPPROTO glue(op_eval_fbu, FCC)(void)
+{
+// 3
+ T2 = FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1);
+}
+
+void OPPROTO glue(op_eval_fbe, FCC)(void)
+{
+// 0
+ T2 = !FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1);
+}
+
+void OPPROTO glue(op_eval_fbue, FCC)(void)
+{
+// 0 or 3
+ T2 = !(FFLAG_SET(FSR_FCC1) ^ FFLAG_SET(FSR_FCC0));
+ FORCE_RET();
+}
+
+void OPPROTO glue(op_eval_fbge, FCC)(void)
+{
+// 0 or 2
+ T2 = !FFLAG_SET(FSR_FCC0);
+}
+
+void OPPROTO glue(op_eval_fbuge, FCC)(void)
+{
+// !1
+ T2 = !(FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1));
+}
+
+void OPPROTO glue(op_eval_fble, FCC)(void)
+{
+// 0 or 1
+ T2 = !FFLAG_SET(FSR_FCC1);
+}
+
+void OPPROTO glue(op_eval_fbule, FCC)(void)
+{
+// !2
+ T2 = !(!FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1));
+}
+
+void OPPROTO glue(op_eval_fbo, FCC)(void)
+{
+// !3
+ T2 = !(FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1));
+}
+
+#undef FCC
+#undef FFLAG_SET
diff --git a/target-sparc/fop_template.h b/target-sparc/fop_template.h
new file mode 100644
index 0000000..74988f7
--- /dev/null
+++ b/target-sparc/fop_template.h
@@ -0,0 +1,81 @@
+/*
+ * SPARC micro operations (templates for various register related
+ * operations)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/* floating point registers moves */
+void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void)
+{
+ FT0 = REG;
+}
+
+void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void)
+{
+ REG = FT0;
+}
+
+void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void)
+{
+ FT1 = REG;
+}
+
+void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void)
+{
+ REG = FT1;
+}
+
+/* double floating point registers moves */
+void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void)
+{
+ CPU_DoubleU u;
+ uint32_t *p = (uint32_t *)&REG;
+ u.l.lower = *(p +1);
+ u.l.upper = *p;
+ DT0 = u.d;
+}
+
+void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void)
+{
+ CPU_DoubleU u;
+ uint32_t *p = (uint32_t *)&REG;
+ u.d = DT0;
+ *(p +1) = u.l.lower;
+ *p = u.l.upper;
+}
+
+void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void)
+{
+ CPU_DoubleU u;
+ uint32_t *p = (uint32_t *)&REG;
+ u.l.lower = *(p +1);
+ u.l.upper = *p;
+ DT1 = u.d;
+}
+
+void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void)
+{
+ CPU_DoubleU u;
+ uint32_t *p = (uint32_t *)&REG;
+ u.d = DT1;
+ *(p +1) = u.l.lower;
+ *p = u.l.upper;
+}
+
+#undef REG
+#undef REGNAME
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
new file mode 100644
index 0000000..8f12667
--- /dev/null
+++ b/target-sparc/helper.c
@@ -0,0 +1,589 @@
+/*
+ * sparc helpers
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <signal.h>
+#include <assert.h>
+
+#include "cpu.h"
+#include "exec-all.h"
+
+//#define DEBUG_MMU
+
+/* Sparc MMU emulation */
+
+/* thread support */
+
+spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
+
+void cpu_lock(void)
+{
+ spin_lock(&global_cpu_lock);
+}
+
+void cpu_unlock(void)
+{
+ spin_unlock(&global_cpu_lock);
+}
+
+#if defined(CONFIG_USER_ONLY)
+
+int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu)
+{
+ if (rw & 2)
+ env->exception_index = TT_TFAULT;
+ else
+ env->exception_index = TT_DFAULT;
+ return 1;
+}
+
+#else
+
+#ifndef TARGET_SPARC64
+/*
+ * Sparc V8 Reference MMU (SRMMU)
+ */
+static const int access_table[8][8] = {
+ { 0, 0, 0, 0, 2, 0, 3, 3 },
+ { 0, 0, 0, 0, 2, 0, 0, 0 },
+ { 2, 2, 0, 0, 0, 2, 3, 3 },
+ { 2, 2, 0, 0, 0, 2, 0, 0 },
+ { 2, 0, 2, 0, 2, 2, 3, 3 },
+ { 2, 0, 2, 0, 2, 0, 2, 0 },
+ { 2, 2, 2, 0, 2, 2, 3, 3 },
+ { 2, 2, 2, 0, 2, 2, 2, 0 }
+};
+
+static const int perm_table[2][8] = {
+ {
+ PAGE_READ,
+ PAGE_READ | PAGE_WRITE,
+ PAGE_READ | PAGE_EXEC,
+ PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+ PAGE_EXEC,
+ PAGE_READ | PAGE_WRITE,
+ PAGE_READ | PAGE_EXEC,
+ PAGE_READ | PAGE_WRITE | PAGE_EXEC
+ },
+ {
+ PAGE_READ,
+ PAGE_READ | PAGE_WRITE,
+ PAGE_READ | PAGE_EXEC,
+ PAGE_READ | PAGE_WRITE | PAGE_EXEC,
+ PAGE_EXEC,
+ PAGE_READ,
+ 0,
+ 0,
+ }
+};
+
+int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user)
+{
+ int access_perms = 0;
+ target_phys_addr_t pde_ptr;
+ uint32_t pde;
+ target_ulong virt_addr;
+ int error_code = 0, is_dirty;
+ unsigned long page_offset;
+
+ virt_addr = address & TARGET_PAGE_MASK;
+ if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
+ *physical = address;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return 0;
+ }
+
+ *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
+ *physical = 0xfffff000;
+
+ /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
+ /* Context base + context number */
+ pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
+ pde = ldl_phys(pde_ptr);
+
+ /* Ctx pde */
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ return 1 << 2;
+ case 2: /* L0 PTE, maybe should not happen? */
+ case 3: /* Reserved */
+ return 4 << 2;
+ case 1: /* L0 PDE */
+ pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
+ pde = ldl_phys(pde_ptr);
+
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ return (1 << 8) | (1 << 2);
+ case 3: /* Reserved */
+ return (1 << 8) | (4 << 2);
+ case 1: /* L1 PDE */
+ pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
+ pde = ldl_phys(pde_ptr);
+
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ return (2 << 8) | (1 << 2);
+ case 3: /* Reserved */
+ return (2 << 8) | (4 << 2);
+ case 1: /* L2 PDE */
+ pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
+ pde = ldl_phys(pde_ptr);
+
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ return (3 << 8) | (1 << 2);
+ case 1: /* PDE, should not happen */
+ case 3: /* Reserved */
+ return (3 << 8) | (4 << 2);
+ case 2: /* L3 PTE */
+ virt_addr = address & TARGET_PAGE_MASK;
+ page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
+ }
+ break;
+ case 2: /* L2 PTE */
+ virt_addr = address & ~0x3ffff;
+ page_offset = address & 0x3ffff;
+ }
+ break;
+ case 2: /* L1 PTE */
+ virt_addr = address & ~0xffffff;
+ page_offset = address & 0xffffff;
+ }
+ }
+
+ /* update page modified and dirty bits */
+ is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
+ if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
+ pde |= PG_ACCESSED_MASK;
+ if (is_dirty)
+ pde |= PG_MODIFIED_MASK;
+ stl_phys_notdirty(pde_ptr, pde);
+ }
+ /* check access */
+ access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
+ error_code = access_table[*access_index][access_perms];
+ if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
+ return error_code;
+
+ /* the page can be put in the TLB */
+ *prot = perm_table[is_user][access_perms];
+ if (!(pde & PG_MODIFIED_MASK)) {
+ /* only set write access if already dirty... otherwise wait
+ for dirty access */
+ *prot &= ~PAGE_WRITE;
+ }
+
+ /* Even if large ptes, we map only one 4KB page in the cache to
+ avoid filling it too fast */
+ *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
+ return error_code;
+}
+
+/* Perform address translation */
+int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu)
+{
+ target_phys_addr_t paddr;
+ unsigned long vaddr;
+ int error_code = 0, prot, ret = 0, access_index;
+
+ error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
+ if (error_code == 0) {
+ vaddr = address & TARGET_PAGE_MASK;
+ paddr &= TARGET_PAGE_MASK;
+#ifdef DEBUG_MMU
+ printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
+#endif
+ ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
+ return ret;
+ }
+
+ if (env->mmuregs[3]) /* Fault status register */
+ env->mmuregs[3] = 1; /* overflow (not read before another fault) */
+ env->mmuregs[3] |= (access_index << 5) | error_code | 2;
+ env->mmuregs[4] = address; /* Fault address register */
+
+ if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
+ // No fault mode: if a mapping is available, just override
+ // permissions. If no mapping is available, redirect accesses to
+ // neverland. Fake/overridden mappings will be flushed when
+ // switching to normal mode.
+ vaddr = address & TARGET_PAGE_MASK;
+ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
+ return ret;
+ } else {
+ if (rw & 2)
+ env->exception_index = TT_TFAULT;
+ else
+ env->exception_index = TT_DFAULT;
+ return 1;
+ }
+}
+
+target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
+{
+ target_phys_addr_t pde_ptr;
+ uint32_t pde;
+
+ /* Context base + context number */
+ pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
+ pde = ldl_phys(pde_ptr);
+
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ case 2: /* PTE, maybe should not happen? */
+ case 3: /* Reserved */
+ return 0;
+ case 1: /* L1 PDE */
+ if (mmulev == 3)
+ return pde;
+ pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
+ pde = ldl_phys(pde_ptr);
+
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ case 3: /* Reserved */
+ return 0;
+ case 2: /* L1 PTE */
+ return pde;
+ case 1: /* L2 PDE */
+ if (mmulev == 2)
+ return pde;
+ pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
+ pde = ldl_phys(pde_ptr);
+
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ case 3: /* Reserved */
+ return 0;
+ case 2: /* L2 PTE */
+ return pde;
+ case 1: /* L3 PDE */
+ if (mmulev == 1)
+ return pde;
+ pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
+ pde = ldl_phys(pde_ptr);
+
+ switch (pde & PTE_ENTRYTYPE_MASK) {
+ default:
+ case 0: /* Invalid */
+ case 1: /* PDE, should not happen */
+ case 3: /* Reserved */
+ return 0;
+ case 2: /* L3 PTE */
+ return pde;
+ }
+ }
+ }
+ }
+ return 0;
+}
+
+#ifdef DEBUG_MMU
+void dump_mmu(CPUState *env)
+{
+ target_ulong va, va1, va2;
+ unsigned int n, m, o;
+ target_phys_addr_t pde_ptr, pa;
+ uint32_t pde;
+
+ printf("MMU dump:\n");
+ pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
+ pde = ldl_phys(pde_ptr);
+ printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
+ for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
+ pde_ptr = mmu_probe(env, va, 2);
+ if (pde_ptr) {
+ pa = cpu_get_phys_page_debug(env, va);
+ printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
+ for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
+ pde_ptr = mmu_probe(env, va1, 1);
+ if (pde_ptr) {
+ pa = cpu_get_phys_page_debug(env, va1);
+ printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
+ for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
+ pde_ptr = mmu_probe(env, va2, 0);
+ if (pde_ptr) {
+ pa = cpu_get_phys_page_debug(env, va2);
+ printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
+ }
+ }
+ }
+ }
+ }
+ }
+ printf("MMU dump ends\n");
+}
+#endif /* DEBUG_MMU */
+
+#else /* !TARGET_SPARC64 */
+/*
+ * UltraSparc IIi I/DMMUs
+ */
+static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user)
+{
+ target_ulong mask;
+ unsigned int i;
+
+ if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
+ *physical = address;
+ *prot = PAGE_READ | PAGE_WRITE;
+ return 0;
+ }
+
+ for (i = 0; i < 64; i++) {
+ switch ((env->dtlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0: // 8k
+ mask = 0xffffffffffffe000ULL;
+ break;
+ case 0x1: // 64k
+ mask = 0xffffffffffff0000ULL;
+ break;
+ case 0x2: // 512k
+ mask = 0xfffffffffff80000ULL;
+ break;
+ case 0x3: // 4M
+ mask = 0xffffffffffc00000ULL;
+ break;
+ }
+ // ctx match, vaddr match?
+ if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
+ (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
+ // valid, access ok?
+ if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
+ ((env->dtlb_tte[i] & 0x4) && is_user) ||
+ (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
+ if (env->dmmuregs[3]) /* Fault status register */
+ env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
+ env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
+ env->dmmuregs[4] = address; /* Fault address register */
+ env->exception_index = TT_DFAULT;
+#ifdef DEBUG_MMU
+ printf("DFAULT at 0x%" PRIx64 "\n", address);
+#endif
+ return 1;
+ }
+ *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
+ *prot = PAGE_READ;
+ if (env->dtlb_tte[i] & 0x2)
+ *prot |= PAGE_WRITE;
+ return 0;
+ }
+ }
+#ifdef DEBUG_MMU
+ printf("DMISS at 0x%" PRIx64 "\n", address);
+#endif
+ env->exception_index = TT_DMISS;
+ return 1;
+}
+
+static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user)
+{
+ target_ulong mask;
+ unsigned int i;
+
+ if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
+ *physical = address;
+ *prot = PAGE_EXEC;
+ return 0;
+ }
+
+ for (i = 0; i < 64; i++) {
+ switch ((env->itlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0: // 8k
+ mask = 0xffffffffffffe000ULL;
+ break;
+ case 0x1: // 64k
+ mask = 0xffffffffffff0000ULL;
+ break;
+ case 0x2: // 512k
+ mask = 0xfffffffffff80000ULL;
+ break;
+ case 0x3: // 4M
+ mask = 0xffffffffffc00000ULL;
+ break;
+ }
+ // ctx match, vaddr match?
+ if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
+ (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
+ // valid, access ok?
+ if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
+ ((env->itlb_tte[i] & 0x4) && is_user)) {
+ if (env->immuregs[3]) /* Fault status register */
+ env->immuregs[3] = 2; /* overflow (not read before another fault) */
+ env->immuregs[3] |= (is_user << 3) | 1;
+ env->exception_index = TT_TFAULT;
+#ifdef DEBUG_MMU
+ printf("TFAULT at 0x%" PRIx64 "\n", address);
+#endif
+ return 1;
+ }
+ *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
+ *prot = PAGE_EXEC;
+ return 0;
+ }
+ }
+#ifdef DEBUG_MMU
+ printf("TMISS at 0x%" PRIx64 "\n", address);
+#endif
+ env->exception_index = TT_TMISS;
+ return 1;
+}
+
+int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user)
+{
+ if (rw == 2)
+ return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
+ else
+ return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
+}
+
+/* Perform address translation */
+int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu)
+{
+ target_ulong virt_addr, vaddr;
+ target_phys_addr_t paddr;
+ int error_code = 0, prot, ret = 0, access_index;
+
+ error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
+ if (error_code == 0) {
+ virt_addr = address & TARGET_PAGE_MASK;
+ vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
+#ifdef DEBUG_MMU
+ printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
+#endif
+ ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
+ return ret;
+ }
+ // XXX
+ return 1;
+}
+
+#ifdef DEBUG_MMU
+void dump_mmu(CPUState *env)
+{
+ unsigned int i;
+ const char *mask;
+
+ printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
+ if ((env->lsu & DMMU_E) == 0) {
+ printf("DMMU disabled\n");
+ } else {
+ printf("DMMU dump:\n");
+ for (i = 0; i < 64; i++) {
+ switch ((env->dtlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0:
+ mask = " 8k";
+ break;
+ case 0x1:
+ mask = " 64k";
+ break;
+ case 0x2:
+ mask = "512k";
+ break;
+ case 0x3:
+ mask = " 4M";
+ break;
+ }
+ if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
+ printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
+ env->dtlb_tag[i] & ~0x1fffULL,
+ env->dtlb_tte[i] & 0x1ffffffe000ULL,
+ mask,
+ env->dtlb_tte[i] & 0x4? "priv": "user",
+ env->dtlb_tte[i] & 0x2? "RW": "RO",
+ env->dtlb_tte[i] & 0x40? "locked": "unlocked",
+ env->dtlb_tag[i] & 0x1fffULL);
+ }
+ }
+ }
+ if ((env->lsu & IMMU_E) == 0) {
+ printf("IMMU disabled\n");
+ } else {
+ printf("IMMU dump:\n");
+ for (i = 0; i < 64; i++) {
+ switch ((env->itlb_tte[i] >> 61) & 3) {
+ default:
+ case 0x0:
+ mask = " 8k";
+ break;
+ case 0x1:
+ mask = " 64k";
+ break;
+ case 0x2:
+ mask = "512k";
+ break;
+ case 0x3:
+ mask = " 4M";
+ break;
+ }
+ if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
+ printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
+ env->itlb_tag[i] & ~0x1fffULL,
+ env->itlb_tte[i] & 0x1ffffffe000ULL,
+ mask,
+ env->itlb_tte[i] & 0x4? "priv": "user",
+ env->itlb_tte[i] & 0x40? "locked": "unlocked",
+ env->itlb_tag[i] & 0x1fffULL);
+ }
+ }
+ }
+}
+#endif /* DEBUG_MMU */
+
+#endif /* TARGET_SPARC64 */
+#endif /* !CONFIG_USER_ONLY */
+
+void memcpy32(target_ulong *dst, const target_ulong *src)
+{
+ dst[0] = src[0];
+ dst[1] = src[1];
+ dst[2] = src[2];
+ dst[3] = src[3];
+ dst[4] = src[4];
+ dst[5] = src[5];
+ dst[6] = src[6];
+ dst[7] = src[7];
+}
diff --git a/target-sparc/op.c b/target-sparc/op.c
new file mode 100644
index 0000000..7ea209e
--- /dev/null
+++ b/target-sparc/op.c
@@ -0,0 +1,1597 @@
+/*
+ SPARC micro operations
+
+ Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include "exec.h"
+
+ /*XXX*/
+#define REGNAME g0
+#define REG (env->gregs[0])
+#include "op_template.h"
+#define REGNAME g1
+#define REG (env->gregs[1])
+#include "op_template.h"
+#define REGNAME g2
+#define REG (env->gregs[2])
+#include "op_template.h"
+#define REGNAME g3
+#define REG (env->gregs[3])
+#include "op_template.h"
+#define REGNAME g4
+#define REG (env->gregs[4])
+#include "op_template.h"
+#define REGNAME g5
+#define REG (env->gregs[5])
+#include "op_template.h"
+#define REGNAME g6
+#define REG (env->gregs[6])
+#include "op_template.h"
+#define REGNAME g7
+#define REG (env->gregs[7])
+#include "op_template.h"
+#define REGNAME i0
+#define REG (REGWPTR[16])
+#include "op_template.h"
+#define REGNAME i1
+#define REG (REGWPTR[17])
+#include "op_template.h"
+#define REGNAME i2
+#define REG (REGWPTR[18])
+#include "op_template.h"
+#define REGNAME i3
+#define REG (REGWPTR[19])
+#include "op_template.h"
+#define REGNAME i4
+#define REG (REGWPTR[20])
+#include "op_template.h"
+#define REGNAME i5
+#define REG (REGWPTR[21])
+#include "op_template.h"
+#define REGNAME i6
+#define REG (REGWPTR[22])
+#include "op_template.h"
+#define REGNAME i7
+#define REG (REGWPTR[23])
+#include "op_template.h"
+#define REGNAME l0
+#define REG (REGWPTR[8])
+#include "op_template.h"
+#define REGNAME l1
+#define REG (REGWPTR[9])
+#include "op_template.h"
+#define REGNAME l2
+#define REG (REGWPTR[10])
+#include "op_template.h"
+#define REGNAME l3
+#define REG (REGWPTR[11])
+#include "op_template.h"
+#define REGNAME l4
+#define REG (REGWPTR[12])
+#include "op_template.h"
+#define REGNAME l5
+#define REG (REGWPTR[13])
+#include "op_template.h"
+#define REGNAME l6
+#define REG (REGWPTR[14])
+#include "op_template.h"
+#define REGNAME l7
+#define REG (REGWPTR[15])
+#include "op_template.h"
+#define REGNAME o0
+#define REG (REGWPTR[0])
+#include "op_template.h"
+#define REGNAME o1
+#define REG (REGWPTR[1])
+#include "op_template.h"
+#define REGNAME o2
+#define REG (REGWPTR[2])
+#include "op_template.h"
+#define REGNAME o3
+#define REG (REGWPTR[3])
+#include "op_template.h"
+#define REGNAME o4
+#define REG (REGWPTR[4])
+#include "op_template.h"
+#define REGNAME o5
+#define REG (REGWPTR[5])
+#include "op_template.h"
+#define REGNAME o6
+#define REG (REGWPTR[6])
+#include "op_template.h"
+#define REGNAME o7
+#define REG (REGWPTR[7])
+#include "op_template.h"
+
+#define REGNAME f0
+#define REG (env->fpr[0])
+#include "fop_template.h"
+#define REGNAME f1
+#define REG (env->fpr[1])
+#include "fop_template.h"
+#define REGNAME f2
+#define REG (env->fpr[2])
+#include "fop_template.h"
+#define REGNAME f3
+#define REG (env->fpr[3])
+#include "fop_template.h"
+#define REGNAME f4
+#define REG (env->fpr[4])
+#include "fop_template.h"
+#define REGNAME f5
+#define REG (env->fpr[5])
+#include "fop_template.h"
+#define REGNAME f6
+#define REG (env->fpr[6])
+#include "fop_template.h"
+#define REGNAME f7
+#define REG (env->fpr[7])
+#include "fop_template.h"
+#define REGNAME f8
+#define REG (env->fpr[8])
+#include "fop_template.h"
+#define REGNAME f9
+#define REG (env->fpr[9])
+#include "fop_template.h"
+#define REGNAME f10
+#define REG (env->fpr[10])
+#include "fop_template.h"
+#define REGNAME f11
+#define REG (env->fpr[11])
+#include "fop_template.h"
+#define REGNAME f12
+#define REG (env->fpr[12])
+#include "fop_template.h"
+#define REGNAME f13
+#define REG (env->fpr[13])
+#include "fop_template.h"
+#define REGNAME f14
+#define REG (env->fpr[14])
+#include "fop_template.h"
+#define REGNAME f15
+#define REG (env->fpr[15])
+#include "fop_template.h"
+#define REGNAME f16
+#define REG (env->fpr[16])
+#include "fop_template.h"
+#define REGNAME f17
+#define REG (env->fpr[17])
+#include "fop_template.h"
+#define REGNAME f18
+#define REG (env->fpr[18])
+#include "fop_template.h"
+#define REGNAME f19
+#define REG (env->fpr[19])
+#include "fop_template.h"
+#define REGNAME f20
+#define REG (env->fpr[20])
+#include "fop_template.h"
+#define REGNAME f21
+#define REG (env->fpr[21])
+#include "fop_template.h"
+#define REGNAME f22
+#define REG (env->fpr[22])
+#include "fop_template.h"
+#define REGNAME f23
+#define REG (env->fpr[23])
+#include "fop_template.h"
+#define REGNAME f24
+#define REG (env->fpr[24])
+#include "fop_template.h"
+#define REGNAME f25
+#define REG (env->fpr[25])
+#include "fop_template.h"
+#define REGNAME f26
+#define REG (env->fpr[26])
+#include "fop_template.h"
+#define REGNAME f27
+#define REG (env->fpr[27])
+#include "fop_template.h"
+#define REGNAME f28
+#define REG (env->fpr[28])
+#include "fop_template.h"
+#define REGNAME f29
+#define REG (env->fpr[29])
+#include "fop_template.h"
+#define REGNAME f30
+#define REG (env->fpr[30])
+#include "fop_template.h"
+#define REGNAME f31
+#define REG (env->fpr[31])
+#include "fop_template.h"
+
+#ifdef TARGET_SPARC64
+#define REGNAME f32
+#define REG (env->fpr[32])
+#include "fop_template.h"
+#define REGNAME f34
+#define REG (env->fpr[34])
+#include "fop_template.h"
+#define REGNAME f36
+#define REG (env->fpr[36])
+#include "fop_template.h"
+#define REGNAME f38
+#define REG (env->fpr[38])
+#include "fop_template.h"
+#define REGNAME f40
+#define REG (env->fpr[40])
+#include "fop_template.h"
+#define REGNAME f42
+#define REG (env->fpr[42])
+#include "fop_template.h"
+#define REGNAME f44
+#define REG (env->fpr[44])
+#include "fop_template.h"
+#define REGNAME f46
+#define REG (env->fpr[46])
+#include "fop_template.h"
+#define REGNAME f48
+#define REG (env->fpr[47])
+#include "fop_template.h"
+#define REGNAME f50
+#define REG (env->fpr[50])
+#include "fop_template.h"
+#define REGNAME f52
+#define REG (env->fpr[52])
+#include "fop_template.h"
+#define REGNAME f54
+#define REG (env->fpr[54])
+#include "fop_template.h"
+#define REGNAME f56
+#define REG (env->fpr[56])
+#include "fop_template.h"
+#define REGNAME f58
+#define REG (env->fpr[58])
+#include "fop_template.h"
+#define REGNAME f60
+#define REG (env->fpr[60])
+#include "fop_template.h"
+#define REGNAME f62
+#define REG (env->fpr[62])
+#include "fop_template.h"
+#endif
+
+#ifdef TARGET_SPARC64
+#ifdef WORDS_BIGENDIAN
+typedef union UREG64 {
+ struct { uint16_t v3, v2, v1, v0; } w;
+ struct { uint32_t v1, v0; } l;
+ uint64_t q;
+} UREG64;
+#else
+typedef union UREG64 {
+ struct { uint16_t v0, v1, v2, v3; } w;
+ struct { uint32_t v0, v1; } l;
+ uint64_t q;
+} UREG64;
+#endif
+
+#define PARAMQ1 \
+({\
+ UREG64 __p;\
+ __p.l.v1 = PARAM1;\
+ __p.l.v0 = PARAM2;\
+ __p.q;\
+})
+
+void OPPROTO op_movq_T0_im64(void)
+{
+ T0 = PARAMQ1;
+}
+
+void OPPROTO op_movq_T1_im64(void)
+{
+ T1 = PARAMQ1;
+}
+
+#define XFLAG_SET(x) ((env->xcc&x)?1:0)
+
+#else
+#define EIP (env->pc)
+#endif
+
+#define FLAG_SET(x) ((env->psr&x)?1:0)
+
+void OPPROTO op_movl_T0_0(void)
+{
+ T0 = 0;
+}
+
+void OPPROTO op_movl_T0_im(void)
+{
+ T0 = (uint32_t)PARAM1;
+}
+
+void OPPROTO op_movl_T1_im(void)
+{
+ T1 = (uint32_t)PARAM1;
+}
+
+void OPPROTO op_movl_T2_im(void)
+{
+ T2 = (uint32_t)PARAM1;
+}
+
+void OPPROTO op_movl_T0_sim(void)
+{
+ T0 = (int32_t)PARAM1;
+}
+
+void OPPROTO op_movl_T1_sim(void)
+{
+ T1 = (int32_t)PARAM1;
+}
+
+void OPPROTO op_movl_T2_sim(void)
+{
+ T2 = (int32_t)PARAM1;
+}
+
+void OPPROTO op_movl_T0_env(void)
+{
+ T0 = *(uint32_t *)((char *)env + PARAM1);
+}
+
+void OPPROTO op_movl_env_T0(void)
+{
+ *(uint32_t *)((char *)env + PARAM1) = T0;
+}
+
+void OPPROTO op_movtl_T0_env(void)
+{
+ T0 = *(target_ulong *)((char *)env + PARAM1);
+}
+
+void OPPROTO op_movtl_env_T0(void)
+{
+ *(target_ulong *)((char *)env + PARAM1) = T0;
+}
+
+void OPPROTO op_add_T1_T0(void)
+{
+ T0 += T1;
+}
+
+void OPPROTO op_add_T1_T0_cc(void)
+{
+ target_ulong src1;
+
+ src1 = T0;
+ T0 += T1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ env->psr |= PSR_OVF;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (T0 < src1)
+ env->xcc |= PSR_CARRY;
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
+ env->xcc |= PSR_OVF;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (T0 < src1)
+ env->psr |= PSR_CARRY;
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+#endif
+ FORCE_RET();
+}
+
+void OPPROTO op_addx_T1_T0(void)
+{
+ T0 += T1 + FLAG_SET(PSR_CARRY);
+}
+
+void OPPROTO op_addx_T1_T0_cc(void)
+{
+ target_ulong src1;
+ src1 = T0;
+ if (FLAG_SET(PSR_CARRY))
+ {
+ T0 += T1 + 1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if ((T0 & 0xffffffff) <= (src1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ env->xcc = 0;
+ if (T0 <= src1)
+ env->xcc |= PSR_CARRY;
+#else
+ if (T0 <= src1)
+ env->psr |= PSR_CARRY;
+#endif
+ }
+ else
+ {
+ T0 += T1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ env->xcc = 0;
+ if (T0 < src1)
+ env->xcc |= PSR_CARRY;
+#else
+ if (T0 < src1)
+ env->psr |= PSR_CARRY;
+#endif
+ }
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ env->psr |= PSR_OVF;
+
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
+ env->xcc |= PSR_OVF;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+#endif
+ FORCE_RET();
+}
+
+void OPPROTO op_sub_T1_T0(void)
+{
+ T0 -= T1;
+}
+
+void OPPROTO op_sub_T1_T0_cc(void)
+{
+ target_ulong src1;
+
+ src1 = T0;
+ T0 -= T1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ env->psr |= PSR_OVF;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (src1 < T1)
+ env->xcc |= PSR_CARRY;
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
+ env->xcc |= PSR_OVF;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (src1 < T1)
+ env->psr |= PSR_CARRY;
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+#endif
+ FORCE_RET();
+}
+
+void OPPROTO op_subx_T1_T0(void)
+{
+ T0 -= T1 + FLAG_SET(PSR_CARRY);
+}
+
+void OPPROTO op_subx_T1_T0_cc(void)
+{
+ target_ulong src1;
+ src1 = T0;
+ if (FLAG_SET(PSR_CARRY))
+ {
+ T0 -= T1 + 1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if ((src1 & 0xffffffff) <= (T1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ env->xcc = 0;
+ if (src1 <= T1)
+ env->xcc |= PSR_CARRY;
+#else
+ if (src1 <= T1)
+ env->psr |= PSR_CARRY;
+#endif
+ }
+ else
+ {
+ T0 -= T1;
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
+ env->psr |= PSR_CARRY;
+ env->xcc = 0;
+ if (src1 < T1)
+ env->xcc |= PSR_CARRY;
+#else
+ if (src1 < T1)
+ env->psr |= PSR_CARRY;
+#endif
+ }
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
+ ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
+ env->psr |= PSR_OVF;
+
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
+ env->xcc |= PSR_OVF;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+#endif
+ FORCE_RET();
+}
+
+void OPPROTO op_and_T1_T0(void)
+{
+ T0 &= T1;
+}
+
+void OPPROTO op_or_T1_T0(void)
+{
+ T0 |= T1;
+}
+
+void OPPROTO op_xor_T1_T0(void)
+{
+ T0 ^= T1;
+}
+
+void OPPROTO op_andn_T1_T0(void)
+{
+ T0 &= ~T1;
+}
+
+void OPPROTO op_orn_T1_T0(void)
+{
+ T0 |= ~T1;
+}
+
+void OPPROTO op_xnor_T1_T0(void)
+{
+ T0 ^= ~T1;
+}
+
+void OPPROTO op_umul_T1_T0(void)
+{
+ uint64_t res;
+ res = (uint64_t) T0 * (uint64_t) T1;
+#ifdef TARGET_SPARC64
+ T0 = res;
+#else
+ T0 = res & 0xffffffff;
+#endif
+ env->y = res >> 32;
+}
+
+void OPPROTO op_smul_T1_T0(void)
+{
+ uint64_t res;
+ res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1);
+#ifdef TARGET_SPARC64
+ T0 = res;
+#else
+ T0 = res & 0xffffffff;
+#endif
+ env->y = res >> 32;
+}
+
+void OPPROTO op_mulscc_T1_T0(void)
+{
+ unsigned int b1, N, V, b2;
+ target_ulong src1;
+
+ N = FLAG_SET(PSR_NEG);
+ V = FLAG_SET(PSR_OVF);
+ b1 = N ^ V;
+ b2 = T0 & 1;
+ T0 = (b1 << 31) | (T0 >> 1);
+ if (!(env->y & 1))
+ T1 = 0;
+ /* do addition and update flags */
+ src1 = T0;
+ T0 += T1;
+ env->psr = 0;
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (T0 < src1)
+ env->psr |= PSR_CARRY;
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+ env->y = (b2 << 31) | (env->y >> 1);
+ FORCE_RET();
+}
+
+void OPPROTO op_udiv_T1_T0(void)
+{
+ uint64_t x0;
+ uint32_t x1;
+
+ x0 = T0 | ((uint64_t) (env->y) << 32);
+ x1 = T1;
+ x0 = x0 / x1;
+ if (x0 > 0xffffffff) {
+ T0 = 0xffffffff;
+ T1 = 1;
+ } else {
+ T0 = x0;
+ T1 = 0;
+ }
+ FORCE_RET();
+}
+
+void OPPROTO op_sdiv_T1_T0(void)
+{
+ int64_t x0;
+ int32_t x1;
+
+ x0 = T0 | ((int64_t) (env->y) << 32);
+ x1 = T1;
+ x0 = x0 / x1;
+ if ((int32_t) x0 != x0) {
+ T0 = x0 < 0? 0x80000000: 0x7fffffff;
+ T1 = 1;
+ } else {
+ T0 = x0;
+ T1 = 0;
+ }
+ FORCE_RET();
+}
+
+void OPPROTO op_div_cc(void)
+{
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (T1)
+ env->psr |= PSR_OVF;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+ if (T1)
+ env->psr |= PSR_OVF;
+#endif
+ FORCE_RET();
+}
+
+#ifdef TARGET_SPARC64
+void OPPROTO op_mulx_T1_T0(void)
+{
+ T0 *= T1;
+ FORCE_RET();
+}
+
+void OPPROTO op_udivx_T1_T0(void)
+{
+ T0 /= T1;
+ FORCE_RET();
+}
+
+void OPPROTO op_sdivx_T1_T0(void)
+{
+ if (T0 == INT64_MIN && T1 == -1)
+ T0 = INT64_MIN;
+ else
+ T0 /= (target_long) T1;
+ FORCE_RET();
+}
+#endif
+
+void OPPROTO op_logic_T0_cc(void)
+{
+ env->psr = 0;
+#ifdef TARGET_SPARC64
+ if (!(T0 & 0xffffffff))
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+
+ env->xcc = 0;
+ if (!T0)
+ env->xcc |= PSR_ZERO;
+ if ((int64_t) T0 < 0)
+ env->xcc |= PSR_NEG;
+#else
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+#endif
+ FORCE_RET();
+}
+
+void OPPROTO op_sll(void)
+{
+ T0 <<= T1;
+}
+
+#ifdef TARGET_SPARC64
+void OPPROTO op_srl(void)
+{
+ T0 = (T0 & 0xffffffff) >> T1;
+}
+
+void OPPROTO op_srlx(void)
+{
+ T0 >>= T1;
+}
+
+void OPPROTO op_sra(void)
+{
+ T0 = ((int32_t) (T0 & 0xffffffff)) >> T1;
+}
+
+void OPPROTO op_srax(void)
+{
+ T0 = ((int64_t) T0) >> T1;
+}
+#else
+void OPPROTO op_srl(void)
+{
+ T0 >>= T1;
+}
+
+void OPPROTO op_sra(void)
+{
+ T0 = ((int32_t) T0) >> T1;
+}
+#endif
+
+/* Load and store */
+#define MEMSUFFIX _raw
+#include "op_mem.h"
+#if !defined(CONFIG_USER_ONLY)
+#define MEMSUFFIX _user
+#include "op_mem.h"
+
+#define MEMSUFFIX _kernel
+#include "op_mem.h"
+#endif
+
+void OPPROTO op_ldfsr(void)
+{
+ PUT_FSR32(env, *((uint32_t *) &FT0));
+ helper_ldfsr();
+}
+
+void OPPROTO op_stfsr(void)
+{
+ *((uint32_t *) &FT0) = GET_FSR32(env);
+}
+
+#ifndef TARGET_SPARC64
+void OPPROTO op_rdpsr(void)
+{
+ do_rdpsr();
+}
+
+void OPPROTO op_wrpsr(void)
+{
+ do_wrpsr();
+ FORCE_RET();
+}
+
+void OPPROTO op_rett(void)
+{
+ helper_rett();
+ FORCE_RET();
+}
+
+/* XXX: use another pointer for %iN registers to avoid slow wrapping
+ handling ? */
+void OPPROTO op_save(void)
+{
+ uint32_t cwp;
+ cwp = (env->cwp - 1) & (NWINDOWS - 1);
+ if (env->wim & (1 << cwp)) {
+ raise_exception(TT_WIN_OVF);
+ }
+ set_cwp(cwp);
+ FORCE_RET();
+}
+
+void OPPROTO op_restore(void)
+{
+ uint32_t cwp;
+ cwp = (env->cwp + 1) & (NWINDOWS - 1);
+ if (env->wim & (1 << cwp)) {
+ raise_exception(TT_WIN_UNF);
+ }
+ set_cwp(cwp);
+ FORCE_RET();
+}
+#else
+void OPPROTO op_rdccr(void)
+{
+ T0 = GET_CCR(env);
+}
+
+void OPPROTO op_wrccr(void)
+{
+ PUT_CCR(env, T0);
+}
+
+void OPPROTO op_rdtick(void)
+{
+ T0 = 0; // XXX read cycle counter and bit 31
+}
+
+void OPPROTO op_wrtick(void)
+{
+ // XXX write cycle counter and bit 31
+}
+
+void OPPROTO op_rdtpc(void)
+{
+ T0 = env->tpc[env->tl];
+}
+
+void OPPROTO op_wrtpc(void)
+{
+ env->tpc[env->tl] = T0;
+}
+
+void OPPROTO op_rdtnpc(void)
+{
+ T0 = env->tnpc[env->tl];
+}
+
+void OPPROTO op_wrtnpc(void)
+{
+ env->tnpc[env->tl] = T0;
+}
+
+void OPPROTO op_rdtstate(void)
+{
+ T0 = env->tstate[env->tl];
+}
+
+void OPPROTO op_wrtstate(void)
+{
+ env->tstate[env->tl] = T0;
+}
+
+void OPPROTO op_rdtt(void)
+{
+ T0 = env->tt[env->tl];
+}
+
+void OPPROTO op_wrtt(void)
+{
+ env->tt[env->tl] = T0;
+}
+
+void OPPROTO op_rdpstate(void)
+{
+ T0 = env->pstate;
+}
+
+void OPPROTO op_wrpstate(void)
+{
+ do_wrpstate();
+}
+
+// CWP handling is reversed in V9, but we still use the V8 register
+// order.
+void OPPROTO op_rdcwp(void)
+{
+ T0 = NWINDOWS - 1 - env->cwp;
+}
+
+void OPPROTO op_wrcwp(void)
+{
+ env->cwp = NWINDOWS - 1 - T0;
+}
+
+/* XXX: use another pointer for %iN registers to avoid slow wrapping
+ handling ? */
+void OPPROTO op_save(void)
+{
+ uint32_t cwp;
+ cwp = (env->cwp - 1) & (NWINDOWS - 1);
+ if (env->cansave == 0) {
+ raise_exception(TT_SPILL | (env->otherwin != 0 ?
+ (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
+ ((env->wstate & 0x7) << 2)));
+ } else {
+ if (env->cleanwin - env->canrestore == 0) {
+ // XXX Clean windows without trap
+ raise_exception(TT_CLRWIN);
+ } else {
+ env->cansave--;
+ env->canrestore++;
+ set_cwp(cwp);
+ }
+ }
+ FORCE_RET();
+}
+
+void OPPROTO op_restore(void)
+{
+ uint32_t cwp;
+ cwp = (env->cwp + 1) & (NWINDOWS - 1);
+ if (env->canrestore == 0) {
+ raise_exception(TT_FILL | (env->otherwin != 0 ?
+ (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
+ ((env->wstate & 0x7) << 2)));
+ } else {
+ env->cansave++;
+ env->canrestore--;
+ set_cwp(cwp);
+ }
+ FORCE_RET();
+}
+#endif
+
+void OPPROTO op_exception(void)
+{
+ env->exception_index = PARAM1;
+ cpu_loop_exit();
+}
+
+void OPPROTO op_trap_T0(void)
+{
+ env->exception_index = TT_TRAP + (T0 & 0x7f);
+ cpu_loop_exit();
+}
+
+void OPPROTO op_trapcc_T0(void)
+{
+ if (T2) {
+ env->exception_index = TT_TRAP + (T0 & 0x7f);
+ cpu_loop_exit();
+ }
+ FORCE_RET();
+}
+
+void OPPROTO op_fpexception_im(void)
+{
+ env->exception_index = TT_FP_EXCP;
+ env->fsr &= ~FSR_FTT_MASK;
+ env->fsr |= PARAM1;
+ cpu_loop_exit();
+ FORCE_RET();
+}
+
+void OPPROTO op_debug(void)
+{
+ helper_debug();
+}
+
+void OPPROTO op_exit_tb(void)
+{
+ EXIT_TB();
+}
+
+void OPPROTO op_eval_ba(void)
+{
+ T2 = 1;
+}
+
+void OPPROTO op_eval_be(void)
+{
+ T2 = FLAG_SET(PSR_ZERO);
+}
+
+void OPPROTO op_eval_ble(void)
+{
+ target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
+
+ T2 = Z | (N ^ V);
+}
+
+void OPPROTO op_eval_bl(void)
+{
+ target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
+
+ T2 = N ^ V;
+}
+
+void OPPROTO op_eval_bleu(void)
+{
+ target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
+
+ T2 = C | Z;
+}
+
+void OPPROTO op_eval_bcs(void)
+{
+ T2 = FLAG_SET(PSR_CARRY);
+}
+
+void OPPROTO op_eval_bvs(void)
+{
+ T2 = FLAG_SET(PSR_OVF);
+}
+
+void OPPROTO op_eval_bn(void)
+{
+ T2 = 0;
+}
+
+void OPPROTO op_eval_bneg(void)
+{
+ T2 = FLAG_SET(PSR_NEG);
+}
+
+void OPPROTO op_eval_bne(void)
+{
+ T2 = !FLAG_SET(PSR_ZERO);
+}
+
+void OPPROTO op_eval_bg(void)
+{
+ target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
+
+ T2 = !(Z | (N ^ V));
+}
+
+void OPPROTO op_eval_bge(void)
+{
+ target_ulong N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
+
+ T2 = !(N ^ V);
+}
+
+void OPPROTO op_eval_bgu(void)
+{
+ target_ulong Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
+
+ T2 = !(C | Z);
+}
+
+void OPPROTO op_eval_bcc(void)
+{
+ T2 = !FLAG_SET(PSR_CARRY);
+}
+
+void OPPROTO op_eval_bpos(void)
+{
+ T2 = !FLAG_SET(PSR_NEG);
+}
+
+void OPPROTO op_eval_bvc(void)
+{
+ T2 = !FLAG_SET(PSR_OVF);
+}
+
+#ifdef TARGET_SPARC64
+void OPPROTO op_eval_xbe(void)
+{
+ T2 = XFLAG_SET(PSR_ZERO);
+}
+
+void OPPROTO op_eval_xble(void)
+{
+ target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
+
+ T2 = Z | (N ^ V);
+}
+
+void OPPROTO op_eval_xbl(void)
+{
+ target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
+
+ T2 = N ^ V;
+}
+
+void OPPROTO op_eval_xbleu(void)
+{
+ target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
+
+ T2 = C | Z;
+}
+
+void OPPROTO op_eval_xbcs(void)
+{
+ T2 = XFLAG_SET(PSR_CARRY);
+}
+
+void OPPROTO op_eval_xbvs(void)
+{
+ T2 = XFLAG_SET(PSR_OVF);
+}
+
+void OPPROTO op_eval_xbneg(void)
+{
+ T2 = XFLAG_SET(PSR_NEG);
+}
+
+void OPPROTO op_eval_xbne(void)
+{
+ T2 = !XFLAG_SET(PSR_ZERO);
+}
+
+void OPPROTO op_eval_xbg(void)
+{
+ target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
+
+ T2 = !(Z | (N ^ V));
+}
+
+void OPPROTO op_eval_xbge(void)
+{
+ target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
+
+ T2 = !(N ^ V);
+}
+
+void OPPROTO op_eval_xbgu(void)
+{
+ target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY);
+
+ T2 = !(C | Z);
+}
+
+void OPPROTO op_eval_xbcc(void)
+{
+ T2 = !XFLAG_SET(PSR_CARRY);
+}
+
+void OPPROTO op_eval_xbpos(void)
+{
+ T2 = !XFLAG_SET(PSR_NEG);
+}
+
+void OPPROTO op_eval_xbvc(void)
+{
+ T2 = !XFLAG_SET(PSR_OVF);
+}
+#endif
+
+#define FCC
+#define FFLAG_SET(x) (env->fsr & x? 1: 0)
+#include "fbranch_template.h"
+
+#ifdef TARGET_SPARC64
+#define FCC _fcc1
+#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0)
+#include "fbranch_template.h"
+#define FCC _fcc2
+#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0)
+#include "fbranch_template.h"
+#define FCC _fcc3
+#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0)
+#include "fbranch_template.h"
+#endif
+
+#ifdef TARGET_SPARC64
+void OPPROTO op_eval_brz(void)
+{
+ T2 = (T0 == 0);
+}
+
+void OPPROTO op_eval_brnz(void)
+{
+ T2 = (T0 != 0);
+}
+
+void OPPROTO op_eval_brlz(void)
+{
+ T2 = ((int64_t)T0 < 0);
+}
+
+void OPPROTO op_eval_brlez(void)
+{
+ T2 = ((int64_t)T0 <= 0);
+}
+
+void OPPROTO op_eval_brgz(void)
+{
+ T2 = ((int64_t)T0 > 0);
+}
+
+void OPPROTO op_eval_brgez(void)
+{
+ T2 = ((int64_t)T0 >= 0);
+}
+
+void OPPROTO op_jmp_im64(void)
+{
+ env->pc = PARAMQ1;
+}
+
+void OPPROTO op_movq_npc_im64(void)
+{
+ env->npc = PARAMQ1;
+}
+#endif
+
+void OPPROTO op_jmp_im(void)
+{
+ env->pc = (uint32_t)PARAM1;
+}
+
+void OPPROTO op_movl_npc_im(void)
+{
+ env->npc = (uint32_t)PARAM1;
+}
+
+void OPPROTO op_movl_npc_T0(void)
+{
+ env->npc = T0;
+}
+
+void OPPROTO op_mov_pc_npc(void)
+{
+ env->pc = env->npc;
+}
+
+void OPPROTO op_next_insn(void)
+{
+ env->pc = env->npc;
+ env->npc = env->npc + 4;
+}
+
+void OPPROTO op_goto_tb0(void)
+{
+ GOTO_TB(op_goto_tb0, PARAM1, 0);
+}
+
+void OPPROTO op_goto_tb1(void)
+{
+ GOTO_TB(op_goto_tb1, PARAM1, 1);
+}
+
+void OPPROTO op_jmp_label(void)
+{
+ GOTO_LABEL_PARAM(1);
+}
+
+void OPPROTO op_jnz_T2_label(void)
+{
+ if (T2)
+ GOTO_LABEL_PARAM(1);
+ FORCE_RET();
+}
+
+void OPPROTO op_jz_T2_label(void)
+{
+ if (!T2)
+ GOTO_LABEL_PARAM(1);
+ FORCE_RET();
+}
+
+void OPPROTO op_flush_T0(void)
+{
+ helper_flush(T0);
+}
+
+#define F_OP(name, p) void OPPROTO op_f##name##p(void)
+
+#define F_BINOP(name) \
+ F_OP(name, s) \
+ { \
+ FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
+ } \
+ F_OP(name, d) \
+ { \
+ DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
+ }
+
+F_BINOP(add);
+F_BINOP(sub);
+F_BINOP(mul);
+F_BINOP(div);
+#undef F_BINOP
+
+void OPPROTO op_fsmuld(void)
+{
+ DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
+ float32_to_float64(FT1, &env->fp_status),
+ &env->fp_status);
+}
+
+#define F_HELPER(name) \
+ F_OP(name, s) \
+ { \
+ do_f##name##s(); \
+ } \
+ F_OP(name, d) \
+ { \
+ do_f##name##d(); \
+ }
+
+F_HELPER(sqrt);
+
+F_OP(neg, s)
+{
+ FT0 = float32_chs(FT1);
+}
+
+F_OP(abs, s)
+{
+ do_fabss();
+}
+
+F_HELPER(cmp);
+
+#ifdef TARGET_SPARC64
+F_OP(neg, d)
+{
+ DT0 = float64_chs(DT1);
+}
+
+F_OP(abs, d)
+{
+ do_fabsd();
+}
+
+void OPPROTO op_fcmps_fcc1(void)
+{
+ do_fcmps_fcc1();
+}
+
+void OPPROTO op_fcmpd_fcc1(void)
+{
+ do_fcmpd_fcc1();
+}
+
+void OPPROTO op_fcmps_fcc2(void)
+{
+ do_fcmps_fcc2();
+}
+
+void OPPROTO op_fcmpd_fcc2(void)
+{
+ do_fcmpd_fcc2();
+}
+
+void OPPROTO op_fcmps_fcc3(void)
+{
+ do_fcmps_fcc3();
+}
+
+void OPPROTO op_fcmpd_fcc3(void)
+{
+ do_fcmpd_fcc3();
+}
+#endif
+
+/* Integer to float conversion. */
+#ifdef USE_INT_TO_FLOAT_HELPERS
+F_HELPER(ito);
+#else
+F_OP(ito, s)
+{
+ FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
+}
+
+F_OP(ito, d)
+{
+ DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
+}
+
+#ifdef TARGET_SPARC64
+F_OP(xto, s)
+{
+ FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
+}
+
+F_OP(xto, d)
+{
+ DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
+}
+#endif
+#endif
+#undef F_HELPER
+
+/* floating point conversion */
+void OPPROTO op_fdtos(void)
+{
+ FT0 = float64_to_float32(DT1, &env->fp_status);
+}
+
+void OPPROTO op_fstod(void)
+{
+ DT0 = float32_to_float64(FT1, &env->fp_status);
+}
+
+/* Float to integer conversion. */
+void OPPROTO op_fstoi(void)
+{
+ *((int32_t *)&FT0) = float32_to_int32(FT1, &env->fp_status);
+}
+
+void OPPROTO op_fdtoi(void)
+{
+ *((int32_t *)&FT0) = float64_to_int32(DT1, &env->fp_status);
+}
+
+#ifdef TARGET_SPARC64
+void OPPROTO op_fstox(void)
+{
+ *((int64_t *)&DT0) = float32_to_int64(FT1, &env->fp_status);
+}
+
+void OPPROTO op_fdtox(void)
+{
+ *((int64_t *)&DT0) = float64_to_int64(DT1, &env->fp_status);
+}
+
+void OPPROTO op_fmovs_cc(void)
+{
+ if (T2)
+ FT0 = FT1;
+}
+
+void OPPROTO op_fmovd_cc(void)
+{
+ if (T2)
+ DT0 = DT1;
+}
+
+void OPPROTO op_mov_cc(void)
+{
+ if (T2)
+ T0 = T1;
+}
+
+void OPPROTO op_flushw(void)
+{
+ if (env->cansave != NWINDOWS - 2) {
+ raise_exception(TT_SPILL | (env->otherwin != 0 ?
+ (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
+ ((env->wstate & 0x7) << 2)));
+ }
+}
+
+void OPPROTO op_saved(void)
+{
+ env->cansave++;
+ if (env->otherwin == 0)
+ env->canrestore--;
+ else
+ env->otherwin--;
+ FORCE_RET();
+}
+
+void OPPROTO op_restored(void)
+{
+ env->canrestore++;
+ if (env->cleanwin < NWINDOWS - 1)
+ env->cleanwin++;
+ if (env->otherwin == 0)
+ env->cansave--;
+ else
+ env->otherwin--;
+ FORCE_RET();
+}
+
+void OPPROTO op_popc(void)
+{
+ do_popc();
+}
+
+void OPPROTO op_done(void)
+{
+ do_done();
+}
+
+void OPPROTO op_retry(void)
+{
+ do_retry();
+}
+
+void OPPROTO op_sir(void)
+{
+ // XXX
+
+}
+
+void OPPROTO op_ld_asi_reg()
+{
+ T0 += PARAM1;
+ helper_ld_asi(env->asi, PARAM2, PARAM3);
+}
+
+void OPPROTO op_st_asi_reg()
+{
+ T0 += PARAM1;
+ helper_st_asi(env->asi, PARAM2, PARAM3);
+}
+#endif
+
+void OPPROTO op_ld_asi()
+{
+ helper_ld_asi(PARAM1, PARAM2, PARAM3);
+}
+
+void OPPROTO op_st_asi()
+{
+ helper_st_asi(PARAM1, PARAM2, PARAM3);
+}
+
+#ifdef TARGET_SPARC64
+void OPPROTO op_alignaddr()
+{
+ uint64_t tmp;
+
+ tmp = T0 + T1;
+ env->gsr &= ~7ULL;
+ env->gsr |= tmp & 7ULL;
+ T0 = tmp & ~7ULL;
+}
+
+void OPPROTO op_faligndata()
+{
+ uint64_t tmp;
+
+ tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
+ tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
+ (*((uint64_t *)&DT0)) = tmp;
+}
+#endif
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
new file mode 100644
index 0000000..f4f725d
--- /dev/null
+++ b/target-sparc/op_helper.c
@@ -0,0 +1,918 @@
+#include "exec.h"
+
+//#define DEBUG_PCALL
+//#define DEBUG_MMU
+
+void raise_exception(int tt)
+{
+ env->exception_index = tt;
+ cpu_loop_exit();
+}
+
+#ifdef USE_INT_TO_FLOAT_HELPERS
+void do_fitos(void)
+{
+ FT0 = int32_to_float32(*((int32_t *)&FT1));
+}
+
+void do_fitod(void)
+{
+ DT0 = int32_to_float64(*((int32_t *)&FT1));
+}
+#endif
+
+void do_fabss(void)
+{
+ FT0 = float32_abs(FT1);
+}
+
+#ifdef TARGET_SPARC64
+void do_fabsd(void)
+{
+ DT0 = float64_abs(DT1);
+}
+#endif
+
+void do_fsqrts(void)
+{
+ FT0 = float32_sqrt(FT1, &env->fp_status);
+}
+
+void do_fsqrtd(void)
+{
+ DT0 = float64_sqrt(DT1, &env->fp_status);
+}
+
+#define GEN_FCMP(name, size, reg1, reg2, FS) \
+ void glue(do_, name) (void) \
+ { \
+ env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
+ switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
+ case float_relation_unordered: \
+ T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
+ if (env->fsr & FSR_NVM) { \
+ env->fsr |= T0; \
+ raise_exception(TT_FP_EXCP); \
+ } else { \
+ env->fsr |= FSR_NVA; \
+ } \
+ break; \
+ case float_relation_less: \
+ T0 = FSR_FCC0 << FS; \
+ break; \
+ case float_relation_greater: \
+ T0 = FSR_FCC1 << FS; \
+ break; \
+ default: \
+ T0 = 0; \
+ break; \
+ } \
+ env->fsr |= T0; \
+ }
+
+GEN_FCMP(fcmps, float32, FT0, FT1, 0);
+GEN_FCMP(fcmpd, float64, DT0, DT1, 0);
+
+#ifdef TARGET_SPARC64
+GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22);
+GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22);
+
+GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24);
+GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24);
+
+GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26);
+GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26);
+#endif
+
+#if defined(CONFIG_USER_ONLY)
+void helper_ld_asi(int asi, int size, int sign)
+{
+}
+
+void helper_st_asi(int asi, int size, int sign)
+{
+}
+#else
+#ifndef TARGET_SPARC64
+void helper_ld_asi(int asi, int size, int sign)
+{
+ uint32_t ret = 0;
+
+ switch (asi) {
+ case 3: /* MMU probe */
+ {
+ int mmulev;
+
+ mmulev = (T0 >> 8) & 15;
+ if (mmulev > 4)
+ ret = 0;
+ else {
+ ret = mmu_probe(env, T0, mmulev);
+ //bswap32s(&ret);
+ }
+#ifdef DEBUG_MMU
+ printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
+#endif
+ }
+ break;
+ case 4: /* read MMU regs */
+ {
+ int reg = (T0 >> 8) & 0xf;
+
+ ret = env->mmuregs[reg];
+ if (reg == 3) /* Fault status cleared on read */
+ env->mmuregs[reg] = 0;
+#ifdef DEBUG_MMU
+ printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
+#endif
+ }
+ break;
+ case 0x20 ... 0x2f: /* MMU passthrough */
+ switch(size) {
+ case 1:
+ ret = ldub_phys(T0);
+ break;
+ case 2:
+ ret = lduw_phys(T0 & ~1);
+ break;
+ default:
+ case 4:
+ ret = ldl_phys(T0 & ~3);
+ break;
+ case 8:
+ ret = ldl_phys(T0 & ~3);
+ T0 = ldl_phys((T0 + 4) & ~3);
+ break;
+ }
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+ T1 = ret;
+}
+
+void helper_st_asi(int asi, int size, int sign)
+{
+ switch(asi) {
+ case 3: /* MMU flush */
+ {
+ int mmulev;
+
+ mmulev = (T0 >> 8) & 15;
+#ifdef DEBUG_MMU
+ printf("mmu flush level %d\n", mmulev);
+#endif
+ switch (mmulev) {
+ case 0: // flush page
+ tlb_flush_page(env, T0 & 0xfffff000);
+ break;
+ case 1: // flush segment (256k)
+ case 2: // flush region (16M)
+ case 3: // flush context (4G)
+ case 4: // flush entire
+ tlb_flush(env, 1);
+ break;
+ default:
+ break;
+ }
+#ifdef DEBUG_MMU
+ dump_mmu(env);
+#endif
+ return;
+ }
+ case 4: /* write MMU regs */
+ {
+ int reg = (T0 >> 8) & 0xf;
+ uint32_t oldreg;
+
+ oldreg = env->mmuregs[reg];
+ switch(reg) {
+ case 0:
+ env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
+ env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
+ // Mappings generated during no-fault mode or MMU
+ // disabled mode are invalid in normal mode
+ if (oldreg != env->mmuregs[reg])
+ tlb_flush(env, 1);
+ break;
+ case 2:
+ env->mmuregs[reg] = T1;
+ if (oldreg != env->mmuregs[reg]) {
+ /* we flush when the MMU context changes because
+ QEMU has no MMU context support */
+ tlb_flush(env, 1);
+ }
+ break;
+ case 3:
+ case 4:
+ break;
+ default:
+ env->mmuregs[reg] = T1;
+ break;
+ }
+#ifdef DEBUG_MMU
+ if (oldreg != env->mmuregs[reg]) {
+ printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
+ }
+ dump_mmu(env);
+#endif
+ return;
+ }
+ case 0x17: /* Block copy, sta access */
+ {
+ // value (T1) = src
+ // address (T0) = dst
+ // copy 32 bytes
+ uint32_t src = T1, dst = T0;
+ uint8_t temp[32];
+
+ tswap32s(&src);
+
+ cpu_physical_memory_read(src, (void *) &temp, 32);
+ cpu_physical_memory_write(dst, (void *) &temp, 32);
+ }
+ return;
+ case 0x1f: /* Block fill, stda access */
+ {
+ // value (T1, T2)
+ // address (T0) = dst
+ // fill 32 bytes
+ int i;
+ uint32_t dst = T0;
+ uint64_t val;
+
+ val = (((uint64_t)T1) << 32) | T2;
+ tswap64s(&val);
+
+ for (i = 0; i < 32; i += 8, dst += 8) {
+ cpu_physical_memory_write(dst, (void *) &val, 8);
+ }
+ }
+ return;
+ case 0x20 ... 0x2f: /* MMU passthrough */
+ {
+ switch(size) {
+ case 1:
+ stb_phys(T0, T1);
+ break;
+ case 2:
+ stw_phys(T0 & ~1, T1);
+ break;
+ case 4:
+ default:
+ stl_phys(T0 & ~3, T1);
+ break;
+ case 8:
+ stl_phys(T0 & ~3, T1);
+ stl_phys((T0 + 4) & ~3, T2);
+ break;
+ }
+ }
+ return;
+ default:
+ return;
+ }
+}
+
+#else
+
+void helper_ld_asi(int asi, int size, int sign)
+{
+ uint64_t ret = 0;
+
+ if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
+ raise_exception(TT_PRIV_ACT);
+
+ switch (asi) {
+ case 0x14: // Bypass
+ case 0x15: // Bypass, non-cacheable
+ {
+ switch(size) {
+ case 1:
+ ret = ldub_phys(T0);
+ break;
+ case 2:
+ ret = lduw_phys(T0 & ~1);
+ break;
+ case 4:
+ ret = ldl_phys(T0 & ~3);
+ break;
+ default:
+ case 8:
+ ret = ldq_phys(T0 & ~7);
+ break;
+ }
+ break;
+ }
+ case 0x04: // Nucleus
+ case 0x0c: // Nucleus Little Endian (LE)
+ case 0x10: // As if user primary
+ case 0x11: // As if user secondary
+ case 0x18: // As if user primary LE
+ case 0x19: // As if user secondary LE
+ case 0x1c: // Bypass LE
+ case 0x1d: // Bypass, non-cacheable LE
+ case 0x24: // Nucleus quad LDD 128 bit atomic
+ case 0x2c: // Nucleus quad LDD 128 bit atomic
+ case 0x4a: // UPA config
+ case 0x82: // Primary no-fault
+ case 0x83: // Secondary no-fault
+ case 0x88: // Primary LE
+ case 0x89: // Secondary LE
+ case 0x8a: // Primary no-fault LE
+ case 0x8b: // Secondary no-fault LE
+ // XXX
+ break;
+ case 0x45: // LSU
+ ret = env->lsu;
+ break;
+ case 0x50: // I-MMU regs
+ {
+ int reg = (T0 >> 3) & 0xf;
+
+ ret = env->immuregs[reg];
+ break;
+ }
+ case 0x51: // I-MMU 8k TSB pointer
+ case 0x52: // I-MMU 64k TSB pointer
+ case 0x55: // I-MMU data access
+ // XXX
+ break;
+ case 0x56: // I-MMU tag read
+ {
+ unsigned int i;
+
+ for (i = 0; i < 64; i++) {
+ // Valid, ctx match, vaddr match
+ if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
+ env->itlb_tag[i] == T0) {
+ ret = env->itlb_tag[i];
+ break;
+ }
+ }
+ break;
+ }
+ case 0x58: // D-MMU regs
+ {
+ int reg = (T0 >> 3) & 0xf;
+
+ ret = env->dmmuregs[reg];
+ break;
+ }
+ case 0x5e: // D-MMU tag read
+ {
+ unsigned int i;
+
+ for (i = 0; i < 64; i++) {
+ // Valid, ctx match, vaddr match
+ if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
+ env->dtlb_tag[i] == T0) {
+ ret = env->dtlb_tag[i];
+ break;
+ }
+ }
+ break;
+ }
+ case 0x59: // D-MMU 8k TSB pointer
+ case 0x5a: // D-MMU 64k TSB pointer
+ case 0x5b: // D-MMU data pointer
+ case 0x5d: // D-MMU data access
+ case 0x48: // Interrupt dispatch, RO
+ case 0x49: // Interrupt data receive
+ case 0x7f: // Incoming interrupt vector, RO
+ // XXX
+ break;
+ case 0x54: // I-MMU data in, WO
+ case 0x57: // I-MMU demap, WO
+ case 0x5c: // D-MMU data in, WO
+ case 0x5f: // D-MMU demap, WO
+ case 0x77: // Interrupt vector, WO
+ default:
+ ret = 0;
+ break;
+ }
+ T1 = ret;
+}
+
+void helper_st_asi(int asi, int size, int sign)
+{
+ if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
+ raise_exception(TT_PRIV_ACT);
+
+ switch(asi) {
+ case 0x14: // Bypass
+ case 0x15: // Bypass, non-cacheable
+ {
+ switch(size) {
+ case 1:
+ stb_phys(T0, T1);
+ break;
+ case 2:
+ stw_phys(T0 & ~1, T1);
+ break;
+ case 4:
+ stl_phys(T0 & ~3, T1);
+ break;
+ case 8:
+ default:
+ stq_phys(T0 & ~7, T1);
+ break;
+ }
+ }
+ return;
+ case 0x04: // Nucleus
+ case 0x0c: // Nucleus Little Endian (LE)
+ case 0x10: // As if user primary
+ case 0x11: // As if user secondary
+ case 0x18: // As if user primary LE
+ case 0x19: // As if user secondary LE
+ case 0x1c: // Bypass LE
+ case 0x1d: // Bypass, non-cacheable LE
+ case 0x24: // Nucleus quad LDD 128 bit atomic
+ case 0x2c: // Nucleus quad LDD 128 bit atomic
+ case 0x4a: // UPA config
+ case 0x88: // Primary LE
+ case 0x89: // Secondary LE
+ // XXX
+ return;
+ case 0x45: // LSU
+ {
+ uint64_t oldreg;
+
+ oldreg = env->lsu;
+ env->lsu = T1 & (DMMU_E | IMMU_E);
+ // Mappings generated during D/I MMU disabled mode are
+ // invalid in normal mode
+ if (oldreg != env->lsu) {
+#ifdef DEBUG_MMU
+ printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
+ dump_mmu(env);
+#endif
+ tlb_flush(env, 1);
+ }
+ return;
+ }
+ case 0x50: // I-MMU regs
+ {
+ int reg = (T0 >> 3) & 0xf;
+ uint64_t oldreg;
+
+ oldreg = env->immuregs[reg];
+ switch(reg) {
+ case 0: // RO
+ case 4:
+ return;
+ case 1: // Not in I-MMU
+ case 2:
+ case 7:
+ case 8:
+ return;
+ case 3: // SFSR
+ if ((T1 & 1) == 0)
+ T1 = 0; // Clear SFSR
+ break;
+ case 5: // TSB access
+ case 6: // Tag access
+ default:
+ break;
+ }
+ env->immuregs[reg] = T1;
+#ifdef DEBUG_MMU
+ if (oldreg != env->immuregs[reg]) {
+ printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
+ }
+ dump_mmu(env);
+#endif
+ return;
+ }
+ case 0x54: // I-MMU data in
+ {
+ unsigned int i;
+
+ // Try finding an invalid entry
+ for (i = 0; i < 64; i++) {
+ if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
+ env->itlb_tag[i] = env->immuregs[6];
+ env->itlb_tte[i] = T1;
+ return;
+ }
+ }
+ // Try finding an unlocked entry
+ for (i = 0; i < 64; i++) {
+ if ((env->itlb_tte[i] & 0x40) == 0) {
+ env->itlb_tag[i] = env->immuregs[6];
+ env->itlb_tte[i] = T1;
+ return;
+ }
+ }
+ // error state?
+ return;
+ }
+ case 0x55: // I-MMU data access
+ {
+ unsigned int i = (T0 >> 3) & 0x3f;
+
+ env->itlb_tag[i] = env->immuregs[6];
+ env->itlb_tte[i] = T1;
+ return;
+ }
+ case 0x57: // I-MMU demap
+ // XXX
+ return;
+ case 0x58: // D-MMU regs
+ {
+ int reg = (T0 >> 3) & 0xf;
+ uint64_t oldreg;
+
+ oldreg = env->dmmuregs[reg];
+ switch(reg) {
+ case 0: // RO
+ case 4:
+ return;
+ case 3: // SFSR
+ if ((T1 & 1) == 0) {
+ T1 = 0; // Clear SFSR, Fault address
+ env->dmmuregs[4] = 0;
+ }
+ env->dmmuregs[reg] = T1;
+ break;
+ case 1: // Primary context
+ case 2: // Secondary context
+ case 5: // TSB access
+ case 6: // Tag access
+ case 7: // Virtual Watchpoint
+ case 8: // Physical Watchpoint
+ default:
+ break;
+ }
+ env->dmmuregs[reg] = T1;
+#ifdef DEBUG_MMU
+ if (oldreg != env->dmmuregs[reg]) {
+ printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
+ }
+ dump_mmu(env);
+#endif
+ return;
+ }
+ case 0x5c: // D-MMU data in
+ {
+ unsigned int i;
+
+ // Try finding an invalid entry
+ for (i = 0; i < 64; i++) {
+ if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
+ env->dtlb_tag[i] = env->dmmuregs[6];
+ env->dtlb_tte[i] = T1;
+ return;
+ }
+ }
+ // Try finding an unlocked entry
+ for (i = 0; i < 64; i++) {
+ if ((env->dtlb_tte[i] & 0x40) == 0) {
+ env->dtlb_tag[i] = env->dmmuregs[6];
+ env->dtlb_tte[i] = T1;
+ return;
+ }
+ }
+ // error state?
+ return;
+ }
+ case 0x5d: // D-MMU data access
+ {
+ unsigned int i = (T0 >> 3) & 0x3f;
+
+ env->dtlb_tag[i] = env->dmmuregs[6];
+ env->dtlb_tte[i] = T1;
+ return;
+ }
+ case 0x5f: // D-MMU demap
+ case 0x49: // Interrupt data receive
+ // XXX
+ return;
+ case 0x51: // I-MMU 8k TSB pointer, RO
+ case 0x52: // I-MMU 64k TSB pointer, RO
+ case 0x56: // I-MMU tag read, RO
+ case 0x59: // D-MMU 8k TSB pointer, RO
+ case 0x5a: // D-MMU 64k TSB pointer, RO
+ case 0x5b: // D-MMU data pointer, RO
+ case 0x5e: // D-MMU tag read, RO
+ case 0x48: // Interrupt dispatch, RO
+ case 0x7f: // Incoming interrupt vector, RO
+ case 0x82: // Primary no-fault, RO
+ case 0x83: // Secondary no-fault, RO
+ case 0x8a: // Primary no-fault LE, RO
+ case 0x8b: // Secondary no-fault LE, RO
+ default:
+ return;
+ }
+}
+#endif
+#endif /* !CONFIG_USER_ONLY */
+
+#ifndef TARGET_SPARC64
+void helper_rett()
+{
+ unsigned int cwp;
+
+ env->psret = 1;
+ cwp = (env->cwp + 1) & (NWINDOWS - 1);
+ if (env->wim & (1 << cwp)) {
+ raise_exception(TT_WIN_UNF);
+ }
+ set_cwp(cwp);
+ env->psrs = env->psrps;
+}
+#endif
+
+void helper_ldfsr(void)
+{
+ int rnd_mode;
+ switch (env->fsr & FSR_RD_MASK) {
+ case FSR_RD_NEAREST:
+ rnd_mode = float_round_nearest_even;
+ break;
+ default:
+ case FSR_RD_ZERO:
+ rnd_mode = float_round_to_zero;
+ break;
+ case FSR_RD_POS:
+ rnd_mode = float_round_up;
+ break;
+ case FSR_RD_NEG:
+ rnd_mode = float_round_down;
+ break;
+ }
+ set_float_rounding_mode(rnd_mode, &env->fp_status);
+}
+
+void helper_debug()
+{
+ env->exception_index = EXCP_DEBUG;
+ cpu_loop_exit();
+}
+
+#ifndef TARGET_SPARC64
+void do_wrpsr()
+{
+ PUT_PSR(env, T0);
+}
+
+void do_rdpsr()
+{
+ T0 = GET_PSR(env);
+}
+
+#else
+
+void do_popc()
+{
+ T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL);
+ T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL);
+ T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL);
+ T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL);
+ T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL);
+ T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL);
+}
+
+static inline uint64_t *get_gregset(uint64_t pstate)
+{
+ switch (pstate) {
+ default:
+ case 0:
+ return env->bgregs;
+ case PS_AG:
+ return env->agregs;
+ case PS_MG:
+ return env->mgregs;
+ case PS_IG:
+ return env->igregs;
+ }
+}
+
+void do_wrpstate()
+{
+ uint64_t new_pstate, pstate_regs, new_pstate_regs;
+ uint64_t *src, *dst;
+
+ new_pstate = T0 & 0xf3f;
+ pstate_regs = env->pstate & 0xc01;
+ new_pstate_regs = new_pstate & 0xc01;
+ if (new_pstate_regs != pstate_regs) {
+ // Switch global register bank
+ src = get_gregset(new_pstate_regs);
+ dst = get_gregset(pstate_regs);
+ memcpy32(dst, env->gregs);
+ memcpy32(env->gregs, src);
+ }
+ env->pstate = new_pstate;
+}
+
+void do_done(void)
+{
+ env->tl--;
+ env->pc = env->tnpc[env->tl];
+ env->npc = env->tnpc[env->tl] + 4;
+ PUT_CCR(env, env->tstate[env->tl] >> 32);
+ env->asi = (env->tstate[env->tl] >> 24) & 0xff;
+ env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
+ set_cwp(env->tstate[env->tl] & 0xff);
+}
+
+void do_retry(void)
+{
+ env->tl--;
+ env->pc = env->tpc[env->tl];
+ env->npc = env->tnpc[env->tl];
+ PUT_CCR(env, env->tstate[env->tl] >> 32);
+ env->asi = (env->tstate[env->tl] >> 24) & 0xff;
+ env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
+ set_cwp(env->tstate[env->tl] & 0xff);
+}
+#endif
+
+void set_cwp(int new_cwp)
+{
+ /* put the modified wrap registers at their proper location */
+ if (env->cwp == (NWINDOWS - 1))
+ memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
+ env->cwp = new_cwp;
+ /* put the wrap registers at their temporary location */
+ if (new_cwp == (NWINDOWS - 1))
+ memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
+ env->regwptr = env->regbase + (new_cwp * 16);
+ REGWPTR = env->regwptr;
+}
+
+void cpu_set_cwp(CPUState *env1, int new_cwp)
+{
+ CPUState *saved_env;
+#ifdef reg_REGWPTR
+ target_ulong *saved_regwptr;
+#endif
+
+ saved_env = env;
+#ifdef reg_REGWPTR
+ saved_regwptr = REGWPTR;
+#endif
+ env = env1;
+ set_cwp(new_cwp);
+ env = saved_env;
+#ifdef reg_REGWPTR
+ REGWPTR = saved_regwptr;
+#endif
+}
+
+#ifdef TARGET_SPARC64
+void do_interrupt(int intno)
+{
+#ifdef DEBUG_PCALL
+ if (loglevel & CPU_LOG_INT) {
+ static int count;
+ fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
+ count, intno,
+ env->pc,
+ env->npc, env->regwptr[6]);
+ cpu_dump_state(env, logfile, fprintf, 0);
+#if 0
+ {
+ int i;
+ uint8_t *ptr;
+
+ fprintf(logfile, " code=");
+ ptr = (uint8_t *)env->pc;
+ for(i = 0; i < 16; i++) {
+ fprintf(logfile, " %02x", ldub(ptr + i));
+ }
+ fprintf(logfile, "\n");
+ }
+#endif
+ count++;
+ }
+#endif
+#if !defined(CONFIG_USER_ONLY)
+ if (env->tl == MAXTL) {
+ cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
+ return;
+ }
+#endif
+ env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
+ ((env->pstate & 0xfff) << 8) | (env->cwp & 0xff);
+ env->tpc[env->tl] = env->pc;
+ env->tnpc[env->tl] = env->npc;
+ env->tt[env->tl] = intno;
+ env->pstate = PS_PEF | PS_PRIV | PS_AG;
+ env->tbr &= ~0x7fffULL;
+ env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
+ if (env->tl < MAXTL - 1) {
+ env->tl++;
+ } else {
+ env->pstate |= PS_RED;
+ if (env->tl != MAXTL)
+ env->tl++;
+ }
+ env->pc = env->tbr;
+ env->npc = env->pc + 4;
+ env->exception_index = 0;
+}
+#else
+void do_interrupt(int intno)
+{
+ int cwp;
+
+#ifdef DEBUG_PCALL
+ if (loglevel & CPU_LOG_INT) {
+ static int count;
+ fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
+ count, intno,
+ env->pc,
+ env->npc, env->regwptr[6]);
+ cpu_dump_state(env, logfile, fprintf, 0);
+#if 0
+ {
+ int i;
+ uint8_t *ptr;
+
+ fprintf(logfile, " code=");
+ ptr = (uint8_t *)env->pc;
+ for(i = 0; i < 16; i++) {
+ fprintf(logfile, " %02x", ldub(ptr + i));
+ }
+ fprintf(logfile, "\n");
+ }
+#endif
+ count++;
+ }
+#endif
+#if !defined(CONFIG_USER_ONLY)
+ if (env->psret == 0) {
+ cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
+ return;
+ }
+#endif
+ env->psret = 0;
+ cwp = (env->cwp - 1) & (NWINDOWS - 1);
+ set_cwp(cwp);
+ env->regwptr[9] = env->pc;
+ env->regwptr[10] = env->npc;
+ env->psrps = env->psrs;
+ env->psrs = 1;
+ env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
+ env->pc = env->tbr;
+ env->npc = env->pc + 4;
+ env->exception_index = 0;
+}
+#endif
+
+#if !defined(CONFIG_USER_ONLY)
+
+#define MMUSUFFIX _mmu
+#define GETPC() (__builtin_return_address(0))
+
+#define SHIFT 0
+#include "softmmu_template.h"
+
+#define SHIFT 1
+#include "softmmu_template.h"
+
+#define SHIFT 2
+#include "softmmu_template.h"
+
+#define SHIFT 3
+#include "softmmu_template.h"
+
+
+/* try to fill the TLB and return an exception if error. If retaddr is
+ NULL, it means that the function was called in C code (i.e. not
+ from generated code or from helper.c) */
+/* XXX: fix it to restore all registers */
+void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
+{
+ TranslationBlock *tb;
+ int ret;
+ unsigned long pc;
+ CPUState *saved_env;
+
+ /* XXX: hack to restore env in all cases, even if not called from
+ generated code */
+ saved_env = env;
+ env = cpu_single_env;
+
+ ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
+ if (ret) {
+ if (retaddr) {
+ /* now we have a real cpu fault */
+ pc = (unsigned long)retaddr;
+ tb = tb_find_pc(pc);
+ if (tb) {
+ /* the PC is inside the translated code. It means that we have
+ a virtual CPU fault */
+ cpu_restore_state(tb, env, pc, (void *)T2);
+ }
+ }
+ cpu_loop_exit();
+ }
+ env = saved_env;
+}
+
+#endif
diff --git a/target-sparc/op_mem.h b/target-sparc/op_mem.h
new file mode 100644
index 0000000..f5dbd26
--- /dev/null
+++ b/target-sparc/op_mem.h
@@ -0,0 +1,114 @@
+/*** Integer load ***/
+#define SPARC_LD_OP(name, qp) \
+void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
+{ \
+ T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0); \
+}
+
+#define SPARC_LD_OP_S(name, qp) \
+ void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
+ { \
+ T1 = (target_long)glue(qp, MEMSUFFIX)(T0); \
+ }
+
+#define SPARC_ST_OP(name, op) \
+void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \
+{ \
+ glue(op, MEMSUFFIX)(T0, T1); \
+}
+
+SPARC_LD_OP(ld, ldl);
+SPARC_LD_OP(ldub, ldub);
+SPARC_LD_OP(lduh, lduw);
+SPARC_LD_OP_S(ldsb, ldsb);
+SPARC_LD_OP_S(ldsh, ldsw);
+
+/*** Integer store ***/
+SPARC_ST_OP(st, stl);
+SPARC_ST_OP(stb, stb);
+SPARC_ST_OP(sth, stw);
+
+void OPPROTO glue(op_std, MEMSUFFIX)(void)
+{
+ glue(stl, MEMSUFFIX)(T0, T1);
+ glue(stl, MEMSUFFIX)((T0 + 4), T2);
+}
+
+void OPPROTO glue(op_ldstub, MEMSUFFIX)(void)
+{
+ T1 = glue(ldub, MEMSUFFIX)(T0);
+ glue(stb, MEMSUFFIX)(T0, 0xff); /* XXX: Should be Atomically */
+}
+
+void OPPROTO glue(op_swap, MEMSUFFIX)(void)
+{
+ target_ulong tmp = glue(ldl, MEMSUFFIX)(T0);
+ glue(stl, MEMSUFFIX)(T0, T1); /* XXX: Should be Atomically */
+ T1 = tmp;
+}
+
+void OPPROTO glue(op_ldd, MEMSUFFIX)(void)
+{
+ T1 = glue(ldl, MEMSUFFIX)(T0);
+ T0 = glue(ldl, MEMSUFFIX)((T0 + 4));
+}
+
+/*** Floating-point store ***/
+void OPPROTO glue(op_stf, MEMSUFFIX) (void)
+{
+ glue(stfl, MEMSUFFIX)(T0, FT0);
+}
+
+void OPPROTO glue(op_stdf, MEMSUFFIX) (void)
+{
+ glue(stfq, MEMSUFFIX)(T0, DT0);
+}
+
+/*** Floating-point load ***/
+void OPPROTO glue(op_ldf, MEMSUFFIX) (void)
+{
+ FT0 = glue(ldfl, MEMSUFFIX)(T0);
+}
+
+void OPPROTO glue(op_lddf, MEMSUFFIX) (void)
+{
+ DT0 = glue(ldfq, MEMSUFFIX)(T0);
+}
+
+#ifdef TARGET_SPARC64
+/* XXX: Should be Atomically */
+/* XXX: There are no cas[x] instructions, only cas[x]a */
+void OPPROTO glue(op_cas, MEMSUFFIX)(void)
+{
+ uint32_t tmp;
+
+ tmp = glue(ldl, MEMSUFFIX)(T0);
+ T2 &= 0xffffffffULL;
+ if (tmp == (T1 & 0xffffffffULL)) {
+ glue(stl, MEMSUFFIX)(T0, T2);
+ }
+ T2 = tmp;
+}
+
+void OPPROTO glue(op_casx, MEMSUFFIX)(void)
+{
+ uint64_t tmp;
+
+ // XXX
+ tmp = (uint64_t)glue(ldl, MEMSUFFIX)(T0) << 32;
+ tmp |= glue(ldl, MEMSUFFIX)(T0);
+ if (tmp == T1) {
+ glue(stq, MEMSUFFIX)(T0, T2);
+ }
+ T2 = tmp;
+}
+
+void OPPROTO glue(op_ldsw, MEMSUFFIX)(void)
+{
+ T1 = (int64_t)(glue(ldl, MEMSUFFIX)(T0) & 0xffffffff);
+}
+
+SPARC_LD_OP(ldx, ldq);
+SPARC_ST_OP(stx, stq);
+#endif
+#undef MEMSUFFIX
diff --git a/target-sparc/op_template.h b/target-sparc/op_template.h
new file mode 100644
index 0000000..ecf65fd
--- /dev/null
+++ b/target-sparc/op_template.h
@@ -0,0 +1,48 @@
+/*
+ * SPARC micro operations (templates for various register related
+ * operations)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+void OPPROTO glue(op_movl_T0_, REGNAME)(void)
+{
+ T0 = REG;
+}
+
+void OPPROTO glue(op_movl_T1_, REGNAME)(void)
+{
+ T1 = REG;
+}
+
+void OPPROTO glue(op_movl_T2_, REGNAME)(void)
+{
+ T2 = REG;
+}
+
+void OPPROTO glue(glue(op_movl_, REGNAME), _T0)(void)
+{
+ REG = T0;
+}
+
+void OPPROTO glue(glue(op_movl_, REGNAME), _T1)(void)
+{
+ REG = T1;
+}
+
+#undef REG
+#undef REGNAME
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
new file mode 100644
index 0000000..a522d77
--- /dev/null
+++ b/target-sparc/translate.c
@@ -0,0 +1,2845 @@
+/*
+ SPARC translation
+
+ Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
+ Copyright (C) 2003-2005 Fabrice Bellard
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ TODO-list:
+
+ Rest of V9 instructions, VIS instructions
+ NPC/PC static optimisations (use JUMP_TB when possible)
+ Optimize synthetic instructions
+ Optional alignment check
+ 128-bit float
+ Tagged add/sub
+*/
+
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "cpu.h"
+#include "exec-all.h"
+#include "disas.h"
+
+#define DEBUG_DISAS
+
+#define DYNAMIC_PC 1 /* dynamic pc value */
+#define JUMP_PC 2 /* dynamic pc value which takes only two values
+ according to jump_pc[T2] */
+
+typedef struct DisasContext {
+ target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
+ target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
+ target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
+ int is_br;
+ int mem_idx;
+ int fpu_enabled;
+ struct TranslationBlock *tb;
+} DisasContext;
+
+static uint16_t *gen_opc_ptr;
+static uint32_t *gen_opparam_ptr;
+extern FILE *logfile;
+extern int loglevel;
+
+enum {
+#define DEF(s,n,copy_size) INDEX_op_ ## s,
+#include "opc.h"
+#undef DEF
+ NB_OPS
+};
+
+#include "gen-op.h"
+
+// This function uses non-native bit order
+#define GET_FIELD(X, FROM, TO) \
+ ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
+
+// This function uses the order in the manuals, i.e. bit 0 is 2^0
+#define GET_FIELD_SP(X, FROM, TO) \
+ GET_FIELD(X, 31 - (TO), 31 - (FROM))
+
+#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
+#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
+
+#ifdef TARGET_SPARC64
+#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
+#else
+#define DFPREG(r) (r)
+#endif
+
+#ifdef USE_DIRECT_JUMP
+#define TBPARAM(x)
+#else
+#define TBPARAM(x) (long)(x)
+#endif
+
+static int sign_extend(int x, int len)
+{
+ len = 32 - len;
+ return (x << len) >> len;
+}
+
+#define IS_IMM (insn & (1<<13))
+
+static void disas_sparc_insn(DisasContext * dc);
+
+static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
+ {
+ gen_op_movl_g0_T0,
+ gen_op_movl_g1_T0,
+ gen_op_movl_g2_T0,
+ gen_op_movl_g3_T0,
+ gen_op_movl_g4_T0,
+ gen_op_movl_g5_T0,
+ gen_op_movl_g6_T0,
+ gen_op_movl_g7_T0,
+ gen_op_movl_o0_T0,
+ gen_op_movl_o1_T0,
+ gen_op_movl_o2_T0,
+ gen_op_movl_o3_T0,
+ gen_op_movl_o4_T0,
+ gen_op_movl_o5_T0,
+ gen_op_movl_o6_T0,
+ gen_op_movl_o7_T0,
+ gen_op_movl_l0_T0,
+ gen_op_movl_l1_T0,
+ gen_op_movl_l2_T0,
+ gen_op_movl_l3_T0,
+ gen_op_movl_l4_T0,
+ gen_op_movl_l5_T0,
+ gen_op_movl_l6_T0,
+ gen_op_movl_l7_T0,
+ gen_op_movl_i0_T0,
+ gen_op_movl_i1_T0,
+ gen_op_movl_i2_T0,
+ gen_op_movl_i3_T0,
+ gen_op_movl_i4_T0,
+ gen_op_movl_i5_T0,
+ gen_op_movl_i6_T0,
+ gen_op_movl_i7_T0,
+ },
+ {
+ gen_op_movl_g0_T1,
+ gen_op_movl_g1_T1,
+ gen_op_movl_g2_T1,
+ gen_op_movl_g3_T1,
+ gen_op_movl_g4_T1,
+ gen_op_movl_g5_T1,
+ gen_op_movl_g6_T1,
+ gen_op_movl_g7_T1,
+ gen_op_movl_o0_T1,
+ gen_op_movl_o1_T1,
+ gen_op_movl_o2_T1,
+ gen_op_movl_o3_T1,
+ gen_op_movl_o4_T1,
+ gen_op_movl_o5_T1,
+ gen_op_movl_o6_T1,
+ gen_op_movl_o7_T1,
+ gen_op_movl_l0_T1,
+ gen_op_movl_l1_T1,
+ gen_op_movl_l2_T1,
+ gen_op_movl_l3_T1,
+ gen_op_movl_l4_T1,
+ gen_op_movl_l5_T1,
+ gen_op_movl_l6_T1,
+ gen_op_movl_l7_T1,
+ gen_op_movl_i0_T1,
+ gen_op_movl_i1_T1,
+ gen_op_movl_i2_T1,
+ gen_op_movl_i3_T1,
+ gen_op_movl_i4_T1,
+ gen_op_movl_i5_T1,
+ gen_op_movl_i6_T1,
+ gen_op_movl_i7_T1,
+ }
+};
+
+static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
+ {
+ gen_op_movl_T0_g0,
+ gen_op_movl_T0_g1,
+ gen_op_movl_T0_g2,
+ gen_op_movl_T0_g3,
+ gen_op_movl_T0_g4,
+ gen_op_movl_T0_g5,
+ gen_op_movl_T0_g6,
+ gen_op_movl_T0_g7,
+ gen_op_movl_T0_o0,
+ gen_op_movl_T0_o1,
+ gen_op_movl_T0_o2,
+ gen_op_movl_T0_o3,
+ gen_op_movl_T0_o4,
+ gen_op_movl_T0_o5,
+ gen_op_movl_T0_o6,
+ gen_op_movl_T0_o7,
+ gen_op_movl_T0_l0,
+ gen_op_movl_T0_l1,
+ gen_op_movl_T0_l2,
+ gen_op_movl_T0_l3,
+ gen_op_movl_T0_l4,
+ gen_op_movl_T0_l5,
+ gen_op_movl_T0_l6,
+ gen_op_movl_T0_l7,
+ gen_op_movl_T0_i0,
+ gen_op_movl_T0_i1,
+ gen_op_movl_T0_i2,
+ gen_op_movl_T0_i3,
+ gen_op_movl_T0_i4,
+ gen_op_movl_T0_i5,
+ gen_op_movl_T0_i6,
+ gen_op_movl_T0_i7,
+ },
+ {
+ gen_op_movl_T1_g0,
+ gen_op_movl_T1_g1,
+ gen_op_movl_T1_g2,
+ gen_op_movl_T1_g3,
+ gen_op_movl_T1_g4,
+ gen_op_movl_T1_g5,
+ gen_op_movl_T1_g6,
+ gen_op_movl_T1_g7,
+ gen_op_movl_T1_o0,
+ gen_op_movl_T1_o1,
+ gen_op_movl_T1_o2,
+ gen_op_movl_T1_o3,
+ gen_op_movl_T1_o4,
+ gen_op_movl_T1_o5,
+ gen_op_movl_T1_o6,
+ gen_op_movl_T1_o7,
+ gen_op_movl_T1_l0,
+ gen_op_movl_T1_l1,
+ gen_op_movl_T1_l2,
+ gen_op_movl_T1_l3,
+ gen_op_movl_T1_l4,
+ gen_op_movl_T1_l5,
+ gen_op_movl_T1_l6,
+ gen_op_movl_T1_l7,
+ gen_op_movl_T1_i0,
+ gen_op_movl_T1_i1,
+ gen_op_movl_T1_i2,
+ gen_op_movl_T1_i3,
+ gen_op_movl_T1_i4,
+ gen_op_movl_T1_i5,
+ gen_op_movl_T1_i6,
+ gen_op_movl_T1_i7,
+ },
+ {
+ gen_op_movl_T2_g0,
+ gen_op_movl_T2_g1,
+ gen_op_movl_T2_g2,
+ gen_op_movl_T2_g3,
+ gen_op_movl_T2_g4,
+ gen_op_movl_T2_g5,
+ gen_op_movl_T2_g6,
+ gen_op_movl_T2_g7,
+ gen_op_movl_T2_o0,
+ gen_op_movl_T2_o1,
+ gen_op_movl_T2_o2,
+ gen_op_movl_T2_o3,
+ gen_op_movl_T2_o4,
+ gen_op_movl_T2_o5,
+ gen_op_movl_T2_o6,
+ gen_op_movl_T2_o7,
+ gen_op_movl_T2_l0,
+ gen_op_movl_T2_l1,
+ gen_op_movl_T2_l2,
+ gen_op_movl_T2_l3,
+ gen_op_movl_T2_l4,
+ gen_op_movl_T2_l5,
+ gen_op_movl_T2_l6,
+ gen_op_movl_T2_l7,
+ gen_op_movl_T2_i0,
+ gen_op_movl_T2_i1,
+ gen_op_movl_T2_i2,
+ gen_op_movl_T2_i3,
+ gen_op_movl_T2_i4,
+ gen_op_movl_T2_i5,
+ gen_op_movl_T2_i6,
+ gen_op_movl_T2_i7,
+ }
+};
+
+static GenOpFunc1 *gen_op_movl_TN_im[3] = {
+ gen_op_movl_T0_im,
+ gen_op_movl_T1_im,
+ gen_op_movl_T2_im
+};
+
+// Sign extending version
+static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
+ gen_op_movl_T0_sim,
+ gen_op_movl_T1_sim,
+ gen_op_movl_T2_sim
+};
+
+#ifdef TARGET_SPARC64
+#define GEN32(func, NAME) \
+static GenOpFunc *NAME ## _table [64] = { \
+NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
+NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
+NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
+NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
+NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
+NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
+NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
+NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
+NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
+NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
+NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
+NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
+}; \
+static inline void func(int n) \
+{ \
+ NAME ## _table[n](); \
+}
+#else
+#define GEN32(func, NAME) \
+static GenOpFunc *NAME ## _table [32] = { \
+NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
+NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
+NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
+NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
+NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
+NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
+NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
+NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
+}; \
+static inline void func(int n) \
+{ \
+ NAME ## _table[n](); \
+}
+#endif
+
+/* floating point registers moves */
+GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
+GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
+GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
+GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
+
+GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
+GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
+GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
+GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
+
+#ifdef TARGET_SPARC64
+// 'a' versions allowed to user depending on asi
+#if defined(CONFIG_USER_ONLY)
+#define supervisor(dc) 0
+#define gen_op_ldst(name) gen_op_##name##_raw()
+#define OP_LD_TABLE(width) \
+ static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
+ { \
+ int asi, offset; \
+ \
+ if (IS_IMM) { \
+ offset = GET_FIELD(insn, 25, 31); \
+ if (is_ld) \
+ gen_op_ld_asi_reg(offset, size, sign); \
+ else \
+ gen_op_st_asi_reg(offset, size, sign); \
+ return; \
+ } \
+ asi = GET_FIELD(insn, 19, 26); \
+ switch (asi) { \
+ case 0x80: /* Primary address space */ \
+ gen_op_##width##_raw(); \
+ break; \
+ case 0x82: /* Primary address space, non-faulting load */ \
+ gen_op_##width##_raw(); \
+ break; \
+ default: \
+ break; \
+ } \
+ }
+
+#else
+#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
+#define OP_LD_TABLE(width) \
+ static GenOpFunc *gen_op_##width[] = { \
+ &gen_op_##width##_user, \
+ &gen_op_##width##_kernel, \
+ }; \
+ \
+ static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
+ { \
+ int asi, offset; \
+ \
+ if (IS_IMM) { \
+ offset = GET_FIELD(insn, 25, 31); \
+ if (is_ld) \
+ gen_op_ld_asi_reg(offset, size, sign); \
+ else \
+ gen_op_st_asi_reg(offset, size, sign); \
+ return; \
+ } \
+ asi = GET_FIELD(insn, 19, 26); \
+ if (is_ld) \
+ gen_op_ld_asi(asi, size, sign); \
+ else \
+ gen_op_st_asi(asi, size, sign); \
+ }
+
+#define supervisor(dc) (dc->mem_idx == 1)
+#endif
+#else
+#if defined(CONFIG_USER_ONLY)
+#define gen_op_ldst(name) gen_op_##name##_raw()
+#define OP_LD_TABLE(width)
+#define supervisor(dc) 0
+#else
+#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
+#define OP_LD_TABLE(width) \
+static GenOpFunc *gen_op_##width[] = { \
+ &gen_op_##width##_user, \
+ &gen_op_##width##_kernel, \
+}; \
+ \
+static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
+{ \
+ int asi; \
+ \
+ asi = GET_FIELD(insn, 19, 26); \
+ switch (asi) { \
+ case 10: /* User data access */ \
+ gen_op_##width##_user(); \
+ break; \
+ case 11: /* Supervisor data access */ \
+ gen_op_##width##_kernel(); \
+ break; \
+ case 0x20 ... 0x2f: /* MMU passthrough */ \
+ if (is_ld) \
+ gen_op_ld_asi(asi, size, sign); \
+ else \
+ gen_op_st_asi(asi, size, sign); \
+ break; \
+ default: \
+ if (is_ld) \
+ gen_op_ld_asi(asi, size, sign); \
+ else \
+ gen_op_st_asi(asi, size, sign); \
+ break; \
+ } \
+}
+
+#define supervisor(dc) (dc->mem_idx == 1)
+#endif
+#endif
+
+OP_LD_TABLE(ld);
+OP_LD_TABLE(st);
+OP_LD_TABLE(ldub);
+OP_LD_TABLE(lduh);
+OP_LD_TABLE(ldsb);
+OP_LD_TABLE(ldsh);
+OP_LD_TABLE(stb);
+OP_LD_TABLE(sth);
+OP_LD_TABLE(std);
+OP_LD_TABLE(ldstub);
+OP_LD_TABLE(swap);
+OP_LD_TABLE(ldd);
+OP_LD_TABLE(stf);
+OP_LD_TABLE(stdf);
+OP_LD_TABLE(ldf);
+OP_LD_TABLE(lddf);
+
+#ifdef TARGET_SPARC64
+OP_LD_TABLE(ldsw);
+OP_LD_TABLE(ldx);
+OP_LD_TABLE(stx);
+OP_LD_TABLE(cas);
+OP_LD_TABLE(casx);
+#endif
+
+static inline void gen_movl_imm_TN(int reg, uint32_t imm)
+{
+ gen_op_movl_TN_im[reg](imm);
+}
+
+static inline void gen_movl_imm_T1(uint32_t val)
+{
+ gen_movl_imm_TN(1, val);
+}
+
+static inline void gen_movl_imm_T0(uint32_t val)
+{
+ gen_movl_imm_TN(0, val);
+}
+
+static inline void gen_movl_simm_TN(int reg, int32_t imm)
+{
+ gen_op_movl_TN_sim[reg](imm);
+}
+
+static inline void gen_movl_simm_T1(int32_t val)
+{
+ gen_movl_simm_TN(1, val);
+}
+
+static inline void gen_movl_simm_T0(int32_t val)
+{
+ gen_movl_simm_TN(0, val);
+}
+
+static inline void gen_movl_reg_TN(int reg, int t)
+{
+ if (reg)
+ gen_op_movl_reg_TN[t][reg] ();
+ else
+ gen_movl_imm_TN(t, 0);
+}
+
+static inline void gen_movl_reg_T0(int reg)
+{
+ gen_movl_reg_TN(reg, 0);
+}
+
+static inline void gen_movl_reg_T1(int reg)
+{
+ gen_movl_reg_TN(reg, 1);
+}
+
+static inline void gen_movl_reg_T2(int reg)
+{
+ gen_movl_reg_TN(reg, 2);
+}
+
+static inline void gen_movl_TN_reg(int reg, int t)
+{
+ if (reg)
+ gen_op_movl_TN_reg[t][reg] ();
+}
+
+static inline void gen_movl_T0_reg(int reg)
+{
+ gen_movl_TN_reg(reg, 0);
+}
+
+static inline void gen_movl_T1_reg(int reg)
+{
+ gen_movl_TN_reg(reg, 1);
+}
+
+static inline void gen_jmp_im(target_ulong pc)
+{
+#ifdef TARGET_SPARC64
+ if (pc == (uint32_t)pc) {
+ gen_op_jmp_im(pc);
+ } else {
+ gen_op_jmp_im64(pc >> 32, pc);
+ }
+#else
+ gen_op_jmp_im(pc);
+#endif
+}
+
+static inline void gen_movl_npc_im(target_ulong npc)
+{
+#ifdef TARGET_SPARC64
+ if (npc == (uint32_t)npc) {
+ gen_op_movl_npc_im(npc);
+ } else {
+ gen_op_movq_npc_im64(npc >> 32, npc);
+ }
+#else
+ gen_op_movl_npc_im(npc);
+#endif
+}
+
+static inline void gen_goto_tb(DisasContext *s, int tb_num,
+ target_ulong pc, target_ulong npc)
+{
+ TranslationBlock *tb;
+
+ tb = s->tb;
+ if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
+ (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
+ /* jump to same page: we can use a direct jump */
+ if (tb_num == 0)
+ gen_op_goto_tb0(TBPARAM(tb));
+ else
+ gen_op_goto_tb1(TBPARAM(tb));
+ gen_jmp_im(pc);
+ gen_movl_npc_im(npc);
+ gen_op_movl_T0_im((long)tb + tb_num);
+ gen_op_exit_tb();
+ } else {
+ /* jump to another page: currently not optimized */
+ gen_jmp_im(pc);
+ gen_movl_npc_im(npc);
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ }
+}
+
+static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
+{
+ int l1;
+
+ l1 = gen_new_label();
+
+ gen_op_jz_T2_label(l1);
+
+ gen_goto_tb(dc, 0, pc1, pc1 + 4);
+
+ gen_set_label(l1);
+ gen_goto_tb(dc, 1, pc2, pc2 + 4);
+}
+
+static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
+{
+ int l1;
+
+ l1 = gen_new_label();
+
+ gen_op_jz_T2_label(l1);
+
+ gen_goto_tb(dc, 0, pc2, pc1);
+
+ gen_set_label(l1);
+ gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
+}
+
+static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
+{
+ gen_goto_tb(dc, 0, pc, npc);
+}
+
+static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
+{
+ int l1, l2;
+
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ gen_op_jz_T2_label(l1);
+
+ gen_movl_npc_im(npc1);
+ gen_op_jmp_label(l2);
+
+ gen_set_label(l1);
+ gen_movl_npc_im(npc2);
+ gen_set_label(l2);
+}
+
+/* call this function before using T2 as it may have been set for a jump */
+static inline void flush_T2(DisasContext * dc)
+{
+ if (dc->npc == JUMP_PC) {
+ gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
+ dc->npc = DYNAMIC_PC;
+ }
+}
+
+static inline void save_npc(DisasContext * dc)
+{
+ if (dc->npc == JUMP_PC) {
+ gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
+ dc->npc = DYNAMIC_PC;
+ } else if (dc->npc != DYNAMIC_PC) {
+ gen_movl_npc_im(dc->npc);
+ }
+}
+
+static inline void save_state(DisasContext * dc)
+{
+ gen_jmp_im(dc->pc);
+ save_npc(dc);
+}
+
+static inline void gen_mov_pc_npc(DisasContext * dc)
+{
+ if (dc->npc == JUMP_PC) {
+ gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
+ gen_op_mov_pc_npc();
+ dc->pc = DYNAMIC_PC;
+ } else if (dc->npc == DYNAMIC_PC) {
+ gen_op_mov_pc_npc();
+ dc->pc = DYNAMIC_PC;
+ } else {
+ dc->pc = dc->npc;
+ }
+}
+
+static GenOpFunc * const gen_cond[2][16] = {
+ {
+ gen_op_eval_ba,
+ gen_op_eval_be,
+ gen_op_eval_ble,
+ gen_op_eval_bl,
+ gen_op_eval_bleu,
+ gen_op_eval_bcs,
+ gen_op_eval_bneg,
+ gen_op_eval_bvs,
+ gen_op_eval_bn,
+ gen_op_eval_bne,
+ gen_op_eval_bg,
+ gen_op_eval_bge,
+ gen_op_eval_bgu,
+ gen_op_eval_bcc,
+ gen_op_eval_bpos,
+ gen_op_eval_bvc,
+ },
+ {
+#ifdef TARGET_SPARC64
+ gen_op_eval_ba,
+ gen_op_eval_xbe,
+ gen_op_eval_xble,
+ gen_op_eval_xbl,
+ gen_op_eval_xbleu,
+ gen_op_eval_xbcs,
+ gen_op_eval_xbneg,
+ gen_op_eval_xbvs,
+ gen_op_eval_bn,
+ gen_op_eval_xbne,
+ gen_op_eval_xbg,
+ gen_op_eval_xbge,
+ gen_op_eval_xbgu,
+ gen_op_eval_xbcc,
+ gen_op_eval_xbpos,
+ gen_op_eval_xbvc,
+#endif
+ },
+};
+
+static GenOpFunc * const gen_fcond[4][16] = {
+ {
+ gen_op_eval_ba,
+ gen_op_eval_fbne,
+ gen_op_eval_fblg,
+ gen_op_eval_fbul,
+ gen_op_eval_fbl,
+ gen_op_eval_fbug,
+ gen_op_eval_fbg,
+ gen_op_eval_fbu,
+ gen_op_eval_bn,
+ gen_op_eval_fbe,
+ gen_op_eval_fbue,
+ gen_op_eval_fbge,
+ gen_op_eval_fbuge,
+ gen_op_eval_fble,
+ gen_op_eval_fbule,
+ gen_op_eval_fbo,
+ },
+#ifdef TARGET_SPARC64
+ {
+ gen_op_eval_ba,
+ gen_op_eval_fbne_fcc1,
+ gen_op_eval_fblg_fcc1,
+ gen_op_eval_fbul_fcc1,
+ gen_op_eval_fbl_fcc1,
+ gen_op_eval_fbug_fcc1,
+ gen_op_eval_fbg_fcc1,
+ gen_op_eval_fbu_fcc1,
+ gen_op_eval_bn,
+ gen_op_eval_fbe_fcc1,
+ gen_op_eval_fbue_fcc1,
+ gen_op_eval_fbge_fcc1,
+ gen_op_eval_fbuge_fcc1,
+ gen_op_eval_fble_fcc1,
+ gen_op_eval_fbule_fcc1,
+ gen_op_eval_fbo_fcc1,
+ },
+ {
+ gen_op_eval_ba,
+ gen_op_eval_fbne_fcc2,
+ gen_op_eval_fblg_fcc2,
+ gen_op_eval_fbul_fcc2,
+ gen_op_eval_fbl_fcc2,
+ gen_op_eval_fbug_fcc2,
+ gen_op_eval_fbg_fcc2,
+ gen_op_eval_fbu_fcc2,
+ gen_op_eval_bn,
+ gen_op_eval_fbe_fcc2,
+ gen_op_eval_fbue_fcc2,
+ gen_op_eval_fbge_fcc2,
+ gen_op_eval_fbuge_fcc2,
+ gen_op_eval_fble_fcc2,
+ gen_op_eval_fbule_fcc2,
+ gen_op_eval_fbo_fcc2,
+ },
+ {
+ gen_op_eval_ba,
+ gen_op_eval_fbne_fcc3,
+ gen_op_eval_fblg_fcc3,
+ gen_op_eval_fbul_fcc3,
+ gen_op_eval_fbl_fcc3,
+ gen_op_eval_fbug_fcc3,
+ gen_op_eval_fbg_fcc3,
+ gen_op_eval_fbu_fcc3,
+ gen_op_eval_bn,
+ gen_op_eval_fbe_fcc3,
+ gen_op_eval_fbue_fcc3,
+ gen_op_eval_fbge_fcc3,
+ gen_op_eval_fbuge_fcc3,
+ gen_op_eval_fble_fcc3,
+ gen_op_eval_fbule_fcc3,
+ gen_op_eval_fbo_fcc3,
+ },
+#else
+ {}, {}, {},
+#endif
+};
+
+#ifdef TARGET_SPARC64
+static void gen_cond_reg(int cond)
+{
+ switch (cond) {
+ case 0x1:
+ gen_op_eval_brz();
+ break;
+ case 0x2:
+ gen_op_eval_brlez();
+ break;
+ case 0x3:
+ gen_op_eval_brlz();
+ break;
+ case 0x5:
+ gen_op_eval_brnz();
+ break;
+ case 0x6:
+ gen_op_eval_brgz();
+ break;
+ default:
+ case 0x7:
+ gen_op_eval_brgez();
+ break;
+ }
+}
+#endif
+
+/* XXX: potentially incorrect if dynamic npc */
+static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
+{
+ unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
+ target_ulong target = dc->pc + offset;
+
+ if (cond == 0x0) {
+ /* unconditional not taken */
+ if (a) {
+ dc->pc = dc->npc + 4;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = dc->pc + 4;
+ }
+ } else if (cond == 0x8) {
+ /* unconditional taken */
+ if (a) {
+ dc->pc = target;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = target;
+ }
+ } else {
+ flush_T2(dc);
+ gen_cond[cc][cond]();
+ if (a) {
+ gen_branch_a(dc, (long)dc->tb, target, dc->npc);
+ dc->is_br = 1;
+ } else {
+ dc->pc = dc->npc;
+ dc->jump_pc[0] = target;
+ dc->jump_pc[1] = dc->npc + 4;
+ dc->npc = JUMP_PC;
+ }
+ }
+}
+
+/* XXX: potentially incorrect if dynamic npc */
+static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
+{
+ unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
+ target_ulong target = dc->pc + offset;
+
+ if (cond == 0x0) {
+ /* unconditional not taken */
+ if (a) {
+ dc->pc = dc->npc + 4;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = dc->pc + 4;
+ }
+ } else if (cond == 0x8) {
+ /* unconditional taken */
+ if (a) {
+ dc->pc = target;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = target;
+ }
+ } else {
+ flush_T2(dc);
+ gen_fcond[cc][cond]();
+ if (a) {
+ gen_branch_a(dc, (long)dc->tb, target, dc->npc);
+ dc->is_br = 1;
+ } else {
+ dc->pc = dc->npc;
+ dc->jump_pc[0] = target;
+ dc->jump_pc[1] = dc->npc + 4;
+ dc->npc = JUMP_PC;
+ }
+ }
+}
+
+#ifdef TARGET_SPARC64
+/* XXX: potentially incorrect if dynamic npc */
+static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
+{
+ unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
+ target_ulong target = dc->pc + offset;
+
+ flush_T2(dc);
+ gen_cond_reg(cond);
+ if (a) {
+ gen_branch_a(dc, (long)dc->tb, target, dc->npc);
+ dc->is_br = 1;
+ } else {
+ dc->pc = dc->npc;
+ dc->jump_pc[0] = target;
+ dc->jump_pc[1] = dc->npc + 4;
+ dc->npc = JUMP_PC;
+ }
+}
+
+static GenOpFunc * const gen_fcmps[4] = {
+ gen_op_fcmps,
+ gen_op_fcmps_fcc1,
+ gen_op_fcmps_fcc2,
+ gen_op_fcmps_fcc3,
+};
+
+static GenOpFunc * const gen_fcmpd[4] = {
+ gen_op_fcmpd,
+ gen_op_fcmpd_fcc1,
+ gen_op_fcmpd_fcc2,
+ gen_op_fcmpd_fcc3,
+};
+#endif
+
+static int gen_trap_ifnofpu(DisasContext * dc)
+{
+#if !defined(CONFIG_USER_ONLY)
+ if (!dc->fpu_enabled) {
+ save_state(dc);
+ gen_op_exception(TT_NFPU_INSN);
+ dc->is_br = 1;
+ return 1;
+ }
+#endif
+ return 0;
+}
+
+/* before an instruction, dc->pc must be static */
+static void disas_sparc_insn(DisasContext * dc)
+{
+ unsigned int insn, opc, rs1, rs2, rd;
+
+ insn = ldl_code(dc->pc);
+ opc = GET_FIELD(insn, 0, 1);
+
+ rd = GET_FIELD(insn, 2, 6);
+ switch (opc) {
+ case 0: /* branches/sethi */
+ {
+ unsigned int xop = GET_FIELD(insn, 7, 9);
+ int32_t target;
+ switch (xop) {
+#ifdef TARGET_SPARC64
+ case 0x1: /* V9 BPcc */
+ {
+ int cc;
+
+ target = GET_FIELD_SP(insn, 0, 18);
+ target = sign_extend(target, 18);
+ target <<= 2;
+ cc = GET_FIELD_SP(insn, 20, 21);
+ if (cc == 0)
+ do_branch(dc, target, insn, 0);
+ else if (cc == 2)
+ do_branch(dc, target, insn, 1);
+ else
+ goto illegal_insn;
+ goto jmp_insn;
+ }
+ case 0x3: /* V9 BPr */
+ {
+ target = GET_FIELD_SP(insn, 0, 13) |
+ (GET_FIELD_SP(insn, 20, 21) << 14);
+ target = sign_extend(target, 16);
+ target <<= 2;
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ do_branch_reg(dc, target, insn);
+ goto jmp_insn;
+ }
+ case 0x5: /* V9 FBPcc */
+ {
+ int cc = GET_FIELD_SP(insn, 20, 21);
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ target = GET_FIELD_SP(insn, 0, 18);
+ target = sign_extend(target, 19);
+ target <<= 2;
+ do_fbranch(dc, target, insn, cc);
+ goto jmp_insn;
+ }
+#endif
+ case 0x2: /* BN+x */
+ {
+ target = GET_FIELD(insn, 10, 31);
+ target = sign_extend(target, 22);
+ target <<= 2;
+ do_branch(dc, target, insn, 0);
+ goto jmp_insn;
+ }
+ case 0x6: /* FBN+x */
+ {
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ target = GET_FIELD(insn, 10, 31);
+ target = sign_extend(target, 22);
+ target <<= 2;
+ do_fbranch(dc, target, insn, 0);
+ goto jmp_insn;
+ }
+ case 0x4: /* SETHI */
+#define OPTIM
+#if defined(OPTIM)
+ if (rd) { // nop
+#endif
+ uint32_t value = GET_FIELD(insn, 10, 31);
+ gen_movl_imm_T0(value << 10);
+ gen_movl_T0_reg(rd);
+#if defined(OPTIM)
+ }
+#endif
+ break;
+ case 0x0: /* UNIMPL */
+ default:
+ goto illegal_insn;
+ }
+ break;
+ }
+ break;
+ case 1:
+ /*CALL*/ {
+ target_long target = GET_FIELDs(insn, 2, 31) << 2;
+
+#ifdef TARGET_SPARC64
+ if (dc->pc == (uint32_t)dc->pc) {
+ gen_op_movl_T0_im(dc->pc);
+ } else {
+ gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
+ }
+#else
+ gen_op_movl_T0_im(dc->pc);
+#endif
+ gen_movl_T0_reg(15);
+ target += dc->pc;
+ gen_mov_pc_npc(dc);
+ dc->npc = target;
+ }
+ goto jmp_insn;
+ case 2: /* FPU & Logical Operations */
+ {
+ unsigned int xop = GET_FIELD(insn, 7, 12);
+ if (xop == 0x3a) { /* generate trap */
+ int cond;
+
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) {
+ rs2 = GET_FIELD(insn, 25, 31);
+#if defined(OPTIM)
+ if (rs2 != 0) {
+#endif
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ } else {
+ rs2 = GET_FIELD(insn, 27, 31);
+#if defined(OPTIM)
+ if (rs2 != 0) {
+#endif
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ }
+ cond = GET_FIELD(insn, 3, 6);
+ if (cond == 0x8) {
+ save_state(dc);
+ gen_op_trap_T0();
+ } else if (cond != 0) {
+#ifdef TARGET_SPARC64
+ /* V9 icc/xcc */
+ int cc = GET_FIELD_SP(insn, 11, 12);
+ flush_T2(dc);
+ save_state(dc);
+ if (cc == 0)
+ gen_cond[0][cond]();
+ else if (cc == 2)
+ gen_cond[1][cond]();
+ else
+ goto illegal_insn;
+#else
+ flush_T2(dc);
+ save_state(dc);
+ gen_cond[0][cond]();
+#endif
+ gen_op_trapcc_T0();
+ }
+ gen_op_next_insn();
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ dc->is_br = 1;
+ goto jmp_insn;
+ } else if (xop == 0x28) {
+ rs1 = GET_FIELD(insn, 13, 17);
+ switch(rs1) {
+ case 0: /* rdy */
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
+ gen_movl_T0_reg(rd);
+ break;
+ case 15: /* stbar / V9 membar */
+ break; /* no effect? */
+#ifdef TARGET_SPARC64
+ case 0x2: /* V9 rdccr */
+ gen_op_rdccr();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x3: /* V9 rdasi */
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x4: /* V9 rdtick */
+ gen_op_rdtick();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x5: /* V9 rdpc */
+ if (dc->pc == (uint32_t)dc->pc) {
+ gen_op_movl_T0_im(dc->pc);
+ } else {
+ gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
+ }
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x6: /* V9 rdfprs */
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x13: /* Graphics Status */
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x17: /* Tick compare */
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x18: /* System tick */
+ gen_op_rdtick(); // XXX
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x19: /* System tick compare */
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x10: /* Performance Control */
+ case 0x11: /* Performance Instrumentation Counter */
+ case 0x12: /* Dispatch Control */
+ case 0x14: /* Softint set, WO */
+ case 0x15: /* Softint clear, WO */
+ case 0x16: /* Softint write */
+#endif
+ default:
+ goto illegal_insn;
+ }
+#if !defined(CONFIG_USER_ONLY)
+#ifndef TARGET_SPARC64
+ } else if (xop == 0x29) { /* rdpsr / V9 unimp */
+ if (!supervisor(dc))
+ goto priv_insn;
+ gen_op_rdpsr();
+ gen_movl_T0_reg(rd);
+ break;
+#endif
+ } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
+ if (!supervisor(dc))
+ goto priv_insn;
+#ifdef TARGET_SPARC64
+ rs1 = GET_FIELD(insn, 13, 17);
+ switch (rs1) {
+ case 0: // tpc
+ gen_op_rdtpc();
+ break;
+ case 1: // tnpc
+ gen_op_rdtnpc();
+ break;
+ case 2: // tstate
+ gen_op_rdtstate();
+ break;
+ case 3: // tt
+ gen_op_rdtt();
+ break;
+ case 4: // tick
+ gen_op_rdtick();
+ break;
+ case 5: // tba
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+ break;
+ case 6: // pstate
+ gen_op_rdpstate();
+ break;
+ case 7: // tl
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
+ break;
+ case 8: // pil
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
+ break;
+ case 9: // cwp
+ gen_op_rdcwp();
+ break;
+ case 10: // cansave
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
+ break;
+ case 11: // canrestore
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
+ break;
+ case 12: // cleanwin
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
+ break;
+ case 13: // otherwin
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
+ break;
+ case 14: // wstate
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
+ break;
+ case 31: // ver
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
+ break;
+ case 15: // fq
+ default:
+ goto illegal_insn;
+ }
+#else
+ gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
+#endif
+ gen_movl_T0_reg(rd);
+ break;
+ } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
+#ifdef TARGET_SPARC64
+ gen_op_flushw();
+#else
+ if (!supervisor(dc))
+ goto priv_insn;
+ gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
+ gen_movl_T0_reg(rd);
+#endif
+ break;
+#endif
+ } else if (xop == 0x34) { /* FPU Operations */
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ rs1 = GET_FIELD(insn, 13, 17);
+ rs2 = GET_FIELD(insn, 27, 31);
+ xop = GET_FIELD(insn, 18, 26);
+ switch (xop) {
+ case 0x1: /* fmovs */
+ gen_op_load_fpr_FT0(rs2);
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x5: /* fnegs */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fnegs();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x9: /* fabss */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fabss();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x29: /* fsqrts */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fsqrts();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x2a: /* fsqrtd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fsqrtd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x2b: /* fsqrtq */
+ goto nfpu_insn;
+ case 0x41:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fadds();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x42:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_faddd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x43: /* faddq */
+ goto nfpu_insn;
+ case 0x45:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fsubs();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x46:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fsubd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x47: /* fsubq */
+ goto nfpu_insn;
+ case 0x49:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fmuls();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x4a:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fmuld();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x4b: /* fmulq */
+ goto nfpu_insn;
+ case 0x4d:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fdivs();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x4e:
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fdivd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x4f: /* fdivq */
+ goto nfpu_insn;
+ case 0x69:
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fsmuld();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x6e: /* fdmulq */
+ goto nfpu_insn;
+ case 0xc4:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fitos();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xc6:
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fdtos();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xc7: /* fqtos */
+ goto nfpu_insn;
+ case 0xc8:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fitod();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xc9:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fstod();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xcb: /* fqtod */
+ goto nfpu_insn;
+ case 0xcc: /* fitoq */
+ goto nfpu_insn;
+ case 0xcd: /* fstoq */
+ goto nfpu_insn;
+ case 0xce: /* fdtoq */
+ goto nfpu_insn;
+ case 0xd1:
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fstoi();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xd2:
+ gen_op_load_fpr_DT1(rs2);
+ gen_op_fdtoi();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0xd3: /* fqtoi */
+ goto nfpu_insn;
+#ifdef TARGET_SPARC64
+ case 0x2: /* V9 fmovd */
+ gen_op_load_fpr_DT0(DFPREG(rs2));
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x6: /* V9 fnegd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fnegd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xa: /* V9 fabsd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fabsd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x81: /* V9 fstox */
+ gen_op_load_fpr_FT1(rs2);
+ gen_op_fstox();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x82: /* V9 fdtox */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fdtox();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x84: /* V9 fxtos */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fxtos();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x88: /* V9 fxtod */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_op_fxtod();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x3: /* V9 fmovq */
+ case 0x7: /* V9 fnegq */
+ case 0xb: /* V9 fabsq */
+ case 0x83: /* V9 fqtox */
+ case 0x8c: /* V9 fxtoq */
+ goto nfpu_insn;
+#endif
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop == 0x35) { /* FPU Operations */
+#ifdef TARGET_SPARC64
+ int cond;
+#endif
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ rs1 = GET_FIELD(insn, 13, 17);
+ rs2 = GET_FIELD(insn, 27, 31);
+ xop = GET_FIELD(insn, 18, 26);
+#ifdef TARGET_SPARC64
+ if ((xop & 0x11f) == 0x005) { // V9 fmovsr
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ flush_T2(dc);
+ gen_cond_reg(cond);
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ gen_cond_reg(cond);
+ gen_op_fmovs_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
+ goto nfpu_insn;
+ }
+#endif
+ switch (xop) {
+#ifdef TARGET_SPARC64
+ case 0x001: /* V9 fmovscc %fcc0 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[0][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x002: /* V9 fmovdcc %fcc0 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[0][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x003: /* V9 fmovqcc %fcc0 */
+ goto nfpu_insn;
+ case 0x041: /* V9 fmovscc %fcc1 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[1][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x042: /* V9 fmovdcc %fcc1 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[1][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x043: /* V9 fmovqcc %fcc1 */
+ goto nfpu_insn;
+ case 0x081: /* V9 fmovscc %fcc2 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[2][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x082: /* V9 fmovdcc %fcc2 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[2][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x083: /* V9 fmovqcc %fcc2 */
+ goto nfpu_insn;
+ case 0x0c1: /* V9 fmovscc %fcc3 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_fcond[3][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x0c2: /* V9 fmovdcc %fcc3 */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_fcond[3][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x0c3: /* V9 fmovqcc %fcc3 */
+ goto nfpu_insn;
+ case 0x101: /* V9 fmovscc %icc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_cond[0][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x102: /* V9 fmovdcc %icc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_cond[0][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x103: /* V9 fmovqcc %icc */
+ goto nfpu_insn;
+ case 0x181: /* V9 fmovscc %xcc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_FT0(rd);
+ gen_op_load_fpr_FT1(rs2);
+ flush_T2(dc);
+ gen_cond[1][cond]();
+ gen_op_fmovs_cc();
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x182: /* V9 fmovdcc %xcc */
+ cond = GET_FIELD_SP(insn, 14, 17);
+ gen_op_load_fpr_DT0(rd);
+ gen_op_load_fpr_DT1(rs2);
+ flush_T2(dc);
+ gen_cond[1][cond]();
+ gen_op_fmovd_cc();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ case 0x183: /* V9 fmovqcc %xcc */
+ goto nfpu_insn;
+#endif
+ case 0x51: /* V9 %fcc */
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+#ifdef TARGET_SPARC64
+ gen_fcmps[rd & 3]();
+#else
+ gen_op_fcmps();
+#endif
+ break;
+ case 0x52: /* V9 %fcc */
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+#ifdef TARGET_SPARC64
+ gen_fcmpd[rd & 3]();
+#else
+ gen_op_fcmpd();
+#endif
+ break;
+ case 0x53: /* fcmpq */
+ goto nfpu_insn;
+ case 0x55: /* fcmpes, V9 %fcc */
+ gen_op_load_fpr_FT0(rs1);
+ gen_op_load_fpr_FT1(rs2);
+#ifdef TARGET_SPARC64
+ gen_fcmps[rd & 3]();
+#else
+ gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
+#endif
+ break;
+ case 0x56: /* fcmped, V9 %fcc */
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+#ifdef TARGET_SPARC64
+ gen_fcmpd[rd & 3]();
+#else
+ gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
+#endif
+ break;
+ case 0x57: /* fcmpeq */
+ goto nfpu_insn;
+ default:
+ goto illegal_insn;
+ }
+#if defined(OPTIM)
+ } else if (xop == 0x2) {
+ // clr/mov shortcut
+
+ rs1 = GET_FIELD(insn, 13, 17);
+ if (rs1 == 0) {
+ // or %g0, x, y -> mov T1, x; mov y, T1
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
+ gen_movl_simm_T1(rs2);
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_movl_T1_reg(rd);
+ } else {
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ // or x, #0, y -> mov T1, x; mov y, T1
+ rs2 = GET_FIELDs(insn, 19, 31);
+ if (rs2 != 0) {
+ gen_movl_simm_T1(rs2);
+ gen_op_or_T1_T0();
+ }
+ } else { /* register */
+ // or x, %g0, y -> mov T1, x; mov y, T1
+ rs2 = GET_FIELD(insn, 27, 31);
+ if (rs2 != 0) {
+ gen_movl_reg_T1(rs2);
+ gen_op_or_T1_T0();
+ }
+ }
+ gen_movl_T0_reg(rd);
+ }
+#endif
+#ifdef TARGET_SPARC64
+ } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 20, 31);
+ gen_movl_simm_T1(rs2);
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_op_sll();
+ gen_movl_T0_reg(rd);
+ } else if (xop == 0x26) { /* srl, V9 srlx */
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 20, 31);
+ gen_movl_simm_T1(rs2);
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+ gen_movl_reg_T1(rs2);
+ }
+ if (insn & (1 << 12))
+ gen_op_srlx();
+ else
+ gen_op_srl();
+ gen_movl_T0_reg(rd);
+ } else if (xop == 0x27) { /* sra, V9 srax */
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 20, 31);
+ gen_movl_simm_T1(rs2);
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+ gen_movl_reg_T1(rs2);
+ }
+ if (insn & (1 << 12))
+ gen_op_srax();
+ else
+ gen_op_sra();
+ gen_movl_T0_reg(rd);
+#endif
+ } else if (xop < 0x38) {
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
+ gen_movl_simm_T1(rs2);
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+ gen_movl_reg_T1(rs2);
+ }
+ if (xop < 0x20) {
+ switch (xop & ~0x10) {
+ case 0x0:
+ if (xop & 0x10)
+ gen_op_add_T1_T0_cc();
+ else
+ gen_op_add_T1_T0();
+ break;
+ case 0x1:
+ gen_op_and_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0x2:
+ gen_op_or_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0x3:
+ gen_op_xor_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0x4:
+ if (xop & 0x10)
+ gen_op_sub_T1_T0_cc();
+ else
+ gen_op_sub_T1_T0();
+ break;
+ case 0x5:
+ gen_op_andn_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0x6:
+ gen_op_orn_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0x7:
+ gen_op_xnor_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0x8:
+ if (xop & 0x10)
+ gen_op_addx_T1_T0_cc();
+ else
+ gen_op_addx_T1_T0();
+ break;
+#ifdef TARGET_SPARC64
+ case 0x9: /* V9 mulx */
+ gen_op_mulx_T1_T0();
+ break;
+#endif
+ case 0xa:
+ gen_op_umul_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0xb:
+ gen_op_smul_T1_T0();
+ if (xop & 0x10)
+ gen_op_logic_T0_cc();
+ break;
+ case 0xc:
+ if (xop & 0x10)
+ gen_op_subx_T1_T0_cc();
+ else
+ gen_op_subx_T1_T0();
+ break;
+#ifdef TARGET_SPARC64
+ case 0xd: /* V9 udivx */
+ gen_op_udivx_T1_T0();
+ break;
+#endif
+ case 0xe:
+ gen_op_udiv_T1_T0();
+ if (xop & 0x10)
+ gen_op_div_cc();
+ break;
+ case 0xf:
+ gen_op_sdiv_T1_T0();
+ if (xop & 0x10)
+ gen_op_div_cc();
+ break;
+ default:
+ goto illegal_insn;
+ }
+ gen_movl_T0_reg(rd);
+ } else {
+ switch (xop) {
+ case 0x20: /* taddcc */
+ case 0x21: /* tsubcc */
+ case 0x22: /* taddcctv */
+ case 0x23: /* tsubcctv */
+ goto illegal_insn;
+ case 0x24: /* mulscc */
+ gen_op_mulscc_T1_T0();
+ gen_movl_T0_reg(rd);
+ break;
+#ifndef TARGET_SPARC64
+ case 0x25: /* sll */
+ gen_op_sll();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x26: /* srl */
+ gen_op_srl();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x27: /* sra */
+ gen_op_sra();
+ gen_movl_T0_reg(rd);
+ break;
+#endif
+ case 0x30:
+ {
+ switch(rd) {
+ case 0: /* wry */
+ gen_op_xor_T1_T0();
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
+ break;
+#ifdef TARGET_SPARC64
+ case 0x2: /* V9 wrccr */
+ gen_op_wrccr();
+ break;
+ case 0x3: /* V9 wrasi */
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
+ break;
+ case 0x6: /* V9 wrfprs */
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
+ break;
+ case 0xf: /* V9 sir, nop if user */
+#if !defined(CONFIG_USER_ONLY)
+ if (supervisor(dc))
+ gen_op_sir();
+#endif
+ break;
+ case 0x13: /* Graphics Status */
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
+ break;
+ case 0x17: /* Tick compare */
+#if !defined(CONFIG_USER_ONLY)
+ if (!supervisor(dc))
+ goto illegal_insn;
+#endif
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
+ break;
+ case 0x18: /* System tick */
+#if !defined(CONFIG_USER_ONLY)
+ if (!supervisor(dc))
+ goto illegal_insn;
+#endif
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
+ break;
+ case 0x19: /* System tick compare */
+#if !defined(CONFIG_USER_ONLY)
+ if (!supervisor(dc))
+ goto illegal_insn;
+#endif
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
+ break;
+
+ case 0x10: /* Performance Control */
+ case 0x11: /* Performance Instrumentation Counter */
+ case 0x12: /* Dispatch Control */
+ case 0x14: /* Softint set */
+ case 0x15: /* Softint clear */
+ case 0x16: /* Softint write */
+#endif
+ default:
+ goto illegal_insn;
+ }
+ }
+ break;
+#if !defined(CONFIG_USER_ONLY)
+ case 0x31: /* wrpsr, V9 saved, restored */
+ {
+ if (!supervisor(dc))
+ goto priv_insn;
+#ifdef TARGET_SPARC64
+ switch (rd) {
+ case 0:
+ gen_op_saved();
+ break;
+ case 1:
+ gen_op_restored();
+ break;
+ default:
+ goto illegal_insn;
+ }
+#else
+ gen_op_xor_T1_T0();
+ gen_op_wrpsr();
+ save_state(dc);
+ gen_op_next_insn();
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ dc->is_br = 1;
+#endif
+ }
+ break;
+ case 0x32: /* wrwim, V9 wrpr */
+ {
+ if (!supervisor(dc))
+ goto priv_insn;
+ gen_op_xor_T1_T0();
+#ifdef TARGET_SPARC64
+ switch (rd) {
+ case 0: // tpc
+ gen_op_wrtpc();
+ break;
+ case 1: // tnpc
+ gen_op_wrtnpc();
+ break;
+ case 2: // tstate
+ gen_op_wrtstate();
+ break;
+ case 3: // tt
+ gen_op_wrtt();
+ break;
+ case 4: // tick
+ gen_op_wrtick();
+ break;
+ case 5: // tba
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+ break;
+ case 6: // pstate
+ gen_op_wrpstate();
+ save_state(dc);
+ gen_op_next_insn();
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ dc->is_br = 1;
+ break;
+ case 7: // tl
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
+ break;
+ case 8: // pil
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
+ break;
+ case 9: // cwp
+ gen_op_wrcwp();
+ break;
+ case 10: // cansave
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
+ break;
+ case 11: // canrestore
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
+ break;
+ case 12: // cleanwin
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
+ break;
+ case 13: // otherwin
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
+ break;
+ case 14: // wstate
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
+ break;
+ default:
+ goto illegal_insn;
+ }
+#else
+ gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
+#endif
+ }
+ break;
+#ifndef TARGET_SPARC64
+ case 0x33: /* wrtbr, V9 unimp */
+ {
+ if (!supervisor(dc))
+ goto priv_insn;
+ gen_op_xor_T1_T0();
+ gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
+ }
+ break;
+#endif
+#endif
+#ifdef TARGET_SPARC64
+ case 0x2c: /* V9 movcc */
+ {
+ int cc = GET_FIELD_SP(insn, 11, 12);
+ int cond = GET_FIELD_SP(insn, 14, 17);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELD_SPs(insn, 0, 10);
+ gen_movl_simm_T1(rs2);
+ }
+ else {
+ rs2 = GET_FIELD_SP(insn, 0, 4);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_movl_reg_T0(rd);
+ flush_T2(dc);
+ if (insn & (1 << 18)) {
+ if (cc == 0)
+ gen_cond[0][cond]();
+ else if (cc == 2)
+ gen_cond[1][cond]();
+ else
+ goto illegal_insn;
+ } else {
+ gen_fcond[cc][cond]();
+ }
+ gen_op_mov_cc();
+ gen_movl_T0_reg(rd);
+ break;
+ }
+ case 0x2d: /* V9 sdivx */
+ gen_op_sdivx_T1_T0();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x2e: /* V9 popc */
+ {
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELD_SPs(insn, 0, 12);
+ gen_movl_simm_T1(rs2);
+ // XXX optimize: popc(constant)
+ }
+ else {
+ rs2 = GET_FIELD_SP(insn, 0, 4);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_op_popc();
+ gen_movl_T0_reg(rd);
+ }
+ case 0x2f: /* V9 movr */
+ {
+ int cond = GET_FIELD_SP(insn, 10, 12);
+ rs1 = GET_FIELD(insn, 13, 17);
+ flush_T2(dc);
+ gen_movl_reg_T0(rs1);
+ gen_cond_reg(cond);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELD_SPs(insn, 0, 10);
+ gen_movl_simm_T1(rs2);
+ }
+ else {
+ rs2 = GET_FIELD_SP(insn, 0, 4);
+ gen_movl_reg_T1(rs2);
+ }
+ gen_movl_reg_T0(rd);
+ gen_op_mov_cc();
+ gen_movl_T0_reg(rd);
+ break;
+ }
+ case 0x36: /* UltraSparc shutdown, VIS */
+ {
+ int opf = GET_FIELD_SP(insn, 5, 13);
+ rs1 = GET_FIELD(insn, 13, 17);
+ rs2 = GET_FIELD(insn, 27, 31);
+
+ switch (opf) {
+ case 0x018: /* VIS I alignaddr */
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ gen_movl_reg_T0(rs1);
+ gen_movl_reg_T1(rs2);
+ gen_op_alignaddr();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x01a: /* VIS I alignaddrl */
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ // XXX
+ break;
+ case 0x048: /* VIS I faligndata */
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ gen_op_load_fpr_DT0(rs1);
+ gen_op_load_fpr_DT1(rs2);
+ gen_op_faligndata();
+ gen_op_store_DT0_fpr(rd);
+ break;
+ default:
+ goto illegal_insn;
+ }
+ break;
+ }
+#endif
+ default:
+ goto illegal_insn;
+ }
+ }
+#ifdef TARGET_SPARC64
+ } else if (xop == 0x39) { /* V9 return */
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
+#if defined(OPTIM)
+ if (rs2) {
+#endif
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+#if defined(OPTIM)
+ if (rs2) {
+#endif
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ }
+ gen_op_restore();
+ gen_mov_pc_npc(dc);
+ gen_op_movl_npc_T0();
+ dc->npc = DYNAMIC_PC;
+ goto jmp_insn;
+#endif
+ } else {
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
+#if defined(OPTIM)
+ if (rs2) {
+#endif
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+#if defined(OPTIM)
+ if (rs2) {
+#endif
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ }
+ switch (xop) {
+ case 0x38: /* jmpl */
+ {
+ if (rd != 0) {
+#ifdef TARGET_SPARC64
+ if (dc->pc == (uint32_t)dc->pc) {
+ gen_op_movl_T1_im(dc->pc);
+ } else {
+ gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
+ }
+#else
+ gen_op_movl_T1_im(dc->pc);
+#endif
+ gen_movl_T1_reg(rd);
+ }
+ gen_mov_pc_npc(dc);
+ gen_op_movl_npc_T0();
+ dc->npc = DYNAMIC_PC;
+ }
+ goto jmp_insn;
+#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
+ case 0x39: /* rett, V9 return */
+ {
+ if (!supervisor(dc))
+ goto priv_insn;
+ gen_mov_pc_npc(dc);
+ gen_op_movl_npc_T0();
+ dc->npc = DYNAMIC_PC;
+ gen_op_rett();
+ }
+ goto jmp_insn;
+#endif
+ case 0x3b: /* flush */
+ gen_op_flush_T0();
+ break;
+ case 0x3c: /* save */
+ save_state(dc);
+ gen_op_save();
+ gen_movl_T0_reg(rd);
+ break;
+ case 0x3d: /* restore */
+ save_state(dc);
+ gen_op_restore();
+ gen_movl_T0_reg(rd);
+ break;
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
+ case 0x3e: /* V9 done/retry */
+ {
+ switch (rd) {
+ case 0:
+ if (!supervisor(dc))
+ goto priv_insn;
+ dc->npc = DYNAMIC_PC;
+ dc->pc = DYNAMIC_PC;
+ gen_op_done();
+ goto jmp_insn;
+ case 1:
+ if (!supervisor(dc))
+ goto priv_insn;
+ dc->npc = DYNAMIC_PC;
+ dc->pc = DYNAMIC_PC;
+ gen_op_retry();
+ goto jmp_insn;
+ default:
+ goto illegal_insn;
+ }
+ }
+ break;
+#endif
+ default:
+ goto illegal_insn;
+ }
+ }
+ break;
+ }
+ break;
+ case 3: /* load/store instructions */
+ {
+ unsigned int xop = GET_FIELD(insn, 7, 12);
+ rs1 = GET_FIELD(insn, 13, 17);
+ gen_movl_reg_T0(rs1);
+ if (IS_IMM) { /* immediate */
+ rs2 = GET_FIELDs(insn, 19, 31);
+#if defined(OPTIM)
+ if (rs2 != 0) {
+#endif
+ gen_movl_simm_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ } else { /* register */
+ rs2 = GET_FIELD(insn, 27, 31);
+#if defined(OPTIM)
+ if (rs2 != 0) {
+#endif
+ gen_movl_reg_T1(rs2);
+ gen_op_add_T1_T0();
+#if defined(OPTIM)
+ }
+#endif
+ }
+ if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
+ (xop > 0x17 && xop < 0x1d ) || \
+ (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
+ switch (xop) {
+ case 0x0: /* load word */
+ gen_op_ldst(ld);
+ break;
+ case 0x1: /* load unsigned byte */
+ gen_op_ldst(ldub);
+ break;
+ case 0x2: /* load unsigned halfword */
+ gen_op_ldst(lduh);
+ break;
+ case 0x3: /* load double word */
+ gen_op_ldst(ldd);
+ gen_movl_T0_reg(rd + 1);
+ break;
+ case 0x9: /* load signed byte */
+ gen_op_ldst(ldsb);
+ break;
+ case 0xa: /* load signed halfword */
+ gen_op_ldst(ldsh);
+ break;
+ case 0xd: /* ldstub -- XXX: should be atomically */
+ gen_op_ldst(ldstub);
+ break;
+ case 0x0f: /* swap register with memory. Also atomically */
+ gen_movl_reg_T1(rd);
+ gen_op_ldst(swap);
+ break;
+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+ case 0x10: /* load word alternate */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_lda(insn, 1, 4, 0);
+ break;
+ case 0x11: /* load unsigned byte alternate */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_lduba(insn, 1, 1, 0);
+ break;
+ case 0x12: /* load unsigned halfword alternate */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_lduha(insn, 1, 2, 0);
+ break;
+ case 0x13: /* load double word alternate */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_ldda(insn, 1, 8, 0);
+ gen_movl_T0_reg(rd + 1);
+ break;
+ case 0x19: /* load signed byte alternate */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_ldsba(insn, 1, 1, 1);
+ break;
+ case 0x1a: /* load signed halfword alternate */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_ldsha(insn, 1, 2 ,1);
+ break;
+ case 0x1d: /* ldstuba -- XXX: should be atomically */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_ldstuba(insn, 1, 1, 0);
+ break;
+ case 0x1f: /* swap reg with alt. memory. Also atomically */
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_movl_reg_T1(rd);
+ gen_op_swapa(insn, 1, 4, 0);
+ break;
+
+#ifndef TARGET_SPARC64
+ /* avoid warnings */
+ (void) &gen_op_stfa;
+ (void) &gen_op_stdfa;
+ (void) &gen_op_ldfa;
+ (void) &gen_op_lddfa;
+#else
+#if !defined(CONFIG_USER_ONLY)
+ (void) &gen_op_cas;
+ (void) &gen_op_casx;
+#endif
+#endif
+#endif
+#ifdef TARGET_SPARC64
+ case 0x08: /* V9 ldsw */
+ gen_op_ldst(ldsw);
+ break;
+ case 0x0b: /* V9 ldx */
+ gen_op_ldst(ldx);
+ break;
+ case 0x18: /* V9 ldswa */
+ gen_op_ldswa(insn, 1, 4, 1);
+ break;
+ case 0x1b: /* V9 ldxa */
+ gen_op_ldxa(insn, 1, 8, 0);
+ break;
+ case 0x2d: /* V9 prefetch, no effect */
+ goto skip_move;
+ case 0x30: /* V9 ldfa */
+ gen_op_ldfa(insn, 1, 8, 0); // XXX
+ break;
+ case 0x33: /* V9 lddfa */
+ gen_op_lddfa(insn, 1, 8, 0); // XXX
+
+ break;
+ case 0x3d: /* V9 prefetcha, no effect */
+ goto skip_move;
+ case 0x32: /* V9 ldqfa */
+ goto nfpu_insn;
+#endif
+ default:
+ goto illegal_insn;
+ }
+ gen_movl_T1_reg(rd);
+#ifdef TARGET_SPARC64
+ skip_move: ;
+#endif
+ } else if (xop >= 0x20 && xop < 0x24) {
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ switch (xop) {
+ case 0x20: /* load fpreg */
+ gen_op_ldst(ldf);
+ gen_op_store_FT0_fpr(rd);
+ break;
+ case 0x21: /* load fsr */
+ gen_op_ldst(ldf);
+ gen_op_ldfsr();
+ break;
+ case 0x22: /* load quad fpreg */
+ goto nfpu_insn;
+ case 0x23: /* load double fpreg */
+ gen_op_ldst(lddf);
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
+ xop == 0xe || xop == 0x1e) {
+ gen_movl_reg_T1(rd);
+ switch (xop) {
+ case 0x4:
+ gen_op_ldst(st);
+ break;
+ case 0x5:
+ gen_op_ldst(stb);
+ break;
+ case 0x6:
+ gen_op_ldst(sth);
+ break;
+ case 0x7:
+ flush_T2(dc);
+ gen_movl_reg_T2(rd + 1);
+ gen_op_ldst(std);
+ break;
+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+ case 0x14:
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_sta(insn, 0, 4, 0);
+ break;
+ case 0x15:
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_stba(insn, 0, 1, 0);
+ break;
+ case 0x16:
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ gen_op_stha(insn, 0, 2, 0);
+ break;
+ case 0x17:
+#ifndef TARGET_SPARC64
+ if (!supervisor(dc))
+ goto priv_insn;
+#endif
+ flush_T2(dc);
+ gen_movl_reg_T2(rd + 1);
+ gen_op_stda(insn, 0, 8, 0);
+ break;
+#endif
+#ifdef TARGET_SPARC64
+ case 0x0e: /* V9 stx */
+ gen_op_ldst(stx);
+ break;
+ case 0x1e: /* V9 stxa */
+ gen_op_stxa(insn, 0, 8, 0); // XXX
+ break;
+#endif
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop > 0x23 && xop < 0x28) {
+ if (gen_trap_ifnofpu(dc))
+ goto jmp_insn;
+ switch (xop) {
+ case 0x24:
+ gen_op_load_fpr_FT0(rd);
+ gen_op_ldst(stf);
+ break;
+ case 0x25: /* stfsr, V9 stxfsr */
+ gen_op_stfsr();
+ gen_op_ldst(stf);
+ break;
+ case 0x26: /* stdfq */
+ goto nfpu_insn;
+ case 0x27:
+ gen_op_load_fpr_DT0(DFPREG(rd));
+ gen_op_ldst(stdf);
+ break;
+ default:
+ goto illegal_insn;
+ }
+ } else if (xop > 0x33 && xop < 0x3f) {
+#ifdef TARGET_SPARC64
+ switch (xop) {
+ case 0x34: /* V9 stfa */
+ gen_op_stfa(insn, 0, 0, 0); // XXX
+ break;
+ case 0x37: /* V9 stdfa */
+ gen_op_stdfa(insn, 0, 0, 0); // XXX
+ break;
+ case 0x3c: /* V9 casa */
+ gen_op_casa(insn, 0, 4, 0); // XXX
+ break;
+ case 0x3e: /* V9 casxa */
+ gen_op_casxa(insn, 0, 8, 0); // XXX
+ break;
+ case 0x36: /* V9 stqfa */
+ goto nfpu_insn;
+ default:
+ goto illegal_insn;
+ }
+#else
+ goto illegal_insn;
+#endif
+ }
+ else
+ goto illegal_insn;
+ }
+ break;
+ }
+ /* default case for non jump instructions */
+ if (dc->npc == DYNAMIC_PC) {
+ dc->pc = DYNAMIC_PC;
+ gen_op_next_insn();
+ } else if (dc->npc == JUMP_PC) {
+ /* we can do a static jump */
+ gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
+ dc->is_br = 1;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = dc->npc + 4;
+ }
+ jmp_insn:
+ return;
+ illegal_insn:
+ save_state(dc);
+ gen_op_exception(TT_ILL_INSN);
+ dc->is_br = 1;
+ return;
+#if !defined(CONFIG_USER_ONLY)
+ priv_insn:
+ save_state(dc);
+ gen_op_exception(TT_PRIV_INSN);
+ dc->is_br = 1;
+ return;
+#endif
+ nfpu_insn:
+ save_state(dc);
+ gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
+ dc->is_br = 1;
+}
+
+static inline int gen_intermediate_code_internal(TranslationBlock * tb,
+ int spc, CPUSPARCState *env)
+{
+ target_ulong pc_start, last_pc;
+ uint16_t *gen_opc_end;
+ DisasContext dc1, *dc = &dc1;
+ int j, lj = -1;
+
+ memset(dc, 0, sizeof(DisasContext));
+ dc->tb = tb;
+ pc_start = tb->pc;
+ dc->pc = pc_start;
+ last_pc = dc->pc;
+ dc->npc = (target_ulong) tb->cs_base;
+#if defined(CONFIG_USER_ONLY)
+ dc->mem_idx = 0;
+ dc->fpu_enabled = 1;
+#else
+ dc->mem_idx = ((env->psrs) != 0);
+#ifdef TARGET_SPARC64
+ dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
+#else
+ dc->fpu_enabled = ((env->psref) != 0);
+#endif
+#endif
+ gen_opc_ptr = gen_opc_buf;
+ gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
+ gen_opparam_ptr = gen_opparam_buf;
+ nb_gen_labels = 0;
+
+ do {
+ if (env->nb_breakpoints > 0) {
+ for(j = 0; j < env->nb_breakpoints; j++) {
+ if (env->breakpoints[j] == dc->pc) {
+ if (dc->pc != pc_start)
+ save_state(dc);
+ gen_op_debug();
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ dc->is_br = 1;
+ goto exit_gen_loop;
+ }
+ }
+ }
+ if (spc) {
+ if (loglevel > 0)
+ fprintf(logfile, "Search PC...\n");
+ j = gen_opc_ptr - gen_opc_buf;
+ if (lj < j) {
+ lj++;
+ while (lj < j)
+ gen_opc_instr_start[lj++] = 0;
+ gen_opc_pc[lj] = dc->pc;
+ gen_opc_npc[lj] = dc->npc;
+ gen_opc_instr_start[lj] = 1;
+ }
+ }
+ last_pc = dc->pc;
+ disas_sparc_insn(dc);
+
+ if (dc->is_br)
+ break;
+ /* if the next PC is different, we abort now */
+ if (dc->pc != (last_pc + 4))
+ break;
+ /* if we reach a page boundary, we stop generation so that the
+ PC of a TT_TFAULT exception is always in the right page */
+ if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
+ break;
+ /* if single step mode, we generate only one instruction and
+ generate an exception */
+ if (env->singlestep_enabled) {
+ gen_jmp_im(dc->pc);
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ break;
+ }
+ } while ((gen_opc_ptr < gen_opc_end) &&
+ (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
+
+ exit_gen_loop:
+ if (!dc->is_br) {
+ if (dc->pc != DYNAMIC_PC &&
+ (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
+ /* static PC and NPC: we can use direct chaining */
+ gen_branch(dc, (long)tb, dc->pc, dc->npc);
+ } else {
+ if (dc->pc != DYNAMIC_PC)
+ gen_jmp_im(dc->pc);
+ save_npc(dc);
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ }
+ }
+ *gen_opc_ptr = INDEX_op_end;
+ if (spc) {
+ j = gen_opc_ptr - gen_opc_buf;
+ lj++;
+ while (lj <= j)
+ gen_opc_instr_start[lj++] = 0;
+ tb->size = 0;
+#if 0
+ if (loglevel > 0) {
+ page_dump(logfile);
+ }
+#endif
+ gen_opc_jump_pc[0] = dc->jump_pc[0];
+ gen_opc_jump_pc[1] = dc->jump_pc[1];
+ } else {
+ tb->size = last_pc + 4 - pc_start;
+ }
+#ifdef DEBUG_DISAS
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
+ fprintf(logfile, "--------------\n");
+ fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
+ target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
+ fprintf(logfile, "\n");
+ if (loglevel & CPU_LOG_TB_OP) {
+ fprintf(logfile, "OP:\n");
+ dump_ops(gen_opc_buf, gen_opparam_buf);
+ fprintf(logfile, "\n");
+ }
+ }
+#endif
+ return 0;
+}
+
+int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
+{
+ return gen_intermediate_code_internal(tb, 0, env);
+}
+
+int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
+{
+ return gen_intermediate_code_internal(tb, 1, env);
+}
+
+extern int ram_size;
+
+void cpu_reset(CPUSPARCState *env)
+{
+ memset(env, 0, sizeof(*env));
+ tlb_flush(env, 1);
+ env->cwp = 0;
+ env->wim = 1;
+ env->regwptr = env->regbase + (env->cwp * 16);
+#if defined(CONFIG_USER_ONLY)
+ env->user_mode_only = 1;
+#ifdef TARGET_SPARC64
+ env->cleanwin = NWINDOWS - 1;
+ env->cansave = NWINDOWS - 1;
+#endif
+#else
+ env->psrs = 1;
+ env->psrps = 1;
+ env->gregs[1] = ram_size;
+#ifdef TARGET_SPARC64
+ env->pstate = PS_PRIV;
+ env->version = GET_VER(env);
+ env->pc = 0x1fff0000000ULL;
+#else
+ env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
+ env->pc = 0xffd00000;
+#endif
+ env->npc = env->pc + 4;
+#endif
+}
+
+CPUSPARCState *cpu_sparc_init(void)
+{
+ CPUSPARCState *env;
+
+ env = qemu_mallocz(sizeof(CPUSPARCState));
+ if (!env)
+ return NULL;
+ cpu_exec_init(env);
+ cpu_reset(env);
+ return (env);
+}
+
+#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
+
+void cpu_dump_state(CPUState *env, FILE *f,
+ int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
+ int flags)
+{
+ int i, x;
+
+ cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
+ cpu_fprintf(f, "General Registers:\n");
+ for (i = 0; i < 4; i++)
+ cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
+ cpu_fprintf(f, "\n");
+ for (; i < 8; i++)
+ cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
+ cpu_fprintf(f, "\nCurrent Register Window:\n");
+ for (x = 0; x < 3; x++) {
+ for (i = 0; i < 4; i++)
+ cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
+ (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
+ env->regwptr[i + x * 8]);
+ cpu_fprintf(f, "\n");
+ for (; i < 8; i++)
+ cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
+ (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
+ env->regwptr[i + x * 8]);
+ cpu_fprintf(f, "\n");
+ }
+ cpu_fprintf(f, "\nFloating Point Registers:\n");
+ for (i = 0; i < 32; i++) {
+ if ((i & 3) == 0)
+ cpu_fprintf(f, "%%f%02d:", i);
+ cpu_fprintf(f, " %016lf", env->fpr[i]);
+ if ((i & 3) == 3)
+ cpu_fprintf(f, "\n");
+ }
+#ifdef TARGET_SPARC64
+ cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d\n",
+ env->pstate, GET_CCR(env), env->asi, env->tl);
+ cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
+ env->cansave, env->canrestore, env->otherwin, env->wstate,
+ env->cleanwin, NWINDOWS - 1 - env->cwp);
+#else
+ cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
+ GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
+ GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
+ env->psrs?'S':'-', env->psrps?'P':'-',
+ env->psret?'E':'-', env->wim);
+#endif
+ cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
+}
+
+#if defined(CONFIG_USER_ONLY)
+target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+{
+ return addr;
+}
+
+#else
+extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+ int *access_index, target_ulong address, int rw,
+ int is_user);
+
+target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+{
+ target_phys_addr_t phys_addr;
+ int prot, access_index;
+
+ if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
+ if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
+ return -1;
+ return phys_addr;
+}
+#endif
+
+void helper_flush(target_ulong addr)
+{
+ addr &= ~7;
+ tb_invalidate_page_range(addr, addr + 8);
+}
generated by cgit v1.1 at 2025-01-25 17:15:07 +0000