diff options
100 files changed, 28306 insertions, 2828 deletions
diff --git a/Makefile.android b/Makefile.android index 22d7438..f5c008b 100644 --- a/Makefile.android +++ b/Makefile.android @@ -45,20 +45,23 @@ endif MY_LDLIBS := -# this is needed to build the emulator on 64-bit Linux systems -ifeq ($(HOST_OS)-$(HOST_ARCH),linux-x86) - MY_CFLAGS += -Wa,--32 -endif - ifeq ($(HOST_OS),freebsd) - MY_CFLAGS += -Wa,--32 -I /usr/local/include + MY_CFLAGS += -I /usr/local/include endif ifeq ($(HOST_OS),windows) - MY_CFLAGS += -D_WIN32 - # we need Win32 features that are available since Windows 2000 Professional/Server (NT 5.0) + # we need Win32 features that are available since Windows 2000 Professional/Server (NT 5.0) MY_CFLAGS += -DWINVER=0x501 - MY_LDLIBS += -lvfw32 + MY_CFLAGS += -D_WIN32 + ifneq ($(BUILD_HOST_64bit),) + # Microsoft 64-bit compiler define both _WIN32 and _WIN64 + MY_CFLAGS += -D_WIN64 + # amd64-mingw32msvc- toolchain still name it vfw32. May change it once amd64-mingw32msvc- + # is stabilized + MY_LDLIBS += -lvfw32 + else + MY_LDLIBS += -lvfw32 + endif endif ifeq ($(HOST_ARCH),ppc) @@ -91,17 +94,17 @@ endif # adequate values for HOST_CC # ifneq ($(BUILD_STANDALONE_EMULATOR),true) - # On Linux, use our custom 32-bit host toolchain, which contains the - # relevant headers and 32-bit libraries for audio (The host 64-bit Lucid - # doesn't provide these anymore, only their 64-bit versions). + # On Linux, use our custom 32-bit host toolchain (unless BUILD_HOST_64bit=1) + # which contains the relevant headers and 32-bit libraries for audio (The host 64-bit + # Lucid doesn't provide these anymore, only their 64-bit versions). ifeq ($(HOST_OS),linux) - HOST_SDK_TOOLCHAIN_PREFIX := prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/bin/i686-linux + HOST_SDK_TOOLCHAIN_PREFIX := prebuilts/tools/gcc-sdk # Don't do anything if the toolchain is not there - ifneq (,$(strip $(wildcard $(HOST_SDK_TOOLCHAIN_PREFIX)-gcc))) - MY_CC := $(HOST_SDK_TOOLCHAIN_PREFIX)-gcc - MY_CXX := $(HOST_SDK_TOOLCHAIN_PREFIX)-g++ - MY_AR := $(HOST_SDK_TOOLCHAIN_PREFIX)-ar - endif # $(HOST_SDK_TOOLCHAIN_PREFIX)-gcc exists + ifneq (,$(strip $(wildcard $(HOST_SDK_TOOLCHAIN_PREFIX)/gcc))) + MY_CC := $(HOST_SDK_TOOLCHAIN_PREFIX)/gcc + MY_CXX := $(HOST_SDK_TOOLCHAIN_PREFIX)/g++ + MY_AR := $(HOST_SDK_TOOLCHAIN_PREFIX)/ar + endif # $(HOST_SDK_TOOLCHAIN_PREFIX)/gcc exists endif # HOST_OS == linux ifneq ($(USE_CCACHE),) @@ -109,16 +112,29 @@ ifneq ($(BUILD_STANDALONE_EMULATOR),true) ccache := $(strip $(wildcard $(ccache))) ifneq ($(ccache),$(firstword $(MY_CC))) MY_CC := $(ccache) $(MY_CC) + MY_CXX := $(ccache) $(MY_CXX) endif ccache := endif + + QEMU_OPENGLES_INCLUDE := sdk/emulator/opengl/host/include + QEMU_OPENGLES_LIBS := $(HOST_OUT) endif ifneq ($(combo_target)$(TARGET_SIMULATOR),HOST_true) - ifneq ($(HOST_ARCH),x86_64) - MY_CFLAGS += -m32 - MY_LDLIBS += -m32 + ifneq ($(BUILD_HOST_64bit),) + MY_CFLAGS += -m64 + MY_LDLIBS += -m64 + else + ifneq ($(HOST_ARCH),x86_64) + MY_CFLAGS += -m32 + MY_LDLIBS += -m32 + endif + endif + + ifneq ($(BUILD_HOST_static),) + MY_LDLIBS += -static endif endif @@ -184,6 +200,8 @@ ifeq ($(HOST_OS),linux) endif ifeq ($(HOST_OS),windows) + # amd64-mingw32msvc- toolchain still name it ws2_32. May change it once amd64-mingw32msvc- + # is stabilized QEMU_SYSTEM_LDLIBS += -lwinmm -lws2_32 -liphlpapi else QEMU_SYSTEM_LDLIBS += -lpthread @@ -235,7 +253,6 @@ LOCAL_STATIC_LIBRARIES := \ emulator-libui \ emulator-common \ - LOCAL_CFLAGS += -DCONFIG_STANDALONE_UI=1 LOCAL_CFLAGS += $(EMULATOR_COMMON_CFLAGS) $(EMULATOR_LIBUI_CFLAGS) diff --git a/Makefile.common b/Makefile.common index 8b98df8..4382bd2 100644 --- a/Makefile.common +++ b/Makefile.common @@ -54,7 +54,8 @@ gen-hw-config-defs = \ ### THESE ARE POTENTIALLY USED BY ALL COMPONENTS ### -$(call start-emulator-library, emulator-common) +common_LOCAL_CFLAGS = +common_LOCAL_SRC_FILES = EMULATOR_COMMON_CFLAGS := @@ -90,12 +91,12 @@ ZLIB_DIR := distrib/zlib-1.2.3 include $(LOCAL_PATH)/$(ZLIB_DIR)/sources.make EMULATOR_COMMON_CFLAGS += -I$(LOCAL_PATH)/$(ZLIB_DIR) -LOCAL_SRC_FILES += $(ZLIB_SOURCES) +common_LOCAL_SRC_FILES += $(ZLIB_SOURCES) ########################################################### # Android utility functions # -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ sockets.c \ iolooper-select.c \ android/async-console.c \ @@ -127,12 +128,31 @@ LOCAL_SRC_FILES += \ android/utils/tempfile.c \ android/utils/vector.c \ -$(call gen-hw-config-defs) +common_LOCAL_CFLAGS += $(EMULATOR_COMMON_CFLAGS) -LOCAL_CFLAGS += $(EMULATOR_COMMON_CFLAGS) +## one for 32-bit +$(call start-emulator-library, emulator-common) +LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) +LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) +$(call gen-hw-config-defs) $(call end-emulator-library) +## another for 64-bit +# NOTE: only linux in non-standalone mode is supported, because +# 1) For Windows: amd64-mingw32msvc-gcc doesn't work, see http://b/issue?id=5949152. +# 2) For MacOSX: 64-bit libSDL*.a 1.2.x depends on NSQuickDrawView doesn't exist +# 3) Standalone has --try-64 +ifeq ($(HOST_OS),linux) + ifneq ($(BUILD_STANDALONE_EMULATOR),true) + $(call start-emulator-library, emulator64-common) + LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) -m64 + LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) + $(call gen-hw-config-defs) + $(call end-emulator-library) + endif # BUILD_STANDALONE_EMULATOR == nil +endif # HOST_OS == linux + ############################################################################## ############################################################################## ### @@ -141,11 +161,14 @@ $(call end-emulator-library) ### THESE ARE USED BY 'emulator-ui' AND THE STANDALONE PROGRAMS ### -$(call start-emulator-library, emulator-libui) +common_LOCAL_CFLAGS = +common_LOCAL_SRC_FILES = -EMULATOR_LIBUI_CFLAGS := +ifneq ($(QEMU_OPENGLES_INCLUDE),) + EMULATOR_LIBUI_CFLAGS := -I$(QEMU_OPENGLES_INCLUDE) +endif -LOCAL_CFLAGS += $(EMULATOR_COMMON_CFLAGS) +common_LOCAL_CFLAGS += $(EMULATOR_COMMON_CFLAGS) ########################################################### # Libpng configuration @@ -157,7 +180,7 @@ EMULATOR_LIBUI_CFLAGS += \ $(LIBPNG_CFLAGS) \ -I$(LOCAL_PATH)/$(LIBPNG_DIR) -LOCAL_SRC_FILES += $(LIBPNG_SOURCES) loadpng.c +common_LOCAL_SRC_FILES += $(LIBPNG_SOURCES) loadpng.c ############################################################################## # SDL-related definitions @@ -199,7 +222,7 @@ endif ifneq ($(BUILD_SDL_FROM_SOURCES),true) - SDL_CONFIG ?= prebuilt/$(QEMU_HOST_TAG)/sdl/bin/sdl-config + SDL_CONFIG ?= prebuilts/tools/$(QEMU_HOST_TAG)/sdl/bin/sdl-config SDL_CFLAGS := $(shell $(SDL_CONFIG) --cflags) # We need to filter out the _GNU_SOURCE variable because it breaks recent @@ -211,12 +234,13 @@ ifneq ($(BUILD_SDL_FROM_SOURCES),true) # Circular dependencies between libSDL and libSDLmain # We repeat the libraries in the final link to work around it SDL_STATIC_LIBRARIES := libSDL libSDLmain libSDL libSDLmain + SDL_STATIC_LIBRARIES_64 := lib64SDL lib64SDLmain lib64SDL lib64SDLmain else # BUILD_SDL_FROM_SOURCES SDL_DIR := distrib/sdl-1.2.12 include $(LOCAL_PATH)/$(SDL_DIR)/sources.make - LOCAL_SRC_FILES += $(SDL_SOURCES) + common_LOCAL_SRC_FILES += $(SDL_SOURCES) EMULATOR_LIBUI_CFLAGS += \ -I$(LOCAL_PATH)/$(SDL_DIR)/include @@ -247,25 +271,42 @@ SKIN_SOURCES := rect.c \ composer.c \ surface.c \ -LOCAL_SRC_FILES += $(SKIN_SOURCES:%=android/skin/%) +common_LOCAL_SRC_FILES += $(SKIN_SOURCES:%=android/skin/%) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ android/user-config.c \ android/resource.c \ android/qemulator.c \ android/keycode.c \ -$(call gen-hw-config-defs) - # enable MMX code for our skin scaler ifeq ($(HOST_ARCH),x86) -LOCAL_CFLAGS += -DUSE_MMX=1 -mmmx +common_LOCAL_CFLAGS += -DUSE_MMX=1 -mmmx endif -LOCAL_CFLAGS += $(EMULATOR_LIBUI_CFLAGS) +common_LOCAL_CFLAGS += $(EMULATOR_LIBUI_CFLAGS) + +## one for 32-bit +$(call start-emulator-library, emulator-libui) +LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) +LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) +$(call gen-hw-config-defs) $(call end-emulator-library) + +## another for 64-bit, see note in emulator64-common +ifeq ($(HOST_OS),linux) + ifneq ($(BUILD_STANDALONE_EMULATOR),true) + $(call start-emulator-library, emulator64-libui) + LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) -m64 + LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) + $(call gen-hw-config-defs) + $(call end-emulator-library) + endif # BUILD_STANDALONE_EMULATOR == nil +endif # HOST_OS == linux + + ############################################################################## ############################################################################## ### @@ -274,11 +315,13 @@ $(call end-emulator-library) ### THESE ARE USED BY EVERYTHING EXCEPT 'emulator-ui' ### -$(call start-emulator-library, emulator-libqemu) +common_LOCAL_CFLAGS = +common_LOCAL_SRC_FILES = + EMULATOR_LIBQEMU_CFLAGS := -LOCAL_CFLAGS += $(EMULATOR_COMMON_CFLAGS) +common_LOCAL_CFLAGS += $(EMULATOR_COMMON_CFLAGS) ########################################################### # Jpeg configuration @@ -290,13 +333,13 @@ EMULATOR_LIBQEMU_CFLAGS += \ $(LIBJPEG_CFLAGS) \ -I$(LOCAL_PATH)/$(LIBJPEG_DIR) -LOCAL_SRC_FILES += $(LIBJPEG_SOURCES) +common_LOCAL_SRC_FILES += $(LIBJPEG_SOURCES) AUDIO_SOURCES := noaudio.c wavaudio.c wavcapture.c mixeng.c AUDIO_CFLAGS := -I$(LOCAL_PATH)/audio -DHAS_AUDIO AUDIO_LDLIBS := -LOCAL_CFLAGS += -Wall -Wno-missing-field-initializers +common_LOCAL_CFLAGS += -Wall -Wno-missing-field-initializers ifeq ($(HOST_OS),darwin) CONFIG_COREAUDIO ?= yes @@ -351,17 +394,17 @@ endif AUDIO_SOURCES := $(call sort,$(AUDIO_SOURCES:%=audio/%)) -LOCAL_CFLAGS += -Wno-sign-compare \ +common_LOCAL_CFLAGS += -Wno-sign-compare \ -fno-strict-aliasing -W -Wall -Wno-unused-parameter \ # this is very important, otherwise the generated binaries may # not link properly on our build servers ifeq ($(HOST_OS),linux) -LOCAL_CFLAGS += -fno-stack-protector +common_LOCAL_CFLAGS += -fno-stack-protector endif -LOCAL_SRC_FILES += $(AUDIO_SOURCES) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += $(AUDIO_SOURCES) +common_LOCAL_SRC_FILES += \ android/audio-test.c # other flags @@ -374,14 +417,14 @@ endif EMULATOR_LIBQEMU_CFLAGS += $(AUDIO_CFLAGS) EMULATOR_LIBQEMU_LDLIBS += $(AUDIO_LDLIBS) -LOCAL_CFLAGS += -Wno-missing-field-initializers +common_LOCAL_CFLAGS += -Wno-missing-field-initializers # migration sources # ifeq ($(HOST_OS),windows) - LOCAL_SRC_FILES += migration-dummy-android.c + common_LOCAL_SRC_FILES += migration-dummy-android.c else - LOCAL_SRC_FILES += migration.c \ + common_LOCAL_SRC_FILES += migration.c \ migration-exec.c \ migration-tcp-android.c endif @@ -435,16 +478,19 @@ CORE_MISC_SOURCES = \ android/hw-pipe-net.c \ android/qemu-setup.c \ android/snapshot.c \ - android/android-device.c \ + android/async-socket-connector.c \ + android/async-socket.c \ + android/sdk-controller-socket.c \ android/sensors-port.c \ android/utils/timezone.c \ android/camera/camera-format-converters.c \ android/camera/camera-service.c \ android/adb-server.c \ android/adb-qemud.c \ - android/snaphost-android.c - -$(call gen-hw-config-defs) + android/snaphost-android.c \ + android/multitouch-screen.c \ + android/multitouch-port.c \ + android/utils/jpeg-compress.c ifeq ($(HOST_ARCH),x86) CORE_MISC_SOURCES += i386-dis.c @@ -477,10 +523,10 @@ ifeq ($(HOST_OS),darwin) CORE_MISC_SOURCES += android/camera/camera-capture-mac.m endif -LOCAL_SRC_FILES += $(CORE_MISC_SOURCES) +common_LOCAL_SRC_FILES += $(CORE_MISC_SOURCES) # Required -LOCAL_CFLAGS += -D_XOPEN_SOURCE=600 -D_BSD_SOURCE=1 +common_LOCAL_CFLAGS += -D_XOPEN_SOURCE=600 -D_BSD_SOURCE=1 SLIRP_SOURCES := \ bootp.c \ @@ -502,7 +548,7 @@ SLIRP_SOURCES := \ tftp.c \ udp.c -LOCAL_SRC_FILES += $(SLIRP_SOURCES:%=slirp-android/%) +common_LOCAL_SRC_FILES += $(SLIRP_SOURCES:%=slirp-android/%) EMULATOR_LIBQEMU_CFLAGS += -I$(LOCAL_PATH)/slirp-android # socket proxy support @@ -513,7 +559,7 @@ PROXY_SOURCES := \ proxy_http_connector.c \ proxy_http_rewriter.c \ -LOCAL_SRC_FILES += $(PROXY_SOURCES:%=proxy/%) +common_LOCAL_SRC_FILES += $(PROXY_SOURCES:%=proxy/%) EMULATOR_LIBQEMU_CFLAGS += -I$(LOCAL_PATH)/proxy # include telephony stuff @@ -527,13 +573,13 @@ TELEPHONY_SOURCES := \ sms.c \ remote_call.c -LOCAL_SRC_FILES += $(TELEPHONY_SOURCES:%=telephony/%) +common_LOCAL_SRC_FILES += $(TELEPHONY_SOURCES:%=telephony/%) EMULATOR_LIBQEMU_CFLAGS += -I$(LOCAL_PATH)/telephony # sources inherited from upstream, but not fully # integrated into android emulator # -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ json-lexer.c \ json-parser.c \ json-streamer.c \ @@ -545,31 +591,57 @@ LOCAL_SRC_FILES += \ qlist.c \ qstring.c \ -# gdbstub-xml.c contains C-compilable arrays corresponding to the content -# of $(LOCAL_PATH)/gdb-xml/, and is generated with the 'feature_to_c.sh' script. -# -intermediates := $(call intermediates-dir-for,STATIC_LIBRARIES,$(LOCAL_MODULE),true) - ifeq ($(QEMU_TARGET_XML_SOURCES),) QEMU_TARGET_XML_SOURCES := arm-core arm-neon arm-vfp arm-vfp3 QEMU_TARGET_XML_SOURCES := $(QEMU_TARGET_XML_SOURCES:%=$(LOCAL_PATH)/gdb-xml/%.xml) endif -QEMU_GDBSTUB_XML_C := $(intermediates)/gdbstub-xml.c +common_LOCAL_CFLAGS += $(EMULATOR_LIBQEMU_CFLAGS) + + +## one for 32-bit +$(call start-emulator-library, emulator-libqemu) +# gdbstub-xml.c contains C-compilable arrays corresponding to the content +# of $(LOCAL_PATH)/gdb-xml/, and is generated with the 'feature_to_c.sh' script. +# +intermediates = $(call intermediates-dir-for,STATIC_LIBRARIES,$(LOCAL_MODULE),true) +QEMU_GDBSTUB_XML_C = $(intermediates)/gdbstub-xml.c $(QEMU_GDBSTUB_XML_C): PRIVATE_PATH := $(LOCAL_PATH) $(QEMU_GDBSTUB_XML_C): PRIVATE_SOURCES := $(TARGET_XML_SOURCES) $(QEMU_GDBSTUB_XML_C): PRIVATE_CUSTOM_TOOL = $(PRIVATE_PATH)/feature_to_c.sh $@ $(QEMU_TARGET_XML_SOURCES) $(QEMU_GDBSTUB_XML_C): $(QEMU_TARGET_XML_SOURCES) $(LOCAL_PATH)/feature_to_c.sh $(hide) rm -f $@ $(transform-generated-source) - LOCAL_GENERATED_SOURCES += $(QEMU_GDBSTUB_XML_C) +LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) -I$(intermediates) +LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) +$(call gen-hw-config-defs) +$(call end-emulator-library) -EMULATOR_LIBQEMU_CFLAGS += -I$(intermediates) -LOCAL_CFLAGS += $(EMULATOR_LIBQEMU_CFLAGS) +## another for 64-bit, see note in emulator64-common +ifeq ($(HOST_OS),linux) + ifneq ($(BUILD_STANDALONE_EMULATOR),true) + $(call start-emulator-library, emulator64-libqemu) + # gdbstub-xml.c contains C-compilable arrays corresponding to the content + # of $(LOCAL_PATH)/gdb-xml/, and is generated with the 'feature_to_c.sh' script. + # + intermediates = $(call intermediates-dir-for,STATIC_LIBRARIES,$(LOCAL_MODULE),true) + QEMU_GDBSTUB_XML_C = $(intermediates)/gdbstub-xml.c + $(QEMU_GDBSTUB_XML_C): PRIVATE_PATH := $(LOCAL_PATH) + $(QEMU_GDBSTUB_XML_C): PRIVATE_SOURCES := $(TARGET_XML_SOURCES) + $(QEMU_GDBSTUB_XML_C): PRIVATE_CUSTOM_TOOL = $(PRIVATE_PATH)/feature_to_c.sh $@ $(QEMU_TARGET_XML_SOURCES) + $(QEMU_GDBSTUB_XML_C): $(QEMU_TARGET_XML_SOURCES) $(LOCAL_PATH)/feature_to_c.sh + $(hide) rm -f $@ + $(transform-generated-source) + LOCAL_GENERATED_SOURCES += $(QEMU_GDBSTUB_XML_C) + LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) -I$(intermediates) -m64 + LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) + $(call gen-hw-config-defs) + $(call end-emulator-library) + endif # BUILD_STANDALONE_EMULATOR == nil +endif # HOST_OS == linux -$(call end-emulator-library) # Block sources, we must compile them with each executable because they # are only referenced by the rest of the code using constructor functions. @@ -611,9 +683,8 @@ BLOCK_CFLAGS += -DCONFIG_BDRV_WHITELIST="" ### THEM IN emulator-libqemu SINCE THE SOURCES ARE C++ ### -$(call start-emulator-library, emulator-libelff) - -LOCAL_CPP_EXTENSION := .cc +common_LOCAL_CFLAGS = +common_LOCAL_SRC_FILES = ELFF_CFLAGS := -I$(LOCAL_PATH)/elff ELFF_LDLIBS := -lstdc++ @@ -627,15 +698,33 @@ ELFF_SOURCES := \ elf_mapped_section.cc \ elff_api.cc \ -LOCAL_SRC_FILES += $(ELFF_SOURCES:%=elff/%) +common_LOCAL_SRC_FILES += $(ELFF_SOURCES:%=elff/%) -LOCAL_CFLAGS += \ +common_LOCAL_CFLAGS += \ -fno-exceptions \ $(ELFF_CFLAGS) \ + +## one for 32-bit +$(call start-emulator-library, emulator-libelff) +LOCAL_CPP_EXTENSION := .cc +LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) +LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) $(call end-emulator-library) +## another for 64-bit, see note in emulator64-common +ifeq ($(HOST_OS),linux) + ifneq ($(BUILD_STANDALONE_EMULATOR),true) + $(call start-emulator-library, emulator64-libelff) + LOCAL_CPP_EXTENSION := .cc + LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) -m64 + LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) + $(call end-emulator-library) + endif # BUILD_STANDALONE_EMULATOR == nil +endif # HOST_OS == linux + + ############################################################################## ############################################################################## ### diff --git a/Makefile.target b/Makefile.target index e1c4e28..e8a41f4 100644 --- a/Makefile.target +++ b/Makefile.target @@ -42,13 +42,15 @@ EMULATOR_TARGET_CFLAGS += \ -DTARGET_ARCH=\"$(EMULATOR_TARGET_ARCH)\" -$(call start-emulator-library, emulator-target-$(EMULATOR_TARGET_CPU)) +common_LOCAL_CFLAGS = +common_LOCAL_SRC_FILES = + # The following is to ensure that "config.h" will map to a target-specific # configuration file header. -LOCAL_CFLAGS += $(EMULATOR_TARGET_CFLAGS) +common_LOCAL_CFLAGS += $(EMULATOR_TARGET_CFLAGS) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ tcg/tcg.c \ ############################################################################## @@ -86,7 +88,6 @@ HW_SOURCES := \ usb.c \ watchdog.c -$(call gen-hw-config-defs) ifeq ($(EMULATOR_TARGET_ARCH),arm) HW_SOURCES += android_arm.c \ @@ -102,14 +103,14 @@ HW_SOURCES += android_arm.c \ HW_OBJ_SOURCES := hw/smc91c111.c HW_OBJ_CFLAGS := $(EMULATOR_TARGET_CFLAGS) -LOCAL_SRC_FILES += arm-dis.c +common_LOCAL_SRC_FILES += arm-dis.c # smc91c111.c requires <zlib.h> -LOCAL_CFLAGS += $(ZLIB_CFLAGS) +common_LOCAL_CFLAGS += $(ZLIB_CFLAGS) endif # required to ensure we properly initialize virtual audio hardware -LOCAL_CFLAGS += -DHAS_AUDIO +common_LOCAL_CFLAGS += -DHAS_AUDIO ifeq ($(EMULATOR_TARGET_ARCH),x86) HW_SOURCES += \ @@ -134,9 +135,9 @@ HW_OBJ_CFLAGS := $(EMULATOR_TARGET_CFLAGS) endif -LOCAL_SRC_FILES += $(HW_SOURCES:%=hw/%) +common_LOCAL_SRC_FILES += $(HW_SOURCES:%=hw/%) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ cpu-exec.c \ exec.c \ translate-all.c \ @@ -147,14 +148,14 @@ LOCAL_SRC_FILES += \ ############################################################################## # CPU-specific emulation. # -LOCAL_CFLAGS += -fno-PIC -fomit-frame-pointer -Wno-sign-compare +common_LOCAL_CFLAGS += -fno-PIC -fomit-frame-pointer -Wno-sign-compare ifeq ($(HOST_ARCH),ppc) - LOCAL_CFLAGS += -D__powerpc__ + common_LOCAL_CFLAGS += -D__powerpc__ endif ifeq ($(EMULATOR_TARGET_ARCH),arm) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ target-arm/op_helper.c \ target-arm/iwmmxt_helper.c \ target-arm/neon_helper.c \ @@ -166,36 +167,36 @@ LOCAL_SRC_FILES += \ hw/armv7m_nvic.c \ arm-semi.c \ -LOCAL_SRC_FILES += fpu/softfloat.c +common_LOCAL_SRC_FILES += fpu/softfloat.c endif ifeq ($(EMULATOR_TARGET_ARCH), x86) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ target-i386/op_helper.c \ target-i386/helper.c \ target-i386/translate.c \ target-i386/machine.c \ ifeq ($(HOST_OS),darwin) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ target-i386/hax-all.c \ target-i386/hax-darwin.c endif ifeq ($(HOST_OS),windows) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ target-i386/hax-all.c \ target-i386/hax-windows.c endif -LOCAL_SRC_FILES += fpu/softfloat-native.c +common_LOCAL_SRC_FILES += fpu/softfloat-native.c endif # compile KVM only if target is x86 on x86 Linux QEMU_KVM_TAG := $(QEMU_HOST_TAG)-$(EMULATOR_TARGET_ARCH) QEMU_DO_KVM := $(if $(filter linux-x86-x86 linux-x86_64-x86,$(QEMU_KVM_TAG)),true,false) ifeq ($(QEMU_DO_KVM),true) - LOCAL_SRC_FILES += \ + common_LOCAL_SRC_FILES += \ target-i386/kvm.c \ target-i386/kvm-gs-restore.c \ kvm-all.c \ @@ -210,7 +211,7 @@ endif # memory is within allocated block. This information also allows detecting # memory leaks and attempts to free/realloc invalid pointers. # -LOCAL_CFLAGS += \ +common_LOCAL_CFLAGS += \ -I$(LOCAL_PATH)/memcheck \ -I$(LOCAL_PATH)/elff @@ -221,23 +222,43 @@ MCHK_SOURCES := \ memcheck_mmrange_map.c \ memcheck_util.c \ -LOCAL_SRC_FILES += $(MCHK_SOURCES:%=memcheck/%) +common_LOCAL_SRC_FILES += $(MCHK_SOURCES:%=memcheck/%) -LOCAL_SRC_FILES += \ +common_LOCAL_SRC_FILES += \ cpus.c \ arch_init.c # What a mess, os-posix.c depends on the exact values of options # which are target specific. ifeq ($(HOST_OS),windows) - LOCAL_SRC_FILES += os-win32.c oslib-win32.c + common_LOCAL_SRC_FILES += os-win32.c oslib-win32.c else - LOCAL_SRC_FILES += os-posix.c oslib-posix.c + common_LOCAL_SRC_FILES += os-posix.c oslib-posix.c endif -$(call gen-hx-header,qemu-options.hx,qemu-options.def,os-posix.c os-win32.c) + +## one for 32-bit +$(call start-emulator-library, emulator-target-$(EMULATOR_TARGET_CPU)) +LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) +LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) +$(call gen-hw-config-defs) +$(call gen-hx-header,qemu-options.hx,qemu-options.def,os-posix.c os-win32.c) $(call end-emulator-library) +## another for 64-bit, see note in file Makefile.common emulator64-common +ifeq ($(HOST_OS),linux) + ifneq ($(BUILD_STANDALONE_EMULATOR),true) + $(call start-emulator-library, emulator64-target-$(EMULATOR_TARGET_CPU)) + LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) -m64 + LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) + $(call gen-hw-config-defs) + $(call gen-hx-header,qemu-options.hx,qemu-options.def,os-posix.c os-win32.c) + $(call end-emulator-library) + endif # BUILD_STANDALONE_EMULATOR == nil +endif # HOST_OS == linux + + + ############################################################################## ############################################################################## ### @@ -253,8 +274,11 @@ LOCAL_CFLAGS += \ $(EMULATOR_TARGET_CFLAGS) \ -DCONFIG_STANDALONE_CORE \ -LOCAL_CFLAGS += -Wno-missing-field-initializers +ifneq ($(QEMU_OPENGLES_INCLUDE),) + LOCAL_CFLAGS += -I$(QEMU_OPENGLES_INCLUDE) +endif +LOCAL_CFLAGS += -Wno-missing-field-initializers LOCAL_STATIC_LIBRARIES := \ emulator-libqemu \ @@ -302,7 +326,7 @@ endif # Generate a completely static executable if needed. # Note that this means no sound and graphics on Linux. # -ifeq ($(CONFIG_STATIC_EXECUTABLE),true) +ifneq ($(strip $(CONFIG_STATIC_EXECUTABLE)$(BUILD_HOST_static)),) LOCAL_SRC_FILES += dynlink-static.c LOCAL_LDLIBS += -static endif @@ -326,28 +350,31 @@ $(call end-emulator-program) ### ### -$(call start-emulator-program, emulator-$(EMULATOR_TARGET_ARCH)) +common_LOCAL_LDLIBS = +common_LOCAL_CFLAGS = +common_LOCAL_SRC_FILES = -LOCAL_STATIC_LIBRARIES := \ + +common_LOCAL_STATIC_LIBRARIES := \ emulator-libui \ emulator-libqemu \ emulator-target-$(EMULATOR_TARGET_CPU) \ emulator-libelff \ emulator-common \ -LOCAL_LDLIBS += \ +common_LOCAL_LDLIBS += \ $(EMULATOR_COMMON_LDLIBS) \ $(EMULATOR_LIBQEMU_LDLIBS) \ $(EMULATOR_LIBUI_LDLIBS) \ $(ELFF_LDLIBS) \ -LOCAL_CFLAGS += \ +common_LOCAL_CFLAGS += \ $(EMULATOR_TARGET_CFLAGS) \ $(EMULATOR_COMMON_CFLAGS) \ $(EMULATOR_LIBQEMU_CFLAGS) \ $(EMULATOR_LIBUI_CFLAGS) -LOCAL_SRC_FILES := \ +common_LOCAL_SRC_FILES := \ audio/audio.c \ disas.c \ dma-helpers.c \ @@ -371,28 +398,60 @@ LOCAL_SRC_FILES := \ android/protocol/ui-commands-qemu.c \ android/ -$(call gen-hx-header,qemu-monitor.hx,qemu-monitor.h,monitor.c) -$(call gen-hx-header,qemu-options.hx,qemu-options.def,vl-android.c qemu-options.h) -$(call gen-hw-config-defs) # The following files cannot be in static libraries because they contain # constructor functions that are otherwise stripped by the final linker -LOCAL_SRC_FILES += $(HW_OBJ_SOURCES) -LOCAL_CFLAGS += $(HW_OBJ_CFLAGS) +common_LOCAL_SRC_FILES += $(HW_OBJ_SOURCES) +common_LOCAL_CFLAGS += $(HW_OBJ_CFLAGS) -LOCAL_SRC_FILES += $(BLOCK_SOURCES) -LOCAL_CFLAGS += $(BLOCK_CFLAGS) +common_LOCAL_SRC_FILES += $(BLOCK_SOURCES) +common_LOCAL_CFLAGS += $(BLOCK_CFLAGS) -LOCAL_SRC_FILES += $(SDLMAIN_SOURCES) +common_LOCAL_SRC_FILES += $(SDLMAIN_SOURCES) # Generate a completely static executable if needed. # Note that this means no sound and graphics on Linux. # -ifeq ($(CONFIG_STATIC_EXECUTABLE),true) - LOCAL_SRC_FILES += dynlink-static.c - LOCAL_LDLIBS += -static +ifneq ($(strip $(CONFIG_STATIC_EXECUTABLE)$(BUILD_HOST_static)),) + common_LOCAL_SRC_FILES += dynlink-static.c + common_LOCAL_LDLIBS += -static endif -LOCAL_STATIC_LIBRARIES += $(SDL_STATIC_LIBRARIES) - +## one for 32-bit +$(call start-emulator-program, emulator-$(EMULATOR_TARGET_ARCH)) +LOCAL_STATIC_LIBRARIES += \ + emulator-libui \ + emulator-libqemu \ + emulator-target-$(EMULATOR_TARGET_CPU) \ + emulator-libelff \ + emulator-common \ + $(SDL_STATIC_LIBRARIES) +LOCAL_LDLIBS += $(common_LOCAL_LDLIBS) +LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) +LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) +$(call gen-hx-header,qemu-monitor.hx,qemu-monitor.h,monitor.c) +$(call gen-hx-header,qemu-options.hx,qemu-options.def,vl-android.c qemu-options.h) +$(call gen-hw-config-defs) $(call end-emulator-program) + + +## another for 64-bit, see note in file Makefile.common emulator64-common +ifeq ($(HOST_OS),linux) + ifneq ($(BUILD_STANDALONE_EMULATOR),true) + $(call start-emulator-program, emulator64-$(EMULATOR_TARGET_ARCH)) + LOCAL_STATIC_LIBRARIES += \ + emulator64-libui \ + emulator64-libqemu \ + emulator64-target-$(EMULATOR_TARGET_CPU) \ + emulator64-libelff \ + emulator64-common \ + $(SDL_STATIC_LIBRARIES_64) + LOCAL_LDLIBS += $(common_LOCAL_LDLIBS) -m64 + LOCAL_CFLAGS += $(common_LOCAL_CFLAGS) -m64 + LOCAL_SRC_FILES += $(common_LOCAL_SRC_FILES) + $(call gen-hx-header,qemu-monitor.hx,qemu-monitor.h,monitor.c) + $(call gen-hx-header,qemu-options.hx,qemu-options.def,vl-android.c qemu-options.h) + $(call gen-hw-config-defs) + $(call end-emulator-program) + endif # BUILD_STANDALONE_EMULATOR == nil +endif # HOST_OS == linux diff --git a/android-configure.sh b/android-configure.sh index 6d25d20..beb7427 100755 --- a/android-configure.sh +++ b/android-configure.sh @@ -116,12 +116,12 @@ EOF exit 1 fi -# On Linux, try to use our 32-bit prebuilt toolchain to generate binaries +# On Linux, try to use our prebuilt toolchain to generate binaries # that are compatible with Ubuntu 8.04 -if [ -z "$CC" -a -z "$OPTION_CC" -a "$HOST_OS" = linux -a "$OPTION_TRY_64" != "yes" ] ; then - HOST_CC=`dirname $0`/../../prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/bin/i686-linux-gcc +if [ -z "$CC" -a -z "$OPTION_CC" -a "$HOST_OS" = linux ] ; then + HOST_CC=`dirname $0`/../../prebuilts/tools/gcc-sdk/gcc if [ -f "$HOST_CC" ] ; then - echo "Using prebuilt 32-bit toolchain: $HOST_CC" + echo "Using prebuilt toolchain: $HOST_CC" CC="$HOST_CC" fi fi @@ -132,6 +132,10 @@ if [ -n "$OPTION_CC" ]; then CC="$OPTION_CC" fi +if [ -z "$CC" ]; then + CC=$HOST_CC +fi + # we only support generating 32-bit binaris on 64-bit systems. # And we may need to add a -Wa,--32 to CFLAGS to let the assembler # generate 32-bit binaries on Linux x86_64. @@ -180,7 +184,11 @@ fi # platform build tree and copy them into objs/lib/ automatically, unless # you use --gles-libs to point explicitely to a different directory. # -GLES_SHARED_LIBRARIES="libOpenglRender libGLES_CM_translator libGLES_V2_translator libEGL_translator" +if [ "$OPTION_TRY_64" != "yes" ] ; then + GLES_SHARED_LIBRARIES="libOpenglRender libGLES_CM_translator libGLES_V2_translator libEGL_translator" +else + GLES_SHARED_LIBRARIES="lib64OpenglRender lib64GLES_CM_translator lib64GLES_V2_translator lib64EGL_translator" +fi if [ "$IN_ANDROID_BUILD" = "yes" ] ; then locate_android_prebuilt @@ -196,10 +204,15 @@ if [ "$IN_ANDROID_BUILD" = "yes" ] ; then if [ ! -f $CCACHE ] ; then CCACHE="$ANDROID_PREBUILT/ccache$EXE" fi + if [ ! -f $CCACHE ] ; then + CCACHE="$ANDROID_PREBUILTS/ccache/ccache$EXE" + fi if [ -f $CCACHE ] ; then CC="$CCACHE $CC" + log "Prebuilt : CCACHE=$CCACHE" + else + log "Prebuilt : CCACHE can't be found" fi - log "Prebuilt : CCACHE=$CCACHE" fi # finally ensure that our new binary is copied to the 'out' @@ -227,7 +240,7 @@ if [ "$IN_ANDROID_BUILD" = "yes" ] ; then GLES_SUPPORT=yes if [ -z "$GLES_INCLUDE" ]; then log "GLES : Probing for headers" - GLES_INCLUDE=$ANDROID_TOP/development/tools/emulator/opengl/host/include + GLES_INCLUDE=$ANDROID_TOP/sdk/emulator/opengl/host/include if [ -d "$GLES_INCLUDE" ]; then log "GLES : Headers in $GLES_INCLUDE" else @@ -511,6 +524,7 @@ fi echo "HOST_PREBUILT_TAG := $TARGET_OS" >> $config_mk echo "HOST_EXEEXT := $TARGET_EXEEXT" >> $config_mk echo "PREBUILT := $ANDROID_PREBUILT" >> $config_mk +echo "PREBUILTS := $ANDROID_PREBUILTS" >> $config_mk PWD=`pwd` echo "SRC_PATH := $PWD" >> $config_mk diff --git a/android/adb-qemud.c b/android/adb-qemud.c index bc51807..9d82251 100644 --- a/android/adb-qemud.c +++ b/android/adb-qemud.c @@ -26,11 +26,15 @@ #define E(...) derror(__VA_ARGS__) #define W(...) dwarning(__VA_ARGS__) #define D(...) VERBOSE_PRINT(adbclient,__VA_ARGS__) +#define DD(...) VERBOSE_PRINT(adb,__VA_ARGS__) #define D_ACTIVE VERBOSE_CHECK(adbclient) +#define DD_ACTIVE VERBOSE_CHECK(adb) #define QB(b, s) quote_bytes((const char*)b, (s < 32) ? s : 32) -#define SERVICE_NAME "adb" - +#define SERVICE_NAME "adb" +#define DEBUG_SERVICE_NAME "adb-debug" +/* Maximum length of the message that can be received from the guest. */ +#define ADB_MAX_MSG_LEN 8 /* Enumerates ADB client state values. */ typedef enum AdbClientState { /* Waiting on a connection from ADB host. */ @@ -55,6 +59,17 @@ struct AdbClient { QemudClient* qemud_client; /* Connection state. */ AdbClientState state; + /* Buffer, collecting accept / stop messages from client. */ + char msg_buffer[ADB_MAX_MSG_LEN]; + /* Current position in message buffer. */ + int msg_cur; +}; + +/* ADB debugging client descriptor. */ +typedef struct AdbDbgClient AdbDbgClient; +struct AdbDbgClient { + /* QEMUD client pipe for this client. */ + QemudClient* qemud_client; }; /******************************************************************************** @@ -173,17 +188,36 @@ _adb_client_recv(void* opaque, uint8_t* msg, int msglen, QemudClient* client) D("ADB client %p(o=%p) received from guest %d bytes in %s", adb_client, adb_client->opaque, msglen, QB(msg, msglen)); + if (adb_client->state == ADBC_STATE_CONNECTED) { + /* Connection is fully established. Dispatch the message to the host. */ + adb_server_on_guest_message(adb_client->opaque, msg, msglen); + return; + } + + /* + * At this point we expect either "accept", or "start" messages. Depending + * on the state of the pipe (although small) these messages could be broken + * into pieces. So, simply checking msg for "accept", or "start" may not + * work. Lets collect them first in internal buffer, and then will see. + */ + + /* Make sure tha message doesn't overflow the buffer. */ + if ((msglen + adb_client->msg_cur) > sizeof(adb_client->msg_buffer)) { + D("Unexpected message in ADB client."); + adb_client->msg_cur = 0; + return; + } + /* Append to current message. */ + memcpy(adb_client->msg_buffer + adb_client->msg_cur, msg, msglen); + adb_client->msg_cur += msglen; + /* Properly dispatch the message, depending on the client state. */ switch (adb_client->state) { - case ADBC_STATE_CONNECTED: - /* Connection is fully established. Dispatch the message to the - * host. */ - adb_server_on_guest_message(adb_client->opaque, msg, msglen); - break; - case ADBC_STATE_WAIT_ON_HOST: /* At this state the only message that is allowed is 'accept' */ - if (msglen == 6 && !memcmp(msg, "accept", 6)) { + if (adb_client->msg_cur == 6 && + !memcmp(adb_client->msg_buffer, "accept", 6)) { + adb_client->msg_cur = 0; /* Register ADB guest connection with the ADB server. */ adb_client->opaque = adb_server_register_guest(adb_client, &_adb_client_routines); @@ -200,7 +234,9 @@ _adb_client_recv(void* opaque, uint8_t* msg, int msglen, QemudClient* client) case ADBC_STATE_HOST_CONNECTED: /* At this state the only message that is allowed is 'start' */ - if (msglen == 5 && !memcmp(msg, "start", 5)) { + if (adb_client->msg_cur && + !memcmp(adb_client->msg_buffer, "start", 5)) { + adb_client->msg_cur = 0; adb_client->state = ADBC_STATE_CONNECTED; adb_server_complete_connection(adb_client->opaque); } else { @@ -259,6 +295,82 @@ _adb_service_connect(void* opaque, } /******************************************************************************** + * Debugging ADB guest communication. + *******************************************************************************/ + +/* Allocates AdbDbgClient instance. */ +static AdbDbgClient* +_adb_dbg_client_new(void) +{ + AdbDbgClient* adb_dbg_client; + + ANEW0(adb_dbg_client); + + return adb_dbg_client; +} + +/* Frees AdbDbgClient instance, allocated with _adb_dbg_client_new */ +static void +_adb_dbg_client_free(AdbDbgClient* adb_dbg_client) +{ + if (adb_dbg_client != NULL) { + free(adb_dbg_client); + } +} + +/* A callback that is invoked when ADB debugging guest sends data to the service. + * Param: + * opaque - AdbDbgClient instance. + * msg, msglen - Message received from the ADB guest. + * client - adb-debug QEMUD client. + */ +static void +_adb_dbg_client_recv(void* opaque, uint8_t* msg, int msglen, QemudClient* client) +{ + if (DD_ACTIVE) { + fprintf(stderr, "ADB: %s", (const char*)msg); + } +} + +/* A callback that is invoked when ADB debugging guest disconnects from the + * service. */ +static void +_adb_dbg_client_close(void* opaque) +{ + AdbDbgClient* const adb_dbg_client = (AdbDbgClient*)opaque; + + DD("ADB debugging client %p is disconnected from the guest.", adb_dbg_client); + _adb_dbg_client_free(adb_dbg_client); +} + +/* A callback that is invoked when ADB daemon running inside the guest connects + * to the debugging service. + * Client parameters are ignored here. + */ +static QemudClient* +_adb_debug_service_connect(void* opaque, + QemudService* serv, + int channel, + const char* client_param) +{ + /* Create new QEMUD client for the connection with ADB debugger. */ + AdbDbgClient* const adb_dbg_client = _adb_dbg_client_new(); + + DD("Connecting ADB debugging guest: '%s'", + client_param ? client_param : "<null>"); + adb_dbg_client->qemud_client = + qemud_client_new(serv, channel, client_param, adb_dbg_client, + _adb_dbg_client_recv, _adb_dbg_client_close, NULL, NULL); + if (adb_dbg_client->qemud_client == NULL) { + DD("Unable to create QEMUD client for ADB debugging guest."); + _adb_dbg_client_free(adb_dbg_client); + return NULL; + } + + return adb_dbg_client->qemud_client; +} + +/******************************************************************************** * ADB service API. *******************************************************************************/ @@ -272,6 +384,7 @@ static int _inited = 0; } if (!_inited) { + /* Register main ADB service. */ QemudService* serv = qemud_service_register(SERVICE_NAME, 0, NULL, _adb_service_connect, NULL, NULL); @@ -281,5 +394,15 @@ static int _inited = 0; return; } D("%s: Registered '%s' qemud service", __FUNCTION__, SERVICE_NAME); + + /* Register debugging ADB service. */ + serv = qemud_service_register(DEBUG_SERVICE_NAME, 0, NULL, + _adb_debug_service_connect, NULL, NULL); + if (serv != NULL) { + DD("Registered '%s' qemud service", DEBUG_SERVICE_NAME); + } else { + dwarning("%s: Could not register '%s' service", + __FUNCTION__, DEBUG_SERVICE_NAME); + } } } diff --git a/android/android-device.c b/android/android-device.c deleted file mode 100644 index 37af0c6..0000000 --- a/android/android-device.c +++ /dev/null @@ -1,1496 +0,0 @@ -/* - * Copyright (C) 2011 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Encapsulates exchange protocol between the emulator, and an Android device - * that is connected to the host via USB. The communication is established over - * a TCP port forwarding, enabled by ADB. - */ - -#include "android/android-device.h" -#include "utils/panic.h" -#include "iolooper.h" - -#define E(...) derror(__VA_ARGS__) -#define W(...) dwarning(__VA_ARGS__) -#define D(...) VERBOSE_PRINT(adevice,__VA_ARGS__) -#define D_ACTIVE VERBOSE_CHECK(adevice) - -/******************************************************************************** - * Common android device socket - *******************************************************************************/ - -/* Milliseconds between retrying asynchronous connections to the device. */ -#define ADS_RETRY_CONNECTION_TIMEOUT 3000 - -/* Socket type. */ -typedef enum ADSType { - /* Query socket. */ - ADS_TYPE_QUERY = 0, - /* Events socket. */ - ADS_TYPE_EVENT = 1 -} ADSType; - -/* Status of the socket. */ -typedef enum ADSStatus { - /* Socket is disconnected. */ - ADS_DISCONNECTED, - /* Connection process has been started. */ - ADS_CONNECTING, - /* Connection has been established. */ - ADS_CONNECTED, - /* Socket has been registered with the server. */ - ADS_REGISTERED, -} ADSStatus; - -/* Identifies socket as a "query" socket with the server. */ -static const char* _ads_query_socket_id = "query"; -/* Identifies socket as an "event" socket with the server. */ -static const char* _ads_event_socket_id = "event"; - -/* Android device socket descriptor. */ -typedef struct AndroidDevSocket AndroidDevSocket; - -/* - * Callback routines. - */ - -/* Callback routine that is called when a socket is connected. - * Param: - * opaque - Opaque pointer associated with the socket. Typicaly it's the same - * pointer that is associated with AndroidDevice instance. - * ads - Connection socket. - * failure - If zero, indicates that socket has been successuly connected. If a - * connection error has occured, this parameter contains the error code (as - * in 'errno). - */ -typedef void (*ads_socket_connected_cb)(void* opaque, - struct AndroidDevSocket* ads, - int failure); - -/* Android device socket descriptor. */ -struct AndroidDevSocket { - /* Socket type. */ - ADSType type; - /* Socket status. */ - ADSStatus socket_status; - /* TCP address for the socket. */ - SockAddress address; - /* Android device descriptor that owns the socket. */ - AndroidDevice* ad; - /* Opaque pointer associated with the socket. Typicaly it's the same - * pointer that is associated with AndroidDevice instance.*/ - void* opaque; - /* Deadline for current I/O performed on the socket. */ - Duration deadline; - /* Socket's file descriptor. */ - int fd; -}; - -/* Query socket descriptor. */ -typedef struct AndroidQuerySocket { - /* Common device socket. */ - AndroidDevSocket dev_socket; -} AndroidQuerySocket; - -/* Describes data to send via an asynchronous socket. */ -typedef struct AsyncSendBuffer { - /* Next buffer to send. */ - struct AsyncSendBuffer* next; - /* Callback to invoke when data transfer is completed. */ - async_send_cb complete_cb; - /* An opaque pointer to pass to the transfer completion callback. */ - void* complete_opaque; - /* Data to send. */ - uint8_t* data; - /* Size of the entire data buffer. */ - int data_size; - /* Remaining bytes to send. */ - int data_remaining; - /* Boolean flag indicating whether to free data buffer upon completion. */ - int free_on_completion; -} AsyncSendBuffer; - -/* Event socket descriptor. */ -typedef struct AndroidEventSocket { - /* Common socket descriptor. */ - AndroidDevSocket dev_socket; - /* Asynchronous connector to the device. */ - AsyncConnector connector[1]; - /* I/O port for asynchronous I/O on this socket. */ - LoopIo io[1]; - /* Asynchronous string reader. */ - AsyncLineReader alr; - /* Callback to call at the end of the asynchronous connection to this socket. - * Can be NULL. */ - ads_socket_connected_cb on_connected; - /* Callback to call when an event is received on this socket. Can be NULL. */ - event_cb on_event; - /* Lists buffers that are pending to be sent. */ - AsyncSendBuffer* send_pending; -} AndroidEventSocket; - -/* Android device descriptor. */ -struct AndroidDevice { - /* Query socket for the device. */ - AndroidQuerySocket query_socket; - /* Event socket for the device. */ - AndroidEventSocket event_socket; - /* An opaque pointer associated with this descriptor. */ - void* opaque; - /* I/O looper for synchronous I/O on the sockets for this device. */ - IoLooper* io_looper; - /* Timer that is used to retry asynchronous connections. */ - LoopTimer timer[1]; - /* I/O looper for asynchronous I/O. */ - Looper* looper; - /* Callback to call when device is fully connected. */ - device_connected_cb on_connected; - /* I/O failure callback .*/ - io_failure_cb on_io_failure; -}; - -/* Creates descriptor for a buffer to send asynchronously. - * Param: - * data, size - Buffer to send. - * free_on_close - Boolean flag indicating whether to free data buffer upon - * completion. - * cb - Callback to invoke when data transfer is completed. - * opaque - An opaque pointer to pass to the transfer completion callback. - */ -static AsyncSendBuffer* -_async_send_buffer_create(void* data, - int size, - int free_on_close, - async_send_cb cb, - void* opaque) -{ - AsyncSendBuffer* desc = malloc(sizeof(AsyncSendBuffer)); - if (desc == NULL) { - APANIC("Unable to allocate %d bytes for AsyncSendBuffer", - sizeof(AsyncSendBuffer)); - } - desc->next = NULL; - desc->data = (uint8_t*)data; - desc->data_size = desc->data_remaining = size; - desc->free_on_completion = free_on_close; - desc->complete_cb = cb; - desc->complete_opaque = opaque; - - return desc; -} - -/* Completes data transfer for the given descriptor. - * Note that this routine will free the descriptor. - * Param: - * desc - Asynchronous data transfer descriptor. Will be freed upon the exit - * from this routine. - * res - Data transfer result. - */ -static void -_async_send_buffer_complete(AsyncSendBuffer* desc, ATResult res) -{ - /* Invoke completion callback (if present) */ - if (desc->complete_cb) { - desc->complete_cb(desc->complete_opaque, res, desc->data, desc->data_size, - desc->data_size - desc->data_remaining); - } - - /* Free data buffer (if required) */ - if (desc->free_on_completion) { - free(desc->data); - } - - /* Free the descriptor itself. */ - free(desc); -} - -/******************************************************************************** - * Common socket declarations - *******************************************************************************/ - -/* Initializes common device socket. - * Param: - * ads - Socket descriptor to initialize. - * opaque - An opaque pointer to associate with the socket. Typicaly it's the - * same pointer that is associated with AndroidDevice instance. - * ad - Android device descriptor that owns the socket. - * port - Socket's TCP port. - * type - Socket type (query, or event). - */ -static int _android_dev_socket_init(AndroidDevSocket* ads, - void* opaque, - AndroidDevice* ad, - int port, - ADSType type); - -/* Destroys socket descriptor. */ -static void _android_dev_socket_destroy(AndroidDevSocket* ads); - -/* Synchronously connects to the socket, and registers it with the server. - * Param: - * ads - Socket to connect. Must have 'deadline' field properly setup. - * Return: - * 0 on success, -1 on failure with errno containing the reason for failure. - */ -static int _android_dev_socket_connect(AndroidDevSocket* ads); - -/* Synchronously registers a connected socket with the server. - * Param: - * ads - Socket to register. Must be connected, and must have 'deadline' field - * properly setup. - * Return: - * 0 on success, -1 on failure with errno containing the reason for failure. - */ -static int _android_dev_socket_register(AndroidDevSocket* ads); - -/* Disconnects the socket (if it was connected) */ -static void _android_dev_socket_disconnect(AndroidDevSocket* ads); - -/* Synchronously sends data to the socket. - * Param: - * ads - Socket to send the data to. Must be connected, and must have 'deadline' - * field properly setup. - * buff, buffsize - Buffer to send. - * Return: - * Number of bytes sent on success, or -1 on failure with errno containing the - * reason for failure. - */ -static int _android_dev_socket_send(AndroidDevSocket* ads, - const char* buff, - int buffsize); - -/* Synchronously receives data from the socket. - * Param: - * ads - Socket to receive the data from. Must be connected, and must have - * 'deadline' field properly setup. - * buff, buffsize - Buffer where to receive data. - * Return: - * Number of bytes received on success, or -1 on failure with errno containing - * the reason for failure. - */ -static int _android_dev_socket_recv(AndroidDevSocket* ads, - char* buf, - int bufsize); - -/* Synchronously reads zero-terminated string from the socket. - * Param: - * ads - Socket to read the string from. Must be connected, and must have - * 'deadline' field properly setup. - * str, strsize - Buffer where to read the string. - * Return: - * Number of charactes read into the string buffer (including zero-terminator) - * on success, or -1 on failure with 'errno' containing the reason for failure. - * If this routine returns -1, and errno contains ENOMEM, this is an indicator - * that supplied string buffer was too small for the receiving string. - */ -static int _android_dev_socket_read_string(AndroidDevSocket* ads, - char* str, - int strsize); - -/* Synchronously reads zero-terminated query response from the socket. - * All queries respond with an 'ok', or 'ko' prefix, indicating a success, or - * failure. Prefix can be followed by more query response data, separated from - * the prefix with a ':' character. This routine helps separating prefix from the - * data, by placing only the query response data into provided buffer. 'ko' or - * 'ok' will be encoded in the return value. - * Param: - * ads - Socket to read the response from. Must be connected, and must have - * 'deadline' field properly setup. - * data, datasize - Buffer where to read the query response data. - * Return: - * Number of charactes read into the data buffer (including zero-terminator) on - * success, or -1 on failure with errno containing the reason for failure. - * If the query has been completed with 'ko', this routine will return -1, with - * errno set to 0. If this routine returned -1, and errno is set to EINVAL, this - * indicates that reply string didn't match expected query reply format. - */ -static int _android_dev_socket_read_response(AndroidDevSocket* ads, - char* str, - int strsize); - -/* Gets ID string for the channel. */ -AINLINED const char* -_ads_id_str(AndroidDevSocket* ads) -{ - return (ads->type == ADS_TYPE_QUERY) ? _ads_query_socket_id : - _ads_event_socket_id; -} - -/* Gets socket's TCP port. */ -AINLINED int -_ads_port(AndroidDevSocket* ads) -{ - return sock_address_get_port(&ads->address); -} - -/* Gets synchronous I/O looper for the socket. */ -AINLINED IoLooper* -_ads_io_looper(AndroidDevSocket* ads) -{ - return ads->ad->io_looper; -} - -/* Sets deadline on a socket operation, given relative timeout. - * Param: - * ads - Socket descriptor to set deadline for. - * to - Relative timeout (in millisec) for the operation. - * AD_INFINITE_WAIT passed in this parameter means "no deadline". - */ -AINLINED void -_ads_set_deadline(AndroidDevSocket* ads, int to) -{ - ads->deadline = (to == AD_INFINITE_WAIT) ? DURATION_INFINITE : - iolooper_now() + to; -} - -/******************************************************************************** - * Common socket implementation - *******************************************************************************/ - -static int -_android_dev_socket_init(AndroidDevSocket* ads, - void* opaque, - AndroidDevice* ad, - int port, - ADSType type) -{ - ads->type = type; - ads->socket_status = ADS_DISCONNECTED; - ads->opaque = opaque; - ads->ad = ad; - ads->fd = -1; - sock_address_init_inet(&ads->address, SOCK_ADDRESS_INET_LOOPBACK, port); - - return 0; -} - -static void -_android_dev_socket_destroy(AndroidDevSocket* ads) -{ - /* Make sure it's disconnected. */ - _android_dev_socket_disconnect(ads); - - /* Finalize socket address. */ - sock_address_done(&ads->address); - memset(&ads->address, 0, sizeof(ads->address)); -} - -static int -_android_dev_socket_connect(AndroidDevSocket* ads) -{ - int res; - - /* Create communication socket. */ - ads->fd = socket_create_inet(SOCKET_STREAM); - if (ads->fd < 0) { - D("Unable to create socket for channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - return -1; - } - socket_set_nonblock(ads->fd); - - /* Synchronously connect to it. */ - ads->socket_status = ADS_CONNECTING; - iolooper_add_write(_ads_io_looper(ads), ads->fd); - res = socket_connect(ads->fd, &ads->address); - while (res < 0 && errno == EINTR) { - res = socket_connect(ads->fd, &ads->address); - } - - if (res && (errno == EINPROGRESS || errno == EWOULDBLOCK || errno == EAGAIN)) { - /* Connection is delayed. Wait for it until timeout expires. */ - res = iolooper_wait_absolute(_ads_io_looper(ads), ads->deadline); - if (res > 0) { - /* Pick up on possible connection error. */ - errno = socket_get_error(ads->fd); - res = (errno == 0) ? 0 : -1; - } else { - res = -1; - } - } - iolooper_del_write(_ads_io_looper(ads), ads->fd); - - if (res == 0) { - D("Channel '%s'@%d is connected", _ads_id_str(ads), _ads_port(ads)); - /* Socket is connected. Now register it with the server. */ - ads->socket_status = ADS_CONNECTED; - res = _android_dev_socket_register(ads); - } else { - D("Unable to connect channel '%s' to port %d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - } - - if (res) { - _android_dev_socket_disconnect(ads); - } - - return res; -} - -static int -_android_dev_socket_register(AndroidDevSocket* ads) -{ - /* Make sure that socket is connected. */ - if (ads->socket_status < ADS_CONNECTED) { - D("Attempt to register a disconnected channel '%s'@%d", - _ads_id_str(ads), _ads_port(ads)); - errno = ECONNRESET; - return -1; - } - - /* Register this socket accordingly to its type. */ - const char* reg_str = _ads_id_str(ads); - int res = _android_dev_socket_send(ads, reg_str, strlen(reg_str) + 1); - if (res > 0) { - /* Receive reply. Note that according to the protocol, the server should - * reply to channel registration with 'ok', or 'ko' (just like with queries), - * so we can use query reply reader here. */ - char reply[256]; - res = _android_dev_socket_read_response(ads, reply, sizeof(reply)); - if (res >= 0) { - /* Socket is now registered. */ - ads->socket_status = ADS_REGISTERED; - D("Channel '%s'@%d is registered", _ads_id_str(ads), _ads_port(ads)); - res = 0; - } else { - if (errno == 0) { - /* 'ko' condition */ - D("Device failed registration of channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), reply); - errno = EINVAL; - } else { - D("I/O failure while registering channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - } - res = -1; - } - } else { - D("Unable to send registration query for channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - res = -1; - } - - return res; -} - -static void -_android_dev_socket_disconnect(AndroidDevSocket* ads) -{ - /* Preserve errno */ - const int save_error = errno; - if (ads->socket_status != ADS_DISCONNECTED) { - /* Reset I/O looper for this socket. */ - iolooper_modify(_ads_io_looper(ads), ads->fd, - IOLOOPER_READ | IOLOOPER_WRITE, 0); - - /* Mark as disconnected. */ - ads->socket_status = ADS_DISCONNECTED; - - /* Close socket. */ - if (ads->fd >= 0) { - socket_close(ads->fd); - ads->fd = -1; - } - } - errno = save_error; -} - -static int -_android_dev_socket_send(AndroidDevSocket* ads, const char* buff, int to_send) -{ - int sent = 0; - - /* Make sure that socket is connected. */ - if (ads->socket_status < ADS_CONNECTED) { - D("Attempt to send via disconnected channel '%s'@%d", - _ads_id_str(ads), _ads_port(ads)); - errno = ECONNRESET; - return -1; - } - - iolooper_add_write(_ads_io_looper(ads), ads->fd); - do { - int res = socket_send(ads->fd, buff + sent, to_send - sent); - if (res == 0) { - /* Disconnection. */ - errno = ECONNRESET; - sent = -1; - break; - } - - if (res < 0) { - if (errno == EINTR) { - /* loop on EINTR */ - continue; - } - - if (errno == EWOULDBLOCK || errno == EAGAIN) { - res = iolooper_wait_absolute(_ads_io_looper(ads), ads->deadline); - if (res > 0) { - /* Ready to write. */ - continue; - } - } - sent = -1; - break; - } - sent += res; - } while (sent < to_send); - iolooper_del_write(_ads_io_looper(ads), ads->fd); - - /* In case of an I/O failure we have to invoke failure callback. Note that we - * report I/O failures only on registered sockets. */ - if (sent < 0) { - D("I/O error while sending data via channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - - if (ads->ad->on_io_failure != NULL && ads->socket_status > ADS_CONNECTED) { - const char save_error = errno; - ads->ad->on_io_failure(ads->opaque, ads->ad, save_error); - errno = save_error; - } - } - - return sent; -} - -static int -_android_dev_socket_recv(AndroidDevSocket* ads, char* buf, int bufsize) -{ - int recvd = 0; - - /* Make sure that socket is connected. */ - if (ads->socket_status < ADS_CONNECTED) { - D("Attempt to receive from disconnected channel '%s'@%d", - _ads_id_str(ads), _ads_port(ads)); - errno = ECONNRESET; - return -1; - } - - iolooper_add_read(_ads_io_looper(ads), ads->fd); - do { - int res = socket_recv(ads->fd, buf + recvd, bufsize - recvd); - if (res == 0) { - /* Disconnection. */ - errno = ECONNRESET; - recvd = -1; - break; - } - - if (res < 0) { - if (errno == EINTR) { - /* loop on EINTR */ - continue; - } - - if (errno == EWOULDBLOCK || errno == EAGAIN) { - res = iolooper_wait_absolute(_ads_io_looper(ads), ads->deadline); - if (res > 0) { - /* Ready to read. */ - continue; - } - } - recvd = -1; - break; - } - recvd += res; - } while (recvd < bufsize); - iolooper_del_read(_ads_io_looper(ads), ads->fd); - - /* In case of an I/O failure we have to invoke failure callback. Note that we - * report I/O failures only on registered sockets. */ - if (recvd < 0) { - D("I/O error while receiving from channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - - if (ads->ad->on_io_failure != NULL && ads->socket_status > ADS_CONNECTED) { - const char save_error = errno; - ads->ad->on_io_failure(ads->opaque, ads->ad, save_error); - errno = save_error; - } - } - - return recvd; -} - -static int -_android_dev_socket_read_string(AndroidDevSocket* ads, char* str, int strsize) -{ - int n; - - /* Char by char read from the socket, until zero-terminator is read. */ - for (n = 0; n < strsize; n++) { - if (_android_dev_socket_recv(ads, str + n, 1) > 0) { - if (str[n] == '\0') { - /* Done. */ - return n + 1; /* Including zero-terminator. */ - } - } else { - /* I/O error. */ - return -1; - } - } - - /* Buffer was too small. Report that by setting errno to ENOMEM. */ - D("Buffer %d is too small to receive a string from channel '%s'@%d", - strsize, _ads_id_str(ads), _ads_port(ads)); - errno = ENOMEM; - return -1; -} - -static int -_android_dev_socket_read_response(AndroidDevSocket* ads, char* data, int datasize) -{ - int n, res; - int success = 0; - int failure = 0; - int bad_format = 0; - char ok[4]; - - *data = '\0'; - - /* Char by char read from the socket, until ok/ko is read. */ - for (n = 0; n < 2; n++) { - res = _android_dev_socket_recv(ads, ok + n, 1); - if (res > 0) { - if (ok[n] == '\0') { - /* EOS is unexpected here! */ - D("Bad query reply format on channel '%s'@%d: '%s' is too short.", - _ads_id_str(ads), _ads_port(ads), ok); - errno = EINVAL; - return -1; - } - } else { - /* I/O error. */ - return -1; - } - } - - /* Next character must be either ':', or '\0' */ - res = _android_dev_socket_recv(ads, ok + n, 1); - if (res <= 0) { - /* I/O error. */ - return -1; - } - - /* - * Verify format. - */ - - /* Check ok / ko */ - success = memcmp(ok, "ok", 2) == 0; - failure = memcmp(ok, "ko", 2) == 0; - - /* Check the prefix: 'ok'|'ko' & ':'|'\0' */ - if ((success || failure) && (ok[n] == '\0' || ok[n] == ':')) { - /* Format is good. */ - if (ok[n] == '\0') { - /* We're done: no extra data in response. */ - errno = 0; - return success ? 0 : -1; - } - /* Reset buffer offset, so we will start to read the remaining query - * data to the beginning of the supplied buffer. */ - n = 0; - } else { - /* Bad format. Lets move what we've read to the main buffer, and - * continue filling it in. */ - bad_format = 1; - n++; - memcpy(data, ok, n); - } - - /* Read the remainder of reply to the supplied data buffer. */ - res = _android_dev_socket_read_string(ads, data + n, datasize - n); - if (res < 0) { - return res; - } - - /* Lets see if format was bad */ - if (bad_format) { - D("Bad query reply format on channel '%s'@%d: %s.", - _ads_id_str(ads), _ads_port(ads), data); - errno = EINVAL; - return -1; - } else { - errno = 0; - return success ? n : -1; - } -} - -/******************************************************************************** - * Query socket declarations - *******************************************************************************/ - -/* Initializes query socket descriptor. - * Param: - * adsquery - Socket descriptor to initialize. - * opaque - An opaque pointer to associate with the socket. Typicaly it's the - * same pointer that is associated with AndroidDevice instance. - * ad - Android device descriptor that owns the socket. - * port - TCP socket port. - */ -static int _android_query_socket_init(AndroidQuerySocket* adsquery, - void* opaque, - AndroidDevice* ad, - int port); - -/* Destroys query socket descriptor. */ -static void _android_query_socket_destroy(AndroidQuerySocket* adsquery); - -/* Synchronously connects the query socket, and registers it with the server. - * Param: - * adsquery - Descriptor for the query socket to connect. Must have 'deadline' - * field properly setup. - * cb - Callback to invoke when socket connection is completed. Can be NULL. - * Return: - * Zero on success, or non-zero on failure. - */ -static int _android_query_socket_connect(AndroidQuerySocket* adsquery); - -/* Disconnects the query socket. */ -static void _android_query_socket_disconnect(AndroidQuerySocket* adsquery); - -/******************************************************************************** - * Query socket implementation - *******************************************************************************/ - -static int -_android_query_socket_init(AndroidQuerySocket* adsquery, - void* opaque, - AndroidDevice* ad, - int port) -{ - return _android_dev_socket_init(&adsquery->dev_socket, opaque, ad, port, - ADS_TYPE_QUERY); -} - -static void -_android_query_socket_destroy(AndroidQuerySocket* adsquery) -{ - _android_query_socket_disconnect(adsquery); - _android_dev_socket_destroy(&adsquery->dev_socket); -} - -static int -_android_query_socket_connect(AndroidQuerySocket* adsquery) -{ - return _android_dev_socket_connect(&adsquery->dev_socket); -} - -static void -_android_query_socket_disconnect(AndroidQuerySocket* adsquery) -{ - _android_dev_socket_disconnect(&adsquery->dev_socket); -} - -/******************************************************************************** - * Events socket declarations - *******************************************************************************/ - -/* Initializes event socket descriptor. - * Param: - * adsevent - Socket descriptor to initialize. - * opaque - An opaque pointer to associate with the socket. Typicaly it's the - * same pointer that is associated with AndroidDevice instance. - * ad - Android device descriptor that owns the socket. - * port - TCP socket port. - */ -static int _android_event_socket_init(AndroidEventSocket* adsevent, - void* opaque, - AndroidDevice* ad, - int port); - -/* Destroys the event socket descriptor. */ -static void _android_event_socket_destroy(AndroidEventSocket* adsevent); - -/* Synchronously connects event socket. - * Param: - * adsevent - Descriptor for the event socket to connect. Must have 'deadline' - * field properly setup. - * Return: - * Zero on success, or non-zero on failure. - */ -static int _android_event_socket_connect_sync(AndroidEventSocket* adsevent); - -/* Initiates asynchronous event socket connection. - * Param: - * adsevent - Descriptor for the event socket to connect. Must have 'deadline' - * field properly setup. - * cb - Callback to invoke when socket connection is completed. Can be NULL. - * Return: - * Zero on success, or non-zero on failure. - */ -static int _android_event_socket_connect_async(AndroidEventSocket* adsevent, - ads_socket_connected_cb cb); - -/* Disconnects the event socket. */ -static void _android_event_socket_disconnect(AndroidEventSocket* adsevent); - -/* Initiates listening on the event socket. - * Param: - * adsevent - Descriptor for the event socket to listen on. - * str, strsize - Buffer where to read the string. - * cb - A callback to call when the event string is read. Can be NULL. - * Return: - * Zero on success, or non-zero on failure. - */ -static int _android_event_socket_listen(AndroidEventSocket* adsevent, - char* str, - int strsize, - event_cb cb); - -/* Asynchronously sends data via event socket. - * Param: - * adsevent - Descriptor for the event socket to send data to. - * data, size - Buffer containing data to send. - * free_on_close - A boolean flag indicating whether the data buffer should be - * freed upon data transfer completion. - * cb - Callback to invoke when data transfer is completed. - * opaque - An opaque pointer to pass to the transfer completion callback. - */ -static int _android_event_socket_send(AndroidEventSocket* adsevent, - void* data, - int size, - int free_on_close, - async_send_cb cb, - void* opaque); - -/* Cancels all asynchronous data transfers on the event socket. - * Param: - * adsevent - Descriptor for the event socket to cancel data transfer. - * reason - Reason for the cancellation. - */ -static void _android_event_socket_cancel_send(AndroidEventSocket* adsevent, - ATResult reason); - -/* Event socket's asynchronous I/O looper callback. - * Param: - * opaque - AndroidEventSocket instance. - * fd - Socket's FD. - * events - I/O type bitsmask (read | write). - */ -static void _on_event_socket_io(void* opaque, int fd, unsigned events); - -/* Callback that is invoked when asynchronous event socket connection is - * completed. */ -static void _on_event_socket_connected(AndroidEventSocket* adsevent, int failure); - -/* Callback that is invoked when an event is received from the device. */ -static void _on_event_received(AndroidEventSocket* adsevent); - -/* Gets I/O looper for asynchronous I/O on event socket. */ -AINLINED Looper* -_aes_looper(AndroidEventSocket* adsevent) -{ - return adsevent->dev_socket.ad->looper; -} - -/******************************************************************************** - * Events socket implementation - *******************************************************************************/ - -static int -_android_event_socket_init(AndroidEventSocket* adsevent, - void* opaque, - AndroidDevice* ad, - int port) -{ - return _android_dev_socket_init(&adsevent->dev_socket, opaque, ad, port, - ADS_TYPE_EVENT); -} - -static void -_android_event_socket_destroy(AndroidEventSocket* adsevent) -{ - _android_event_socket_disconnect(adsevent); - _android_dev_socket_destroy(&adsevent->dev_socket); -} - - -static int -_android_event_socket_connect_sync(AndroidEventSocket* adsevent) -{ - AndroidDevSocket* ads = &adsevent->dev_socket; - const int res = _android_dev_socket_connect(&adsevent->dev_socket); - if (res == 0) { - /* Prepare for async I/O on the event socket. */ - loopIo_init(adsevent->io, _aes_looper(adsevent), ads->fd, - _on_event_socket_io, adsevent); - } - return res; -} - -static int -_android_event_socket_connect_async(AndroidEventSocket* adsevent, - ads_socket_connected_cb cb) -{ - AsyncStatus status; - AndroidDevSocket* ads = &adsevent->dev_socket; - - /* Create asynchronous socket. */ - ads->fd = socket_create_inet(SOCKET_STREAM); - if (ads->fd < 0) { - D("Unable to create socket for channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - if (cb != NULL) { - cb(ads->opaque, ads, errno); - } - return -1; - } - socket_set_nonblock(ads->fd); - - /* Prepare for async I/O on the event socket. */ - loopIo_init(adsevent->io, _aes_looper(adsevent), ads->fd, - _on_event_socket_io, adsevent); - - /* Try to connect. */ - ads->socket_status = ADS_CONNECTING; - adsevent->on_connected = cb; - status = asyncConnector_init(adsevent->connector, &ads->address, adsevent->io); - switch (status) { - case ASYNC_COMPLETE: - /* We're connected to the device socket. */ - ads->socket_status = ADS_CONNECTED; - _on_event_socket_connected(adsevent, 0); - break; - case ASYNC_ERROR: - _on_event_socket_connected(adsevent, errno); - break; - case ASYNC_NEED_MORE: - /* Attempt to connect would block, so connection competion is - * delegates to the looper's I/O routine. */ - default: - break; - } - - return 0; -} - -static void -_android_event_socket_disconnect(AndroidEventSocket* adsevent) -{ - AndroidDevSocket* ads = &adsevent->dev_socket; - - if (ads->socket_status != ADS_DISCONNECTED) { - /* Cancel data transfer. */ - _android_event_socket_cancel_send(adsevent, ATR_DISCONNECT); - - /* Stop all async I/O. */ - loopIo_done(adsevent->io); - - /* Disconnect common socket. */ - _android_dev_socket_disconnect(ads); - } -} - -static int -_android_event_socket_listen(AndroidEventSocket* adsevent, - char* str, - int strsize, - event_cb cb) -{ - AsyncStatus status; - AndroidDevSocket* ads = &adsevent->dev_socket; - - /* Make sure that device is connected. */ - if (ads->socket_status < ADS_CONNECTED) { - D("Attempt to listen on a disconnected channel '%s'@%d", - _ads_id_str(ads), _ads_port(ads)); - errno = ECONNRESET; - return -1; - } - - /* NOTE: only one reader at any given time! */ - adsevent->on_event = cb; - asyncLineReader_init(&adsevent->alr, str, strsize, adsevent->io); - /* Default EOL for the line reader was '\n'. */ - asyncLineReader_setEOL(&adsevent->alr, '\0'); - status = asyncLineReader_read(&adsevent->alr); - if (status == ASYNC_COMPLETE) { - /* Data has been transferred immediately. Do the callback here. */ - _on_event_received(adsevent); - } else if (status == ASYNC_ERROR) { - D("Error while listening on channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - /* There is one special failure here, when buffer was too small to - * contain the entire string. This is not an I/O, but rather a - * protocol error. So we don't report it to the I/O failure - * callback. */ - if (errno == ENOMEM) { - _on_event_received(adsevent); - } else { - if (ads->ad->on_io_failure != NULL) { - ads->ad->on_io_failure(ads->ad->opaque, ads->ad, errno); - } - } - return -1; - } - return 0; -} - -static int -_android_event_socket_send(AndroidEventSocket* adsevent, - void* data, - int size, - int free_on_close, - async_send_cb cb, - void* opaque) -{ - /* Create data transfer descriptor, and place it at the end of the list. */ - AsyncSendBuffer* const desc = - _async_send_buffer_create(data, size, free_on_close, cb, opaque); - AsyncSendBuffer** place = &adsevent->send_pending; - while (*place != NULL) { - place = &((*place)->next); - } - *place = desc; - - /* We're ready to transfer data. */ - loopIo_wantWrite(adsevent->io); - - return 0; -} - -static void -_android_event_socket_cancel_send(AndroidEventSocket* adsevent, ATResult reason) -{ - while (adsevent->send_pending != NULL) { - AsyncSendBuffer* const to_cancel = adsevent->send_pending; - adsevent->send_pending = to_cancel->next; - _async_send_buffer_complete(to_cancel, reason); - } - loopIo_dontWantWrite(adsevent->io); -} - -static void -_on_event_socket_io(void* opaque, int fd, unsigned events) -{ - AsyncStatus status; - AndroidEventSocket* adsevent = (AndroidEventSocket*)opaque; - AndroidDevSocket* ads = &adsevent->dev_socket; - - /* Lets see if we're still wating on a connection to occur. */ - if (ads->socket_status == ADS_CONNECTING) { - /* Complete socket connection. */ - status = asyncConnector_run(adsevent->connector); - if (status == ASYNC_COMPLETE) { - /* We're connected to the device socket. */ - ads->socket_status = ADS_CONNECTED; - D("Channel '%s'@%d is connected asynchronously", - _ads_id_str(ads), _ads_port(ads)); - _on_event_socket_connected(adsevent, 0); - } else if (status == ASYNC_ERROR) { - _on_event_socket_connected(adsevent, adsevent->connector->error); - } - return; - } - - /* - * Device is connected. Continue with the data transfer. - */ - - if ((events & LOOP_IO_READ) != 0) { - /* Continue reading data. */ - status = asyncLineReader_read(&adsevent->alr); - if (status == ASYNC_COMPLETE) { - _on_event_received(adsevent); - } else if (status == ASYNC_ERROR) { - D("I/O failure while reading from channel '%s'@%d: %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - /* There is one special failure here, when buffer was too small to - * contain the entire string. This is not an I/O, but rather a - * protocol error. So we don't report it to the I/O failure - * callback. */ - if (errno == ENOMEM) { - _on_event_received(adsevent); - } else { - if (ads->ad->on_io_failure != NULL) { - ads->ad->on_io_failure(ads->ad->opaque, ads->ad, errno); - } - } - } - } - - if ((events & LOOP_IO_WRITE) != 0) { - while (adsevent->send_pending != NULL) { - AsyncSendBuffer* to_send = adsevent->send_pending; - const int offset = to_send->data_size - to_send->data_remaining; - const int sent = socket_send(ads->fd, to_send->data + offset, - to_send->data_remaining); - if (sent < 0) { - if (errno == EWOULDBLOCK) { - /* Try again later. */ - return; - } else { - /* An error has occured. */ - _android_event_socket_cancel_send(adsevent, ATR_IO_ERROR); - if (ads->ad->on_io_failure != NULL) { - ads->ad->on_io_failure(ads->ad->opaque, ads->ad, errno); - } - return; - } - } else if (sent == 0) { - /* Disconnect condition. */ - _android_event_socket_cancel_send(adsevent, ATR_DISCONNECT); - if (ads->ad->on_io_failure != NULL) { - ads->ad->on_io_failure(ads->ad->opaque, ads->ad, errno); - } - return; - } else if (sent == to_send->data_remaining) { - /* All data is sent. */ - adsevent->send_pending = to_send->next; - _async_send_buffer_complete(to_send, ATR_SUCCESS); - } else { - /* Chunk is sent. */ - to_send->data_remaining -= sent; - return; - } - } - loopIo_dontWantWrite(adsevent->io); - } -} - -static void -_on_event_socket_connected(AndroidEventSocket* adsevent, int failure) -{ - int res; - AndroidDevSocket* ads = &adsevent->dev_socket; - - if (failure) { - _android_event_socket_disconnect(adsevent); - if (adsevent->on_connected != NULL) { - adsevent->on_connected(ads->opaque, ads, failure); - } - return; - } - - /* Complete event socket connection by identifying it as "event" socket with - * the application. */ - res = _android_dev_socket_register(ads); - if (res) { - const int save_error = errno; - _android_event_socket_disconnect(adsevent); - errno = save_error; - } - - /* Notify callback about connection completion. */ - if (adsevent->on_connected != NULL) { - if (res) { - adsevent->on_connected(ads->opaque, ads, errno); - } else { - adsevent->on_connected(ads->opaque, ads, 0); - } - } -} - -static void -_on_event_received(AndroidEventSocket* adsevent) -{ - if (adsevent->on_event != NULL) { - AndroidDevice* ad = adsevent->dev_socket.ad; - adsevent->on_event(ad->opaque, ad, (char*)adsevent->alr.buffer, - adsevent->alr.pos); - } -} - -/******************************************************************************** - * Android device connection - *******************************************************************************/ - -/* Callback that is invoked when event socket is connected and registered as part - * of the _android_device_connect_async API. - * Param: - * opaque - Opaque pointer associated with AndroidDevice instance. - * ads - Common socket descriptor for the event socket. - * failure - If zero connection has succeeded, otherwise contains 'errno'-reason - * for connection failure. - */ -static void -_on_android_device_connected_async(void* opaque, - AndroidDevSocket* ads, - int failure) -{ - int res; - AndroidDevice* ad = ads->ad; - - if (failure) { - /* Depending on the failure code we will either retry, or bail out. */ - switch (failure) { - case EPIPE: - case EAGAIN: - case EINPROGRESS: - case EALREADY: - case EHOSTUNREACH: - case EHOSTDOWN: - case ECONNREFUSED: - case ESHUTDOWN: - case ENOTCONN: - case ECONNRESET: - case ECONNABORTED: - case ENETRESET: - case ENETUNREACH: - case ENETDOWN: - case EBUSY: -#if !defined(_DARWIN_C_SOURCE) && !defined(_WIN32) - case ERESTART: - case ECOMM: - case ENONET: -#endif /* !_DARWIN_C_SOURCE && !_WIN32 */ - /* Device is not available / reachable at the moment. - * Retry connection later. */ - loopTimer_startRelative(ad->timer, ADS_RETRY_CONNECTION_TIMEOUT); - return; - default: - D("Failed to asynchronously connect channel '%s':%d %s", - _ads_id_str(ads), _ads_port(ads), strerror(errno)); - if (ad->on_connected != NULL) { - ad->on_connected(ad->opaque, ad, failure); - } - break; - } - return; - } - - /* Event socket is connected. Connect the query socket now. Give it 5 - * seconds to connect. */ - _ads_set_deadline(&ad->query_socket.dev_socket, 5000); - res = _android_query_socket_connect(&ad->query_socket); - if (res == 0) { - /* Query socket is connected. */ - if (ad->on_connected != NULL) { - ad->on_connected(ad->opaque, ad, 0); - } - } else { - /* If connection completion has failed - disconnect the sockets. */ - _android_event_socket_disconnect(&ad->event_socket); - _android_query_socket_disconnect(&ad->query_socket); - - if (ad->on_connected != NULL) { - ad->on_connected(ad->opaque, ad, errno); - } - } -} - -static void -_on_timer(void* opaque) -{ - /* Retry the connection. */ - AndroidDevice* ad = (AndroidDevice*)opaque; - android_device_connect_async(ad, ad->on_connected); -} - -/* Destroys and frees the descriptor. */ -static void -_android_device_free(AndroidDevice* ad) -{ - if (ad != NULL) { - _android_event_socket_destroy(&ad->event_socket); - _android_query_socket_destroy(&ad->query_socket); - - /* Delete asynchronous I/O looper. */ - if (ad->looper != NULL ) { - loopTimer_done(ad->timer); - looper_free(ad->looper); - } - - /* Delete synchronous I/O looper. */ - if (ad->io_looper != NULL) { - iolooper_reset(ad->io_looper); - iolooper_free(ad->io_looper); - } - - AFREE(ad); - } -} - -/******************************************************************************** - * Android device API - *******************************************************************************/ - -AndroidDevice* -android_device_init(void* opaque, int port, io_failure_cb on_io_failure) -{ - int res; - AndroidDevice* ad; - - ANEW0(ad); - - ad->opaque = opaque; - ad->on_io_failure = on_io_failure; - - /* Create I/O looper for synchronous I/O on the device. */ - ad->io_looper = iolooper_new(); - if (ad->io_looper == NULL) { - E("Unable to create synchronous I/O looper for android device."); - _android_device_free(ad); - return NULL; - } - - /* Create a looper for asynchronous I/O on the device. */ - ad->looper = looper_newCore(); - if (ad->looper != NULL) { - /* Create a timer that will be used for connection retries. */ - loopTimer_init(ad->timer, ad->looper, _on_timer, ad); - } else { - E("Unable to create asynchronous I/O looper for android device."); - _android_device_free(ad); - return NULL; - } - - /* Init query socket. */ - res = _android_query_socket_init(&ad->query_socket, opaque, ad, port); - if (res) { - _android_device_free(ad); - return NULL; - } - - /* Init event socket. */ - res = _android_event_socket_init(&ad->event_socket, opaque, ad, port); - if (res) { - _android_device_free(ad); - return NULL; - } - - return ad; -} - -void -android_device_destroy(AndroidDevice* ad) -{ - if (ad != NULL) { - _android_device_free(ad); - } -} - -int -android_device_connect_sync(AndroidDevice* ad, int to) -{ - int res; - - /* Setup deadline for the connections. */ - _ads_set_deadline(&ad->query_socket.dev_socket, to); - ad->event_socket.dev_socket.deadline = ad->query_socket.dev_socket.deadline; - - /* Connect the query socket first. */ - res = _android_query_socket_connect(&ad->query_socket); - if (!res) { - /* Connect to the event socket next. */ - res = _android_event_socket_connect_sync(&ad->event_socket); - } - - return res; -} - -int -android_device_connect_async(AndroidDevice* ad, device_connected_cb on_connected) -{ - /* No deadline for async connections. */ - ad->query_socket.dev_socket.deadline = DURATION_INFINITE; - ad->event_socket.dev_socket.deadline = DURATION_INFINITE; - - /* Connect to the event socket first, and delegate query socket connection - * into callback invoked when event socket is connected. NOTE: In case of - * failure 'on_connected' callback has already been called from - * _on_android_device_connected_async routine. */ - ad->on_connected = on_connected; - return _android_event_socket_connect_async(&ad->event_socket, - _on_android_device_connected_async); -} - -void -android_device_disconnect(AndroidDevice* ad) -{ - _android_event_socket_disconnect(&ad->event_socket); - _android_query_socket_disconnect(&ad->query_socket); -} - -int -android_device_query(AndroidDevice* ad, - const char* query, - char* buff, - size_t buffsize, - int to) -{ - int res; - - /* Setup deadline for the query. */ - _ads_set_deadline(&ad->query_socket.dev_socket, to); - - /* Send the query. */ - res = _android_dev_socket_send(&ad->query_socket.dev_socket, query, - strlen(query) + 1); - if (res > 0) { - /* Receive the response. */ - res = _android_dev_socket_read_response(&ad->query_socket.dev_socket, - buff, buffsize); - return (res >= 0) ? 0 : -1; - } - - return -1; -} - -int -android_device_start_query(AndroidDevice* ad, const char* query, int to) -{ - int res; - - /* Setup deadline for the query. */ - _ads_set_deadline(&ad->query_socket.dev_socket, to); - - /* Send the query header. */ - res = _android_dev_socket_send(&ad->query_socket.dev_socket, query, - strlen(query) + 1); - return (res > 0) ? 0 : -1; -} - -int -android_device_send_query_data(AndroidDevice* ad, const void* data, int size) -{ - return _android_dev_socket_send(&ad->query_socket.dev_socket, data, size); -} - -int -android_device_complete_query(AndroidDevice* ad, char* buff, size_t buffsize) -{ - /* Receive the response to the query. */ - const int res = _android_dev_socket_read_response(&ad->query_socket.dev_socket, - buff, buffsize); - return (res >= 0) ? 0 : -1; -} - -int -android_device_listen(AndroidDevice* ad, - char* buff, - int buffsize, - event_cb on_event) -{ - return _android_event_socket_listen(&ad->event_socket, buff, buffsize, - on_event); -} - -int -android_device_send_async(AndroidDevice* ad, - void* data, - int size, - int free_on_close, - async_send_cb cb, - void* opaque) -{ - return _android_event_socket_send(&ad->event_socket, data, size, - free_on_close, cb, opaque); -} diff --git a/android/android-device.h b/android/android-device.h deleted file mode 100644 index 6825819..0000000 --- a/android/android-device.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (C) 2011 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef ANDROID_ANDROID_DEVICE_H_ -#define ANDROID_ANDROID_DEVICE_H_ - -/* - * Encapsulates an exchange protocol between the emulator, and an Android device - * that is connected to the host via USB. The communication is established over - * a TCP port forwarding, enabled by ADB (always use 'adb -d forward ...' variant - * of this command, so ADB will know to enable port forwarding on the connected - * device, and not on the emulator's guest system). - * - * Exchange protocol contains two channel: - * - * - Query channel. - * - Event channel. - * - * Both channels are implemented on top of TCP sockets that are connected to the - * same port. - * - * I QUERY CHANNEL. - * Query channel is intended to send queries to and receive responses from the - * connected device. It is implemented on top of iolooper_xxx API (see iolooper.h) - * because it must work outside of the main event loop. This is required to enable - * proper initialization of components (such as sensors) that must be set up - * before emulator enters the main loop. - * - * II EVENT CHANNEL. - * Event channel is intended to listen on events sent from the device, and - * asynchronously report them back to the client of this API by invoking an event - * callback that was registered by the client. Event channel is implemented on - * top of asyncXxx API (see android/async-utils.*). Note that using of asyncXxx - * API limits the use of event channel to the time after the emulator has entered - * its main event loop. The only exception is if event channel is connected from - * android_device_connect_sync API, in which case iolooper_xxx API is used to - * establish the connection. However, even in this case listening for events will - * not be available until after the emulator enters its event loop, since event - * listening always uses asyncXxx API. - * - * III. ESTABLISHING CONNECTION. - * ADB port forwarding requires that the server socket is to be run on the device, - * while emulator must use a client socket for communication. Thus, it's the - * emulator that initiates the connection. - * - * There are two ways how emulator can initiate the connection: - * - * - Synchronous connection. - * - Asynchronous connection. - * - * III.I SYNCHROUNOUS CONNECTION. - * Synchronous connection is initiated via android_device_connect_sync API, and - * completes synchronously. - * - * This API should be used when connection with the device is required at the time - * of the call. For instance, when initializing sensor emulation, connection with - * the device is required to properly set up the emulator before the guest system - * starts, and before emulator enters its main event loop. - * - * III.II ASYNCHRONOUS CONNECTION. - * Asynchronous connection is initiated via android_device_connect_async API. The - * main difference with the synchronous connection is that this API will not fail - * if connection is not immediately available. If connection is not available at - * the time of the call, the API will schedule a retry (based on a timer), and - * will continue reprying untill connection becomes available, or until an error - * occurs that prevent further retries. - * - * This API should be used when ... Well, whenever appropriate. For instance, - * sensor emulation will use this API to restore lost connection with the device. - * - * NOTE: Asynchronous connection will complete no sooner than the emulator enters - * its main loop. - * - * IV EXCHANGE PROTOCOL. - * Obviously, there must be some application running on the device, that implements - * a socket server listening on the forwarded TCP port, and accepting the clients. - * - * IV.I Query vs. event channel. - * The exchange protocol assumes, that when a channel is connected, it will - * identify itself by sending a string containing channel type. Only after such - * identification has been made the channel becomes available for use. - * - * IV.II Message format. - * All data that is transferred in both directions over both channels are zero- - * terminated strings. - */ - -#include "qemu-common.h" -#include "android/async-utils.h" -#include "android/utils/debug.h" - -/* TCP port reserved for sensor emulation. */ -#define AD_SENSOR_PORT 1968 - -/* Definis infinite timeout. */ -#define AD_INFINITE_WAIT -1 - -/* Enumerates results of asynchronous data transfer. - */ -typedef enum ATResult { - /* Data transfer has been completed. */ - ATR_SUCCESS, - /* Socket got disconnected while data transfer has been in progress. */ - ATR_DISCONNECT, - /* An I/O error has occured. 'errno' contains error value. */ - ATR_IO_ERROR, -} ATResult; - -/* Android device descriptor. */ -typedef struct AndroidDevice AndroidDevice; - -/******************************************************************************** - * Callback declarations - *******************************************************************************/ - -/* Callback routine that is invoked when android device is connected, or failed - * to connect. As discussed above, this callback is called when both, query and - * event channels have been connected. This callback is used only for asynchronous - * connections. - * Param: - * opaque - Opaque pointer that was passed to android_device_init API. - * ad - Androd device descriptor for the connection. - * failure - Zero indicates that connection with the device has been successfuly - * established. Non-zero vaule passed in this parameter indicates a failure, - * and contains 'errno'-reason for failure. - */ -typedef void (*device_connected_cb)(void* opaque, AndroidDevice* ad, int failure); - -/* Callback routine that is invoked on an event received in the event channel. - * NOTE: It's important to check 'errno' in this callback. If 'errno' is set to - * ENOMEM, this signals that buffer passed to android_device_listen was too small - * to contain the entire event message. - * Param: - * opaque - Opaque pointer that was passed to android_device_init API. - * ad - Androd device descriptor for the connection. - * msg - Event message (a zero-terminated string) received from the device. - * msgsize - Event message size (including zero-terminator). - */ -typedef void (*event_cb)(void* opaque, AndroidDevice* ad, char* msg, int msgsize); - -/* Callback routine that is invoked when an I/O failure occurs on a channel. - * Note that this callback will not be invoked on connection failures. - * Param: - * opaque - Opaque pointer that was passed to android_device_init API. - * ad - Android device instance - * failure - Contains 'errno' indicating the reason for failure. - */ -typedef void (*io_failure_cb)(void* opaque, AndroidDevice* ad, int failure); - -/* Callback routine that is invoked when an asynchronous data send has been - * completed. - * Param: - * opaque - An opaque pointer associated with the data. - * res - Result of data transfer. - * data, size - Transferred data buffer. - * sent - Number of sent bytes. - */ -typedef void (*async_send_cb)(void* opaque, - ATResult res, - void* data, - int size, - int sent); - -/******************************************************************************** - * Android Device API. - *******************************************************************************/ - -/* Initializes android device descriptor. - * Param: - * opaque - An opaque pointer to associate with the descriptor. This pointer - * will be passed to all callbacks (see above) that were invoked by the - * initializing android device instance. - * port - TCP port to use for connection. - * on_io_failure - Callback to invoke when an I/O failure occurs on a channel - * used by the initializing android device instance. Can be NULL. - * Return: - * Initialized android device descriptor on success, or NULL on failure. - */ -extern AndroidDevice* android_device_init(void* opaque, - int port, - io_failure_cb on_io_failure); - -/* Disconnects and destroys android device descriptor. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * Note that memory allocated for this descriptor will be freed in this - * routine. - */ -extern void android_device_destroy(AndroidDevice* ad); - -/* Synchronously connects to the device. See notes above for more details. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * to - Milliseconds to wait for connection to be established. - * Return: - * Zero on success, or non-zero value on failure with 'errno' properly set. - */ -extern int android_device_connect_sync(AndroidDevice* ad, int to); - -/* Asynchronously connects to the device. See notes above for more details. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * on_connected - Callback to invoke when connection is completed (i,e, both, - * event, and query channels have been connected). This parameter can be - * NULL. Note that connection errors will be also reported through this - * callback. Also note that this callback will be invoked even if this - * routine returns with a failure. - * Return: - * Zero on success, or non-zero value on failure with 'errno' properly set. - */ -extern int android_device_connect_async(AndroidDevice* ad, - device_connected_cb on_connected); - -/* Disconnects from the android device. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - */ -extern void android_device_disconnect(AndroidDevice* ad); - -/* Queries the device via query channel. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * query - Zero-terminated query string. - * buff, buffsize - Buffer where to receive the response to the query. - * to - Milliseconds to wait for the entire query to complete. - * Return: - * Zero on success, or non-zero value on failure with 'errno' properly set: - * - 0 Indicates that the server has failed the query. - * - Anything else indicates an I/O error. - */ -extern int android_device_query(AndroidDevice* ad, - const char* query, - char* buff, - size_t buffsize, - int to); - -/* Starts a query that may require more than one buffer transfer. - * This routine allows to initiate a query that may require more than one call to - * send_data, or may have a format that differs from the usual (a zero-terminated - * string). For instance, sending a BLOB data should use this routine to start a - * a query, then use android_device_send_query_data to transfer the data, and - * then call android_device_complete_query to obtain the response. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * query - Zero-terminated query string. - * to - Milliseconds to wait for the entire query to complete. - * Return: - * Zero on success, or non-zero value on failure with 'errno' properly set: - * - 0 Indicates that the server has failed the query. - * - Anything else indicates an I/O error. - */ -extern int android_device_start_query(AndroidDevice* ad, - const char* query, - int to); - -/* Sends data block for a query started with android_device_start_query - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * data, size - Data to transfer. - * Return: - * Number of bytes transferred on success, or -1 on failure with errno - * containing the reason for failure. - */ -extern int android_device_send_query_data(AndroidDevice* ad, - const void* data, - int size); - -/* Completes a query started with android_device_start_query, and receives the - * query response. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * buff, buffsize - Buffer where to receive the response to the query. - * Return: - * Zero on success, or non-zero value on failure with 'errno' properly set. - */ -extern int android_device_complete_query(AndroidDevice* ad, char* buff, size_t buffsize); - -/* Start listening on the event channel. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * buff, buffsize - Buffer where to receive the event message. - * on_event - Callback to invoke on event. Note that this callback will be - * invoked even if this routine returns with a failure. - * Return: - * Zero on success, or non-zero value on failure with 'errno' properly set. - */ -extern int android_device_listen(AndroidDevice* ad, - char* buff, - int buffsize, - event_cb on_event); - -/* Asynchronously sends data to the android device. - * Param: - * ad - Android device descriptor, returned from android_device_init API. - * data, size - Buffer containing data to send. - * free_on_close - A boolean flag indicating whether the data buffer should be - * freed upon data transfer completion. - * cb - Callback to invoke when data transfer is completed. - * opaque - An opaque pointer to pass to the transfer completion callback. - */ -extern int android_device_send_async(AndroidDevice* ad, - void* data, - int size, - int free_on_close, - async_send_cb cb, - void* opaque); - -#endif /* ANDROID_ANDROID_DEVICE_H_ */ diff --git a/android/android.h b/android/android.h index 189b5c2..e32f9f5 100644 --- a/android/android.h +++ b/android/android.h @@ -97,6 +97,13 @@ extern int android_parse_network_speed(const char* speed); * accordingly. returns -1 on error, 0 on success */ extern int android_parse_network_latency(const char* delay); +/** in qemu_setup.c */ + +#define ANDROID_GLSTRING_BUF_SIZE 128 +extern char android_gl_vendor[ANDROID_GLSTRING_BUF_SIZE]; +extern char android_gl_renderer[ANDROID_GLSTRING_BUF_SIZE]; +extern char android_gl_version[ANDROID_GLSTRING_BUF_SIZE]; + extern void android_emulation_setup( void ); extern void android_emulation_teardown( void ); diff --git a/android/async-io-common.h b/android/async-io-common.h new file mode 100644 index 0000000..02b2c96 --- /dev/null +++ b/android/async-io-common.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ANDROID_ASYNC_IO_COMMON_H_ +#define ANDROID_ASYNC_IO_COMMON_H_ + +/* + * Contains declarations common for asynchronous socket I/O + */ + +/* Enumerates asynchronous I/O states. + * Values from this enum are passed to callbacks associated with an I/O, + * indicating at what state the I/O is. */ +typedef enum AsyncIOState { + /* Asynchronous I/O has been queued. (0) */ + ASIO_STATE_QUEUED, + /* Asynchronous I/O has started. This state indicates that I/O has been + * performed for the first time. (1) */ + ASIO_STATE_STARTED, + /* Asynchronous I/O is continuing. This state indicates that I/O has been + * invoked for the second (or more) time. (2) */ + ASIO_STATE_CONTINUES, + /* Asynchronous I/O is about to be retried. (3) */ + ASIO_STATE_RETRYING, + /* Asynchronous I/O has been successfuly completed. (4) */ + ASIO_STATE_SUCCEEDED, + /* Asynchronous I/O has failed. (5) */ + ASIO_STATE_FAILED, + /* Asynchronous I/O has timed out. (6) */ + ASIO_STATE_TIMED_OUT, + /* Asynchronous I/O has been cancelled (due to disconnect, for + * instance). (7) */ + ASIO_STATE_CANCELLED, + /* Asynchronous I/O is finished and is about to be discarder. This state is + * useful in case there is an association between an I/O and some client's + * component, that holds a reference associated with this I/O. When callback + * is invoked with this state, it means that it's safe to drop that extra + * reference associated with the I/O (8) */ + ASIO_STATE_FINISHED, +} AsyncIOState; + +/* Enumerates actions to perform with an I/O on state transition. + * Values from this enum are returned from async I/O callbacks, indicating what + * action should be performed with the I/O by I/O handler. */ +typedef enum AsyncIOAction { + /* I/O is done. Perform default action depending on I/O type. */ + ASIO_ACTION_DONE, + /* Abort the I/O. */ + ASIO_ACTION_ABORT, + /* Retry the I/O. */ + ASIO_ACTION_RETRY, +} AsyncIOAction; + +#endif /* ANDROID_ASYNC_IO_COMMON_H_ */ diff --git a/android/async-socket-connector.c b/android/async-socket-connector.c new file mode 100644 index 0000000..f4d51b5 --- /dev/null +++ b/android/async-socket-connector.c @@ -0,0 +1,412 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Encapsulates exchange protocol between the emulator, and an Android device + * that is connected to the host via USB. The communication is established over + * a TCP port forwarding, enabled by ADB. + */ + +#include "android/utils/debug.h" +#include "android/async-socket-connector.h" +#include "utils/panic.h" +#include "iolooper.h" + +#define E(...) derror(__VA_ARGS__) +#define W(...) dwarning(__VA_ARGS__) +#define D(...) VERBOSE_PRINT(asconnector,__VA_ARGS__) +#define D_ACTIVE VERBOSE_CHECK(asconnector) + +#define TRACE_ON 0 + +#if TRACE_ON +#define T(...) VERBOSE_PRINT(asconnector,__VA_ARGS__) +#else +#define T(...) +#endif + +/******************************************************************************** + * Internals + *******************************************************************************/ + +struct AsyncSocketConnector { + /* TCP address for the connection. */ + SockAddress address; + /* I/O looper for asynchronous I/O. */ + Looper* looper; + /* I/O port for asynchronous connection. */ + LoopIo connector_io[1]; + /* Timer that is used to retry asynchronous connections. */ + LoopTimer connector_timer[1]; + /* Asynchronous connector to the socket. */ + AsyncConnector connector[1]; + /* Callback to invoke on connection events. */ + asc_event_cb on_connected_cb; + /* An opaque parameter to pass to the connection callback. */ + void* on_connected_cb_opaque; + /* Retry timeout in milliseconds. */ + int retry_to; + /* Socket descriptor for the connection. */ + int fd; + /* Number of outstanding references to the connector. */ + int ref_count; + /* Flags whether (1) or not (0) connector owns the looper. */ + int owns_looper; +}; + +/* Asynchronous I/O looper callback invoked by the connector. + * Param: + * opaque - AsyncSocketConnector instance. + * fd, events - Standard I/O callback parameters. + */ +static void _on_async_socket_connector_io(void* opaque, int fd, unsigned events); + +/* Gets socket's address string. */ +AINLINED const char* +_asc_socket_string(AsyncSocketConnector* connector) +{ + return sock_address_to_string(&connector->address); +} + +/* Destroys AsyncSocketConnector instance. + * Param: + * connector - Initialized AsyncSocketConnector instance. + */ +static void +_async_socket_connector_free(AsyncSocketConnector* connector) +{ + if (connector != NULL) { + T("ASC %s: Connector is destroying...", _asc_socket_string(connector)); + + /* Stop all activities. */ + if (asyncConnector_stop(connector->connector) == 0) { + /* Connection was in progress. We need to destroy I/O descriptor for + * that connection. */ + D("ASC %s: Stopped async connection in progress.", + _asc_socket_string(connector)); + loopIo_done(connector->connector_io); + } + + /* Free allocated resources. */ + if (connector->looper != NULL) { + loopTimer_done(connector->connector_timer); + if (connector->owns_looper) { + looper_free(connector->looper); + } + } + + if (connector->fd >= 0) { + socket_close(connector->fd); + } + + T("ASC %s: Connector is destroyed", _asc_socket_string(connector)); + + sock_address_done(&connector->address); + + AFREE(connector); + } +} + +/* Opens connection socket. + * Param: + * connector - Initialized AsyncSocketConnector instance. + * Return: + * 0 on success, or -1 on failure. + */ +static int +_async_socket_connector_open_socket(AsyncSocketConnector* connector) +{ + /* Open socket. */ + connector->fd = socket_create_inet(SOCKET_STREAM); + if (connector->fd < 0) { + D("ASC %s: Unable to create socket: %d -> %s", + _asc_socket_string(connector), errno, strerror(errno)); + return -1; + } + + /* Prepare for async I/O on the connector. */ + socket_set_nonblock(connector->fd); + + T("ASC %s: Connector socket is opened with FD = %d", + _asc_socket_string(connector), connector->fd); + + return 0; +} + +/* Closes connection socket. + * Param: + * connector - Initialized AsyncSocketConnector instance. + * Return: + * 0 on success, or -1 on failure. + */ +static void +_async_socket_connector_close_socket(AsyncSocketConnector* connector) +{ + if (connector->fd >= 0) { + socket_close(connector->fd); + T("ASC %s: Connector socket FD = %d is closed.", + _asc_socket_string(connector), connector->fd); + connector->fd = -1; + } +} + +/* Asynchronous connector (AsyncConnector instance) has completed connection + * attempt. + * Param: + * connector - Initialized AsyncSocketConnector instance. Note: When this + * callback is called, the caller has referenced passed connector object, + * So, it's guaranteed that this connector is not going to be destroyed + * while this routine executes. + * status - Status of the connection attempt. + */ +static void +_on_async_socket_connector_connecting(AsyncSocketConnector* connector, + AsyncStatus status) +{ + AsyncIOAction action = ASIO_ACTION_DONE; + + switch (status) { + case ASYNC_COMPLETE: + loopIo_done(connector->connector_io); + D("Socket '%s' is connected", _asc_socket_string(connector)); + /* Invoke "on connected" callback */ + action = connector->on_connected_cb(connector->on_connected_cb_opaque, + connector, ASIO_STATE_SUCCEEDED); + break; + + case ASYNC_ERROR: + loopIo_done(connector->connector_io); + D("Error while connecting to socket '%s': %d -> %s", + _asc_socket_string(connector), errno, strerror(errno)); + /* Invoke "on connected" callback */ + action = connector->on_connected_cb(connector->on_connected_cb_opaque, + connector, ASIO_STATE_FAILED); + break; + + case ASYNC_NEED_MORE: + T("ASC %s: Waiting on connection to complete. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + return; + } + + if (action == ASIO_ACTION_RETRY) { + D("ASC %s: Retrying connection. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + loopTimer_startRelative(connector->connector_timer, connector->retry_to); + } else if (action == ASIO_ACTION_ABORT) { + D("ASC %s: Client has aborted connection. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + } +} + +static void +_on_async_socket_connector_io(void* opaque, int fd, unsigned events) +{ + AsyncSocketConnector* const connector = (AsyncSocketConnector*)opaque; + + /* Reference the connector while we're handing I/O. */ + async_socket_connector_reference(connector); + + /* Notify the client that another connection attempt is about to start. */ + const AsyncIOAction action = + connector->on_connected_cb(connector->on_connected_cb_opaque, + connector, ASIO_STATE_CONTINUES); + if (action != ASIO_ACTION_ABORT) { + /* Complete socket connection. */ + const AsyncStatus status = asyncConnector_run(connector->connector); + _on_async_socket_connector_connecting(connector, status); + } else { + D("ASC %s: Client has aborted connection. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + } + + /* Release the connector after we're done with handing I/O. */ + async_socket_connector_release(connector); +} + +/* Retry connection timer callback. + * Param: + * opaque - AsyncSocketConnector instance. + */ +static void +_on_async_socket_connector_retry(void* opaque) +{ + AsyncStatus status; + AsyncSocketConnector* const connector = (AsyncSocketConnector*)opaque; + + T("ASC %s: Reconnect timer expired. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + + /* Reference the connector while we're in callback. */ + async_socket_connector_reference(connector); + + /* Invoke the callback to notify about a connection retry attempt. */ + AsyncIOAction action = + connector->on_connected_cb(connector->on_connected_cb_opaque, + connector, ASIO_STATE_RETRYING); + + if (action != ASIO_ACTION_ABORT) { + /* Close handle opened for the previous (failed) attempt. */ + _async_socket_connector_close_socket(connector); + + /* Retry connection attempt. */ + if (_async_socket_connector_open_socket(connector) == 0) { + loopIo_init(connector->connector_io, connector->looper, + connector->fd, _on_async_socket_connector_io, connector); + status = asyncConnector_init(connector->connector, + &connector->address, + connector->connector_io); + } else { + status = ASYNC_ERROR; + } + + _on_async_socket_connector_connecting(connector, status); + } else { + D("ASC %s: Client has aborted connection. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + } + + /* Release the connector after we're done with the callback. */ + async_socket_connector_release(connector); +} + +/******************************************************************************** + * Async connector implementation + *******************************************************************************/ + +AsyncSocketConnector* +async_socket_connector_new(const SockAddress* address, + int retry_to, + asc_event_cb cb, + void* cb_opaque, + Looper* looper) +{ + AsyncSocketConnector* connector; + + if (cb == NULL) { + W("No callback for AsyncSocketConnector for socket '%s'", + sock_address_to_string(address)); + errno = EINVAL; + return NULL; + } + + ANEW0(connector); + + connector->fd = -1; + connector->retry_to = retry_to; + connector->on_connected_cb = cb; + connector->on_connected_cb_opaque = cb_opaque; + connector->ref_count = 1; + + /* Copy socket address. */ +#ifdef _WIN32 + connector->address = *address; +#else + if (sock_address_get_family(address) == SOCKET_UNIX) { + sock_address_init_unix(&connector->address, sock_address_get_path(address)); + } else { + connector->address = *address; + } +#endif + + /* Create a looper for asynchronous I/O. */ + if (looper == NULL) { + connector->looper = looper_newCore(); + if (connector->looper == NULL) { + E("Unable to create I/O looper for AsyncSocketConnector for socket '%s'", + _asc_socket_string(connector)); + cb(cb_opaque, connector, ASIO_STATE_FAILED); + _async_socket_connector_free(connector); + return NULL; + } + connector->owns_looper = 1; + } else { + connector->looper = looper; + connector->owns_looper = 0; + } + + /* Create a timer that will be used for connection retries. */ + loopTimer_init(connector->connector_timer, connector->looper, + _on_async_socket_connector_retry, connector); + + T("ASC %s: New connector object", _asc_socket_string(connector)); + + return connector; +} + +int +async_socket_connector_reference(AsyncSocketConnector* connector) +{ + assert(connector->ref_count > 0); + connector->ref_count++; + return connector->ref_count; +} + +int +async_socket_connector_release(AsyncSocketConnector* connector) +{ + assert(connector->ref_count > 0); + connector->ref_count--; + if (connector->ref_count == 0) { + /* Last reference has been dropped. Destroy this object. */ + _async_socket_connector_free(connector); + return 0; + } + return connector->ref_count; +} + +void +async_socket_connector_connect(AsyncSocketConnector* connector) +{ + AsyncStatus status; + + T("ASC %s: Handling connect request. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + + if (_async_socket_connector_open_socket(connector) == 0) { + const AsyncIOAction action = + connector->on_connected_cb(connector->on_connected_cb_opaque, + connector, ASIO_STATE_STARTED); + if (action == ASIO_ACTION_ABORT) { + D("ASC %s: Client has aborted connection. Connector FD = %d", + _asc_socket_string(connector), connector->fd); + return; + } else { + loopIo_init(connector->connector_io, connector->looper, + connector->fd, _on_async_socket_connector_io, connector); + status = asyncConnector_init(connector->connector, + &connector->address, + connector->connector_io); + } + } else { + status = ASYNC_ERROR; + } + + _on_async_socket_connector_connecting(connector, status); +} + +int +async_socket_connector_pull_fd(AsyncSocketConnector* connector) +{ + const int fd = connector->fd; + if (fd >= 0) { + connector->fd = -1; + } + + T("ASC %s: Client has pulled connector FD %d", _asc_socket_string(connector), fd); + + return fd; +} diff --git a/android/async-socket-connector.h b/android/async-socket-connector.h new file mode 100644 index 0000000..d49d203 --- /dev/null +++ b/android/async-socket-connector.h @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ANDROID_ASYNC_SOCKET_CONNECTOR_H_ +#define ANDROID_ASYNC_SOCKET_CONNECTOR_H_ + +#include "qemu-common.h" +#include "android/async-io-common.h" +#include "android/async-utils.h" + +/* + * Contains declaration of an API that allows asynchronous connection to a + * socket with retries. + * + * The typical usage of this API is as such: + * + * 1. The client creates an asynchronous connector instance by calling + * async_socket_connector_new routine, supplying there address of the socket + * to connect, and a callback to invoke on connection events. + * 2. The client then proceeds with calling async_socket_connector_connect that + * would initiate connection attempts. + * + * The main job on the client side falls on the client's callback routine that + * serves the connection events. Once connection has been initiated, the connector + * will invoke that callback to report current connection status. + * + * In general, there are three connection events passed to the callback: + * 1. Success. + * 2. Failure. + * 3. Retry. + * + * Typically, when client's callback is called for a successful connection, the + * client will pull connected socket's FD from the connector, and then this FD + * will be used by the client for I/O on the connected socket. + * + * When client's callback is invoked with an error (ASIO_STATE_FAILED event), the + * client has an opportunity to review the error (available in 'errno'), and + * either abort the connection by returning ASIO_ACTION_ABORT, or schedule a retry + * by returning ASIO_ACTION_RETRY from the callback. If client returns ASIO_ACTION_ABORT + * from the callback, the connector will stop connection attempts, and will + * self-destruct. If ASIO_ACTION_RETRY is returned from the callback, the connector + * will retry connection attempt after timeout that was set by the caller in the + * call to async_socket_connector_new routine. + * + * When client's callback is invoked with ASIO_STATE_RETRYING (indicating that + * connector is about to retry a connection attempt), the client has an opportunity + * to cancel further connection attempts by returning ASIO_ACTION_ABORT, or it + * can allow another connection attempt by returning ASIO_ACTION_RETRY. + * + * Since it's hard to control lifespan of an object in asynchronous environment, + * we make AsyncSocketConnector a referenced object, that will self-destruct when + * its reference count drops to zero, indicating that the last client has + * abandoned that object. + */ + +/* Declares async socket connector descriptor. */ +typedef struct AsyncSocketConnector AsyncSocketConnector; + +/* Declares callback that connector's client uses to monitor connection + * status / progress. + * Param: + * opaque - An opaque pointer associated with the client. + * connector - AsyncSocketConnector instance. + * event - Event that has occurred. If event is set to ASIO_STATE_FAILED, + * errno contains connection error. + * Return: + * One of AsyncIOAction values. + */ +typedef AsyncIOAction (*asc_event_cb)(void* opaque, + AsyncSocketConnector* connector, + AsyncIOState event); + +/* Creates and initializes AsyncSocketConnector instance. + * Note that upon exit from this routine the reference count to the returned + * object is set to 1. + * Param: + * address - Initialized socket address to connect to. + * retry_to - Timeout to retry a failed connection attempt in milliseconds. + * cb, cb_opaque - Callback to invoke on connection events. This callback is + * required, and must not be NULL. + * looper - An optional (can be NULL) I/O looper to use for connection I/O. If + * this parameter is NULL, the connector will create its own looper. + * Return: + * Initialized AsyncSocketConnector instance. Note that AsyncSocketConnector + * instance returned from this routine will be destroyed by the connector itself, + * when its work on connecting to the socket is completed. Typically, connector + * will destroy its descriptor after client's callback routine returns with a + * status other than ASIO_ACTION_RETRY. + */ +extern AsyncSocketConnector* async_socket_connector_new(const SockAddress* address, + int retry_to, + asc_event_cb cb, + void* cb_opaque, + Looper* looper); + +/* References AsyncSocketConnector object. + * Param: + * connector - Initialized AsyncSocketConnector instance. + * Return: + * Number of outstanding references to the object. + */ +extern int async_socket_connector_reference(AsyncSocketConnector* connector); + +/* Releases AsyncSocketConnector object. + * Note that upon exit from this routine the object might be destroyed, even if + * the routine returns value other than zero. + * Param: + * connector - Initialized AsyncSocketConnector instance. + * Return: + * Number of outstanding references to the object. + */ +extern int async_socket_connector_release(AsyncSocketConnector* connector); + +/* Initiates asynchronous connection. + * Note that connection result will be reported via callback set with the call to + * async_socket_connector_new routine. + * Param: + * connector - Initialized AsyncSocketConnector instance. Note that this + * connector descriptor might be destroyed asynchronously, before this + * routine returns. + */ +extern void async_socket_connector_connect(AsyncSocketConnector* connector); + +/* Pulls socket's file descriptor from the connector. + * This routine should be called from the connection callback on successful + * connection status. This will provide the connector's client with an operational + * socket FD, and at the same time this will tell the connector not to close the + * FD when connector descriptor gets destroyed. + * Param: + * connector - Initialized AsyncSocketConnector instance. + * Return: + * File descriptor for the connected socket. + */ +extern int async_socket_connector_pull_fd(AsyncSocketConnector* connector); + +#endif /* ANDROID_ASYNC_SOCKET_CONNECTOR_H_ */ diff --git a/android/async-socket.c b/android/async-socket.c new file mode 100644 index 0000000..ab4e4b6 --- /dev/null +++ b/android/async-socket.c @@ -0,0 +1,1314 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Encapsulates exchange protocol between the emulator, and an Android device + * that is connected to the host via USB. The communication is established over + * a TCP port forwarding, enabled by ADB. + */ + +#include "android/utils/debug.h" +#include "android/async-socket-connector.h" +#include "android/async-socket.h" +#include "utils/panic.h" +#include "iolooper.h" + +#define E(...) derror(__VA_ARGS__) +#define W(...) dwarning(__VA_ARGS__) +#define D(...) VERBOSE_PRINT(asyncsocket,__VA_ARGS__) +#define D_ACTIVE VERBOSE_CHECK(asyncsocket) + +#define TRACE_ON 0 + +#if TRACE_ON +#define T(...) VERBOSE_PRINT(asyncsocket,__VA_ARGS__) +#else +#define T(...) +#endif + +/******************************************************************************** + * Asynchronous Socket internal API declarations + *******************************************************************************/ + +/* Gets socket's address string. */ +static const char* _async_socket_string(AsyncSocket* as); + +/* Gets socket's looper. */ +static Looper* _async_socket_get_looper(AsyncSocket* as); + +/* Handler for the I/O time out. + * Param: + * as - Asynchronous socket for the I/O. + * asio - Desciptor for the timed out I/O. + */ +static AsyncIOAction _async_socket_io_timed_out(AsyncSocket* as, + AsyncSocketIO* asio); + +/******************************************************************************** + * Asynchronous Socket Reader / Writer + *******************************************************************************/ + +struct AsyncSocketIO { + /* Next I/O in the reader, or writer list. */ + AsyncSocketIO* next; + /* Asynchronous socket for this I/O. */ + AsyncSocket* as; + /* Timer used for time outs on this I/O. */ + LoopTimer timer[1]; + /* An opaque pointer associated with this I/O. */ + void* io_opaque; + /* Buffer where to read / write data. */ + uint8_t* buffer; + /* Bytes to transfer through the socket for this I/O. */ + uint32_t to_transfer; + /* Bytes thransferred through the socket in this I/O. */ + uint32_t transferred; + /* I/O callback for this I/O. */ + on_as_io_cb on_io; + /* I/O type selector: 1 - read, 0 - write. */ + int is_io_read; + /* State of the I/O. */ + AsyncIOState state; + /* Number of outstanding references to the I/O. */ + int ref_count; + /* Deadline for this I/O */ + Duration deadline; +}; + +/* + * Recycling I/O instances. + * Since AsyncSocketIO instances are not that large, it makes sence to recycle + * them for faster allocation, rather than allocating and freeing them for each + * I/O on the socket. + */ + +/* List of recycled I/O descriptors. */ +static AsyncSocketIO* _asio_recycled = NULL; +/* Number of I/O descriptors that are recycled in the _asio_recycled list. */ +static int _recycled_asio_count = 0; +/* Maximum number of I/O descriptors that can be recycled. */ +static const int _max_recycled_asio_num = 32; + +/* Handler for an I/O time-out timer event. + * When this routine is invoked, it indicates that a time out has occurred on an + * I/O. + * Param: + * opaque - AsyncSocketIO instance representing the timed out I/O. + */ +static void _on_async_socket_io_timed_out(void* opaque); + +/* Creates new I/O descriptor. + * Param: + * as - Asynchronous socket for the I/O. + * is_io_read - I/O type selector: 1 - read, 0 - write. + * buffer, len - Reader / writer buffer address. + * io_cb - Callback for this reader / writer. + * io_opaque - An opaque pointer associated with the I/O. + * deadline - Deadline to complete the I/O. + * Return: + * Initialized AsyncSocketIO instance. + */ +static AsyncSocketIO* +_async_socket_rw_new(AsyncSocket* as, + int is_io_read, + void* buffer, + uint32_t len, + on_as_io_cb io_cb, + void* io_opaque, + Duration deadline) +{ + /* Lookup in the recycler first. */ + AsyncSocketIO* asio = _asio_recycled; + if (asio != NULL) { + /* Pull the descriptor from recycler. */ + _asio_recycled = asio->next; + _recycled_asio_count--; + } else { + /* No recycled descriptors. Allocate new one. */ + ANEW0(asio); + } + + asio->next = NULL; + asio->as = as; + asio->is_io_read = is_io_read; + asio->buffer = (uint8_t*)buffer; + asio->to_transfer = len; + asio->transferred = 0; + asio->on_io = io_cb; + asio->io_opaque = io_opaque; + asio->state = ASIO_STATE_QUEUED; + asio->ref_count = 1; + asio->deadline = deadline; + loopTimer_init(asio->timer, _async_socket_get_looper(as), + _on_async_socket_io_timed_out, asio); + loopTimer_startAbsolute(asio->timer, deadline); + + /* Reference socket that is holding this I/O. */ + async_socket_reference(as); + + T("ASocket %s: %s I/O descriptor %p is created for %d bytes of data", + _async_socket_string(as), is_io_read ? "READ" : "WRITE", asio, len); + + return asio; +} + +/* Destroys and frees I/O descriptor. */ +static void +_async_socket_io_free(AsyncSocketIO* asio) +{ + AsyncSocket* const as = asio->as; + + T("ASocket %s: %s I/O descriptor %p is destroyed.", + _async_socket_string(as), asio->is_io_read ? "READ" : "WRITE", asio); + + loopTimer_done(asio->timer); + + /* Try to recycle it first, and free the memory if recycler is full. */ + if (_recycled_asio_count < _max_recycled_asio_num) { + asio->next = _asio_recycled; + _asio_recycled = asio; + _recycled_asio_count++; + } else { + AFREE(asio); + } + + /* Release socket that is holding this I/O. */ + async_socket_release(as); +} + +/* An I/O has been finished and its descriptor is about to be discarded. */ +static void +_async_socket_io_finished(AsyncSocketIO* asio) +{ + /* Notify the client of the I/O that I/O is finished. */ + asio->on_io(asio->io_opaque, asio, ASIO_STATE_FINISHED); +} + +int +async_socket_io_reference(AsyncSocketIO* asio) +{ + assert(asio->ref_count > 0); + asio->ref_count++; + return asio->ref_count; +} + +int +async_socket_io_release(AsyncSocketIO* asio) +{ + assert(asio->ref_count > 0); + asio->ref_count--; + if (asio->ref_count == 0) { + _async_socket_io_finished(asio); + /* Last reference has been dropped. Destroy this object. */ + _async_socket_io_free(asio); + return 0; + } + return asio->ref_count; +} + +/* Creates new asynchronous socket reader. + * Param: + * as - Asynchronous socket for the reader. + * buffer, len - Reader's buffer. + * io_cb - Reader's callback. + * reader_opaque - An opaque pointer associated with the reader. + * deadline - Deadline to complete the operation. + * Return: + * An initialized AsyncSocketIO intance. + */ +static AsyncSocketIO* +_async_socket_reader_new(AsyncSocket* as, + void* buffer, + uint32_t len, + on_as_io_cb io_cb, + void* reader_opaque, + Duration deadline) +{ + AsyncSocketIO* const asio = _async_socket_rw_new(as, 1, buffer, len, io_cb, + reader_opaque, deadline); + return asio; +} + +/* Creates new asynchronous socket writer. + * Param: + * as - Asynchronous socket for the writer. + * buffer, len - Writer's buffer. + * io_cb - Writer's callback. + * writer_opaque - An opaque pointer associated with the writer. + * deadline - Deadline to complete the operation. + * Return: + * An initialized AsyncSocketIO intance. + */ +static AsyncSocketIO* +_async_socket_writer_new(AsyncSocket* as, + const void* buffer, + uint32_t len, + on_as_io_cb io_cb, + void* writer_opaque, + Duration deadline) +{ + AsyncSocketIO* const asio = _async_socket_rw_new(as, 0, (void*)buffer, len, + io_cb, writer_opaque, + deadline); + return asio; +} + +/* I/O timed out. */ +static void +_on_async_socket_io_timed_out(void* opaque) +{ + AsyncSocketIO* const asio = (AsyncSocketIO*)opaque; + AsyncSocket* const as = asio->as; + + D("ASocket %s: %s I/O with deadline %lld has timed out at %lld", + _async_socket_string(as), asio->is_io_read ? "READ" : "WRITE", + asio->deadline, async_socket_deadline(as, 0)); + + /* Reference while in callback. */ + async_socket_io_reference(asio); + _async_socket_io_timed_out(asio->as, asio); + async_socket_io_release(asio); +} + +/******************************************************************************** + * Public Asynchronous Socket I/O API + *******************************************************************************/ + +AsyncSocket* +async_socket_io_get_socket(const AsyncSocketIO* asio) +{ + async_socket_reference(asio->as); + return asio->as; +} + +void +async_socket_io_cancel_time_out(AsyncSocketIO* asio) +{ + loopTimer_stop(asio->timer); +} + +void* +async_socket_io_get_io_opaque(const AsyncSocketIO* asio) +{ + return asio->io_opaque; +} + +void* +async_socket_io_get_client_opaque(const AsyncSocketIO* asio) +{ + return async_socket_get_client_opaque(asio->as); +} + +void* +async_socket_io_get_buffer_info(const AsyncSocketIO* asio, + uint32_t* transferred, + uint32_t* to_transfer) +{ + if (transferred != NULL) { + *transferred = asio->transferred; + } + if (to_transfer != NULL) { + *to_transfer = asio->to_transfer; + } + return asio->buffer; +} + +void* +async_socket_io_get_buffer(const AsyncSocketIO* asio) +{ + return asio->buffer; +} + +uint32_t +async_socket_io_get_transferred(const AsyncSocketIO* asio) +{ + return asio->transferred; +} + +uint32_t +async_socket_io_get_to_transfer(const AsyncSocketIO* asio) +{ + return asio->to_transfer; +} + +int +async_socket_io_is_read(const AsyncSocketIO* asio) +{ + return asio->is_io_read; +} + +/******************************************************************************** + * Asynchronous Socket internals + *******************************************************************************/ + +struct AsyncSocket { + /* TCP address for the socket. */ + SockAddress address; + /* Connection callback for this socket. */ + on_as_connection_cb on_connection; + /* An opaque pointer associated with this socket by the client. */ + void* client_opaque; + /* I/O looper for asynchronous I/O on the socket. */ + Looper* looper; + /* I/O descriptor for asynchronous I/O on the socket. */ + LoopIo io[1]; + /* Timer to use for reconnection attempts. */ + LoopTimer reconnect_timer[1]; + /* Head of the list of the active readers. */ + AsyncSocketIO* readers_head; + /* Tail of the list of the active readers. */ + AsyncSocketIO* readers_tail; + /* Head of the list of the active writers. */ + AsyncSocketIO* writers_head; + /* Tail of the list of the active writers. */ + AsyncSocketIO* writers_tail; + /* Socket's file descriptor. */ + int fd; + /* Timeout to use for reconnection attempts. */ + int reconnect_to; + /* Number of outstanding references to the socket. */ + int ref_count; + /* Flags whether (1) or not (0) socket owns the looper. */ + int owns_looper; +}; + +static const char* +_async_socket_string(AsyncSocket* as) +{ + return sock_address_to_string(&as->address); +} + +static Looper* +_async_socket_get_looper(AsyncSocket* as) +{ + return as->looper; +} + +/* Pulls first reader out of the list. + * Param: + * as - Initialized AsyncSocket instance. + * Return: + * First I/O pulled out of the list, or NULL if there are no I/O in the list. + * Note that the caller is responsible for releasing the I/O object returned + * from this routine. + */ +static AsyncSocketIO* +_async_socket_pull_first_io(AsyncSocket* as, + AsyncSocketIO** list_head, + AsyncSocketIO** list_tail) +{ + AsyncSocketIO* const ret = *list_head; + if (ret != NULL) { + *list_head = ret->next; + ret->next = NULL; + if (*list_head == NULL) { + *list_tail = NULL; + } + } + return ret; +} + +/* Pulls first reader out of the list. + * Param: + * as - Initialized AsyncSocket instance. + * Return: + * First reader pulled out of the list, or NULL if there are no readers in the + * list. + * Note that the caller is responsible for releasing the I/O object returned + * from this routine. + */ +static AsyncSocketIO* +_async_socket_pull_first_reader(AsyncSocket* as) +{ + return _async_socket_pull_first_io(as, &as->readers_head, &as->readers_tail); +} + +/* Pulls first writer out of the list. + * Param: + * as - Initialized AsyncSocket instance. + * Return: + * First writer pulled out of the list, or NULL if there are no writers in the + * list. + * Note that the caller is responsible for releasing the I/O object returned + * from this routine. + */ +static AsyncSocketIO* +_async_socket_pull_first_writer(AsyncSocket* as) +{ + return _async_socket_pull_first_io(as, &as->writers_head, &as->writers_tail); +} + +/* Removes an I/O descriptor from a list of active I/O. + * Param: + * as - Initialized AsyncSocket instance. + * list_head, list_tail - Pointers to the list head and tail. + * io - I/O to remove. + * Return: + * Boolean: 1 if I/O has been removed, or 0 if I/O has not been found in the list. + */ +static int +_async_socket_remove_io(AsyncSocket* as, + AsyncSocketIO** list_head, + AsyncSocketIO** list_tail, + AsyncSocketIO* io) +{ + AsyncSocketIO* prev = NULL; + + while (*list_head != NULL && io != *list_head) { + prev = *list_head; + list_head = &((*list_head)->next); + } + if (*list_head == NULL) { + D("%s: I/O %p is not found in the list for socket '%s'", + __FUNCTION__, io, _async_socket_string(as)); + return 0; + } + + *list_head = io->next; + if (prev != NULL) { + prev->next = io->next; + } + if (*list_tail == io) { + *list_tail = prev; + } + + /* Release I/O adjusting reference added when I/O has been saved in the list. */ + async_socket_io_release(io); + + return 1; +} + +/* Advances to the next I/O in the list. + * Param: + * as - Initialized AsyncSocket instance. + * list_head, list_tail - Pointers to the list head and tail. + */ +static void +_async_socket_advance_io(AsyncSocket* as, + AsyncSocketIO** list_head, + AsyncSocketIO** list_tail) +{ + AsyncSocketIO* first_io = *list_head; + if (first_io != NULL) { + *list_head = first_io->next; + first_io->next = NULL; + } + if (*list_head == NULL) { + *list_tail = NULL; + } + if (first_io != NULL) { + /* Release I/O removed from the head of the list. */ + async_socket_io_release(first_io); + } +} + +/* Advances to the next reader in the list. + * Param: + * as - Initialized AsyncSocket instance. + */ +static void +_async_socket_advance_reader(AsyncSocket* as) +{ + _async_socket_advance_io(as, &as->readers_head, &as->readers_tail); +} + +/* Advances to the next writer in the list. + * Param: + * as - Initialized AsyncSocket instance. + */ +static void +_async_socket_advance_writer(AsyncSocket* as) +{ + _async_socket_advance_io(as, &as->writers_head, &as->writers_tail); +} + +/* Completes an I/O. + * Param: + * as - Initialized AsyncSocket instance. + * asio - I/O to complete. + * Return: + * One of AsyncIOAction values. + */ +static AsyncIOAction +_async_socket_complete_io(AsyncSocket* as, AsyncSocketIO* asio) +{ + T("ASocket %s: %s I/O %p is completed.", + _async_socket_string(as), asio->is_io_read ? "READ" : "WRITE", asio); + + /* Stop the timer. */ + async_socket_io_cancel_time_out(asio); + + return asio->on_io(asio->io_opaque, asio, ASIO_STATE_SUCCEEDED); +} + +/* Timeouts an I/O. + * Param: + * as - Initialized AsyncSocket instance. + * asio - An I/O that has timed out. + * Return: + * One of AsyncIOAction values. + */ +static AsyncIOAction +_async_socket_io_timed_out(AsyncSocket* as, AsyncSocketIO* asio) +{ + T("ASocket %s: %s I/O %p with deadline %lld has timed out at %lld", + _async_socket_string(as), asio->is_io_read ? "READ" : "WRITE", asio, + asio->deadline, async_socket_deadline(as, 0)); + + /* Report to the client. */ + const AsyncIOAction action = asio->on_io(asio->io_opaque, asio, + ASIO_STATE_TIMED_OUT); + + /* Remove the I/O from a list of active I/O for actions other than retry. */ + if (action != ASIO_ACTION_RETRY) { + if (asio->is_io_read) { + _async_socket_remove_io(as, &as->readers_head, &as->readers_tail, asio); + } else { + _async_socket_remove_io(as, &as->writers_head, &as->writers_tail, asio); + } + } + + return action; +} + +/* Cancels an I/O. + * Param: + * as - Initialized AsyncSocket instance. + * asio - An I/O to cancel. + * Return: + * One of AsyncIOAction values. + */ +static AsyncIOAction +_async_socket_cancel_io(AsyncSocket* as, AsyncSocketIO* asio) +{ + T("ASocket %s: %s I/O %p is cancelled.", + _async_socket_string(as), asio->is_io_read ? "READ" : "WRITE", asio); + + /* Stop the timer. */ + async_socket_io_cancel_time_out(asio); + + return asio->on_io(asio->io_opaque, asio, ASIO_STATE_CANCELLED); +} + +/* Reports an I/O failure. + * Param: + * as - Initialized AsyncSocket instance. + * asio - An I/O that has failed. Can be NULL for general failures. + * failure - Failure (errno) that has occurred. + * Return: + * One of AsyncIOAction values. + */ +static AsyncIOAction +_async_socket_io_failure(AsyncSocket* as, AsyncSocketIO* asio, int failure) +{ + T("ASocket %s: %s I/O %p has failed: %d -> %s", + _async_socket_string(as), asio->is_io_read ? "READ" : "WRITE", asio, + failure, strerror(failure)); + + /* Stop the timer. */ + async_socket_io_cancel_time_out(asio); + + errno = failure; + return asio->on_io(asio->io_opaque, asio, ASIO_STATE_FAILED); +} + +/* Cancels all the active socket readers. + * Param: + * as - Initialized AsyncSocket instance. + */ +static void +_async_socket_cancel_readers(AsyncSocket* as) +{ + while (as->readers_head != NULL) { + AsyncSocketIO* const to_cancel = _async_socket_pull_first_reader(as); + /* We ignore action returned from the cancellation callback, since we're + * in a disconnected state here. */ + _async_socket_cancel_io(as, to_cancel); + async_socket_io_release(to_cancel); + } +} + +/* Cancels all the active socket writers. + * Param: + * as - Initialized AsyncSocket instance. + */ +static void +_async_socket_cancel_writers(AsyncSocket* as) +{ + while (as->writers_head != NULL) { + AsyncSocketIO* const to_cancel = _async_socket_pull_first_writer(as); + /* We ignore action returned from the cancellation callback, since we're + * in a disconnected state here. */ + _async_socket_cancel_io(as, to_cancel); + async_socket_io_release(to_cancel); + } +} + +/* Cancels all the I/O on the socket. */ +static void +_async_socket_cancel_all_io(AsyncSocket* as) +{ + /* Stop the reconnection timer. */ + loopTimer_stop(as->reconnect_timer); + + /* Stop read / write on the socket. */ + loopIo_dontWantWrite(as->io); + loopIo_dontWantRead(as->io); + + /* Cancel active readers and writers. */ + _async_socket_cancel_readers(as); + _async_socket_cancel_writers(as); +} + +/* Closes socket handle used by the async socket. + * Param: + * as - Initialized AsyncSocket instance. + */ +static void +_async_socket_close_socket(AsyncSocket* as) +{ + if (as->fd >= 0) { + T("ASocket %s: Socket handle %d is closed.", + _async_socket_string(as), as->fd); + loopIo_done(as->io); + socket_close(as->fd); + as->fd = -1; + } +} + +/* Destroys AsyncSocket instance. + * Param: + * as - Initialized AsyncSocket instance. + */ +static void +_async_socket_free(AsyncSocket* as) +{ + if (as != NULL) { + T("ASocket %s: Socket descriptor is destroyed.", _async_socket_string(as)); + + /* Close socket. */ + _async_socket_close_socket(as); + + /* Free allocated resources. */ + if (as->looper != NULL) { + loopTimer_done(as->reconnect_timer); + if (as->owns_looper) { + looper_free(as->looper); + } + } + sock_address_done(&as->address); + AFREE(as); + } +} + +/* Starts reconnection attempts after connection has been lost. + * Param: + * as - Initialized AsyncSocket instance. + * to - Milliseconds to wait before reconnection attempt. + */ +static void +_async_socket_reconnect(AsyncSocket* as, int to) +{ + T("ASocket %s: reconnecting in %dms...", _async_socket_string(as), to); + + /* Make sure that no I/O is active, and socket is closed before we + * reconnect. */ + _async_socket_cancel_all_io(as); + + /* Set the timer for reconnection attempt. */ + loopTimer_startRelative(as->reconnect_timer, to); +} + +/******************************************************************************** + * Asynchronous Socket callbacks + *******************************************************************************/ + +/* A callback that is invoked when socket gets disconnected. + * Param: + * as - Initialized AsyncSocket instance. + */ +static void +_on_async_socket_disconnected(AsyncSocket* as) +{ + /* Save error to restore it for the client's callback. */ + const int save_errno = errno; + AsyncIOAction action = ASIO_ACTION_ABORT; + + D("ASocket %s: Disconnected.", _async_socket_string(as)); + + /* Cancel all the I/O on this socket. */ + _async_socket_cancel_all_io(as); + + /* Close the socket. */ + _async_socket_close_socket(as); + + /* Restore errno, and invoke client's callback. */ + errno = save_errno; + action = as->on_connection(as->client_opaque, as, ASIO_STATE_FAILED); + + if (action == ASIO_ACTION_RETRY) { + /* Client requested reconnection. */ + _async_socket_reconnect(as, as->reconnect_to); + } +} + +/* A callback that is invoked on socket's I/O failure. + * Param: + * as - Initialized AsyncSocket instance. + * asio - Descriptor for the failed I/O. Can be NULL for general failures. + */ +static AsyncIOAction +_on_async_socket_failure(AsyncSocket* as, AsyncSocketIO* asio) +{ + D("ASocket %s: %s I/O failure: %d -> %s", + _async_socket_string(as), asio->is_io_read ? "READ" : "WRITE", + errno, strerror(errno)); + + /* Report the failure. */ + return _async_socket_io_failure(as, asio, errno); +} + +/* A callback that is invoked when there is data available to read. + * Param: + * as - Initialized AsyncSocket instance. + * Return: + * 0 on success, or -1 on failure. Failure returned from this routine will + * skip writes (if awailable) behind this read. + */ +static int +_on_async_socket_recv(AsyncSocket* as) +{ + AsyncIOAction action; + + /* Get current reader. */ + AsyncSocketIO* const asr = as->readers_head; + if (asr == NULL) { + D("ASocket %s: No reader is available.", _async_socket_string(as)); + loopIo_dontWantRead(as->io); + return 0; + } + + /* Reference the reader while we're working with it in this callback. */ + async_socket_io_reference(asr); + + /* Bump I/O state, and inform the client that I/O is in progress. */ + if (asr->state == ASIO_STATE_QUEUED) { + asr->state = ASIO_STATE_STARTED; + } else { + asr->state = ASIO_STATE_CONTINUES; + } + action = asr->on_io(asr->io_opaque, asr, asr->state); + if (action == ASIO_ACTION_ABORT) { + D("ASocket %s: Read is aborted by the client.", _async_socket_string(as)); + /* Move on to the next reader. */ + _async_socket_advance_reader(as); + /* Lets see if there are still active readers, and enable, or disable + * read I/O callback accordingly. */ + if (as->readers_head != NULL) { + loopIo_wantRead(as->io); + } else { + loopIo_dontWantRead(as->io); + } + async_socket_io_release(asr); + return 0; + } + + /* Read next chunk of data. */ + int res = socket_recv(as->fd, asr->buffer + asr->transferred, + asr->to_transfer - asr->transferred); + while (res < 0 && errno == EINTR) { + res = socket_recv(as->fd, asr->buffer + asr->transferred, + asr->to_transfer - asr->transferred); + } + + if (res == 0) { + /* Socket has been disconnected. */ + errno = ECONNRESET; + _on_async_socket_disconnected(as); + async_socket_io_release(asr); + return -1; + } + + if (res < 0) { + if (errno == EWOULDBLOCK || errno == EAGAIN) { + /* Yield to writes behind this read. */ + loopIo_wantRead(as->io); + async_socket_io_release(asr); + return 0; + } + + /* An I/O error. */ + action = _on_async_socket_failure(as, asr); + if (action != ASIO_ACTION_RETRY) { + D("ASocket %s: Read is aborted on failure.", _async_socket_string(as)); + /* Move on to the next reader. */ + _async_socket_advance_reader(as); + /* Lets see if there are still active readers, and enable, or disable + * read I/O callback accordingly. */ + if (as->readers_head != NULL) { + loopIo_wantRead(as->io); + } else { + loopIo_dontWantRead(as->io); + } + } + async_socket_io_release(asr); + return -1; + } + + /* Update the reader's descriptor. */ + asr->transferred += res; + if (asr->transferred == asr->to_transfer) { + /* This read is completed. Move on to the next reader. */ + _async_socket_advance_reader(as); + + /* Notify reader completion. */ + _async_socket_complete_io(as, asr); + } + + /* Lets see if there are still active readers, and enable, or disable read + * I/O callback accordingly. */ + if (as->readers_head != NULL) { + loopIo_wantRead(as->io); + } else { + loopIo_dontWantRead(as->io); + } + + async_socket_io_release(asr); + + return 0; +} + +/* A callback that is invoked when there is data available to write. + * Param: + * as - Initialized AsyncSocket instance. + * Return: + * 0 on success, or -1 on failure. Failure returned from this routine will + * skip reads (if awailable) behind this write. + */ +static int +_on_async_socket_send(AsyncSocket* as) +{ + AsyncIOAction action; + + /* Get current writer. */ + AsyncSocketIO* const asw = as->writers_head; + if (asw == NULL) { + D("ASocket %s: No writer is available.", _async_socket_string(as)); + loopIo_dontWantWrite(as->io); + return 0; + } + + /* Reference the writer while we're working with it in this callback. */ + async_socket_io_reference(asw); + + /* Bump I/O state, and inform the client that I/O is in progress. */ + if (asw->state == ASIO_STATE_QUEUED) { + asw->state = ASIO_STATE_STARTED; + } else { + asw->state = ASIO_STATE_CONTINUES; + } + action = asw->on_io(asw->io_opaque, asw, asw->state); + if (action == ASIO_ACTION_ABORT) { + D("ASocket %s: Write is aborted by the client.", _async_socket_string(as)); + /* Move on to the next writer. */ + _async_socket_advance_writer(as); + /* Lets see if there are still active writers, and enable, or disable + * write I/O callback accordingly. */ + if (as->writers_head != NULL) { + loopIo_wantWrite(as->io); + } else { + loopIo_dontWantWrite(as->io); + } + async_socket_io_release(asw); + return 0; + } + + /* Write next chunk of data. */ + int res = socket_send(as->fd, asw->buffer + asw->transferred, + asw->to_transfer - asw->transferred); + while (res < 0 && errno == EINTR) { + res = socket_send(as->fd, asw->buffer + asw->transferred, + asw->to_transfer - asw->transferred); + } + + if (res == 0) { + /* Socket has been disconnected. */ + errno = ECONNRESET; + _on_async_socket_disconnected(as); + async_socket_io_release(asw); + return -1; + } + + if (res < 0) { + if (errno == EWOULDBLOCK || errno == EAGAIN) { + /* Yield to reads behind this write. */ + loopIo_wantWrite(as->io); + async_socket_io_release(asw); + return 0; + } + + /* An I/O error. */ + action = _on_async_socket_failure(as, asw); + if (action != ASIO_ACTION_RETRY) { + D("ASocket %s: Write is aborted on failure.", _async_socket_string(as)); + /* Move on to the next writer. */ + _async_socket_advance_writer(as); + /* Lets see if there are still active writers, and enable, or disable + * write I/O callback accordingly. */ + if (as->writers_head != NULL) { + loopIo_wantWrite(as->io); + } else { + loopIo_dontWantWrite(as->io); + } + } + async_socket_io_release(asw); + return -1; + } + + /* Update the writer descriptor. */ + asw->transferred += res; + if (asw->transferred == asw->to_transfer) { + /* This write is completed. Move on to the next writer. */ + _async_socket_advance_writer(as); + + /* Notify writer completion. */ + _async_socket_complete_io(as, asw); + } + + /* Lets see if there are still active writers, and enable, or disable write + * I/O callback accordingly. */ + if (as->writers_head != NULL) { + loopIo_wantWrite(as->io); + } else { + loopIo_dontWantWrite(as->io); + } + + async_socket_io_release(asw); + + return 0; +} + +/* A callback that is invoked when an I/O is available on socket. + * Param: + * as - Initialized AsyncSocket instance. + * fd - Socket's file descriptor. + * events - LOOP_IO_READ | LOOP_IO_WRITE bitmask. + */ +static void +_on_async_socket_io(void* opaque, int fd, unsigned events) +{ + AsyncSocket* const as = (AsyncSocket*)opaque; + + /* Reference the socket while we're working with it in this callback. */ + async_socket_reference(as); + + if ((events & LOOP_IO_READ) != 0) { + if (_on_async_socket_recv(as) != 0) { + async_socket_release(as); + return; + } + } + + if ((events & LOOP_IO_WRITE) != 0) { + if (_on_async_socket_send(as) != 0) { + async_socket_release(as); + return; + } + } + + async_socket_release(as); +} + +/* A callback that is invoked by asynchronous socket connector on connection + * events. + * Param: + * opaque - Initialized AsyncSocket instance. + * connector - Connector that is used to connect this socket. + * event - Connection event. + * Return: + * One of AsyncIOAction values. + */ +static AsyncIOAction +_on_connector_events(void* opaque, + AsyncSocketConnector* connector, + AsyncIOState event) +{ + AsyncIOAction action; + AsyncSocket* const as = (AsyncSocket*)opaque; + + /* Reference the socket while we're working with it in this callback. */ + async_socket_reference(as); + + if (event == ASIO_STATE_SUCCEEDED) { + /* Accept the connection. */ + as->fd = async_socket_connector_pull_fd(connector); + loopIo_init(as->io, as->looper, as->fd, _on_async_socket_io, as); + } + + /* Invoke client's callback. */ + action = as->on_connection(as->client_opaque, as, event); + if (event == ASIO_STATE_SUCCEEDED && action != ASIO_ACTION_DONE) { + /* For whatever reason the client didn't want to keep this connection. + * Close it. */ + D("ASocket %s: Connection is discarded by the client.", + _async_socket_string(as)); + _async_socket_close_socket(as); + } + + if (action != ASIO_ACTION_RETRY) { + async_socket_connector_release(connector); + } + + async_socket_release(as); + + return action; +} + +/* Timer callback invoked to reconnect the lost connection. + * Param: + * as - Initialized AsyncSocket instance. + */ +void +_on_async_socket_reconnect(void* opaque) +{ + AsyncSocket* as = (AsyncSocket*)opaque; + + /* Reference the socket while we're working with it in this callback. */ + async_socket_reference(as); + async_socket_connect(as, as->reconnect_to); + async_socket_release(as); +} + + +/******************************************************************************** + * Android Device Socket public API + *******************************************************************************/ + +AsyncSocket* +async_socket_new(int port, + int reconnect_to, + on_as_connection_cb client_cb, + void* client_opaque, + Looper* looper) +{ + AsyncSocket* as; + + if (client_cb == NULL) { + E("Invalid client_cb parameter"); + return NULL; + } + + ANEW0(as); + + as->fd = -1; + as->client_opaque = client_opaque; + as->on_connection = client_cb; + as->readers_head = as->readers_tail = NULL; + as->reconnect_to = reconnect_to; + as->ref_count = 1; + sock_address_init_inet(&as->address, SOCK_ADDRESS_INET_LOOPBACK, port); + if (looper == NULL) { + as->looper = looper_newCore(); + if (as->looper == NULL) { + E("Unable to create I/O looper for async socket '%s'", + _async_socket_string(as)); + client_cb(client_opaque, as, ASIO_STATE_FAILED); + _async_socket_free(as); + return NULL; + } + as->owns_looper = 1; + } else { + as->looper = looper; + as->owns_looper = 0; + } + + loopTimer_init(as->reconnect_timer, as->looper, _on_async_socket_reconnect, as); + + T("ASocket %s: Descriptor is created.", _async_socket_string(as)); + + return as; +} + +int +async_socket_reference(AsyncSocket* as) +{ + assert(as->ref_count > 0); + as->ref_count++; + return as->ref_count; +} + +int +async_socket_release(AsyncSocket* as) +{ + assert(as->ref_count > 0); + as->ref_count--; + if (as->ref_count == 0) { + /* Last reference has been dropped. Destroy this object. */ + _async_socket_cancel_all_io(as); + _async_socket_free(as); + return 0; + } + return as->ref_count; +} + +void +async_socket_connect(AsyncSocket* as, int retry_to) +{ + T("ASocket %s: Handling connection request for %dms...", + _async_socket_string(as), retry_to); + + AsyncSocketConnector* const connector = + async_socket_connector_new(&as->address, retry_to, _on_connector_events, + as, as->looper); + if (connector != NULL) { + async_socket_connector_connect(connector); + } else { + as->on_connection(as->client_opaque, as, ASIO_STATE_FAILED); + } +} + +void +async_socket_disconnect(AsyncSocket* as) +{ + T("ASocket %s: Handling disconnection request...", _async_socket_string(as)); + + if (as != NULL) { + _async_socket_cancel_all_io(as); + _async_socket_close_socket(as); + } +} + +void +async_socket_reconnect(AsyncSocket* as, int retry_to) +{ + T("ASocket %s: Handling reconnection request for %dms...", + _async_socket_string(as), retry_to); + + _async_socket_cancel_all_io(as); + _async_socket_close_socket(as); + _async_socket_reconnect(as, retry_to); +} + +void +async_socket_read_abs(AsyncSocket* as, + void* buffer, uint32_t len, + on_as_io_cb reader_cb, + void* reader_opaque, + Duration deadline) +{ + T("ASocket %s: Handling read for %d bytes with deadline %lld...", + _async_socket_string(as), len, deadline); + + AsyncSocketIO* const asr = + _async_socket_reader_new(as, buffer, len, reader_cb, reader_opaque, + deadline); + if (async_socket_is_connected(as)) { + /* Add new reader to the list. Note that we use initial reference from I/O + * 'new' routine as "in the list" reference counter. */ + if (as->readers_head == NULL) { + as->readers_head = as->readers_tail = asr; + } else { + as->readers_tail->next = asr; + as->readers_tail = asr; + } + loopIo_wantRead(as->io); + } else { + D("ASocket %s: Read on a disconnected socket.", _async_socket_string(as)); + errno = ECONNRESET; + reader_cb(reader_opaque, asr, ASIO_STATE_FAILED); + async_socket_io_release(asr); + } +} + +void +async_socket_read_rel(AsyncSocket* as, + void* buffer, uint32_t len, + on_as_io_cb reader_cb, + void* reader_opaque, + int to) +{ + const Duration dl = (to >= 0) ? looper_now(_async_socket_get_looper(as)) + to : + DURATION_INFINITE; + async_socket_read_abs(as, buffer, len, reader_cb, reader_opaque, dl); +} + +void +async_socket_write_abs(AsyncSocket* as, + const void* buffer, uint32_t len, + on_as_io_cb writer_cb, + void* writer_opaque, + Duration deadline) +{ + T("ASocket %s: Handling write for %d bytes with deadline %lld...", + _async_socket_string(as), len, deadline); + + AsyncSocketIO* const asw = + _async_socket_writer_new(as, buffer, len, writer_cb, writer_opaque, + deadline); + if (async_socket_is_connected(as)) { + /* Add new writer to the list. Note that we use initial reference from I/O + * 'new' routine as "in the list" reference counter. */ + if (as->writers_head == NULL) { + as->writers_head = as->writers_tail = asw; + } else { + as->writers_tail->next = asw; + as->writers_tail = asw; + } + loopIo_wantWrite(as->io); + } else { + D("ASocket %s: Write on a disconnected socket.", _async_socket_string(as)); + errno = ECONNRESET; + writer_cb(writer_opaque, asw, ASIO_STATE_FAILED); + async_socket_io_release(asw); + } +} + +void +async_socket_write_rel(AsyncSocket* as, + const void* buffer, uint32_t len, + on_as_io_cb writer_cb, + void* writer_opaque, + int to) +{ + const Duration dl = (to >= 0) ? looper_now(_async_socket_get_looper(as)) + to : + DURATION_INFINITE; + async_socket_write_abs(as, buffer, len, writer_cb, writer_opaque, dl); +} + +void* +async_socket_get_client_opaque(const AsyncSocket* as) +{ + return as->client_opaque; +} + +Duration +async_socket_deadline(AsyncSocket* as, int rel) +{ + return (rel >= 0) ? looper_now(_async_socket_get_looper(as)) + rel : + DURATION_INFINITE; +} + +int +async_socket_get_port(const AsyncSocket* as) +{ + return sock_address_get_port(&as->address); +} + +int +async_socket_is_connected(const AsyncSocket* as) +{ + return as->fd >= 0; +} diff --git a/android/async-socket.h b/android/async-socket.h new file mode 100644 index 0000000..bdfd272 --- /dev/null +++ b/android/async-socket.h @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ANDROID_ASYNC_SOCKET_H_ +#define ANDROID_ASYNC_SOCKET_H_ + +#include "qemu-common.h" +#include "android/async-io-common.h" +#include "android/async-utils.h" + +/* + * Contains declaration of an API that encapsulates communication via an + * asynchronous socket. + * + * This is pretty basic API that allows asynchronous connection to a socket, + * and asynchronous read from / write to the connected socket. + * + * Since all the operations (including connection) are asynchronous, all the + * operation results are reported back to the client of this API via set of + * callbacks that client supplied to this API. + * + * Since it's hard to control lifespan of an object in asynchronous environment, + * we make AsyncSocketConnector a referenced object, that will self-destruct when + * its reference count drops to zero, indicating that the last client has + * abandoned that object. + */ + +/* Declares asynchronous socket descriptor. */ +typedef struct AsyncSocket AsyncSocket; + +/* Asynchronous socket I/O (reader, or writer) descriptor. */ +typedef struct AsyncSocketIO AsyncSocketIO; + +/* Defines client's callback set to monitor socket connection. + * Param: + * client_opaque - An opaque pointer associated with the client. + * as - Initialized AsyncSocket instance. + * status - Socket connection status. + * Return: + * One of the AsyncIOAction values. + */ +typedef AsyncIOAction (*on_as_connection_cb)(void* client_opaque, + AsyncSocket* as, + AsyncIOState status); + +/* Defines client's callback set to monitor I/O progress. + * Param: + * io_opaque - An opaque pointer associated with the I/O. + * asio - Async I/O in progress. + * status - Status of the I/O. + * Return: + * One of the AsyncIOAction values. + */ +typedef AsyncIOAction (*on_as_io_cb)(void* io_opaque, + AsyncSocketIO* asio, + AsyncIOState status); + +/******************************************************************************** + * AsyncSocketIO API + *******************************************************************************/ + +/* References AsyncSocketIO object. + * Param: + * asio - Initialized AsyncSocketIO instance. + * Return: + * Number of outstanding references to the object. + */ +extern int async_socket_io_reference(AsyncSocketIO* asio); + +/* Releases AsyncSocketIO object. + * Note that upon exit from this routine the object might be destroyed, even if + * the routine returns value other than zero. + * Param: + * asio - Initialized AsyncSocketIO instance. + * Return: + * Number of outstanding references to the object. + */ +extern int async_socket_io_release(AsyncSocketIO* asio); + +/* Gets AsyncSocket instance for an I/O. Note that this routine will reference + * AsyncSocket instance before returning it to the caller. */ +extern AsyncSocket* async_socket_io_get_socket(const AsyncSocketIO* asio); + +/* Cancels time out set for an I/O */ +extern void async_socket_io_cancel_time_out(AsyncSocketIO* asio); + +/* Gets an opaque pointer associated with an I/O */ +extern void* async_socket_io_get_io_opaque(const AsyncSocketIO* asio); + +/* Gets an opaque pointer associated with the client that has requested I/O */ +extern void* async_socket_io_get_client_opaque(const AsyncSocketIO* asio); + +/* Gets I/O buffer information. + * Param: + * asio - I/O descriptor. + * transferred - Optional pointer to receive number of bytes transferred with + * this I/O. Can be NULL. + * to_transfer - Optional pointer to receive number of bytes requested to + * transfer with this I/O. Can be NULL. + * Return: + * I/O buffer. + */ +extern void* async_socket_io_get_buffer_info(const AsyncSocketIO* asio, + uint32_t* transferred, + uint32_t* to_transfer); + +/* Gets I/O buffer. */ +extern void* async_socket_io_get_buffer(const AsyncSocketIO* asio); + +/* Gets number of bytes transferred with this I/O. */ +extern uint32_t async_socket_io_get_transferred(const AsyncSocketIO* asio); + +/* Gets number of bytes requested to transfer with this I/O. */ +extern uint32_t async_socket_io_get_to_transfer(const AsyncSocketIO* asio); + +/* Gets I/O type: read (returns 1), or write (returns 0). */ +extern int async_socket_io_is_read(const AsyncSocketIO* asio); + +/******************************************************************************** + * AsyncSocket API + *******************************************************************************/ + +/* Creates an asynchronous socket descriptor. + * Param: + * port - TCP port to connect the socket to. + * reconnect_to - Timeout before trying to reconnect after disconnection. + * connect_cb - Client callback to monitor connection state (must not be NULL). + * client_opaque - An opaque pointer to associate with the socket client. + * looper - An optional (can be NULL) I/O looper to use for socket I/O. If + * this parameter is NULL, the socket will create its own looper. + * Return: + * Initialized AsyncSocket instance on success, or NULL on failure. + */ +extern AsyncSocket* async_socket_new(int port, + int reconnect_to, + on_as_connection_cb connect_cb, + void* client_opaque, + Looper* looper); + +/* References AsyncSocket object. + * Param: + * as - Initialized AsyncSocket instance. + * Return: + * Number of outstanding references to the object. + */ +extern int async_socket_reference(AsyncSocket* as); + +/* Releases AsyncSocket object. + * Note that upon exit from this routine the object might be destroyed, even if + * the routine returns value other than zero. + * Param: + * as - Initialized AsyncSocket instance. + * Return: + * Number of outstanding references to the object. + */ +extern int async_socket_release(AsyncSocket* as); + +/* Asynchronously connects to an asynchronous socket. + * Note that connection result will be reported via callback passed to the + * async_socket_new routine. + * Param: + * as - Initialized AsyncSocket instance. + * retry_to - Number of milliseconds to wait before retrying a failed + * connection attempt. + */ +extern void async_socket_connect(AsyncSocket* as, int retry_to); + +/* Disconnects from an asynchronous socket. + * NOTE: AsyncSocket instance referenced in this call will be destroyed in this + * routine. + * Param: + * as - Initialized and connected AsyncSocket instance. + */ +extern void async_socket_disconnect(AsyncSocket* as); + +/* Asynchronously reconnects to an asynchronous socket. + * Note that connection result will be reported via callback passed to the + * async_socket_new routine. + * Param: + * as - Initialized AsyncSocket instance. + * retry_to - Number of milliseconds to wait before trying to reconnect. + */ +extern void async_socket_reconnect(AsyncSocket* as, int retry_to); + +/* Asynchronously reads data from an asynchronous socket with a deadline. + * Param: + * as - Initialized and connected AsyncSocket instance. + * buffer, len - Buffer where to read data. + * reader_cb - Callback to monitor I/O progress (must not be NULL). + * reader_opaque - An opaque pointer associated with the reader. + * deadline - Deadline to complete the read. + */ +extern void async_socket_read_abs(AsyncSocket* as, + void* buffer, uint32_t len, + on_as_io_cb reader_cb, + void* reader_opaque, + Duration deadline); + +/* Asynchronously reads data from an asynchronous socket with a relative timeout. + * Param: + * as - Initialized and connected AsyncSocket instance. + * buffer, len - Buffer where to read data. + * reader_cb - Callback to monitor I/O progress (must not be NULL). + * reader_opaque - An opaque pointer associated with the reader. + * to - Milliseconds to complete the read. to < 0 indicates "no timeout" + */ +extern void async_socket_read_rel(AsyncSocket* as, + void* buffer, uint32_t len, + on_as_io_cb reader_cb, + void* reader_opaque, + int to); + +/* Asynchronously writes data to an asynchronous socket with a deadline. + * Param: + * as - Initialized and connected AsyncSocket instance. + * buffer, len - Buffer with writing data. + * writer_cb - Callback to monitor I/O progress (must not be NULL). + * writer_opaque - An opaque pointer associated with the writer. + * deadline - Deadline to complete the write. + */ +extern void async_socket_write_abs(AsyncSocket* as, + const void* buffer, uint32_t len, + on_as_io_cb writer_cb, + void* writer_opaque, + Duration deadline); + +/* Asynchronously writes data to an asynchronous socket with a relative timeout. + * Param: + * as - Initialized and connected AsyncSocket instance. + * buffer, len - Buffer with writing data. + * writer_cb - Callback to monitor I/O progress (must not be NULL) + * writer_opaque - An opaque pointer associated with the writer. + * to - Milliseconds to complete the write. to < 0 indicates "no timeout" + */ +extern void async_socket_write_rel(AsyncSocket* as, + const void* buffer, uint32_t len, + on_as_io_cb writer_cb, + void* writer_opaque, + int to); + +/* Get a deadline for the given time interval relative to "now". + * Param: + * as - Initialized AsyncSocket instance. + * rel - Time interval. If < 0 an infinite duration will be returned. + * Return: + * A deadline for the given time interval relative to "now". + */ +extern Duration async_socket_deadline(AsyncSocket* as, int rel); + +/* Gets an opaque pointer associated with the socket's client */ +extern void* async_socket_get_client_opaque(const AsyncSocket* as); + +/* Gets TCP port for the socket. */ +extern int async_socket_get_port(const AsyncSocket* as); + +/* Checks if socket is connected. + * Return: + * Boolean: 1 - socket is connected, 0 - socket is not connected. + */ +extern int async_socket_is_connected(const AsyncSocket* as); + +#endif /* ANDROID_ASYNC_SOCKET_H_ */ diff --git a/android/async-utils.c b/android/async-utils.c index e410de0..9732111 100644 --- a/android/async-utils.c +++ b/android/async-utils.c @@ -268,3 +268,14 @@ asyncConnector_run(AsyncConnector* ac) return ASYNC_COMPLETE; } } + +int +asyncConnector_stop(AsyncConnector* ac) +{ + if (ac->state == CONNECT_CONNECTING) { + loopIo_dontWantWrite(ac->io); + ac->state = CONNECT_COMPLETED; + return 0; + } + return -1; +} diff --git a/android/async-utils.h b/android/async-utils.h index 6d460c2..30dfbe3 100644 --- a/android/async-utils.h +++ b/android/async-utils.h @@ -225,4 +225,12 @@ asyncConnector_init(AsyncConnector* ac, AsyncStatus asyncConnector_run(AsyncConnector* ac); +/* Stops connection in progress. + * Return: + * 0 if connection in progress has been stopped, or -1 if no connection has been + * in progress. + */ +int +asyncConnector_stop(AsyncConnector* ac); + #endif /* ANDROID_ASYNC_UTILS_H */ diff --git a/android/avd/hardware-properties.ini b/android/avd/hardware-properties.ini index ebf2450..582083c 100644 --- a/android/avd/hardware-properties.ini +++ b/android/avd/hardware-properties.ini @@ -46,12 +46,13 @@ default = 0 abstract = Device ram size description = The amount of physical RAM on the device, in megabytes. -# Touch screen support -name = hw.touchScreen -type = boolean -default = yes -abstract = Touch-screen support -description = Whether there is a touch screen or not on the device. +# Touch screen type +name = hw.screen +type = string +enum = touch, multi-touch, no-touch +default = touch +abstract = Touch screen type +description = Defines type of the screen. # Hardware main keys (back/home) name = hw.mainKeys @@ -70,7 +71,7 @@ description = Whether there is a trackball on the device. # Keyboard support (qwerty/azerty) name = hw.keyboard type = boolean -default = yes +default = no abstract = Keyboard support description = Whether the device has a QWERTY keyboard. @@ -114,23 +115,6 @@ default = yes abstract = GSM modem support description = Whether there is a GSM modem in the device. -# Camera support -name = hw.camera -type = boolean -default = yes -abstract = Camera support -description = Whether the device has a camera. - -name = hw.camera.maxHorizontalPixels -type = integer -default = 640 -abstract = Maximum horizontal camera pixels - -name = hw.camera.maxVerticalPixels -type = integer -default = 480 -abstract = Maximum vertical camera pixels - # GPS support name = hw.gps type = boolean @@ -209,16 +193,18 @@ abstract = LCD pixel height name = hw.lcd.depth type = integer +enum = 16, 32 default = 16 abstract = LCD color depth -description = Must be 16 or 32. Color bit depth of emulated framebuffer. +description = Color bit depth of emulated framebuffer. # LCD density name = hw.lcd.density type = integer +enum = 120, 160, 240, 213, 320 default = 160 abstract = Abstracted LCD density -description = Must be one of 120 / 160 / 240 / 213/ 320. A value used to roughly describe the density of the LCD screen for automatic resource/asset selection. +description = A value used to roughly describe the density of the LCD screen for automatic resource/asset selection. # LCD backlight - Enable/Disable LCD backlight simulation # default = no : Disabled @@ -237,119 +223,23 @@ default = no abstract = GPU emulation description = Enable/Disable emulated OpenGLES GPU -# Fake camera support -# -name = hw.fakeCamera -type = string -default = back -abstract = Fake camera control -description = Must be 'back', if fake camera is facing back, 'front', if fake camera is facing front, or 'off' if fake camera is disabled. - -# Number of emulated web cameras -# -name = hw.webcam.count -type = integer -default = 6 -abstract = Number of emulated web cameras -description = Defines number of web cameras to emulate. 0 disables webcam emulation. - -# Defines name of the emulated webcam with index 0 -# -name = hw.webcam.0.name -type = string -default = webcam0 -abstract = Name of the 1-st emulated web camera -description = Emulator-generated platform-independent name identifying a camera in the list of enumerated web cameras. - -# Defines name of the emulated webcam with index 1 -# -name = hw.webcam.1.name -type = string -default = webcam1 -abstract = Name of the 2-nd emulated web camera -description = Emulator-generated platform-independent camera name. - -# Defines name of the emulated webcam with index 2 -# -name = hw.webcam.2.name -type = string -default = webcam2 -abstract = Name of the 3-rd emulated web camera -description = Emulator-generated platform-independent camera name. - -# Defines name of the emulated webcam with index 3 -# -name = hw.webcam.3.name -type = string -default = webcam3 -abstract = Name of the 4-th emulated web camera -description = Emulator-generated platform-independent camera name. - -# Defines name of the emulated webcam with index 4 -# -name = hw.webcam.4.name -type = string -default = webcam4 -abstract = Name of the 5-th emulated web camera -description = Emulator-generated platform-independent camera name. - -# Defines name of the emulated webcam with index 5 -# -name = hw.webcam.5.name -type = string -default = webcam5 -abstract = Name of the 6-th emulated web camera -description = Emulator-generated platform-independent camera name. - -# Defines direction of the emulated webcam with index 0 -# -name = hw.webcam.0.direction -type = string -default = front -abstract = 1-st emulated web camera direction -description = Direction of the 1-st emulated web camera - -# Defines direction of the emulated webcam with index 1 -# Note that first two cameras must face in opposite directions in order to enable -# camera switch in the camera application. -# -name = hw.webcam.1.direction -type = string -default = back -abstract = 2-nd emulated web camera direction -description = Direction of the 2-nd emulated web camera - -# Defines direction of the emulated webcam with index 2 -# -name = hw.webcam.2.direction -type = string -default = front -abstract = 3-rd emulated web camera direction -description = Direction of the 3-rd emulated web camera - -# Defines direction of the emulated webcam with index 3 -# -name = hw.webcam.3.direction -type = string -default = front -abstract = 4-th emulated web camera direction -description = Direction of the 4-th emulated web camera - -# Defines direction of the emulated webcam with index 4 +# Configures camera facing back # -name = hw.webcam.4.direction +name = hw.camera.back type = string -default = front -abstract = 5-th emulated web camera direction -description = Direction of the 5-th emulated web camera +enum = emulated, none, webcam0, ... +default = emulated +abstract = Configures camera facing back +description = Must be 'emulated' for a fake camera, 'webcam<N>' for a web camera, or 'none' if back camera is disabled. -# Defines direction of the emulated webcam with index 5 +# Configures camera facing front # -name = hw.webcam.5.direction +name = hw.camera.front type = string -default = front -abstract = 6-th emulated web camera direction -description = Direction of the 6-th emulated web camera +enum = emulated, none, webcam0, ... +default = none +abstract = Configures camera facing front +description = Must be 'emulated' for a fake camera, 'webcam<N>' for a web camera, or 'none' if front camera is disabled. # Maximum VM heap size # Higher values are required for high-dpi devices diff --git a/android/avd/hw-config.c b/android/avd/hw-config.c index 65796d9..2d50ef7 100644 --- a/android/avd/hw-config.c +++ b/android/avd/hw-config.c @@ -125,3 +125,21 @@ androidHwConfig_done( AndroidHwConfig* config ) #include "android/avd/hw-config-defs.h" } + +int +androidHwConfig_isScreenNoTouch( AndroidHwConfig* config ) +{ + return strcmp(config->hw_screen, "no-touch") == 0; +} + +int +androidHwConfig_isScreenTouch( AndroidHwConfig* config ) +{ + return strcmp(config->hw_screen, "touch") == 0; +} + +int +androidHwConfig_isScreenMultiTouch( AndroidHwConfig* config ) +{ + return strcmp(config->hw_screen, "multi-touch") == 0; +} diff --git a/android/avd/hw-config.h b/android/avd/hw-config.h index 3c2480a..fd99e45 100644 --- a/android/avd/hw-config.h +++ b/android/avd/hw-config.h @@ -57,4 +57,11 @@ int androidHwConfig_write( AndroidHwConfig* hwConfig, /* Finalize a given hardware configuration */ void androidHwConfig_done( AndroidHwConfig* config ); +/* Checks if screen doesn't support touch, or multi-touch */ +int androidHwConfig_isScreenNoTouch( AndroidHwConfig* config ); +/* Checks if screen supports touch (but not multi-touch). */ +int androidHwConfig_isScreenTouch( AndroidHwConfig* config ); +/* Checks if screen supports multi-touch. */ +int androidHwConfig_isScreenMultiTouch( AndroidHwConfig* config ); + #endif /* _ANDROID_AVD_HW_CONFIG_H */ diff --git a/android/avd/info.c b/android/avd/info.c index 7fd8cc4..3463f6a 100644 --- a/android/avd/info.c +++ b/android/avd/info.c @@ -780,12 +780,23 @@ _avdInfo_getBuildSkinHardwareIni( AvdInfo* i ) { char* skinName; char* skinDirPath; - char temp[PATH_MAX], *p=temp, *end=p+sizeof(temp); avdInfo_getSkinInfo(i, &skinName, &skinDirPath); if (skinDirPath == NULL) return 0; + int result = avdInfo_getSkinHardwareIni(i, skinName, skinDirPath); + + AFREE(skinName); + AFREE(skinDirPath); + + return result; +} + +int avdInfo_getSkinHardwareIni( AvdInfo* i, char* skinName, char* skinDirPath) +{ + char temp[PATH_MAX], *p=temp, *end=p+sizeof(temp); + p = bufprint(temp, end, "%s/%s/hardware.ini", skinDirPath, skinName); if (p >= end || !path_exists(temp)) { DD("no skin-specific hardware.ini in %s", skinDirPath); @@ -793,6 +804,8 @@ _avdInfo_getBuildSkinHardwareIni( AvdInfo* i ) } D("found skin-specific hardware.ini: %s", temp); + if (i->skinHardwareIni != NULL) + iniFile_free(i->skinHardwareIni); i->skinHardwareIni = iniFile_newFromFile(temp); if (i->skinHardwareIni == NULL) return -1; @@ -1082,7 +1095,7 @@ avdInfo_getSkinInfo( AvdInfo* i, char** pSkinName, char** pSkinDir ) /* First, see if the config.ini contains a SKIN_PATH entry that * names the full directory path for the skin. */ - if ( i->configIni != NULL ) { + if (i->configIni != NULL ) { skinPath = iniFile_getString( i->configIni, SKIN_PATH, NULL ); if (skinPath != NULL) { /* If this skin name is magic or a direct directory path @@ -1207,3 +1220,12 @@ int avdInfo_getAdbdCommunicationMode( AvdInfo* i ) { return path_getAdbdCommunicationMode(i->androidOut); } + +int avdInfo_getSnapshotPresent(AvdInfo* i) +{ + if (i->configIni == NULL) { + return 0; + } else { + return iniFile_getBoolean(i->configIni, "snapshot.present", "no"); + } +} diff --git a/android/avd/info.h b/android/avd/info.h index 74a9b01..4388b7c 100644 --- a/android/avd/info.h +++ b/android/avd/info.h @@ -106,6 +106,9 @@ typedef struct { */ AvdInfo* avdInfo_new( const char* name, AvdInfoParams* params ); +/* Update the AvdInfo hardware config from a given skin name and path */ +int avdInfo_getSkinHardwareIni( AvdInfo* i, char* skinName, char* skinDirPath); + /* A special function used to setup an AvdInfo for use when starting * the emulator from the Android build system. In this specific instance * we're going to create temporary files to hold all writable image @@ -252,6 +255,15 @@ const char* avdInfo_getCoreHwIniPath( AvdInfo* i ); */ int avdInfo_getAdbdCommunicationMode( AvdInfo* i ); +/* Returns config.ini snapshot presense status. + * This routine checks if snapshots are enabled in AVD config.ini file. + * Return: + * 1 - Snapshots are enabled in AVD config.ini file. + * 0 - Snapshots are disabled in AVD config.ini file, of config.ini file is not + * found. +*/ +int avdInfo_getSnapshotPresent(AvdInfo* i); + /* */ #endif /* ANDROID_AVD_INFO_H */ diff --git a/android/avd/util.c b/android/avd/util.c index 82145b5..a174ee3 100644 --- a/android/avd/util.c +++ b/android/avd/util.c @@ -183,7 +183,7 @@ _getSystemProperty( const char* propFile, const char* propName ) file = fopen(propFile, "rb"); if (file == NULL) { - D("Could not open file: %s: %s", temp, strerror(errno)); + D("Could not open file: %s: %s", propFile, strerror(errno)); return NULL; } diff --git a/android/build/common.sh b/android/build/common.sh index de4e3c1..c7235ae 100644 --- a/android/build/common.sh +++ b/android/build/common.sh @@ -493,21 +493,20 @@ get_android_abs_build_var () # Locate the Android prebuilt directory for your os # you should only call this if IN_ANDROID_BUILD is "yes" # -# This will set ANDROID_PREBUILT_HOST_TAG and ANDROID_PREBUILT +# This will set ANDROID_PREBUILT_HOST_TAG, ANDROID_PREBUILT and ANDROID_PREBUILTS # locate_android_prebuilt () { # locate prebuilt directory ANDROID_PREBUILT_HOST_TAG=$OS ANDROID_PREBUILT=$ANDROID_TOP/prebuilt/$ANDROID_PREBUILT_HOST_TAG + ANDROID_PREBUILTS=$ANDROID_TOP/prebuilts/misc/$ANDROID_PREBUILT_HOST_TAG if [ ! -d $ANDROID_PREBUILT ] ; then # this can happen when building on x86_64 case $OS in linux-x86_64) ANDROID_PREBUILT_HOST_TAG=linux-x86 ANDROID_PREBUILT=$ANDROID_TOP/prebuilt/$ANDROID_PREBUILT_HOST_TAG - log "Forcing usage of 32-bit prebuilts" - force_32bit_binaries ;; *) esac @@ -516,7 +515,22 @@ locate_android_prebuilt () exit 1 fi fi + if [ ! -d $ANDROID_PREBUILTS ] ; then + # this can happen when building on x86_64 + case $OS in + linux-x86_64) + ANDROID_PREBUILT_HOST_TAG=linux-x86 + ANDROID_PREBUILTS=$ANDROID_TOP/prebuilts/misc/$ANDROID_PREBUILT_HOST_TAG + ;; + *) + esac + if [ ! -d $ANDROID_PREBUILTS ] ; then + echo "Can't find the prebuilts directory $ANDROID_PREBUILTS in Android build" + exit 1 + fi + fi log "Prebuilt : ANDROID_PREBUILT=$ANDROID_PREBUILT" + log "Prebuilts : ANDROID_PREBUILTS=$ANDROID_PREBUILTS" } ## Build configuration file support @@ -561,6 +575,7 @@ add_android_config_mk () fi echo "HOST_PREBUILT_TAG := $HOST_TAG" >> $config_mk echo "PREBUILT := $ANDROID_PREBUILT" >> $config_mk + echo "PREBUILTS := $ANDROID_PREBUILTS" >> $config_mk } # Find pattern $1 in string $2 diff --git a/android/camera/camera-capture-windows.c b/android/camera/camera-capture-windows.c index 5479e23..7f9df39 100755 --- a/android/camera/camera-capture-windows.c +++ b/android/camera/camera-capture-windows.c @@ -19,6 +19,7 @@ * This code uses capXxx API, available via capCreateCaptureWindow. */ +#include <windows.h> #include <vfw.h> #include "android/camera/camera-capture.h" #include "android/camera/camera-format-converters.h" @@ -223,6 +224,20 @@ _on_captured_frame(HWND hwnd, LPVIDEOHDR hdr) /* Copy captured frame. */ memcpy(wcd->last_frame, hdr->lpData, hdr->dwBytesUsed); + /* If biCompression is set to default (RGB), set correct pixel format + * for converters. */ + if (wcd->frame_bitmap->bmiHeader.biCompression == BI_RGB) { + if (wcd->frame_bitmap->bmiHeader.biBitCount == 32) { + wcd->pixel_format = V4L2_PIX_FMT_BGR32; + } else if (wcd->frame_bitmap->bmiHeader.biBitCount == 16) { + wcd->pixel_format = V4L2_PIX_FMT_RGB565; + } else { + wcd->pixel_format = V4L2_PIX_FMT_BGR24; + } + } else { + wcd->pixel_format = wcd->frame_bitmap->bmiHeader.biCompression; + } + return (LRESULT)0; } @@ -549,7 +564,7 @@ _camera_device_read_frame_callback(WndCameraDevice* wcd, /* Convert framebuffer. */ return convert_frame(wcd->last_frame, - wcd->frame_bitmap->bmiHeader.biCompression, + wcd->pixel_format, wcd->frame_bitmap->bmiHeader.biSizeImage, wcd->frame_bitmap->bmiHeader.biWidth, wcd->frame_bitmap->bmiHeader.biHeight, diff --git a/android/camera/camera-service.c b/android/camera/camera-service.c index bfdde56..173b6f5 100644 --- a/android/camera/camera-service.c +++ b/android/camera/camera-service.c @@ -233,7 +233,8 @@ _camera_info_get_by_display_name(const char* disp_name, CameraInfo* arr, int num { int n; for (n = 0; n < num; n++) { - if (arr[n].display_name != NULL && !strcmp(arr[n].display_name, disp_name)) { + if (!arr[n].in_use && arr[n].display_name != NULL && + !strcmp(arr[n].display_name, disp_name)) { return &arr[n]; } } @@ -265,6 +266,47 @@ _camera_info_get_by_device_name(const char* device_name, CameraInfo* arr, int nu * CameraServiceDesc API *******************************************************************************/ +/* Initialized webcam emulation record in camera service descriptor. + * Param: + * csd - Camera service descriptor to initialize a record in. + * disp_name - Display name of a web camera ('webcam<N>') to use for emulation. + * dir - Direction ('back', or 'front') that emulated camera is facing. + * ci, ci_cnt - Array of webcam information for enumerated web cameras connected + * to the host. + */ +static void +_wecam_setup(CameraServiceDesc* csd, + const char* disp_name, + const char* dir, + CameraInfo* ci, + int ci_cnt) +{ + /* Find webcam record in the list of enumerated web cameras. */ + CameraInfo* found = _camera_info_get_by_display_name(disp_name, ci, ci_cnt); + if (found == NULL) { + W("Camera name '%s' is not found in the list of connected cameras.\n" + "Use '-webcam-list' emulator option to obtain the list of connected camera names.\n", + disp_name); + return; + } + + /* Save to the camera info array that will be used by the service. */ + memcpy(csd->camera_info + csd->camera_count, found, sizeof(CameraInfo)); + /* This camera is taken. */ + found->in_use = 1; + /* Update direction parameter. */ + if (csd->camera_info[csd->camera_count].direction != NULL) { + free(csd->camera_info[csd->camera_count].direction); + } + csd->camera_info[csd->camera_count].direction = ASTRDUP(dir); + D("Camera %d '%s' connected to '%s' facing %s using %.4s pixel format", + csd->camera_count, csd->camera_info[csd->camera_count].display_name, + csd->camera_info[csd->camera_count].device_name, + csd->camera_info[csd->camera_count].direction, + (const char*)(&csd->camera_info[csd->camera_count].pixel_format)); + csd->camera_count++; +} + /* Initializes camera service descriptor. */ static void @@ -272,107 +314,34 @@ _camera_service_init(CameraServiceDesc* csd) { CameraInfo ci[MAX_CAMERA]; int connected_cnt; - int i; /* Enumerate camera devices connected to the host. */ memset(ci, 0, sizeof(CameraInfo) * MAX_CAMERA); memset(csd->camera_info, 0, sizeof(CameraInfo) * MAX_CAMERA); csd->camera_count = 0; - if (android_hw->hw_camera == 0) { - /* Camera emulation is disabled. Skip enumeration of webcameras. */ + /* Lets see if HW config uses web cameras. */ + if (memcmp(android_hw->hw_camera_back, "webcam", 6) && + memcmp(android_hw->hw_camera_front, "webcam", 6)) { + /* Web camera emulation is disabled. Skip enumeration of webcameras. */ return; } + /* Enumerate web cameras connected to the host. */ connected_cnt = enumerate_camera_devices(ci, MAX_CAMERA); if (connected_cnt <= 0) { /* Nothing is connected - nothing to emulate. */ return; } - /* For each webcam declared in hw.ini find an actual camera information - * descriptor, and save it into the service descriptor for the emulation. - * Stop the loop when all the connected cameras have been added to the - * service. */ - for (i = 0; i < android_hw->hw_webcam_count && - csd->camera_count < connected_cnt; i++) { - const char* disp_name; - const char* dir; - CameraInfo* found; - - switch (i) { - case 0: - disp_name = android_hw->hw_webcam_0_name; - dir = android_hw->hw_webcam_0_direction; - break; - case 1: - disp_name = android_hw->hw_webcam_1_name; - dir = android_hw->hw_webcam_1_direction; - break; - case 2: - disp_name = android_hw->hw_webcam_2_name; - dir = android_hw->hw_webcam_2_direction; - break; - case 3: - disp_name = android_hw->hw_webcam_3_name; - dir = android_hw->hw_webcam_3_direction; - break; - case 4: - disp_name = android_hw->hw_webcam_4_name; - dir = android_hw->hw_webcam_4_direction; - break; - case 5: - default: - disp_name = android_hw->hw_webcam_5_name; - dir = android_hw->hw_webcam_5_direction; - break; - } - found = _camera_info_get_by_display_name(disp_name, ci, connected_cnt); - if (found != NULL) { - /* Save to the camera info array that will be used by the service. - * Note that we just copy everything over, and NULL the source - * record. */ - memcpy(csd->camera_info + csd->camera_count, found, sizeof(CameraInfo)); - /* Update direction parameter. */ - if (csd->camera_info[csd->camera_count].direction != NULL) { - free(csd->camera_info[csd->camera_count].direction); - } - csd->camera_info[csd->camera_count].direction = ASTRDUP(dir); - D("Camera %d '%s' connected to '%s' facing %s using %.4s pixel format", - csd->camera_count, csd->camera_info[csd->camera_count].display_name, - csd->camera_info[csd->camera_count].device_name, - csd->camera_info[csd->camera_count].direction, - (const char*)(&csd->camera_info[csd->camera_count].pixel_format)); - csd->camera_count++; - memset(found, 0, sizeof(CameraInfo)); - } else { - W("Camera name '%s' is not found in the list of connected cameras.\n" - "Use '-webcam list' emulator option to obtain the list of connected camera names.\n", - disp_name); - } + /* Set up back camera emulation. */ + if (!memcmp(android_hw->hw_camera_back, "webcam", 6)) { + _wecam_setup(csd, android_hw->hw_camera_back, "back", ci, connected_cnt); } - /* Make sure that camera 0 and camera 1 are facing in opposite directions. - * If they don't the camera application will crash on an attempt to switch - * cameras. */ - if (csd->camera_count > 0) { - const char* cam2_dir = NULL; - const char* cam2_name = NULL; - if (csd->camera_count >= 2) { - cam2_dir = csd->camera_info[1].direction; - cam2_name = csd->camera_info[1].display_name; - } else if (strcmp(android_hw->hw_fakeCamera, "off")) { - cam2_dir = android_hw->hw_fakeCamera; - cam2_name = "fake camera"; - } - if (cam2_dir != NULL && !strcmp(csd->camera_info[0].direction, cam2_dir)) { - W("Cameras '%s' and '%s' are both facing %s.\n" - "It is required by the camera application that first two emulated cameras\n" - "are facing in opposite directions. If they both are facing in the same direction,\n" - "the camera application will crash on an attempt to switch the camera.\n", - csd->camera_info[0].display_name, cam2_name, cam2_dir); - - } + /* Set up front camera emulation. */ + if (!memcmp(android_hw->hw_camera_front, "webcam", 6)) { + _wecam_setup(csd, android_hw->hw_camera_front, "front", ci, connected_cnt); } } @@ -407,7 +376,7 @@ static void _qemu_client_reply_payload(QemudClient* qc, size_t payload_size) { char payload_size_str[9]; - snprintf(payload_size_str, sizeof(payload_size_str), "%08x", payload_size); + snprintf(payload_size_str, sizeof(payload_size_str), "%08zx", payload_size); qemud_client_send(qc, (const uint8_t*)payload_size_str, 8); } @@ -1203,7 +1172,7 @@ _camera_client_recv(void* opaque, static const char _query_frame[] = "frame"; char query_name[64]; - const char* query_param; + const char* query_param = NULL; CameraClient* cc = (CameraClient*)opaque; /* diff --git a/android/cmdline-options.h b/android/cmdline-options.h index 0cf358f..5e8d59f 100644 --- a/android/cmdline-options.h +++ b/android/cmdline-options.h @@ -72,6 +72,7 @@ CFG_PARAM( initdata, "<file>", "same as '-init-data <file>'" ) CFG_PARAM( data, "<file>", "data image (default <datadir>/userdata-qemu.img" ) CFG_PARAM( partition_size, "<size>", "system/data partition size in MBs" ) CFG_PARAM( cache, "<file>", "cache partition image (default is temporary file)" ) +OPT_PARAM( cache_size, "<size>", "cache partition size in MBs" ) CFG_FLAG ( no_cache, "disable the cache partition" ) CFG_FLAG ( nocache, "same as -no-cache" ) OPT_PARAM( sdcard, "<file>", "SD card image (default <system>/sdcard.img") @@ -156,8 +157,13 @@ OPT_PARAM( attach_core, "<console socket>", "attach to a running core process" ) OPT_PARAM( gpu, "<mode>", "set hardware OpenGLES emulation mode" ) -OPT_PARAM( fake_camera, "<mode>", "set fake camera emulation mode" ) -OPT_LIST( webcam, "name=<name>[,dir=<direction>]", "setup web camera emulation" ) +OPT_PARAM( camera_back, "<mode>", "set emulation mode for a camera facing back" ) +OPT_PARAM( camera_front, "<mode>", "set emulation mode for a camera facing front" ) +OPT_FLAG( webcam_list, "lists web cameras available for emulation" ) + +OPT_PARAM( screen, "<mode>", "set emulated screen mode" ) + +OPT_FLAG( force_32bit, "always use 32-bit emulator" ) #undef CFG_FLAG #undef CFG_PARAM diff --git a/android/config/darwin-x86/config-host.h b/android/config/darwin-x86/config-host.h index 0395918..d5e8507 100644 --- a/android/config/darwin-x86/config-host.h +++ b/android/config/darwin-x86/config-host.h @@ -1,6 +1,15 @@ /* This file was autogenerated by 'android-configure.sh' */ #define CONFIG_QEMU_SHAREDIR "/usr/local/share/qemu" +#if defined(__x86_64__) +#define HOST_X86_64 1 +#define HOST_LONG_BITS 64 +#elif defined(__i386__) +#define HOST_I386 1 #define HOST_LONG_BITS 32 +#else +#error Unknown architecture for codegen +#endif + #define CONFIG_FNMATCH 1 #define CONFIG_GDBSTUB 1 #define CONFIG_SLIRP 1 @@ -9,7 +18,6 @@ #define CONFIG_NAND_LIMITS 1 #define QEMU_VERSION "0.10.50" #define QEMU_PKGVERSION "Android" -#define HOST_I386 1 #define CONFIG_IOVEC 1 #define CONFIG_DARWIN 1 #define CONFIG_BSD 1 @@ -18,3 +26,4 @@ #define CONFIG_ANDROID 1 #define CONFIG_POSIX 1 #define CONFIG_MADVISE 1 +#define CONFIG_ANDROID_OPENGLES 1 diff --git a/android/config/freebsd-x86/config-host.h b/android/config/freebsd-x86/config-host.h index 2e44a83..fd31de4 100644 --- a/android/config/freebsd-x86/config-host.h +++ b/android/config/freebsd-x86/config-host.h @@ -1,7 +1,15 @@ /* Automatically generated by configure - do not modify */ #define CONFIG_QEMU_SHAREDIR "/usr/local/share/qemu" -#define HOST_I386 1 -#define HOST_LONG_BITS 32 +#if defined(__x86_64__) +#define HOST_X86_64 1 +#define HOST_LONG_BITS 64 +#elif defined(__i386__) +#define HOST_I386 1 +#define HOST_LONG_BITS 32 +#else +#error Unknown architecture for codegen +#endif + #define CONFIG_MACHINE_BSWAP_H 1 #define CONFIG_FNMATCH 1 #define CONFIG_GDBSTUB 1 diff --git a/android/config/linux-x86/config-host.h b/android/config/linux-x86/config-host.h index 70a0eed..d9f04fa 100644 --- a/android/config/linux-x86/config-host.h +++ b/android/config/linux-x86/config-host.h @@ -1,6 +1,15 @@ /* This file was autogenerated by 'android-configure.sh' */ #define CONFIG_QEMU_SHAREDIR "/usr/local/share/qemu" +#if defined(__x86_64__) +#define HOST_X86_64 1 +#define HOST_LONG_BITS 64 +#elif defined(__i386__) +#define HOST_I386 1 #define HOST_LONG_BITS 32 +#else +#error Unknown architecture for codegen +#endif + #define CONFIG_BYTESWAP_H 1 #define CONFIG_FNMATCH 1 #define CONFIG_GDBSTUB 1 @@ -11,10 +20,10 @@ #define CONFIG_NAND_LIMITS 1 #define QEMU_VERSION "0.10.50" #define QEMU_PKGVERSION "Android" -#define HOST_I386 1 #define CONFIG_KVM_GS_RESTORE 1 #define CONFIG_IOVEC 1 #define CONFIG_LINUX 1 #define CONFIG_POSIX 1 #define CONFIG_ANDROID 1 #define CONFIG_MADVISE 1 +#define CONFIG_ANDROID_OPENGLES 1 diff --git a/android/config/windows/config-host.h b/android/config/windows/config-host.h index ef36e4c..2d2fdc6 100644 --- a/android/config/windows/config-host.h +++ b/android/config/windows/config-host.h @@ -1,12 +1,21 @@ /* This file was autogenerated by 'android-configure.sh' */ #define CONFIG_QEMU_SHAREDIR "/usr/local/share/qemu" +#if defined(__x86_64__) +#define HOST_X86_64 1 +#define HOST_LONG_BITS 64 +#elif defined(__i386__) +#define HOST_I386 1 #define HOST_LONG_BITS 32 +#else +#error Unknown architecture for codegen +#endif + #define CONFIG_GDBSTUB 1 #define CONFIG_SLIRP 1 #define CONFIG_SKINS 1 #define CONFIG_TRACE 1 #define QEMU_VERSION "0.10.50" #define QEMU_PKGVERSION "Android" -#define HOST_I386 1 #define CONFIG_WIN32 1 #define CONFIG_ANDROID 1 +#define CONFIG_ANDROID_OPENGLES 1 diff --git a/android/console.c b/android/console.c index ed02db5..07a59d2 100644 --- a/android/console.c +++ b/android/console.c @@ -1867,7 +1867,7 @@ do_event_send( ControlClient client, char* args ) if (q == p) break; - snprintf(temp, sizeof temp, "%.*s", q-p, p); + snprintf(temp, sizeof temp, "%.*s", (int)(intptr_t)(q-p), p); ret = android_event_from_str( temp, &type, &code, &value ); if (ret < 0) { if (ret == -1) { diff --git a/android/help.c b/android/help.c index 5f151ca..1570160 100644 --- a/android/help.c +++ b/android/help.c @@ -585,6 +585,15 @@ help_cache(stralloc_t* out) } static void +help_cache_size(stralloc_t* out) +{ + PRINTF( + " use '-cache <size>' to specify a /cache partition size in MB. By default,\n" + " the cache partition size is set to 66MB\n\n" + ); +} + +static void help_no_cache(stralloc_t* out) { PRINTF( @@ -1432,12 +1441,12 @@ static void help_gpu(stralloc_t* out) { PRINTF( - " Use -gpu <mode> to force the mode of hardware OpenGLES emulation.\n" - " Valid values for <mode> are:\n\n" + " Use -gpu <mode> to override the mode of hardware OpenGL ES emulation\n" + " indicated by the AVD. Valid values for <mode> are:\n\n" " on -> enable GPU emulation\n" " off -> disable GPU emulation\n" - " auto -> automatic detection\n" + " auto -> use the setting from the AVD\n" " enabled -> same as 'on'\n" " disabled -> same as 'off'\n\n" @@ -1448,43 +1457,71 @@ help_gpu(stralloc_t* out) " force the virtual device to use the slow software renderer instead.\n" " Note that OpenGLES 2.0 is _not_ supported by it.\n\n" - " The 'auto' mode is the default. It will only enable GPU emulation if the\n" - " virtual device supports it, and the host-side OpenGLES emulation library\n" - " could be properly initialized (this can fail when you run the emulator\n" - " under certain restricted environments where the program can't access the\n" - " graphics sub-system (e.g. head-less servers).\n" + " The 'auto' mode is the default. In this mode, the hw.gpu.enabled setting\n" + " in the AVD's hardware-qemu.ini file will determine whether GPU emulation\n" + " is enabled.\n\n" + + " Even if hardware GPU emulation is enabled, if the host-side OpenGL ES\n" + " emulation library cannot be initialized, the emulator will run with GPU\n" + " emulation disabled rather than failing to start.\n" ); } static void -help_fake_camera(stralloc_t* out) +help_camera_back(stralloc_t* out) { PRINTF( - " Use -fake-camera <mode> to control fake camera emulation.\n" + " Use -camera-back <mode> to control emulation of a camera facing back.\n" " Valid values for <mode> are:\n\n" - " off -> disable fake camera emulation\n" - " back -> fake camera is facing back\n" - " front -> fake camera is facing front\n\n" + " emulated -> camera will be emulated using software ('fake') camera emulation\n" + " webcam<N> -> camera will be emulated using a webcamera connected to the host\n" + " none -> camera emulation will be disabled\n\n" ); } static void -help_webcam(stralloc_t* out) +help_camera_front(stralloc_t* out) { PRINTF( - " Use -webcam off to disable web camera emulation.\n" - " Use -webcam list to list web cameras available for emulation.\n" - " Use -webcam name=<name>[,dir=<direction>] to setup parameters for web camera emulation.\n" + " Use -camera-front <mode> to control emulation of a camera facing front.\n" + " Valid values for <mode> are:\n\n" - " <name> platform-independent name identifying emulated camera device.\n" - " use '-webcam list' to obtain the list of emulated camera devices.\n" - " <direction> defines direction the camera is facing. Valid values are:\n\n" + " emulated -> camera will be emulated using software ('fake') camera emulation\n" + " webcam<N> -> camera will be emulated using a webcamera connected to the host\n" + " none -> camera emulation will be disabled\n\n" + ); +} - " front -> emulate camera as facing front\n" - " back -> emulate camera as facing back\n\n" +static void +help_webcam_list(stralloc_t* out) +{ + PRINTF( + " Use -webcam-list to list web cameras available for emulation.\n\n" + ); +} + +static void +help_screen(stralloc_t* out) +{ + PRINTF( + " Use -screen <mode> to set the emulated screen mode.\n" + " Valid values for <mode> are:\n\n" + + " touch -> emulate a touch screen\n" + " multi-touch -> emulate a multi-touch screen\n" + " no-touch -> disable touch and multi-touch screen emulation\n\n" + + " Default mode for screen emulation is 'touch'.\n\n" + ); +} + +static void +help_force_32bit(stralloc_t* out) +{ + PRINTF( + " Use -force-32bit to use 32-bit emulator on 64-bit platforms\n\n" - " Default direction value for emulated web camera is 'front'\n\n" ); } diff --git a/android/hw-events.h b/android/hw-events.h index 488c299..b8340bd 100644 --- a/android/hw-events.h +++ b/android/hw-events.h @@ -41,6 +41,17 @@ typedef enum { /* BEWARE: The following codes are defined by the Linux kernel headers. * The Android "Menu" key is KEY_SOFT1, *not* KEY_MENU */ +/* NOTE: mingw's winnt.h define DELETE to constant + i586-mingw32msvc: #define DELETE 0x00010000L + x86_64-w64-mingw32-gcc: #define DELETE (0x00010000L) + + KEY_CODE belows glues "KEY_" and "DELETE". + While KEY_0x00010000L may not mean anything, + KEY_(0x00010000L) is absolutely harmful to compiler. + Undefine DELETE below + */ +#undef DELETE + #define EVENT_KEY_LIST \ KEY_CODE(ESC ,1) \ KEY_CODE(1 ,2) \ diff --git a/android/hw-sensors.c b/android/hw-sensors.c index 51170cb..a7daea5 100644 --- a/android/hw-sensors.c +++ b/android/hw-sensors.c @@ -339,7 +339,7 @@ _hwSensorClient_tick( void* opaque ) now_ns = qemu_get_clock_ns(vm_clock); - snprintf(buffer, sizeof buffer, "sync:%lld", now_ns/1000); + snprintf(buffer, sizeof buffer, "sync:%" PRId64, now_ns/1000); _hwSensorClient_send(cl, (uint8_t*)buffer, strlen(buffer)); /* rearm timer, use a minimum delay of 20 ms, just to @@ -438,7 +438,7 @@ _hwSensorClient_receive( HwSensorClient* cl, uint8_t* msg, int msglen ) } /* If emulating device is connected update sensor state there too. */ - if (hw->sensors_port != NULL && sensors_port_is_connected(hw->sensors_port)) { + if (hw->sensors_port != NULL) { if (enabled) { sensors_port_enable_sensor(hw->sensors_port, (const char*)msg); } else { @@ -692,11 +692,6 @@ _hwSensors_init( HwSensors* h ) h->sensors[ANDROID_SENSOR_TEMPERATURE].enabled = 1; } - if (h->sensors_port != NULL) { - /* Init sensors on the attached device. */ - sensors_port_init_sensors(h->sensors_port); - } - /* XXX: TODO: Add other tests when we add the corresponding * properties to hardware-properties.ini et al. */ diff --git a/android/looper-qemu.c b/android/looper-qemu.c index 714b48d..c5cffcd 100644 --- a/android/looper-qemu.c +++ b/android/looper-qemu.c @@ -46,7 +46,7 @@ qlooptimer_startAbsolute(void* impl, Duration deadline_ms) if (deadline_ms == DURATION_INFINITE) qemu_del_timer(tt); else - qemu_mod_timer(tt, deadline_ms*1000000); + qemu_mod_timer(tt, deadline_ms); } static void diff --git a/android/main-common.c b/android/main-common.c index 04d200a..2d535c7 100644 --- a/android/main-common.c +++ b/android/main-common.c @@ -232,7 +232,7 @@ sdl_set_window_icon( void ) SDL_GetWMInfo(&wminfo); - SetClassLong( wminfo.window, GCL_HICON, (LONG)icon ); + SetClassLongPtr( wminfo.window, GCLP_HICON, (LONG)icon ); #else /* !_WIN32 */ unsigned icon_w, icon_h; size_t icon_bytes; diff --git a/android/main-emulator.c b/android/main-emulator.c index a6e95c7..0981a71 100644 --- a/android/main-emulator.c +++ b/android/main-emulator.c @@ -50,10 +50,20 @@ int android_verbose; # define DLL_EXTENSION ".so" #endif +#if defined(__x86_64__) +/* Normally emulator is compiled in 32-bit. In standalone it can be compiled + in 64-bit (with ,/android-configure.sh --try-64). In this case, emulator-$ARCH + are also compiled in 64-bit and will search for lib64*.so instead of lib*so */ +#define GLES_EMULATION_LIB "lib64OpenglRender" DLL_EXTENSION +#elif defined(__i386__) #define GLES_EMULATION_LIB "libOpenglRender" DLL_EXTENSION +#else +#error Unknown architecture for codegen +#endif + /* Forward declarations */ -static char* getTargetEmulatorPath(const char* progName, const char* avdArch); +static char* getTargetEmulatorPath(const char* progName, const char* avdArch, const int force_32bit); static char* getSharedLibraryPath(const char* progName, const char* libName); static void prependSharedLibraryPath(const char* prefix); @@ -80,6 +90,7 @@ int main(int argc, char** argv) const char* avdName = NULL; char* avdArch = NULL; char* emulatorPath; + int force_32bit = 0; /* Define ANDROID_EMULATOR_DEBUG to 1 in your environment if you want to * see the debug messages from this launcher program. @@ -89,8 +100,9 @@ int main(int argc, char** argv) if (debug != NULL && *debug && *debug != '0') android_verbose = 1; - /* Parse command-line and look for an avd name - * Either in the form or '-avd <name>' or '@<name>' + /* Parse command-line and look for + * 1) an avd name either in the form or '-avd <name>' or '@<name>' + * 2) '-force-32bit' which always use 32-bit emulator on 64-bit platforms */ int nn; for (nn = 1; nn < argc; nn++) { @@ -99,13 +111,18 @@ int main(int argc, char** argv) if (!strcmp(opt,"-qemu")) break; - if (!strcmp(opt,"-avd") && nn+1 < argc) { - avdName = argv[nn+1]; - break; + if (!strcmp(opt,"-force-32bit")) { + force_32bit = 1; + continue; } - else if (opt[0] == '@' && opt[1] != '\0') { - avdName = opt+1; - break; + + if (!avdName) { + if (!strcmp(opt,"-avd") && nn+1 < argc) { + avdName = argv[nn+1]; + } + else if (opt[0] == '@' && opt[1] != '\0') { + avdName = opt+1; + } } } @@ -133,7 +150,7 @@ int main(int argc, char** argv) } /* Find the architecture-specific program in the same directory */ - emulatorPath = getTargetEmulatorPath(argv[0], avdArch); + emulatorPath = getTargetEmulatorPath(argv[0], avdArch, force_32bit); D("Found target-specific emulator binary: %s\n", emulatorPath); /* Replace it in our command-line */ @@ -173,33 +190,75 @@ int main(int argc, char** argv) return errno; } +static int +getHostOSBitness() +{ + /* + This function returns 64 if host is running 64-bit OS, or 32 otherwise. + + It uses the same technique in ndk/build/core/ndk-common.sh. + Here are comments from there: + + ## On Linux or Darwin, a 64-bit kernel (*) doesn't mean that the user-land + ## is always 32-bit, so use "file" to determine the bitness of the shell + ## that invoked us. The -L option is used to de-reference symlinks. + ## + ## Note that on Darwin, a single executable can contain both x86 and + ## x86_64 machine code, so just look for x86_64 (darwin) or x86-64 (Linux) + ## in the output. + + (*) ie. The following code doesn't always work: + struct utsname u; + int host_runs_64bit_OS = (uname(&u) == 0 && strcmp(u.machine, "x86_64") == 0); + */ + return system("file -L \"$SHELL\" | grep -q \"x86[_-]64\"") == 0 ? 64 : 32; +} /* Find the target-specific emulator binary. This will be something * like <programDir>/emulator-<targetArch>, where <programDir> is * the directory of the current program. */ static char* -getTargetEmulatorPath(const char* progName, const char* avdArch) +getTargetEmulatorPath(const char* progName, const char* avdArch, const int force_32bit) { char* progDir; - char temp[PATH_MAX], *p=temp, *end=p+sizeof(temp); + char path[PATH_MAX], *pathEnd=path+sizeof(path), *p; + const char* emulatorPrefix = "emulator-"; + const char* emulator64Prefix = "emulator64-"; #ifdef _WIN32 const char* exeExt = ".exe"; + /* ToDo: currently amd64-mingw32msvc-gcc doesn't work (http://b/issue?id=5949152) + which prevents us from generating 64-bit emulator for Windows */ + int search_for_64bit_emulator = 0; #else const char* exeExt = ""; + int search_for_64bit_emulator = !force_32bit && getHostOSBitness() == 64; #endif /* Get program's directory name in progDir */ path_split(progName, &progDir, NULL); - p = bufprint(temp, end, "%s/emulator-%s%s", progDir, avdArch, exeExt); + if (search_for_64bit_emulator) { + /* Find 64-bit emulator first */ + p = bufprint(path, pathEnd, "%s/%s%s%s", progDir, emulator64Prefix, avdArch, exeExt); + if (p >= pathEnd) { + APANIC("Path too long: %s\n", progName); + } + if (path_exists(path)) { + free(progDir); + return strdup(path); + } + } + + /* Find 32-bit emulator */ + p = bufprint(path, pathEnd, "%s/%s%s%s", progDir, emulatorPrefix, avdArch, exeExt); free(progDir); - if (p >= end) { + if (p >= pathEnd) { APANIC("Path too long: %s\n", progName); } - if (path_exists(temp)) { - return strdup(temp); + if (path_exists(path)) { + return strdup(path); } /* Mmm, the file doesn't exist, If there is no slash / backslash @@ -210,16 +269,25 @@ getTargetEmulatorPath(const char* progName, const char* avdArch) #else if (strchr(progName, '/') == NULL) { #endif - p = bufprint(temp, end, "emulator-%s%s", avdArch, exeExt); - if (p < end) { - char* resolved = path_search_exec(temp); + if (search_for_64bit_emulator) { + p = bufprint(path, pathEnd, "%s%s%s", emulator64Prefix, avdArch, exeExt); + if (p < pathEnd) { + char* resolved = path_search_exec(path); + if (resolved != NULL) + return resolved; + } + } + + p = bufprint(path, pathEnd, "%s%s%s", emulatorPrefix, avdArch, exeExt); + if (p < pathEnd) { + char* resolved = path_search_exec(path); if (resolved != NULL) return resolved; } } /* Otherwise, the program is missing */ - APANIC("Missing arch-specific emulator program: %s\n", temp); + APANIC("Missing arch-specific emulator program: %s\n", path); return NULL; } @@ -271,7 +339,7 @@ getSharedLibraryPath(const char* progName, const char* libName) } /* try in $progDir/../lib, this corresponds to the platform build - * where the emulator binary is under out/host/<system>/lib and + * where the emulator binary is under out/host/<system>/bin and * the libraries are under out/host/<system>/lib */ { diff --git a/android/main.c b/android/main.c index b7421a1..d9d2274 100644 --- a/android/main.c +++ b/android/main.c @@ -145,7 +145,7 @@ _adjustPartitionSize( const char* description, if (imageMB > defaultMB) { snprintf(temp, sizeof temp, "(%d MB > %d MB)", imageMB, defaultMB); } else { - snprintf(temp, sizeof temp, "(%lld bytes > %lld bytes)", imageBytes, defaultBytes); + snprintf(temp, sizeof temp, "(%" PRIu64 " bytes > %" PRIu64 " bytes)", imageBytes, defaultBytes); } if (inAndroidBuild) { @@ -155,65 +155,6 @@ _adjustPartitionSize( const char* description, return convertMBToBytes(imageMB); } -/* Parses a -webcam option, extracting 'name', and 'dir' values. - * Param: - * param - -webcam option, that should be formatted as such: - * name=<name>[,dir=<direction>] - * name, name_size - buffer (and its size) where to receive <name> - * dir, dir_size - buffer (and its size) where to receive <direction> - */ -static void -_parseWebcamOption(const char* param, - char* name, size_t name_size, - char* dir, size_t dir_size) -{ - const char* dr; - const char* wc_opt = param; - - /* Must start with 'name=' */ - if (strlen(wc_opt) <= 5 || memcmp(wc_opt, "name=", 5)) { - derror("Invalid value for -webcam parameter: %s\n", param); - exit(1); - } - - /* Move on to 'name' value. */ - wc_opt += 5; - dr = strchr(wc_opt, ','); - if (dr == NULL) { - dr = wc_opt + strlen(wc_opt); - } - - /* Make sure that <name> fits */ - if ((dr - wc_opt) < name_size) { - memcpy(name, wc_opt, dr - wc_opt); - name[dr - wc_opt] = '\0'; - if (*dr == '\0') { - /* Default direction value is 'front' */ - strcpy(dir, "front"); - return; - } else { - dr++; - } - } else { - derror("Invalid <name> value for -webcam parameter: %s\n", param); - exit(1); - } - - /* Parse 'dir'. Must begin with 'dir=' */ - if (strlen(dr) <= 4 || memcmp(dr, "dir=", 4)) { - derror("Invalid value for -webcam parameter: %s\n", param); - exit(1); - } - dr += 4; - /* Check the bounds, and the values */ - if (strlen(dr) >= dir_size || (strcmp(dr, "front") && strcmp(dr, "back"))) { - derror("Invalid <direction> value for -webcam parameter: %s\n" - "Valid values are: 'front', or 'back'\n", param); - exit(1); - } - strcpy(dir, dr); -} - int main(int argc, char **argv) { char tmp[MAX_PATH]; @@ -235,7 +176,7 @@ int main(int argc, char **argv) AConfig* skinConfig; char* skinPath; int inAndroidBuild; - uint64_t defaultPartitionSize = convertMBToBytes(66); + uint64_t defaultPartitionSize = convertMBToBytes(200); AndroidOptions opts[1]; /* net.shared_net_ip boot property value. */ @@ -378,6 +319,9 @@ int main(int argc, char **argv) opts->skindir = skinDir; D("autoconfig: -skindir %s", opts->skindir); + + /* update the avd hw config from this new skin */ + avdInfo_getSkinHardwareIni(avd, opts->skin, opts->skindir); } /* Read hardware configuration */ @@ -729,7 +673,7 @@ int main(int argc, char **argv) uint64_t defaultBytes = hw->disk_dataPartition_size == 0 ? defaultPartitionSize : - convertMBToBytes(hw->disk_dataPartition_size); + hw->disk_dataPartition_size; uint64_t dataBytes; const char* dataPath = hw->disk_dataPartition_initPath; @@ -779,6 +723,18 @@ int main(int argc, char **argv) } } + if (hw->disk_cachePartition_path && opts->cache_size) { + /* Set cache partition size per user options. */ + char* end; + long sizeMB = strtol(opts->cache_size, &end, 0); + + if (sizeMB < 0 || *end != 0) { + derror( "-cache-size must be followed by a positive integer" ); + exit(1); + } + hw->disk_cachePartition_size = (uint64_t) sizeMB * ONE_MB; + } + /** SD CARD PARTITION */ if (!hw->hw_sdCard) { @@ -853,7 +809,7 @@ int main(int argc, char **argv) } else { - if (!opts->snapstorage) { + if (!opts->snapstorage && avdInfo_getSnapshotPresent(avd)) { opts->snapstorage = avdInfo_getSnapStoragePath(avd); if (opts->snapstorage != NULL) { D("autoconfig: -snapstorage %s", opts->snapstorage); @@ -1164,90 +1120,36 @@ int main(int argc, char **argv) exit(1); } - if (opts->fake_camera) { - if (!strcmp(opts->fake_camera, "back") || - !strcmp(opts->fake_camera, "front") || - !strcmp(opts->fake_camera, "off")) { - hw->hw_fakeCamera = ASTRDUP(opts->fake_camera); - } else { - derror("Invalid value for -fake-camera <mode> parameter: %s\n", - opts->fake_camera); - derror("Valid values are: back, front, or off\n"); - exit(1); - } + /* Deal with camera emulation */ + if (opts->webcam_list) { + /* List connected webcameras */ + args[n++] = "-list-webcam"; } - int webcam_num = 0; - if (opts->webcam != NULL) { - ParamList* pl = opts->webcam; - for ( ; pl != NULL; pl = pl->next ) { - char webcam_name[64]; - char webcam_dir[16]; - if (!strcmp(pl->param, "off")) { - /* If 'off' is passed, there must be no other -webcam options. */ - if (webcam_num || pl->next != NULL) { - derror("'-webcam off' cannot be combined with other -webcam otions\n"); - exit(1); - } - break; - } - if (!strcmp(pl->param, "list")) { - /* If 'list' is passed, there must be no other -webcam options. */ - if (webcam_num || pl->next != NULL) { - derror("'-webcam list' cannot be combined with other -webcam otions\n"); - exit(1); - } - args[n++] = "-list-webcam"; - break; - } - /* Extract name, and direction */ - _parseWebcamOption(pl->param, webcam_name, sizeof(webcam_name), - webcam_dir, sizeof(webcam_dir)); - /* Save them to appropriate field in hw.ini */ - switch (webcam_num) { - case 0: - hw->hw_webcam_0_name = ASTRDUP(webcam_name); - hw->hw_webcam_0_direction = ASTRDUP(webcam_dir); - break; - case 1: - hw->hw_webcam_1_name = ASTRDUP(webcam_name); - hw->hw_webcam_1_direction = ASTRDUP(webcam_dir); - break; - case 2: - hw->hw_webcam_2_name = ASTRDUP(webcam_name); - hw->hw_webcam_2_direction = ASTRDUP(webcam_dir); - break; - case 3: - hw->hw_webcam_3_name = ASTRDUP(webcam_name); - hw->hw_webcam_3_direction = ASTRDUP(webcam_dir); - break; - case 4: - hw->hw_webcam_4_name = ASTRDUP(webcam_name); - hw->hw_webcam_4_direction = ASTRDUP(webcam_dir); - break; - case 5: - hw->hw_webcam_5_name = ASTRDUP(webcam_name); - hw->hw_webcam_5_direction = ASTRDUP(webcam_dir); - break; - default: - derror("Too many -webcam options. Maximum number of -webcam options is 6\n"); - exit(1); - } - webcam_num++; + if (opts->camera_back) { + /* Validate parameter. */ + if (memcmp(opts->camera_back, "webcam", 6) && + strcmp(opts->camera_back, "emulated") && + strcmp(opts->camera_back, "none")) { + derror("Invalid value for -camera-back <mode> parameter: %s\n" + "Valid values are: 'emulated', 'webcam<N>', or 'none'\n", + opts->camera_back); + exit(1); } - hw->hw_webcam_count = webcam_num; + hw->hw_camera_back = ASTRDUP(opts->camera_back); } - /* Command line options related to webcam, and fake camera should - * override camera emulation flag, set in AVD. */ - if (hw->hw_camera == 0) { - /* Camera emulation is disabled in AVD. Lets see if command line enables - * webcam, or fake camera emulation. */ - if (webcam_num != 0 || - (opts->fake_camera && strcmp(hw->hw_fakeCamera, "off") != 0)) { - /* Command line parameters enable camera emulation. */ - hw->hw_camera = 1; + if (opts->camera_front) { + /* Validate parameter. */ + if (memcmp(opts->camera_front, "webcam", 6) && + strcmp(opts->camera_front, "emulated") && + strcmp(opts->camera_front, "none")) { + derror("Invalid value for -camera-front <mode> parameter: %s\n" + "Valid values are: 'emulated', 'webcam<N>', or 'none'\n", + opts->camera_front); + exit(1); } + hw->hw_camera_front = ASTRDUP(opts->camera_front); } /* physical memory is now in hw->hw_ramSize */ @@ -1271,6 +1173,20 @@ int main(int argc, char **argv) args[n++] = "socket,vlan=1,mcast=230.0.0.10:1234"; } + /* Setup screen emulation */ + if (opts->screen) { + if (strcmp(opts->screen, "touch") && + strcmp(opts->screen, "multi-touch") && + strcmp(opts->screen, "no-touch")) { + + derror("Invalid value for -screen <mode> parameter: %s\n" + "Valid values are: touch, multi-touch, or no-touch\n", + opts->screen); + exit(1); + } + hw->hw_screen = ASTRDUP(opts->screen); + } + while(argc-- > 0) { args[n++] = *argv++; } diff --git a/android/multitouch-port.c b/android/multitouch-port.c new file mode 100644 index 0000000..7cb9656 --- /dev/null +++ b/android/multitouch-port.c @@ -0,0 +1,442 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "qemu-common.h" +#include "utils/panic.h" +#include "android/hw-events.h" +#include "android/charmap.h" +#include "android/multitouch-screen.h" +#include "android/sdk-controller-socket.h" +#include "android/multitouch-port.h" +#include "android/globals.h" /* for android_hw */ +#include "android/utils/misc.h" +#include "android/utils/jpeg-compress.h" +#include "android/utils/debug.h" + +#define E(...) derror(__VA_ARGS__) +#define W(...) dwarning(__VA_ARGS__) +#define D(...) VERBOSE_PRINT(mtport,__VA_ARGS__) +#define D_ACTIVE VERBOSE_CHECK(mtport) + +#define TRACE_ON 1 + +#if TRACE_ON +#define T(...) VERBOSE_PRINT(mtport,__VA_ARGS__) +#else +#define T(...) +#endif + +/* Timeout (millisec) to use when communicating with SDK controller. */ +#define SDKCTL_MT_TIMEOUT 3000 + +/* + * Message types used in multi-touch emulation. + */ + +/* Pointer move message. */ +#define SDKCTL_MT_MOVE 1 +/* First pointer down message. */ +#define SDKCTL_MT_FISRT_DOWN 2 +/* Last pointer up message. */ +#define SDKCTL_MT_LAST_UP 3 +/* Pointer down message. */ +#define SDKCTL_MT_POINTER_DOWN 4 +/* Pointer up message. */ +#define SDKCTL_MT_POINTER_UP 5 +/* Sends framebuffer update. */ +#define SDKCTL_MT_FB_UPDATE 6 + +/* Multi-touch port descriptor. */ +struct AndroidMTSPort { + /* Caller identifier. */ + void* opaque; + /* Communication socket. */ + SDKCtlSocket* sdkctl; + /* Initialized JPEG compressor instance. */ + AJPEGDesc* jpeg_compressor; + /* Direct packet descriptor for framebuffer updates. */ + SDKCtlDirectPacket* fb_packet; +}; + +/* Data sent with SDKCTL_MT_QUERY_START */ +typedef struct QueryDispData { + /* Width of the emulator display. */ + int width; + /* Height of the emulator display. */ + int height; +} QueryDispData; + +/* Multi-touch event structure received from SDK controller port. */ +typedef struct AndroidMTEvent { + /* Pointer identifier. */ + int pid; + /* Pointer 'x' coordinate. */ + int x; + /* Pointer 'y' coordinate. */ + int y; + /* Pointer pressure. */ + int pressure; +} AndroidMTEvent; + +/* Multi-touch pointer descriptor received from SDK controller port. */ +typedef struct AndroidMTPtr { + /* Pointer identifier. */ + int pid; +} AndroidMTPtr; + +/* Destroys and frees the descriptor. */ +static void +_mts_port_free(AndroidMTSPort* mtsp) +{ + if (mtsp != NULL) { + if (mtsp->fb_packet != NULL) { + sdkctl_direct_packet_release(mtsp->fb_packet); + } + if (mtsp->jpeg_compressor != NULL) { + jpeg_compressor_destroy(mtsp->jpeg_compressor); + } + if (mtsp->sdkctl != NULL) { + sdkctl_socket_release(mtsp->sdkctl); + } + AFREE(mtsp); + } +} + +/******************************************************************************** + * Multi-touch action handlers + *******************************************************************************/ + +/* + * Although there are a lot of similarities in the way the handlers below are + * implemented, for the sake of tracing / debugging it's better to have a + * separate handler for each distinctive action. + */ + +/* First pointer down event handler. */ +static void +_on_action_down(int tracking_id, int x, int y, int pressure) +{ + multitouch_update_pointer(MTES_DEVICE, tracking_id, x, y, pressure); +} + +/* Last pointer up event handler. */ +static void +_on_action_up(int tracking_id) +{ + multitouch_update_pointer(MTES_DEVICE, tracking_id, 0, 0, 0); +} + +/* Pointer down event handler. */ +static void +_on_action_pointer_down(int tracking_id, int x, int y, int pressure) +{ + multitouch_update_pointer(MTES_DEVICE, tracking_id, x, y, pressure); +} + +/* Pointer up event handler. */ +static void +_on_action_pointer_up(int tracking_id) +{ + multitouch_update_pointer(MTES_DEVICE, tracking_id, 0, 0, 0); +} + +/* Pointer move event handler. */ +static void +_on_action_move(int tracking_id, int x, int y, int pressure) +{ + multitouch_update_pointer(MTES_DEVICE, tracking_id, x, y, pressure); +} + +/******************************************************************************** + * Multi-touch event handlers + *******************************************************************************/ + +/* Handles "pointer move" event. + * Param: + * param - Array of moving pointers. + * pointers_count - Number of pointers in the array. + */ +static void +_on_move(const AndroidMTEvent* param, int pointers_count) +{ + int n; + for (n = 0; n < pointers_count; n++, param++) { + T("Multi-touch: MOVE(%d): %d-> %d:%d:%d", + n, param->pid, param->x, param->y, param->pressure); + _on_action_move(param->pid, param->x, param->y, param->pressure); + } +} + +/* Handles "first pointer down" event. */ +static void +_on_down(const AndroidMTEvent* param) +{ + T("Multi-touch: 1-ST DOWN: %d-> %d:%d:%d", + param->pid, param->x, param->y, param->pressure); + _on_action_down(param->pid, param->x, param->y, param->pressure); +} + +/* Handles "last pointer up" event. */ +static void +_on_up(const AndroidMTPtr* param) +{ + T("Multi-touch: LAST UP: %d", param->pid); + _on_action_up(param->pid); +} + +/* Handles "next pointer down" event. */ +static void +_on_pdown(const AndroidMTEvent* param) +{ + T("Multi-touch: DOWN: %d-> %d:%d:%d", + param->pid, param->x, param->y, param->pressure); + _on_action_pointer_down(param->pid, param->x, param->y, param->pressure); +} + +/* Handles "next pointer up" event. */ +static void +_on_pup(const AndroidMTPtr* param) +{ + T("Multi-touch: UP: %d", param->pid); + _on_action_pointer_up(param->pid); +} + +/******************************************************************************** + * Device communication callbacks + *******************************************************************************/ + +/* A callback that is invoked on SDK controller socket connection events. */ +static AsyncIOAction +_on_multitouch_socket_connection(void* opaque, + SDKCtlSocket* sdkctl, + AsyncIOState status) +{ + if (status == ASIO_STATE_FAILED) { + /* Reconnect (after timeout delay) on failures */ + if (sdkctl_socket_is_handshake_ok(sdkctl)) { + sdkctl_socket_reconnect(sdkctl, SDKCTL_DEFAULT_TCP_PORT, + SDKCTL_MT_TIMEOUT); + } + } + return ASIO_ACTION_DONE; +} + +/* A callback that is invoked on SDK controller port connection events. */ +static void +_on_multitouch_port_connection(void* opaque, + SDKCtlSocket* sdkctl, + SdkCtlPortStatus status) +{ + switch (status) { + case SDKCTL_PORT_CONNECTED: + D("Multi-touch: SDK Controller is connected"); + break; + + case SDKCTL_PORT_DISCONNECTED: + D("Multi-touch: SDK Controller is disconnected"); + break; + + case SDKCTL_PORT_ENABLED: + D("Multi-touch: SDK Controller port is enabled."); + break; + + case SDKCTL_PORT_DISABLED: + D("Multi-touch: SDK Controller port is disabled."); + break; + + case SDKCTL_HANDSHAKE_CONNECTED: + D("Multi-touch: Handshake succeeded with connected port."); + break; + + case SDKCTL_HANDSHAKE_NO_PORT: + D("Multi-touch: Handshake succeeded with disconnected port."); + break; + + case SDKCTL_HANDSHAKE_DUP: + W("Multi-touch: Handshake failed due to port duplication."); + sdkctl_socket_disconnect(sdkctl); + break; + + case SDKCTL_HANDSHAKE_UNKNOWN_QUERY: + W("Multi-touch: Handshake failed due to unknown query."); + sdkctl_socket_disconnect(sdkctl); + break; + + case SDKCTL_HANDSHAKE_UNKNOWN_RESPONSE: + default: + W("Multi-touch: Handshake failed due to unknown reason."); + sdkctl_socket_disconnect(sdkctl); + break; + } +} + +/* A callback that is invoked when a message is received from the device. */ +static void +_on_multitouch_message(void* client_opaque, + SDKCtlSocket* sdkctl, + SDKCtlMessage* message, + int msg_type, + void* msg_data, + int msg_size) +{ + switch (msg_type) { + case SDKCTL_MT_MOVE: { + assert((msg_size / sizeof(AndroidMTEvent)) && !(msg_size % sizeof(AndroidMTEvent))); + _on_move((const AndroidMTEvent*)msg_data, msg_size / sizeof(AndroidMTEvent)); + break; + } + + case SDKCTL_MT_FISRT_DOWN: + assert(msg_size / sizeof(AndroidMTEvent) && !(msg_size % sizeof(AndroidMTEvent))); + _on_down((const AndroidMTEvent*)msg_data); + break; + + case SDKCTL_MT_LAST_UP: + _on_up((const AndroidMTPtr*)msg_data); + break; + + case SDKCTL_MT_POINTER_DOWN: + assert(msg_size / sizeof(AndroidMTEvent) && !(msg_size % sizeof(AndroidMTEvent))); + _on_pdown((const AndroidMTEvent*)msg_data); + break; + + case SDKCTL_MT_POINTER_UP: + _on_pup((const AndroidMTPtr*)msg_data); + break; + + default: + W("Multi-touch: Unknown message %d", msg_type); + break; + } +} + +/******************************************************************************** + * MTS port API + *******************************************************************************/ + +AndroidMTSPort* +mts_port_create(void* opaque) +{ + AndroidMTSPort* mtsp; + + ANEW0(mtsp); + mtsp->opaque = opaque; + + /* Initialize default MTS descriptor. */ + multitouch_init(mtsp); + + /* Create JPEG compressor. Put message header + MTFrameHeader in front of the + * compressed data. this way we will have entire query ready to be + * transmitted to the device. */ + mtsp->jpeg_compressor = + jpeg_compressor_create(sdkctl_message_get_header_size() + sizeof(MTFrameHeader), 4096); + + mtsp->sdkctl = sdkctl_socket_new(SDKCTL_MT_TIMEOUT, "multi-touch", + _on_multitouch_socket_connection, + _on_multitouch_port_connection, + _on_multitouch_message, mtsp); + sdkctl_init_recycler(mtsp->sdkctl, 64, 8); + + /* Create a direct packet that will wrap up framebuffer updates. Note that + * we need to do this after we have initialized the recycler! */ + mtsp->fb_packet = sdkctl_direct_packet_new(mtsp->sdkctl); + + /* Now we can initiate connection witm MT port on the device. */ + sdkctl_socket_connect(mtsp->sdkctl, SDKCTL_DEFAULT_TCP_PORT, + SDKCTL_MT_TIMEOUT); + + return mtsp; +} + +void +mts_port_destroy(AndroidMTSPort* mtsp) +{ + _mts_port_free(mtsp); +} + +/******************************************************************************** + * Handling framebuffer updates + *******************************************************************************/ + +/* Compresses a framebuffer region into JPEG image. + * Param: + * mtsp - Multi-touch port descriptor with initialized JPEG compressor. + * fmt Descriptor for framebuffer region to compress. + * fb Beginning of the framebuffer. + * jpeg_quality JPEG compression quality. A number from 1 to 100. Note that + * value 10 provides pretty decent image for the purpose of multi-touch + * emulation. + */ +static void +_fb_compress(const AndroidMTSPort* mtsp, + const MTFrameHeader* fmt, + const uint8_t* fb, + int jpeg_quality, + int ydir) +{ + T("Multi-touch: compressing %d bytes frame buffer", fmt->w * fmt->h * fmt->bpp); + + jpeg_compressor_compress_fb(mtsp->jpeg_compressor, fmt->x, fmt->y, fmt->w, + fmt->h, fmt->disp_height, fmt->bpp, fmt->bpl, + fb, jpeg_quality, ydir); +} + +int +mts_port_send_frame(AndroidMTSPort* mtsp, + MTFrameHeader* fmt, + const uint8_t* fb, + on_sdkctl_direct_cb cb, + void* cb_opaque, + int ydir) +{ + /* Make sure that port is connected. */ + if (!sdkctl_socket_is_port_ready(mtsp->sdkctl)) { + return -1; + } + + /* Compress framebuffer region. 10% quality seems to be sufficient. */ + fmt->format = MTFB_JPEG; + _fb_compress(mtsp, fmt, fb, 10, ydir); + + /* Total size of the update data: header + JPEG image. */ + const int update_size = + sizeof(MTFrameHeader) + jpeg_compressor_get_jpeg_size(mtsp->jpeg_compressor); + + /* Update message starts at the beginning of the buffer allocated by the + * compressor's destination manager. */ + uint8_t* const msg = (uint8_t*)jpeg_compressor_get_buffer(mtsp->jpeg_compressor); + + /* Initialize message header. */ + sdkctl_init_message_header(msg, SDKCTL_MT_FB_UPDATE, update_size); + + /* Copy framebuffer update header to the message. */ + memcpy(msg + sdkctl_message_get_header_size(), fmt, sizeof(MTFrameHeader)); + + /* Compression rate... */ + const float comp_rate = ((float)jpeg_compressor_get_jpeg_size(mtsp->jpeg_compressor) / (fmt->w * fmt->h * fmt->bpp)) * 100; + + /* Zeroing the rectangle in the update header we indicate that it contains + * no updates. */ + fmt->x = fmt->y = fmt->w = fmt->h = 0; + + /* Send update to the device. */ + sdkctl_direct_packet_send(mtsp->fb_packet, msg, cb, cb_opaque); + + T("Multi-touch: Sent %d bytes in framebuffer update. Compression rate is %.2f%%", + update_size, comp_rate); + + return 0; +} diff --git a/android/multitouch-port.h b/android/multitouch-port.h new file mode 100644 index 0000000..5652b43 --- /dev/null +++ b/android/multitouch-port.h @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ANDROID_ANDROID_MULTITOUCH_PORT_H_ +#define ANDROID_ANDROID_MULTITOUCH_PORT_H_ + +#include "android/sdk-controller-socket.h" + +/* + * Encapsulates exchange protocol between the multi-touch screen emulator, and an + * application running on an Android device that provides touch events, and is + * connected to the host via USB. + */ + +/* + * Codes that define transmitted framebuffer format: + * + * NOTE: Application on the device side depends on these values. Any changes + * made here must be reflected in the app too. Application location is at + * 'sdk/apps/SdkController/SdkControllerMultitouch' root. + */ + +/* Framebuffer is transmitted as JPEG. */ +#define MTFB_JPEG 1 +/* Framebuffer is transmitted as raw RGB565 bitmap. */ +#define MTFB_RGB565 2 +/* Framebuffer is transmitted as raw RGB888 bitmap. */ +#define MTFB_RGB888 3 + +/* Framebuffer update descriptor. + * This descriptor is used to collect properties of the updated framebuffer + * region. This descriptor is also sent to the MT emulation application on the + * device, so it can properly redraw its screen. + * + * NOTE: Application on the device side depends on that structure. Any changes + * made here must be reflected in the app too. Application location is at + * 'sdk/apps/SdkController/SdkControllerMultitouch' root. + */ +typedef struct MTFrameHeader { + /* Size of the header. Must be always sizeof(MTFrameHeader). */ + int header_size; + /* Display width */ + int disp_width; + /* Display height */ + int disp_height; + /* x, y, w, and h define framebuffer region that has been updated. */ + int x; + int y; + int w; + int h; + /* Bytes per line in the framebufer. */ + int bpl; + /* Bytes per pixel in the framebufer. */ + int bpp; + /* Defines format in which framebuffer is transmitted to the device. */ + int format; +} MTFrameHeader; + +/* Declares multi-touch port descriptor. */ +typedef struct AndroidMTSPort AndroidMTSPort; + +/* Creates multi-touch port, and connects it to the device. + * Param: + * opaque - An opaque pointer that is passed back to the callback routines. + * Return: + * Initialized device descriptor on success, or NULL on failure. If failure is + * returned from this routine, 'errno' indicates the reason for failure. If this + * routine successeds, a connection is established with the sensor reading + * application on the device. + */ +extern AndroidMTSPort* mts_port_create(void* opaque); + +/* Disconnects from the multi-touch port, and destroys the descriptor. */ +extern void mts_port_destroy(AndroidMTSPort* amtp); + +/* Sends framebuffer update to the multi-touch emulation application, running on + * the android device. + * Param: + * mtsp - Android multi-touch port instance returned from mts_port_create. + * fmt - Framebuffer update descriptor. + * fb - Beginning of the framebuffer. + * cb - Callback to invoke when update has been transferred to the MT-emulating + * application on the device. + * cb_opaque - An opaque parameter to pass back to the 'cb' callback. + * ydir - Indicates direction in which lines are arranged in the framebuffer. If + * this value is negative, lines are arranged in bottom-up format (i.e. the + * bottom line is at the beginning of the buffer). + * Return: + * 0 on success, or != 0 on failure. + */ +extern int mts_port_send_frame(AndroidMTSPort* mtsp, + MTFrameHeader* fmt, + const uint8_t* fb, + on_sdkctl_direct_cb cb, + void* cb_opaque, + int ydir); + +#endif /* ANDROID_ANDROID_MULTITOUCH_PORT_H_ */ diff --git a/android/multitouch-screen.c b/android/multitouch-screen.c new file mode 100644 index 0000000..59d4d75 --- /dev/null +++ b/android/multitouch-screen.c @@ -0,0 +1,468 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "qemu-common.h" +#include "user-events.h" +#include "android/display-core.h" +#include "android/hw-events.h" +#include "android/charmap.h" +#include "android/globals.h" /* for android_hw */ +#include "android/utils/misc.h" +#include "android/utils/debug.h" +#include "android/multitouch-screen.h" + +#define E(...) derror(__VA_ARGS__) +#define W(...) dwarning(__VA_ARGS__) +#define D(...) VERBOSE_PRINT(mtscreen,__VA_ARGS__) +#define D_ACTIVE VERBOSE_CHECK(mtscreen) + +#define TRACE_ON 1 + +#if TRACE_ON +#define T(...) VERBOSE_PRINT(mtscreen,__VA_ARGS__) +#else +#define T(...) +#endif + + +/* Maximum number of pointers, supported by multi-touch emulation. */ +#define MTS_POINTERS_NUM 10 +/* Signals that pointer is not tracked (or is "up"). */ +#define MTS_POINTER_UP -1 +/* Special tracking ID for a mouse pointer. */ +#define MTS_POINTER_MOUSE -2 + +/* Describes state of a multi-touch pointer */ +typedef struct MTSPointerState { + /* Tracking ID assigned to the pointer by an app emulating multi-touch. */ + int tracking_id; + /* X - coordinate of the tracked pointer. */ + int x; + /* Y - coordinate of the tracked pointer. */ + int y; + /* Current pressure value. */ + int pressure; +} MTSPointerState; + +/* Describes state of an emulated multi-touch screen. */ +typedef struct MTSState { + /* Multi-touch port connected to the device. */ + AndroidMTSPort* mtsp; + /* Emulator's display state. */ + DisplayState* ds; + /* Number of tracked pointers. */ + int tracked_ptr_num; + /* Index in the 'tracked_pointers' array of the last pointer for which + * ABS_MT_SLOT was sent. -1 indicates that no slot selection has been made + * yet. */ + int current_slot; + /* Accumulator for ABS_TOUCH_MAJOR value. */ + int touch_major; + /* Array of multi-touch pointers. */ + MTSPointerState tracked_pointers[MTS_POINTERS_NUM]; + /* Header collecting framebuffer information and updates. */ + MTFrameHeader fb_header; + /* Boolean value indicating if framebuffer updates are currently being + * transferred to the application running on the device. */ + int fb_transfer_in_progress; + /* Indicates direction in which lines are arranged in the framebuffer. If + * this value is negative, lines are arranged in bottom-up format (i.e. the + * bottom line is at the beginning of the buffer). */ + int ydir; + /* Current framebuffer pointer. */ + uint8_t* current_fb; +} MTSState; + +/* Default multi-touch screen descriptor */ +static MTSState _MTSState; + +/* Pushes event to the event device. */ +static void +_push_event(int type, int code, int value) +{ + user_event_generic(type, code, value); +} + +/* Gets an index in the MTS's tracking pointers array MTS for the given + * tracking id. + * Return: + * Index of a matching entry in the MTS's tracking pointers array, or -1 if + * matching entry was not found. + */ +static int +_mtsstate_get_pointer_index(const MTSState* mts_state, int tracking_id) +{ + int index; + for (index = 0; index < MTS_POINTERS_NUM; index++) { + if (mts_state->tracked_pointers[index].tracking_id == tracking_id) { + return index; + } + } + return -1; +} + +/* Gets an index of the first untracking pointer in the MTS's tracking pointers + * array. + * Return: + * An index of the first untracking pointer, or -1 if all pointers are tracked. + */ +static int +_mtsstate_get_available_pointer_index(const MTSState* mts_state) +{ + return _mtsstate_get_pointer_index(mts_state, MTS_POINTER_UP); +} + +/* Handles a "pointer down" event + * Param: + * mts_state - MTS state descriptor. + * tracking_id - Tracking ID of the "downed" pointer. + * x, y - "Downed" pointer coordinates, + * pressure - Pressure value for the pointer. + */ +static void +_mts_pointer_down(MTSState* mts_state, int tracking_id, int x, int y, int pressure) +{ + /* Get first available slot for the new pointer. */ + const int slot_index = _mtsstate_get_available_pointer_index(mts_state); + + /* Make sure there is a place for the pointer. */ + if (slot_index >= 0) { + /* Initialize pointer's entry. */ + mts_state->tracked_ptr_num++; + mts_state->tracked_pointers[slot_index].tracking_id = tracking_id; + mts_state->tracked_pointers[slot_index].x = x; + mts_state->tracked_pointers[slot_index].y = y; + mts_state->tracked_pointers[slot_index].pressure = pressure; + + /* Send events indicating a "pointer down" to the EventHub */ + /* Make sure that correct slot is selected. */ + if (slot_index != mts_state->current_slot) { + _push_event(EV_ABS, ABS_MT_SLOT, slot_index); + } + _push_event(EV_ABS, ABS_MT_TRACKING_ID, slot_index); + _push_event(EV_ABS, ABS_MT_TOUCH_MAJOR, ++mts_state->touch_major); + _push_event(EV_ABS, ABS_MT_PRESSURE, pressure); + _push_event(EV_ABS, ABS_MT_POSITION_X, x); + _push_event(EV_ABS, ABS_MT_POSITION_Y, y); + _push_event(EV_SYN, SYN_REPORT, 0); + mts_state->current_slot = slot_index; + } else { + D("MTS pointer count is exceeded."); + return; + } +} + +/* Handles a "pointer up" event + * Param: + * mts_state - MTS state descriptor. + * slot_index - Pointer's index in the MTS's array of tracked pointers. + */ +static void +_mts_pointer_up(MTSState* mts_state, int slot_index) +{ + /* Make sure that correct slot is selected. */ + if (slot_index != mts_state->current_slot) { + _push_event(EV_ABS, ABS_MT_SLOT, slot_index); + } + + /* Send event indicating "pointer up" to the EventHub. */ + _push_event(EV_ABS, ABS_MT_TRACKING_ID, -1); + _push_event(EV_SYN, SYN_REPORT, 0); + + /* Update MTS descriptor, removing the tracked pointer. */ + mts_state->tracked_pointers[slot_index].tracking_id = MTS_POINTER_UP; + mts_state->tracked_pointers[slot_index].x = 0; + mts_state->tracked_pointers[slot_index].y = 0; + mts_state->tracked_pointers[slot_index].pressure = 0; + + /* Since current slot is no longer tracked, make sure we will do a "select" + * next time we send events to the EventHub. */ + mts_state->current_slot = -1; + mts_state->tracked_ptr_num--; + assert(mts_state->tracked_ptr_num >= 0); +} + +/* Handles a "pointer move" event + * Param: + * mts_state - MTS state descriptor. + * slot_index - Pointer's index in the MTS's array of tracked pointers. + * x, y - New pointer coordinates, + * pressure - Pressure value for the pointer. + */ +static void +_mts_pointer_move(MTSState* mts_state, int slot_index, int x, int y, int pressure) +{ + MTSPointerState* ptr_state = &mts_state->tracked_pointers[slot_index]; + + /* Make sure that coordinates have really changed. */ + if (ptr_state->x == x && ptr_state->y == y) { + /* Coordinates didn't change. Bail out. */ + return; + } + + /* Make sure that the right slot is selected. */ + if (slot_index != mts_state->current_slot) { + _push_event(EV_ABS, ABS_MT_SLOT, slot_index); + mts_state->current_slot = slot_index; + } + + /* Push the changes down. */ + if (ptr_state->pressure != pressure && pressure != 0) { + _push_event(EV_ABS, ABS_MT_PRESSURE, pressure); + ptr_state->pressure = pressure; + } + if (ptr_state->x != x) { + _push_event(EV_ABS, ABS_MT_POSITION_X, x); + ptr_state->x = x; + } + if (ptr_state->y != y) { + _push_event(EV_ABS, ABS_MT_POSITION_Y, y); + ptr_state->y = y; + } + _push_event(EV_SYN, SYN_REPORT, 0); +} + +/******************************************************************************** + * Multi-touch API + *******************************************************************************/ + +/* Multi-touch service initialization flag. */ +static int _is_mt_initialized = 0; + +/* Callback that is invoked when framebuffer update has been transmitted to the + * device. */ +static AsyncIOAction +_on_fb_sent(void* opaque, SDKCtlDirectPacket* packet, AsyncIOState status) +{ + MTSState* const mts_state = (MTSState*)opaque; + + if (status == ASIO_STATE_SUCCEEDED) { + /* Lets see if we have accumulated more changes while transmission has been + * in progress. */ + if (mts_state->fb_header.w && mts_state->fb_header.h) { + /* Send accumulated updates. */ + if (mts_port_send_frame(mts_state->mtsp, &mts_state->fb_header, + mts_state->current_fb, _on_fb_sent, mts_state, + mts_state->ydir)) { + mts_state->fb_transfer_in_progress = 0; + } + } else { + /* Framebuffer transfer is completed, and no more updates are pending. */ + mts_state->fb_transfer_in_progress = 0; + } + } + + return ASIO_ACTION_DONE; +} + +/* Common handler for framebuffer updates invoked by both, software, and OpenGLES + * renderers. + */ +static void +_mt_fb_common_update(MTSState* mts_state, int x, int y, int w, int h) +{ + if (mts_state->fb_header.w == 0 && mts_state->fb_header.h == 0) { + /* First update after previous one has been transmitted to the device. */ + mts_state->fb_header.x = x; + mts_state->fb_header.y = y; + mts_state->fb_header.w = w; + mts_state->fb_header.h = h; + } else { + /* + * Accumulate framebuffer changes in the header. + */ + + /* "right" and "bottom" coordinates of the current update. */ + int right = mts_state->fb_header.x + mts_state->fb_header.w; + int bottom = mts_state->fb_header.y + mts_state->fb_header.h; + + /* "right" and "bottom" coordinates of the new update. */ + const int new_right = x + w; + const int new_bottom = y + h; + + /* Accumulate changed rectangle coordinates in the header. */ + if (mts_state->fb_header.x > x) { + mts_state->fb_header.x = x; + } + if (mts_state->fb_header.y > y) { + mts_state->fb_header.y = y; + } + if (right < new_right) { + right = new_right; + } + if (bottom < new_bottom) { + bottom = new_bottom; + } + mts_state->fb_header.w = right - mts_state->fb_header.x; + mts_state->fb_header.h = bottom - mts_state->fb_header.y; + } + + /* We will send updates to the device only after previous transmission is + * completed. */ + if (!mts_state->fb_transfer_in_progress) { + mts_state->fb_transfer_in_progress = 1; + if (mts_port_send_frame(mts_state->mtsp, &mts_state->fb_header, + mts_state->current_fb, _on_fb_sent, mts_state, + mts_state->ydir)) { + mts_state->fb_transfer_in_progress = 0; + } + } +} + +/* A callback invoked on framebuffer updates by software renderer. + * Param: + * opaque - MTSState instance. + * x, y, w, h - Defines an updated rectangle inside the framebuffer. + */ +static void +_mt_fb_update(void* opaque, int x, int y, int w, int h) +{ + MTSState* const mts_state = (MTSState*)opaque; + const DisplaySurface* const surface = mts_state->ds->surface; + + T("Multi-touch: Software renderer framebuffer update: %d:%d -> %dx%d", + x, y, w, h); + + /* TODO: For sofware renderer general framebuffer properties can change on + * the fly. Find a callback that can catch that. For now, just copy FB + * properties over in every FB update. */ + mts_state->fb_header.bpp = surface->pf.bytes_per_pixel; + mts_state->fb_header.bpl = surface->linesize; + mts_state->fb_header.disp_width = surface->width; + mts_state->fb_header.disp_height = surface->height; + mts_state->current_fb = surface->data; + mts_state->ydir = 1; + + _mt_fb_common_update(mts_state, x, y, w, h); +} + +void +multitouch_opengles_fb_update(void* context, + int w, int h, int ydir, + int format, int type, + unsigned char* pixels) +{ + MTSState* const mts_state = &_MTSState; + + /* Make sure MT port is initialized. */ + if (!_is_mt_initialized) { + return; + } + + T("Multi-touch: openGLES framebuffer update: 0:0 -> %dx%d", w, h); + + /* GLES format is always RGBA8888 */ + mts_state->fb_header.bpp = 4; + mts_state->fb_header.bpl = 4 * w; + mts_state->fb_header.disp_width = w; + mts_state->fb_header.disp_height = h; + mts_state->current_fb = pixels; + mts_state->ydir = ydir; + + /* GLES emulator alwas update the entire framebuffer. */ + _mt_fb_common_update(mts_state, 0, 0, w, h); +} + +void +multitouch_init(AndroidMTSPort* mtsp) +{ + if (!_is_mt_initialized) { + MTSState* const mts_state = &_MTSState; + DisplayState* const ds = get_displaystate(); + DisplayUpdateListener* dul; + int index; + + /* + * Initialize the descriptor. + */ + + memset(mts_state, 0, sizeof(MTSState)); + mts_state->tracked_ptr_num = 0; + mts_state->current_slot = -1; + for (index = 0; index < MTS_POINTERS_NUM; index++) { + mts_state->tracked_pointers[index].tracking_id = MTS_POINTER_UP; + } + mts_state->mtsp = mtsp; + mts_state->fb_header.header_size = sizeof(MTFrameHeader); + mts_state->fb_transfer_in_progress = 0; + + /* + * Set framebuffer update listener. + */ + + ANEW0(dul); + dul->opaque = &_MTSState; + dul->dpy_update = _mt_fb_update; + + /* Initialize framebuffer information in the screen descriptor. */ + mts_state->ds = ds; + mts_state->fb_header.disp_width = ds->surface->width; + mts_state->fb_header.disp_height = ds->surface->height; + mts_state->fb_header.x = mts_state->fb_header.y = 0; + mts_state->fb_header.w = mts_state->fb_header.h = 0; + mts_state->fb_header.bpp = ds->surface->pf.bytes_per_pixel; + mts_state->fb_header.bpl = ds->surface->linesize; + mts_state->fb_transfer_in_progress = 0; + + register_displayupdatelistener(ds, dul); + + _is_mt_initialized = 1; + } +} + +void +multitouch_update_pointer(MTESource source, + int tracking_id, + int x, + int y, + int pressure) +{ + MTSState* const mts_state = &_MTSState; + + /* Assign a fixed tracking ID to the mouse pointer. */ + if (source == MTES_MOUSE) { + tracking_id = MTS_POINTER_MOUSE; + } + + /* Find the tracked pointer for the tracking ID. */ + const int slot_index = _mtsstate_get_pointer_index(mts_state, tracking_id); + if (slot_index < 0) { + /* This is the first time the pointer is seen. Must be "pressed", + * otherwise it's "hoovering", which we don't support yet. */ + if (pressure == 0) { + if (tracking_id != MTS_POINTER_MOUSE) { + D("Unexpected MTS pointer update for tracking id: %d", + tracking_id); + } + return; + } + + /* This is a "pointer down" event */ + _mts_pointer_down(mts_state, tracking_id, x, y, pressure); + } else if (pressure == 0) { + /* This is a "pointer up" event */ + _mts_pointer_up(mts_state, slot_index); + } else { + /* This is a "pointer move" event */ + _mts_pointer_move(mts_state, slot_index, x, y, pressure); + } +} + +int +multitouch_get_max_slot() +{ + return MTS_POINTERS_NUM - 1; +} diff --git a/android/multitouch-screen.h b/android/multitouch-screen.h new file mode 100644 index 0000000..95ae86a --- /dev/null +++ b/android/multitouch-screen.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ANDROID_MULTITOUCH_SCREEN_H_ +#define ANDROID_MULTITOUCH_SCREEN_H_ + +#include "android/sdk-controller-socket.h" +#include "android/multitouch-port.h" + +/* + * Encapsulates functionality of multi-touch screen. Main task of this component + * is to report touch events to the emulated system via event device (see + * hw/goldfish_events_device.c) The source of touch events can be a mouse, or an + * actual android device that is used for multi-touch emulation. Note that since + * we need to simultaneousely support a mouse and a device as event source, we + * need to know which one has sent us a touch event. This is important for proper + * tracking of pointer IDs when multitouch is in play. + */ + +/* Defines a source of multi-touch event. This is used to properly track + * pointer IDs. + */ +typedef enum MTESource { + /* The event is associated with a mouse. */ + MTES_MOUSE, + /* The event is associated with an actual android device. */ + MTES_DEVICE, +} MTESource; + +/* Initializes MTSState instance. + * Param: + * mtsp - Instance of the multi-touch port connected to the device. + */ +extern void multitouch_init(AndroidMTSPort* mtsp); + +/* Handles a MT pointer event. + * Param: + * source - Identifies the source of the event (mouse or a device). + * tracking_id - Tracking ID of the pointer. + * x, y - Pointer coordinates, + * pressure - Pressure value for the pointer. + */ +extern void multitouch_update_pointer(MTESource source, + int tracking_id, + int x, + int y, + int pressure); + +/* Gets maximum slot index available for the multi-touch emulation. */ +extern int multitouch_get_max_slot(); + +/* A callback set to monitor OpenGLES framebuffer updates. + * This callback is called by the renderer just before each new frame is + * displayed, providing a copy of the framebuffer contents. + * The callback will be called from one of the renderer's threads, so it may + * require synchronization on any data structures it modifies. The pixels buffer + * may be overwritten as soon as the callback returns. + * The pixels buffer is intentionally not const: the callback may modify the data + * without copying to another buffer if it wants, e.g. in-place RGBA to RGB + * conversion, or in-place y-inversion. + * Param: + * context The pointer optionally provided when the callback was + * registered. The client can use this to pass whatever + * information it wants to the callback. + * width, height Dimensions of the image, in pixels. Rows are tightly packed; + * there is no inter-row padding. + * ydir Indicates row order: 1 means top-to-bottom order, -1 means + * bottom-to-top order. + * format, type Format and type GL enums, as used in glTexImage2D() or + * glReadPixels(), describing the pixel format. + * pixels The framebuffer image. + * + * In the first implementation, ydir is always -1 (bottom to top), format and + * type are always GL_RGBA and GL_UNSIGNED_BYTE, and the width and height will + * always be the same as the ones passed to initOpenGLRenderer(). + */ +extern void multitouch_opengles_fb_update(void* context, + int width, + int height, + int ydir, + int format, + int type, + unsigned char* pixels); + +#endif /* ANDROID_MULTITOUCH_SCREEN_H_ */ diff --git a/android/opengles.c b/android/opengles.c index 4913d0c..521dc03 100644 --- a/android/opengles.c +++ b/android/opengles.c @@ -12,39 +12,45 @@ #include "config-host.h" #include "android/opengles.h" + +/* Declared in "android/globals.h" */ +int android_gles_fast_pipes = 1; + +#if CONFIG_ANDROID_OPENGLES + #include "android/globals.h" #include <android/utils/debug.h> #include <android/utils/path.h> #include <android/utils/bufprint.h> #include <android/utils/dll.h> + +#define RENDER_API_NO_PROTOTYPES 1 +#include <libOpenglRender/render_api.h> + #include <stdio.h> #include <stdlib.h> #define D(...) VERBOSE_PRINT(init,__VA_ARGS__) #define DD(...) VERBOSE_PRINT(gles,__VA_ARGS__) -/* Declared in "android/globals.h" */ -int android_gles_fast_pipes = 1; - /* Name of the GLES rendering library we're going to use */ +#if HOST_LONG_BITS == 32 #define RENDERER_LIB_NAME "libOpenglRender" +#elif HOST_LONG_BITS == 64 +#define RENDERER_LIB_NAME "lib64OpenglRender" +#else +#error Unknown HOST_LONG_BITS +#endif -/* These definitions *must* match those under: - * development/tools/emulator/opengl/host/include/libOpenglRender/render_api.h - */ #define DYNLINK_FUNCTIONS \ - DYNLINK_FUNC(int,initLibrary,(void),(),return) \ - DYNLINK_FUNC(int,setStreamMode,(int a),(a),return) \ - DYNLINK_FUNC(int,initOpenGLRenderer,(int width, int height, int port),(width,height,port),return) \ - DYNLINK_FUNC(int,createOpenGLSubwindow,(void* window, int x, int y, int width, int height, float zRot),(window,x,y,width,height,zRot),return)\ - DYNLINK_FUNC(int,destroyOpenGLSubwindow,(void),(),return)\ - DYNLINK_FUNC(void,repaintOpenGLDisplay,(void),(),)\ - DYNLINK_FUNC(void,stopOpenGLRenderer,(void),(),) - -#define STREAM_MODE_DEFAULT 0 -#define STREAM_MODE_TCP 1 -#define STREAM_MODE_UNIX 2 -#define STREAM_MODE_PIPE 3 + DYNLINK_FUNC(initLibrary) \ + DYNLINK_FUNC(setStreamMode) \ + DYNLINK_FUNC(initOpenGLRenderer) \ + DYNLINK_FUNC(getHardwareStrings) \ + DYNLINK_FUNC(createOpenGLSubwindow) \ + DYNLINK_FUNC(destroyOpenGLSubwindow) \ + DYNLINK_FUNC(repaintOpenGLDisplay) \ + DYNLINK_FUNC(stopOpenGLRenderer) #ifndef CONFIG_STANDALONE_UI /* Defined in android/hw-pipe-net.c */ @@ -53,15 +59,10 @@ extern int android_init_opengles_pipes(void); static ADynamicLibrary* rendererLib; -/* Define the pointers and the wrapper functions to call them */ -#define DYNLINK_FUNC(result,name,sig,params,ret) \ - static result (*_ptr_##name) sig; \ - static result name sig { \ - ret (*_ptr_##name) params ; \ - } - +/* Define the function pointers */ +#define DYNLINK_FUNC(name) \ + static name##Fn name = NULL; DYNLINK_FUNCTIONS - #undef DYNLINK_FUNC static int @@ -69,10 +70,11 @@ initOpenglesEmulationFuncs(ADynamicLibrary* rendererLib) { void* symbol; char* error; -#define DYNLINK_FUNC(result,name,sig,params,ret) \ - symbol = adynamicLibrary_findSymbol( rendererLib, #name, &error ); \ + +#define DYNLINK_FUNC(name) \ + symbol = adynamicLibrary_findSymbol(rendererLib, #name, &error); \ if (symbol != NULL) { \ - _ptr_##name = symbol; \ + name = symbol; \ } else { \ derror("GLES emulation: Could not find required symbol (%s): %s", #name, error); \ free(error); \ @@ -80,6 +82,7 @@ initOpenglesEmulationFuncs(ADynamicLibrary* rendererLib) } DYNLINK_FUNCTIONS #undef DYNLINK_FUNC + return 0; } @@ -120,10 +123,10 @@ android_initOpenglesEmulation(void) /* XXX: NEED Win32 pipe implementation */ setStreamMode(STREAM_MODE_TCP); #else - setStreamMode(STREAM_MODE_UNIX); + setStreamMode(STREAM_MODE_UNIX); #endif } else { - setStreamMode(STREAM_MODE_TCP); + setStreamMode(STREAM_MODE_TCP); } return 0; @@ -135,20 +138,76 @@ BAD_EXIT: } int -android_startOpenglesRenderer(int width, int height) +android_startOpenglesRenderer(int width, int height, OnPostFunc onPost, void* onPostContext) { if (!rendererLib) { D("Can't start OpenGLES renderer without support libraries"); return -1; } - if (initOpenGLRenderer(width, height,ANDROID_OPENGLES_BASE_PORT) != 0) { + if (!initOpenGLRenderer(width, height, ANDROID_OPENGLES_BASE_PORT, onPost, onPostContext)) { D("Can't start OpenGLES renderer?"); return -1; } return 0; } +static void strncpy_safe(char* dst, const char* src, size_t n) +{ + strncpy(dst, src, n); + dst[n-1] = '\0'; +} + +static void extractBaseString(char* dst, const char* src, size_t dstSize) +{ + size_t len = strlen(src); + const char* begin = strchr(src, '('); + const char* end = strrchr(src, ')'); + + if (!begin || !end) { + strncpy_safe(dst, src, dstSize); + return; + } + begin += 1; + + // "foo (bar)" + // ^ ^ + // b e + // = 5 8 + // substring with NUL-terminator is end-begin+1 bytes + if (end - begin + 1 > dstSize) { + end = begin + dstSize - 1; + } + + strncpy_safe(dst, begin, end - begin + 1); +} + +void +android_getOpenglesHardwareStrings(char* vendor, size_t vendorBufSize, + char* renderer, size_t rendererBufSize, + char* version, size_t versionBufSize) +{ + const char *vendorSrc, *rendererSrc, *versionSrc; + + getHardwareStrings(&vendorSrc, &rendererSrc, &versionSrc); + if (!vendorSrc) vendorSrc = ""; + if (!rendererSrc) rendererSrc = ""; + if (!versionSrc) versionSrc = ""; + + /* Special case for the default ES to GL translators: extract the strings + * of the underlying OpenGL implementation. */ + if (strncmp(vendorSrc, "Google", 6) == 0 && + strncmp(rendererSrc, "Android Emulator OpenGL ES Translator", 37) == 0) { + extractBaseString(vendor, vendorSrc, vendorBufSize); + extractBaseString(renderer, rendererSrc, rendererBufSize); + extractBaseString(version, versionSrc, versionBufSize); + } else { + strncpy_safe(vendor, vendorSrc, vendorBufSize); + strncpy_safe(renderer, rendererSrc, rendererBufSize); + strncpy_safe(version, versionSrc, versionBufSize); + } +} + void android_stopOpenglesRenderer(void) { @@ -161,7 +220,8 @@ int android_showOpenglesWindow(void* window, int x, int y, int width, int height, float rotation) { if (rendererLib) { - return createOpenGLSubwindow(window, x, y, width, height, rotation); + int success = createOpenGLSubwindow((FBNativeWindowType)window, x, y, width, height, rotation); + return success ? 0 : -1; } else { return -1; } @@ -171,7 +231,8 @@ int android_hideOpenglesWindow(void) { if (rendererLib) { - return destroyOpenGLSubwindow(); + int success = destroyOpenGLSubwindow(); + return success ? 0 : -1; } else { return -1; } @@ -199,3 +260,38 @@ android_gles_unix_path(char* buff, size_t buffsize, int port) } p = bufprint(p, end, "qemu-gles-%d", port); } + +#else // CONFIG_ANDROID_OPENGLES + +int android_initOpenglesEmulation(void) +{ + return -1; +} + +int android_startOpenglesRenderer(int width, int height, OnPostFunc onPost, void* onPostContext) +{ + return -1; +} + +void android_stopOpenglesRenderer(void) +{} + +int android_showOpenglesWindow(void* window, int x, int y, int width, int height, float rotation) +{ + return -1; +} + +int android_hideOpenglesWindow(void) +{ + return -1; +} + +void android_redrawOpenglesWindow(void) +{} + +void android_gles_unix_path(char* buff, size_t buffsize, int port) +{ + buff[0] = '\0'; +} + +#endif // !CONFIG_ANDROID_OPENGLES diff --git a/android/opengles.h b/android/opengles.h index 2202e92..4e83c02 100644 --- a/android/opengles.h +++ b/android/opengles.h @@ -16,6 +16,10 @@ #define ANDROID_OPENGLES_BASE_PORT 22468 +/* See the description in render_api.h. */ +typedef void (*OnPostFunc)(void* context, int width, int height, int ydir, + int format, int type, unsigned char* pixels); + /* Call this function to initialize the hardware opengles emulation. * This function will abort if we can't find the corresponding host * libraries through dlopen() or equivalent. @@ -23,9 +27,23 @@ int android_initOpenglesEmulation(void); /* Tries to start the renderer process. Returns 0 on success, -1 on error. - * At the moment, this must be done before the VM starts. + * At the moment, this must be done before the VM starts. The onPost callback + * may be NULL. + */ +int android_startOpenglesRenderer(int width, int height, + OnPostFunc onPost, void* onPostContext); + +/* Retrieve the Vendor/Renderer/Version strings describing the underlying GL + * implementation. The call only works while the renderer is started. + * + * Each string is copied into the corresponding buffer. If the original string + * (including NUL terminator) is more than xxBufSize bytes, it will be + * truncated. In all cases, including failure, the buffer will be NUL- + * terminated when this function returns. */ -int android_startOpenglesRenderer(int width, int height); +void android_getOpenglesHardwareStrings(char* vendor, size_t vendorBufSize, + char* renderer, size_t rendererBufSize, + char* version, size_t versionBufSize); int android_showOpenglesWindow(void* window, int x, int y, int width, int height, float rotation); diff --git a/android/qemu-setup.c b/android/qemu-setup.c index 181c95b..8b8f0b0 100644 --- a/android/qemu-setup.c +++ b/android/qemu-setup.c @@ -47,6 +47,11 @@ char* op_http_proxy = NULL; /* Base port for the emulated system. */ int android_base_port; +/* Strings describing the host system's OpenGL implementation */ +char android_gl_vendor[ANDROID_GLSTRING_BUF_SIZE]; +char android_gl_renderer[ANDROID_GLSTRING_BUF_SIZE]; +char android_gl_version[ANDROID_GLSTRING_BUF_SIZE]; + /*** APPLICATION DIRECTORY *** Where are we ? ***/ @@ -483,6 +488,14 @@ void android_emulation_setup( void ) char tmp[PATH_MAX]; const char* appdir = get_app_dir(); + const size_t ARGSLEN = + PATH_MAX + // max ping program path + 10 + // max VERSION_STRING length + 3*ANDROID_GLSTRING_BUF_SIZE + // max GL string lengths + 29 + // static args characters + 1; // NUL terminator + char args[ARGSLEN]; + if (snprintf( tmp, PATH_MAX, "%s%s%s", appdir, PATH_SEP, _ANDROID_PING_PROGRAM ) >= PATH_MAX) { dprint( "Application directory too long: %s", appdir); @@ -507,10 +520,12 @@ void android_emulation_setup( void ) if (!comspec) comspec = "cmd.exe"; // Run - char args[PATH_MAX + 30]; - if (snprintf( args, PATH_MAX, "/C \"%s\" ping emulator " VERSION_STRING, - tmp) >= PATH_MAX ) { - D( "DDMS path too long: %s", tmp); + if (snprintf(args, ARGSLEN, + "/C \"%s\" ping emulator " VERSION_STRING " \"%s\" \"%s\" \"%s\"", + tmp, android_gl_vendor, android_gl_renderer, android_gl_version) + >= ARGSLEN) + { + D( "DDMS command line too long: %s", args); return; } @@ -540,13 +555,17 @@ void android_emulation_setup( void ) int fd = open("/dev/null", O_WRONLY); dup2(fd, 1); dup2(fd, 2); - execl( tmp, _ANDROID_PING_PROGRAM, "ping", "emulator", VERSION_STRING, NULL ); + execl( tmp, _ANDROID_PING_PROGRAM, "ping", "emulator", VERSION_STRING, + android_gl_vendor, android_gl_renderer, android_gl_version, + NULL ); } END_NOSIGALRM /* don't do anything in the parent or in case of error */ - strncat( tmp, " ping emulator " VERSION_STRING, PATH_MAX - strlen(tmp) ); - D( "ping command: %s", tmp ); + snprintf(args, ARGSLEN, + "%s ping emulator " VERSION_STRING " \"%s\" \"%s\" \"%s\"", + tmp, android_gl_vendor, android_gl_renderer, android_gl_version); + D( "ping command: %s", args ); #endif } } diff --git a/android/qemulator.c b/android/qemulator.c index 35587ff..eb3b59e 100644 --- a/android/qemulator.c +++ b/android/qemulator.c @@ -81,7 +81,8 @@ qemulator_setup( QEmulator* emulator ) qemulator_set_title(emulator); - skin_window_enable_touch ( emulator->window, android_hw->hw_touchScreen != 0 ); + skin_window_enable_touch ( emulator->window, + !androidHwConfig_isScreenNoTouch(android_hw)); skin_window_enable_dpad ( emulator->window, android_hw->hw_dPad != 0 ); skin_window_enable_qwerty( emulator->window, android_hw->hw_keyboard != 0 ); skin_window_enable_trackball( emulator->window, android_hw->hw_trackBall != 0 ); diff --git a/android/sdk-controller-socket.c b/android/sdk-controller-socket.c new file mode 100644 index 0000000..8b0d813 --- /dev/null +++ b/android/sdk-controller-socket.c @@ -0,0 +1,2201 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Encapsulates exchange protocol between the emulator, and an Android device + * that is connected to the host via USB. The communication is established over + * a TCP port forwarding, enabled by ADB. + */ + +#include "android/utils/debug.h" +#include "android/async-socket-connector.h" +#include "android/async-socket.h" +#include "android/sdk-controller-socket.h" +#include "utils/panic.h" +#include "iolooper.h" + +#define E(...) derror(__VA_ARGS__) +#define W(...) dwarning(__VA_ARGS__) +#define D(...) VERBOSE_PRINT(sdkctlsocket,__VA_ARGS__) +#define D_ACTIVE VERBOSE_CHECK(sdkctlsocket) + +#define TRACE_ON 0 + +#if TRACE_ON +#define T(...) VERBOSE_PRINT(sdkctlsocket,__VA_ARGS__) +#else +#define T(...) +#endif + +/* Recycling memory descriptor. */ +typedef struct SDKCtlRecycled SDKCtlRecycled; +struct SDKCtlRecycled { + union { + /* Next recycled descriptor (while listed in recycler). */ + SDKCtlRecycled* next; + /* Allocated memory size (while outside of the recycler). */ + uint32_t size; + }; +}; + +/* + * Types of the data packets sent via SDK controller socket. + */ + +/* The packet is a message. */ +#define SDKCTL_PACKET_MESSAGE 1 +/* The packet is a query. */ +#define SDKCTL_PACKET_QUERY 2 +/* The packet is a response to a query. */ +#define SDKCTL_PACKET_QUERY_RESPONSE 3 + +/* + * Types of intenal port messages sent via SDK controller socket. + */ + +/* Port is connected. + * This message is sent by SDK controller when the service connects a socket with + * a port that provides requested emulation functionality. + */ +#define SDKCTL_MSG_PORT_CONNECTED -1 +/* Port is disconnected. + * This message is sent by SDK controller when a port that provides requested + * emulation functionality disconnects from the socket. + */ +#define SDKCTL_MSG_PORT_DISCONNECTED -2 +/* Port is enabled. + * This message is sent by SDK controller when a port that provides requested + * emulation functionality is ready to do the emulation. + */ +#define SDKCTL_MSG_PORT_ENABLED -3 +/* Port is disabled. + * This message is sent by SDK controller when a port that provides requested + * emulation functionality is not ready to do the emulation. + */ +#define SDKCTL_MSG_PORT_DISABLED -4 + +/* + * Types of internal queries sent via SDK controller socket. + */ + +/* Handshake query. + * This query is sent to SDK controller service as part of the connection + * protocol implementation. + */ +#define SDKCTL_QUERY_HANDSHAKE -1 + +/******************************************************************************** + * SDKCtlPacket declarations + *******************************************************************************/ + +/* Packet signature value ('SDKC'). */ +static const int _sdkctl_packet_sig = 0x53444B43; + +/* Data packet descriptor. + * + * All packets, sent and received via SDK controller socket begin with this + * header, with packet data immediately following this header. + */ +typedef struct SDKCtlPacketHeader { + /* Signature. */ + int signature; + /* Total size of the data to transfer with this packet, including this + * header. The transferring data should immediatelly follow this header. */ + int size; + /* Encodes packet type. See SDKCTL_PACKET_XXX for the list of packet types + * used by SDK controller. */ + int type; +} SDKCtlPacketHeader; + +/* Packet descriptor, allocated by this API for data packets to be sent to SDK + * controller. + * + * When packet descriptors are allocated by this API, they are allocated large + * enough to contain this header, and packet data to send to the service, + * immediately following this descriptor. + */ +typedef struct SDKCtlPacket { + /* Supports recycling. Don't put anything in front: recycler expects this + * to be the first field in recyclable descriptor. */ + SDKCtlRecycled recycling; + + /* SDK controller socket that transmits this packet. */ + SDKCtlSocket* sdkctl; + /* Number of outstanding references to the packet. */ + int ref_count; + + /* Common packet header. Packet data immediately follows this header, so it + * must be the last field in SDKCtlPacket descriptor. */ + SDKCtlPacketHeader header; +} SDKCtlPacket; + +/******************************************************************************** + * SDKCtlDirectPacket declarations + *******************************************************************************/ + +/* Direct packet descriptor, allocated by this API for direct data packets to be + * sent to SDK controller service on the device. + * + * Direct packet (unlike SDKCtlPacket) don't contain data buffer, but rather + * reference data allocated by the client. This is useful when client sends large + * amount of data (such as framebuffer updates sent my multi-touch port), and + * regular packet descriptors for such large transfer cannot be obtained from the + * recycler. + */ +struct SDKCtlDirectPacket { + /* Supports recycling. Don't put anything in front: recycler expects this + * to be the first field in recyclable descriptor. */ + SDKCtlRecycled recycling; + + /* SDKCtlSocket that owns this packet. */ + SDKCtlSocket* sdkctl; + /* Packet to send. */ + SDKCtlPacketHeader* packet; + /* Callback to invoke on packet transmission events. */ + on_sdkctl_direct_cb on_sent; + /* An opaque pointer to pass to on_sent callback. */ + void* on_sent_opaque; + /* Number of outstanding references to the packet. */ + int ref_count; +}; + +/******************************************************************************** + * SDKCtlQuery declarations + *******************************************************************************/ + +/* Query packet descriptor. + * + * All queries, sent and received via SDK controller socket begin with this + * header, with query data immediately following this header. + */ +typedef struct SDKCtlQueryHeader { + /* Data packet header for this query. */ + SDKCtlPacketHeader packet; + /* A unique query identifier. This ID is used to track the query in the + * asynchronous environment in whcih SDK controller socket operates. */ + int query_id; + /* Query type. */ + int query_type; +} SDKCtlQueryHeader; + +/* Query descriptor, allocated by this API for queries to be sent to SDK + * controller service on the device. + * + * When query descriptors are allocated by this API, they are allocated large + * enough to contain this header, and query data to send to the service, + * immediately following this descriptor. + */ +struct SDKCtlQuery { + /* Supports recycling. Don't put anything in front: recycler expects this + * to be the first field in recyclable descriptor. */ + SDKCtlRecycled recycling; + + /* Next query in the list of active queries. */ + SDKCtlQuery* next; + /* A timer to run time out on this query after it has been sent. */ + LoopTimer timer[1]; + /* Absolute time for this query's deadline. This is the value that query's + * timer is set to after query has been transmitted to the service. */ + Duration deadline; + /* SDK controller socket that owns the query. */ + SDKCtlSocket* sdkctl; + /* A callback to invoke on query state changes. */ + on_sdkctl_query_cb query_cb; + /* An opaque pointer associated with this query. */ + void* query_opaque; + /* Points to an address of a buffer where to save query response. */ + void** response_buffer; + /* Points to a variable containing size of the response buffer (on the way + * in), or actual query response size (when query is completed). */ + uint32_t* response_size; + /* Internal response buffer, allocated if query creator didn't provide its + * own. This field is valid only if response_buffer field is NULL, or is + * pointing to this field. */ + void* internal_resp_buffer; + /* Internal response buffer size used if query creator didn't provide its + * own. This field is valid only if response_size field is NULL, or is + * pointing to this field. */ + uint32_t internal_resp_size; + /* Number of outstanding references to the query. */ + int ref_count; + + /* Common query header. Query data immediately follows this header, so it + * must be last field in SDKCtlQuery descriptor. */ + SDKCtlQueryHeader header; +}; + +/* Query reply descriptor. + * + * All replies to a query, sent and received via SDK controller socket begin with + * this header, with query reply data immediately following this header. + */ +typedef struct SDKCtlQueryReplyHeader { + /* Data packet header for this reply. */ + SDKCtlPacketHeader packet; + + /* An identifier for the query that is addressed with this reply. */ + int query_id; +} SDKCtlQueryReplyHeader; + +/******************************************************************************** + * SDKCtlMessage declarations + *******************************************************************************/ + +/* Message packet descriptor. + * + * All messages, sent and received via SDK controller socket begin with this + * header, with message data immediately following this header. + */ +typedef struct SDKCtlMessageHeader { + /* Data packet header for this query. */ + SDKCtlPacketHeader packet; + /* Message type. */ + int msg_type; +} SDKCtlMessageHeader; + +/* Message packet descriptor. + * + * All messages, sent and received via SDK controller socket begin with this + * header, with message data immediately following this header. + */ +struct SDKCtlMessage { + /* Data packet descriptor for this message. */ + SDKCtlPacket packet; + /* Message type. */ + int msg_type; +}; + +/******************************************************************************** + * SDK Control Socket declarations + *******************************************************************************/ + +/* Enumerates SDKCtlSocket states. */ +typedef enum SDKCtlSocketState { + /* Socket is disconnected from SDK controller. */ + SDKCTL_SOCKET_DISCONNECTED, + /* Connection to SDK controller is in progress. */ + SDKCTL_SOCKET_CONNECTING, + /* Socket is connected to an SDK controller service. */ + SDKCTL_SOCKET_CONNECTED +} SDKCtlSocketState; + +/* Enumerates SDKCtlSocket I/O dispatcher states. */ +typedef enum SDKCtlIODispatcherState { + /* I/O dispatcher expects a packet header. */ + SDKCTL_IODISP_EXPECT_HEADER, + /* I/O dispatcher expects packet data. */ + SDKCTL_IODISP_EXPECT_DATA, + /* I/O dispatcher expects query response header. */ + SDKCTL_IODISP_EXPECT_QUERY_REPLY_HEADER, + /* I/O dispatcher expects query response data. */ + SDKCTL_IODISP_EXPECT_QUERY_REPLY_DATA, +} SDKCtlIODispatcherState; + +/* SDKCtlSocket I/O dispatcher descriptor. */ +typedef struct SDKCtlIODispatcher { + /* SDKCtlSocket instance for this dispatcher. */ + SDKCtlSocket* sdkctl; + /* Dispatcher state. */ + SDKCtlIODispatcherState state; + /* Unites all types of headers used in SDK controller data exchange. */ + union { + /* Common packet header. */ + SDKCtlPacketHeader packet_header; + /* Header for a query packet. */ + SDKCtlQueryHeader query_header; + /* Header for a message packet. */ + SDKCtlMessageHeader message_header; + /* Header for a query response packet. */ + SDKCtlQueryReplyHeader query_reply_header; + }; + /* Descriptor of a packet that is being received from SDK controller. */ + SDKCtlPacket* packet; + /* A query for which a reply is currently being received. */ + SDKCtlQuery* current_query; +} SDKCtlIODispatcher; + +/* SDK controller socket descriptor. */ +struct SDKCtlSocket { + /* SDK controller socket state */ + SDKCtlSocketState state; + /* SDK controller port status */ + SdkCtlPortStatus port_status; + /* I/O dispatcher for the socket. */ + SDKCtlIODispatcher io_dispatcher; + /* Asynchronous socket connected to SDK Controller on the device. */ + AsyncSocket* as; + /* Client callback that monitors this socket connection. */ + on_sdkctl_socket_connection_cb on_socket_connection; + /* Client callback that monitors SDK controller prt connection. */ + on_sdkctl_port_connection_cb on_port_connection; + /* A callback to invoke when a message is received from the SDK controller. */ + on_sdkctl_message_cb on_message; + /* An opaque pointer associated with this socket. */ + void* opaque; + /* Name of an SDK controller port this socket is connected to. */ + char* service_name; + /* I/O looper for timers. */ + Looper* looper; + /* Head of the active query list. */ + SDKCtlQuery* query_head; + /* Tail of the active query list. */ + SDKCtlQuery* query_tail; + /* Query ID generator that gets incremented for each new query. */ + int next_query_id; + /* Timeout before trying to reconnect after disconnection. */ + int reconnect_to; + /* Number of outstanding references to this descriptor. */ + int ref_count; + /* Head of the recycled memory */ + SDKCtlRecycled* recycler; + /* Recyclable block size. */ + uint32_t recycler_block_size; + /* Maximum number of blocks to recycle. */ + int recycler_max; + /* Number of blocs in the recycler. */ + int recycler_count; +}; + +/******************************************************************************** + * SDKCtlSocket recycling management + *******************************************************************************/ + +/* Gets a recycled block for a given SDKCtlSocket, or allocates new memory + * block. */ +static void* +_sdkctl_socket_alloc_recycler(SDKCtlSocket* sdkctl, uint32_t size) +{ + SDKCtlRecycled* block = NULL; + + if (sdkctl->recycler != NULL && size <= sdkctl->recycler_block_size) { + assert(sdkctl->recycler_count > 0); + /* There are blocks in the recycler, and requested size fits. */ + block = sdkctl->recycler; + sdkctl->recycler = block->next; + block->size = sdkctl->recycler_block_size; + sdkctl->recycler_count--; + } else if (size <= sdkctl->recycler_block_size) { + /* There are no blocks in the recycler, but requested size fits. Lets + * allocate block that we can later recycle. */ + block = malloc(sdkctl->recycler_block_size); + if (block == NULL) { + APANIC("SDKCtl %s: Unable to allocate %d bytes block.", + sdkctl->service_name, sdkctl->recycler_block_size); + } + block->size = sdkctl->recycler_block_size; + } else { + /* Requested size doesn't fit the recycler. */ + block = malloc(size); + if (block == NULL) { + APANIC("SDKCtl %s: Unable to allocate %d bytes block", + sdkctl->service_name, size); + } + block->size = size; + } + + return block; +} + +/* Recycles, or frees a block of memory for a given SDKCtlSocket. */ +static void +_sdkctl_socket_free_recycler(SDKCtlSocket* sdkctl, void* mem) +{ + SDKCtlRecycled* const block = (SDKCtlRecycled*)mem; + + if (block->size != sdkctl->recycler_block_size || + sdkctl->recycler_count == sdkctl->recycler_max) { + /* Recycler is full, or block cannot be recycled. Just free the memory. */ + free(mem); + } else { + /* Add that block to the recycler. */ + assert(sdkctl->recycler_count >= 0); + block->next = sdkctl->recycler; + sdkctl->recycler = block; + sdkctl->recycler_count++; + } +} + +/* Empties the recycler for a given SDKCtlSocket. */ +static void +_sdkctl_socket_empty_recycler(SDKCtlSocket* sdkctl) +{ + SDKCtlRecycled* block = sdkctl->recycler; + while (block != NULL) { + void* const to_free = block; + block = block->next; + free(to_free); + } + sdkctl->recycler = NULL; + sdkctl->recycler_count = 0; +} + +/******************************************************************************** + * SDKCtlSocket query list management + *******************************************************************************/ + +/* Adds a query to the list of active queries. + * Param: + * sdkctl - SDKCtlSocket instance for the query. + * query - Query to add to the list. + */ +static void +_sdkctl_socket_add_query(SDKCtlQuery* query) +{ + SDKCtlSocket* const sdkctl = query->sdkctl; + if (sdkctl->query_head == NULL) { + assert(sdkctl->query_tail == NULL); + sdkctl->query_head = sdkctl->query_tail = query; + } else { + sdkctl->query_tail->next = query; + sdkctl->query_tail = query; + } + + /* Keep the query referenced while it's in the list. */ + sdkctl_query_reference(query); +} + +/* Removes a query from the list of active queries. + * Param: + * query - Query to remove from the list of active queries. If query has been + * removed from the list, it will be dereferenced to offset the reference + * that wad made when the query has been added to the list. + * Return: + * Boolean: 1 if query has been removed, or 0 if query has not been found in the + * list of active queries. + */ +static int +_sdkctl_socket_remove_query(SDKCtlQuery* query) +{ + SDKCtlSocket* const sdkctl = query->sdkctl; + SDKCtlQuery* prev = NULL; + SDKCtlQuery* head = sdkctl->query_head; + + /* Quick check: the query could be currently handled by the dispatcher. */ + if (sdkctl->io_dispatcher.current_query == query) { + /* Release the query from dispatcher. */ + sdkctl->io_dispatcher.current_query = NULL; + sdkctl_query_release(query); + return 1; + } + + /* Remove query from the list. */ + while (head != NULL && query != head) { + prev = head; + head = head->next; + } + if (head == NULL) { + D("SDKCtl %s: Query %p is not found in the list.", + sdkctl->service_name, query); + return 0; + } + + if (prev == NULL) { + /* Query is at the head of the list. */ + assert(query == sdkctl->query_head); + sdkctl->query_head = query->next; + } else { + /* Query is in the middle / at the end of the list. */ + assert(query != sdkctl->query_head); + prev->next = query->next; + } + if (sdkctl->query_tail == query) { + /* Query is at the tail of the list. */ + assert(query->next == NULL); + sdkctl->query_tail = prev; + } + query->next = NULL; + + /* Release query that is now removed from the list. Note that query + * passed to this routine should hold an extra reference, owned by the + * caller. */ + sdkctl_query_release(query); + + return 1; +} + +/* Removes a query (based on query ID) from the list of active queries. + * Param: + * sdkctl - SDKCtlSocket instance that owns the query. + * query_id - Identifies the query to remove. + * Return: + * A query removed from the list of active queries, or NULL if query with the + * given ID has not been found in the list. Note that query returned from this + * routine still holds the reference made when the query has been added to the + * list. + */ +static SDKCtlQuery* +_sdkctl_socket_remove_query_id(SDKCtlSocket* sdkctl, int query_id) +{ + SDKCtlQuery* query = NULL; + SDKCtlQuery* prev = NULL; + SDKCtlQuery* head = sdkctl->query_head; + + /* Quick check: the query could be currently handled by dispatcher. */ + if (sdkctl->io_dispatcher.current_query != NULL && + sdkctl->io_dispatcher.current_query->header.query_id == query_id) { + /* Release the query from dispatcher. */ + query = sdkctl->io_dispatcher.current_query; + sdkctl->io_dispatcher.current_query = NULL; + return query; + } + + /* Remove query from the list. */ + while (head != NULL && head->header.query_id != query_id) { + prev = head; + head = head->next; + } + if (head == NULL) { + D("SDKCtl %s: Query ID %d is not found in the list.", + sdkctl->service_name, query_id); + return NULL; + } + + /* Query is found in the list. */ + query = head; + if (prev == NULL) { + /* Query is at the head of the list. */ + assert(query == sdkctl->query_head); + sdkctl->query_head = query->next; + } else { + /* Query is in the middle, or at the end of the list. */ + assert(query != sdkctl->query_head); + prev->next = query->next; + } + if (sdkctl->query_tail == query) { + /* Query is at the tail of the list. */ + assert(query->next == NULL); + sdkctl->query_tail = prev; + } + query->next = NULL; + + return query; +} + +/* Pulls the first query from the list of active queries. + * Param: + * sdkctl - SDKCtlSocket instance that owns the query. + * Return: + * A query removed from the head of the list of active queries, or NULL if query + * list is empty. + */ +static SDKCtlQuery* +_sdkctl_socket_pull_first_query(SDKCtlSocket* sdkctl) +{ + SDKCtlQuery* const query = sdkctl->query_head; + + if (query != NULL) { + sdkctl->query_head = query->next; + if (sdkctl->query_head == NULL) { + sdkctl->query_tail = NULL; + } + } + return query; +} + +/* Generates new query ID for the given SDKCtl. */ +static int +_sdkctl_socket_next_query_id(SDKCtlSocket* sdkctl) +{ + return ++sdkctl->next_query_id; +} + +/******************************************************************************** + * SDKCtlPacket implementation + *******************************************************************************/ + +/* Alocates a packet. */ +static SDKCtlPacket* +_sdkctl_packet_new(SDKCtlSocket* sdkctl, uint32_t size, int type) +{ + /* Allocate packet descriptor large enough to contain packet data. */ + SDKCtlPacket* const packet = + _sdkctl_socket_alloc_recycler(sdkctl, sizeof(SDKCtlPacket) + size); + + packet->sdkctl = sdkctl; + packet->ref_count = 1; + packet->header.signature = _sdkctl_packet_sig; + packet->header.size = size; + packet->header.type = type; + + /* Refence SDKCTlSocket that owns this packet. */ + sdkctl_socket_reference(sdkctl); + + T("SDKCtl %s: Packet %p of type %d is allocated for %d bytes transfer.", + sdkctl->service_name, packet, type, size); + + return packet; +} + +/* Frees a packet. */ +static void +_sdkctl_packet_free(SDKCtlPacket* packet) +{ + SDKCtlSocket* const sdkctl = packet->sdkctl; + + /* Recycle packet. */ + _sdkctl_socket_free_recycler(packet->sdkctl, packet); + + T("SDKCtl %s: Packet %p is freed.", sdkctl->service_name, packet); + + /* Release SDKCTlSocket that owned this packet. */ + sdkctl_socket_release(sdkctl); +} + +/* References a packet. */ +int +_sdkctl_packet_reference(SDKCtlPacket* packet) +{ + assert(packet->ref_count > 0); + packet->ref_count++; + return packet->ref_count; +} + +/* Releases a packet. */ +int +_sdkctl_packet_release(SDKCtlPacket* packet) +{ + assert(packet->ref_count > 0); + packet->ref_count--; + if (packet->ref_count == 0) { + /* Last reference has been dropped. Destroy this object. */ + _sdkctl_packet_free(packet); + return 0; + } + return packet->ref_count; +} + +/* An I/O callback invoked on packet transmission. + * Param: + * io_opaque SDKCtlPacket instance of the packet that's being sent with this I/O. + * asio - Write I/O descriptor. + * status - I/O status. + */ +static AsyncIOAction +_on_sdkctl_packet_send_io(void* io_opaque, + AsyncSocketIO* asio, + AsyncIOState status) +{ + SDKCtlPacket* const packet = (SDKCtlPacket*)io_opaque; + AsyncIOAction action = ASIO_ACTION_DONE; + + /* Reference the packet while we're in this callback. */ + _sdkctl_packet_reference(packet); + + /* Lets see what's going on with query transmission. */ + switch (status) { + case ASIO_STATE_SUCCEEDED: + /* Packet has been sent to the service. */ + T("SDKCtl %s: Packet %p transmission has succeeded.", + packet->sdkctl->service_name, packet); + break; + + case ASIO_STATE_CANCELLED: + T("SDKCtl %s: Packet %p is cancelled.", + packet->sdkctl->service_name, packet); + break; + + case ASIO_STATE_FAILED: + T("SDKCtl %s: Packet %p has failed: %d -> %s", + packet->sdkctl->service_name, packet, errno, strerror(errno)); + break; + + case ASIO_STATE_FINISHED: + /* Time to disassociate the packet with the I/O. */ + _sdkctl_packet_release(packet); + break; + + default: + /* Transitional state. */ + break; + } + + _sdkctl_packet_release(packet); + + return action; +} + +/* Transmits a packet to SDK Controller. + * Param: + * packet - Packet to transmit. + */ +static void +_sdkctl_packet_transmit(SDKCtlPacket* packet) +{ + assert(packet->header.signature == _sdkctl_packet_sig); + + /* Reference to associate with the I/O */ + _sdkctl_packet_reference(packet); + + /* Transmit the packet to SDK controller. */ + async_socket_write_rel(packet->sdkctl->as, &packet->header, packet->header.size, + _on_sdkctl_packet_send_io, packet, -1); + + T("SDKCtl %s: Packet %p size %d is being sent.", + packet->sdkctl->service_name, packet, packet->header.size); +} + +/******************************************************************************** + * SDKCtlDirectPacket implementation + ********************************************************************************/ + +SDKCtlDirectPacket* +sdkctl_direct_packet_new(SDKCtlSocket* sdkctl) +{ + SDKCtlDirectPacket* const packet = + _sdkctl_socket_alloc_recycler(sdkctl, sizeof(SDKCtlDirectPacket)); + + packet->sdkctl = sdkctl; + packet->ref_count = 1; + + /* Refence SDKCTlSocket that owns this packet. */ + sdkctl_socket_reference(packet->sdkctl); + + T("SDKCtl %s: Direct packet %p is allocated.", sdkctl->service_name, packet); + + return packet; +} + +/* Frees a direct packet. */ +static void +_sdkctl_direct_packet_free(SDKCtlDirectPacket* packet) +{ + SDKCtlSocket* const sdkctl = packet->sdkctl; + + /* Free allocated resources. */ + _sdkctl_socket_free_recycler(packet->sdkctl, packet); + + T("SDKCtl %s: Direct packet %p is freed.", sdkctl->service_name, packet); + + /* Release SDKCTlSocket that owned this packet. */ + sdkctl_socket_release(sdkctl); +} + +/* References a packet. */ +int +sdkctl_direct_packet_reference(SDKCtlDirectPacket* packet) +{ + assert(packet->ref_count > 0); + packet->ref_count++; + return packet->ref_count; +} + +/* Releases a packet. */ +int +sdkctl_direct_packet_release(SDKCtlDirectPacket* packet) +{ + assert(packet->ref_count > 0); + packet->ref_count--; + if (packet->ref_count == 0) { + /* Last reference has been dropped. Destroy this object. */ + _sdkctl_direct_packet_free(packet); + return 0; + } + return packet->ref_count; +} + +/* An I/O callback invoked on direct packet transmission. + * Param: + * io_opaque SDKCtlDirectPacket instance of the packet that's being sent with + * this I/O. + * asio - Write I/O descriptor. + * status - I/O status. + */ +static AsyncIOAction +_on_sdkctl_direct_packet_send_io(void* io_opaque, + AsyncSocketIO* asio, + AsyncIOState status) +{ + SDKCtlDirectPacket* const packet = (SDKCtlDirectPacket*)io_opaque; + AsyncIOAction action = ASIO_ACTION_DONE; + + /* Reference the packet while we're in this callback. */ + sdkctl_direct_packet_reference(packet); + + /* Lets see what's going on with query transmission. */ + switch (status) { + case ASIO_STATE_SUCCEEDED: + /* Packet has been sent to the service. */ + T("SDKCtl %s: Direct packet %p transmission has succeeded.", + packet->sdkctl->service_name, packet); + packet->on_sent(packet->on_sent_opaque, packet, status); + break; + + case ASIO_STATE_CANCELLED: + T("SDKCtl %s: Direct packet %p is cancelled.", + packet->sdkctl->service_name, packet); + packet->on_sent(packet->on_sent_opaque, packet, status); + break; + + case ASIO_STATE_FAILED: + T("SDKCtl %s: Direct packet %p has failed: %d -> %s", + packet->sdkctl->service_name, packet, errno, strerror(errno)); + packet->on_sent(packet->on_sent_opaque, packet, status); + break; + + case ASIO_STATE_FINISHED: + /* Time to disassociate with the I/O. */ + sdkctl_direct_packet_release(packet); + break; + + default: + /* Transitional state. */ + break; + } + + sdkctl_direct_packet_release(packet); + + return action; +} + +void +sdkctl_direct_packet_send(SDKCtlDirectPacket* packet, + void* data, + on_sdkctl_direct_cb cb, + void* cb_opaque) +{ + packet->packet = (SDKCtlPacketHeader*)data; + packet->on_sent = cb; + packet->on_sent_opaque = cb_opaque; + assert(packet->packet->signature == _sdkctl_packet_sig); + + /* Reference for I/O */ + sdkctl_direct_packet_reference(packet); + + /* Transmit the packet to SDK controller. */ + async_socket_write_rel(packet->sdkctl->as, packet->packet, packet->packet->size, + _on_sdkctl_direct_packet_send_io, packet, -1); + + T("SDKCtl %s: Direct packet %p size %d is being sent", + packet->sdkctl->service_name, packet, packet->packet->size); +} + +/******************************************************************************** + * SDKCtlMessage implementation + *******************************************************************************/ + +/* Alocates a message descriptor. */ +static SDKCtlMessage* +_sdkctl_message_new(SDKCtlSocket* sdkctl, uint32_t msg_size, int msg_type) +{ + SDKCtlMessage* const msg = + (SDKCtlMessage*)_sdkctl_packet_new(sdkctl, + sizeof(SDKCtlMessageHeader) + msg_size, + SDKCTL_PACKET_MESSAGE); + msg->msg_type = msg_type; + + return msg; +} + +int +sdkctl_message_reference(SDKCtlMessage* msg) +{ + return _sdkctl_packet_reference(&msg->packet); +} + +int +sdkctl_message_release(SDKCtlMessage* msg) +{ + return _sdkctl_packet_release(&msg->packet); +} + +SDKCtlMessage* +sdkctl_message_send(SDKCtlSocket* sdkctl, + int msg_type, + const void* data, + uint32_t size) +{ + SDKCtlMessage* const msg = _sdkctl_message_new(sdkctl, size, msg_type); + if (size != 0 && data != NULL) { + memcpy(msg + 1, data, size); + } + _sdkctl_packet_transmit(&msg->packet); + + return msg; +} + +int +sdkctl_message_get_header_size(void) +{ + return sizeof(SDKCtlMessageHeader); +} + +void +sdkctl_init_message_header(void* msg, int msg_type, int msg_size) +{ + SDKCtlMessageHeader* const msg_header = (SDKCtlMessageHeader*)msg; + + msg_header->packet.signature = _sdkctl_packet_sig; + msg_header->packet.size = sizeof(SDKCtlMessageHeader) + msg_size; + msg_header->packet.type = SDKCTL_PACKET_MESSAGE; + msg_header->msg_type = msg_type; +} + +/******************************************************************************** + * SDKCtlQuery implementation + *******************************************************************************/ + +/* Frees query descriptor. */ +static void +_sdkctl_query_free(SDKCtlQuery* query) +{ + if (query != NULL) { + SDKCtlSocket* const sdkctl = query->sdkctl; + if (query->internal_resp_buffer != NULL && + (query->response_buffer == NULL || + query->response_buffer == &query->internal_resp_buffer)) { + /* This query used its internal buffer to receive the response. + * Free it. */ + free(query->internal_resp_buffer); + } + + loopTimer_done(query->timer); + + /* Recyle the descriptor. */ + _sdkctl_socket_free_recycler(sdkctl, query); + + T("SDKCtl %s: Query %p is freed.", sdkctl->service_name, query); + + /* Release socket that owned this query. */ + sdkctl_socket_release(sdkctl); + } +} + +/* Cancels timeout for the query. + * + * For the simplicity of implementation, the dispatcher will cancel query timer + * when query response data begins to flow in. If we let the timer to expire at + * that stage, we will end up with data flowing in without real place to + * accomodate it. + */ +static void +_sdkctl_query_cancel_timeout(SDKCtlQuery* query) +{ + loopTimer_stop(query->timer); + + T("SDKCtl %s: Query %p ID %d deadline %lld is cancelled.", + query->sdkctl->service_name, query, query->header.query_id, query->deadline); +} + +/* + * Query I/O callbacks. + */ + +/* Callback that is invoked by the I/O dispatcher when query is successfuly + * completed (i.e. response to the query is received). + */ +static void +_on_sdkctl_query_completed(SDKCtlQuery* query) +{ + T("SDKCtl %s: Query %p ID %d is completed.", + query->sdkctl->service_name, query, query->header.query_id); + + /* Cancel deadline, and inform the client about query completion. */ + _sdkctl_query_cancel_timeout(query); + query->query_cb(query->query_opaque, query, ASIO_STATE_SUCCEEDED); +} + +/* A callback that is invoked on query cancellation. */ +static void +_on_sdkctl_query_cancelled(SDKCtlQuery* query) +{ + /* + * Query cancellation means that SDK controller is disconnected. In turn, + * this means that SDK controller socket will handle disconnection in its + * connection callback. So, at this point all we need to do here is to inform + * the client about query cancellation. + */ + + /* Cancel deadline, and inform the client about query cancellation. */ + _sdkctl_query_cancel_timeout(query); + query->query_cb(query->query_opaque, query, ASIO_STATE_CANCELLED); +} + +/* A timer callback that is invoked on query timeout. + * Param: + * opaque - SDKCtlQuery instance. + */ +static void +_on_skdctl_query_timeout(void* opaque) +{ + SDKCtlQuery* const query = (SDKCtlQuery*)opaque; + + D("SDKCtl %s: Query %p ID %d with deadline %lld has timed out at %lld", + query->sdkctl->service_name, query, query->header.query_id, + query->deadline, async_socket_deadline(query->sdkctl->as, 0)); + + /* Reference the query while we're in this callback. */ + sdkctl_query_reference(query); + + /* Inform the client about deadline expiration. Note that client may + * extend the deadline, and retry the query. */ + const AsyncIOAction action = + query->query_cb(query->query_opaque, query, ASIO_STATE_TIMED_OUT); + + /* For actions other than retry we will destroy the query. */ + if (action != ASIO_ACTION_RETRY) { + _sdkctl_socket_remove_query(query); + } + + sdkctl_query_release(query); +} + +/* A callback that is invoked when query has been sent to the SDK controller. */ +static void +_on_sdkctl_query_sent(SDKCtlQuery* query) +{ + T("SDKCtl %s: Sent %d bytes of query %p ID %d of type %d", + query->sdkctl->service_name, query->header.packet.size, query, + query->header.query_id, query->header.query_type); + + /* Inform the client about the event. */ + query->query_cb(query->query_opaque, query, ASIO_STATE_CONTINUES); + + /* Set a timer to expire at query's deadline, and let the response to come + * through the dispatcher loop. */ + loopTimer_startAbsolute(query->timer, query->deadline); +} + +/* An I/O callback invoked on query transmission. + * Param: + * io_opaque SDKCtlQuery instance of the query that's being sent with this I/O. + * asio - Write I/O descriptor. + * status - I/O status. + */ +static AsyncIOAction +_on_sdkctl_query_send_io(void* io_opaque, + AsyncSocketIO* asio, + AsyncIOState status) +{ + SDKCtlQuery* const query = (SDKCtlQuery*)io_opaque; + AsyncIOAction action = ASIO_ACTION_DONE; + + /* Reference the query while we're in this callback. */ + sdkctl_query_reference(query); + + /* Lets see what's going on with query transmission. */ + switch (status) { + case ASIO_STATE_SUCCEEDED: + /* Query has been sent to the service. */ + _on_sdkctl_query_sent(query); + break; + + case ASIO_STATE_CANCELLED: + T("SDKCtl %s: Query %p ID %d is cancelled in transmission.", + query->sdkctl->service_name, query, query->header.query_id); + /* Remove the query from the list of active queries. */ + _sdkctl_socket_remove_query(query); + _on_sdkctl_query_cancelled(query); + break; + + case ASIO_STATE_TIMED_OUT: + D("SDKCtl %s: Query %p ID %d with deadline %lld has timed out in transmission at %lld", + query->sdkctl->service_name, query, query->header.query_id, + query->deadline, async_socket_deadline(query->sdkctl->as, 0)); + /* Invoke query's callback. */ + action = query->query_cb(query->query_opaque, query, status); + /* For actions other than retry we need to stop the query. */ + if (action != ASIO_ACTION_RETRY) { + _sdkctl_socket_remove_query(query); + } + break; + + case ASIO_STATE_FAILED: + T("SDKCtl %s: Query %p ID %d failed in transmission: %d -> %s", + query->sdkctl->service_name, query, query->header.query_id, + errno, strerror(errno)); + /* Invoke query's callback. Note that we will let the client to + * decide what to do on I/O failure. */ + action = query->query_cb(query->query_opaque, query, status); + /* For actions other than retry we need to stop the query. */ + if (action != ASIO_ACTION_RETRY) { + _sdkctl_socket_remove_query(query); + } + break; + + case ASIO_STATE_FINISHED: + /* Time to disassociate with the I/O. */ + sdkctl_query_release(query); + break; + + default: + /* Transitional state. */ + break; + } + + sdkctl_query_release(query); + + return action; +} + +/******************************************************************************** + * SDKCtlQuery public API implementation + ********************************************************************************/ + +SDKCtlQuery* +sdkctl_query_new(SDKCtlSocket* sdkctl, int query_type, uint32_t in_data_size) +{ + SDKCtlQuery* const query = + _sdkctl_socket_alloc_recycler(sdkctl, sizeof(SDKCtlQuery) + in_data_size); + query->next = NULL; + query->sdkctl = sdkctl; + query->response_buffer = NULL; + query->response_size = NULL; + query->internal_resp_buffer = NULL; + query->internal_resp_size = 0; + query->query_cb = NULL; + query->query_opaque = NULL; + query->deadline = DURATION_INFINITE; + query->ref_count = 1; + query->header.packet.signature = _sdkctl_packet_sig; + query->header.packet.size = sizeof(SDKCtlQueryHeader) + in_data_size; + query->header.packet.type = SDKCTL_PACKET_QUERY; + query->header.query_id = _sdkctl_socket_next_query_id(sdkctl); + query->header.query_type = query_type; + + /* Initialize timer to fire up on query deadline expiration. */ + loopTimer_init(query->timer, sdkctl->looper, _on_skdctl_query_timeout, query); + + /* Reference socket that owns this query. */ + sdkctl_socket_reference(sdkctl); + + T("SDKCtl %s: Query %p ID %d type %d is created for %d bytes of data.", + query->sdkctl->service_name, query, query->header.query_id, + query_type, in_data_size); + + return query; +} + +SDKCtlQuery* +sdkctl_query_new_ex(SDKCtlSocket* sdkctl, + int query_type, + uint32_t in_data_size, + const void* in_data, + void** response_buffer, + uint32_t* response_size, + on_sdkctl_query_cb query_cb, + void* query_opaque) +{ + SDKCtlQuery* const query = sdkctl_query_new(sdkctl, query_type, in_data_size); + + query->response_buffer = response_buffer; + if (query->response_buffer == NULL) { + /* Creator didn't supply a buffer. Use internal one instead. */ + query->response_buffer = &query->internal_resp_buffer; + } + query->response_size = response_size; + if (query->response_size == NULL) { + /* Creator didn't supply a buffer for response size. Use internal one + * instead. */ + query->response_size = &query->internal_resp_size; + } + query->query_cb = query_cb; + query->query_opaque = query_opaque; + /* Init query's input buffer. */ + if (in_data_size != 0 && in_data != NULL) { + memcpy(query + 1, in_data, in_data_size); + } + + return query; +} + +void +sdkctl_query_send(SDKCtlQuery* query, int to) +{ + SDKCtlSocket* const sdkctl = query->sdkctl; + + /* Initialize the deadline. */ + query->deadline = async_socket_deadline(query->sdkctl->as, to); + + /* List the query in the list of active queries. */ + _sdkctl_socket_add_query(query); + + /* Reference query associated with write I/O. */ + sdkctl_query_reference(query); + + assert(query->header.packet.signature == _sdkctl_packet_sig); + /* Transmit the query to SDK controller. */ + async_socket_write_abs(sdkctl->as, &query->header, query->header.packet.size, + _on_sdkctl_query_send_io, query, query->deadline); + + T("SDKCtl %s: Query %p ID %d type %d is being sent with deadline at %lld", + query->sdkctl->service_name, query, query->header.query_id, + query->header.query_type, query->deadline); +} + +SDKCtlQuery* +sdkctl_query_build_and_send(SDKCtlSocket* sdkctl, + int query_type, + uint32_t in_data_size, + const void* in_data, + void** response_buffer, + uint32_t* response_size, + on_sdkctl_query_cb query_cb, + void* query_opaque, + int to) +{ + SDKCtlQuery* const query = + sdkctl_query_new_ex(sdkctl, query_type, in_data_size, in_data, + response_buffer, response_size, query_cb, + query_opaque); + sdkctl_query_send(query, to); + return query; +} + +int +sdkctl_query_reference(SDKCtlQuery* query) +{ + assert(query->ref_count > 0); + query->ref_count++; + return query->ref_count; +} + +int +sdkctl_query_release(SDKCtlQuery* query) +{ + assert(query->ref_count > 0); + query->ref_count--; + if (query->ref_count == 0) { + /* Last reference has been dropped. Destroy this object. */ + _sdkctl_query_free(query); + return 0; + } + return query->ref_count; +} + +void* +sdkctl_query_get_buffer_in(SDKCtlQuery* query) +{ + /* Query buffer starts right after the header. */ + return query + 1; +} + +void* +sdkctl_query_get_buffer_out(SDKCtlQuery* query) +{ + return query->response_buffer != NULL ? *query->response_buffer : + query->internal_resp_buffer; +} + +/******************************************************************************** + * SDKCtlPacket implementation + *******************************************************************************/ + +/* A packet has been received from SDK controller. + * Note that we expect the packet to be a message, since queries, and query + * replies are handled separately. */ +static void +_on_sdkctl_packet_received(SDKCtlSocket* sdkctl, SDKCtlPacket* packet) +{ + T("SDKCtl %s: Received packet size: %d, type: %d", + sdkctl->service_name, packet->header.size, packet->header.type); + + assert(packet->header.signature == _sdkctl_packet_sig); + if (packet->header.type == SDKCTL_PACKET_MESSAGE) { + SDKCtlMessage* const msg = (SDKCtlMessage*)packet; + /* Lets see if this is an internal protocol message. */ + switch (msg->msg_type) { + case SDKCTL_MSG_PORT_CONNECTED: + sdkctl->port_status = SDKCTL_PORT_CONNECTED; + sdkctl->on_port_connection(sdkctl->opaque, sdkctl, + SDKCTL_PORT_CONNECTED); + break; + + case SDKCTL_MSG_PORT_DISCONNECTED: + sdkctl->port_status = SDKCTL_PORT_DISCONNECTED; + sdkctl->on_port_connection(sdkctl->opaque, sdkctl, + SDKCTL_PORT_DISCONNECTED); + break; + + case SDKCTL_MSG_PORT_ENABLED: + sdkctl->port_status = SDKCTL_PORT_ENABLED; + sdkctl->on_port_connection(sdkctl->opaque, sdkctl, + SDKCTL_PORT_ENABLED); + break; + + case SDKCTL_MSG_PORT_DISABLED: + sdkctl->port_status = SDKCTL_PORT_DISABLED; + sdkctl->on_port_connection(sdkctl->opaque, sdkctl, + SDKCTL_PORT_DISABLED); + break; + + default: + /* This is a higher-level message. Dispatch the message to the + * client. */ + sdkctl->on_message(sdkctl->opaque, sdkctl, msg, msg->msg_type, msg + 1, + packet->header.size - sizeof(SDKCtlMessageHeader)); + break; + } + } else { + E("SDKCtl %s: Received unknown packet type %d size %d", + sdkctl->service_name, packet->header.type, packet->header.size); + } +} + +/******************************************************************************** + * SDKCtlIODispatcher implementation + *******************************************************************************/ + +/* An I/O callback invoked when data gets received from the socket. + * Param: + * io_opaque SDKCtlIODispatcher instance associated with the reader. + * asio - Read I/O descriptor. + * status - I/O status. + */ +static AsyncIOAction _on_sdkctl_io_dispatcher_io(void* io_opaque, + AsyncSocketIO* asio, + AsyncIOState status); + +/* Starts I/O dispatcher for SDK controller socket. */ +static void +_sdkctl_io_dispatcher_start(SDKCtlSocket* sdkctl) { + SDKCtlIODispatcher* const dispatcher = &sdkctl->io_dispatcher; + + dispatcher->state = SDKCTL_IODISP_EXPECT_HEADER; + dispatcher->sdkctl = sdkctl; + dispatcher->packet = NULL; + dispatcher->current_query = NULL; + + /* Register a packet header reader with the socket. */ + async_socket_read_rel(dispatcher->sdkctl->as, &dispatcher->packet_header, + sizeof(SDKCtlPacketHeader), _on_sdkctl_io_dispatcher_io, + dispatcher, -1); +} + +/* Resets I/O dispatcher for SDK controller socket. */ +static void +_sdkctl_io_dispatcher_reset(SDKCtlSocket* sdkctl) { + SDKCtlIODispatcher* const dispatcher = &sdkctl->io_dispatcher; + + /* Cancel current query. */ + if (dispatcher->current_query != NULL) { + SDKCtlQuery* const query = dispatcher->current_query; + dispatcher->current_query = NULL; + _on_sdkctl_query_cancelled(query); + sdkctl_query_release(query); + } + + /* Free packet data buffer. */ + if (dispatcher->packet != NULL) { + _sdkctl_packet_release(dispatcher->packet); + dispatcher->packet = NULL; + } + + /* Reset dispatcher state. */ + dispatcher->state = SDKCTL_IODISP_EXPECT_HEADER; + + T("SDKCtl %s: I/O Dispatcher is reset", sdkctl->service_name); +} + +/* + * I/O dispatcher callbacks. + */ + +/* A callback that is invoked when a failure occurred while dispatcher was + * reading data from the socket. + */ +static void +_on_io_dispatcher_io_failure(SDKCtlIODispatcher* dispatcher, + AsyncSocketIO* asio) +{ + SDKCtlSocket* const sdkctl = dispatcher->sdkctl; + + D("SDKCtl %s: Dispatcher I/O failure: %d -> %s", + sdkctl->service_name, errno, strerror(errno)); + + /* We treat all I/O failures same way we treat disconnection. Just cancel + * everything, disconnect, and let the client to decide what to do next. */ + sdkctl_socket_disconnect(sdkctl); + + /* Report disconnection to the client, and let it restore connection in this + * callback. */ + sdkctl->on_socket_connection(sdkctl->opaque, sdkctl, ASIO_STATE_FAILED); +} + +/* A callback that is invoked when dispatcher's reader has been cancelled. */ +static void +_on_io_dispatcher_io_cancelled(SDKCtlIODispatcher* dispatcher, + AsyncSocketIO* asio) +{ + T("SDKCtl %s: Dispatcher I/O cancelled.", dispatcher->sdkctl->service_name); + + /* If we're in the middle of receiving query reply we need to cancel the + * query. */ + if (dispatcher->current_query != NULL) { + SDKCtlQuery* const query = dispatcher->current_query; + dispatcher->current_query = NULL; + _on_sdkctl_query_cancelled(query); + sdkctl_query_release(query); + } + + /* Discard packet data we've received so far. */ + if (dispatcher->packet != NULL) { + _sdkctl_packet_release(dispatcher->packet); + dispatcher->packet = NULL; + } +} + +/* A generic packet header has been received by I/O dispatcher. */ +static AsyncIOAction +_on_io_dispatcher_packet_header(SDKCtlIODispatcher* dispatcher, + AsyncSocketIO* asio) +{ + SDKCtlSocket* const sdkctl = dispatcher->sdkctl; + + T("SDKCtl %s: Packet header type %d, size %d is received.", + dispatcher->sdkctl->service_name, dispatcher->packet_header.type, + dispatcher->packet_header.size); + + /* Make sure we have a valid packet header. */ + if (dispatcher->packet_header.signature != _sdkctl_packet_sig) { + E("SDKCtl %s: Invalid packet signature %x for packet type %d, size %d", + sdkctl->service_name, dispatcher->packet_header.signature, + dispatcher->packet_header.type, dispatcher->packet_header.size); + /* This is a protocol failure. Treat it as I/O failure: disconnect, and + * let the client to decide what to do next. */ + errno = EINVAL; + _on_io_dispatcher_io_failure(dispatcher, asio); + return ASIO_ACTION_DONE; + } + + /* Here we have three choices for the packet, that define the rest of + * the data that follow it: + * - Regular packet, + * - Response to a query that has been sent to SDK controller, + * - A query from SDK controller. + * Update the state accordingly, and initiate reading of the + * remaining of the packet. + */ + if (dispatcher->packet_header.type == SDKCTL_PACKET_QUERY_RESPONSE) { + /* This is a response to the query. Before receiving response data we + * need to locate the relevant query, and use its response buffer to read + * the data. For that we need to obtain query ID firts. So, initiate + * reading of the remaining part of SDKCtlQueryReplyHeader. */ + dispatcher->state = SDKCTL_IODISP_EXPECT_QUERY_REPLY_HEADER; + async_socket_read_rel(sdkctl->as, &dispatcher->query_reply_header.query_id, + sizeof(SDKCtlQueryReplyHeader) - sizeof(SDKCtlPacketHeader), + _on_sdkctl_io_dispatcher_io, dispatcher, -1); + } else { + /* For regular packets, as well as queries, we simply allocate buffer, + * that fits the entire packet, and read the remainder of the data in + * there. */ + dispatcher->state = SDKCTL_IODISP_EXPECT_DATA; + dispatcher->packet = + _sdkctl_packet_new(sdkctl, dispatcher->packet_header.size, + dispatcher->packet_header.type); + /* Initiate reading of the packet data. */ + async_socket_read_rel(sdkctl->as, dispatcher->packet + 1, + dispatcher->packet_header.size - sizeof(SDKCtlPacketHeader), + _on_sdkctl_io_dispatcher_io, dispatcher, -1); + } + + return ASIO_ACTION_DONE; +} + +/* A generic packet has been received by I/O dispatcher. */ +static AsyncIOAction +_on_io_dispatcher_packet(SDKCtlIODispatcher* dispatcher, AsyncSocketIO* asio) +{ + SDKCtlSocket* const sdkctl = dispatcher->sdkctl; + SDKCtlPacket* const packet = dispatcher->packet; + dispatcher->packet = NULL; + + T("SDKCtl %s: Packet type %d, size %d is received.", + dispatcher->sdkctl->service_name, dispatcher->packet_header.type, + dispatcher->packet_header.size); + + _on_sdkctl_packet_received(sdkctl, packet); + _sdkctl_packet_release(packet); + + /* Get ready for the next I/O cycle. */ + dispatcher->state = SDKCTL_IODISP_EXPECT_HEADER; + async_socket_read_rel(sdkctl->as, &dispatcher->packet_header, sizeof(SDKCtlPacketHeader), + _on_sdkctl_io_dispatcher_io, dispatcher, -1); + return ASIO_ACTION_DONE; +} + +/* A query reply header has been received by I/O dispatcher. */ +static AsyncIOAction +_on_io_dispatcher_query_reply_header(SDKCtlIODispatcher* dispatcher, + AsyncSocketIO* asio) +{ + SDKCtlSocket* const sdkctl = dispatcher->sdkctl; + SDKCtlQuery* query; + + T("SDKCtl %s: Query reply header is received for query ID %d", + dispatcher->sdkctl->service_name, dispatcher->query_reply_header.query_id); + + /* Pull the query out of the list of active queries. It's the dispatcher that + * owns this query now. */ + dispatcher->current_query = + _sdkctl_socket_remove_query_id(sdkctl, dispatcher->query_reply_header.query_id); + query = dispatcher->current_query; + const uint32_t query_data_size = + dispatcher->packet_header.size - sizeof(SDKCtlQueryReplyHeader); + dispatcher->state = SDKCTL_IODISP_EXPECT_QUERY_REPLY_DATA; + + if (query == NULL) { + D("%s: Query #%d is not found by dispatcher", + dispatcher->sdkctl->service_name, dispatcher->query_reply_header.query_id); + + /* Query is not found. Just read the remainder of reply up in the air, + * and then discard when it's over. */ + dispatcher->state = SDKCTL_IODISP_EXPECT_QUERY_REPLY_DATA; + dispatcher->packet = + _sdkctl_packet_new(sdkctl, dispatcher->packet_header.size, + dispatcher->packet_header.type); + /* Copy query reply info to the packet. */ + memcpy(&dispatcher->packet->header, &dispatcher->query_reply_header, + sizeof(SDKCtlQueryReplyHeader)); + async_socket_read_rel(sdkctl->as, dispatcher->packet + 1, query_data_size, + _on_sdkctl_io_dispatcher_io, dispatcher, -1); + } else { + /* Prepare to receive query reply. For the simplicity sake, cancel query + * time out, so it doesn't expire on us while we're in the middle of + * receiving query's reply. */ + _sdkctl_query_cancel_timeout(query); + + if (*query->response_size < query_data_size) { + *query->response_buffer = malloc(query_data_size); + if (*query->response_buffer == NULL) { + APANIC("%s: Unable to allocate %d bytes for query response", + sdkctl->service_name, query_data_size); + } + } + /* Save the actual query response size. */ + *query->response_size = query_data_size; + + /* Start reading query response. */ + async_socket_read_rel(sdkctl->as, *query->response_buffer, + *query->response_size, _on_sdkctl_io_dispatcher_io, + dispatcher, -1); + } + + return ASIO_ACTION_DONE; +} + +/* A query reply header has been received by I/O dispatcher. */ +static AsyncIOAction +_on_io_dispatcher_query_reply(SDKCtlIODispatcher* dispatcher, AsyncSocketIO* asio) +{ + SDKCtlSocket* const sdkctl = dispatcher->sdkctl; + SDKCtlQuery* const query = dispatcher->current_query; + dispatcher->current_query = NULL; + + if (query != NULL) { + _ANDROID_ASSERT(query->header.query_id == dispatcher->query_reply_header.query_id, + "SDKCtl %s: Query ID mismatch in I/O dispatcher", + sdkctl->service_name); + T("SDKCtl %s: Query reply is received for query %p ID %d. Reply size is %d", + dispatcher->sdkctl->service_name, query, query->header.query_id, + *query->response_size); + + /* Complete the query, and release it from the dispatcher. */ + _on_sdkctl_query_completed(query); + sdkctl_query_release(query); + } else { + /* This was "read up in the air" for a cancelled query. Just discard the + * read data. */ + if (dispatcher->packet != NULL) { + _sdkctl_packet_release(dispatcher->packet); + dispatcher->packet = NULL; + } + } + + /* Get ready for the next I/O cycle. */ + dispatcher->state = SDKCTL_IODISP_EXPECT_HEADER; + async_socket_read_rel(sdkctl->as, &dispatcher->packet_header, sizeof(SDKCtlPacketHeader), + _on_sdkctl_io_dispatcher_io, dispatcher, -1); + return ASIO_ACTION_DONE; +} + +/* An I/O callback invoked when data gets received from the socket. + * This is main I/O dispatcher loop. + * Param: + * io_opaque SDKCtlIODispatcher instance associated with the reader. + * asio - Read I/O descriptor. + * status - I/O status. + */ +static AsyncIOAction +_on_sdkctl_io_dispatcher_io(void* io_opaque, + AsyncSocketIO* asio, + AsyncIOState status) +{ + AsyncIOAction action = ASIO_ACTION_DONE; + SDKCtlIODispatcher* const dispatcher = (SDKCtlIODispatcher*)io_opaque; + SDKCtlSocket* const sdkctl = dispatcher->sdkctl; + + /* Reference SDKCtlSocket while we're in this callback. */ + sdkctl_socket_reference(sdkctl); + + if (status != ASIO_STATE_SUCCEEDED) { + /* Something going on with I/O other than receiving data.. */ + switch (status) { + case ASIO_STATE_STARTED: + /* Data has started flowing in. Cancel timeout on I/O that has + * started, so we can complete the current state of the + * dispatcher without interruptions other than I/O failures. */ + async_socket_io_cancel_time_out(asio); + break; + + case ASIO_STATE_FAILED: + /* I/O failure has occurred. Handle the failure. */ + _on_io_dispatcher_io_failure(dispatcher, asio); + break; + + case ASIO_STATE_TIMED_OUT: + /* The way I/O dispatcher is implemented, this should never + * happen, because dispatcher doesn't set I/O expiration time + * when registering its readers. */ + _ANDROID_ASSERT(0, + "SDKCtl %s: We should never receive ASIO_STATE_TIMED_OUT in SDKCtl I/O dispatcher.", + sdkctl->service_name); + break; + + case ASIO_STATE_CANCELLED: + /* Cancellation means that we're in the middle of handling + * disconnection. Sooner or later, this dispatcher will be reset, + * so we don't really care about keeping its state at this point. + */ + _on_io_dispatcher_io_cancelled(dispatcher, asio); + break; + + case ASIO_STATE_FINISHED: + break; + + default: + _ANDROID_ASSERT(0, "SDKCtl %s: Unexpected I/O status %d in the dispatcher", + sdkctl->service_name, status); + /* Handle this as protocol failure. */ + errno = EINVAL; + _on_io_dispatcher_io_failure(dispatcher, asio); + action = ASIO_ACTION_ABORT; + break; + } + + sdkctl_socket_release(sdkctl); + + return action; + } + + /* Requested data has been read. Handle the chunk depending on dispatcher's + * state. */ + switch (dispatcher->state) { + case SDKCTL_IODISP_EXPECT_HEADER: + /* A generic packet header is received. */ + action = _on_io_dispatcher_packet_header(dispatcher, asio); + break; + + case SDKCTL_IODISP_EXPECT_QUERY_REPLY_HEADER: + /* Query reply header is received. */ + action = _on_io_dispatcher_query_reply_header(dispatcher, asio); + break; + + case SDKCTL_IODISP_EXPECT_QUERY_REPLY_DATA: + /* Query reply is received. Complete the query. */ + action = _on_io_dispatcher_query_reply(dispatcher, asio); + break; + + case SDKCTL_IODISP_EXPECT_DATA: + /* A generic packet is received. */ + action = _on_io_dispatcher_packet(dispatcher, asio); + break; + + default: + _ANDROID_ASSERT(0, "SDKCtl %s: Unexpected I/O dispacher state %d", + sdkctl->service_name, dispatcher->state); + break; + } + + sdkctl_socket_release(sdkctl); + + return action; +} + +/******************************************************************************** + * SDKCtlSocket internals. + *******************************************************************************/ + +/* Cancels all queries that is active on this socket. */ +static void +_sdkctl_socket_cancel_all_queries(SDKCtlSocket* sdkctl) +{ + SDKCtlIODispatcher* const dispatcher = &sdkctl->io_dispatcher; + SDKCtlQuery* query; + + /* Cancel query that is being completed in dispatcher. */ + if (dispatcher->current_query != NULL) { + SDKCtlQuery* const query = dispatcher->current_query; + dispatcher->current_query = NULL; + _on_sdkctl_query_cancelled(query); + sdkctl_query_release(query); + } + + /* One by one empty query list cancelling pulled queries. */ + query = _sdkctl_socket_pull_first_query(sdkctl); + while (query != NULL) { + _sdkctl_query_cancel_timeout(query); + query->query_cb(query->query_opaque, query, ASIO_STATE_CANCELLED); + sdkctl_query_release(query); + query = _sdkctl_socket_pull_first_query(sdkctl); + } +} + +/* Cancels all packets that is active on this socket. */ +static void +_sdkctl_socket_cancel_all_packets(SDKCtlSocket* sdkctl) +{ +} + +/* Cancels all I/O that is active on this socket. */ +static void +_sdkctl_socket_cancel_all_io(SDKCtlSocket* sdkctl) +{ + /* Cancel all queries, and packets that are active for this I/O. */ + _sdkctl_socket_cancel_all_queries(sdkctl); + _sdkctl_socket_cancel_all_packets(sdkctl); +} + +/* Disconnects AsyncSocket for SDKCtlSocket. */ +static void +_sdkctl_socket_disconnect_socket(SDKCtlSocket* sdkctl) +{ + if (sdkctl->as != NULL) { + /* Disconnect the socket. This will trigger I/O cancellation callbacks. */ + async_socket_disconnect(sdkctl->as); + + /* Cancel all I/O that is active on this socket. */ + _sdkctl_socket_cancel_all_io(sdkctl); + + /* Reset I/O dispatcher. */ + _sdkctl_io_dispatcher_reset(sdkctl); + } + + sdkctl->state = SDKCTL_SOCKET_DISCONNECTED; + sdkctl->port_status = SDKCTL_PORT_DISCONNECTED; +} + +/* Frees SDKCtlSocket instance. */ +static void +_sdkctl_socket_free(SDKCtlSocket* sdkctl) +{ + if (sdkctl != NULL) { + T("SDKCtl %s: descriptor is destroing.", sdkctl->service_name); + + /* Disconnect, and release the socket. */ + if (sdkctl->as != NULL) { + async_socket_disconnect(sdkctl->as); + async_socket_release(sdkctl->as); + } + + /* Free allocated resources. */ + if (sdkctl->looper != NULL) { + looper_free(sdkctl->looper); + } + if (sdkctl->service_name != NULL) { + free(sdkctl->service_name); + } + _sdkctl_socket_empty_recycler(sdkctl); + + AFREE(sdkctl); + } +} + +/******************************************************************************** + * SDK Control Socket connection callbacks. + *******************************************************************************/ + +/* Initiates handshake query when SDK controller socket is connected. */ +static void _sdkctl_do_handshake(SDKCtlSocket* sdkctl); + +/* A socket connection is established. + * Here we will start I/O dispatcher, and will initiate a handshake with + * the SdkController service for this socket. */ +static AsyncIOAction +_on_async_socket_connected(SDKCtlSocket* sdkctl) +{ + D("SDKCtl %s: Socket is connected.", sdkctl->service_name); + + /* Notify the client that connection is established. */ + const AsyncIOAction action = + sdkctl->on_socket_connection(sdkctl->opaque, sdkctl, ASIO_STATE_SUCCEEDED); + + if (action == ASIO_ACTION_DONE) { + /* Initialize, and start main I/O dispatcher. */ + _sdkctl_io_dispatcher_start(sdkctl); + + /* Initiate handshake. */ + _sdkctl_do_handshake(sdkctl); + + return action; + } else { + /* Client didn't like something about this connection. */ + return action; + } +} + +/* Handles lost connection with SdkController service. */ +static AsyncIOAction +_on_async_socket_disconnected(SDKCtlSocket* sdkctl) +{ + D("SDKCtl %s: Socket has been disconnected.", sdkctl->service_name); + + _sdkctl_socket_disconnect_socket(sdkctl); + + AsyncIOAction action = sdkctl->on_socket_connection(sdkctl->opaque, sdkctl, + ASIO_STATE_FAILED); + if (action == ASIO_ACTION_DONE) { + /* Default action for disconnect is to reestablish the connection. */ + action = ASIO_ACTION_RETRY; + } + if (action == ASIO_ACTION_RETRY) { + sdkctl->state = SDKCTL_SOCKET_CONNECTING; + } + return action; +} + +/* An entry point for all socket connection events. + * Here we will dispatch connection events to appropriate handlers. + * Param: + * client_opaque - SDKCtlSocket isntance. + */ +static AsyncIOAction +_on_async_socket_connection(void* client_opaque, + AsyncSocket* as, + AsyncIOState status) +{ + AsyncIOAction action = ASIO_ACTION_DONE; + SDKCtlSocket* const sdkctl = (SDKCtlSocket*)client_opaque; + + /* Reference the socket while in this callback. */ + sdkctl_socket_reference(sdkctl); + + switch (status) { + case ASIO_STATE_SUCCEEDED: + sdkctl->state = SDKCTL_SOCKET_CONNECTED; + _on_async_socket_connected(sdkctl); + break; + + case ASIO_STATE_FAILED: + if (sdkctl->state == SDKCTL_SOCKET_CONNECTED) { + /* This is disconnection condition. */ + action = _on_async_socket_disconnected(sdkctl); + } else { + /* An error has occurred while attempting to connect to socket. + * Lets try again... */ + action = ASIO_ACTION_RETRY; + } + break; + + case ASIO_STATE_RETRYING: + default: + action = ASIO_ACTION_RETRY; + break; + } + + sdkctl_socket_release(sdkctl); + + return action; +} + +/******************************************************************************** + * SDK Control Socket public API + *******************************************************************************/ + +SDKCtlSocket* +sdkctl_socket_new(int reconnect_to, + const char* service_name, + on_sdkctl_socket_connection_cb on_socket_connection, + on_sdkctl_port_connection_cb on_port_connection, + on_sdkctl_message_cb on_message, + void* opaque) +{ + SDKCtlSocket* sdkctl; + ANEW0(sdkctl); + + sdkctl->state = SDKCTL_SOCKET_DISCONNECTED; + sdkctl->port_status = SDKCTL_PORT_DISCONNECTED; + sdkctl->opaque = opaque; + sdkctl->service_name = ASTRDUP(service_name); + sdkctl->on_socket_connection = on_socket_connection; + sdkctl->on_port_connection = on_port_connection; + sdkctl->on_message = on_message; + sdkctl->reconnect_to = reconnect_to; + sdkctl->as = NULL; + sdkctl->next_query_id = 0; + sdkctl->query_head = sdkctl->query_tail = NULL; + sdkctl->ref_count = 1; + sdkctl->recycler = NULL; + sdkctl->recycler_block_size = 0; + sdkctl->recycler_max = 0; + sdkctl->recycler_count = 0; + + T("SDKCtl %s: descriptor is created.", sdkctl->service_name); + + sdkctl->looper = looper_newCore(); + if (sdkctl->looper == NULL) { + E("Unable to create I/O looper for SDKCtl socket '%s'", + service_name); + on_socket_connection(opaque, sdkctl, ASIO_STATE_FAILED); + _sdkctl_socket_free(sdkctl); + return NULL; + } + + return sdkctl; +} + +int sdkctl_socket_reference(SDKCtlSocket* sdkctl) +{ + assert(sdkctl->ref_count > 0); + sdkctl->ref_count++; + return sdkctl->ref_count; +} + +int +sdkctl_socket_release(SDKCtlSocket* sdkctl) +{ + assert(sdkctl->ref_count > 0); + sdkctl->ref_count--; + if (sdkctl->ref_count == 0) { + /* Last reference has been dropped. Destroy this object. */ + _sdkctl_socket_free(sdkctl); + return 0; + } + return sdkctl->ref_count; +} + +void +sdkctl_init_recycler(SDKCtlSocket* sdkctl, + uint32_t data_size, + int max_recycled_num) +{ + if (sdkctl->recycler != NULL) { + D("SDKCtl %s: Recycler is already initialized. Ignoring recycler init.", + sdkctl->service_name); + return; + } + + /* SDKCtlQuery is max descriptor sizeof. */ + data_size += sizeof(SDKCtlQuery); + + sdkctl->recycler_block_size = data_size; + sdkctl->recycler_max = max_recycled_num; + sdkctl->recycler_count = 0; +} + +void +sdkctl_socket_connect(SDKCtlSocket* sdkctl, int port, int retry_to) +{ + T("SDKCtl %s: Handling connect request to port %d, retrying in %dms...", + sdkctl->service_name, port, retry_to); + + sdkctl->state = SDKCTL_SOCKET_CONNECTING; + sdkctl->as = async_socket_new(port, sdkctl->reconnect_to, + _on_async_socket_connection, sdkctl, + sdkctl->looper); + if (sdkctl->as == NULL) { + E("Unable to allocate AsyncSocket for SDKCtl socket '%s'", + sdkctl->service_name); + sdkctl->on_socket_connection(sdkctl->opaque, sdkctl, ASIO_STATE_FAILED); + } else { + async_socket_connect(sdkctl->as, retry_to); + } +} + +void +sdkctl_socket_reconnect(SDKCtlSocket* sdkctl, int port, int retry_to) +{ + T("SDKCtl %s: Handling reconnection request to port %d, retrying in %dms...", + sdkctl->service_name, port, retry_to); + + _sdkctl_socket_disconnect_socket(sdkctl); + + if (sdkctl->as == NULL) { + sdkctl_socket_connect(sdkctl, port, retry_to); + } else { + sdkctl->state = SDKCTL_SOCKET_CONNECTING; + async_socket_reconnect(sdkctl->as, retry_to); + } +} + +void +sdkctl_socket_disconnect(SDKCtlSocket* sdkctl) +{ + T("SDKCtl %s: Handling disconnect request.", sdkctl->service_name); + + _sdkctl_socket_disconnect_socket(sdkctl); +} + +int +sdkctl_socket_is_connected(SDKCtlSocket* sdkctl) +{ + return (sdkctl->state == SDKCTL_SOCKET_CONNECTED) ? 1 : 0; +} + +int +sdkctl_socket_is_port_ready(SDKCtlSocket* sdkctl) +{ + return (sdkctl->port_status == SDKCTL_PORT_ENABLED) ? 1 : 0; +} + +SdkCtlPortStatus +sdkctl_socket_get_port_status(SDKCtlSocket* sdkctl) +{ + return sdkctl->port_status; +} + +int +sdkctl_socket_is_handshake_ok(SDKCtlSocket* sdkctl) +{ + switch (sdkctl->port_status) { + case SDKCTL_HANDSHAKE_DUP: + case SDKCTL_HANDSHAKE_UNKNOWN_QUERY: + case SDKCTL_HANDSHAKE_UNKNOWN_RESPONSE: + return 0; + default: + return 1; + } +} + +/******************************************************************************** + * Handshake query + *******************************************************************************/ + +/* + * Handshake result values. + */ + +/* Handshake has succeeded completed, and service-side port is connected. */ +#define SDKCTL_HANDSHAKE_RESP_CONNECTED 0 +/* Handshake has succeeded completed, but service-side port is not connected. */ +#define SDKCTL_HANDSHAKE_RESP_NOPORT 1 +/* Handshake has failed due to duplicate connection request. */ +#define SDKCTL_HANDSHAKE_RESP_DUP -1 +/* Handshake has failed due to unknown query. */ +#define SDKCTL_HANDSHAKE_RESP_QUERY_UNKNOWN -2 + +/* A callback that is ivoked on handshake I/O events. */ +static AsyncIOAction +_on_handshake_io(void* query_opaque, + SDKCtlQuery* query, + AsyncIOState status) +{ + SDKCtlSocket* const sdkctl = (SDKCtlSocket*)query_opaque; + + if (status == ASIO_STATE_SUCCEEDED) { + const int* res = (const int*)(*query->response_buffer); + SdkCtlPortStatus handshake_status; + switch (*res) { + case SDKCTL_HANDSHAKE_RESP_CONNECTED: + D("SDKCtl %s: Handshake succeeded. Port is connected", + sdkctl->service_name); + handshake_status = SDKCTL_HANDSHAKE_CONNECTED; + break; + + case SDKCTL_HANDSHAKE_RESP_NOPORT: + D("SDKCtl %s: Handshake succeeded. Port is not connected", + sdkctl->service_name); + handshake_status = SDKCTL_HANDSHAKE_NO_PORT; + break; + + case SDKCTL_HANDSHAKE_RESP_DUP: + D("SDKCtl %s: Handshake failed: duplicate connection.", + sdkctl->service_name); + handshake_status = SDKCTL_HANDSHAKE_DUP; + break; + + case SDKCTL_HANDSHAKE_RESP_QUERY_UNKNOWN: + D("SDKCtl %s: Handshake failed: unknown query.", + sdkctl->service_name); + handshake_status = SDKCTL_HANDSHAKE_UNKNOWN_QUERY; + break; + + default: + E("SDKCtl %s: Unknown handshake response: %d", + sdkctl->service_name, *res); + handshake_status = SDKCTL_HANDSHAKE_UNKNOWN_RESPONSE; + break; + } + sdkctl->port_status = handshake_status; + sdkctl->on_port_connection(sdkctl->opaque, sdkctl, handshake_status); + } else { + /* Something is going on with the handshake... */ + switch (status) { + case ASIO_STATE_FAILED: + case ASIO_STATE_TIMED_OUT: + case ASIO_STATE_CANCELLED: + D("SDKCtl %s: Handshake failed: I/O state %d. Error: %d -> %s", + sdkctl->service_name, status, errno, strerror(errno)); + sdkctl->on_socket_connection(sdkctl->opaque, sdkctl, + ASIO_STATE_FAILED); + break; + + default: + break; + } + } + return ASIO_ACTION_DONE; +} + +static AsyncIOAction +_on_sdkctl_endianness_io(void* io_opaque, + AsyncSocketIO* asio, + AsyncIOState status) { + SDKCtlSocket* const sdkctl = (SDKCtlSocket*)io_opaque; + + if (status == ASIO_STATE_SUCCEEDED) { + /* Now it's time to initiate handshake message. */ + D("SDKCtl %s: Sending handshake query...", sdkctl->service_name); + SDKCtlQuery* query = + sdkctl_query_build_and_send(sdkctl, SDKCTL_QUERY_HANDSHAKE, + strlen(sdkctl->service_name), + sdkctl->service_name, NULL, NULL, + _on_handshake_io, sdkctl, 3000); + sdkctl_query_release(query); + return ASIO_ACTION_DONE; + } else { + /* Something is going on with the endianness... */ + switch (status) { + case ASIO_STATE_FAILED: + case ASIO_STATE_TIMED_OUT: + case ASIO_STATE_CANCELLED: + D("SDKCtl %s: endianness failed: I/O state %d. Error: %d -> %s", + sdkctl->service_name, status, errno, strerror(errno)); + sdkctl->on_socket_connection(sdkctl->opaque, sdkctl, ASIO_STATE_FAILED); + break; + + default: + break; + } + } + return ASIO_ACTION_DONE; +} + +static void +_sdkctl_do_handshake(SDKCtlSocket* sdkctl) +{ +#ifndef HOST_WORDS_BIGENDIAN +static const char _host_end = 0; +#else +static const char _host_end = 1; +#endif + + D("SDKCtl %s: Sending endianness: %d", sdkctl->service_name, _host_end); + + /* Before we can send any structured data to the SDK controller we need to + * report endianness of the host. */ + async_socket_write_rel(sdkctl->as, &_host_end, 1, + _on_sdkctl_endianness_io, sdkctl, 3000); +} diff --git a/android/sdk-controller-socket.h b/android/sdk-controller-socket.h new file mode 100644 index 0000000..e58a4e2 --- /dev/null +++ b/android/sdk-controller-socket.h @@ -0,0 +1,599 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ANDROID_SDKCONTROL_SOCKET_H_ +#define ANDROID_SDKCONTROL_SOCKET_H_ + +#include "android/async-socket.h" +#include "android/async-utils.h" + +/* + * Contains declaration of an API that encapsulates communication protocol with + * SdkController running on an Android device. + * + * SdkController is used to provide: + * + * - Realistic sensor emulation. + * - Multi-touch emulation. + * - Open for other types of emulation. + * + * The idea behind this type of emulation is such that there is an actual + * Android device that is connected via USB to the host running the emulator. + * On the device there is an SdkController service running that enables + * communication between an Android application that gathers information required + * by the emulator, and transmits that info to the emulator. + * + * SdkController service on the device, and SDKCtlSocket API implemented here + * implement the exchange protocol between an Android application, and emulation + * engine running inside the emulator. + * + * In turn, the exchange protocol is implemented on top of asynchronous socket + * communication (abstracted in AsyncSocket protocol implemented in + * android/async-socket.*). It means that connection, and all data transfer + * (both, in, and out) are completely asynchronous, and results of each operation + * are reported through callbacks. + * + * Essentially, this entire API implements two types of protocols: + * + * - Connection protocol. + * - Data exchange protocol. + * + * 1. Connection protocol. + * + * Connecting to SdkController service on the attached device can be broken down + * into two phases: + * - Connecting to a TCP socket. + * - Sending a "handshake" query to the SdkController. + * + * 1.1. Connecting to the socket. + * + * TCP socket connection with SdkController is enabled by using adb port + * forwarding. SdkController is always listening to a local abstract socket named + * 'android.sdk.controller', so to enable connecting to it from the host, run + * + * adb forward tcp:<port> localabstract: android.sdk.controller + * + * After that TCP socket for the requested port can be used to connect to + * SdkController, and connecting to it is no different than connecting to any + * socket server. Except for one thing: adb port forwarding is implemented in + * such a way, that socket_connect will always succeed, even if there is no + * server listening to that port on the other side of connection. Moreover, + * even socked_send will succeed in this case, so the only way to ensure that + * SdkController in deed is listening is to exchange a handshake with it: + * Fortunatelly, an attempt to read from forwarded TCP port on condition that + * there is no listener on the oher side will fail. + * + * 1.2. Handshake query. + * + * Handshake query is a special type of query that SDKCtlSocket sends to the + * SdkController upon successful socket connection. This query served two + * purposes: + * - Informs the SdkController about host endianness. This information is + * important, because SdkController needs it in order to format its messages + * with proper endianness. + * - Ensures that SdkController is in deed listening on the other side of the + * connected socket. + * + * Connection with SdkController is considered to be successfuly established when + * SdkController responds to the handshake query, thus, completing the connection. + * + * 2. Data exchange protocol. + * + * As it was mentioned above, all data transfer in this API is completely + * asynchronous, and result of each data transfer is reported via callbacks. + * This also complicates destruction of data involved in exchange, since in an + * asynchronous environment it's hard to control the lifespan of an object, its + * owner, and who and when is responsible to free resources allocated for the + * transfer. To address this issue, all the descriptors that this API operates + * with are referenced on use / released after use, and get freed when reference + * counter for them drops to zero, indicating that there is no component that is + * interested in that particular descriptor. + * + * There are three types of data in the exchange protocol: + * - A message - the simplest type of data that doesn't require any replies. + * - A query - A message that require a reply, and + * - A query reply - A message that delivers query reply. + */ + +/* Default TCP port to use for connection with SDK controller. */ +#define SDKCTL_DEFAULT_TCP_PORT 1970 + +/* Declares SDK controller socket descriptor. */ +typedef struct SDKCtlSocket SDKCtlSocket; + +/* Declares SDK controller message descriptor. */ +typedef struct SDKCtlMessage SDKCtlMessage; + +/* Declares SDK controller query descriptor. */ +typedef struct SDKCtlQuery SDKCtlQuery; + +/* Declares SDK controller direct packet descriptor. + * Direct packet (unlike message, or query packets) doesn't contain data buffer, + * but rather references message, or query data allocated by the client. + */ +typedef struct SDKCtlDirectPacket SDKCtlDirectPacket; + +/* Defines client's callback set to monitor SDK controller socket connection. + * + * SDKCtlSocket will invoke this callback when connection to TCP port is + * established, but before handshake query is processed. The client should use + * on_sdkctl_handshake_cb to receive notification about an operational connection + * with SdkController. + * + * The main purpose of this callback for the client is to monitor connection + * state: in addition to TCP port connection, this callback will be invoked when + * connection with the port is lost. + * + * Param: + * client_opaque - An opaque pointer associated with the client. + * sdkctl - Initialized SDKCtlSocket instance. + * status - Socket connection status. Can be one of these: + * - ASIO_STATE_SUCCEEDED : Socket is connected to the port. + * - ASIO_STATE_FAILED : Connection attempt has failed, or connection with + * the port is lost. + * Return: + * One of the AsyncIOAction values. + */ +typedef AsyncIOAction (*on_sdkctl_socket_connection_cb)(void* client_opaque, + SDKCtlSocket* sdkctl, + AsyncIOState status); + +/* Enumerates port connection statuses passed to port connection callback. + */ +typedef enum SdkCtlPortStatus { + /* Service-side port has connected to the socket. */ + SDKCTL_PORT_DISCONNECTED, + /* Service-side port has disconnected from the socket. */ + SDKCTL_PORT_CONNECTED, + /* Service-side port has enabled emulation */ + SDKCTL_PORT_ENABLED, + /* Service-side port has disabled emulation */ + SDKCTL_PORT_DISABLED, + /* Handshake request has succeeded, and service-side port is connected. */ + SDKCTL_HANDSHAKE_CONNECTED, + /* Handshake request has succeeded, but service-side port is not connected. */ + SDKCTL_HANDSHAKE_NO_PORT, + /* Handshake request has failed due to port duplication. */ + SDKCTL_HANDSHAKE_DUP, + /* Handshake request has failed on an unknown query. */ + SDKCTL_HANDSHAKE_UNKNOWN_QUERY, + /* Handshake request has failed on an unknown response. */ + SDKCTL_HANDSHAKE_UNKNOWN_RESPONSE, +} SdkCtlPortStatus; + +/* Defines client's callback set to receive port connection status. + * + * Port connection is different than socket connection, and indicates whether + * or not a service-side port that provides requested emulation functionality is + * hooked up with the connected socket. For instance, multi-touch port may be + * inactive at the time when socket is connected. So, there is a successful + * socket connection, but there is no service at the device end that provides + * multi-touch functionality. So, for multi-touch example, this callback will be + * invoked when multi-touch port at the device end becomes active, and hooks up + * with the socket that was connected before. + * + * Param: + * client_opaque - An opaque pointer associated with the client. + * sdkctl - Initialized SDKCtlSocket instance. + * status - Port connection status. + */ +typedef void (*on_sdkctl_port_connection_cb)(void* client_opaque, + SDKCtlSocket* sdkctl, + SdkCtlPortStatus status); + +/* Defines a message notification callback. + * Param: + * client_opaque - An opaque pointer associated with the client. + * sdkctl - Initialized SDKCtlSocket instance. + * message - Descriptor for received message. Note that message descriptor will + * be released upon exit from this callback (thus, could be freed along + * with message data). If the client is interested in working with that + * message after the callback returns, it should reference the message + * descriptor in this callback. + * msg_type - Message type. + * msg_data, msg_size - Message data. + */ +typedef void (*on_sdkctl_message_cb)(void* client_opaque, + SDKCtlSocket* sdkctl, + SDKCtlMessage* message, + int msg_type, + void* msg_data, + int msg_size); + +/* Defines query completion callback. + * Param: + * query_opaque - An opaque pointer associated with the query by the client. + * query - Query descriptor. Note that query descriptor will be released upon + * exit from this callback (thus, could be freed along with query data). If + * the client is interested in working with that query after the callback + * returns, it should reference the query descriptor in this callback. + * status - Query status. Can be one of these: + * - ASIO_STATE_CONTINUES : Query data has been transmitted to the service, + * and query is now waiting for response. + * - ASIO_STATE_SUCCEEDED : Query has been successfully completed. + * - ASIO_STATE_FAILED : Query has failed on an I/O. + * - ASIO_STATE_TIMED_OUT : Deadline set for the query has expired. + * - ASIO_STATE_CANCELLED : Query has been cancelled due to socket + * disconnection. + * Return: + * One of the AsyncIOAction values. + */ +typedef AsyncIOAction (*on_sdkctl_query_cb)(void* query_opaque, + SDKCtlQuery* query, + AsyncIOState status); + +/* Defines direct packet completion callback. + * Param: + * opaque - An opaque pointer associated with the direct packet by the client. + * packet - Packet descriptor. Note that packet descriptor will be released + * upon exit from this callback (thus, could be freed). If the client is + * interested in working with that packet after the callback returns, it + * should reference the packet descriptor in this callback. + * status - Packet status. Can be one of these: + * - ASIO_STATE_SUCCEEDED : Packet has been successfully sent. + * - ASIO_STATE_FAILED : Packet has failed on an I/O. + * - ASIO_STATE_CANCELLED : Packet has been cancelled due to socket + * disconnection. + * Return: + * One of the AsyncIOAction values. + */ +typedef AsyncIOAction (*on_sdkctl_direct_cb)(void* opaque, + SDKCtlDirectPacket* packet, + AsyncIOState status); + +/******************************************************************************** + * SDKCtlDirectPacket API + ********************************************************************************/ + +/* Creates new SDKCtlDirectPacket descriptor. + * Param: + * sdkctl - Initialized SDKCtlSocket instance to create a direct packet for. + * Return: + * Referenced SDKCtlDirectPacket instance. + */ +extern SDKCtlDirectPacket* sdkctl_direct_packet_new(SDKCtlSocket* sdkctl); + +/* References SDKCtlDirectPacket object. + * Param: + * packet - Initialized SDKCtlDirectPacket instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_direct_packet_reference(SDKCtlDirectPacket* packet); + +/* Releases SDKCtlDirectPacket object. + * Note that upon exiting from this routine the object might be destroyed, even + * if this routine returns value other than zero. + * Param: + * packet - Initialized SDKCtlDirectPacket instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_direct_packet_release(SDKCtlDirectPacket* packet); + +/* Sends direct packet. + * Param: + * packet - Packet descriptor for the direct packet to send. + * data - Data to send with the packet. Must be fully initialized message, or + * query header. + * cb, cb_opaque - Callback to invoke on packet transmission events. + */ +extern void sdkctl_direct_packet_send(SDKCtlDirectPacket* packet, + void* data, + on_sdkctl_direct_cb cb, + void* cb_opaque); + +/******************************************************************************** + * SDKCtlMessage API + ********************************************************************************/ + +/* References SDKCtlMessage object. + * Param: + * msg - Initialized SDKCtlMessage instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_message_reference(SDKCtlMessage* msg); + +/* Releases SDKCtlMessage object. + * Note that upon exiting from this routine the object might be destroyed, even + * if this routine returns value other than zero. + * Param: + * msg - Initialized SDKCtlMessage instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_message_release(SDKCtlMessage* msg); + +/* Builds and sends a message to the device. + * Param: + * sdkctl - SDKCtlSocket instance for the message. + * msg_type - Defines message type. + * data - Message data. Can be NULL if there is no data associated with the + * message. + * size - Byte size of the data buffer. + * Return: + * Referenced SDKCtlQuery descriptor. + */ +extern SDKCtlMessage* sdkctl_message_send(SDKCtlSocket* sdkctl, + int msg_type, + const void* data, + uint32_t size); + +/* Gets message header size */ +extern int sdkctl_message_get_header_size(void); + +/* Initializes message header. + * Param: + * msg - Beginning of the message packet. + * msg_type - Message type. + * msg_size - Message data size. + */ +extern void sdkctl_init_message_header(void* msg, int msg_type, int msg_size); + +/******************************************************************************** + * SDKCtlQuery API + ********************************************************************************/ + +/* Creates, and partially initializes query descriptor. + * Note that returned descriptor is referenced, and it must be eventually + * released with a call to sdkctl_query_release. + * Param: + * sdkctl - SDKCtlSocket instance for the query. + * query_type - Defines query type. + * in_data_size Size of the query's input buffer (data to be sent with this + * query). Note that buffer for query data will be allocated along with the + * query descriptor. Use sdkctl_query_get_buffer_in to get address of data + * buffer for this query. + * Return: + * Referenced SDKCtlQuery descriptor. + */ +extern SDKCtlQuery* sdkctl_query_new(SDKCtlSocket* sdkctl, + int query_type, + uint32_t in_data_size); + +/* Creates, and fully initializes query descriptor. + * Note that returned descriptor is referenced, and it must be eventually + * released with a call to sdkctl_query_release. + * Param: + * sdkctl - SDKCtlSocket instance for the query. + * query_type - Defines query type. + * in_data_size Size of the query's input buffer (data to be sent with this + * query). Note that buffer for query data will be allocated along with the + * query descriptor. Use sdkctl_query_get_buffer_in to get address of data + * buffer for this query. + * in_data - Data to initialize query's input buffer with. + * response_buffer - Contains address of the buffer addressing preallocated + * response buffer on the way in, and address of the buffer containing query + * response on query completion. If this parameter is NULL, the API will + * allocate its own query response buffer, which is going to be freed after + * query completion. + * response_size - Contains size of preallocated response buffer on the way in, + * and size of the received response on query completion. Can be NULL. + * query_cb - A callback to monitor query state. + * query_opaque - An opaque pointer associated with the query. + * Return: + * Referenced SDKCtlQuery descriptor. + */ +extern SDKCtlQuery* sdkctl_query_new_ex(SDKCtlSocket* sdkctl, + int query_type, + uint32_t in_data_size, + const void* in_data, + void** response_buffer, + uint32_t* response_size, + on_sdkctl_query_cb query_cb, + void* query_opaque); + +/* Sends query to SDK controller. + * Param: + * query - Query to send. Note that this must be a fully initialized query + * descriptor. + * to - Milliseconds to allow for the query to complete. Negative value means + * "forever". + */ +extern void sdkctl_query_send(SDKCtlQuery* query, int to); + +/* Creates, fully initializes query descriptor, and sends the query to SDK + * controller. + * Note that returned descriptor is referenced, and it must be eventually + * released with a call to sdkctl_query_release. + * Param: + * sdkctl - SDKCtlSocket instance for the query. + * query_type - Defines query type. + * in_data_size Size of the query's input buffer (data to be sent with this + * query). Note that buffer for query data will be allocated along with the + * query descriptor. Use sdkctl_query_get_buffer_in to get address of data + * buffer for this query. + * in_data - Data to initialize query's input buffer with. + * response_buffer - Contains address of the buffer addressing preallocated + * response buffer on the way in, and address of the buffer containing query + * response on query completion. If this parameter is NULL, the API will + * allocate its own query response buffer, which is going to be freed after + * query completion. + * response_size - Contains size of preallocated response buffer on the way in, + * and size of the received response on query completion. Can be NULL. + * query_cb - A callback to monitor query state. + * query_opaque - An opaque pointer associated with the query. + * to - Milliseconds to allow for the query to complete. Negative value means + * "forever". + * Return: + * Referenced SDKCtlQuery descriptor for the query that has been sent. + */ +extern SDKCtlQuery* sdkctl_query_build_and_send(SDKCtlSocket* sdkctl, + int query_type, + uint32_t in_data_size, + const void* in_data, + void** response_buffer, + uint32_t* response_size, + on_sdkctl_query_cb query_cb, + void* query_opaque, + int to); + +/* References SDKCtlQuery object. + * Param: + * query - Initialized SDKCtlQuery instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_query_reference(SDKCtlQuery* query); + +/* Releases SDKCtlQuery object. + * Note that upon exit from this routine the object might be destroyed, even if + * this routine returns value other than zero. + * Param: + * query - Initialized SDKCtlQuery instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_query_release(SDKCtlQuery* query); + +/* Gets address of query's input data buffer (data to be send). + * Param: + * query - Query to get data buffer for. + * Return: + * Address of query's input data buffer. + */ +extern void* sdkctl_query_get_buffer_in(SDKCtlQuery* query); + +/* Gets address of query's output data buffer (response data). + * Param: + * query - Query to get data buffer for. + * Return: + * Address of query's output data buffer. + */ +extern void* sdkctl_query_get_buffer_out(SDKCtlQuery* query); + +/******************************************************************************** + * SDKCtlSocket API + ********************************************************************************/ + +/* Creates an SDK controller socket descriptor. + * Param: + * reconnect_to - Timeout before trying to reconnect, or retry connection + * attempts after disconnection, or on connection failures. + * service_name - Name of the SdkController service for this socket (such as + * 'sensors', 'milti-touch', etc.) + * on_socket_connection - A callback to invoke on socket connection events. + * on_port_connection - A callback to invoke on port connection events. + * on_message - A callback to invoke when a message is received from the SDK + * controller. + * opaque - An opaque pointer to associate with the socket. + * Return: + * Initialized SDKCtlSocket instance on success, or NULL on failure. + */ +extern SDKCtlSocket* sdkctl_socket_new(int reconnect_to, + const char* service_name, + on_sdkctl_socket_connection_cb on_socket_connection, + on_sdkctl_port_connection_cb on_port_connection, + on_sdkctl_message_cb on_message, + void* opaque); + +/* Improves throughput by recycling memory allocated for buffers transferred via + * this API. + * + * In many cases data exchanged between SDK controller sides are small, and, + * although may come quite often, are coming in a sequential manner. For instance, + * sensor service on the device may send us sensor updates every 20ms, one after + * another. For such data traffic it makes perfect sense to recycle memory + * allocated for the previous sensor update, rather than to free it just to + * reallocate same buffer in 20ms. This routine sets properties of the recycler + * for the given SDK controller connection. Recycling includes memory allocated + * for all types of data transferred in this API: packets, and queries. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * data_size - Size of buffer to allocate for each data block. + * max_recycled_num - Maximum number of allocated buffers to keep in the + * recycler. + */ +extern void sdkctl_init_recycler(SDKCtlSocket* sdkctl, + uint32_t data_size, + int max_recycled_num); + +/* References SDKCtlSocket object. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_socket_reference(SDKCtlSocket* sdkctl); + +/* Releases SDKCtlSocket object. + * Note that upon exit from this routine the object might be destroyed, even if + * this routine returns value other than zero. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * Return: + * Number of outstanding references to the object. + */ +extern int sdkctl_socket_release(SDKCtlSocket* sdkctl); + +/* Asynchronously connects to SDK controller. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * port - TCP port to connect the socket to. + * retry_to - Number of milliseconds to wait before retrying a failed + * connection attempt. + */ +extern void sdkctl_socket_connect(SDKCtlSocket* sdkctl, int port, int retry_to); + +/* Asynchronously reconnects to SDK controller. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * port - TCP port to reconnect the socket to. + * retry_to - Number of milliseconds to wait before reconnecting. Same timeout + * will be used for retrying a failed connection attempt. + */ +extern void sdkctl_socket_reconnect(SDKCtlSocket* sdkctl, int port, int retry_to); + +/* Disconnects from SDK controller. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + */ +extern void sdkctl_socket_disconnect(SDKCtlSocket* sdkctl); + +/* Checks if SDK controller socket is connected. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * Return: + * Boolean: 1 if socket is connected, 0 if socket is not connected. + */ +extern int sdkctl_socket_is_connected(SDKCtlSocket* sdkctl); + +/* Checks if SDK controller port is ready for emulation. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * Return: + * Boolean: 1 if port is ready, 0 if port is not ready. + */ +extern int sdkctl_socket_is_port_ready(SDKCtlSocket* sdkctl); + +/* Gets status of the SDK controller port for this socket. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * Return: + * Status of the SDK controller port for this socket. + */ +extern SdkCtlPortStatus sdkctl_socket_get_port_status(SDKCtlSocket* sdkctl); + +/* Checks if handshake was successful. + * Param: + * sdkctl - Initialized SDKCtlSocket instance. + * Return: + * Boolean: 1 if handshake was successful, 0 if handshake was not successful. + */ +extern int sdkctl_socket_is_handshake_ok(SDKCtlSocket* sdkctl); + +#endif /* ANDROID_SDKCONTROL_SOCKET_H_ */ diff --git a/android/sensors-port.c b/android/sensors-port.c index 9e9351d..6831fe3 100644 --- a/android/sensors-port.c +++ b/android/sensors-port.c @@ -14,328 +14,474 @@ * limitations under the License. */ +#include "android/sdk-controller-socket.h" #include "android/sensors-port.h" #include "android/hw-sensors.h" +#include "android/utils/debug.h" #define E(...) derror(__VA_ARGS__) #define W(...) dwarning(__VA_ARGS__) #define D(...) VERBOSE_PRINT(sensors_port,__VA_ARGS__) #define D_ACTIVE VERBOSE_CHECK(sensors_port) -/* Maximum number of sensors supported. */ -#define ASP_MAX_SENSOR 12 +#define TRACE_ON 1 -/* Maximum length of a sensor message. */ -#define ASP_MAX_SENSOR_MSG 1024 +#if TRACE_ON +#define T(...) VERBOSE_PRINT(sensors_port,__VA_ARGS__) +#else +#define T(...) +#endif -/* Maximum length of a sensor event. */ -#define ASP_MAX_SENSOR_EVENT 256 +/* Timeout (millisec) to use when communicating with SDK controller. */ +#define SDKCTL_SENSORS_TIMEOUT 3000 -/* Query timeout in milliseconds. */ -#define ASP_QUERY_TIMEOUT 3000 +/* + * Queries sent to sensors port of the SDK controller. + */ + +/* Queries the port for list of available sensors. */ +#define SDKCTL_SENSORS_QUERY_LIST 1 + +/* + * Messages sent between the emuator, and sensors port of the SDK controller. + */ + +/* Starts sensor emulation. */ +#define SDKCTL_SENSORS_START 1 +/* Stops sensor emulation. */ +#define SENSOR_SENSORS_STOP 2 +/* Enables emulation for a sensor. */ +#define SDKCTL_SENSORS_ENABLE 3 +/* Disables emulation for a sensor. */ +#define SDKCTL_SENSORS_DISABLE 4 +/* This message delivers sensor values. */ +#define SDKCTL_SENSORS_SENSOR_EVENT 5 + + +/* Describes a sensor on the device. + * When SDK controller sensors port replies to a "list" query, it replies with + * a flat buffer containing entries of this type following each other. End of + * each entry is a zero-terminator for its 'sensor_name' field. The end of the + * entire list is marked with an entry, containing -1 at its 'sensor_id' field. + */ +typedef struct SensorEntry { + /* Identifies sensor on the device. Value -1 indicates list terminator, + * rather than a valid sensor descriptor. */ + int sensor_id; + /* Beginning of zero-terminated sensor name. */ + char sensor_name[1]; +} SensorEntry; + +/* Describes a sensor in the array of emulated sensors. */ +typedef struct SensorDescriptor { + /* Identifies sensor on the device. */ + int sensor_id; + /* Identifies sensor in emulator. */ + int emulator_id; + /* Sensor name. */ + char* sensor_name; +} SensorDescriptor; + +/* Sensor event message descriptor. + * Entries of this type are sent along with SDKCTL_SENSORS_SENSOR_EVENT message + */ +typedef struct SensorEvent { + /* Identifies a device sensor for which values have been delivered. */ + int sensor_id; + /* Sensor values. */ + float fvalues[3]; +} SensorEvent; /* Sensors port descriptor. */ struct AndroidSensorsPort { /* Caller identifier. */ - void* opaque; - /* Connected android device. */ - AndroidDevice* device; - /* String containing list of all available sensors. */ - char sensors[ASP_MAX_SENSOR * 64]; - /* Array of available sensor names. Note that each string in this array - * points inside the 'sensors' buffer. */ - const char* sensor_list[ASP_MAX_SENSOR]; - /* Number of available sensors. */ - int sensors_num; - /* Connection status: 1 connected, 0 - disconnected. */ - int is_connected; - /* Buffer where to receive sensor messages. */ - char sensor_msg[ASP_MAX_SENSOR_MSG]; - /* Buffer where to receive sensor events. */ - char events[ASP_MAX_SENSOR_EVENT]; + void* opaque; + /* Communication socket. */ + SDKCtlSocket* sdkctl; + /* Lists sensors available for emulation. */ + SensorDescriptor** sensors; + /* Number of sensors in 'sensors' list. */ + int sensors_count; }; +/******************************************************************************** + * Sensors port internals + *******************************************************************************/ + +/* Checks if sensor descriptor is the terminator. + * Return: + * Boolean, 1 if it is a terminator, 0 if it is not. + */ +static int +_sensor_entry_is_terminator(const SensorEntry* entry) +{ + return entry == NULL || entry->sensor_id == -1; +} + +/* Gets next sensor descriptor. + * Return: + * Next sensor desciptor, or NULL if there are no more descriptors in the list. + */ +static const SensorEntry* +_sensor_entry_next(const SensorEntry* entry) +{ + if (!_sensor_entry_is_terminator(entry)) { + /* Next descriptor begins right after zero-terminator for the sensor_name + * field of this descriptor. */ + entry = (const SensorEntry*)(entry->sensor_name + strlen(entry->sensor_name) + 1); + if (!_sensor_entry_is_terminator(entry)) { + return entry; + } + } + return NULL; +} + +/* Gets number of entries in the list. */ +static int +_sensor_entry_list_size(const SensorEntry* entry) { + int ret = 0; + while (!_sensor_entry_is_terminator(entry)) { + ret++; + entry = _sensor_entry_next(entry); + } + return ret; +} + +/* Discards sensors saved in AndroidSensorsPort's array. */ +static void +_sensors_port_discard_sensors(AndroidSensorsPort* asp) +{ + if (asp->sensors != NULL) { + int n; + for (n = 0; n < asp->sensors_count; n++) { + if (asp->sensors[n] != NULL) { + free(asp->sensors[n]->sensor_name); + AFREE(asp->sensors[n]); + } + } + free(asp->sensors); + asp->sensors = NULL; + } + asp->sensors_count = 0; +} + + /* Destroys and frees the descriptor. */ static void _sensors_port_free(AndroidSensorsPort* asp) { if (asp != NULL) { - if (asp->device != NULL) { - android_device_destroy(asp->device); + _sensors_port_discard_sensors(asp); + if (asp->sdkctl != NULL) { + sdkctl_socket_release(asp->sdkctl); } AFREE(asp); } } -/******************************************************************************** - * Sensors port callbacks - *******************************************************************************/ - -/* A callback that invoked on sensor events. - * Param: - * opaque - AndroidSensorsPort instance. - * ad - Android device used by this sensors port. - * msg, msgsize - Sensor event message - * failure - Message receiving status. - */ +/* Parses flat sensor list, and saves its entries into 'sensors' array filed of + * the AndroidSensorsPort descriptor. */ static void -_on_sensor_received(void* opaque, AndroidDevice* ad, char* msg, int msgsize) +_sensors_port_save_sensors(AndroidSensorsPort* asp, const SensorEntry* list) { - float fvalues[3] = {0, 0, 0}; - char sensor[ASP_MAX_SENSOR_MSG]; - char* value; - int id; - AndroidSensorsPort* asp = (AndroidSensorsPort*)opaque; - - if (errno) { - D("Sensors notification has failed on sensors port: %s", strerror(errno)); - return; - } - - /* Parse notification, separating sensor name from parameters. */ - memcpy(sensor, msg, msgsize); - value = strchr(sensor, ':'); - if (value == NULL) { - W("Bad format for sensor notification: %s", msg); - return; - } - sensor[value-sensor] = '\0'; - value++; - - id = android_sensors_get_id_from_name(sensor); - if (id >= 0) { - /* Parse the value part to get the sensor values(a, b, c) */ - int i; - char* pnext; - char* pend = value + strlen(value); - for (i = 0; i < 3; i++, value = pnext + 1) { - pnext=strchr( value, ':' ); - if (pnext) { - *pnext = 0; + const int count = _sensor_entry_list_size(list); + if (count != 0) { + int n; + /* Allocate array for sensor descriptors. */ + asp->sensors = malloc(sizeof(SensorDescriptor*) * count); + + /* Iterate through the flat sensor list, filling up array of emulated + * sensors. */ + const SensorEntry* entry = _sensor_entry_is_terminator(list) ? NULL : list; + for (n = 0; n < count && entry != NULL; n++) { + /* Get emulator-side ID for the sensor. < 0 value indicates that + * sensor is not supported by the emulator. */ + const int emulator_id = + android_sensors_get_id_from_name((char*)entry->sensor_name); + if (emulator_id >= 0) { + SensorDescriptor* desc; + ANEW0(desc); + desc->emulator_id = emulator_id; + desc->sensor_id = entry->sensor_id; + desc->sensor_name = ASTRDUP(entry->sensor_name); + + asp->sensors[asp->sensors_count++] = desc; + D("Sensors: Emulated sensor '%s': Device id = %d, Emulator id = %d", + desc->sensor_name, desc->sensor_id, desc->emulator_id); } else { - pnext = pend; - } - - if (pnext > value) { - if (1 != sscanf( value,"%g", &fvalues[i] )) { - W("Bad parameters in sensor notification %s", msg); - return; - } + D("Sensors: Sensor '%s' is not support by emulator", + entry->sensor_name); } + entry = _sensor_entry_next(entry); } - android_sensors_set(id, fvalues[0], fvalues[1], fvalues[2]); - } else { - W("Unknown sensor name '%s' in '%s'", sensor, msg); + D("Sensors: Emulating %d sensors", asp->sensors_count); } - - /* Listen to the next event. */ - android_device_listen(ad, asp->events, sizeof(asp->events), _on_sensor_received); } -/* A callback that is invoked when android device is connected (i.e. both, command - * and event channels have been stablished. - * Param: - * opaque - AndroidSensorsPort instance. - * ad - Android device used by this sensors port. - * failure - Connections status. - */ -static void -_on_device_connected(void* opaque, AndroidDevice* ad, int failure) +/* Finds sensor descriptor for an SDK controller-side ID. */ +static const SensorDescriptor* +_sensor_from_sdkctl_id(AndroidSensorsPort* asp, int id) { - if (!failure) { - AndroidSensorsPort* asp = (AndroidSensorsPort*)opaque; - asp->is_connected = 1; - D("Sensor emulation has started"); - /* Initialize sensors on device. */ - sensors_port_init_sensors(asp); + int n; + for (n = 0; n < asp->sensors_count; n++) { + if (asp->sensors[n]->sensor_id == id) { + return asp->sensors[n]; + } } + return NULL; } -/* Invoked when an I/O failure occurs on a socket. - * Note that this callback will not be invoked on connection failures. +/* Initiates sensor emulation. * Param: - * opaque - AndroidSensorsPort instance. - * ad - Android device instance - * ads - Connection socket where failure has occured. - * failure - Contains 'errno' indicating the reason for failure. + * asp - Android sensors port instance returned from sensors_port_create. + * Return: + * Zero on success, failure otherwise. */ static void -_on_io_failure(void* opaque, AndroidDevice* ad, int failure) +_sensors_port_start(AndroidSensorsPort* asp) { - AndroidSensorsPort* asp = (AndroidSensorsPort*)opaque; - E("Sensors port got disconnected: %s", strerror(failure)); - asp->is_connected = false; - android_device_disconnect(ad); - android_device_connect_async(ad, _on_device_connected); + int n; + + if (!sdkctl_socket_is_port_ready(asp->sdkctl)) { + /* SDK controller side is not ready for emulation. Retreat... */ + D("Sensors: SDK controller side is not ready for emulation."); + return; + } + + /* Disable all sensors, and reenable only those that are emulated by + * hardware. */ + sensors_port_disable_sensor(asp, "all"); + + /* Walk throuh the list of enabled sensors enabling them on the device. */ + for (n = 0; n < asp->sensors_count; n++) { + if (android_sensors_get_sensor_status(asp->sensors[n]->emulator_id) == 1) { + /* Reenable emulation for this sensor. */ + sensors_port_enable_sensor(asp, asp->sensors[n]->sensor_name); + D("Sensors: Sensor '%s' is enabled on SDK controller.", + asp->sensors[n]->sensor_name); + } + } + + /* Start the emulation. */ + SDKCtlMessage* const msg = + sdkctl_message_send(asp->sdkctl, SDKCTL_SENSORS_START, NULL, 0); + sdkctl_message_release(msg); + + D("Sensors: Emulation has been started."); } /******************************************************************************** - * Sensors port API + * Sensors port callbacks *******************************************************************************/ -AndroidSensorsPort* -sensors_port_create(void* opaque) +/* Completion for the "list" query. */ +static AsyncIOAction +_on_sensor_list_query(void* query_opaque, + SDKCtlQuery* query, + AsyncIOState status) { - AndroidSensorsPort* asp; - char* wrk; - int res; + AndroidSensorsPort* const asp = (AndroidSensorsPort*)(query_opaque); + if (status != ASIO_STATE_SUCCEEDED) { + /* We don't really care about failures at this point. They will + * eventually surface up in another place. */ + return ASIO_ACTION_DONE; + } - ANEW0(asp); - asp->opaque = opaque; - asp->is_connected = 0; + /* Parse query response which is a flat list of SensorEntry entries. */ + const SensorEntry* const list = + (const SensorEntry*)sdkctl_query_get_buffer_out(query); + D("Sensors: Sensor list received with %d sensors.", + _sensor_entry_list_size(list)); + _sensors_port_save_sensors(asp, list); - asp->device = android_device_init(asp, AD_SENSOR_PORT, _on_io_failure); - if (asp->device == NULL) { - _sensors_port_free(asp); - return NULL; - } + /* At this point we are ready to statr sensor emulation. */ + _sensors_port_start(asp); - res = android_device_connect_sync(asp->device, ASP_QUERY_TIMEOUT); - if (res != 0) { - sensors_port_destroy(asp); - return NULL; - } + return ASIO_ACTION_DONE; +} - res = android_device_query(asp->device, "list", - asp->sensors, sizeof(asp->sensors), - ASP_QUERY_TIMEOUT); - if (res != 0) { - sensors_port_destroy(asp); - return NULL; +/* A callback that is invoked on sensor events. + * Param: + * asp - AndroidSensorsPort instance. + * event - Sensor event. + */ +static void +_on_sensor_event(AndroidSensorsPort* asp, const SensorEvent* event) +{ + /* Find corresponding server descriptor. */ + const SensorDescriptor* const desc = + _sensor_from_sdkctl_id(asp, event->sensor_id); + if (desc != NULL) { + T("Sensors: %s -> %f, %f, %f", desc->sensor_name, + event->fvalues[0], event->fvalues[1], + event->fvalues[2]); + /* Fire up sensor change in the guest. */ + android_sensors_set(desc->emulator_id, event->fvalues[0], + event->fvalues[1], event->fvalues[2]); + } else { + W("Sensors: No descriptor for sensor %d", event->sensor_id); } +} - /* Parse sensor list. */ - asp->sensors_num = 0; - wrk = asp->sensors; - - while (wrk != NULL && *wrk != '\0' && *wrk != '\n') { - asp->sensor_list[asp->sensors_num] = wrk; - asp->sensors_num++; - wrk = strchr(wrk, '\n'); - if (wrk != NULL) { - *wrk = '\0'; wrk++; +/* A callback that is invoked on SDK controller socket connection events. */ +static AsyncIOAction +_on_sensors_socket_connection(void* client_opaque, + SDKCtlSocket* sdkctl, + AsyncIOState status) +{ + AndroidSensorsPort* const asp = (AndroidSensorsPort*)client_opaque; + if (status == ASIO_STATE_FAILED) { + /* Disconnection could mean that user is swapping devices. New device may + * have different set of sensors, so we need to re-query sensor list on + * reconnection. */ + _sensors_port_discard_sensors(asp); + + /* Reconnect (after timeout delay) on failures */ + if (sdkctl_socket_is_handshake_ok(sdkctl)) { + sdkctl_socket_reconnect(sdkctl, SDKCTL_DEFAULT_TCP_PORT, + SDKCTL_SENSORS_TIMEOUT); } } - - android_device_listen(asp->device, asp->events, sizeof(asp->events), - _on_sensor_received); - return asp; + return ASIO_ACTION_DONE; } -int -sensors_port_init_sensors(AndroidSensorsPort* asp) +/* A callback that is invoked on SDK controller port connection events. */ +static void +_on_sensors_port_connection(void* client_opaque, + SDKCtlSocket* sdkctl, + SdkCtlPortStatus status) { - int res, id; + AndroidSensorsPort* const asp = (AndroidSensorsPort*)client_opaque; + switch (status) { + case SDKCTL_PORT_CONNECTED: { + D("Sensors: SDK Controller is connected."); + /* Query list of available sensors. */ + SDKCtlQuery* const query = + sdkctl_query_build_and_send(asp->sdkctl, SDKCTL_SENSORS_QUERY_LIST, + 0, NULL, NULL, NULL, + _on_sensor_list_query, asp, + SDKCTL_SENSORS_TIMEOUT); + sdkctl_query_release(query); + break; + } - /* Disable all sensors for now. Reenable only those that are emulated. */ - res = sensors_port_disable_sensor(asp, "all"); - if (res) { - return res; + case SDKCTL_PORT_DISCONNECTED: + _sensors_port_discard_sensors(asp); + D("Sensors: SDK Controller is disconnected."); + break; + + case SDKCTL_PORT_ENABLED: + _sensors_port_start(asp); + D("Sensors: SDK Controller is enabled."); + break; + + case SDKCTL_PORT_DISABLED: + D("Sensors: SDK Controller is disabled."); + break; + + case SDKCTL_HANDSHAKE_CONNECTED: + D("Sensors: SDK Controller has succeeded handshake, and port is connected."); + break; + + case SDKCTL_HANDSHAKE_NO_PORT: + D("Sensors: SDK Controller has succeeded handshake, and port is not connected."); + break; + + case SDKCTL_HANDSHAKE_DUP: + E("Sensors: SDK Controller has failed the handshake due to port duplication."); + sdkctl_socket_disconnect(sdkctl); + break; + + case SDKCTL_HANDSHAKE_UNKNOWN_QUERY: + E("Sensors: SDK Controller has failed the handshake due to unknown query."); + sdkctl_socket_disconnect(sdkctl); + break; + + case SDKCTL_HANDSHAKE_UNKNOWN_RESPONSE: + default: + E("Sensors: Handshake has failed due to unknown reasons."); + sdkctl_socket_disconnect(sdkctl); + break; } +} - /* Start listening on sensor events. */ - res = android_device_listen(asp->device, asp->events, sizeof(asp->events), - _on_sensor_received); - if (res) { - return res; +/* A callback that is invoked when a message is received from SDK controller. */ +static void +_on_sensors_message(void* client_opaque, + SDKCtlSocket* sdkctl, + SDKCtlMessage* message, + int msg_type, + void* msg_data, + int msg_size) +{ + AndroidSensorsPort* const asp = (AndroidSensorsPort*)client_opaque; + switch (msg_type) { + case SDKCTL_SENSORS_SENSOR_EVENT: + _on_sensor_event(asp, (const SensorEvent*)msg_data); + break; + + default: + E("Sensors: Unknown message type %d", msg_type); + break; } +} - /* Walk throuh the list of enabled sensors enabling them on the device. */ - for (id = 0; id < MAX_SENSORS; id++) { - if (android_sensors_get_sensor_status(id) == 1) { - res = sensors_port_enable_sensor(asp, android_sensors_get_name_from_id(id)); - if (res == 0) { - D("Sensor '%s' is enabled on the device.", - android_sensors_get_name_from_id(id)); - } - } - } +/******************************************************************************** + * Sensors port API + *******************************************************************************/ + +AndroidSensorsPort* +sensors_port_create(void* opaque) +{ + AndroidSensorsPort* asp; - /* Start sensor events. */ - return sensors_port_start(asp); + ANEW0(asp); + asp->opaque = opaque; + asp->sensors = NULL; + asp->sensors_count = 0; + asp->sdkctl = sdkctl_socket_new(SDKCTL_SENSORS_TIMEOUT, "sensors", + _on_sensors_socket_connection, + _on_sensors_port_connection, + _on_sensors_message, asp); + sdkctl_init_recycler(asp->sdkctl, 76, 8); + sdkctl_socket_connect(asp->sdkctl, SDKCTL_DEFAULT_TCP_PORT, + SDKCTL_SENSORS_TIMEOUT); + return asp; } void sensors_port_destroy(AndroidSensorsPort* asp) { + if (asp->sdkctl != NULL) { + sdkctl_socket_disconnect(asp->sdkctl); + } _sensors_port_free(asp); } int -sensors_port_is_connected(AndroidSensorsPort* asp) -{ - return asp->is_connected; -} - -int sensors_port_enable_sensor(AndroidSensorsPort* asp, const char* name) { - char query[1024]; - char qresp[1024]; - snprintf(query, sizeof(query), "enable:%s", name); - const int res = - android_device_query(asp->device, query, qresp, sizeof(qresp), - ASP_QUERY_TIMEOUT); - if (res) { - if (errno) { - D("Query '%s' failed on I/O: %s", query, strerror(errno)); - } else { - D("Query '%s' failed on device: %s", query, qresp); - } + if (asp->sdkctl != NULL && sdkctl_socket_is_port_ready(asp->sdkctl)) { + SDKCtlMessage* const msg = sdkctl_message_send(asp->sdkctl, + SDKCTL_SENSORS_ENABLE, + name, strlen(name)); + sdkctl_message_release(msg); + return 0; + } else { + return -1; } - return res; } int sensors_port_disable_sensor(AndroidSensorsPort* asp, const char* name) { - char query[1024]; - char qresp[1024]; - snprintf(query, sizeof(query), "disable:%s", name); - const int res = - android_device_query(asp->device, query, qresp, sizeof(qresp), - ASP_QUERY_TIMEOUT); - if (res) { - if (errno) { - D("Query '%s' failed on I/O: %s", query, strerror(errno)); - } else { - D("Query '%s' failed on device: %s", query, qresp); - } - } - return res; -} - -int -sensors_port_start(AndroidSensorsPort* asp) -{ - char qresp[ASP_MAX_SENSOR_MSG]; - const int res = - android_device_query(asp->device, "start", qresp, sizeof(qresp), - ASP_QUERY_TIMEOUT); - if (res) { - if (errno) { - D("Query 'start' failed on I/O: %s", strerror(errno)); - } else { - D("Query 'start' failed on device: %s", qresp); - } - } - return res; -} - -int -sensors_port_stop(AndroidSensorsPort* asp) -{ - char qresp[ASP_MAX_SENSOR_MSG]; - const int res = - android_device_query(asp->device, "stop", qresp, sizeof(qresp), - ASP_QUERY_TIMEOUT); - if (res) { - if (errno) { - D("Query 'stop' failed on I/O: %s", strerror(errno)); - } else { - D("Query 'stop' failed on device: %s", qresp); - } + if (asp->sdkctl != NULL && sdkctl_socket_is_port_ready(asp->sdkctl)) { + SDKCtlMessage* const msg = sdkctl_message_send(asp->sdkctl, + SDKCTL_SENSORS_DISABLE, + name, strlen(name)); + sdkctl_message_release(msg); + return 0; + } else { + return -1; } - - return res; } diff --git a/android/sensors-port.h b/android/sensors-port.h index dc5c966..a35d700 100644 --- a/android/sensors-port.h +++ b/android/sensors-port.h @@ -23,8 +23,6 @@ * the host via USB. */ -#include "android/android-device.h" - /* Declares sensors port descriptor. */ typedef struct AndroidSensorsPort AndroidSensorsPort; @@ -42,15 +40,6 @@ extern AndroidSensorsPort* sensors_port_create(void* opaque); /* Disconnects from the sensors port, and destroys the descriptor. */ extern void sensors_port_destroy(AndroidSensorsPort* asp); -/* Initializes sensors on the connected device. */ -extern int sensors_port_init_sensors(AndroidSensorsPort* asp); - -/* Checks if port is connected to a sensor reading application on the device. - * Note that connection can go out and then be restored at any time after - * sensors_port_create API succeeded. - */ -extern int sensors_port_is_connected(AndroidSensorsPort* asp); - /* Enables events from a particular sensor. * Param: * asp - Android sensors port instance returned from sensors_port_create. @@ -72,20 +61,4 @@ extern int sensors_port_enable_sensor(AndroidSensorsPort* asp, const char* name) */ extern int sensors_port_disable_sensor(AndroidSensorsPort* asp, const char* name); -/* Queries the connected application to start delivering sensor events. - * Param: - * asp - Android sensors port instance returned from sensors_port_create. - * Return: - * Zero on success, failure otherwise. - */ -extern int sensors_port_start(AndroidSensorsPort* asp); - -/* Queries the connected application to stop delivering sensor events. - * Param: - * asp - Android sensors port instance returned from sensors_port_create. - * Return: - * Zero on success, failure otherwise. - */ -extern int sensors_port_stop(AndroidSensorsPort* asp); - #endif /* ANDROID_SENSORS_PORT_H_ */ diff --git a/android/tools/gen-hw-config.py b/android/tools/gen-hw-config.py index 3822485..201ef04 100755 --- a/android/tools/gen-hw-config.py +++ b/android/tools/gen-hw-config.py @@ -28,7 +28,7 @@ def quoteStringForC(str): # a dictionary that maps item types as they appear in the .ini # file into macro names in the generated C header # -typesToMacros = { +typesToMacros = { 'integer': 'HWCFG_INT', 'string': 'HWCFG_STRING', 'boolean': 'HWCFG_BOOL', @@ -69,12 +69,27 @@ class Item: self.default = None self.abstract = "" self.description = "" + self.enum_values = [] def add(self,key,val): if key == 'type': self.type = val + elif key == 'enum': + # Build list of enumerated values + self.enum_values = [ s.strip() for s in val.split(',') ] + # If default value has been already set, make sure it's in the list + if self.default and not self.default in self.enum_values: + print "Property '" + self.name + "': Default value '" + self.default + "' is missing in enum: ", + print self.enum_values, + sys.exit(1) elif key == 'default': - self.default = val + # If this is an enum, make sure that default value is in the list. + if val and self.enum_values and not val in self.enum_values: + print "Property '" + self.name + "': Default value '" + val + "' is missing in enum: ", + print self.enum_values, + sys.exit(1) + else: + self.default = val elif key == 'abstract': self.abstract = val elif key == 'description': diff --git a/android/utils/debug.h b/android/utils/debug.h index 272499a..5aa52ba 100644 --- a/android/utils/debug.h +++ b/android/utils/debug.h @@ -38,9 +38,15 @@ _VERBOSE_TAG(camera, "camera") \ _VERBOSE_TAG(adevice, "android device connected via port forwarding") \ _VERBOSE_TAG(sensors_port, "sensors emulator connected to android device") \ + _VERBOSE_TAG(mtport, "multi-touch emulator connected to android device") \ + _VERBOSE_TAG(mtscreen, "multi-touch screen emulation") \ _VERBOSE_TAG(gles, "hardware OpenGLES emulation") \ _VERBOSE_TAG(adbserver, "ADB server") \ _VERBOSE_TAG(adbclient, "ADB QEMU client") \ + _VERBOSE_TAG(adb, "ADB debugger") \ + _VERBOSE_TAG(asconnector, "Asynchronous socket connector") \ + _VERBOSE_TAG(asyncsocket, "Asynchronous socket") \ + _VERBOSE_TAG(sdkctlsocket, "Socket tethering to SdkControl server") \ #define _VERBOSE_TAG(x,y) VERBOSE_##x, typedef enum { diff --git a/android/utils/jpeg-compress.c b/android/utils/jpeg-compress.c new file mode 100644 index 0000000..cd45bf5 --- /dev/null +++ b/android/utils/jpeg-compress.c @@ -0,0 +1,207 @@ +/* Copyright (C) 2011 The Android Open Source Project +** +** This software is licensed under the terms of the GNU General Public +** License version 2, as published by the Free Software Foundation, and +** may be copied, distributed, and modified under those terms. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +*/ + +#include <stdint.h> +#include "jinclude.h" +#include "jpeglib.h" +#include "jpeg-compress.h" +#include "panic.h" + +/* Implements JPEG destination manager's init_destination routine. */ +static void _on_init_destination(j_compress_ptr cinfo); +/* Implements JPEG destination manager's empty_output_buffer routine. */ +static boolean _on_empty_output_buffer(j_compress_ptr cinfo); +/* Implements JPEG destination manager's term_destination routine. */ +static void _on_term_destination(j_compress_ptr cinfo); + +/* JPEG compression descriptor. */ +struct AJPEGDesc { + /* Common JPEG compression destination manager header. */ + struct jpeg_destination_mgr common; + /* Buffer where to save compressed output. */ + uint8_t* jpeg_buf; + /* Byte size of the 'jpeg_buf' */ + int size; + /* Chunk size to increment the 'jpeg_buf' with on each allocation request. */ + int chunk_size; + /* Size of the header to put in front of the compressed data. */ + int header_size; +}; + +/******************************************************************************** + * jpeglib callbacks. + *******************************************************************************/ + +/* Implements JPEG destination manager's init_destination routine. */ +static void +_on_init_destination(j_compress_ptr cinfo) +{ + AJPEGDesc* const dst = (AJPEGDesc*)cinfo->dest; + if (dst->jpeg_buf == NULL) { + /* This is the first time our destination manager is initialized. + * Allocate minimal buffer. */ + dst->size = dst->chunk_size; + dst->jpeg_buf = malloc(dst->size); + if (dst->jpeg_buf == NULL) { + APANIC("Unable to allocate %d bytes for JPEG compression", dst->size); + } + } + /* Initialize common header with entire destination buffer. */ + dst->common.next_output_byte = dst->jpeg_buf + dst->header_size; + dst->common.free_in_buffer = dst->size - dst->header_size; +} + +/* Implements JPEG destination manager's empty_output_buffer routine. + * Name is a bit misleading here. This routine is called by the compressor when + * output buffer doesn't have enough free space to contain the next chunk of the + * compressed data. So, here we should reallocate the output buffer, rather than + * "empty" it. + */ +static boolean +_on_empty_output_buffer(j_compress_ptr cinfo) +{ + AJPEGDesc* const dst = (AJPEGDesc*)cinfo->dest; + /* Save already compressed data size. */ + const int accumulated = jpeg_compressor_get_jpeg_size(dst); + + /* Reallocate output buffer. */ + dst->size += dst->chunk_size; + dst->jpeg_buf = realloc(dst->jpeg_buf, dst->size); + if (dst->jpeg_buf == NULL) { + APANIC("Unable to allocate %d bytes for JPEG compression", dst->size); + } + + /* Update common header. */ + dst->common.next_output_byte = dst->jpeg_buf + accumulated + dst->header_size; + dst->common.free_in_buffer = dst->size - accumulated - dst->header_size; + + return TRUE; +} + +/* Implements JPEG destination manager's term_destination routine. + * We don't do anything here. All the cleanup will be performed when the user + * calls jpeg_compressor_destroy. */ +static void +_on_term_destination(j_compress_ptr cinfo) +{ +} + +/******************************************************************************** + * JPEG compressor API. + *******************************************************************************/ + +AJPEGDesc* +jpeg_compressor_create(int header_size, int chunk_size) +{ + AJPEGDesc* dsc = (AJPEGDesc*)malloc(sizeof(AJPEGDesc)); + if (dsc == NULL) { + APANIC("Unable to allocate JPEG compression descriptor."); + } + + dsc->common.next_output_byte = NULL; + dsc->common.free_in_buffer = 0; + dsc->common.init_destination = _on_init_destination; + dsc->common.empty_output_buffer = _on_empty_output_buffer; + dsc->common.term_destination = _on_term_destination; + dsc->jpeg_buf = NULL; + dsc->size = 0; + dsc->chunk_size = chunk_size; + dsc->header_size = header_size; + return dsc; +} + +void +jpeg_compressor_destroy(AJPEGDesc* dsc) +{ + if (dsc != NULL) { + if (dsc->jpeg_buf != NULL) { + free(dsc->jpeg_buf); + } + free(dsc); + } +} + +int +jpeg_compressor_get_jpeg_size(const AJPEGDesc* dsc) +{ + return (dsc->jpeg_buf == NULL) ? 0 : + (uint8_t*)dsc->common.next_output_byte - dsc->jpeg_buf - dsc->header_size; +} + +void* +jpeg_compressor_get_buffer(const AJPEGDesc* dsc) +{ + return dsc->jpeg_buf; +} + +int +jpeg_compressor_get_header_size(const AJPEGDesc* dsc) +{ + return dsc->header_size; +} + +void +jpeg_compressor_compress_fb(AJPEGDesc* dsc, + int x, int y, int w, int h, int num_lines, + int bpp, int bpl, + const uint8_t* fb, + int jpeg_quality, + int ydir){ + struct jpeg_compress_struct cinfo = {0}; + struct jpeg_error_mgr err_mgr; + const int x_shift = x * bpp; + + /* + * Initialize compressin information structure, and start compression + */ + + cinfo.err = jpeg_std_error(&err_mgr); + jpeg_create_compress(&cinfo); + cinfo.dest = &dsc->common; + cinfo.image_width = w; + cinfo.image_height = h; + + /* Decode framebuffer's pixel format. There can be only three: + * - RGB565, + * - RGBA8888, + * - RGBX8888 */ + if (bpp == 2) { + /* This is RGB565 - most commonly used pixel format for framebuffer. */ + cinfo.input_components = 2; + cinfo.in_color_space = JCS_RGB_565; + } else { + /* RGBA8888, or RGBX8888 - makes no difference here. */ + cinfo.input_components = 4; + cinfo.in_color_space = JCS_RGBA_8888; + } + jpeg_set_defaults(&cinfo); + jpeg_set_quality(&cinfo, jpeg_quality, TRUE); + jpeg_start_compress(&cinfo, TRUE); + + /* Line by line compress the region. */ + if (ydir >= 0) { + while (cinfo.next_scanline < cinfo.image_height) { + JSAMPROW rgb = (JSAMPROW)(fb + (cinfo.next_scanline + y) * bpl + x_shift); + jpeg_write_scanlines(&cinfo, (JSAMPARRAY)&rgb, 1); + } + } else { + const int y_shift = num_lines - y - 1; + while (cinfo.next_scanline < cinfo.image_height) { + JSAMPROW rgb = (JSAMPROW)(fb + (y_shift - cinfo.next_scanline) * bpl + x_shift); + jpeg_write_scanlines(&cinfo, (JSAMPARRAY)&rgb, 1); + } + } + + /* Complete the compression. */ + jpeg_finish_compress(&cinfo); + jpeg_destroy_compress(&cinfo); +} diff --git a/android/utils/jpeg-compress.h b/android/utils/jpeg-compress.h new file mode 100644 index 0000000..1f84a5d --- /dev/null +++ b/android/utils/jpeg-compress.h @@ -0,0 +1,99 @@ +/* Copyright (C) 2011 The Android Open Source Project +** +** This software is licensed under the terms of the GNU General Public +** License version 2, as published by the Free Software Foundation, and +** may be copied, distributed, and modified under those terms. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +*/ +#ifndef _ANDROID_UTILS_JPEG_COMPRESS_H +#define _ANDROID_UTILS_JPEG_COMPRESS_H + +/* + * Contains declaration of utility routines that compress an RGB bitmap into + * a JPEG image. + * + * NOTE: This code uses a jpeglib library located in distrib/jpeg-6b. It's a + * 3-rd party library that uses its own type definitions that are different from + * the ones that are use elsewhere in the emulator code. For instance, in the + * emulator built for Windows, sizeof(bool) = 1, while in the jpeglib sizeof(bool) = 4. + * So, to simplify dealing with these issues, all the code that uses jpeglib should + * be compiled separately, and should include only headers that are used to compile + * jpeglib. + */ + + +/* Declares descriptor for a JPEG compression. */ +typedef struct AJPEGDesc AJPEGDesc; + +/* Creates a descriptor that will be used for compression. + * Param: + * header_size - Number of bytes to allocate for a custom header that should + * preceed the actual JPEG buffer. This is useful when sending JPEG + * somewhere else along with some extra data about the compressed image. + * cunk_size - Number of bytes to increment the compressed buffer with each time + * compressor requests more memory. + * Return: + * Initialized compression descriptor. + */ +extern AJPEGDesc* jpeg_compressor_create(int header_size, int chunk_size); + +/* Destroys compressor descriptor. + * Param: + * dsc - Compressin descriptor, obtained with jpeg_compressor_create. + */ +extern void jpeg_compressor_destroy(AJPEGDesc* dsc); + +/* Returns compressed data size. + * Param: + * dsc - Compression descriptor, obtained with jpeg_compressor_create. + * Return: + * Compressed data size. + */ +extern int jpeg_compressor_get_jpeg_size(const AJPEGDesc* dsc); + +/* Returns compressed buffer. + * Param: + * dsc - Compression descriptor, obtained with jpeg_compressor_create. + * Return: + * Compressed buffer. NOTE: if 'header_size' parameter passed to the jpeg_compressor_create + * for this descriptor was not zero, this routine returns a pointer to the custom + * header. Compressed data follows immediately after that header. + */ +extern void* jpeg_compressor_get_buffer(const AJPEGDesc* dsc); + +/* Returns size of the custom header placed before the compressed data. + * Param: + * dsc - Compression descriptor, obtained with jpeg_compressor_create. + * Return: + * Size of the custom header placed before the compressed data. + */ +extern int jpeg_compressor_get_header_size(const AJPEGDesc* dsc); + +/* Compresses a framebuffer region into JPEG image. + * Param: + * dsc - Compression descriptor, obtained with jpeg_compressor_create. + * x, y, w, h - Coordinates and sizes of framebuffer region to compress. + * num_lines - Number of lines in the framebuffer (true height). + * bpp - Number of bytes per pixel in the framebuffer. + * bpl - Number of bytes per line in the framebuffer. + * fb - Beginning of the framebuffer. + * jpeg_quality JPEG compression quality. A number from 1 to 100. Note that + * value 10 provides pretty decent image for the purpose of multi-touch + * emulation. + * ydir - Indicates direction in which lines are arranged in the framebuffer. If + * this value is negative, lines are arranged in bottom-up format (i.e. the + * bottom line is at the beginning of the buffer). + */ +extern void jpeg_compressor_compress_fb(AJPEGDesc* dsc, + int x, int y, int w, int h, + int num_lines, + int bpp, int bpl, + const uint8_t* fb, + int jpeg_quality, + int ydir); + +#endif /* _ANDROID_UTILS_JPEG_COMPRESS_H */ diff --git a/android/utils/path.c b/android/utils/path.c index 1bcdc4e..3e9d97b 100644 --- a/android/utils/path.c +++ b/android/utils/path.c @@ -78,8 +78,12 @@ path_parent( const char* path, int levels ) while (base > path && !ispathsep(base[-1])) base--; - if (base <= path) /* we can't go that far */ + if (base <= path) { + if (end == base+1 && base[0] == '.' && levels == 1) + return strdup(".."); + /* we can't go that far */ return NULL; + } if (end == base+1 && base[0] == '.') goto Next; diff --git a/android/utils/system.c b/android/utils/system.c index e65c602..6a6a4e1 100644 --- a/android/utils/system.c +++ b/android/utils/system.c @@ -67,7 +67,7 @@ android_realloc( void* block, size_t size ) if (block2 != NULL) return block2; - fprintf(stderr, "PANIC: not enough memory to reallocate %lld bytes\n", (uint64_t)size); + fprintf(stderr, "PANIC: not enough memory to reallocate %zu bytes\n", size); exit(1); return NULL; } diff --git a/android/utils/system.h b/android/utils/system.h index 464957d..531c7eb 100644 --- a/android/utils/system.h +++ b/android/utils/system.h @@ -14,6 +14,7 @@ #include <string.h> #include <stdint.h> +#define __STDC_FORMAT_MACROS 1 #include <inttypes.h> /* for PRId64 et al. */ #include "android/utils/assert.h" @@ -173,11 +174,8 @@ extern void sleep_ms( int timeout ); #ifndef PRIx64 # define PRIx64 "llx" #endif -#ifndef PRUd64 -# define PRUd64 "llu" -#endif -#ifndef PRUx64 -# define PRUx64 "llx" +#ifndef PRIu64 +# define PRIu64 "llu" #endif /* */ diff --git a/distrib/jpeg-6b/jccolor.c b/distrib/jpeg-6b/jccolor.c index 67078ab..61e262d 100644 --- a/distrib/jpeg-6b/jccolor.c +++ b/distrib/jpeg-6b/jccolor.c @@ -219,6 +219,52 @@ rgb565_ycc_convert (j_compress_ptr cinfo, } } } + +/* Converts RGBA8888 row into YCbCr */ +METHODDEF(void) +rgba8888_ycc_convert (j_compress_ptr cinfo, + JSAMPARRAY input_buf, JSAMPIMAGE output_buf, + JDIMENSION output_row, int num_rows) +{ + my_cconvert_ptr cconvert = (my_cconvert_ptr) cinfo->cconvert; + register int r, g, b; + register INT32 * ctab = cconvert->rgb_ycc_tab; + register INT32* inptr; + register JSAMPROW outptr0, outptr1, outptr2; + register JDIMENSION col; + JDIMENSION num_cols = cinfo->image_width; + + while (--num_rows >= 0) { + inptr = (INT32*)(*input_buf++); + outptr0 = output_buf[0][output_row]; + outptr1 = output_buf[1][output_row]; + outptr2 = output_buf[2][output_row]; + output_row++; + for (col = 0; col < num_cols; col++) { + register const unsigned char* color = (unsigned char*)(inptr + col); + r = (*color) & 0xff; color++; + g = (*color) & 0xff; color++; + b = (*color) & 0xff; color++; + /* If the inputs are 0..MAXJSAMPLE, the outputs of these equations + * must be too; we do not need an explicit range-limiting operation. + * Hence the value being shifted is never negative, and we don't + * need the general RIGHT_SHIFT macro. + */ + /* Y */ + outptr0[col] = (JSAMPLE) + ((ctab[r+R_Y_OFF] + ctab[g+G_Y_OFF] + ctab[b+B_Y_OFF]) + >> SCALEBITS); + /* Cb */ + outptr1[col] = (JSAMPLE) + ((ctab[r+R_CB_OFF] + ctab[g+G_CB_OFF] + ctab[b+B_CB_OFF]) + >> SCALEBITS); + /* Cr */ + outptr2[col] = (JSAMPLE) + ((ctab[r+R_CR_OFF] + ctab[g+G_CR_OFF] + ctab[b+B_CR_OFF]) + >> SCALEBITS); + } + } +} #endif /* ANDROID_RGB */ /**************** Cases other than RGB -> YCbCr **************/ @@ -505,6 +551,10 @@ jinit_color_converter (j_compress_ptr cinfo) if (cinfo->input_components != 2) ERREXIT(cinfo, JERR_BAD_IN_COLORSPACE); break; + case JCS_RGBA_8888: + if (cinfo->input_components != 4) + ERREXIT(cinfo, JERR_BAD_IN_COLORSPACE); + break; #endif /* ANDROID_RGB */ default: /* JCS_UNKNOWN can be anything */ @@ -551,6 +601,9 @@ jinit_color_converter (j_compress_ptr cinfo) else if (cinfo->in_color_space == JCS_RGB_565) { cconvert->pub.start_pass = rgb_ycc_start; cconvert->pub.color_convert = rgb565_ycc_convert; + } else if (cinfo->in_color_space == JCS_RGBA_8888) { + cconvert->pub.start_pass = rgb_ycc_start; + cconvert->pub.color_convert = rgba8888_ycc_convert; } #endif /* ANDROID_RGB */ else diff --git a/distrib/jpeg-6b/jcparam.c b/distrib/jpeg-6b/jcparam.c index b305179..f8404dd 100644 --- a/distrib/jpeg-6b/jcparam.c +++ b/distrib/jpeg-6b/jcparam.c @@ -379,6 +379,7 @@ jpeg_default_colorspace (j_compress_ptr cinfo) break; #ifdef ANDROID_RGB case JCS_RGB_565: + case JCS_RGBA_8888: jpeg_set_colorspace(cinfo, JCS_YCbCr); break; #endif /* ANDROID_RGB */ diff --git a/distrib/jpeg-6b/jmorecfg.h b/distrib/jpeg-6b/jmorecfg.h index 236bbcb..9dfde01 100644 --- a/distrib/jpeg-6b/jmorecfg.h +++ b/distrib/jpeg-6b/jmorecfg.h @@ -17,12 +17,14 @@ * */ +#include <inttypes.h> + #define ANDROID_RGB #ifdef ANDROID_RGB #define PACK_SHORT_565(r,g,b) ((((r)<<8)&0xf800)|(((g)<<3)&0x7E0)|((b)>>3)) #define PACK_TWO_PIXELS(l,r) ((r<<16) | l) -#define PACK_NEED_ALIGNMENT(ptr) (((int)(ptr))&3) +#define PACK_NEED_ALIGNMENT(ptr) (((int)(intptr_t)(ptr))&3) #define WRITE_TWO_PIXELS(addr, pixels) do { \ ((INT16*)(addr))[0] = (pixels); \ ((INT16*)(addr))[1] = (pixels)>>16; \ diff --git a/distrib/sdl-1.2.12/src/video/x11/SDL_x11dyn.c b/distrib/sdl-1.2.12/src/video/x11/SDL_x11dyn.c index 7b99d73..6e97c32 100644 --- a/distrib/sdl-1.2.12/src/video/x11/SDL_x11dyn.c +++ b/distrib/sdl-1.2.12/src/video/x11/SDL_x11dyn.c @@ -109,6 +109,21 @@ char *(*pXGetICValues)(XIC, ...) = NULL; #undef SDL_X11_SYM +static void *SDL_XGetRequest_workaround(Display* dpy, CARD8 type, size_t len) +{ + xReq *req; + WORD64ALIGN + if (dpy->bufptr + len > dpy->bufmax) + _XFlush(dpy); + dpy->last_req = dpy->bufptr; + req = (xReq*)dpy->bufptr; + req->reqType = type; + req->length = len / 4; + dpy->bufptr += len; + dpy->request++; + return req; +} + static int x11_load_refcount = 0; void SDL_X11_UnloadSymbols(void) @@ -168,6 +183,15 @@ int SDL_X11_LoadSymbols(void) X11_GetSym("XGetICValues",&SDL_X11_HAVE_UTF8,(void **)&pXGetICValues); #endif + /* + * In case we're built with newer Xlib headers, we need to make sure + * that _XGetRequest() is available, even on older systems. + * Otherwise, various Xlib macros we use will call a NULL pointer. + */ + if (!SDL_X11_HAVE_XGETREQUEST) { + p_XGetRequest = SDL_XGetRequest_workaround; + } + if (SDL_X11_HAVE_BASEXLIB) { /* all required symbols loaded. */ SDL_ClearError(); XInitThreads(); diff --git a/distrib/sdl-1.2.12/src/video/x11/SDL_x11sym.h b/distrib/sdl-1.2.12/src/video/x11/SDL_x11sym.h index b8d90e4..610982c 100644 --- a/distrib/sdl-1.2.12/src/video/x11/SDL_x11sym.h +++ b/distrib/sdl-1.2.12/src/video/x11/SDL_x11sym.h @@ -181,6 +181,12 @@ SDL_X11_SYM(void,_XRead32,(Display *dpy,register long *data,long len),(dpy,data, #endif /* + * libX11 1.4.99.1 added _XGetRequest, and macros use it behind the scenes. + */ +SDL_X11_MODULE(XGETREQUEST) +SDL_X11_SYM(void *,_XGetRequest,(Display* a,CARD8 b,size_t c),(a,b,c),return) + +/* * These only show up on some variants of Unix. */ #if defined(__osf__) diff --git a/elff/dwarf_utils.cc b/elff/dwarf_utils.cc index 1d84b66..3b998b4 100644 --- a/elff/dwarf_utils.cc +++ b/elff/dwarf_utils.cc @@ -14,7 +14,9 @@ * Contains implementation of misc. DWARF utility routines. */ -#include "stdio.h" +#include <stdio.h> +#define __STDC_FORMAT_MACROS 1 +#include <inttypes.h> #include "dwarf_utils.h" /* "Stringifies" the parameter. */ @@ -275,12 +277,12 @@ dump_value(const Dwarf_Value* attr_value) { break; case DWARF_VALUE_U64: - printf("XWORD) = %" FMT_I64 "u (x%" FMT_I64 "X)\n", attr_value->u64, + printf("XWORD) = %" PRIu64 " (x%" PRIX64 ")\n", attr_value->u64, attr_value->u64); break; case DWARF_VALUE_S64: - printf("SXWORD) = %" FMT_I64 "d (x%" FMT_I64 "X)\n", attr_value->s64, + printf("SXWORD) = %" PRId64 " (x%" PRIX64 ")\n", attr_value->s64, attr_value->s64); break; @@ -293,7 +295,7 @@ dump_value(const Dwarf_Value* attr_value) { break; case DWARF_VALUE_PTR64: - printf("PTR64) = x%08" FMT_I64 "X\n", attr_value->ptr64); + printf("PTR64) = x%08" PRIX64 "\n", attr_value->ptr64); break; case DWARF_VALUE_BLOCK: @@ -11,6 +11,7 @@ struct hax_vcpu_state; #ifdef CONFIG_HAX int hax_enabled(void); +int hax_set_ramsize(uint64_t ramsize); int hax_init(int smp_cpus); int hax_init_vcpu(CPUState *env); /* Execute vcpu in non-root mode */ diff --git a/hw/goldfish_events_device.c b/hw/goldfish_events_device.c index a5b2a21..dad76ad 100644 --- a/hw/goldfish_events_device.c +++ b/hw/goldfish_events_device.c @@ -13,6 +13,7 @@ #include "android/hw-events.h" #include "android/charmap.h" #include "android/globals.h" /* for android_hw */ +#include "android/multitouch-screen.h" #include "irq.h" #include "user-events.h" #include "console.h" @@ -68,6 +69,18 @@ typedef struct size_t abs_info_count; } events_state; +/* An entry in the array of ABS_XXX values */ +typedef struct ABSEntry { + /* Minimum ABS_XXX value. */ + uint32_t min; + /* Maximum ABS_XXX value. */ + uint32_t max; + /* 'fuzz;, and 'flat' ABS_XXX values are always zero here. */ + uint32_t fuzz; + uint32_t flat; +} ABSEntry; + + /* modify this each time you change the events_device structure. you * will also need to upadte events_state_load and events_state_save */ @@ -258,20 +271,27 @@ static void events_put_mouse(void *opaque, int dx, int dy, int dz, int buttons_s * in android/skin/trackball.c and android/skin/window.c */ if (dz == 0) { - enqueue_event(s, EV_ABS, ABS_X, dx); - enqueue_event(s, EV_ABS, ABS_Y, dy); - enqueue_event(s, EV_ABS, ABS_Z, dz); - enqueue_event(s, EV_KEY, BTN_TOUCH, buttons_state&1); + if (androidHwConfig_isScreenMultiTouch(android_hw)) { + /* Convert mouse event into multi-touch event */ + multitouch_update_pointer(MTES_MOUSE, 0, dx, dy, + (buttons_state & 1) ? 0x81 : 0); + } else if (androidHwConfig_isScreenTouch(android_hw)) { + enqueue_event(s, EV_ABS, ABS_X, dx); + enqueue_event(s, EV_ABS, ABS_Y, dy); + enqueue_event(s, EV_ABS, ABS_Z, dz); + enqueue_event(s, EV_KEY, BTN_TOUCH, buttons_state&1); + enqueue_event(s, EV_SYN, 0, 0); + } } else { enqueue_event(s, EV_REL, REL_X, dx); enqueue_event(s, EV_REL, REL_Y, dy); + enqueue_event(s, EV_SYN, 0, 0); } - enqueue_event(s, EV_SYN, 0, 0); } static void events_put_generic(void* opaque, int type, int code, int value) { - events_state *s = (events_state *) opaque; + events_state *s = (events_state *) opaque; enqueue_event(s, type, code, value); } @@ -382,11 +402,13 @@ void events_dev_init(uint32_t base, qemu_irq irq) if (config->hw_trackBall) { events_set_bit(s, EV_KEY, BTN_MOUSE); } - if (config->hw_touchScreen) { + if (androidHwConfig_isScreenTouch(config)) { events_set_bit(s, EV_KEY, BTN_TOUCH); } - if (config->hw_camera) { + if (strcmp(config->hw_camera_back, "none") || + strcmp(config->hw_camera_front, "none")) { + /* Camera emulation is enabled. */ events_set_bit(s, EV_KEY, KEY_CAMERA); } @@ -431,13 +453,13 @@ void events_dev_init(uint32_t base, qemu_irq irq) * * EV_ABS events are sent when the touchscreen is pressed */ - if (config->hw_touchScreen) { - int32_t* values; + if (!androidHwConfig_isScreenNoTouch(config)) { + ABSEntry* abs_values; events_set_bit (s, EV_SYN, EV_ABS ); events_set_bits(s, EV_ABS, ABS_X, ABS_Z); /* Allocate the absinfo to report the min/max bounds for each - * absolute dimension. The array must contain 3 tuples + * absolute dimension. The array must contain 3, or ABS_MAX tuples * of (min,max,fuzz,flat) 32-bit values. * * min and max are the bounds @@ -448,33 +470,39 @@ void events_dev_init(uint32_t base, qemu_irq irq) * There is no need to save/restore this array in a snapshot * since the values only depend on the hardware configuration. */ - s->abs_info_count = 3*4; - s->abs_info = values = malloc(sizeof(uint32_t)*s->abs_info_count); - - /* ABS_X min/max/fuzz/flat */ - values[0] = 0; - values[1] = config->hw_lcd_width-1; - values[2] = 0; - values[3] = 0; - values += 4; - - /* ABS_Y */ - values[0] = 0; - values[1] = config->hw_lcd_height-1; - values[2] = 0; - values[3] = 0; - values += 4; - - /* ABS_Z */ - values[0] = 0; - values[1] = 1; - values[2] = 0; - values[3] = 0; + s->abs_info_count = androidHwConfig_isScreenMultiTouch(config) ? ABS_MAX * 4 : 3 * 4; + const int abs_size = sizeof(uint32_t) * s->abs_info_count; + s->abs_info = malloc(abs_size); + memset(s->abs_info, 0, abs_size); + abs_values = (ABSEntry*)s->abs_info; + + abs_values[ABS_X].max = config->hw_lcd_width-1; + abs_values[ABS_Y].max = config->hw_lcd_height-1; + abs_values[ABS_Z].max = 1; + + if (androidHwConfig_isScreenMultiTouch(config)) { + /* + * Setup multitouch. + */ + events_set_bit(s, EV_ABS, ABS_MT_SLOT); + events_set_bit(s, EV_ABS, ABS_MT_POSITION_X); + events_set_bit(s, EV_ABS, ABS_MT_POSITION_Y); + events_set_bit(s, EV_ABS, ABS_MT_TRACKING_ID); + events_set_bit(s, EV_ABS, ABS_MT_TOUCH_MAJOR); + events_set_bit(s, EV_ABS, ABS_MT_PRESSURE); + + abs_values[ABS_MT_SLOT].max = multitouch_get_max_slot(); + abs_values[ABS_MT_TRACKING_ID].max = abs_values[ABS_MT_SLOT].max + 1; + abs_values[ABS_MT_POSITION_X].max = abs_values[ABS_X].max; + abs_values[ABS_MT_POSITION_Y].max = abs_values[ABS_Y].max; + abs_values[ABS_MT_TOUCH_MAJOR].max = 0x7fffffff; // TODO: Make it less random + abs_values[ABS_MT_PRESSURE].max = 0x100; // TODO: Make it less random + } } /* configure EV_SW array * - * EW_SW events are sent to indicate that the keyboard lid + * EV_SW events are sent to indicate that the keyboard lid * was closed or opened (done when we switch layouts through * KP-7 or KP-9). * diff --git a/hw/goldfish_fb.c b/hw/goldfish_fb.c index d74d797..16450b3 100644 --- a/hw/goldfish_fb.c +++ b/hw/goldfish_fb.c @@ -319,7 +319,11 @@ compute_fb_update_rect_linear(FbUpdateState* fbs, xx1 = 0; DUFF4(width, { - if (src[xx1] != dst[xx1]) + uint16_t spix = src[xx1]; +#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) + spix = (uint16_t)((spix << 8) | (spix >> 8)); +#endif + if (spix != dst[xx1]) break; xx1++; }); @@ -332,8 +336,8 @@ compute_fb_update_rect_linear(FbUpdateState* fbs, break; xx2--; }); -#if HOST_WORDS_BIGENDIAN - /* Convert the guest little-endian pixels into big-endian ones */ +#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) + /* Convert the guest pixels into host ones */ int xx = xx1; DUFF4(xx2-xx1+1,{ unsigned spix = src[xx]; @@ -382,7 +386,12 @@ compute_fb_update_rect_linear(FbUpdateState* fbs, xx1 = 0; DUFF4(width, { - if (src[xx1] != dst[xx1]) { + uint32_t spix = src[xx1]; +#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) + spix = (spix << 16) | (spix >> 16); + spix = ((spix << 8) & 0xff00ff00) | ((spix >> 8) & 0x00ff00ff); +#endif + if (spix != dst[xx1]) { break; } xx1++; @@ -397,8 +406,8 @@ compute_fb_update_rect_linear(FbUpdateState* fbs, } xx2--; }); -#if HOST_WORDS_BIGENDIAN - /* Convert the guest little-endian pixels into big-endian ones */ +#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) + /* Convert the guest pixels into host ones */ int xx = xx1; DUFF4(xx2-xx1+1,{ uint32_t spix = src[xx]; diff --git a/hw/goldfish_nand.c b/hw/goldfish_nand.c index 31e814b..55f77f6 100644 --- a/hw/goldfish_nand.c +++ b/hw/goldfish_nand.c @@ -140,7 +140,7 @@ typedef struct { * 2: saving actual disk contents as well * 3: use the correct data length and truncate to avoid padding. */ -#define NAND_DEV_STATE_SAVE_VERSION 3 +#define NAND_DEV_STATE_SAVE_VERSION 4 #define QFIELD_STRUCT nand_dev_controller_state QFIELD_BEGIN(nand_dev_controller_state_fields) @@ -149,6 +149,8 @@ QFIELD_BEGIN(nand_dev_controller_state_fields) QFIELD_INT32(addr_high), QFIELD_INT32(transfer_size), QFIELD_INT32(data), + QFIELD_INT32(batch_addr_low), + QFIELD_INT32(batch_addr_high), QFIELD_INT32(result), QFIELD_END diff --git a/hw/goldfish_pipe.c b/hw/goldfish_pipe.c index 97daefb..276ac9a 100644 --- a/hw/goldfish_pipe.c +++ b/hw/goldfish_pipe.c @@ -55,7 +55,7 @@ /* Maximum length of pipe service name, in characters (excluding final 0) */ #define MAX_PIPE_SERVICE_NAME_SIZE 255 -#define GOLDFISH_PIPE_SAVE_VERSION 1 +#define GOLDFISH_PIPE_SAVE_VERSION 2 /*********************************************************************** *********************************************************************** @@ -960,9 +960,9 @@ struct PipeDevice { uint32_t status; uint32_t channel; uint32_t wakes; + uint64_t params_addr; }; - static void pipeDevice_doCommand( PipeDevice* dev, uint32_t command ) { @@ -1097,6 +1097,42 @@ static void pipe_dev_write(void *opaque, target_phys_addr_t offset, uint32_t val s->channel = value; break; + case PIPE_REG_PARAMS_ADDR_HIGH: + s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL << 32) ) | + ((uint64_t)value << 32); + break; + + case PIPE_REG_PARAMS_ADDR_LOW: + s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL) ) | value; + break; + + case PIPE_REG_ACCESS_PARAMS: + { + struct access_params aps; + uint32_t cmd; + + /* Don't touch aps.result if anything wrong */ + if (s->params_addr == 0) + break; + + cpu_physical_memory_read(s->params_addr, (void*)&aps, + sizeof(struct access_params)); + + /* sync pipe device state from batch buffer */ + s->channel = aps.channel; + s->size = aps.size; + s->address = aps.address; + cmd = aps.cmd; + if ((cmd != PIPE_CMD_READ_BUFFER) && (cmd != PIPE_CMD_WRITE_BUFFER)) + break; + + pipeDevice_doCommand(s, cmd); + aps.result = s->status; + cpu_physical_memory_write(s->params_addr, (void*)&aps, + sizeof(struct access_params)); + } + break; + default: D("%s: offset=%d (0x%x) value=%d (0x%x)\n", __FUNCTION__, offset, offset, value, value); @@ -1136,6 +1172,12 @@ static uint32_t pipe_dev_read(void *opaque, target_phys_addr_t offset) DR("%s: wakes %d", __FUNCTION__, dev->wakes); return dev->wakes; + case PIPE_REG_PARAMS_ADDR_HIGH: + return dev->params_addr >> 32; + + case PIPE_REG_PARAMS_ADDR_LOW: + return dev->params_addr & 0xFFFFFFFFUL; + default: D("%s: offset=%d (0x%x)\n", __FUNCTION__, offset, offset); } @@ -1165,6 +1207,7 @@ goldfish_pipe_save( QEMUFile* file, void* opaque ) qemu_put_be32(file, dev->status); qemu_put_be32(file, dev->channel); qemu_put_be32(file, dev->wakes); + qemu_put_be64(file, dev->params_addr); /* Count the number of pipe connections */ int count = 0; @@ -1193,6 +1236,7 @@ goldfish_pipe_load( QEMUFile* file, void* opaque, int version_id ) dev->status = qemu_get_be32(file); dev->channel = qemu_get_be32(file); dev->wakes = qemu_get_be32(file); + dev->params_addr = qemu_get_be64(file); /* Count the number of pipe connections */ int count = qemu_get_sbe32(file); diff --git a/hw/goldfish_pipe.h b/hw/goldfish_pipe.h index f08cef8..10efa96 100644 --- a/hw/goldfish_pipe.h +++ b/hw/goldfish_pipe.h @@ -153,6 +153,11 @@ extern void goldfish_pipe_wake( void* hwpipe, unsigned flags ); #define PIPE_REG_SIZE 0x0c /* read/write: buffer size */ #define PIPE_REG_ADDRESS 0x10 /* write: physical address */ #define PIPE_REG_WAKES 0x14 /* read: wake flags */ +/* read/write: parameter buffer address */ +#define PIPE_REG_PARAMS_ADDR_LOW 0x18 +#define PIPE_REG_PARAMS_ADDR_HIGH 0x1c +/* write: access with paremeter buffer */ +#define PIPE_REG_ACCESS_PARAMS 0x20 /* list of commands for PIPE_REG_COMMAND */ #define PIPE_CMD_OPEN 1 /* open new channel */ @@ -189,4 +194,14 @@ extern void goldfish_pipe_wake( void* hwpipe, unsigned flags ); void pipe_dev_init(void); +struct access_params{ + uint32_t channel; + uint32_t size; + uint32_t address; + uint32_t cmd; + uint32_t result; + /* reserved for future extension */ + uint32_t flags; +}; + #endif /* _HW_GOLDFISH_PIPE_H */ diff --git a/hw/mips-bios.h b/hw/mips-bios.h new file mode 100644 index 0000000..b4b88ac --- /dev/null +++ b/hw/mips-bios.h @@ -0,0 +1,8 @@ +#include "cpu.h" + +#define BIOS_SIZE (4 * 1024 * 1024) +#ifdef TARGET_WORDS_BIGENDIAN +#define BIOS_FILENAME "mips_bios.bin" +#else +#define BIOS_FILENAME "mipsel_bios.bin" +#endif diff --git a/hw/mips.h b/hw/mips.h new file mode 100644 index 0000000..5fd72bb --- /dev/null +++ b/hw/mips.h @@ -0,0 +1,43 @@ +#ifndef HW_MIPS_H +#define HW_MIPS_H +/* Definitions for mips board emulation. */ + +/* gt64xxx.c */ +PCIBus *pci_gt64120_init(qemu_irq *pic); + +/* ds1225y.c */ +void *ds1225y_init(target_phys_addr_t mem_base, const char *filename); +void ds1225y_set_protection(void *opaque, int protection); + +/* g364fb.c */ +int g364fb_mm_init(target_phys_addr_t vram_base, + target_phys_addr_t ctrl_base, int it_shift, + qemu_irq irq); + +/* mipsnet.c */ +void mipsnet_init(int base, qemu_irq irq, NICInfo *nd); + +/* jazz_led.c */ +extern void jazz_led_init(target_phys_addr_t base); + +/* mips_int.c */ +extern void cpu_mips_irq_init_cpu(CPUState *env); + +/* mips_timer.c */ +extern void cpu_mips_clock_init(CPUState *); + +/* rc4030.c */ +typedef struct rc4030DMAState *rc4030_dma; +void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write); +void rc4030_dma_read(void *dma, uint8_t *buf, int len); +void rc4030_dma_write(void *dma, uint8_t *buf, int len); + +void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, + qemu_irq **irqs, rc4030_dma **dmas); + +/* dp8393x.c */ +void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift, + qemu_irq irq, void* mem_opaque, + void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)); + +#endif diff --git a/hw/mips_int.c b/hw/mips_int.c new file mode 100644 index 0000000..ad48b4f --- /dev/null +++ b/hw/mips_int.c @@ -0,0 +1,45 @@ +#include "hw.h" +#include "mips.h" +#include "cpu.h" + +/* Raise IRQ to CPU if necessary. It must be called every time the active + IRQ may change */ +void cpu_mips_update_irq(CPUState *env) +{ + if ((env->CP0_Status & (1 << CP0St_IE)) && + !(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM)) { + if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && + !(env->interrupt_request & CPU_INTERRUPT_HARD)) { + cpu_interrupt(env, CPU_INTERRUPT_HARD); + } + } else + cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); +} + +static void cpu_mips_irq_request(void *opaque, int irq, int level) +{ + CPUState *env = (CPUState *)opaque; + + if (irq < 0 || irq > 7) + return; + + if (level) { + env->CP0_Cause |= 1 << (irq + CP0Ca_IP); + } else { + env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); + } + cpu_mips_update_irq(env); +} + +void cpu_mips_irq_init_cpu(CPUState *env) +{ + qemu_irq *qi; + int i; + + qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8); + for (i = 0; i < 8; i++) { + env->irq[i] = qi[i]; + } +} diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c new file mode 100644 index 0000000..b69d7c3 --- /dev/null +++ b/hw/mips_r4k.c @@ -0,0 +1,311 @@ +/* + * QEMU/MIPS pseudo-board + * + * emulates a simple machine with ISA-like bus. + * ISA IO space mapped to the 0x14000000 (PHYS) and + * ISA memory at the 0x10000000 (PHYS, 16Mb in size). + * All peripherial devices are attached to this "bus" with + * the standard PC ISA addresses. +*/ +#include "hw.h" +#include "mips.h" +#include "pc.h" +#include "isa.h" +#include "net.h" +#include "sysemu.h" +#include "boards.h" +#include "flash.h" +#include "qemu-log.h" +#include "mips-bios.h" +#include "ide.h" +#include "loader.h" +#include "elf.h" + +#define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff) + +#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) + +#define MAX_IDE_BUS 2 + +static const int ide_iobase[2] = { 0x1f0, 0x170 }; +static const int ide_iobase2[2] = { 0x3f6, 0x376 }; +static const int ide_irq[2] = { 14, 15 }; + +static PITState *pit; /* PIT i8254 */ + +/* i8254 PIT is attached to the IRQ0 at PIC i8259 */ + +static struct _loaderparams { + int ram_size; + const char *kernel_filename; + const char *kernel_cmdline; + const char *initrd_filename; +} loaderparams; + +static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + if ((addr & 0xffff) == 0 && val == 42) + qemu_system_reset_request (); + else if ((addr & 0xffff) == 4 && val == 42) + qemu_system_shutdown_request (); +} + +static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) +{ + return 0; +} + +static CPUWriteMemoryFunc * const mips_qemu_write[] = { + &mips_qemu_writel, + &mips_qemu_writel, + &mips_qemu_writel, +}; + +static CPUReadMemoryFunc * const mips_qemu_read[] = { + &mips_qemu_readl, + &mips_qemu_readl, + &mips_qemu_readl, +}; + +static int mips_qemu_iomemtype = 0; + +typedef struct ResetData { + CPUState *env; + uint64_t vector; +} ResetData; + +static int64_t load_kernel(void) +{ + int64_t entry, kernel_low, kernel_high; + long kernel_size, initrd_size, params_size; + ram_addr_t initrd_offset; + uint32_t *params_buf; + int big_endian; + +#ifdef TARGET_WORDS_BIGENDIAN + big_endian = 1; +#else + big_endian = 0; +#endif + kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, + (uint64_t *)&entry, (uint64_t *)&kernel_low, + (uint64_t *)&kernel_high, big_endian, ELF_MACHINE, 1); + if (kernel_size >= 0) { + if ((entry & ~0x7fffffffULL) == 0x80000000) + entry = (int32_t)entry; + } else { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + loaderparams.kernel_filename); + exit(1); + } + + /* load initrd */ + initrd_size = 0; + initrd_offset = 0; + if (loaderparams.initrd_filename) { + initrd_size = get_image_size (loaderparams.initrd_filename); + if (initrd_size > 0) { + initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; + if (initrd_offset + initrd_size > ram_size) { + fprintf(stderr, + "qemu: memory too small for initial ram disk '%s'\n", + loaderparams.initrd_filename); + exit(1); + } + initrd_size = load_image_targphys(loaderparams.initrd_filename, + initrd_offset, + ram_size - initrd_offset); + } + if (initrd_size == (target_ulong) -1) { + fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", + loaderparams.initrd_filename); + exit(1); + } + } + + /* Store command line. */ + params_size = 264; + params_buf = qemu_malloc(params_size); + + params_buf[0] = tswap32(ram_size); + params_buf[1] = tswap32(0x12345678); + + if (initrd_size > 0) { + snprintf((char *)params_buf + 8, 256, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", + PHYS_TO_VIRT((uint32_t)initrd_offset), + initrd_size, loaderparams.kernel_cmdline); + } else { + snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline); + } + + rom_add_blob_fixed("params", params_buf, params_size, + (16 << 20) - 264); + + return entry; +} + +static void main_cpu_reset(void *opaque) +{ + ResetData *s = (ResetData *)opaque; + CPUState *env = s->env; + + cpu_reset(env); + env->active_tc.PC = s->vector; +} + +static const int sector_len = 32 * 1024; +static +void mips_r4k_init (ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + char *filename; + ram_addr_t ram_offset; + ram_addr_t bios_offset; + int bios_size; + CPUState *env; + ResetData *reset_info; + RTCState *rtc_state; + int i; + qemu_irq *i8259; + DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; + DriveInfo *dinfo; + + /* init CPUs */ + if (cpu_model == NULL) { +#ifdef TARGET_MIPS64 + cpu_model = "R4000"; +#else + cpu_model = "24Kf"; +#endif + } + env = cpu_init(cpu_model); + if (!env) { + fprintf(stderr, "Unable to find CPU definition\n"); + exit(1); + } + reset_info = qemu_mallocz(sizeof(ResetData)); + reset_info->env = env; + reset_info->vector = env->active_tc.PC; + qemu_register_reset(main_cpu_reset, reset_info); + + /* allocate RAM */ + if (ram_size > (256 << 20)) { + fprintf(stderr, + "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", + ((unsigned int)ram_size / (1 << 20))); + exit(1); + } + ram_offset = qemu_ram_alloc(ram_size); + + cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); + + if (!mips_qemu_iomemtype) { + mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read, + mips_qemu_write, NULL); + } + cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); + + /* Try to load a BIOS image. If this fails, we continue regardless, + but initialize the hardware ourselves. When a kernel gets + preloaded we also initialize the hardware, since the BIOS wasn't + run. */ + if (bios_name == NULL) + bios_name = BIOS_FILENAME; + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (filename) { + bios_size = get_image_size(filename); + } else { + bios_size = -1; + } + if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { + bios_offset = qemu_ram_alloc(BIOS_SIZE); + cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, + bios_offset | IO_MEM_ROM); + + load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); + } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { + uint32_t mips_rom = 0x00400000; + bios_offset = qemu_ram_alloc(mips_rom); + if (!pflash_cfi01_register(0x1fc00000, bios_offset, + dinfo->bdrv, sector_len, mips_rom / sector_len, + 4, 0, 0, 0, 0)) { + fprintf(stderr, "qemu: Error registering flash memory.\n"); + } + } + else { + /* not fatal */ + fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", + bios_name); + } + if (filename) { + qemu_free(filename); + } + + if (kernel_filename) { + loaderparams.ram_size = ram_size; + loaderparams.kernel_filename = kernel_filename; + loaderparams.kernel_cmdline = kernel_cmdline; + loaderparams.initrd_filename = initrd_filename; + reset_info->vector = load_kernel(); + } + + /* Init CPU internal devices */ + cpu_mips_irq_init_cpu(env); + cpu_mips_clock_init(env); + + /* The PIC is attached to the MIPS CPU INT0 pin */ + i8259 = i8259_init(env->irq[2]); + isa_bus_new(NULL); + isa_bus_irqs(i8259); + + rtc_state = rtc_init(2000); + + /* Register 64 KB of ISA IO space at 0x14000000 */ + isa_mmio_init(0x14000000, 0x00010000); + isa_mem_base = 0x10000000; + + pit = pit_init(0x40, i8259[0]); + + for(i = 0; i < MAX_SERIAL_PORTS; i++) { + if (serial_hds[i]) { + serial_isa_init(i, serial_hds[i]); + } + } + + isa_vga_init(); + + if (nd_table[0].vlan) + isa_ne2000_init(0x300, 9, &nd_table[0]); + + if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { + fprintf(stderr, "qemu: too many IDE bus\n"); + exit(1); + } + + for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { + hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); + } + + for(i = 0; i < MAX_IDE_BUS; i++) + isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], + hd[MAX_IDE_DEVS * i], + hd[MAX_IDE_DEVS * i + 1]); + + isa_create_simple("i8042"); +} + +static QEMUMachine mips_machine = { + .name = "mips", + .desc = "mips r4k platform", + .init = mips_r4k_init, +}; + +static void mips_machine_init(void) +{ + qemu_register_machine(&mips_machine); +} + +machine_init(mips_machine_init); diff --git a/hw/mips_timer.c b/hw/mips_timer.c new file mode 100644 index 0000000..6bae90b --- /dev/null +++ b/hw/mips_timer.c @@ -0,0 +1,109 @@ +#include "hw.h" +#include "mips.h" +#include "qemu-timer.h" + +#define TIMER_FREQ 100 * 1000 * 1000 + +/* XXX: do not use a global */ +uint32_t cpu_mips_get_random (CPUState *env) +{ + static uint32_t lfsr = 1; + static uint32_t prev_idx = 0; + uint32_t idx; + /* Don't return same value twice, so get another value */ + do { + lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u); + idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired; + } while (idx == prev_idx); + prev_idx = idx; + return idx; +} + +/* MIPS R4K timer */ +uint32_t cpu_mips_get_count (CPUState *env) +{ + if (env->CP0_Cause & (1 << CP0Ca_DC)) + return env->CP0_Count; + else + return env->CP0_Count + + (uint32_t)muldiv64(qemu_get_clock(vm_clock), + TIMER_FREQ, get_ticks_per_sec()); +} + +static void cpu_mips_timer_update(CPUState *env) +{ + uint64_t now, next; + uint32_t wait; + + now = qemu_get_clock(vm_clock); + wait = env->CP0_Compare - env->CP0_Count - + (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); + next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); + qemu_mod_timer(env->timer, next); +} + +void cpu_mips_store_count (CPUState *env, uint32_t count) +{ + if (env->CP0_Cause & (1 << CP0Ca_DC)) + env->CP0_Count = count; + else { + /* Store new count register */ + env->CP0_Count = + count - (uint32_t)muldiv64(qemu_get_clock(vm_clock), + TIMER_FREQ, get_ticks_per_sec()); + /* Update timer timer */ + cpu_mips_timer_update(env); + } +} + +void cpu_mips_store_compare (CPUState *env, uint32_t value) +{ + env->CP0_Compare = value; + if (!(env->CP0_Cause & (1 << CP0Ca_DC))) + cpu_mips_timer_update(env); + if (env->insn_flags & ISA_MIPS32R2) + env->CP0_Cause &= ~(1 << CP0Ca_TI); + qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); +} + +void cpu_mips_start_count(CPUState *env) +{ + cpu_mips_store_count(env, env->CP0_Count); +} + +void cpu_mips_stop_count(CPUState *env) +{ + /* Store the current value */ + env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock), + TIMER_FREQ, get_ticks_per_sec()); +} + +static void mips_timer_cb (void *opaque) +{ + CPUState *env; + + env = opaque; +#if 0 + qemu_log("%s\n", __func__); +#endif + + if (env->CP0_Cause & (1 << CP0Ca_DC)) + return; + + /* ??? This callback should occur when the counter is exactly equal to + the comparator value. Offset the count by one to avoid immediately + retriggering the callback before any virtual time has passed. */ + env->CP0_Count++; + cpu_mips_timer_update(env); + env->CP0_Count--; + if (env->insn_flags & ISA_MIPS32R2) + env->CP0_Cause |= 1 << CP0Ca_TI; + qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); +} + +void cpu_mips_clock_init (CPUState *env) +{ + env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env); + env->CP0_Compare = 0; + cpu_mips_store_count(env, 1); +} diff --git a/iolooper-select.c b/iolooper-select.c index 955204d..5024c9a 100644 --- a/iolooper-select.c +++ b/iolooper-select.c @@ -175,6 +175,8 @@ iolooper_wait( IoLooper* iol, int64_t duration ) if (count == 0) return 0; + CLAMP_MAC_TIMEOUT(duration); + if (duration < 0) tm = NULL; else { @@ -427,8 +427,8 @@ int kvm_init(int smp_cpus) s->vmfd = -1; s->fd = open("/dev/kvm", O_RDWR); if (s->fd == -1) { - fprintf(stderr, "Could not access KVM kernel module: %m\n"); ret = -errno; + fprintf(stderr, "Could not access KVM kernel module: %m\n"); goto err; } @@ -447,8 +447,11 @@ int kvm_init(int smp_cpus) } s->vmfd = kvm_ioctl(s, KVM_CREATE_VM, 0); - if (s->vmfd < 0) + if (s->vmfd < 0) { + ret = -errno; + fprintf(stderr, "ioctl(KVM_CREATE_VM) failed: %s\n", strerror(errno)); goto err; + } /* initially, KVM allocated its own memory and we had to jump through * hooks to make phys_ram_base point to this. Modern versions of KVM diff --git a/linux_keycodes.h b/linux_keycodes.h index 3875028..195797e 100644 --- a/linux_keycodes.h +++ b/linux_keycodes.h @@ -449,4 +449,60 @@ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x1ff +#ifndef ABS_MT_SLOT +#define ABS_MT_SLOT 0x2f /* MT slot being modified */ +#endif +#ifndef ABS_MT_TOUCH_MAJOR +#define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ +#endif +#ifndef ABS_MT_TOUCH_MINOR +#define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ +#endif +#ifndef ABS_MT_WIDTH_MAJOR +#define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ +#endif +#ifndef ABS_MT_WIDTH_MINOR +#define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ +#endif +#ifndef ABS_MT_ORIENTATION +#define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ +#endif +#ifndef ABS_MT_POSITION_X +#define ABS_MT_POSITION_X 0x35 /* Center X ellipse position */ +#endif +#ifndef ABS_MT_POSITION_Y +#define ABS_MT_POSITION_Y 0x36 /* Center Y ellipse position */ +#endif +#ifndef ABS_MT_TOOL_TYPE +#define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ +#endif +#ifndef ABS_MT_BLOB_ID +#define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ +#endif +#ifndef ABS_MT_TRACKING_ID +#define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ +#endif +#ifndef ABS_MT_PRESSURE +#define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ +#endif +#ifndef ABS_MT_DISTANCE +#define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ +#endif +#ifndef ABS_MAX +#define ABS_MAX 0x3f +#endif + +#ifndef SYN_REPORT +#define SYN_REPORT 0 +#endif +#ifndef SYN_CONFIG +#define SYN_CONFIG 1 +#endif +#ifndef SYN_MT_REPORT +#define SYN_MT_REPORT 2 +#endif +#ifndef SYN_DROPPED +#define SYN_DROPPED 3 +#endif + #endif diff --git a/mips-dis.c b/mips-dis.c new file mode 100644 index 0000000..169169c --- /dev/null +++ b/mips-dis.c @@ -0,0 +1,4842 @@ +/* Print mips instructions for GDB, the GNU debugger, or for objdump. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). + +This file is part of GDB, GAS, and the GNU binutils. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, see <http://www.gnu.org/licenses/>. */ + +#include "dis-asm.h" + +/* mips.h. Mips opcode list for GDB, the GNU debugger. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. + Contributed by Ralph Campbell and OSF + Commented and modified by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, +see <http://www.gnu.org/licenses/>. */ + +/* These are bit masks and shift counts to use to access the various + fields of an instruction. To retrieve the X field of an + instruction, use the expression + (i >> OP_SH_X) & OP_MASK_X + To set the same field (to j), use + i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) + + Make sure you use fields that are appropriate for the instruction, + of course. + + The 'i' format uses OP, RS, RT and IMMEDIATE. + + The 'j' format uses OP and TARGET. + + The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. + + The 'b' format uses OP, RS, RT and DELTA. + + The floating point 'i' format uses OP, RS, RT and IMMEDIATE. + + The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. + + A breakpoint instruction uses OP, CODE and SPEC (10 bits of the + breakpoint instruction are not defined; Kane says the breakpoint + code field in BREAK is 20 bits; yet MIPS assemblers and debuggers + only use ten bits). An optional two-operand form of break/sdbbp + allows the lower ten bits to be set too, and MIPS32 and later + architectures allow 20 bits to be set with a signal operand + (using CODE20). + + The syscall instruction uses CODE20. + + The general coprocessor instructions use COPZ. */ + +#define OP_MASK_OP 0x3f +#define OP_SH_OP 26 +#define OP_MASK_RS 0x1f +#define OP_SH_RS 21 +#define OP_MASK_FR 0x1f +#define OP_SH_FR 21 +#define OP_MASK_FMT 0x1f +#define OP_SH_FMT 21 +#define OP_MASK_BCC 0x7 +#define OP_SH_BCC 18 +#define OP_MASK_CODE 0x3ff +#define OP_SH_CODE 16 +#define OP_MASK_CODE2 0x3ff +#define OP_SH_CODE2 6 +#define OP_MASK_RT 0x1f +#define OP_SH_RT 16 +#define OP_MASK_FT 0x1f +#define OP_SH_FT 16 +#define OP_MASK_CACHE 0x1f +#define OP_SH_CACHE 16 +#define OP_MASK_RD 0x1f +#define OP_SH_RD 11 +#define OP_MASK_FS 0x1f +#define OP_SH_FS 11 +#define OP_MASK_PREFX 0x1f +#define OP_SH_PREFX 11 +#define OP_MASK_CCC 0x7 +#define OP_SH_CCC 8 +#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ +#define OP_SH_CODE20 6 +#define OP_MASK_SHAMT 0x1f +#define OP_SH_SHAMT 6 +#define OP_MASK_FD 0x1f +#define OP_SH_FD 6 +#define OP_MASK_TARGET 0x3ffffff +#define OP_SH_TARGET 0 +#define OP_MASK_COPZ 0x1ffffff +#define OP_SH_COPZ 0 +#define OP_MASK_IMMEDIATE 0xffff +#define OP_SH_IMMEDIATE 0 +#define OP_MASK_DELTA 0xffff +#define OP_SH_DELTA 0 +#define OP_MASK_FUNCT 0x3f +#define OP_SH_FUNCT 0 +#define OP_MASK_SPEC 0x3f +#define OP_SH_SPEC 0 +#define OP_SH_LOCC 8 /* FP condition code. */ +#define OP_SH_HICC 18 /* FP condition code. */ +#define OP_MASK_CC 0x7 +#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ +#define OP_MASK_COP1NORM 0x1 /* a single bit. */ +#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ +#define OP_MASK_COP1SPEC 0xf +#define OP_MASK_COP1SCLR 0x4 +#define OP_MASK_COP1CMP 0x3 +#define OP_SH_COP1CMP 4 +#define OP_SH_FORMAT 21 /* FP short format field. */ +#define OP_MASK_FORMAT 0x7 +#define OP_SH_TRUE 16 +#define OP_MASK_TRUE 0x1 +#define OP_SH_GE 17 +#define OP_MASK_GE 0x01 +#define OP_SH_UNSIGNED 16 +#define OP_MASK_UNSIGNED 0x1 +#define OP_SH_HINT 16 +#define OP_MASK_HINT 0x1f +#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ +#define OP_MASK_MMI 0x3f +#define OP_SH_MMISUB 6 +#define OP_MASK_MMISUB 0x1f +#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ +#define OP_SH_PERFREG 1 +#define OP_SH_SEL 0 /* Coprocessor select field. */ +#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ +#define OP_SH_CODE19 6 /* 19 bit wait code. */ +#define OP_MASK_CODE19 0x7ffff +#define OP_SH_ALN 21 +#define OP_MASK_ALN 0x7 +#define OP_SH_VSEL 21 +#define OP_MASK_VSEL 0x1f +#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, + but 0x8-0xf don't select bytes. */ +#define OP_SH_VECBYTE 22 +#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ +#define OP_SH_VECALIGN 21 +#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ +#define OP_SH_INSMSB 11 +#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ +#define OP_SH_EXTMSBD 11 + +#define OP_OP_COP0 0x10 +#define OP_OP_COP1 0x11 +#define OP_OP_COP2 0x12 +#define OP_OP_COP3 0x13 +#define OP_OP_LWC1 0x31 +#define OP_OP_LWC2 0x32 +#define OP_OP_LWC3 0x33 /* a.k.a. pref */ +#define OP_OP_LDC1 0x35 +#define OP_OP_LDC2 0x36 +#define OP_OP_LDC3 0x37 /* a.k.a. ld */ +#define OP_OP_SWC1 0x39 +#define OP_OP_SWC2 0x3a +#define OP_OP_SWC3 0x3b +#define OP_OP_SDC1 0x3d +#define OP_OP_SDC2 0x3e +#define OP_OP_SDC3 0x3f /* a.k.a. sd */ + +/* MIPS DSP ASE */ +#define OP_SH_DSPACC 11 +#define OP_MASK_DSPACC 0x3 +#define OP_SH_DSPACC_S 21 +#define OP_MASK_DSPACC_S 0x3 +#define OP_SH_DSPSFT 20 +#define OP_MASK_DSPSFT 0x3f +#define OP_SH_DSPSFT_7 19 +#define OP_MASK_DSPSFT_7 0x7f +#define OP_SH_SA3 21 +#define OP_MASK_SA3 0x7 +#define OP_SH_SA4 21 +#define OP_MASK_SA4 0xf +#define OP_SH_IMM8 16 +#define OP_MASK_IMM8 0xff +#define OP_SH_IMM10 16 +#define OP_MASK_IMM10 0x3ff +#define OP_SH_WRDSP 11 +#define OP_MASK_WRDSP 0x3f +#define OP_SH_RDDSP 16 +#define OP_MASK_RDDSP 0x3f +#define OP_SH_BP 11 +#define OP_MASK_BP 0x3 + +/* MIPS MT ASE */ +#define OP_SH_MT_U 5 +#define OP_MASK_MT_U 0x1 +#define OP_SH_MT_H 4 +#define OP_MASK_MT_H 0x1 +#define OP_SH_MTACC_T 18 +#define OP_MASK_MTACC_T 0x3 +#define OP_SH_MTACC_D 13 +#define OP_MASK_MTACC_D 0x3 + +#define OP_OP_COP0 0x10 +#define OP_OP_COP1 0x11 +#define OP_OP_COP2 0x12 +#define OP_OP_COP3 0x13 +#define OP_OP_LWC1 0x31 +#define OP_OP_LWC2 0x32 +#define OP_OP_LWC3 0x33 /* a.k.a. pref */ +#define OP_OP_LDC1 0x35 +#define OP_OP_LDC2 0x36 +#define OP_OP_LDC3 0x37 /* a.k.a. ld */ +#define OP_OP_SWC1 0x39 +#define OP_OP_SWC2 0x3a +#define OP_OP_SWC3 0x3b +#define OP_OP_SDC1 0x3d +#define OP_OP_SDC2 0x3e +#define OP_OP_SDC3 0x3f /* a.k.a. sd */ + +/* Values in the 'VSEL' field. */ +#define MDMX_FMTSEL_IMM_QH 0x1d +#define MDMX_FMTSEL_IMM_OB 0x1e +#define MDMX_FMTSEL_VEC_QH 0x15 +#define MDMX_FMTSEL_VEC_OB 0x16 + +/* UDI */ +#define OP_SH_UDI1 6 +#define OP_MASK_UDI1 0x1f +#define OP_SH_UDI2 6 +#define OP_MASK_UDI2 0x3ff +#define OP_SH_UDI3 6 +#define OP_MASK_UDI3 0x7fff +#define OP_SH_UDI4 6 +#define OP_MASK_UDI4 0xfffff +/* This structure holds information for a particular instruction. */ + +struct mips_opcode +{ + /* The name of the instruction. */ + const char *name; + /* A string describing the arguments for this instruction. */ + const char *args; + /* The basic opcode for the instruction. When assembling, this + opcode is modified by the arguments to produce the actual opcode + that is used. If pinfo is INSN_MACRO, then this is 0. */ + unsigned long match; + /* If pinfo is not INSN_MACRO, then this is a bit mask for the + relevant portions of the opcode when disassembling. If the + actual opcode anded with the match field equals the opcode field, + then we have found the correct instruction. If pinfo is + INSN_MACRO, then this field is the macro identifier. */ + unsigned long mask; + /* For a macro, this is INSN_MACRO. Otherwise, it is a collection + of bits describing the instruction, notably any relevant hazard + information. */ + unsigned long pinfo; + /* A collection of additional bits describing the instruction. */ + unsigned long pinfo2; + /* A collection of bits describing the instruction sets of which this + instruction or macro is a member. */ + unsigned long membership; +}; + +/* These are the characters which may appear in the args field of an + instruction. They appear in the order in which the fields appear + when the instruction is used. Commas and parentheses in the args + string are ignored when assembling, and written into the output + when disassembling. + + Each of these characters corresponds to a mask field defined above. + + "<" 5 bit shift amount (OP_*_SHAMT) + ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) + "a" 26 bit target address (OP_*_TARGET) + "b" 5 bit base register (OP_*_RS) + "c" 10 bit breakpoint code (OP_*_CODE) + "d" 5 bit destination register specifier (OP_*_RD) + "h" 5 bit prefx hint (OP_*_PREFX) + "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) + "j" 16 bit signed immediate (OP_*_DELTA) + "k" 5 bit cache opcode in target register position (OP_*_CACHE) + Also used for immediate operands in vr5400 vector insns. + "o" 16 bit signed offset (OP_*_DELTA) + "p" 16 bit PC relative branch target address (OP_*_DELTA) + "q" 10 bit extra breakpoint code (OP_*_CODE2) + "r" 5 bit same register used as both source and target (OP_*_RS) + "s" 5 bit source register specifier (OP_*_RS) + "t" 5 bit target register (OP_*_RT) + "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) + "v" 5 bit same register used as both source and destination (OP_*_RS) + "w" 5 bit same register used as both target and destination (OP_*_RT) + "U" 5 bit same destination register in both OP_*_RD and OP_*_RT + (used by clo and clz) + "C" 25 bit coprocessor function code (OP_*_COPZ) + "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) + "J" 19 bit wait function code (OP_*_CODE19) + "x" accept and ignore register name + "z" must be zero register + "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) + "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes + LSB (OP_*_SHAMT). + Enforces: 0 <= pos < 32. + "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + (Also used by "dext" w/ different limits, but limits for + that are checked by the M_DEXT macro.) + "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). + Enforces: 32 <= pos < 64. + "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + + Floating point instructions: + "D" 5 bit destination register (OP_*_FD) + "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) + "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) + "S" 5 bit fs source 1 register (OP_*_FS) + "T" 5 bit ft source 2 register (OP_*_FT) + "R" 5 bit fr source 3 register (OP_*_FR) + "V" 5 bit same register used as floating source and destination (OP_*_FS) + "W" 5 bit same register used as floating target and destination (OP_*_FT) + + Coprocessor instructions: + "E" 5 bit target register (OP_*_RT) + "G" 5 bit destination register (OP_*_RD) + "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) + "P" 5 bit performance-monitor register (OP_*_PERFREG) + "e" 5 bit vector register byte specifier (OP_*_VECBYTE) + "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) + see also "k" above + "+D" Combined destination register ("G") and sel ("H") for CP0 ops, + for pretty-printing in disassembly only. + + Macro instructions: + "A" General 32 bit expression + "I" 32 bit immediate (value placed in imm_expr). + "+I" 32 bit immediate (value placed in imm2_expr). + "F" 64 bit floating point constant in .rdata + "L" 64 bit floating point constant in .lit8 + "f" 32 bit floating point constant + "l" 32 bit floating point constant in .lit4 + + MDMX instruction operands (note that while these use the FP register + fields, they accept both $fN and $vN names for the registers): + "O" MDMX alignment offset (OP_*_ALN) + "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + "X" MDMX destination register (OP_*_FD) + "Y" MDMX source register (OP_*_FS) + "Z" MDMX source register (OP_*_FT) + + DSP ASE usage: + "2" 2 bit unsigned immediate for byte align (OP_*_BP) + "3" 3 bit unsigned immediate (OP_*_SA3) + "4" 4 bit unsigned immediate (OP_*_SA4) + "5" 8 bit unsigned immediate (OP_*_IMM8) + "6" 5 bit unsigned immediate (OP_*_RS) + "7" 2 bit dsp accumulator register (OP_*_DSPACC) + "8" 6 bit unsigned immediate (OP_*_WRDSP) + "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) + "0" 6 bit signed immediate (OP_*_DSPSFT) + ":" 7 bit signed immediate (OP_*_DSPSFT_7) + "'" 6 bit unsigned immediate (OP_*_RDDSP) + "@" 10 bit signed immediate (OP_*_IMM10) + + MT ASE usage: + "!" 1 bit usermode flag (OP_*_MT_U) + "$" 1 bit load high flag (OP_*_MT_H) + "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) + "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) + "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) + "+t" 5 bit coprocessor 0 destination register (OP_*_RT) + "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only + + UDI immediates: + "+1" UDI immediate bits 6-10 + "+2" UDI immediate bits 6-15 + "+3" UDI immediate bits 6-20 + "+4" UDI immediate bits 6-25 + + Other: + "()" parens surrounding optional value + "," separates operands + "[]" brackets around index for vector-op scalar operand specifier (vr5400) + "+" Start of extension sequence. + + Characters used so far, for quick reference when adding more: + "234567890" + "%[]<>(),+:'@!$*&" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + "abcdefghijklopqrstuvwxz" + + Extension character sequences used so far ("+" followed by the + following), for quick reference when adding more: + "1234" + "ABCDEFGHIT" + "t" +*/ + +/* These are the bits which may be set in the pinfo field of an + instructions, if it is not equal to INSN_MACRO. */ + +/* Modifies the general purpose register in OP_*_RD. */ +#define INSN_WRITE_GPR_D 0x00000001 +/* Modifies the general purpose register in OP_*_RT. */ +#define INSN_WRITE_GPR_T 0x00000002 +/* Modifies general purpose register 31. */ +#define INSN_WRITE_GPR_31 0x00000004 +/* Modifies the floating point register in OP_*_FD. */ +#define INSN_WRITE_FPR_D 0x00000008 +/* Modifies the floating point register in OP_*_FS. */ +#define INSN_WRITE_FPR_S 0x00000010 +/* Modifies the floating point register in OP_*_FT. */ +#define INSN_WRITE_FPR_T 0x00000020 +/* Reads the general purpose register in OP_*_RS. */ +#define INSN_READ_GPR_S 0x00000040 +/* Reads the general purpose register in OP_*_RT. */ +#define INSN_READ_GPR_T 0x00000080 +/* Reads the floating point register in OP_*_FS. */ +#define INSN_READ_FPR_S 0x00000100 +/* Reads the floating point register in OP_*_FT. */ +#define INSN_READ_FPR_T 0x00000200 +/* Reads the floating point register in OP_*_FR. */ +#define INSN_READ_FPR_R 0x00000400 +/* Modifies coprocessor condition code. */ +#define INSN_WRITE_COND_CODE 0x00000800 +/* Reads coprocessor condition code. */ +#define INSN_READ_COND_CODE 0x00001000 +/* TLB operation. */ +#define INSN_TLB 0x00002000 +/* Reads coprocessor register other than floating point register. */ +#define INSN_COP 0x00004000 +/* Instruction loads value from memory, requiring delay. */ +#define INSN_LOAD_MEMORY_DELAY 0x00008000 +/* Instruction loads value from coprocessor, requiring delay. */ +#define INSN_LOAD_COPROC_DELAY 0x00010000 +/* Instruction has unconditional branch delay slot. */ +#define INSN_UNCOND_BRANCH_DELAY 0x00020000 +/* Instruction has conditional branch delay slot. */ +#define INSN_COND_BRANCH_DELAY 0x00040000 +/* Conditional branch likely: if branch not taken, insn nullified. */ +#define INSN_COND_BRANCH_LIKELY 0x00080000 +/* Moves to coprocessor register, requiring delay. */ +#define INSN_COPROC_MOVE_DELAY 0x00100000 +/* Loads coprocessor register from memory, requiring delay. */ +#define INSN_COPROC_MEMORY_DELAY 0x00200000 +/* Reads the HI register. */ +#define INSN_READ_HI 0x00400000 +/* Reads the LO register. */ +#define INSN_READ_LO 0x00800000 +/* Modifies the HI register. */ +#define INSN_WRITE_HI 0x01000000 +/* Modifies the LO register. */ +#define INSN_WRITE_LO 0x02000000 +/* Takes a trap (easier to keep out of delay slot). */ +#define INSN_TRAP 0x04000000 +/* Instruction stores value into memory. */ +#define INSN_STORE_MEMORY 0x08000000 +/* Instruction uses single precision floating point. */ +#define FP_S 0x10000000 +/* Instruction uses double precision floating point. */ +#define FP_D 0x20000000 +/* Instruction is part of the tx39's integer multiply family. */ +#define INSN_MULT 0x40000000 +/* Instruction synchronize shared memory. */ +#define INSN_SYNC 0x80000000 + +/* These are the bits which may be set in the pinfo2 field of an + instruction. */ + +/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ +#define INSN2_ALIAS 0x00000001 +/* Instruction reads MDMX accumulator. */ +#define INSN2_READ_MDMX_ACC 0x00000002 +/* Instruction writes MDMX accumulator. */ +#define INSN2_WRITE_MDMX_ACC 0x00000004 + +/* Instruction is actually a macro. It should be ignored by the + disassembler, and requires special treatment by the assembler. */ +#define INSN_MACRO 0xffffffff + +/* Masks used to mark instructions to indicate which MIPS ISA level + they were introduced in. ISAs, as defined below, are logical + ORs of these bits, indicating that they support the instructions + defined at the given level. */ + +#define INSN_ISA_MASK 0x00000fff +#define INSN_ISA1 0x00000001 +#define INSN_ISA2 0x00000002 +#define INSN_ISA3 0x00000004 +#define INSN_ISA4 0x00000008 +#define INSN_ISA5 0x00000010 +#define INSN_ISA32 0x00000020 +#define INSN_ISA64 0x00000040 +#define INSN_ISA32R2 0x00000080 +#define INSN_ISA64R2 0x00000100 + +/* Masks used for MIPS-defined ASEs. */ +#define INSN_ASE_MASK 0x0000f000 + +/* DSP ASE */ +#define INSN_DSP 0x00001000 +#define INSN_DSP64 0x00002000 +/* MIPS 16 ASE */ +#define INSN_MIPS16 0x00004000 +/* MIPS-3D ASE */ +#define INSN_MIPS3D 0x00008000 + +/* Chip specific instructions. These are bitmasks. */ + +/* MIPS R4650 instruction. */ +#define INSN_4650 0x00010000 +/* LSI R4010 instruction. */ +#define INSN_4010 0x00020000 +/* NEC VR4100 instruction. */ +#define INSN_4100 0x00040000 +/* Toshiba R3900 instruction. */ +#define INSN_3900 0x00080000 +/* MIPS R10000 instruction. */ +#define INSN_10000 0x00100000 +/* Broadcom SB-1 instruction. */ +#define INSN_SB1 0x00200000 +/* NEC VR4111/VR4181 instruction. */ +#define INSN_4111 0x00400000 +/* NEC VR4120 instruction. */ +#define INSN_4120 0x00800000 +/* NEC VR5400 instruction. */ +#define INSN_5400 0x01000000 +/* NEC VR5500 instruction. */ +#define INSN_5500 0x02000000 + +/* MDMX ASE */ +#define INSN_MDMX 0x04000000 +/* MT ASE */ +#define INSN_MT 0x08000000 +/* SmartMIPS ASE */ +#define INSN_SMARTMIPS 0x10000000 +/* DSP R2 ASE */ +#define INSN_DSPR2 0x20000000 + +/* MIPS ISA defines, use instead of hardcoding ISA level. */ + +#define ISA_UNKNOWN 0 /* Gas internal use. */ +#define ISA_MIPS1 (INSN_ISA1) +#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) +#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) +#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) +#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) + +#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) +#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) + +#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) +#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) + + +/* CPU defines, use instead of hardcoding processor number. Keep this + in sync with bfd/archures.c in order for machine selection to work. */ +#define CPU_UNKNOWN 0 /* Gas internal use. */ +#define CPU_R3000 3000 +#define CPU_R3900 3900 +#define CPU_R4000 4000 +#define CPU_R4010 4010 +#define CPU_VR4100 4100 +#define CPU_R4111 4111 +#define CPU_VR4120 4120 +#define CPU_R4300 4300 +#define CPU_R4400 4400 +#define CPU_R4600 4600 +#define CPU_R4650 4650 +#define CPU_R5000 5000 +#define CPU_VR5400 5400 +#define CPU_VR5500 5500 +#define CPU_R6000 6000 +#define CPU_RM7000 7000 +#define CPU_R8000 8000 +#define CPU_R10000 10000 +#define CPU_R12000 12000 +#define CPU_MIPS16 16 +#define CPU_MIPS32 32 +#define CPU_MIPS32R2 33 +#define CPU_MIPS5 5 +#define CPU_MIPS64 64 +#define CPU_MIPS64R2 65 +#define CPU_SB1 12310201 /* octal 'SB', 01. */ + +/* Test for membership in an ISA including chip specific ISAs. INSN + is pointer to an element of the opcode table; ISA is the specified + ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to + test, or zero if no CPU specific ISA test is desired. */ + +#if 0 +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ + (((insn)->membership & isa) != 0 \ + || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ + || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ + || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ + && ((insn)->membership & INSN_10000) != 0) \ + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ + || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ + || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ + || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ + || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ + || 0) /* Please keep this term for easier source merging. */ +#else +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ + (1 != 0) +#endif + +/* This is a list of macro expanded instructions. + + _I appended means immediate + _A appended means address + _AB appended means address with base register + _D appended means 64 bit floating point constant + _S appended means 32 bit floating point constant. */ + +enum +{ + M_ABS, + M_ADD_I, + M_ADDU_I, + M_AND_I, + M_BALIGN, + M_BEQ, + M_BEQ_I, + M_BEQL_I, + M_BGE, + M_BGEL, + M_BGE_I, + M_BGEL_I, + M_BGEU, + M_BGEUL, + M_BGEU_I, + M_BGEUL_I, + M_BGT, + M_BGTL, + M_BGT_I, + M_BGTL_I, + M_BGTU, + M_BGTUL, + M_BGTU_I, + M_BGTUL_I, + M_BLE, + M_BLEL, + M_BLE_I, + M_BLEL_I, + M_BLEU, + M_BLEUL, + M_BLEU_I, + M_BLEUL_I, + M_BLT, + M_BLTL, + M_BLT_I, + M_BLTL_I, + M_BLTU, + M_BLTUL, + M_BLTU_I, + M_BLTUL_I, + M_BNE, + M_BNE_I, + M_BNEL_I, + M_CACHE_AB, + M_DABS, + M_DADD_I, + M_DADDU_I, + M_DDIV_3, + M_DDIV_3I, + M_DDIVU_3, + M_DDIVU_3I, + M_DEXT, + M_DINS, + M_DIV_3, + M_DIV_3I, + M_DIVU_3, + M_DIVU_3I, + M_DLA_AB, + M_DLCA_AB, + M_DLI, + M_DMUL, + M_DMUL_I, + M_DMULO, + M_DMULO_I, + M_DMULOU, + M_DMULOU_I, + M_DREM_3, + M_DREM_3I, + M_DREMU_3, + M_DREMU_3I, + M_DSUB_I, + M_DSUBU_I, + M_DSUBU_I_2, + M_J_A, + M_JAL_1, + M_JAL_2, + M_JAL_A, + M_L_DOB, + M_L_DAB, + M_LA_AB, + M_LB_A, + M_LB_AB, + M_LBU_A, + M_LBU_AB, + M_LCA_AB, + M_LD_A, + M_LD_OB, + M_LD_AB, + M_LDC1_AB, + M_LDC2_AB, + M_LDC3_AB, + M_LDL_AB, + M_LDR_AB, + M_LH_A, + M_LH_AB, + M_LHU_A, + M_LHU_AB, + M_LI, + M_LI_D, + M_LI_DD, + M_LI_S, + M_LI_SS, + M_LL_AB, + M_LLD_AB, + M_LS_A, + M_LW_A, + M_LW_AB, + M_LWC0_A, + M_LWC0_AB, + M_LWC1_A, + M_LWC1_AB, + M_LWC2_A, + M_LWC2_AB, + M_LWC3_A, + M_LWC3_AB, + M_LWL_A, + M_LWL_AB, + M_LWR_A, + M_LWR_AB, + M_LWU_AB, + M_MOVE, + M_MUL, + M_MUL_I, + M_MULO, + M_MULO_I, + M_MULOU, + M_MULOU_I, + M_NOR_I, + M_OR_I, + M_REM_3, + M_REM_3I, + M_REMU_3, + M_REMU_3I, + M_DROL, + M_ROL, + M_DROL_I, + M_ROL_I, + M_DROR, + M_ROR, + M_DROR_I, + M_ROR_I, + M_S_DA, + M_S_DOB, + M_S_DAB, + M_S_S, + M_SC_AB, + M_SCD_AB, + M_SD_A, + M_SD_OB, + M_SD_AB, + M_SDC1_AB, + M_SDC2_AB, + M_SDC3_AB, + M_SDL_AB, + M_SDR_AB, + M_SEQ, + M_SEQ_I, + M_SGE, + M_SGE_I, + M_SGEU, + M_SGEU_I, + M_SGT, + M_SGT_I, + M_SGTU, + M_SGTU_I, + M_SLE, + M_SLE_I, + M_SLEU, + M_SLEU_I, + M_SLT_I, + M_SLTU_I, + M_SNE, + M_SNE_I, + M_SB_A, + M_SB_AB, + M_SH_A, + M_SH_AB, + M_SW_A, + M_SW_AB, + M_SWC0_A, + M_SWC0_AB, + M_SWC1_A, + M_SWC1_AB, + M_SWC2_A, + M_SWC2_AB, + M_SWC3_A, + M_SWC3_AB, + M_SWL_A, + M_SWL_AB, + M_SWR_A, + M_SWR_AB, + M_SUB_I, + M_SUBU_I, + M_SUBU_I_2, + M_TEQ_I, + M_TGE_I, + M_TGEU_I, + M_TLT_I, + M_TLTU_I, + M_TNE_I, + M_TRUNCWD, + M_TRUNCWS, + M_ULD, + M_ULD_A, + M_ULH, + M_ULH_A, + M_ULHU, + M_ULHU_A, + M_ULW, + M_ULW_A, + M_USH, + M_USH_A, + M_USW, + M_USW_A, + M_USD, + M_USD_A, + M_XOR_I, + M_COP0, + M_COP1, + M_COP2, + M_COP3, + M_NUM_MACROS +}; + + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Many instructions are short hand for other instructions (i.e., The + jal <register> instruction is short for jalr <register>). */ + +extern const struct mips_opcode mips_builtin_opcodes[]; +extern const int bfd_mips_num_builtin_opcodes; +extern struct mips_opcode *mips_opcodes; +extern int bfd_mips_num_opcodes; +#define NUMOPCODES bfd_mips_num_opcodes + + +/* The rest of this file adds definitions for the mips16 TinyRISC + processor. */ + +/* These are the bitmasks and shift counts used for the different + fields in the instruction formats. Other than OP, no masks are + provided for the fixed portions of an instruction, since they are + not needed. + + The I format uses IMM11. + + The RI format uses RX and IMM8. + + The RR format uses RX, and RY. + + The RRI format uses RX, RY, and IMM5. + + The RRR format uses RX, RY, and RZ. + + The RRI_A format uses RX, RY, and IMM4. + + The SHIFT format uses RX, RY, and SHAMT. + + The I8 format uses IMM8. + + The I8_MOVR32 format uses RY and REGR32. + + The IR_MOV32R format uses REG32R and MOV32Z. + + The I64 format uses IMM8. + + The RI64 format uses RY and IMM5. + */ + +#define MIPS16OP_MASK_OP 0x1f +#define MIPS16OP_SH_OP 11 +#define MIPS16OP_MASK_IMM11 0x7ff +#define MIPS16OP_SH_IMM11 0 +#define MIPS16OP_MASK_RX 0x7 +#define MIPS16OP_SH_RX 8 +#define MIPS16OP_MASK_IMM8 0xff +#define MIPS16OP_SH_IMM8 0 +#define MIPS16OP_MASK_RY 0x7 +#define MIPS16OP_SH_RY 5 +#define MIPS16OP_MASK_IMM5 0x1f +#define MIPS16OP_SH_IMM5 0 +#define MIPS16OP_MASK_RZ 0x7 +#define MIPS16OP_SH_RZ 2 +#define MIPS16OP_MASK_IMM4 0xf +#define MIPS16OP_SH_IMM4 0 +#define MIPS16OP_MASK_REGR32 0x1f +#define MIPS16OP_SH_REGR32 0 +#define MIPS16OP_MASK_REG32R 0x1f +#define MIPS16OP_SH_REG32R 3 +#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) +#define MIPS16OP_MASK_MOVE32Z 0x7 +#define MIPS16OP_SH_MOVE32Z 0 +#define MIPS16OP_MASK_IMM6 0x3f +#define MIPS16OP_SH_IMM6 5 + +/* These are the characters which may appears in the args field of an + instruction. They appear in the order in which the fields appear + when the instruction is used. Commas and parentheses in the args + string are ignored when assembling, and written into the output + when disassembling. + + "y" 3 bit register (MIPS16OP_*_RY) + "x" 3 bit register (MIPS16OP_*_RX) + "z" 3 bit register (MIPS16OP_*_RZ) + "Z" 3 bit register (MIPS16OP_*_MOVE32Z) + "v" 3 bit same register as source and destination (MIPS16OP_*_RX) + "w" 3 bit same register as source and destination (MIPS16OP_*_RY) + "0" zero register ($0) + "S" stack pointer ($sp or $29) + "P" program counter + "R" return address register ($ra or $31) + "X" 5 bit MIPS register (MIPS16OP_*_REGR32) + "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) + "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) + "a" 26 bit jump address + "e" 11 bit extension value + "l" register list for entry instruction + "L" register list for exit instruction + + The remaining codes may be extended. Except as otherwise noted, + the full extended operand is a 16 bit signed value. + "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) + ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) + "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) + "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) + "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) + "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) + "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) + "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) + "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) + "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) + "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) + "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) + "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) + "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) + "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) + "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) + "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) + "q" 11 bit branch address (MIPS16OP_*_IMM11) + "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) + "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) + "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) + */ + +/* Save/restore encoding for the args field when all 4 registers are + either saved as arguments or saved/restored as statics. */ +#define MIPS16_ALL_ARGS 0xe +#define MIPS16_ALL_STATICS 0xb + +/* For the mips16, we use the same opcode table format and a few of + the same flags. However, most of the flags are different. */ + +/* Modifies the register in MIPS16OP_*_RX. */ +#define MIPS16_INSN_WRITE_X 0x00000001 +/* Modifies the register in MIPS16OP_*_RY. */ +#define MIPS16_INSN_WRITE_Y 0x00000002 +/* Modifies the register in MIPS16OP_*_RZ. */ +#define MIPS16_INSN_WRITE_Z 0x00000004 +/* Modifies the T ($24) register. */ +#define MIPS16_INSN_WRITE_T 0x00000008 +/* Modifies the SP ($29) register. */ +#define MIPS16_INSN_WRITE_SP 0x00000010 +/* Modifies the RA ($31) register. */ +#define MIPS16_INSN_WRITE_31 0x00000020 +/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ +#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 +/* Reads the register in MIPS16OP_*_RX. */ +#define MIPS16_INSN_READ_X 0x00000080 +/* Reads the register in MIPS16OP_*_RY. */ +#define MIPS16_INSN_READ_Y 0x00000100 +/* Reads the register in MIPS16OP_*_MOVE32Z. */ +#define MIPS16_INSN_READ_Z 0x00000200 +/* Reads the T ($24) register. */ +#define MIPS16_INSN_READ_T 0x00000400 +/* Reads the SP ($29) register. */ +#define MIPS16_INSN_READ_SP 0x00000800 +/* Reads the RA ($31) register. */ +#define MIPS16_INSN_READ_31 0x00001000 +/* Reads the program counter. */ +#define MIPS16_INSN_READ_PC 0x00002000 +/* Reads the general purpose register in MIPS16OP_*_REGR32. */ +#define MIPS16_INSN_READ_GPR_X 0x00004000 +/* Is a branch insn. */ +#define MIPS16_INSN_BRANCH 0x00010000 + +/* The following flags have the same value for the mips16 opcode + table: + INSN_UNCOND_BRANCH_DELAY + INSN_COND_BRANCH_DELAY + INSN_COND_BRANCH_LIKELY (never used) + INSN_READ_HI + INSN_READ_LO + INSN_WRITE_HI + INSN_WRITE_LO + INSN_TRAP + INSN_ISA3 + */ + +extern const struct mips_opcode mips16_opcodes[]; +extern const int bfd_mips16_num_opcodes; + +/* Short hand so the lines aren't too long. */ + +#define LDD INSN_LOAD_MEMORY_DELAY +#define LCD INSN_LOAD_COPROC_DELAY +#define UBD INSN_UNCOND_BRANCH_DELAY +#define CBD INSN_COND_BRANCH_DELAY +#define COD INSN_COPROC_MOVE_DELAY +#define CLD INSN_COPROC_MEMORY_DELAY +#define CBL INSN_COND_BRANCH_LIKELY +#define TRAP INSN_TRAP +#define SM INSN_STORE_MEMORY + +#define WR_d INSN_WRITE_GPR_D +#define WR_t INSN_WRITE_GPR_T +#define WR_31 INSN_WRITE_GPR_31 +#define WR_D INSN_WRITE_FPR_D +#define WR_T INSN_WRITE_FPR_T +#define WR_S INSN_WRITE_FPR_S +#define RD_s INSN_READ_GPR_S +#define RD_b INSN_READ_GPR_S +#define RD_t INSN_READ_GPR_T +#define RD_S INSN_READ_FPR_S +#define RD_T INSN_READ_FPR_T +#define RD_R INSN_READ_FPR_R +#define WR_CC INSN_WRITE_COND_CODE +#define RD_CC INSN_READ_COND_CODE +#define RD_C0 INSN_COP +#define RD_C1 INSN_COP +#define RD_C2 INSN_COP +#define RD_C3 INSN_COP +#define WR_C0 INSN_COP +#define WR_C1 INSN_COP +#define WR_C2 INSN_COP +#define WR_C3 INSN_COP + +#define WR_HI INSN_WRITE_HI +#define RD_HI INSN_READ_HI +#define MOD_HI WR_HI|RD_HI + +#define WR_LO INSN_WRITE_LO +#define RD_LO INSN_READ_LO +#define MOD_LO WR_LO|RD_LO + +#define WR_HILO WR_HI|WR_LO +#define RD_HILO RD_HI|RD_LO +#define MOD_HILO WR_HILO|RD_HILO + +#define IS_M INSN_MULT + +#define WR_MACC INSN2_WRITE_MDMX_ACC +#define RD_MACC INSN2_READ_MDMX_ACC + +#define I1 INSN_ISA1 +#define I2 INSN_ISA2 +#define I3 INSN_ISA3 +#define I4 INSN_ISA4 +#define I5 INSN_ISA5 +#define I32 INSN_ISA32 +#define I64 INSN_ISA64 +#define I33 INSN_ISA32R2 +#define I65 INSN_ISA64R2 + +/* MIPS64 MIPS-3D ASE support. */ +#define I16 INSN_MIPS16 + +/* MIPS32 SmartMIPS ASE support. */ +#define SMT INSN_SMARTMIPS + +/* MIPS64 MIPS-3D ASE support. */ +#define M3D INSN_MIPS3D + +/* MIPS64 MDMX ASE support. */ +#define MX INSN_MDMX + +#define P3 INSN_4650 +#define L1 INSN_4010 +#define V1 (INSN_4100 | INSN_4111 | INSN_4120) +#define T3 INSN_3900 +#define M1 INSN_10000 +#define SB1 INSN_SB1 +#define N411 INSN_4111 +#define N412 INSN_4120 +#define N5 (INSN_5400 | INSN_5500) +#define N54 INSN_5400 +#define N55 INSN_5500 + +#define G1 (T3 \ + ) + +#define G2 (T3 \ + ) + +#define G3 (I4 \ + ) + +/* MIPS DSP ASE support. + NOTE: + 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair + of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have + the same structure as $ac0 (HI + LO). For DSP instructions that write or + read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a + (RD_HILO) attributes, such that HILO dependencies are maintained + conservatively. + + 2. For some mul. instructions that use integer registers as destinations + but destroy HI+LO as side-effect, we add WR_HILO to their attributes. + + 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields + (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write + certain fields of the DSP control register. For simplicity, we decide not + to track dependencies of these fields. + However, "bposge32" is a branch instruction that depends on the "pos" + field. In order to make sure that GAS does not reorder DSP instructions + that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) + attribute to those instructions that write the "pos" field. */ + +#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ +#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ +#define MOD_a WR_a|RD_a +#define DSP_VOLA INSN_TRAP +#define D32 INSN_DSP +#define D33 INSN_DSPR2 +#define D64 INSN_DSP64 + +/* MIPS MT ASE support. */ +#define MT32 INSN_MT + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. + + Many instructions are short hand for other instructions (i.e., The + jal <register> instruction is short for jalr <register>). */ + +const struct mips_opcode mips_builtin_opcodes[] = +{ +/* These instructions appear first so that the disassembler will find + them first. The assemblers uses a hash table based on the + instruction name anyhow. */ +/* name, args, match, mask, pinfo, membership */ +{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, +{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, +{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ +{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */ +{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ +{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ +{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ +{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, +{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, +{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ +{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ +{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ +{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ +{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ +{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ + +{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, +{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, +{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, +{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, +{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, +{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, +{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, +{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, +{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +/* b is at the top of the table. */ +/* bal is at the top of the table. */ +/* bc0[tf]l? are at the bottom of the table. */ +{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, +{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, +{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, +{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, +{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, +{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, +{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, +{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, +/* bc2* are at the bottom of the table. */ +/* bc3* are at the bottom of the table. */ +{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, +{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, +{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, +{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, +{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, +{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, +{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, +{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, +{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, +{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, +{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, +{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, +{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, +{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, +{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, +{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, +{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, +{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, +{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, +{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, +{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, +{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, +{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, +{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, +{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, +{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, +{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, +{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, +{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, +{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, +{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, +{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, +{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, +{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, +{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, +{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, +{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, +{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, +{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, +{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, +{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, +{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, +{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, +{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, +{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, +{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, +{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, +{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, +{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, +{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +/* CW4010 instructions which are aliases for the cache instruction. */ +{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, +{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, +{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, +{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, +{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, +{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, +{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, +{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, +{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, +{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, +/* cfc2 is at the bottom of the table. */ +/* cfc3 is at the bottom of the table. */ +{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, +{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, +{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, +{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, +{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, +{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, +/* ctc2 is at the bottom of the table. */ +/* ctc3 is at the bottom of the table. */ +{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, +{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, +{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, +{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, +{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, +{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, +{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, +{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, +{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, +{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, +{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, +{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, +{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, +{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, +{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, +{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, +{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, +{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, +{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, +{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, +/* dctr and dctw are used on the r5000. */ +{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, +{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, +{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, +{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, +{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, +/* For ddiv, see the comments about div. */ +{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, +{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, +/* For ddivu, see the comments about div. */ +{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, +{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, +{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, +{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, +{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, +{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, +/* The MIPS assembler treats the div opcode with two operands as + though the first operand appeared twice (the first operand is both + a source and a destination). To get the div machine instruction, + you must use an explicit destination of $0. */ +{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, +{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, +{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +/* For divu, see the comments about div. */ +{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, +{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, +{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, +{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, +{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ +{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ +{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, +{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, +{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, +{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, +{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, +{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, +{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, +{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, +{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, +{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, +{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, +{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, +{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, +/* dmfc2 is at the bottom of the table. */ +/* dmtc2 is at the bottom of the table. */ +/* dmfc3 is at the bottom of the table. */ +/* dmtc3 is at the bottom of the table. */ +{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, +{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, +{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, +{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, +{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, +{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, +{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ +{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ +{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, +{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, +{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, +{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, +{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, +{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, +{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, +{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, +{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, +{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, +{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, +{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, +{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, +{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, +{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, +{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, +{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, +{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, +{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, +{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, +{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ +{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ +{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ +{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ +{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ +{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ +{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, +{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, +{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, +{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, +{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, +{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, +{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, +{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, +{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, +{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, +{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, +{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, +{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, +{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, +/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with + the same hazard barrier effect. */ +{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, +{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ +/* SVR4 PIC code requires special handling for j, so it must be a + macro. */ +{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, +/* This form of j is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, +{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, +{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, +/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr + with the same hazard barrier effect. */ +{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, +{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, +/* SVR4 PIC code requires special handling for jal, so it must be a + macro. */ +{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, +{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, +{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, +/* This form of jal is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, +{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, +{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, +{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, +{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, +{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, +{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, +{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, +{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, +{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, +{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, +{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, +{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, +{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ +{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, +{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, +{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, +{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, +{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, +{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, +{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, +{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, +{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, +{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, +{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, +/* li is at the start of the table. */ +{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, +{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, +{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, +{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, +{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, +{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, +{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, +{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, +{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, +{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, +{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, +{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, +{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, +{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, +{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, +{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, +{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ +{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, +{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, +{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, +{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ +{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ +{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, +{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ +{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ +{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, +{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, +{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, +{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, +{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, +{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, +{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, +{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, +{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, +{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, +{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, +{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, +{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, +{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, +{"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, +{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, +{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, +{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, +{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, +{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, +{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, +{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, +{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, +{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, +{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, +{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, +{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, +{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, +/* mfc2 is at the bottom of the table. */ +/* mfhc2 is at the bottom of the table. */ +/* mfc3 is at the bottom of the table. */ +{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, +{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, +{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, +{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, +{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, +{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, +{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, +{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, +{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, +{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, +{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, +{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, +{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, +{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, +{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, +{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, +{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, +{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, +{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, +{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, +{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, +{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, +{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, +{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, +{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +/* move is at the top of the table. */ +{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, +{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, +{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, +{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, +{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, +{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, +{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, +{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, +{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, +{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, +{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, +{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, +/* mtc2 is at the bottom of the table. */ +/* mthc2 is at the bottom of the table. */ +/* mtc3 is at the bottom of the table. */ +{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, +{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, +{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, +{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, +{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, +{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, +{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, +{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, +{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, +{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, +{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, +{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, +{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, +{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, +{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, +{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, +{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, +{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, +{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, +{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, +{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, +{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, +{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, +{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, +{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, +{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, +{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ +{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ +{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, +{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, +{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, +{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, +{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, +{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, +{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, +/* nop is at the start of the table. */ +{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, +{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ +{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, +{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, +{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, + /* pref and prefx are at the start of the table. */ +{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, +{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, +{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, +{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, +{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, +{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, +{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, +{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, +{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, +{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, +{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, +{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, +{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, +{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, +{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, +{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, +{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, +{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, +{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, +{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, +{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, +{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, +{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, +{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, +{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, +{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, +{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, +{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, +{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, +{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, +{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, +{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, +{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, +{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, +{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, +{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, +{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, +{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, +{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, +{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, +{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, +{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, +{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, +{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, +{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 }, +{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, +{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, +{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, +{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, +{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, +{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, +{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, +{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, +{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, +{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, +{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, +{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, +{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, +{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, +{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, +{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, +{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, +{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ +{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, +{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, +{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, +{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, +{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, +{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, +{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ +{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, +{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ +{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, +{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +/* ssnop is at the start of the table. */ +{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, +{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, +{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, +{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, +{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, +{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, +{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, +{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, +{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, +{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, +{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, +{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, +{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ +{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, +{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, +{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, +{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, +{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ +{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ +{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, +{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ +{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ +{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 }, +{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, +{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, +{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, +{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, +{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, +{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, +{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, +{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, +{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, +{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, +{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, +{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, +{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, +{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, +{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, +{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, +{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, +{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, +{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, +{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, +{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, +{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, +{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, +{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, +{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, +{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, +{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, +{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, +{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, +{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, +{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, +{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, +{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, +{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, +{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, +{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, + +/* User Defined Instruction. */ +{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, + +/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format + instructions so they are here for the latters to take precedence. */ +{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, +{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, +{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, +{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, +{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, +{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, +{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, +{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, +{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, +{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, +{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, +{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, +{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, +{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, +{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, +{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, +{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, + +/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X + instructions, so they are here for the latters to take precedence. */ +{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, +{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, + +/* No hazard protection on coprocessor instructions--they shouldn't + change the state of the processor and if they do it's up to the + user to put in nops as necessary. These are at the end so that the + disassembler recognizes more specific versions first. */ +{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, +{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, +{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, +{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, +{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, +{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, +{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, +{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, + /* Conflicts with the 4650's "mul" instruction. Nobody's using the + 4010 any more, so move this insn out of the way. If the object + format gave us more info, we could do this right. */ +{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, +/* MIPS DSP ASE */ +{"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, +{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, +{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, +{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, +{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, +{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, +{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, +{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, +{"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, +{"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, +{"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, +{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, +{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, +{"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, +{"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, +{"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, +{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, +{"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, +{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, +{"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, +{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, +{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, +{"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, +{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, +{"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, +{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, +{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, +{"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, +{"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, +{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, +{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, +/* MIPS DSP ASE Rev2 */ +{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, +{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, +{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, +{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, +{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +/* Move bc0* after mftr and mttr to avoid opcode collision. */ +{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +}; + +#define MIPS_NUM_OPCODES \ + ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) +const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; + +/* const removed from the following to allow for dynamic extensions to the + * built-in instruction set. */ +struct mips_opcode *mips_opcodes = + (struct mips_opcode *) mips_builtin_opcodes; +int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; +#undef MIPS_NUM_OPCODES + +/* Mips instructions are at maximum this many bytes long. */ +#define INSNLEN 4 + + +/* FIXME: These should be shared with gdb somehow. */ + +struct mips_cp0sel_name +{ + unsigned int cp0reg; + unsigned int sel; + const char * const name; +}; + +/* The mips16 registers. */ +static const unsigned int mips16_to_32_reg_map[] = +{ + 16, 17, 2, 3, 4, 5, 6, 7 +}; + +#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] + + +static const char * const mips_gpr_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const mips_gpr_names_oldabi[32] = +{ + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" +}; + +static const char * const mips_gpr_names_newabi[32] = +{ + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" +}; + +static const char * const mips_fpr_names_numeric[32] = +{ + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" +}; + +static const char * const mips_fpr_names_32[32] = +{ + "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", + "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", + "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", + "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" +}; + +static const char * const mips_fpr_names_n32[32] = +{ + "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", + "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", + "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", + "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" +}; + +static const char * const mips_fpr_names_64[32] = +{ + "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", + "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", + "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", + "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" +}; + +static const char * const mips_cp0_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const mips_cp0_names_mips3264[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "$7", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_status", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "c0_debug", + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", + "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", +}; + +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = +{ + { 4, 1, "c0_contextconfig" }, + { 0, 1, "c0_mvpcontrol" }, + { 0, 2, "c0_mvpconf0" }, + { 0, 3, "c0_mvpconf1" }, + { 1, 1, "c0_vpecontrol" }, + { 1, 2, "c0_vpeconf0" }, + { 1, 3, "c0_vpeconf1" }, + { 1, 4, "c0_yqmask" }, + { 1, 5, "c0_vpeschedule" }, + { 1, 6, "c0_vpeschefback" }, + { 2, 1, "c0_tcstatus" }, + { 2, 2, "c0_tcbind" }, + { 2, 3, "c0_tcrestart" }, + { 2, 4, "c0_tchalt" }, + { 2, 5, "c0_tccontext" }, + { 2, 6, "c0_tcschedule" }, + { 2, 7, "c0_tcschefback" }, + { 5, 1, "c0_pagegrain" }, + { 6, 1, "c0_srsconf0" }, + { 6, 2, "c0_srsconf1" }, + { 6, 3, "c0_srsconf2" }, + { 6, 4, "c0_srsconf3" }, + { 6, 5, "c0_srsconf4" }, + { 12, 1, "c0_intctl" }, + { 12, 2, "c0_srsctl" }, + { 12, 3, "c0_srsmap" }, + { 15, 1, "c0_ebase" }, + { 16, 1, "c0_config1" }, + { 16, 2, "c0_config2" }, + { 16, 3, "c0_config3" }, + { 18, 1, "c0_watchlo,1" }, + { 18, 2, "c0_watchlo,2" }, + { 18, 3, "c0_watchlo,3" }, + { 18, 4, "c0_watchlo,4" }, + { 18, 5, "c0_watchlo,5" }, + { 18, 6, "c0_watchlo,6" }, + { 18, 7, "c0_watchlo,7" }, + { 19, 1, "c0_watchhi,1" }, + { 19, 2, "c0_watchhi,2" }, + { 19, 3, "c0_watchhi,3" }, + { 19, 4, "c0_watchhi,4" }, + { 19, 5, "c0_watchhi,5" }, + { 19, 6, "c0_watchhi,6" }, + { 19, 7, "c0_watchhi,7" }, + { 23, 1, "c0_tracecontrol" }, + { 23, 2, "c0_tracecontrol2" }, + { 23, 3, "c0_usertracedata" }, + { 23, 4, "c0_tracebpc" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 27, 1, "c0_cacheerr,1" }, + { 27, 2, "c0_cacheerr,2" }, + { 27, 3, "c0_cacheerr,3" }, + { 28, 1, "c0_datalo" }, + { 28, 2, "c0_taglo1" }, + { 28, 3, "c0_datalo1" }, + { 28, 4, "c0_taglo2" }, + { 28, 5, "c0_datalo2" }, + { 28, 6, "c0_taglo3" }, + { 28, 7, "c0_datalo3" }, + { 29, 1, "c0_datahi" }, + { 29, 2, "c0_taghi1" }, + { 29, 3, "c0_datahi1" }, + { 29, 4, "c0_taghi2" }, + { 29, 5, "c0_datahi2" }, + { 29, 6, "c0_taghi3" }, + { 29, 7, "c0_datahi3" }, +}; + +static const char * const mips_cp0_names_mips3264r2[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_status", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "c0_debug", + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", + "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", +}; + +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = +{ + { 4, 1, "c0_contextconfig" }, + { 5, 1, "c0_pagegrain" }, + { 12, 1, "c0_intctl" }, + { 12, 2, "c0_srsctl" }, + { 12, 3, "c0_srsmap" }, + { 15, 1, "c0_ebase" }, + { 16, 1, "c0_config1" }, + { 16, 2, "c0_config2" }, + { 16, 3, "c0_config3" }, + { 18, 1, "c0_watchlo,1" }, + { 18, 2, "c0_watchlo,2" }, + { 18, 3, "c0_watchlo,3" }, + { 18, 4, "c0_watchlo,4" }, + { 18, 5, "c0_watchlo,5" }, + { 18, 6, "c0_watchlo,6" }, + { 18, 7, "c0_watchlo,7" }, + { 19, 1, "c0_watchhi,1" }, + { 19, 2, "c0_watchhi,2" }, + { 19, 3, "c0_watchhi,3" }, + { 19, 4, "c0_watchhi,4" }, + { 19, 5, "c0_watchhi,5" }, + { 19, 6, "c0_watchhi,6" }, + { 19, 7, "c0_watchhi,7" }, + { 23, 1, "c0_tracecontrol" }, + { 23, 2, "c0_tracecontrol2" }, + { 23, 3, "c0_usertracedata" }, + { 23, 4, "c0_tracebpc" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 27, 1, "c0_cacheerr,1" }, + { 27, 2, "c0_cacheerr,2" }, + { 27, 3, "c0_cacheerr,3" }, + { 28, 1, "c0_datalo" }, + { 28, 2, "c0_taglo1" }, + { 28, 3, "c0_datalo1" }, + { 28, 4, "c0_taglo2" }, + { 28, 5, "c0_datalo2" }, + { 28, 6, "c0_taglo3" }, + { 28, 7, "c0_datalo3" }, + { 29, 1, "c0_datahi" }, + { 29, 2, "c0_taghi1" }, + { 29, 3, "c0_datahi1" }, + { 29, 4, "c0_taghi2" }, + { 29, 5, "c0_datahi2" }, + { 29, 6, "c0_taghi3" }, + { 29, 7, "c0_datahi3" }, +}; + +/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ +static const char * const mips_cp0_names_sb1[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "$7", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_status", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "c0_debug", + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", + "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", +}; + +static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = +{ + { 16, 1, "c0_config1" }, + { 18, 1, "c0_watchlo,1" }, + { 19, 1, "c0_watchhi,1" }, + { 22, 0, "c0_perftrace" }, + { 23, 3, "c0_edebug" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 26, 1, "c0_buserr_pa" }, + { 27, 1, "c0_cacheerr_d" }, + { 27, 3, "c0_cacheerr_d_pa" }, + { 28, 1, "c0_datalo_i" }, + { 28, 2, "c0_taglo_d" }, + { 28, 3, "c0_datalo_d" }, + { 29, 1, "c0_datahi_i" }, + { 29, 2, "c0_taghi_d" }, + { 29, 3, "c0_datahi_d" }, +}; + +static const char * const mips_hwr_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const mips_hwr_names_mips3264r2[32] = +{ + "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", + "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +struct mips_abi_choice +{ + const char *name; + const char * const *gpr_names; + const char * const *fpr_names; +}; + +struct mips_abi_choice mips_abi_choices[] = +{ + { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, + { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, + { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, + { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, +}; + +struct mips_arch_choice +{ + const char *name; + int bfd_mach_valid; + unsigned long bfd_mach; + int processor; + int isa; + const char * const *cp0_names; + const struct mips_cp0sel_name *cp0sel_names; + unsigned int cp0sel_names_len; + const char * const *hwr_names; +}; + +#define bfd_mach_mips3000 3000 +#define bfd_mach_mips3900 3900 +#define bfd_mach_mips4000 4000 +#define bfd_mach_mips4010 4010 +#define bfd_mach_mips4100 4100 +#define bfd_mach_mips4111 4111 +#define bfd_mach_mips4120 4120 +#define bfd_mach_mips4300 4300 +#define bfd_mach_mips4400 4400 +#define bfd_mach_mips4600 4600 +#define bfd_mach_mips4650 4650 +#define bfd_mach_mips5000 5000 +#define bfd_mach_mips5400 5400 +#define bfd_mach_mips5500 5500 +#define bfd_mach_mips6000 6000 +#define bfd_mach_mips7000 7000 +#define bfd_mach_mips8000 8000 +#define bfd_mach_mips9000 9000 +#define bfd_mach_mips10000 10000 +#define bfd_mach_mips12000 12000 +#define bfd_mach_mips16 16 +#define bfd_mach_mips5 5 +#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ +#define bfd_mach_mipsisa32 32 +#define bfd_mach_mipsisa32r2 33 +#define bfd_mach_mipsisa64 64 +#define bfd_mach_mipsisa64r2 65 + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) + +const struct mips_arch_choice mips_arch_choices[] = +{ + { "numeric", 0, 0, 0, 0, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + + { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + + /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. + Note that MIPS-3D and MDMX are not applicable to MIPS32. (See + _MIPS32 Architecture For Programmers Volume I: Introduction to the + MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), + page 1. */ + { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, + ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, + mips_cp0_names_mips3264, + mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), + mips_hwr_names_numeric }, + + { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, + (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 + | INSN_MIPS3D | INSN_MT), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, + + /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ + { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, + ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, + mips_cp0_names_mips3264, + mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), + mips_hwr_names_numeric }, + + { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, + (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 + | INSN_DSP64 | INSN_MT | INSN_MDMX), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, + + { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, + ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, + mips_cp0_names_sb1, + mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), + mips_hwr_names_numeric }, + + /* This entry, mips16, is here only for ISA/processor selection; do + not print its name. */ + { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, +}; + +/* ISA and processor type to disassemble for, and register names to use. + set_default_mips_dis_options and parse_mips_dis_options fill in these + values. */ +static int mips_processor; +static int mips_isa; +static const char * const *mips_gpr_names; +static const char * const *mips_fpr_names; +static const char * const *mips_cp0_names; +static const struct mips_cp0sel_name *mips_cp0sel_names; +static int mips_cp0sel_names_len; +static const char * const *mips_hwr_names; + +/* Other options */ +static int no_aliases; /* If set disassemble as most general inst. */ + +static const struct mips_abi_choice * +choose_abi_by_name (const char *name, unsigned int namelen) +{ + const struct mips_abi_choice *c; + unsigned int i; + + for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) + if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 + && strlen (mips_abi_choices[i].name) == namelen) + c = &mips_abi_choices[i]; + + return c; +} + +static const struct mips_arch_choice * +choose_arch_by_name (const char *name, unsigned int namelen) +{ + const struct mips_arch_choice *c = NULL; + unsigned int i; + + for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) + if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 + && strlen (mips_arch_choices[i].name) == namelen) + c = &mips_arch_choices[i]; + + return c; +} + +static const struct mips_arch_choice * +choose_arch_by_number (unsigned long mach) +{ + static unsigned long hint_bfd_mach; + static const struct mips_arch_choice *hint_arch_choice; + const struct mips_arch_choice *c; + unsigned int i; + + /* We optimize this because even if the user specifies no + flags, this will be done for every instruction! */ + if (hint_bfd_mach == mach + && hint_arch_choice != NULL + && hint_arch_choice->bfd_mach == hint_bfd_mach) + return hint_arch_choice; + + for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) + { + if (mips_arch_choices[i].bfd_mach_valid + && mips_arch_choices[i].bfd_mach == mach) + { + c = &mips_arch_choices[i]; + hint_bfd_mach = mach; + hint_arch_choice = c; + } + } + return c; +} + +static void +set_default_mips_dis_options (struct disassemble_info *info) +{ + const struct mips_arch_choice *chosen_arch; + + /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, + and numeric FPR, CP0 register, and HWR names. */ + mips_isa = ISA_MIPS3; + mips_processor = CPU_R3000; + mips_gpr_names = mips_gpr_names_oldabi; + mips_fpr_names = mips_fpr_names_numeric; + mips_cp0_names = mips_cp0_names_numeric; + mips_cp0sel_names = NULL; + mips_cp0sel_names_len = 0; + mips_hwr_names = mips_hwr_names_numeric; + no_aliases = 0; + + /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ +#if 0 + if (info->flavour == bfd_target_elf_flavour && info->section != NULL) + { + Elf_Internal_Ehdr *header; + + header = elf_elfheader (info->section->owner); + if (is_newabi (header)) + mips_gpr_names = mips_gpr_names_newabi; + } +#endif + + /* Set ISA, architecture, and cp0 register names as best we can. */ +#if !defined(SYMTAB_AVAILABLE) && 0 + /* This is running out on a target machine, not in a host tool. + FIXME: Where does mips_target_info come from? */ + target_processor = mips_target_info.processor; + mips_isa = mips_target_info.isa; +#else + chosen_arch = choose_arch_by_number (info->mach); + if (chosen_arch != NULL) + { + mips_processor = chosen_arch->processor; + mips_isa = chosen_arch->isa; + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_hwr_names = chosen_arch->hwr_names; + } +#endif +} + +static void +parse_mips_dis_option (const char *option, unsigned int len) +{ + unsigned int i, optionlen, vallen; + const char *val; + const struct mips_abi_choice *chosen_abi; + const struct mips_arch_choice *chosen_arch; + + /* Look for the = that delimits the end of the option name. */ + for (i = 0; i < len; i++) + { + if (option[i] == '=') + break; + } + if (i == 0) /* Invalid option: no name before '='. */ + return; + if (i == len) /* Invalid option: no '='. */ + return; + if (i == (len - 1)) /* Invalid option: no value after '='. */ + return; + + optionlen = i; + val = option + (optionlen + 1); + vallen = len - (optionlen + 1); + + if (strncmp("gpr-names", option, optionlen) == 0 + && strlen("gpr-names") == optionlen) + { + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + mips_gpr_names = chosen_abi->gpr_names; + return; + } + + if (strncmp("fpr-names", option, optionlen) == 0 + && strlen("fpr-names") == optionlen) + { + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + mips_fpr_names = chosen_abi->fpr_names; + return; + } + + if (strncmp("cp0-names", option, optionlen) == 0 + && strlen("cp0-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + { + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + } + return; + } + + if (strncmp("hwr-names", option, optionlen) == 0 + && strlen("hwr-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + mips_hwr_names = chosen_arch->hwr_names; + return; + } + + if (strncmp("reg-names", option, optionlen) == 0 + && strlen("reg-names") == optionlen) + { + /* We check both ABI and ARCH here unconditionally, so + that "numeric" will do the desirable thing: select + numeric register names for all registers. Other than + that, a given name probably won't match both. */ + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + { + mips_gpr_names = chosen_abi->gpr_names; + mips_fpr_names = chosen_abi->fpr_names; + } + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + { + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_hwr_names = chosen_arch->hwr_names; + } + return; + } + + /* Invalid option. */ +} + +static void +parse_mips_dis_options (const char *options) +{ + const char *option_end; + + if (options == NULL) + return; + + while (*options != '\0') + { + /* Skip empty options. */ + if (*options == ',') + { + options++; + continue; + } + + /* We know that *options is neither NUL or a comma. */ + option_end = options + 1; + while (*option_end != ',' && *option_end != '\0') + option_end++; + + parse_mips_dis_option (options, option_end - options); + + /* Go on to the next one. If option_end points to a comma, it + will be skipped above. */ + options = option_end; + } +} + +static const struct mips_cp0sel_name * +lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, + unsigned int len, + unsigned int cp0reg, + unsigned int sel) +{ + unsigned int i; + + for (i = 0; i < len; i++) + if (names[i].cp0reg == cp0reg && names[i].sel == sel) + return &names[i]; + return NULL; +} + +/* Print insn arguments for 32/64-bit code. */ + +static void +print_insn_args (const char *d, + register unsigned long int l, + bfd_vma pc, + struct disassemble_info *info, + const struct mips_opcode *opp) +{ + int op, delta; + unsigned int lsb, msb, msbd; + + lsb = 0; + + for (; *d != '\0'; d++) + { + switch (*d) + { + case ',': + case '(': + case ')': + case '[': + case ']': + (*info->fprintf_func) (info->stream, "%c", *d); + break; + + case '+': + /* Extension character; switch for second char. */ + d++; + switch (*d) + { + case '\0': + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, + _("# internal error, incomplete extension sequence (+)")); + return; + + case 'A': + lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; + (*info->fprintf_func) (info->stream, "0x%x", lsb); + break; + + case 'B': + msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; + (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); + break; + + case '1': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI1) & OP_MASK_UDI1); + break; + + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI2) & OP_MASK_UDI2); + break; + + case '3': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI3) & OP_MASK_UDI3); + break; + + case '4': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI4) & OP_MASK_UDI4); + break; + + case 'C': + case 'H': + msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; + (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); + break; + + case 'D': + { + const struct mips_cp0sel_name *n; + unsigned int cp0reg, sel; + + cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; + sel = (l >> OP_SH_SEL) & OP_MASK_SEL; + + /* CP0 register including 'sel' code for mtcN (et al.), to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name(mips_cp0sel_names, + mips_cp0sel_names_len, cp0reg, sel); + if (n != NULL) + (*info->fprintf_func) (info->stream, "%s", n->name); + else + (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); + break; + } + + case 'E': + lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; + (*info->fprintf_func) (info->stream, "0x%x", lsb); + break; + + case 'F': + msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); + break; + + case 'G': + msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); + break; + + case 't': /* Coprocessor 0 reg name */ + (*info->fprintf_func) (info->stream, "%s", + mips_cp0_names[(l >> OP_SH_RT) & + OP_MASK_RT]); + break; + + case 'T': /* Coprocessor 0 reg name */ + { + const struct mips_cp0sel_name *n; + unsigned int cp0reg, sel; + + cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; + sel = (l >> OP_SH_SEL) & OP_MASK_SEL; + + /* CP0 register including 'sel' code for mftc0, to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name(mips_cp0sel_names, + mips_cp0sel_names_len, cp0reg, sel); + if (n != NULL) + (*info->fprintf_func) (info->stream, "%s", n->name); + else + (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); + break; + } + + default: + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, + _("# internal error, undefined extension sequence (+%c)"), + *d); + return; + } + break; + + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_BP) & OP_MASK_BP); + break; + + case '3': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_SA3) & OP_MASK_SA3); + break; + + case '4': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_SA4) & OP_MASK_SA4); + break; + + case '5': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_IMM8) & OP_MASK_IMM8); + break; + + case '6': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_RS) & OP_MASK_RS); + break; + + case '7': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); + break; + + case '8': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); + break; + + case '9': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); + break; + + case '0': /* dsp 6-bit signed immediate in bit 20 */ + delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); + if (delta & 0x20) /* test sign bit */ + delta |= ~OP_MASK_DSPSFT; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case ':': /* dsp 7-bit signed immediate in bit 19 */ + delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); + if (delta & 0x40) /* test sign bit */ + delta |= ~OP_MASK_DSPSFT_7; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case '\'': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); + break; + + case '@': /* dsp 10-bit signed immediate in bit 16 */ + delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); + if (delta & 0x200) /* test sign bit */ + delta |= ~OP_MASK_IMM10; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case '!': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_MT_U) & OP_MASK_MT_U); + break; + + case '$': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_MT_H) & OP_MASK_MT_H); + break; + + case '*': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); + break; + + case '&': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); + break; + + case 'g': + /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ + (*info->fprintf_func) (info->stream, "$%ld", + (l >> OP_SH_RD) & OP_MASK_RD); + break; + + case 's': + case 'b': + case 'r': + case 'v': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); + break; + + case 't': + case 'w': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); + break; + + case 'i': + case 'u': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); + break; + + case 'j': /* Same as i, but sign-extended. */ + case 'o': + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + (*info->fprintf_func) (info->stream, "%d", + delta); + break; + + case 'h': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_PREFX) + & OP_MASK_PREFX)); + break; + + case 'k': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_CACHE) + & OP_MASK_CACHE)); + break; + + case 'a': + info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) + | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); + /* For gdb disassembler, force odd address on jalx. */ + if (info->flavour == bfd_target_unknown_flavour + && strcmp (opp->name, "jalx") == 0) + info->target |= 1; + (*info->print_address_func) (info->target, info); + break; + + case 'p': + /* Sign extend the displacement. */ + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + info->target = (delta << 2) + pc + INSNLEN; + (*info->print_address_func) (info->target, info); + break; + + case 'd': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); + break; + + case 'U': + { + /* First check for both rd and rt being equal. */ + unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; + if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[reg]); + else + { + /* If one is zero use the other. */ + if (reg == 0) + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); + else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[reg]); + else /* Bogus, result depends on processor. */ + (*info->fprintf_func) (info->stream, "%s or %s", + mips_gpr_names[reg], + mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); + } + } + break; + + case 'z': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); + break; + + case '<': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); + break; + + case 'c': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CODE) & OP_MASK_CODE); + break; + + case 'q': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CODE2) & OP_MASK_CODE2); + break; + + case 'C': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_COPZ) & OP_MASK_COPZ); + break; + + case 'B': + (*info->fprintf_func) (info->stream, "0x%lx", + + (l >> OP_SH_CODE20) & OP_MASK_CODE20); + break; + + case 'J': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CODE19) & OP_MASK_CODE19); + break; + + case 'S': + case 'V': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); + break; + + case 'T': + case 'W': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); + break; + + case 'D': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); + break; + + case 'E': + /* Coprocessor register for lwcN instructions, et al. + + Note that there is no load/store cp0 instructions, and + that FPU (cp1) instructions disassemble this field using + 'T' format. Therefore, until we gain understanding of + cp2 register names, we can simply print the register + numbers. */ + (*info->fprintf_func) (info->stream, "$%ld", + (l >> OP_SH_RT) & OP_MASK_RT); + break; + + case 'G': + /* Coprocessor register for mtcN instructions, et al. Note + that FPU (cp1) instructions disassemble this field using + 'S' format. Therefore, we only need to worry about cp0, + cp2, and cp3. */ + op = (l >> OP_SH_OP) & OP_MASK_OP; + if (op == OP_OP_COP0) + (*info->fprintf_func) (info->stream, "%s", + mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); + else + (*info->fprintf_func) (info->stream, "$%ld", + (l >> OP_SH_RD) & OP_MASK_RD); + break; + + case 'K': + (*info->fprintf_func) (info->stream, "%s", + mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); + break; + + case 'N': + (*info->fprintf_func) (info->stream, + ((opp->pinfo & (FP_D | FP_S)) != 0 + ? "$fcc%ld" : "$cc%ld"), + (l >> OP_SH_BCC) & OP_MASK_BCC); + break; + + case 'M': + (*info->fprintf_func) (info->stream, "$fcc%ld", + (l >> OP_SH_CCC) & OP_MASK_CCC); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); + break; + + case 'e': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); + break; + + case '%': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); + break; + + case 'H': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_SEL) & OP_MASK_SEL); + break; + + case 'O': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_ALN) & OP_MASK_ALN); + break; + + case 'Q': + { + unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; + + if ((vsel & 0x10) == 0) + { + int fmt; + + vsel &= 0x0f; + for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) + if ((vsel & 1) == 0) + break; + (*info->fprintf_func) (info->stream, "$v%ld[%d]", + (l >> OP_SH_FT) & OP_MASK_FT, + vsel >> 1); + } + else if ((vsel & 0x08) == 0) + { + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FT) & OP_MASK_FT); + } + else + { + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_FT) & OP_MASK_FT); + } + } + break; + + case 'X': + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FD) & OP_MASK_FD); + break; + + case 'Y': + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FS) & OP_MASK_FS); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FT) & OP_MASK_FT); + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, + _("# internal error, undefined modifier(%c)"), + *d); + return; + } + } +} + +/* Check if the object uses NewABI conventions. */ +#if 0 +static int +is_newabi (header) + Elf_Internal_Ehdr *header; +{ + /* There are no old-style ABIs which use 64-bit ELF. */ + if (header->e_ident[EI_CLASS] == ELFCLASS64) + return 1; + + /* If a 32-bit ELF file, n32 is a new-style ABI. */ + if ((header->e_flags & EF_MIPS_ABI2) != 0) + return 1; + + return 0; +} +#endif + +/* Print the mips instruction at address MEMADDR in debugged memory, + on using INFO. Returns length of the instruction, in bytes, which is + always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if + this is little-endian code. */ + +static int +print_insn_mips (bfd_vma memaddr, + unsigned long int word, + struct disassemble_info *info) +{ + const struct mips_opcode *op; + static bfd_boolean init = 0; + static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; + + /* Build a hash table to shorten the search time. */ + if (! init) + { + unsigned int i; + + for (i = 0; i <= OP_MASK_OP; i++) + { + for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo == INSN_MACRO + || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) + continue; + if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) + { + mips_hash[i] = op; + break; + } + } + } + + init = 1; + } + + info->bytes_per_chunk = INSNLEN; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; + if (op != NULL) + { + for (; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo != INSN_MACRO + && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) + && (word & op->mask) == op->match) + { + const char *d; + + /* We always allow to disassemble the jalx instruction. */ + if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) + && strcmp (op->name, "jalx")) + continue; + + /* Figure out instruction type and branch delay information. */ + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + if ((info->insn_type & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_jsr; + else + info->insn_type = dis_branch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_COND_BRANCH_DELAY + | INSN_COND_BRANCH_LIKELY)) != 0) + { + if ((info->insn_type & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_condjsr; + else + info->insn_type = dis_condbranch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_STORE_MEMORY + | INSN_LOAD_MEMORY_DELAY)) != 0) + info->insn_type = dis_dref; + + (*info->fprintf_func) (info->stream, "%s", op->name); + + d = op->args; + if (d != NULL && *d != '\0') + { + (*info->fprintf_func) (info->stream, "\t"); + print_insn_args (d, word, memaddr, info, op); + } + + return INSNLEN; + } + } + } + + /* Handle undefined instructions. */ + info->insn_type = dis_noninsn; + (*info->fprintf_func) (info->stream, "0x%lx", word); + return INSNLEN; +} + +/* In an environment where we do not know the symbol type of the + instruction we are forced to assume that the low order bit of the + instructions' address may mark it as a mips16 instruction. If we + are single stepping, or the pc is within the disassembled function, + this works. Otherwise, we need a clue. Sometimes. */ + +static int +_print_insn_mips (bfd_vma memaddr, + struct disassemble_info *info, + enum bfd_endian endianness) +{ + bfd_byte buffer[INSNLEN]; + int status; + + set_default_mips_dis_options (info); + parse_mips_dis_options (info->disassembler_options); + +#if 0 +#if 1 + /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ + /* Only a few tools will work this way. */ + if (memaddr & 0x01) + return print_insn_mips16 (memaddr, info); +#endif + +#if SYMTAB_AVAILABLE + if (info->mach == bfd_mach_mips16 + || (info->flavour == bfd_target_elf_flavour + && info->symbols != NULL + && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other + == STO_MIPS16))) + return print_insn_mips16 (memaddr, info); +#endif +#endif + + status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); + if (status == 0) + { + unsigned long insn; + + if (endianness == BFD_ENDIAN_BIG) + insn = (unsigned long) bfd_getb32 (buffer); + else + insn = (unsigned long) bfd_getl32 (buffer); + + return print_insn_mips (memaddr, insn, info); + } + else + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } +} + +int +print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); +} + +int +print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); +} + +/* Disassemble mips16 instructions. */ +#if 0 +static int +print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[2]; + int length; + int insn; + bfd_boolean use_extend; + int extend = 0; + const struct mips_opcode *op, *opend; + + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + length = 2; + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Handle the extend opcode specially. */ + use_extend = FALSE; + if ((insn & 0xf800) == 0xf000) + { + use_extend = TRUE; + extend = insn & 0x7ff; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Check for an extend opcode followed by an extend opcode. */ + if ((insn & 0xf800) == 0xf000) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length; + } + + length += 2; + } + + /* FIXME: Should probably use a hash table on the major opcode here. */ + + opend = mips16_opcodes + bfd_mips16_num_opcodes; + for (op = mips16_opcodes; op < opend; op++) + { + if (op->pinfo != INSN_MACRO + && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) + && (insn & op->mask) == op->match) + { + const char *s; + + if (strchr (op->args, 'a') != NULL) + { + if (use_extend) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length - 2; + } + + use_extend = FALSE; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, + info); + if (status == 0) + { + use_extend = TRUE; + if (info->endian == BFD_ENDIAN_BIG) + extend = bfd_getb16 (buffer); + else + extend = bfd_getl16 (buffer); + length += 2; + } + } + + (*info->fprintf_func) (info->stream, "%s", op->name); + if (op->args[0] != '\0') + (*info->fprintf_func) (info->stream, "\t"); + + for (s = op->args; *s != '\0'; s++) + { + if (*s == ',' + && s[1] == 'w' + && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) + == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + if (*s == ',' + && s[1] == 'v' + && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) + == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, + info); + } + + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + info->branch_delay_insns = 1; + if (info->insn_type != dis_jsr) + info->insn_type = dis_branch; + } + + return length; + } + } + + if (use_extend) + (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); + (*info->fprintf_func) (info->stream, "0x%x", insn); + info->insn_type = dis_noninsn; + + return length; +} + +/* Disassemble an operand for a mips16 instruction. */ + +static void +print_mips16_insn_arg (char type, + const struct mips_opcode *op, + int l, + bfd_boolean use_extend, + int extend, + bfd_vma memaddr, + struct disassemble_info *info) +{ + switch (type) + { + case ',': + case '(': + case ')': + (*info->fprintf_func) (info->stream, "%c", type); + break; + + case 'y': + case 'w': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY))); + break; + + case 'x': + case 'v': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX))); + break; + + case 'z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ))); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z))); + break; + + case '0': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); + break; + + case 'S': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "$pc"); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); + break; + + case 'X': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[((l >> MIPS16OP_SH_REGR32) + & MIPS16OP_MASK_REGR32)]); + break; + + case 'Y': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); + break; + + case '<': + case '>': + case '[': + case ']': + case '4': + case '5': + case 'H': + case 'W': + case 'D': + case 'j': + case '6': + case '8': + case 'V': + case 'C': + case 'U': + case 'k': + case 'K': + case 'p': + case 'q': + case 'A': + case 'B': + case 'E': + { + int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; + + shift = 0; + signedp = 0; + extbits = 16; + pcrel = 0; + extu = 0; + branch = 0; + switch (type) + { + case '<': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 5; + extu = 1; + break; + case '>': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 5; + extu = 1; + break; + case '[': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 6; + extu = 1; + break; + case ']': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 6; + extu = 1; + break; + case '4': + nbits = 4; + immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; + signedp = 1; + extbits = 15; + break; + case '5': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 1; + break; + case 'H': + nbits = 5; + shift = 1; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 2; + break; + case 'W': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 + && (op->pinfo & MIPS16_INSN_READ_SP) == 0) + { + info->insn_type = dis_dref; + info->data_size = 4; + } + break; + case 'D': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'j': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + signedp = 1; + break; + case '6': + nbits = 6; + immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + break; + case '8': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + break; + case 'V': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + /* FIXME: This might be lw, or it might be addiu to $sp or + $pc. We assume it's load. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'C': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'U': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + extu = 1; + break; + case 'k': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'K': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'p': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + pcrel = 1; + branch = 1; + info->insn_type = dis_condbranch; + break; + case 'q': + nbits = 11; + immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; + signedp = 1; + pcrel = 1; + branch = 1; + info->insn_type = dis_branch; + break; + case 'A': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + pcrel = 1; + /* FIXME: This can be lw or la. We assume it is lw. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'B': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'E': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + break; + default: + abort (); + } + + if (! use_extend) + { + if (signedp && immed >= (1 << (nbits - 1))) + immed -= 1 << nbits; + immed <<= shift; + if ((type == '<' || type == '>' || type == '[' || type == ']') + && immed == 0) + immed = 8; + } + else + { + if (extbits == 16) + immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); + else if (extbits == 15) + immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); + else + immed = ((extend >> 6) & 0x1f) | (extend & 0x20); + immed &= (1 << extbits) - 1; + if (! extu && immed >= (1 << (extbits - 1))) + immed -= 1 << extbits; + } + + if (! pcrel) + (*info->fprintf_func) (info->stream, "%d", immed); + else + { + bfd_vma baseaddr; + + if (branch) + { + immed *= 2; + baseaddr = memaddr + 2; + } + else if (use_extend) + baseaddr = memaddr - 2; + else + { + int status; + bfd_byte buffer[2]; + + baseaddr = memaddr; + + /* If this instruction is in the delay slot of a jr + instruction, the base address is the address of the + jr instruction. If it is in the delay slot of jalr + instruction, the base address is the address of the + jalr instruction. This test is unreliable: we have + no way of knowing whether the previous word is + instruction or data. */ + status = (*info->read_memory_func) (memaddr - 4, buffer, 2, + info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf800) == 0x1800)) + baseaddr = memaddr - 4; + else + { + status = (*info->read_memory_func) (memaddr - 2, buffer, + 2, info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf81f) == 0xe800)) + baseaddr = memaddr - 2; + } + } + info->target = (baseaddr & ~((1 << shift) - 1)) + immed; + if (pcrel && branch + && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + info->target |= 1; + (*info->print_address_func) (info->target, info); + } + } + break; + + case 'a': + { + int jalx = l & 0x400; + + if (! use_extend) + extend = 0; + l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + if (!jalx && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + l |= 1; + } + info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; + (*info->print_address_func) (info->target, info); + info->insn_type = dis_jsr; + info->branch_delay_insns = 1; + break; + + case 'l': + case 'L': + { + int need_comma, amask, smask; + + need_comma = 0; + + l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + + amask = (l >> 3) & 7; + + if (amask > 0 && amask < 5) + { + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); + if (amask > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[amask + 3]); + need_comma = 1; + } + + smask = (l >> 1) & 3; + if (smask == 3) + { + (*info->fprintf_func) (info->stream, "%s??", + need_comma ? "," : ""); + need_comma = 1; + } + else if (smask > 0) + { + (*info->fprintf_func) (info->stream, "%s%s", + need_comma ? "," : "", + mips_gpr_names[16]); + if (smask > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[smask + 15]); + need_comma = 1; + } + + if (l & 1) + { + (*info->fprintf_func) (info->stream, "%s%s", + need_comma ? "," : "", + mips_gpr_names[31]); + need_comma = 1; + } + + if (amask == 5 || amask == 6) + { + (*info->fprintf_func) (info->stream, "%s$f0", + need_comma ? "," : ""); + if (amask == 6) + (*info->fprintf_func) (info->stream, "-$f1"); + } + } + break; + + case 'm': + case 'M': + /* MIPS16e save/restore. */ + { + int need_comma = 0; + int amask, args, statics; + int nsreg, smask; + int framesz; + int i, j; + + l = l & 0x7f; + if (use_extend) + l |= extend << 16; + + amask = (l >> 16) & 0xf; + if (amask == MIPS16_ALL_ARGS) + { + args = 4; + statics = 0; + } + else if (amask == MIPS16_ALL_STATICS) + { + args = 0; + statics = 4; + } + else + { + args = amask >> 2; + statics = amask & 3; + } + + if (args > 0) { + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); + if (args > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[4 + args - 1]); + need_comma = 1; + } + + framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; + if (framesz == 0 && !use_extend) + framesz = 128; + + (*info->fprintf_func) (info->stream, "%s%d", + need_comma ? "," : "", + framesz); + + if (l & 0x40) /* $ra */ + (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); + + nsreg = (l >> 24) & 0x7; + smask = 0; + if (l & 0x20) /* $s0 */ + smask |= 1 << 0; + if (l & 0x10) /* $s1 */ + smask |= 1 << 1; + if (nsreg > 0) /* $s2-$s8 */ + smask |= ((1 << nsreg) - 1) << 2; + + /* Find first set static reg bit. */ + for (i = 0; i < 9; i++) + { + if (smask & (1 << i)) + { + (*info->fprintf_func) (info->stream, ",%s", + mips_gpr_names[i == 8 ? 30 : (16 + i)]); + /* Skip over string of set bits. */ + for (j = i; smask & (2 << j); j++) + continue; + if (j > i) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[j == 8 ? 30 : (16 + j)]); + i = j + 1; + } + } + + /* Statics $ax - $a3. */ + if (statics == 1) + (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); + else if (statics > 0) + (*info->fprintf_func) (info->stream, ",%s-%s", + mips_gpr_names[7 - statics + 1], + mips_gpr_names[7]); + } + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) + (info->stream, + _("# internal disassembler error, unrecognised modifier (%c)"), + type); + abort (); + } +} + +void +print_mips_disassembler_options (FILE *stream) +{ + unsigned int i; + + fprintf (stream, _("\n\ +The following MIPS specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _("\n\ + gpr-names=ABI Print GPR names according to specified ABI.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + fpr-names=ABI Print FPR names according to specified ABI.\n\ + Default: numeric.\n")); + + fprintf (stream, _("\n\ + cp0-names=ARCH Print CP0 register names according to\n\ + specified architecture.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + hwr-names=ARCH Print HWR names according to specified \n\ + architecture.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + reg-names=ABI Print GPR and FPR names according to\n\ + specified ABI.\n")); + + fprintf (stream, _("\n\ + reg-names=ARCH Print CP0 register and HWR names according to\n\ + specified architecture.\n")); + + fprintf (stream, _("\n\ + For the options above, the following values are supported for \"ABI\":\n\ + ")); + for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) + fprintf (stream, " %s", mips_abi_choices[i].name); + fprintf (stream, _("\n")); + + fprintf (stream, _("\n\ + For the options above, The following values are supported for \"ARCH\":\n\ + ")); + for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) + if (*mips_arch_choices[i].name != '\0') + fprintf (stream, " %s", mips_arch_choices[i].name); + fprintf (stream, _("\n")); + + fprintf (stream, _("\n")); +} +#endif @@ -186,10 +186,10 @@ int qemu_accept(int s, struct sockaddr *addr, socklen_t *addrlen) } #ifdef WIN32 -int asprintf( char **, char *, ... ); -int vasprintf( char **, char *, va_list ); +int asprintf( char **, const char *, ... ); +int vasprintf( char **, const char *, va_list ); -int vasprintf( char **sptr, char *fmt, va_list argv ) +int vasprintf( char **sptr, const char *fmt, va_list argv ) { int wanted = vsnprintf( *sptr = NULL, 0, fmt, argv ); if( (wanted > 0) && ((*sptr = malloc( 1 + wanted )) != NULL) ) @@ -198,7 +198,7 @@ int vasprintf( char **sptr, char *fmt, va_list argv ) return wanted; } -int asprintf( char **sptr, char *fmt, ... ) +int asprintf( char **sptr, const char *fmt, ... ) { int retval; va_list argv; diff --git a/qemu-common.h b/qemu-common.h index 897d510..79ac779 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -395,4 +395,17 @@ typedef enum DisplayType DT_NOGRAPHIC, } DisplayType; +/* + * A fixer for timeout value passed to select() on Mac. The issue is that Mac's + * version of select() will return EINVAL on timeouts larger than 100000000 + * seconds, even though it should have just clamped it. So, for Mac we should + * make sure that timeout value is bound to 100000000 seconds before passing it + * to select(). + */ +#if _DARWIN_C_SOURCE +#define CLAMP_MAC_TIMEOUT(to) do { if (to > 100000000000LL) to = 100000000000LL; } while (0) +#else +#define CLAMP_MAC_TIMEOUT(to) ((void)0) +#endif // _DARWIN_C_SOURCE + #endif @@ -125,7 +125,7 @@ static const WinsockError _winsock_errors[] = { * errno. */ static int -_fix_errno( void ) +fix_errno( void ) { const WinsockError* werr = _winsock_errors; int unix = EINVAL; /* generic error code */ @@ -143,7 +143,7 @@ _fix_errno( void ) } static int -_set_errno( int code ) +set_errno( int code ) { winsock_error = -1; errno = code; @@ -173,13 +173,13 @@ _errno_str(void) } #else static int -_fix_errno( void ) +fix_errno( void ) { return -1; } static int -_set_errno( int code ) +set_errno( int code ) { errno = code; return -1; @@ -560,7 +560,7 @@ sock_address_to_bsd( const SockAddress* a, sockaddr_storage* paddress, socklen #endif /* HAVE_UNIX_SOCKETS */ default: - return _set_errno(EINVAL); + return set_errno(EINVAL); } return 0; @@ -575,7 +575,7 @@ sock_address_from_bsd( SockAddress* a, const void* from, size_t fromlen ) const struct sockaddr_in* src = from; if (fromlen < sizeof(*src)) - return _set_errno(EINVAL); + return set_errno(EINVAL); a->family = SOCKET_INET; a->u.inet.port = ntohs(src->sin_port); @@ -589,7 +589,7 @@ sock_address_from_bsd( SockAddress* a, const void* from, size_t fromlen ) const struct sockaddr_in6* src = from; if (fromlen < sizeof(*src)) - return _set_errno(EINVAL); + return set_errno(EINVAL); a->family = SOCKET_IN6; a->u.in6.port = ntohs(src->sin6_port); @@ -605,12 +605,12 @@ sock_address_from_bsd( SockAddress* a, const void* from, size_t fromlen ) char* end; if (fromlen < sizeof(*src)) - return _set_errno(EINVAL); + return set_errno(EINVAL); /* check that the path is zero-terminated */ end = memchr(src->sun_path, 0, UNIX_PATH_MAX); if (end == NULL) - return _set_errno(EINVAL); + return set_errno(EINVAL); a->family = SOCKET_UNIX; a->u._unix.owner = 1; @@ -620,7 +620,7 @@ sock_address_from_bsd( SockAddress* a, const void* from, size_t fromlen ) #endif default: - return _set_errno(EINVAL); + return set_errno(EINVAL); } return 0; } @@ -646,7 +646,8 @@ sock_address_init_resolve( SockAddress* a, const char* hostname, uint16_t por err = EHOSTDOWN; break; -#ifdef EAI_NODATA +/* NOTE that in x86_64-w64-mingw32 both EAI_NODATA and EAI_NONAME are the same */ +#if defined(EAI_NODATA) && (EAI_NODATA != EAI_NONAME) case EAI_NODATA: #endif case EAI_NONAME: @@ -660,7 +661,7 @@ sock_address_init_resolve( SockAddress* a, const char* hostname, uint16_t por default: err = EINVAL; } - return _set_errno(err); + return set_errno(err); } /* Parse the returned list of addresses. */ @@ -699,7 +700,7 @@ sock_address_init_resolve( SockAddress* a, const char* hostname, uint16_t por } if (r == NULL) { - ret = _set_errno(ENOENT); + ret = set_errno(ENOENT); goto Exit; } @@ -765,13 +766,13 @@ sock_address_list_create( const char* hostname, case EAI_ADDRFAMILY: #endif case EAI_NODATA: - _set_errno(ENOENT); + set_errno(ENOENT); break; case EAI_FAMILY: - _set_errno(EAFNOSUPPORT); + set_errno(EAFNOSUPPORT); break; case EAI_AGAIN: - _set_errno(EAGAIN); + set_errno(EAGAIN); break; #ifdef EAI_SYSTEM case EAI_SYSTEM: @@ -780,7 +781,7 @@ sock_address_list_create( const char* hostname, break; #endif default: - _set_errno(EINVAL); + set_errno(EINVAL); } return NULL; } @@ -874,7 +875,7 @@ sock_address_get_numeric_info( SockAddress* a, break; #endif default: - return _set_errno(EINVAL); + return set_errno(EINVAL); } ret = getnameinfo( saddr, slen, host, hostlen, serv, servlen, @@ -900,12 +901,12 @@ socket_create( SocketFamily family, SocketType type ) int stype = socket_type_to_bsd(type); if (sfamily < 0 || stype < 0) { - return _set_errno(EINVAL); + return set_errno(EINVAL); } QSOCKET_CALL(ret, socket(sfamily, stype, 0)); if (ret < 0) - return _fix_errno(); + return fix_errno(); return ret; } @@ -956,7 +957,7 @@ int socket_can_read(int fd) int ret; \ QSOCKET_CALL(ret, (cmd)); \ if (ret < 0) \ - return _fix_errno(); \ + return fix_errno(); \ return ret; \ int @@ -998,7 +999,7 @@ socket_recvfrom(int fd, void* buf, int len, SockAddress* from) QSOCKET_CALL(ret,recvfrom(fd,buf,len,0,sa.sa,&salen)); if (ret < 0) - return _fix_errno(); + return fix_errno(); if (sock_address_from_bsd(from, &sa, salen) < 0) return -1; @@ -1039,7 +1040,7 @@ socket_get_address( int fd, SockAddress* address ) QSOCKET_CALL(ret, getsockname(fd, addr.sa, &addrlen)); if (ret < 0) - return _fix_errno(); + return fix_errno(); return sock_address_from_bsd(address, &addr, addrlen); } @@ -1053,7 +1054,7 @@ socket_get_peer_address( int fd, SockAddress* address ) QSOCKET_CALL(ret, getpeername(fd, addr.sa, &addrlen)); if (ret < 0) - return _fix_errno(); + return fix_errno(); return sock_address_from_bsd(address, &addr, addrlen); } @@ -1073,7 +1074,7 @@ socket_accept( int fd, SockAddress* address ) QSOCKET_CALL(ret, accept(fd, addr.sa, &addrlen)); if (ret < 0) - return _fix_errno(); + return fix_errno(); if (address) { if (sock_address_from_bsd(address, &addr, addrlen) < 0) { @@ -1517,7 +1518,7 @@ socket_mcast_inet_add_membership( int s, uint32_t ip ) (const char *)&imr, sizeof(struct ip_mreq)) < 0 ) { - return _fix_errno(); + return fix_errno(); } return 0; } @@ -1534,7 +1535,7 @@ socket_mcast_inet_drop_membership( int s, uint32_t ip ) (const char *)&imr, sizeof(struct ip_mreq)) < 0 ) { - return _fix_errno(); + return fix_errno(); } return 0; } diff --git a/tap-win32.c b/tap-win32.c index ba93355..ce30a50 100644 --- a/tap-win32.c +++ b/tap-win32.c @@ -31,13 +31,7 @@ #include "sysemu.h" #include <stdio.h> #include <windows.h> - -/* NOTE: PCIBus is redefined in winddk.h */ -#define PCIBus _PCIBus -#include <ddk/ntapi.h> -#include <ddk/winddk.h> -#include <ddk/ntddk.h> -#undef PCIBus +#include <winioctl.h> //============= // TAP IOCTLs diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 88547cb..adf91cb 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -258,9 +258,9 @@ #define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */ -#define MCI_STATUS_VAL (1UL<<63) /* valid error */ -#define MCI_STATUS_OVER (1UL<<62) /* previous errors lost */ -#define MCI_STATUS_UC (1UL<<61) /* uncorrected error */ +#define MCI_STATUS_VAL (1ULL<<63) /* valid error */ +#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ +#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ #define MSR_IA32_TSC 0x10 #define MSR_IA32_APICBASE 0x1b diff --git a/target-i386/hax-all.c b/target-i386/hax-all.c index 18d65d0..2540f54 100644 --- a/target-i386/hax-all.c +++ b/target-i386/hax-all.c @@ -120,10 +120,41 @@ hax_fd hax_vcpu_get_fd(CPUState *env) } /* Current version */ -uint32_t hax_cur_version = 0x1; +uint32_t hax_cur_version = 0x2; /* Least HAX kernel version */ uint32_t hax_lest_version = 0x1; +static int hax_get_capability(struct hax_state *hax) +{ + int ret; + struct hax_capabilityinfo capinfo, *cap = &capinfo; + + ret = hax_capability(hax, cap); + if (ret) + return -ENOSYS; + + if ( ((cap->wstatus & HAX_CAP_WORKSTATUS_MASK) == + HAX_CAP_STATUS_NOTWORKING )) + { + if (cap->winfo & HAX_CAP_FAILREASON_VT) + dprint("VT feature is not enabled, HAXM not working.\n"); + else if (cap->winfo & HAX_CAP_FAILREASON_NX) + dprint("NX feature is not enabled, HAXM not working.\n"); + return -ENXIO; + } + + if (cap->wstatus & HAX_CAP_MEMQUOTA) + { + if (cap->mem_quota < hax->mem_quota) + { + dprint("The memory needed by this VM exceeds the driver limit.\n"); + return -ENOSPC; + } + } + + return 0; +} + static int hax_version_support(struct hax_state *hax) { int ret; @@ -258,8 +289,7 @@ struct hax_vm *hax_vm_create(struct hax_state *hax) if (!vm) return NULL; memset(vm, 0, sizeof(struct hax_vm)); - - ret = hax_host_create_vm(hax, vm_id); + ret = hax_host_create_vm(hax, &vm_id); if (ret) { dprint("Failed to create vm %x\n", ret); goto error; @@ -297,15 +327,25 @@ int hax_vm_destroy(struct hax_vm *vm) return 0; } +int hax_set_ramsize(uint64_t ramsize) +{ + struct hax_state *hax = &hax_global; + + memset(hax, 0, sizeof(struct hax_state)); + hax->mem_quota = ram_size; + + return 0; +} + int hax_init(int smp_cpus) { struct hax_state *hax = NULL; + struct hax_qemu_version qversion; int ret; hax_support = 0; hax = &hax_global; - memset(hax, 0, sizeof(struct hax_state)); hax->fd = hax_mod_open(); if (hax_invalid_fd(hax->fd)) @@ -315,6 +355,14 @@ int hax_init(int smp_cpus) goto error; } + ret = hax_get_capability(hax); + /* In case HAXM have no such capability support */ + if (ret && (ret != -ENOSYS)) + { + ret = -EINVAL; + goto error; + } + if (!hax_version_support(hax)) { dprint("Incompatible HAX version. Qemu current version %x ", hax_cur_version ); @@ -331,6 +379,9 @@ int hax_init(int smp_cpus) goto error; } + qversion.cur_version = hax_cur_version; + qversion.least_version = hax_lest_version; + hax_notify_qemu_version(hax->vm->fd, &qversion); hax_support = 1; qemu_register_reset( hax_reset_vcpu_state, 0, NULL); @@ -344,6 +395,31 @@ error: return ret; } +int hax_handle_fastmmio(CPUState *env, struct hax_fastmmio *hft) +{ + uint64_t buf = 0; + + /* + * With fast MMIO, QEMU need not sync vCPU state with HAXM + * driver because it will only invoke MMIO handler + * However, some MMIO operations utilize virtual address like qemu_pipe + * Thus we need to sync the CR0, CR3 and CR4 so that QEMU + * can translate the guest virtual address to guest physical + * address + */ + env->cr[0] = hft->_cr0; + env->cr[2] = hft->_cr2; + env->cr[3] = hft->_cr3; + env->cr[4] = hft->_cr4; + + buf = hft->value; + cpu_physical_memory_rw(hft->gpa, &buf, hft->size, hft->direction); + if (hft->direction == 0) + hft->value = buf; + + return 0; +} + int hax_handle_io(CPUState *env, uint32_t df, uint16_t port, int direction, int size, int count, void *buffer) { @@ -491,6 +567,10 @@ static int hax_vcpu_hax_exec(CPUState *env) case HAX_EXIT_MMIO: ret = HAX_EMUL_ONE; break; + case HAX_EXIT_FAST_MMIO: + ret = hax_handle_fastmmio(env, + (struct hax_fastmmio *)vcpu->iobuf); + break; case HAX_EXIT_REAL: ret = HAX_EMUL_REAL; break; diff --git a/target-i386/hax-darwin.c b/target-i386/hax-darwin.c index b6d27c3..19a1c2d 100644 --- a/target-i386/hax-darwin.c +++ b/target-i386/hax-darwin.c @@ -85,6 +85,20 @@ int hax_set_phys_mem(target_phys_addr_t start_addr, ram_addr_t size, ram_addr_t return ret; } +int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap) +{ + int ret; + + ret = ioctl(hax->fd, HAX_IOCTL_CAPABILITY, cap); + if (ret == -1) + { + dprint("Failed to get HAX capability\n"); + return -errno; + } + + return 0; +} + int hax_mod_version(struct hax_state *hax, struct hax_module_version *version) { int ret; @@ -136,9 +150,10 @@ static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id) return name; } -int hax_host_create_vm(struct hax_state *hax, int vm_id) +int hax_host_create_vm(struct hax_state *hax, int *vmid) { int ret; + int vm_id = 0; if (hax_invalid_fd(hax->fd)) return -EINVAL; @@ -147,7 +162,7 @@ int hax_host_create_vm(struct hax_state *hax, int vm_id) return 0; ret = ioctl(hax->fd, HAX_IOCTL_CREATE_VM, &vm_id); - + *vmid = vm_id; return ret; } @@ -166,6 +181,23 @@ hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id) return fd; } +int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversion) +{ + int ret; + + if (hax_invalid_fd(vm_fd)) + return -EINVAL; + + ret = ioctl(vm_fd, HAX_VM_IOCTL_NOTIFY_QEMU_VERSION, qversion); + if (ret == -1) + { + dprint("Failed to notify qemu API version\n"); + return -errno; + } + + return 0; +} + /* * Simply assume that the size should be bigger than the hax_tunnel, * since the hax_tunnel can be extended later with backward diff --git a/target-i386/hax-darwin.h b/target-i386/hax-darwin.h index 261cfd3..95a9b31 100644 --- a/target-i386/hax-darwin.h +++ b/target-i386/hax-darwin.h @@ -40,6 +40,8 @@ static inline void hax_close_fd(hax_fd fd) #define HAX_IOCTL_VERSION _IOWR(0, 0x20, struct hax_module_version) /* Create VM instance and return the vm_id */ #define HAX_IOCTL_CREATE_VM _IOWR(0, 0x21, int) +/* Get HAXM capability information */ +#define HAX_IOCTL_CAPABILITY _IOR(0, 0x23, struct hax_capabilityinfo) /* Pass down a VM_ID, create a VCPU instance for it */ #define HAX_VM_IOCTL_VCPU_CREATE _IOR(0, 0x80, int) @@ -57,6 +59,14 @@ static inline void hax_close_fd(hax_fd fd) * Setup translation between guest physical address and host physical address */ #define HAX_VM_IOCTL_SET_RAM _IOWR(0, 0x82, struct hax_set_ram_info) + +/* + * QEMU notify HAXM driver of the API version currently in use, so that + * HAXM driver will not present features that possibly not supported + * by QEMU + */ +#define HAX_VM_IOCTL_NOTIFY_QEMU_VERSION _IOW(0, 0x84, struct hax_qemu_version) + /* Run the guest in non-root mode */ #define HAX_VCPU_IOCTL_RUN _IO(0, 0xc0) /* Sync QEMU's guest MSR value to HAX driver */ diff --git a/target-i386/hax-i386.h b/target-i386/hax-i386.h index e55e584..66869da 100644 --- a/target-i386/hax-i386.h +++ b/target-i386/hax-i386.h @@ -40,6 +40,7 @@ struct hax_state hax_fd fd; /* the global hax device interface */ uint32_t version; struct hax_vm *vm; + uint64_t mem_quota; }; #define HAX_MAX_VCPU 0x10 @@ -67,9 +68,11 @@ int hax_sync_vcpu_state(CPUState *env, struct vcpu_state_t *state, int set); int hax_sync_msr(CPUState *env, struct hax_msr_data *msrs, int set); int hax_sync_fpu(CPUState *env, struct fx_layout *fl, int set); int hax_vm_destroy(struct hax_vm *vm); +int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap); +int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversion); /* Common host function */ -int hax_host_create_vm(struct hax_state *hax, int vm_id); +int hax_host_create_vm(struct hax_state *hax, int *vm_id); hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id); int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid); hax_fd hax_host_open_vcpu(int vmid, int vcpuid); diff --git a/target-i386/hax-interface.h b/target-i386/hax-interface.h index 5a9ed31..22d4acc 100644 --- a/target-i386/hax-interface.h +++ b/target-i386/hax-interface.h @@ -316,6 +316,14 @@ enum exit_status { * Now the vcpu is only paused when to be destroid, so simply return to hax */ HAX_EXIT_PAUSED, + /* from API 2.0 */ + /* + * In API 1.0, HAXM driver utilizes QEMU to decode and emulate MMIO + * operations. + * From 2.0, HAXM driver will decode some MMIO instructions to improve + * MMIO handling performance, especially for GLES hardware acceleration + */ + HAX_EXIT_FAST_MMIO, }; /* @@ -328,6 +336,15 @@ struct hax_module_version uint32_t cur_version; }; +/* This interface is support only after API version 2 */ +struct hax_qemu_version +{ + /* Current API version in QEMU*/ + uint32_t cur_version; + /* The least API version supported by QEMU */ + uint32_t least_version; +}; + /* See comments for HAX_VM_IOCTL_ALLOC_RAM ioctl */ struct hax_alloc_ram_info { @@ -347,4 +364,55 @@ struct hax_set_ram_info uint64_t va; }; +/* + * We need to load the HAXM (HAX Manager) to tell if the host system has the + * required capabilities to operate, and we use hax_capabilityinfo to get such + * info from HAXM. + * + * To prevent HAXM from over-consuming RAM, we set the maximum amount of RAM + * that can be used for guests at HAX installation time. Once the quota is + * reached, HAXM will no longer attempt to allocate memory for guests. + * Detect that HAXM is out of quota can take the emulator to non-HAXM model + */ +struct hax_capabilityinfo +{ + /* bit 0: 1 - HAXM is working + * 0 - HAXM is not working possibly because VT/NX is disabled + NX means Non-eXecution, aks. XD (eXecution Disable) + * bit 1: 1 - HAXM has hard limit on how many RAM can be used as guest RAM + * 0 - HAXM has no memory limitation + */ +#define HAX_CAP_STATUS_WORKING 0x1 +#define HAX_CAP_STATUS_NOTWORKING 0x0 +#define HAX_CAP_WORKSTATUS_MASK 0x1 +#define HAX_CAP_MEMQUOTA 0x2 + uint16_t wstatus; + /* + * valid when HAXM is not working + * bit 0: HAXM is not working because VT is not enabeld + * bit 1: HAXM is not working because NX not enabled + */ +#define HAX_CAP_FAILREASON_VT 0x1 +#define HAX_CAP_FAILREASON_NX 0x2 + uint16_t winfo; + uint32_t pad; + uint64_t mem_quota; +}; + +/* API 2.0 */ + +struct hax_fastmmio +{ + uint64_t gpa; + uint64_t value; + uint8_t size; + uint8_t direction; + uint16_t reg_index; + uint32_t pad0; + uint64_t _cr0; + uint64_t _cr2; + uint64_t _cr3; + uint64_t _cr4; +}; + #endif diff --git a/target-i386/hax-windows.c b/target-i386/hax-windows.c index 683a227..6c52388 100644 --- a/target-i386/hax-windows.c +++ b/target-i386/hax-windows.c @@ -133,6 +133,36 @@ int hax_set_phys_mem(target_phys_addr_t start_addr, ram_addr_t size, ram_addr_t return 0; } +int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap) +{ + int ret; + HANDLE hDevice = hax->fd; //handle to hax module + DWORD dSize = 0; + DWORD err = 0; + + if (hax_invalid_fd(hDevice)) { + dprint("Invalid fd for hax device!\n"); + return -ENODEV; + } + + ret = DeviceIoControl(hDevice, + HAX_IOCTL_CAPABILITY, + NULL, 0, + cap, sizeof(*cap), + &dSize, + (LPOVERLAPPED) NULL); + + if (!ret) { + err = GetLastError(); + if (err == ERROR_INSUFFICIENT_BUFFER || + err == ERROR_MORE_DATA) + dprint("hax capability is too long to hold.\n"); + dprint("Failed to get Hax capability:%d\n", err); + return -EFAULT; + } else + return 0; +} + int hax_mod_version(struct hax_state *hax, struct hax_module_version *version) { int ret; @@ -198,9 +228,10 @@ static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id) return name; } -int hax_host_create_vm(struct hax_state *hax, int vm_id) +int hax_host_create_vm(struct hax_state *hax, int *vmid) { int ret; + int vm_id = 0; DWORD dSize = 0; if (hax_invalid_fd(hax->fd)) @@ -219,7 +250,7 @@ int hax_host_create_vm(struct hax_state *hax, int vm_id) dprint("error code:%d", GetLastError()); return -1; } - + *vmid = vm_id; return 0; } @@ -248,6 +279,29 @@ hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id) return hDeviceVM; } +int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversion) +{ + int ret; + DWORD dSize = 0; + + if (hax_invalid_fd(vm_fd)) + return -EINVAL; + + ret = DeviceIoControl(vm_fd, + HAX_VM_IOCTL_NOTIFY_QEMU_VERSION, + qversion, sizeof(struct hax_qemu_version), + NULL, 0, + &dSize, + (LPOVERLAPPED) NULL); + if (!ret) + { + dprint("Failed to notify qemu API version\n"); + return -1; + } + + return 0; +} + int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid) { int ret; diff --git a/target-i386/hax-windows.h b/target-i386/hax-windows.h index b6d60b7..d0c821d 100644 --- a/target-i386/hax-windows.h +++ b/target-i386/hax-windows.h @@ -45,6 +45,7 @@ static inline int hax_invalid_fd(hax_fd fd) /* See comments for the ioctl in hax-darwin.h */ #define HAX_IOCTL_VERSION CTL_CODE(HAX_DEVICE_TYPE, 0x900, METHOD_BUFFERED, FILE_ANY_ACCESS) #define HAX_IOCTL_CREATE_VM CTL_CODE(HAX_DEVICE_TYPE, 0x901, METHOD_BUFFERED, FILE_ANY_ACCESS) +#define HAX_IOCTL_CAPABILITY CTL_CODE(HAX_DEVICE_TYPE, 0x910, METHOD_BUFFERED, FILE_ANY_ACCESS) #define HAX_VM_IOCTL_VCPU_CREATE CTL_CODE(HAX_DEVICE_TYPE, 0x902, METHOD_BUFFERED, FILE_ANY_ACCESS) #define HAX_VM_IOCTL_ALLOC_RAM CTL_CODE(HAX_DEVICE_TYPE, 0x903, METHOD_BUFFERED, FILE_ANY_ACCESS) @@ -62,4 +63,6 @@ static inline int hax_invalid_fd(hax_fd fd) #define HAX_VCPU_SET_REGS CTL_CODE(HAX_DEVICE_TYPE, 0x90d, METHOD_BUFFERED, FILE_ANY_ACCESS) #define HAX_VCPU_GET_REGS CTL_CODE(HAX_DEVICE_TYPE, 0x90e, METHOD_BUFFERED, FILE_ANY_ACCESS) +#define HAX_VM_IOCTL_NOTIFY_QEMU_VERSION CTL_CODE(HAX_DEVICE_TYPE, 0x910, METHOD_BUFFERED, FILE_ANY_ACCESS) + #endif diff --git a/target-mips/TODO b/target-mips/TODO new file mode 100644 index 0000000..4769e2a --- /dev/null +++ b/target-mips/TODO @@ -0,0 +1,53 @@ +Unsolved issues/bugs in the mips/mipsel backend +----------------------------------------------- + +General +------- +- Unimplemented ASEs: + - MIPS16 + - MDMX + - SmartMIPS + - DSP r1 + - DSP r2 +- MT ASE only partially implemented and not functional +- Shadow register support only partially implemented, + lacks set switching on interrupt/exception. +- 34K ITC not implemented. +- A general lack of documentation, especially for technical internals. + Existing documentation is x86-centric. +- Reverse endianness bit not implemented +- The TLB emulation is very inefficient: + Qemu's softmmu implements a x86-style MMU, with separate entries + for read/write/execute, a TLB index which is just a modulo of the + virtual address, and a set of TLBs for each user/kernel/supervisor + MMU mode. + MIPS has a single entry for read/write/execute and only one MMU mode. + But it is fully associative with randomized entry indices, and uses + up to 256 ASID tags as additional matching criterion (which roughly + equates to 256 MMU modes). It also has a global flag which causes + entries to match regardless of ASID. + To cope with these differences, Qemu currently flushes the TLB at + each ASID change. Using the MMU modes to implement ASIDs hinges on + implementing the global bit efficiently. +- save/restore of the CPU state is not implemented (see machine.c). + +MIPS64 +------ +- Userland emulation (both n32 and n64) not functional. + +"Generic" 4Kc system emulation +------------------------------ +- Doesn't correspond to any real hardware. Should be removed some day, + U-Boot is the last remaining user. + +PICA 61 system emulation +------------------------ +- No framebuffer support yet. + +MALTA system emulation +---------------------- +- We fake firmware support instead of doing the real thing +- Real firmware (YAMON) falls over when trying to init RAM, presumably + due to lacking system controller emulation. +- Bonito system controller not implemented +- MSC1 system controller not implemented diff --git a/target-mips/cpu.h b/target-mips/cpu.h new file mode 100644 index 0000000..27bdc95 --- /dev/null +++ b/target-mips/cpu.h @@ -0,0 +1,626 @@ +#if !defined (__MIPS_CPU_H__) +#define __MIPS_CPU_H__ + +#define TARGET_HAS_ICE 1 + +#define ELF_MACHINE EM_MIPS + +#define CPUState struct CPUMIPSState + +#include "config.h" +#include "mips-defs.h" +#include "cpu-defs.h" +#include "softfloat.h" + +// uint_fast8_t and uint_fast16_t not in <sys/int_types.h> +// XXX: move that elsewhere +#if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 +typedef unsigned char uint_fast8_t; +typedef unsigned int uint_fast16_t; +#endif + +struct CPUMIPSState; + +typedef struct r4k_tlb_t r4k_tlb_t; +struct r4k_tlb_t { + target_ulong VPN; + uint32_t PageMask; + uint_fast8_t ASID; + uint_fast16_t G:1; + uint_fast16_t C0:3; + uint_fast16_t C1:3; + uint_fast16_t V0:1; + uint_fast16_t V1:1; + uint_fast16_t D0:1; + uint_fast16_t D1:1; + target_ulong PFN[2]; +}; + +typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; +struct CPUMIPSTLBContext { + uint32_t nb_tlb; + uint32_t tlb_in_use; + int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type); + void (*helper_tlbwi) (void); + void (*helper_tlbwr) (void); + void (*helper_tlbp) (void); + void (*helper_tlbr) (void); + union { + struct { + r4k_tlb_t tlb[MIPS_TLB_MAX]; + } r4k; + } mmu; +}; + +typedef union fpr_t fpr_t; +union fpr_t { + float64 fd; /* ieee double precision */ + float32 fs[2];/* ieee single precision */ + uint64_t d; /* binary double fixed-point */ + uint32_t w[2]; /* binary single fixed-point */ +}; +/* define FP_ENDIAN_IDX to access the same location + * in the fpr_t union regardless of the host endianess + */ +#if defined(HOST_WORDS_BIGENDIAN) +# define FP_ENDIAN_IDX 1 +#else +# define FP_ENDIAN_IDX 0 +#endif + +typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; +struct CPUMIPSFPUContext { + /* Floating point registers */ + fpr_t fpr[32]; + float_status fp_status; + /* fpu implementation/revision register (fir) */ + uint32_t fcr0; +#define FCR0_F64 22 +#define FCR0_L 21 +#define FCR0_W 20 +#define FCR0_3D 19 +#define FCR0_PS 18 +#define FCR0_D 17 +#define FCR0_S 16 +#define FCR0_PRID 8 +#define FCR0_REV 0 + /* fcsr */ + uint32_t fcr31; +#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) +#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) +#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) +#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) +#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) +#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) +#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) +#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) +#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) +#define FP_INEXACT 1 +#define FP_UNDERFLOW 2 +#define FP_OVERFLOW 4 +#define FP_DIV0 8 +#define FP_INVALID 16 +#define FP_UNIMPLEMENTED 32 +}; + +#define NB_MMU_MODES 3 + +typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; +struct CPUMIPSMVPContext { + int32_t CP0_MVPControl; +#define CP0MVPCo_CPA 3 +#define CP0MVPCo_STLB 2 +#define CP0MVPCo_VPC 1 +#define CP0MVPCo_EVP 0 + int32_t CP0_MVPConf0; +#define CP0MVPC0_M 31 +#define CP0MVPC0_TLBS 29 +#define CP0MVPC0_GS 28 +#define CP0MVPC0_PCP 27 +#define CP0MVPC0_PTLBE 16 +#define CP0MVPC0_TCA 15 +#define CP0MVPC0_PVPE 10 +#define CP0MVPC0_PTC 0 + int32_t CP0_MVPConf1; +#define CP0MVPC1_CIM 31 +#define CP0MVPC1_CIF 30 +#define CP0MVPC1_PCX 20 +#define CP0MVPC1_PCP2 10 +#define CP0MVPC1_PCP1 0 +}; + +typedef struct mips_def_t mips_def_t; + +#define MIPS_SHADOW_SET_MAX 16 +#define MIPS_TC_MAX 5 +#define MIPS_FPU_MAX 1 +#define MIPS_DSP_ACC 4 + +typedef struct TCState TCState; +struct TCState { + target_ulong gpr[32]; + target_ulong PC; + target_ulong HI[MIPS_DSP_ACC]; + target_ulong LO[MIPS_DSP_ACC]; + target_ulong ACX[MIPS_DSP_ACC]; + target_ulong DSPControl; + int32_t CP0_TCStatus; +#define CP0TCSt_TCU3 31 +#define CP0TCSt_TCU2 30 +#define CP0TCSt_TCU1 29 +#define CP0TCSt_TCU0 28 +#define CP0TCSt_TMX 27 +#define CP0TCSt_RNST 23 +#define CP0TCSt_TDS 21 +#define CP0TCSt_DT 20 +#define CP0TCSt_DA 15 +#define CP0TCSt_A 13 +#define CP0TCSt_TKSU 11 +#define CP0TCSt_IXMT 10 +#define CP0TCSt_TASID 0 + int32_t CP0_TCBind; +#define CP0TCBd_CurTC 21 +#define CP0TCBd_TBE 17 +#define CP0TCBd_CurVPE 0 + target_ulong CP0_TCHalt; + target_ulong CP0_TCContext; + target_ulong CP0_TCSchedule; + target_ulong CP0_TCScheFBack; + int32_t CP0_Debug_tcstatus; +}; + +typedef struct CPUMIPSState CPUMIPSState; +struct CPUMIPSState { + TCState active_tc; + CPUMIPSFPUContext active_fpu; + + uint32_t current_tc; + uint32_t current_fpu; + + uint32_t SEGBITS; + uint32_t PABITS; + target_ulong SEGMask; + target_ulong PAMask; + + int32_t CP0_Index; + /* CP0_MVP* are per MVP registers. */ + int32_t CP0_Random; + int32_t CP0_VPEControl; +#define CP0VPECo_YSI 21 +#define CP0VPECo_GSI 20 +#define CP0VPECo_EXCPT 16 +#define CP0VPECo_TE 15 +#define CP0VPECo_TargTC 0 + int32_t CP0_VPEConf0; +#define CP0VPEC0_M 31 +#define CP0VPEC0_XTC 21 +#define CP0VPEC0_TCS 19 +#define CP0VPEC0_SCS 18 +#define CP0VPEC0_DSC 17 +#define CP0VPEC0_ICS 16 +#define CP0VPEC0_MVP 1 +#define CP0VPEC0_VPA 0 + int32_t CP0_VPEConf1; +#define CP0VPEC1_NCX 20 +#define CP0VPEC1_NCP2 10 +#define CP0VPEC1_NCP1 0 + target_ulong CP0_YQMask; + target_ulong CP0_VPESchedule; + target_ulong CP0_VPEScheFBack; + int32_t CP0_VPEOpt; +#define CP0VPEOpt_IWX7 15 +#define CP0VPEOpt_IWX6 14 +#define CP0VPEOpt_IWX5 13 +#define CP0VPEOpt_IWX4 12 +#define CP0VPEOpt_IWX3 11 +#define CP0VPEOpt_IWX2 10 +#define CP0VPEOpt_IWX1 9 +#define CP0VPEOpt_IWX0 8 +#define CP0VPEOpt_DWX7 7 +#define CP0VPEOpt_DWX6 6 +#define CP0VPEOpt_DWX5 5 +#define CP0VPEOpt_DWX4 4 +#define CP0VPEOpt_DWX3 3 +#define CP0VPEOpt_DWX2 2 +#define CP0VPEOpt_DWX1 1 +#define CP0VPEOpt_DWX0 0 + target_ulong CP0_EntryLo0; + target_ulong CP0_EntryLo1; + target_ulong CP0_Context; + int32_t CP0_PageMask; + int32_t CP0_PageGrain; + int32_t CP0_Wired; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; +#define CP0SRSC0_M 31 +#define CP0SRSC0_SRS3 20 +#define CP0SRSC0_SRS2 10 +#define CP0SRSC0_SRS1 0 + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; +#define CP0SRSC1_M 31 +#define CP0SRSC1_SRS6 20 +#define CP0SRSC1_SRS5 10 +#define CP0SRSC1_SRS4 0 + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; +#define CP0SRSC2_M 31 +#define CP0SRSC2_SRS9 20 +#define CP0SRSC2_SRS8 10 +#define CP0SRSC2_SRS7 0 + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; +#define CP0SRSC3_M 31 +#define CP0SRSC3_SRS12 20 +#define CP0SRSC3_SRS11 10 +#define CP0SRSC3_SRS10 0 + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; +#define CP0SRSC4_SRS15 20 +#define CP0SRSC4_SRS14 10 +#define CP0SRSC4_SRS13 0 + int32_t CP0_HWREna; + target_ulong CP0_BadVAddr; + int32_t CP0_Count; + target_ulong CP0_EntryHi; + int32_t CP0_Compare; + int32_t CP0_Status; +#define CP0St_CU3 31 +#define CP0St_CU2 30 +#define CP0St_CU1 29 +#define CP0St_CU0 28 +#define CP0St_RP 27 +#define CP0St_FR 26 +#define CP0St_RE 25 +#define CP0St_MX 24 +#define CP0St_PX 23 +#define CP0St_BEV 22 +#define CP0St_TS 21 +#define CP0St_SR 20 +#define CP0St_NMI 19 +#define CP0St_IM 8 +#define CP0St_KX 7 +#define CP0St_SX 6 +#define CP0St_UX 5 +#define CP0St_KSU 3 +#define CP0St_ERL 2 +#define CP0St_EXL 1 +#define CP0St_IE 0 + int32_t CP0_IntCtl; +#define CP0IntCtl_IPTI 29 +#define CP0IntCtl_IPPC1 26 +#define CP0IntCtl_VS 5 + int32_t CP0_SRSCtl; +#define CP0SRSCtl_HSS 26 +#define CP0SRSCtl_EICSS 18 +#define CP0SRSCtl_ESS 12 +#define CP0SRSCtl_PSS 6 +#define CP0SRSCtl_CSS 0 + int32_t CP0_SRSMap; +#define CP0SRSMap_SSV7 28 +#define CP0SRSMap_SSV6 24 +#define CP0SRSMap_SSV5 20 +#define CP0SRSMap_SSV4 16 +#define CP0SRSMap_SSV3 12 +#define CP0SRSMap_SSV2 8 +#define CP0SRSMap_SSV1 4 +#define CP0SRSMap_SSV0 0 + int32_t CP0_Cause; +#define CP0Ca_BD 31 +#define CP0Ca_TI 30 +#define CP0Ca_CE 28 +#define CP0Ca_DC 27 +#define CP0Ca_PCI 26 +#define CP0Ca_IV 23 +#define CP0Ca_WP 22 +#define CP0Ca_IP 8 +#define CP0Ca_IP_mask 0x0000FF00 +#define CP0Ca_EC 2 + target_ulong CP0_EPC; + int32_t CP0_PRid; + int32_t CP0_EBase; + int32_t CP0_Config0; +#define CP0C0_M 31 +#define CP0C0_K23 28 +#define CP0C0_KU 25 +#define CP0C0_MDU 20 +#define CP0C0_MM 17 +#define CP0C0_BM 16 +#define CP0C0_BE 15 +#define CP0C0_AT 13 +#define CP0C0_AR 10 +#define CP0C0_MT 7 +#define CP0C0_VI 3 +#define CP0C0_K0 0 + int32_t CP0_Config1; +#define CP0C1_M 31 +#define CP0C1_MMU 25 +#define CP0C1_IS 22 +#define CP0C1_IL 19 +#define CP0C1_IA 16 +#define CP0C1_DS 13 +#define CP0C1_DL 10 +#define CP0C1_DA 7 +#define CP0C1_C2 6 +#define CP0C1_MD 5 +#define CP0C1_PC 4 +#define CP0C1_WR 3 +#define CP0C1_CA 2 +#define CP0C1_EP 1 +#define CP0C1_FP 0 + int32_t CP0_Config2; +#define CP0C2_M 31 +#define CP0C2_TU 28 +#define CP0C2_TS 24 +#define CP0C2_TL 20 +#define CP0C2_TA 16 +#define CP0C2_SU 12 +#define CP0C2_SS 8 +#define CP0C2_SL 4 +#define CP0C2_SA 0 + int32_t CP0_Config3; +#define CP0C3_M 31 +#define CP0C3_DSPP 10 +#define CP0C3_LPA 7 +#define CP0C3_VEIC 6 +#define CP0C3_VInt 5 +#define CP0C3_SP 4 +#define CP0C3_MT 2 +#define CP0C3_SM 1 +#define CP0C3_TL 0 + int32_t CP0_Config6; + int32_t CP0_Config7; + /* XXX: Maybe make LLAddr per-TC? */ + target_ulong lladdr; + target_ulong llval; + target_ulong llnewval; + target_ulong llreg; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + target_ulong CP0_WatchLo[8]; + int32_t CP0_WatchHi[8]; + target_ulong CP0_XContext; + int32_t CP0_Framemask; + int32_t CP0_Debug; +#define CP0DB_DBD 31 +#define CP0DB_DM 30 +#define CP0DB_LSNM 28 +#define CP0DB_Doze 27 +#define CP0DB_Halt 26 +#define CP0DB_CNT 25 +#define CP0DB_IBEP 24 +#define CP0DB_DBEP 21 +#define CP0DB_IEXI 20 +#define CP0DB_VER 15 +#define CP0DB_DEC 10 +#define CP0DB_SSt 8 +#define CP0DB_DINT 5 +#define CP0DB_DIB 4 +#define CP0DB_DDBS 3 +#define CP0DB_DDBL 2 +#define CP0DB_DBp 1 +#define CP0DB_DSS 0 + target_ulong CP0_DEPC; + int32_t CP0_Performance0; + int32_t CP0_TagLo; + int32_t CP0_DataLo; + int32_t CP0_TagHi; + int32_t CP0_DataHi; + target_ulong CP0_ErrorEPC; + int32_t CP0_DESAVE; + /* We waste some space so we can handle shadow registers like TCs. */ + TCState tcs[MIPS_SHADOW_SET_MAX]; + CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; + /* Qemu */ + int error_code; + uint32_t hflags; /* CPU State */ + /* TMASK defines different execution modes */ +#define MIPS_HFLAG_TMASK 0x03FF +#define MIPS_HFLAG_MODE 0x0007 /* execution modes */ + /* The KSU flags must be the lowest bits in hflags. The flag order + must be the same as defined for CP0 Status. This allows to use + the bits as the value of mmu_idx. */ +#define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */ +#define MIPS_HFLAG_UM 0x0002 /* user mode flag */ +#define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */ +#define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */ +#define MIPS_HFLAG_DM 0x0004 /* Debug mode */ +#define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */ +#define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */ +#define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */ +#define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */ + /* True if the MIPS IV COP1X instructions can be used. This also + controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + and RSQRT.D. */ +#define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ +#define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ +#define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ + /* If translation is interrupted between the branch instruction and + * the delay slot, record what type of branch it is so that we can + * resume translation properly. It might be possible to reduce + * this from three bits to two. */ +#define MIPS_HFLAG_BMASK 0x1C00 +#define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ +#define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ +#define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ +#define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ + target_ulong btarget; /* Jump / branch target */ + target_ulong bcond; /* Branch condition (if needed) */ + + int SYNCI_Step; /* Address step size for SYNCI */ + int CCRes; /* Cycle count resolution/divisor */ + uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ + uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ + int insn_flags; /* Supported instruction set */ + + target_ulong tls_value; /* For usermode emulation */ + + CPU_COMMON + + CPUMIPSMVPContext *mvp; + CPUMIPSTLBContext *tlb; + + const mips_def_t *cpu_model; + void *irq[8]; + struct QEMUTimer *timer; /* Internal timer */ +}; + +int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type); +int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type); +int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type); +void r4k_helper_tlbwi (void); +void r4k_helper_tlbwr (void); +void r4k_helper_tlbp (void); +void r4k_helper_tlbr (void); +void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); + +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, + int unused, int size); + +#define cpu_init cpu_mips_init +#define cpu_exec cpu_mips_exec +#define cpu_gen_code cpu_mips_gen_code +#define cpu_signal_handler cpu_mips_signal_handler +#define cpu_list mips_cpu_list + +#define CPU_SAVE_VERSION 3 + +/* MMU modes definitions. We carefully match the indices with our + hflags layout. */ +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _super +#define MMU_MODE2_SUFFIX _user +#define MMU_USER_IDX 2 +static inline int cpu_mmu_index (CPUState *env) +{ + return env->hflags & MIPS_HFLAG_KSU; +} + +static inline int is_cpu_user (CPUState *env) +{ +#ifdef CONFIG_USER_ONLY + return 1; +#else + return ((env->CP0_Status & + ((3 << CP0St_KSU) | (1 << CP0St_ERL) | (1 << CP0St_EXL))) == (3 << CP0St_KSU)); +#endif // CONFIG_USER_ONLY +} + +static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +{ + if (newsp) + env->active_tc.gpr[29] = newsp; + env->active_tc.gpr[7] = 0; + env->active_tc.gpr[2] = 0; +} + +#include "cpu-all.h" +#include "exec-all.h" + +/* Memory access type : + * may be needed for precise access rights control and precise exceptions. + */ +enum { + /* 1 bit to define user level / supervisor access */ + ACCESS_USER = 0x00, + ACCESS_SUPER = 0x01, + /* 1 bit to indicate direction */ + ACCESS_STORE = 0x02, + /* Type of instruction that generated the access */ + ACCESS_CODE = 0x10, /* Code fetch access */ + ACCESS_INT = 0x20, /* Integer load/store access */ + ACCESS_FLOAT = 0x30, /* floating point load/store access */ +}; + +/* Exceptions */ +enum { + EXCP_NONE = -1, + EXCP_RESET = 0, + EXCP_SRESET, + EXCP_DSS, + EXCP_DINT, + EXCP_DDBL, + EXCP_DDBS, + EXCP_NMI, + EXCP_MCHECK, + EXCP_EXT_INTERRUPT, /* 8 */ + EXCP_DFWATCH, + EXCP_DIB, + EXCP_IWATCH, + EXCP_AdEL, + EXCP_AdES, + EXCP_TLBF, + EXCP_IBE, + EXCP_DBp, /* 16 */ + EXCP_SYSCALL, + EXCP_BREAK, + EXCP_CpU, + EXCP_RI, + EXCP_OVERFLOW, + EXCP_TRAP, + EXCP_FPE, + EXCP_DWATCH, /* 24 */ + EXCP_LTLBL, + EXCP_TLBL, + EXCP_TLBS, + EXCP_DBE, + EXCP_THREAD, + EXCP_MDMX, + EXCP_C2E, + EXCP_CACHE, /* 32 */ + + EXCP_LAST = EXCP_CACHE, +}; +/* Dummy exception for conditional stores. */ +#define EXCP_SC 0x100 + +int cpu_mips_exec(CPUMIPSState *s); +CPUMIPSState *cpu_mips_init(const char *cpu_model); +//~ uint32_t cpu_mips_get_clock (void); +int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); + +/* mips_timer.c */ +uint32_t cpu_mips_get_random (CPUState *env); +uint32_t cpu_mips_get_count (CPUState *env); +void cpu_mips_store_count (CPUState *env, uint32_t value); +void cpu_mips_store_compare (CPUState *env, uint32_t value); +void cpu_mips_start_count(CPUState *env); +void cpu_mips_stop_count(CPUState *env); + +/* mips_int.c */ +void cpu_mips_update_irq (CPUState *env); + +/* helper.c */ +int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, + int mmu_idx, int is_softmmu); +#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault +void do_interrupt (CPUState *env); +void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); +target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address, + int rw); + +static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +{ + env->active_tc.PC = tb->pc; + env->hflags &= ~MIPS_HFLAG_BMASK; + env->hflags |= tb->flags & MIPS_HFLAG_BMASK; +} + +static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, + target_ulong *cs_base, int *flags) +{ + *pc = env->active_tc.PC; + *cs_base = 0; + *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); +} + +static inline void cpu_set_tls(CPUState *env, target_ulong newtls) +{ + env->tls_value = newtls; +} + +#endif /* !defined (__MIPS_CPU_H__) */ diff --git a/target-mips/exec.h b/target-mips/exec.h new file mode 100644 index 0000000..8a118bb --- /dev/null +++ b/target-mips/exec.h @@ -0,0 +1,95 @@ +#if !defined(__QEMU_MIPS_EXEC_H__) +#define __QEMU_MIPS_EXEC_H__ + +//#define DEBUG_OP + +#include "config.h" +#include "mips-defs.h" +#include "dyngen-exec.h" +#include "cpu-defs.h" + +register struct CPUMIPSState *env asm(AREG0); + +#include "cpu.h" +#include "exec-all.h" + +#if !defined(CONFIG_USER_ONLY) +#include "softmmu_exec.h" +#endif /* !defined(CONFIG_USER_ONLY) */ + +void dump_fpu(CPUState *env); +void fpu_dump_state(CPUState *env, FILE *f, + int (*fpu_fprintf)(FILE *f, const char *fmt, ...), + int flags); + +void cpu_mips_clock_init (CPUState *env); +void cpu_mips_tlb_flush (CPUState *env, int flush_global); + +static inline void env_to_regs(void) +{ +} + +static inline void regs_to_env(void) +{ +} + +static inline int cpu_has_work(CPUState *env) +{ + return (env->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)); +} + + +static inline int cpu_halted(CPUState *env) +{ + if (!env->halted) + return 0; + if (cpu_has_work(env)) { + env->halted = 0; + return 0; + } + return EXCP_HALTED; +} + +static inline void compute_hflags(CPUState *env) +{ + env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | + MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | + MIPS_HFLAG_UX); + if (!(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM)) { + env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; + } +#if defined(TARGET_MIPS64) + if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || + (env->CP0_Status & (1 << CP0St_PX)) || + (env->CP0_Status & (1 << CP0St_UX))) + env->hflags |= MIPS_HFLAG_64; + if (env->CP0_Status & (1 << CP0St_UX)) + env->hflags |= MIPS_HFLAG_UX; +#endif + if ((env->CP0_Status & (1 << CP0St_CU0)) || + !(env->hflags & MIPS_HFLAG_KSU)) + env->hflags |= MIPS_HFLAG_CP0; + if (env->CP0_Status & (1 << CP0St_CU1)) + env->hflags |= MIPS_HFLAG_FPU; + if (env->CP0_Status & (1 << CP0St_FR)) + env->hflags |= MIPS_HFLAG_F64; + if (env->insn_flags & ISA_MIPS32R2) { + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) + env->hflags |= MIPS_HFLAG_COP1X; + } else if (env->insn_flags & ISA_MIPS32) { + if (env->hflags & MIPS_HFLAG_64) + env->hflags |= MIPS_HFLAG_COP1X; + } else if (env->insn_flags & ISA_MIPS4) { + /* All supported MIPS IV CPUs use the XX (CU3) to enable + and disable the MIPS IV extensions to the MIPS III ISA. + Some other MIPS IV CPUs ignore the bit, so the check here + would be too restrictive for them. */ + if (env->CP0_Status & (1 << CP0St_CU3)) + env->hflags |= MIPS_HFLAG_COP1X; + } +} + +#endif /* !defined(__QEMU_MIPS_EXEC_H__) */ diff --git a/target-mips/helper.c b/target-mips/helper.c new file mode 100644 index 0000000..ec87114 --- /dev/null +++ b/target-mips/helper.c @@ -0,0 +1,647 @@ +/* + * MIPS emulation helpers for qemu. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include <stdarg.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <inttypes.h> +#include <signal.h> + +#include "cpu.h" +#include "exec-all.h" + +enum { + TLBRET_DIRTY = -4, + TLBRET_INVALID = -3, + TLBRET_NOMATCH = -2, + TLBRET_BADADDR = -1, + TLBRET_MATCH = 0 +}; + +/* no MMU emulation */ +int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type) +{ + *physical = address; + *prot = PAGE_READ | PAGE_WRITE; + return TLBRET_MATCH; +} + +/* fixed mapping MMU emulation */ +int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type) +{ + if (address <= (int32_t)0x7FFFFFFFUL) { + if (!(env->CP0_Status & (1 << CP0St_ERL))) + *physical = address + 0x40000000UL; + else + *physical = address; + } else if (address <= (int32_t)0xBFFFFFFFUL) + *physical = address & 0x1FFFFFFF; + else + *physical = address; + + *prot = PAGE_READ | PAGE_WRITE; + return TLBRET_MATCH; +} + +/* MIPS32/MIPS64 R4000-style MMU emulation */ +int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, + target_ulong address, int rw, int access_type) +{ + uint8_t ASID = env->CP0_EntryHi & 0xFF; + int i; + + for (i = 0; i < env->tlb->tlb_in_use; i++) { + r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + target_ulong tag = address & ~mask; + target_ulong VPN = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &= env->SEGMask; +#endif + + /* Check ASID, virtual page number & size */ + if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { + /* TLB match */ + int n = !!(address & mask & ~(mask >> 1)); + /* Check access rights */ + if (!(n ? tlb->V1 : tlb->V0)) + return TLBRET_INVALID; + if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { + *physical = tlb->PFN[n] | (address & (mask >> 1)); + *prot = PAGE_READ; + if (n ? tlb->D1 : tlb->D0) + *prot |= PAGE_WRITE; + return TLBRET_MATCH; + } + return TLBRET_DIRTY; + } + } + return TLBRET_NOMATCH; +} + +#if !defined(CONFIG_USER_ONLY) +static int get_physical_address (CPUState *env, target_phys_addr_t *physical, + int *prot, target_ulong address, + int rw, int access_type) +{ + /* User mode can only access useg/xuseg */ + int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; + int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; + int kernel_mode = !user_mode && !supervisor_mode; +#if defined(TARGET_MIPS64) + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; +#endif + int ret = TLBRET_MATCH; + +#if 0 + qemu_log("user mode %d h %08x\n", user_mode, env->hflags); +#endif + + if (address <= (int32_t)0x7FFFFFFFUL) { + /* useg */ + if (env->CP0_Status & (1 << CP0St_ERL)) { + *physical = address & 0xFFFFFFFF; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } +#if defined(TARGET_MIPS64) + } else if (address < 0x4000000000000000ULL) { + /* xuseg */ + if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0x8000000000000000ULL) { + /* xsseg */ + if ((supervisor_mode || kernel_mode) && + SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0xC000000000000000ULL) { + /* xkphys */ + if (kernel_mode && KX && + (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { + *physical = address & env->PAMask; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0xFFFFFFFF80000000ULL) { + /* xkseg */ + if (kernel_mode && KX && + address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } +#endif + } else if (address < (int32_t)0xA0000000UL) { + /* kseg0 */ + if (kernel_mode) { + *physical = address - (int32_t)0x80000000UL; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = TLBRET_BADADDR; + } + } else if (address < (int32_t)0xC0000000UL) { + /* kseg1 */ + if (kernel_mode) { + *physical = address - (int32_t)0xA0000000UL; + *prot = PAGE_READ | PAGE_WRITE; + } else { + ret = TLBRET_BADADDR; + } + } else if (address < (int32_t)0xE0000000UL) { + /* sseg (kseg2) */ + if (supervisor_mode || kernel_mode) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else { + /* kseg3 */ + /* XXX: debug segment is not emulated */ + if (kernel_mode) { + ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + } else { + ret = TLBRET_BADADDR; + } + } +#if 0 + qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", + address, rw, access_type, *physical, *prot, ret); +#endif + + return ret; +} +#endif + +static void raise_mmu_exception(CPUState *env, target_ulong address, + int rw, int tlb_error) +{ + int exception = 0, error_code = 0; + + switch (tlb_error) { + default: + case TLBRET_BADADDR: + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (rw) + exception = EXCP_AdES; + else + exception = EXCP_AdEL; + break; + case TLBRET_NOMATCH: + /* No TLB match for a mapped address */ + if (rw) + exception = EXCP_TLBS; + else + exception = EXCP_TLBL; + error_code = 1; + break; + case TLBRET_INVALID: + /* TLB match with no valid bit */ + if (rw) + exception = EXCP_TLBS; + else + exception = EXCP_TLBL; + break; + case TLBRET_DIRTY: + /* TLB match but 'D' bit is cleared */ + exception = EXCP_LTLBL; + break; + + } + /* Raise exception */ + env->CP0_BadVAddr = address; + env->CP0_Context = (env->CP0_Context & ~0x007fffff) | + ((address >> 9) & 0x007ffff0); + env->CP0_EntryHi = + (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); +#if defined(TARGET_MIPS64) + env->CP0_EntryHi &= env->SEGMask; + env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | + ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | + ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); +#endif + env->exception_index = exception; + env->error_code = error_code; +} + +target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) +{ +#if defined(CONFIG_USER_ONLY) + return addr; +#else + target_phys_addr_t phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) + return -1; + return phys_addr; +#endif +} + +int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, + int mmu_idx, int is_softmmu) +{ +#if !defined(CONFIG_USER_ONLY) + target_phys_addr_t physical; + int prot; +#endif + int access_type; + int ret = 0; + +#if 0 + log_cpu_state(env, 0); +#endif + qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", + __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu); + + rw &= 1; + + /* data access */ + /* XXX: put correct access by using cpu_restore_state() + correctly */ + access_type = ACCESS_INT; +#if defined(CONFIG_USER_ONLY) + ret = TLBRET_NOMATCH; +#else + ret = get_physical_address(env, &physical, &prot, + address, rw, access_type); + qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", + __func__, address, ret, physical, prot); + if (ret == TLBRET_MATCH) { + ret = tlb_set_page(env, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot, + mmu_idx, is_softmmu); + } else if (ret < 0) +#endif + { + raise_mmu_exception(env, address, rw, ret); + ret = 1; + } + + return ret; +} + +#if !defined(CONFIG_USER_ONLY) +target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw) +{ + target_phys_addr_t physical; + int prot; + int access_type; + int ret = 0; + + rw &= 1; + + /* data access */ + access_type = ACCESS_INT; + ret = get_physical_address(env, &physical, &prot, + address, rw, access_type); + if (ret != TLBRET_MATCH) { + raise_mmu_exception(env, address, rw, ret); + return -1LL; + } else { + return physical; + } +} +#endif + +static const char * const excp_names[EXCP_LAST + 1] = { + [EXCP_RESET] = "reset", + [EXCP_SRESET] = "soft reset", + [EXCP_DSS] = "debug single step", + [EXCP_DINT] = "debug interrupt", + [EXCP_NMI] = "non-maskable interrupt", + [EXCP_MCHECK] = "machine check", + [EXCP_EXT_INTERRUPT] = "interrupt", + [EXCP_DFWATCH] = "deferred watchpoint", + [EXCP_DIB] = "debug instruction breakpoint", + [EXCP_IWATCH] = "instruction fetch watchpoint", + [EXCP_AdEL] = "address error load", + [EXCP_AdES] = "address error store", + [EXCP_TLBF] = "TLB refill", + [EXCP_IBE] = "instruction bus error", + [EXCP_DBp] = "debug breakpoint", + [EXCP_SYSCALL] = "syscall", + [EXCP_BREAK] = "break", + [EXCP_CpU] = "coprocessor unusable", + [EXCP_RI] = "reserved instruction", + [EXCP_OVERFLOW] = "arithmetic overflow", + [EXCP_TRAP] = "trap", + [EXCP_FPE] = "floating point", + [EXCP_DDBS] = "debug data break store", + [EXCP_DWATCH] = "data watchpoint", + [EXCP_LTLBL] = "TLB modify", + [EXCP_TLBL] = "TLB load", + [EXCP_TLBS] = "TLB store", + [EXCP_DBE] = "data bus error", + [EXCP_DDBL] = "debug data break load", + [EXCP_THREAD] = "thread", + [EXCP_MDMX] = "MDMX", + [EXCP_C2E] = "precise coprocessor 2", + [EXCP_CACHE] = "cache error", +}; + +void do_interrupt (CPUState *env) +{ +#if !defined(CONFIG_USER_ONLY) + target_ulong offset; + int cause = -1; + const char *name; + + if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { + if (env->exception_index < 0 || env->exception_index > EXCP_LAST) + name = "unknown"; + else + name = excp_names[env->exception_index]; + + qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", + __func__, env->active_tc.PC, env->CP0_EPC, name); + } + if (env->exception_index == EXCP_EXT_INTERRUPT && + (env->hflags & MIPS_HFLAG_DM)) + env->exception_index = EXCP_DINT; + offset = 0x180; + switch (env->exception_index) { + case EXCP_DSS: + env->CP0_Debug |= 1 << CP0DB_DSS; + /* Debug single step cannot be raised inside a delay slot and + resume will always occur on the next instruction + (but we assume the pc has always been updated during + code translation). */ + env->CP0_DEPC = env->active_tc.PC; + goto enter_debug_mode; + case EXCP_DINT: + env->CP0_Debug |= 1 << CP0DB_DINT; + goto set_DEPC; + case EXCP_DIB: + env->CP0_Debug |= 1 << CP0DB_DIB; + goto set_DEPC; + case EXCP_DBp: + env->CP0_Debug |= 1 << CP0DB_DBp; + goto set_DEPC; + case EXCP_DDBS: + env->CP0_Debug |= 1 << CP0DB_DDBS; + goto set_DEPC; + case EXCP_DDBL: + env->CP0_Debug |= 1 << CP0DB_DDBL; + set_DEPC: + if (env->hflags & MIPS_HFLAG_BMASK) { + /* If the exception was raised from a delay slot, + come back to the jump. */ + env->CP0_DEPC = env->active_tc.PC - 4; + env->hflags &= ~MIPS_HFLAG_BMASK; + } else { + env->CP0_DEPC = env->active_tc.PC; + } + enter_debug_mode: + env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + env->hflags &= ~(MIPS_HFLAG_KSU); + /* EJTAG probe trap enable is not implemented... */ + if (!(env->CP0_Status & (1 << CP0St_EXL))) + env->CP0_Cause &= ~(1 << CP0Ca_BD); + env->active_tc.PC = (int32_t)0xBFC00480; + break; + case EXCP_RESET: + cpu_reset(env); + break; + case EXCP_SRESET: + env->CP0_Status |= (1 << CP0St_SR); + memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); + goto set_error_EPC; + case EXCP_NMI: + env->CP0_Status |= (1 << CP0St_NMI); + set_error_EPC: + if (env->hflags & MIPS_HFLAG_BMASK) { + /* If the exception was raised from a delay slot, + come back to the jump. */ + env->CP0_ErrorEPC = env->active_tc.PC - 4; + env->hflags &= ~MIPS_HFLAG_BMASK; + } else { + env->CP0_ErrorEPC = env->active_tc.PC; + } + env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); + env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + env->hflags &= ~(MIPS_HFLAG_KSU); + if (!(env->CP0_Status & (1 << CP0St_EXL))) + env->CP0_Cause &= ~(1 << CP0Ca_BD); + env->active_tc.PC = (int32_t)0xBFC00000; + break; + case EXCP_EXT_INTERRUPT: + cause = 0; + if (env->CP0_Cause & (1 << CP0Ca_IV)) + offset = 0x200; + goto set_EPC; + case EXCP_LTLBL: + cause = 1; + goto set_EPC; + case EXCP_TLBL: + cause = 2; + if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { +#if defined(TARGET_MIPS64) + int R = env->CP0_BadVAddr >> 62; + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; + + if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) + offset = 0x080; + else +#endif + offset = 0x000; + } + goto set_EPC; + case EXCP_TLBS: + cause = 3; + if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { +#if defined(TARGET_MIPS64) + int R = env->CP0_BadVAddr >> 62; + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; + + if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) + offset = 0x080; + else +#endif + offset = 0x000; + } + goto set_EPC; + case EXCP_AdEL: + cause = 4; + goto set_EPC; + case EXCP_AdES: + cause = 5; + goto set_EPC; + case EXCP_IBE: + cause = 6; + goto set_EPC; + case EXCP_DBE: + cause = 7; + goto set_EPC; + case EXCP_SYSCALL: + cause = 8; + goto set_EPC; + case EXCP_BREAK: + cause = 9; + goto set_EPC; + case EXCP_RI: + cause = 10; + goto set_EPC; + case EXCP_CpU: + cause = 11; + env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | + (env->error_code << CP0Ca_CE); + goto set_EPC; + case EXCP_OVERFLOW: + cause = 12; + goto set_EPC; + case EXCP_TRAP: + cause = 13; + goto set_EPC; + case EXCP_FPE: + cause = 15; + goto set_EPC; + case EXCP_C2E: + cause = 18; + goto set_EPC; + case EXCP_MDMX: + cause = 22; + goto set_EPC; + case EXCP_DWATCH: + cause = 23; + /* XXX: TODO: manage defered watch exceptions */ + goto set_EPC; + case EXCP_MCHECK: + cause = 24; + goto set_EPC; + case EXCP_THREAD: + cause = 25; + goto set_EPC; + case EXCP_CACHE: + cause = 30; + if (env->CP0_Status & (1 << CP0St_BEV)) { + offset = 0x100; + } else { + offset = 0x20000100; + } + set_EPC: + if (!(env->CP0_Status & (1 << CP0St_EXL))) { + if (env->hflags & MIPS_HFLAG_BMASK) { + /* If the exception was raised from a delay slot, + come back to the jump. */ + env->CP0_EPC = env->active_tc.PC - 4; + env->CP0_Cause |= (1 << CP0Ca_BD); + } else { + env->CP0_EPC = env->active_tc.PC; + env->CP0_Cause &= ~(1 << CP0Ca_BD); + } + env->CP0_Status |= (1 << CP0St_EXL); + env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + env->hflags &= ~(MIPS_HFLAG_KSU); + } + env->hflags &= ~MIPS_HFLAG_BMASK; + if (env->CP0_Status & (1 << CP0St_BEV)) { + env->active_tc.PC = (int32_t)0xBFC00200; + } else { + env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); + } + env->active_tc.PC += offset; + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); + break; + default: + qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); + printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); + exit(1); + } + if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { + qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" + " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", + __func__, env->active_tc.PC, env->CP0_EPC, cause, + env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, + env->CP0_DEPC); + } +#endif + env->exception_index = EXCP_NONE; +} + +void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) +{ + r4k_tlb_t *tlb; + target_ulong addr; + target_ulong end; + uint8_t ASID = env->CP0_EntryHi & 0xFF; + target_ulong mask; + + tlb = &env->tlb->mmu.r4k.tlb[idx]; + /* The qemu TLB is flushed when the ASID changes, so no need to + flush these entries again. */ + if (tlb->G == 0 && tlb->ASID != ASID) { + return; + } + + if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { + /* For tlbwr, we can shadow the discarded entry into + a new (fake) TLB entry, as long as the guest can not + tell that it's there. */ + env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; + env->tlb->tlb_in_use++; + return; + } + + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + if (tlb->V0) { + addr = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { + addr |= 0x3FFFFF0000000000ULL; + } +#endif + end = addr | (mask >> 1); + while (addr < end) { + tlb_flush_page (env, addr); + addr += TARGET_PAGE_SIZE; + } + } + if (tlb->V1) { + addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); +#if defined(TARGET_MIPS64) + if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { + addr |= 0x3FFFFF0000000000ULL; + } +#endif + end = addr | mask; + while (addr - 1 < end) { + tlb_flush_page (env, addr); + addr += TARGET_PAGE_SIZE; + } + } +} diff --git a/target-mips/helper.h b/target-mips/helper.h new file mode 100644 index 0000000..ab47b1a --- /dev/null +++ b/target-mips/helper.h @@ -0,0 +1,282 @@ +#include "def-helper.h" + +DEF_HELPER_2(raise_exception_err, void, i32, int) +DEF_HELPER_1(raise_exception, void, i32) +DEF_HELPER_0(interrupt_restart, void) + +#ifdef TARGET_MIPS64 +DEF_HELPER_3(ldl, tl, tl, tl, int) +DEF_HELPER_3(ldr, tl, tl, tl, int) +DEF_HELPER_3(sdl, void, tl, tl, int) +DEF_HELPER_3(sdr, void, tl, tl, int) +#endif +DEF_HELPER_3(lwl, tl, tl, tl, int) +DEF_HELPER_3(lwr, tl, tl, tl, int) +DEF_HELPER_3(swl, void, tl, tl, int) +DEF_HELPER_3(swr, void, tl, tl, int) + +#ifndef CONFIG_USER_ONLY +DEF_HELPER_2(ll, tl, tl, int) +DEF_HELPER_3(sc, tl, tl, tl, int) +#ifdef TARGET_MIPS64 +DEF_HELPER_2(lld, tl, tl, int) +DEF_HELPER_3(scd, tl, tl, tl, int) +#endif +#endif + +DEF_HELPER_FLAGS_1(clo, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +DEF_HELPER_FLAGS_1(clz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +#ifdef TARGET_MIPS64 +DEF_HELPER_FLAGS_1(dclo, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +DEF_HELPER_FLAGS_1(dclz, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) +DEF_HELPER_2(dmult, void, tl, tl) +DEF_HELPER_2(dmultu, void, tl, tl) +#endif + +DEF_HELPER_2(muls, tl, tl, tl) +DEF_HELPER_2(mulsu, tl, tl, tl) +DEF_HELPER_2(macc, tl, tl, tl) +DEF_HELPER_2(maccu, tl, tl, tl) +DEF_HELPER_2(msac, tl, tl, tl) +DEF_HELPER_2(msacu, tl, tl, tl) +DEF_HELPER_2(mulhi, tl, tl, tl) +DEF_HELPER_2(mulhiu, tl, tl, tl) +DEF_HELPER_2(mulshi, tl, tl, tl) +DEF_HELPER_2(mulshiu, tl, tl, tl) +DEF_HELPER_2(macchi, tl, tl, tl) +DEF_HELPER_2(macchiu, tl, tl, tl) +DEF_HELPER_2(msachi, tl, tl, tl) +DEF_HELPER_2(msachiu, tl, tl, tl) + +#ifndef CONFIG_USER_ONLY +/* CP0 helpers */ +DEF_HELPER_0(mfc0_mvpcontrol, tl) +DEF_HELPER_0(mfc0_mvpconf0, tl) +DEF_HELPER_0(mfc0_mvpconf1, tl) +DEF_HELPER_0(mfc0_random, tl) +DEF_HELPER_0(mfc0_tcstatus, tl) +DEF_HELPER_0(mftc0_tcstatus, tl) +DEF_HELPER_0(mfc0_tcbind, tl) +DEF_HELPER_0(mftc0_tcbind, tl) +DEF_HELPER_0(mfc0_tcrestart, tl) +DEF_HELPER_0(mftc0_tcrestart, tl) +DEF_HELPER_0(mfc0_tchalt, tl) +DEF_HELPER_0(mftc0_tchalt, tl) +DEF_HELPER_0(mfc0_tccontext, tl) +DEF_HELPER_0(mftc0_tccontext, tl) +DEF_HELPER_0(mfc0_tcschedule, tl) +DEF_HELPER_0(mftc0_tcschedule, tl) +DEF_HELPER_0(mfc0_tcschefback, tl) +DEF_HELPER_0(mftc0_tcschefback, tl) +DEF_HELPER_0(mfc0_count, tl) +DEF_HELPER_0(mftc0_entryhi, tl) +DEF_HELPER_0(mftc0_status, tl) +DEF_HELPER_0(mfc0_lladdr, tl) +DEF_HELPER_1(mfc0_watchlo, tl, i32) +DEF_HELPER_1(mfc0_watchhi, tl, i32) +DEF_HELPER_0(mfc0_debug, tl) +DEF_HELPER_0(mftc0_debug, tl) +#ifdef TARGET_MIPS64 +DEF_HELPER_0(dmfc0_tcrestart, tl) +DEF_HELPER_0(dmfc0_tchalt, tl) +DEF_HELPER_0(dmfc0_tccontext, tl) +DEF_HELPER_0(dmfc0_tcschedule, tl) +DEF_HELPER_0(dmfc0_tcschefback, tl) +DEF_HELPER_0(dmfc0_lladdr, tl) +DEF_HELPER_1(dmfc0_watchlo, tl, i32) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER_1(mtc0_index, void, tl) +DEF_HELPER_1(mtc0_mvpcontrol, void, tl) +DEF_HELPER_1(mtc0_vpecontrol, void, tl) +DEF_HELPER_1(mtc0_vpeconf0, void, tl) +DEF_HELPER_1(mtc0_vpeconf1, void, tl) +DEF_HELPER_1(mtc0_yqmask, void, tl) +DEF_HELPER_1(mtc0_vpeopt, void, tl) +DEF_HELPER_1(mtc0_entrylo0, void, tl) +DEF_HELPER_1(mtc0_tcstatus, void, tl) +DEF_HELPER_1(mttc0_tcstatus, void, tl) +DEF_HELPER_1(mtc0_tcbind, void, tl) +DEF_HELPER_1(mttc0_tcbind, void, tl) +DEF_HELPER_1(mtc0_tcrestart, void, tl) +DEF_HELPER_1(mttc0_tcrestart, void, tl) +DEF_HELPER_1(mtc0_tchalt, void, tl) +DEF_HELPER_1(mttc0_tchalt, void, tl) +DEF_HELPER_1(mtc0_tccontext, void, tl) +DEF_HELPER_1(mttc0_tccontext, void, tl) +DEF_HELPER_1(mtc0_tcschedule, void, tl) +DEF_HELPER_1(mttc0_tcschedule, void, tl) +DEF_HELPER_1(mtc0_tcschefback, void, tl) +DEF_HELPER_1(mttc0_tcschefback, void, tl) +DEF_HELPER_1(mtc0_entrylo1, void, tl) +DEF_HELPER_1(mtc0_context, void, tl) +DEF_HELPER_1(mtc0_pagemask, void, tl) +DEF_HELPER_1(mtc0_pagegrain, void, tl) +DEF_HELPER_1(mtc0_wired, void, tl) +DEF_HELPER_1(mtc0_srsconf0, void, tl) +DEF_HELPER_1(mtc0_srsconf1, void, tl) +DEF_HELPER_1(mtc0_srsconf2, void, tl) +DEF_HELPER_1(mtc0_srsconf3, void, tl) +DEF_HELPER_1(mtc0_srsconf4, void, tl) +DEF_HELPER_1(mtc0_hwrena, void, tl) +DEF_HELPER_1(mtc0_count, void, tl) +DEF_HELPER_1(mtc0_entryhi, void, tl) +DEF_HELPER_1(mttc0_entryhi, void, tl) +DEF_HELPER_1(mtc0_compare, void, tl) +DEF_HELPER_1(mtc0_status, void, tl) +DEF_HELPER_1(mttc0_status, void, tl) +DEF_HELPER_1(mtc0_intctl, void, tl) +DEF_HELPER_1(mtc0_srsctl, void, tl) +DEF_HELPER_1(mtc0_cause, void, tl) +DEF_HELPER_1(mtc0_ebase, void, tl) +DEF_HELPER_1(mtc0_config0, void, tl) +DEF_HELPER_1(mtc0_config2, void, tl) +DEF_HELPER_1(mtc0_lladdr, void, tl) +DEF_HELPER_2(mtc0_watchlo, void, tl, i32) +DEF_HELPER_2(mtc0_watchhi, void, tl, i32) +DEF_HELPER_1(mtc0_xcontext, void, tl) +DEF_HELPER_1(mtc0_framemask, void, tl) +DEF_HELPER_1(mtc0_debug, void, tl) +DEF_HELPER_1(mttc0_debug, void, tl) +DEF_HELPER_1(mtc0_performance0, void, tl) +DEF_HELPER_1(mtc0_taglo, void, tl) +DEF_HELPER_1(mtc0_datalo, void, tl) +DEF_HELPER_1(mtc0_taghi, void, tl) +DEF_HELPER_1(mtc0_datahi, void, tl) + +/* MIPS MT functions */ +DEF_HELPER_1(mftgpr, tl, i32); +DEF_HELPER_1(mftlo, tl, i32) +DEF_HELPER_1(mfthi, tl, i32) +DEF_HELPER_1(mftacx, tl, i32) +DEF_HELPER_0(mftdsp, tl) +DEF_HELPER_2(mttgpr, void, tl, i32) +DEF_HELPER_2(mttlo, void, tl, i32) +DEF_HELPER_2(mtthi, void, tl, i32) +DEF_HELPER_2(mttacx, void, tl, i32) +DEF_HELPER_1(mttdsp, void, tl) +DEF_HELPER_1(dmt, tl, tl) +DEF_HELPER_1(emt, tl, tl) +DEF_HELPER_1(dvpe, tl, tl) +DEF_HELPER_1(evpe, tl, tl) +#endif /* !CONFIG_USER_ONLY */ +DEF_HELPER_2(fork, void, tl, tl) +DEF_HELPER_1(yield, tl, tl) + +/* CP1 functions */ +DEF_HELPER_1(cfc1, tl, i32) +DEF_HELPER_2(ctc1, void, tl, i32) + +DEF_HELPER_1(float_cvtd_s, i64, i32) +DEF_HELPER_1(float_cvtd_w, i64, i32) +DEF_HELPER_1(float_cvtd_l, i64, i64) +DEF_HELPER_1(float_cvtl_d, i64, i64) +DEF_HELPER_1(float_cvtl_s, i64, i32) +DEF_HELPER_1(float_cvtps_pw, i64, i64) +DEF_HELPER_1(float_cvtpw_ps, i64, i64) +DEF_HELPER_1(float_cvts_d, i32, i64) +DEF_HELPER_1(float_cvts_w, i32, i32) +DEF_HELPER_1(float_cvts_l, i32, i64) +DEF_HELPER_1(float_cvts_pl, i32, i32) +DEF_HELPER_1(float_cvts_pu, i32, i32) +DEF_HELPER_1(float_cvtw_s, i32, i32) +DEF_HELPER_1(float_cvtw_d, i32, i64) + +DEF_HELPER_2(float_addr_ps, i64, i64, i64) +DEF_HELPER_2(float_mulr_ps, i64, i64, i64) + +#define FOP_PROTO(op) \ +DEF_HELPER_1(float_ ## op ## l_s, i64, i32) \ +DEF_HELPER_1(float_ ## op ## l_d, i64, i64) \ +DEF_HELPER_1(float_ ## op ## w_s, i32, i32) \ +DEF_HELPER_1(float_ ## op ## w_d, i32, i64) +FOP_PROTO(round) +FOP_PROTO(trunc) +FOP_PROTO(ceil) +FOP_PROTO(floor) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_1(float_ ## op ## _s, i32, i32) \ +DEF_HELPER_1(float_ ## op ## _d, i64, i64) +FOP_PROTO(sqrt) +FOP_PROTO(rsqrt) +FOP_PROTO(recip) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_1(float_ ## op ## _s, i32, i32) \ +DEF_HELPER_1(float_ ## op ## _d, i64, i64) \ +DEF_HELPER_1(float_ ## op ## _ps, i64, i64) +FOP_PROTO(abs) +FOP_PROTO(chs) +FOP_PROTO(recip1) +FOP_PROTO(rsqrt1) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_2(float_ ## op ## _s, i32, i32, i32) \ +DEF_HELPER_2(float_ ## op ## _d, i64, i64, i64) \ +DEF_HELPER_2(float_ ## op ## _ps, i64, i64, i64) +FOP_PROTO(add) +FOP_PROTO(sub) +FOP_PROTO(mul) +FOP_PROTO(div) +FOP_PROTO(recip2) +FOP_PROTO(rsqrt2) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_3(float_ ## op ## _s, i32, i32, i32, i32) \ +DEF_HELPER_3(float_ ## op ## _d, i64, i64, i64, i64) \ +DEF_HELPER_3(float_ ## op ## _ps, i64, i64, i64, i64) +FOP_PROTO(muladd) +FOP_PROTO(mulsub) +FOP_PROTO(nmuladd) +FOP_PROTO(nmulsub) +#undef FOP_PROTO + +#define FOP_PROTO(op) \ +DEF_HELPER_3(cmp_d_ ## op, void, i64, i64, int) \ +DEF_HELPER_3(cmpabs_d_ ## op, void, i64, i64, int) \ +DEF_HELPER_3(cmp_s_ ## op, void, i32, i32, int) \ +DEF_HELPER_3(cmpabs_s_ ## op, void, i32, i32, int) \ +DEF_HELPER_3(cmp_ps_ ## op, void, i64, i64, int) \ +DEF_HELPER_3(cmpabs_ps_ ## op, void, i64, i64, int) +FOP_PROTO(f) +FOP_PROTO(un) +FOP_PROTO(eq) +FOP_PROTO(ueq) +FOP_PROTO(olt) +FOP_PROTO(ult) +FOP_PROTO(ole) +FOP_PROTO(ule) +FOP_PROTO(sf) +FOP_PROTO(ngle) +FOP_PROTO(seq) +FOP_PROTO(ngl) +FOP_PROTO(lt) +FOP_PROTO(nge) +FOP_PROTO(le) +FOP_PROTO(ngt) +#undef FOP_PROTO + +/* Special functions */ +#ifndef CONFIG_USER_ONLY +DEF_HELPER_0(tlbwi, void) +DEF_HELPER_0(tlbwr, void) +DEF_HELPER_0(tlbp, void) +DEF_HELPER_0(tlbr, void) +DEF_HELPER_0(di, tl) +DEF_HELPER_0(ei, tl) +DEF_HELPER_0(eret, void) +DEF_HELPER_0(deret, void) +#endif /* !CONFIG_USER_ONLY */ +DEF_HELPER_0(rdhwr_cpunum, tl) +DEF_HELPER_0(rdhwr_synci_step, tl) +DEF_HELPER_0(rdhwr_cc, tl) +DEF_HELPER_0(rdhwr_ccres, tl) +DEF_HELPER_1(pmon, void, int) +DEF_HELPER_0(wait, void) + +#include "def-helper.h" diff --git a/target-mips/machine.c b/target-mips/machine.c new file mode 100644 index 0000000..9ffac71 --- /dev/null +++ b/target-mips/machine.c @@ -0,0 +1,308 @@ +#include "hw/hw.h" +#include "hw/boards.h" + +#include "exec-all.h" + +static void save_tc(QEMUFile *f, TCState *tc) +{ + int i; + + /* Save active TC */ + for(i = 0; i < 32; i++) + qemu_put_betls(f, &tc->gpr[i]); + qemu_put_betls(f, &tc->PC); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_put_betls(f, &tc->HI[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_put_betls(f, &tc->LO[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_put_betls(f, &tc->ACX[i]); + qemu_put_betls(f, &tc->DSPControl); + qemu_put_sbe32s(f, &tc->CP0_TCStatus); + qemu_put_sbe32s(f, &tc->CP0_TCBind); + qemu_put_betls(f, &tc->CP0_TCHalt); + qemu_put_betls(f, &tc->CP0_TCContext); + qemu_put_betls(f, &tc->CP0_TCSchedule); + qemu_put_betls(f, &tc->CP0_TCScheFBack); + qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); +} + +static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) +{ + int i; + + for(i = 0; i < 32; i++) + qemu_put_be64s(f, &fpu->fpr[i].d); + qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess); + qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode); + qemu_put_s8s(f, &fpu->fp_status.float_exception_flags); + qemu_put_be32s(f, &fpu->fcr0); + qemu_put_be32s(f, &fpu->fcr31); +} + +void cpu_save(QEMUFile *f, void *opaque) +{ + CPUState *env = opaque; + int i; + + /* Save active TC */ + save_tc(f, &env->active_tc); + + /* Save active FPU */ + save_fpu(f, &env->active_fpu); + + /* Save MVP */ + qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl); + qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0); + qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1); + + /* Save TLB */ + qemu_put_be32s(f, &env->tlb->nb_tlb); + qemu_put_be32s(f, &env->tlb->tlb_in_use); + for(i = 0; i < MIPS_TLB_MAX; i++) { + uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) | + (env->tlb->mmu.r4k.tlb[i].C0 << 7) | + (env->tlb->mmu.r4k.tlb[i].C1 << 4) | + (env->tlb->mmu.r4k.tlb[i].V0 << 3) | + (env->tlb->mmu.r4k.tlb[i].V1 << 2) | + (env->tlb->mmu.r4k.tlb[i].D0 << 1) | + (env->tlb->mmu.r4k.tlb[i].D1 << 0)); + uint8_t asid; + + qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); + qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); + asid = env->tlb->mmu.r4k.tlb[i].ASID; + qemu_put_8s(f, &asid); + qemu_put_be16s(f, &flags); + qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); + qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); + } + + /* Save CPU metastate */ + qemu_put_be32s(f, &env->current_tc); + qemu_put_be32s(f, &env->current_fpu); + qemu_put_sbe32s(f, &env->error_code); + qemu_put_be32s(f, &env->hflags); + qemu_put_betls(f, &env->btarget); + i = env->bcond; + qemu_put_sbe32s(f, &i); + + /* Save remaining CP1 registers */ + qemu_put_sbe32s(f, &env->CP0_Index); + qemu_put_sbe32s(f, &env->CP0_Random); + qemu_put_sbe32s(f, &env->CP0_VPEControl); + qemu_put_sbe32s(f, &env->CP0_VPEConf0); + qemu_put_sbe32s(f, &env->CP0_VPEConf1); + qemu_put_betls(f, &env->CP0_YQMask); + qemu_put_betls(f, &env->CP0_VPESchedule); + qemu_put_betls(f, &env->CP0_VPEScheFBack); + qemu_put_sbe32s(f, &env->CP0_VPEOpt); + qemu_put_betls(f, &env->CP0_EntryLo0); + qemu_put_betls(f, &env->CP0_EntryLo1); + qemu_put_betls(f, &env->CP0_Context); + qemu_put_sbe32s(f, &env->CP0_PageMask); + qemu_put_sbe32s(f, &env->CP0_PageGrain); + qemu_put_sbe32s(f, &env->CP0_Wired); + qemu_put_sbe32s(f, &env->CP0_SRSConf0); + qemu_put_sbe32s(f, &env->CP0_SRSConf1); + qemu_put_sbe32s(f, &env->CP0_SRSConf2); + qemu_put_sbe32s(f, &env->CP0_SRSConf3); + qemu_put_sbe32s(f, &env->CP0_SRSConf4); + qemu_put_sbe32s(f, &env->CP0_HWREna); + qemu_put_betls(f, &env->CP0_BadVAddr); + qemu_put_sbe32s(f, &env->CP0_Count); + qemu_put_betls(f, &env->CP0_EntryHi); + qemu_put_sbe32s(f, &env->CP0_Compare); + qemu_put_sbe32s(f, &env->CP0_Status); + qemu_put_sbe32s(f, &env->CP0_IntCtl); + qemu_put_sbe32s(f, &env->CP0_SRSCtl); + qemu_put_sbe32s(f, &env->CP0_SRSMap); + qemu_put_sbe32s(f, &env->CP0_Cause); + qemu_put_betls(f, &env->CP0_EPC); + qemu_put_sbe32s(f, &env->CP0_PRid); + qemu_put_sbe32s(f, &env->CP0_EBase); + qemu_put_sbe32s(f, &env->CP0_Config0); + qemu_put_sbe32s(f, &env->CP0_Config1); + qemu_put_sbe32s(f, &env->CP0_Config2); + qemu_put_sbe32s(f, &env->CP0_Config3); + qemu_put_sbe32s(f, &env->CP0_Config6); + qemu_put_sbe32s(f, &env->CP0_Config7); + qemu_put_betls(f, &env->lladdr); + for(i = 0; i < 8; i++) + qemu_put_betls(f, &env->CP0_WatchLo[i]); + for(i = 0; i < 8; i++) + qemu_put_sbe32s(f, &env->CP0_WatchHi[i]); + qemu_put_betls(f, &env->CP0_XContext); + qemu_put_sbe32s(f, &env->CP0_Framemask); + qemu_put_sbe32s(f, &env->CP0_Debug); + qemu_put_betls(f, &env->CP0_DEPC); + qemu_put_sbe32s(f, &env->CP0_Performance0); + qemu_put_sbe32s(f, &env->CP0_TagLo); + qemu_put_sbe32s(f, &env->CP0_DataLo); + qemu_put_sbe32s(f, &env->CP0_TagHi); + qemu_put_sbe32s(f, &env->CP0_DataHi); + qemu_put_betls(f, &env->CP0_ErrorEPC); + qemu_put_sbe32s(f, &env->CP0_DESAVE); + + /* Save inactive TC state */ + for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) + save_tc(f, &env->tcs[i]); + for (i = 0; i < MIPS_FPU_MAX; i++) + save_fpu(f, &env->fpus[i]); +} + +static void load_tc(QEMUFile *f, TCState *tc) +{ + int i; + + /* Save active TC */ + for(i = 0; i < 32; i++) + qemu_get_betls(f, &tc->gpr[i]); + qemu_get_betls(f, &tc->PC); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_get_betls(f, &tc->HI[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_get_betls(f, &tc->LO[i]); + for(i = 0; i < MIPS_DSP_ACC; i++) + qemu_get_betls(f, &tc->ACX[i]); + qemu_get_betls(f, &tc->DSPControl); + qemu_get_sbe32s(f, &tc->CP0_TCStatus); + qemu_get_sbe32s(f, &tc->CP0_TCBind); + qemu_get_betls(f, &tc->CP0_TCHalt); + qemu_get_betls(f, &tc->CP0_TCContext); + qemu_get_betls(f, &tc->CP0_TCSchedule); + qemu_get_betls(f, &tc->CP0_TCScheFBack); + qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); +} + +static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) +{ + int i; + + for(i = 0; i < 32; i++) + qemu_get_be64s(f, &fpu->fpr[i].d); + qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); + qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); + qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); + qemu_get_be32s(f, &fpu->fcr0); + qemu_get_be32s(f, &fpu->fcr31); +} + +int cpu_load(QEMUFile *f, void *opaque, int version_id) +{ + CPUState *env = opaque; + int i; + + if (version_id != 3) + return -EINVAL; + + /* Load active TC */ + load_tc(f, &env->active_tc); + + /* Load active FPU */ + load_fpu(f, &env->active_fpu); + + /* Load MVP */ + qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); + qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); + qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); + + /* Load TLB */ + qemu_get_be32s(f, &env->tlb->nb_tlb); + qemu_get_be32s(f, &env->tlb->tlb_in_use); + for(i = 0; i < MIPS_TLB_MAX; i++) { + uint16_t flags; + uint8_t asid; + + qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); + qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); + qemu_get_8s(f, &asid); + env->tlb->mmu.r4k.tlb[i].ASID = asid; + qemu_get_be16s(f, &flags); + env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1; + env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; + env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; + env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; + env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; + env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; + env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; + qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); + qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); + } + + /* Load CPU metastate */ + qemu_get_be32s(f, &env->current_tc); + qemu_get_be32s(f, &env->current_fpu); + qemu_get_sbe32s(f, &env->error_code); + qemu_get_be32s(f, &env->hflags); + qemu_get_betls(f, &env->btarget); + qemu_get_sbe32s(f, &i); + env->bcond = i; + + /* Load remaining CP1 registers */ + qemu_get_sbe32s(f, &env->CP0_Index); + qemu_get_sbe32s(f, &env->CP0_Random); + qemu_get_sbe32s(f, &env->CP0_VPEControl); + qemu_get_sbe32s(f, &env->CP0_VPEConf0); + qemu_get_sbe32s(f, &env->CP0_VPEConf1); + qemu_get_betls(f, &env->CP0_YQMask); + qemu_get_betls(f, &env->CP0_VPESchedule); + qemu_get_betls(f, &env->CP0_VPEScheFBack); + qemu_get_sbe32s(f, &env->CP0_VPEOpt); + qemu_get_betls(f, &env->CP0_EntryLo0); + qemu_get_betls(f, &env->CP0_EntryLo1); + qemu_get_betls(f, &env->CP0_Context); + qemu_get_sbe32s(f, &env->CP0_PageMask); + qemu_get_sbe32s(f, &env->CP0_PageGrain); + qemu_get_sbe32s(f, &env->CP0_Wired); + qemu_get_sbe32s(f, &env->CP0_SRSConf0); + qemu_get_sbe32s(f, &env->CP0_SRSConf1); + qemu_get_sbe32s(f, &env->CP0_SRSConf2); + qemu_get_sbe32s(f, &env->CP0_SRSConf3); + qemu_get_sbe32s(f, &env->CP0_SRSConf4); + qemu_get_sbe32s(f, &env->CP0_HWREna); + qemu_get_betls(f, &env->CP0_BadVAddr); + qemu_get_sbe32s(f, &env->CP0_Count); + qemu_get_betls(f, &env->CP0_EntryHi); + qemu_get_sbe32s(f, &env->CP0_Compare); + qemu_get_sbe32s(f, &env->CP0_Status); + qemu_get_sbe32s(f, &env->CP0_IntCtl); + qemu_get_sbe32s(f, &env->CP0_SRSCtl); + qemu_get_sbe32s(f, &env->CP0_SRSMap); + qemu_get_sbe32s(f, &env->CP0_Cause); + qemu_get_betls(f, &env->CP0_EPC); + qemu_get_sbe32s(f, &env->CP0_PRid); + qemu_get_sbe32s(f, &env->CP0_EBase); + qemu_get_sbe32s(f, &env->CP0_Config0); + qemu_get_sbe32s(f, &env->CP0_Config1); + qemu_get_sbe32s(f, &env->CP0_Config2); + qemu_get_sbe32s(f, &env->CP0_Config3); + qemu_get_sbe32s(f, &env->CP0_Config6); + qemu_get_sbe32s(f, &env->CP0_Config7); + qemu_get_betls(f, &env->lladdr); + for(i = 0; i < 8; i++) + qemu_get_betls(f, &env->CP0_WatchLo[i]); + for(i = 0; i < 8; i++) + qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); + qemu_get_betls(f, &env->CP0_XContext); + qemu_get_sbe32s(f, &env->CP0_Framemask); + qemu_get_sbe32s(f, &env->CP0_Debug); + qemu_get_betls(f, &env->CP0_DEPC); + qemu_get_sbe32s(f, &env->CP0_Performance0); + qemu_get_sbe32s(f, &env->CP0_TagLo); + qemu_get_sbe32s(f, &env->CP0_DataLo); + qemu_get_sbe32s(f, &env->CP0_TagHi); + qemu_get_sbe32s(f, &env->CP0_DataHi); + qemu_get_betls(f, &env->CP0_ErrorEPC); + qemu_get_sbe32s(f, &env->CP0_DESAVE); + + /* Load inactive TC state */ + for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) + load_tc(f, &env->tcs[i]); + for (i = 0; i < MIPS_FPU_MAX; i++) + load_fpu(f, &env->fpus[i]); + + /* XXX: ensure compatiblity for halted bit ? */ + tlb_flush(env, 1); + return 0; +} diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h new file mode 100644 index 0000000..54e80f1 --- /dev/null +++ b/target-mips/mips-defs.h @@ -0,0 +1,63 @@ +#if !defined (__QEMU_MIPS_DEFS_H__) +#define __QEMU_MIPS_DEFS_H__ + +/* If we want to use host float regs... */ +//#define USE_HOST_FLOAT_REGS + +/* Real pages are variable size... */ +#define TARGET_PAGE_BITS 12 +#define MIPS_TLB_MAX 128 + +#if defined(TARGET_MIPS64) +#define TARGET_LONG_BITS 64 +#else +#define TARGET_LONG_BITS 32 +#endif + +/* Masks used to mark instructions to indicate which ISA level they + were introduced in. */ +#define ISA_MIPS1 0x00000001 +#define ISA_MIPS2 0x00000002 +#define ISA_MIPS3 0x00000004 +#define ISA_MIPS4 0x00000008 +#define ISA_MIPS5 0x00000010 +#define ISA_MIPS32 0x00000020 +#define ISA_MIPS32R2 0x00000040 +#define ISA_MIPS64 0x00000080 +#define ISA_MIPS64R2 0x00000100 + +/* MIPS ASEs. */ +#define ASE_MIPS16 0x00001000 +#define ASE_MIPS3D 0x00002000 +#define ASE_MDMX 0x00004000 +#define ASE_DSP 0x00008000 +#define ASE_DSPR2 0x00010000 +#define ASE_MT 0x00020000 +#define ASE_SMARTMIPS 0x00040000 + +/* Chip specific instructions. */ +#define INSN_VR54XX 0x80000000 + +/* MIPS CPU defines. */ +#define CPU_MIPS1 (ISA_MIPS1) +#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) +#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) +#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) + +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) + +/* MIPS Technologies "Release 1" */ +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) + +/* MIPS Technologies "Release 2" */ +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) + +/* Strictly follow the architecture standard: + - Disallow "special" instruction handling for PMON/SPIM. + Note that we still maintain Count/Compare to match the host clock. */ +//#define MIPS_STRICT_STANDARD 1 + +#endif /* !defined (__QEMU_MIPS_DEFS_H__) */ diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c new file mode 100644 index 0000000..61a39df --- /dev/null +++ b/target-mips/op_helper.c @@ -0,0 +1,2992 @@ +/* + * MIPS emulation helpers for qemu. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include <stdlib.h> +#include "exec.h" + +#include "host-utils.h" + +#include "helper.h" +/*****************************************************************************/ +/* Exceptions processing helpers */ + +void helper_raise_exception_err (uint32_t exception, int error_code) +{ +#if 1 + if (exception < 0x100) + qemu_log("%s: %d %d\n", __func__, exception, error_code); +#endif + env->exception_index = exception; + env->error_code = error_code; + cpu_loop_exit(); +} + +void helper_raise_exception (uint32_t exception) +{ + helper_raise_exception_err(exception, 0); +} + +void helper_interrupt_restart (void) +{ + if (!(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM) && + (env->CP0_Status & (1 << CP0St_IE)) && + (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { + env->CP0_Cause &= ~(0x1f << CP0Ca_EC); + helper_raise_exception(EXCP_EXT_INTERRUPT); + } +} + +#if !defined(CONFIG_USER_ONLY) +static void do_restore_state (void *pc_ptr) +{ + TranslationBlock *tb; + unsigned long pc = (unsigned long) pc_ptr; + + tb = tb_find_pc (pc); + if (tb) { + cpu_restore_state (tb, env, pc); + } +} +#endif + +#if defined(CONFIG_USER_ONLY) +#define HELPER_LD(name, insn, type) \ +static inline type do_##name(target_ulong addr, int mem_idx) \ +{ \ + return (type) insn##_raw(addr); \ +} +#else +#define HELPER_LD(name, insn, type) \ +static inline type do_##name(target_ulong addr, int mem_idx) \ +{ \ + switch (mem_idx) \ + { \ + case 0: return (type) insn##_kernel(addr); break; \ + case 1: return (type) insn##_super(addr); break; \ + default: \ + case 2: return (type) insn##_user(addr); break; \ + } \ +} +#endif +HELPER_LD(lbu, ldub, uint8_t) +HELPER_LD(lw, ldl, int32_t) +#ifdef TARGET_MIPS64 +HELPER_LD(ld, ldq, int64_t) +#endif +#undef HELPER_LD + +#if defined(CONFIG_USER_ONLY) +#define HELPER_ST(name, insn, type) \ +static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +{ \ + insn##_raw(addr, val); \ +} +#else +#define HELPER_ST(name, insn, type) \ +static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +{ \ + switch (mem_idx) \ + { \ + case 0: insn##_kernel(addr, val); break; \ + case 1: insn##_super(addr, val); break; \ + default: \ + case 2: insn##_user(addr, val); break; \ + } \ +} +#endif +HELPER_ST(sb, stb, uint8_t) +HELPER_ST(sw, stl, uint32_t) +#ifdef TARGET_MIPS64 +HELPER_ST(sd, stq, uint64_t) +#endif +#undef HELPER_ST + +target_ulong helper_clo (target_ulong arg1) +{ + return clo32(arg1); +} + +target_ulong helper_clz (target_ulong arg1) +{ + return clz32(arg1); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_dclo (target_ulong arg1) +{ + return clo64(arg1); +} + +target_ulong helper_dclz (target_ulong arg1) +{ + return clz64(arg1); +} +#endif /* TARGET_MIPS64 */ + +/* 64 bits arithmetic for 32 bits hosts */ +static inline uint64_t get_HILO (void) +{ + return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; +} + +static inline void set_HILO (uint64_t HILO) +{ + env->active_tc.LO[0] = (int32_t)HILO; + env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO) +{ + env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO) +{ + arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +/* Multiplication variants of the vr54xx. */ +target_ulong helper_muls (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_macc (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_macchi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_maccu (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_msac (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_msachi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_msacu (target_ulong arg1, target_ulong arg2) +{ + set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); + + return arg1; +} + +target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + + return arg1; +} + +target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + + return arg1; +} + +target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2) +{ + set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); + + return arg1; +} + +#ifdef TARGET_MIPS64 +void helper_dmult (target_ulong arg1, target_ulong arg2) +{ + muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); +} + +void helper_dmultu (target_ulong arg1, target_ulong arg2) +{ + mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); +} +#endif + +#ifndef CONFIG_USER_ONLY + +static inline target_phys_addr_t do_translate_address(target_ulong address, int rw) +{ + target_phys_addr_t lladdr; + + lladdr = cpu_mips_translate_address(env, address, rw); + + if (lladdr == -1LL) { + cpu_loop_exit(); + } else { + return lladdr; + } +} + +#define HELPER_LD_ATOMIC(name, insn) \ +target_ulong helper_##name(target_ulong arg, int mem_idx) \ +{ \ + env->lladdr = do_translate_address(arg, 0); \ + env->llval = do_##insn(arg, mem_idx); \ + return env->llval; \ +} +HELPER_LD_ATOMIC(ll, lw) +#ifdef TARGET_MIPS64 +HELPER_LD_ATOMIC(lld, ld) +#endif +#undef HELPER_LD_ATOMIC + +#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ +target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \ +{ \ + target_long tmp; \ + \ + if (arg2 & almask) { \ + env->CP0_BadVAddr = arg2; \ + helper_raise_exception(EXCP_AdES); \ + } \ + if (do_translate_address(arg2, 1) == env->lladdr) { \ + tmp = do_##ld_insn(arg2, mem_idx); \ + if (tmp == env->llval) { \ + do_##st_insn(arg2, arg1, mem_idx); \ + return 1; \ + } \ + } \ + return 0; \ +} +HELPER_ST_ATOMIC(sc, lw, sw, 0x3) +#ifdef TARGET_MIPS64 +HELPER_ST_ATOMIC(scd, ld, sd, 0x7) +#endif +#undef HELPER_ST_ATOMIC +#endif + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK(v) ((v) & 3) +#define GET_OFFSET(addr, offset) (addr + (offset)) +#else +#define GET_LMASK(v) (((v) & 3) ^ 3) +#define GET_OFFSET(addr, offset) (addr - (offset)) +#endif + +target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + target_ulong tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); + + if (GET_LMASK(arg2) <= 2) { + tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); + } + + if (GET_LMASK(arg2) <= 1) { + tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); + } + + if (GET_LMASK(arg2) == 0) { + tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + arg1 = (arg1 & 0xFFFFFF00) | tmp; + } + return (int32_t)arg1; +} + +target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + target_ulong tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0xFFFFFF00) | tmp; + + if (GET_LMASK(arg2) >= 1) { + tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); + } + + if (GET_LMASK(arg2) >= 2) { + tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); + } + + if (GET_LMASK(arg2) == 3) { + tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); + } + return (int32_t)arg1; +} + +void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx); + + if (GET_LMASK(arg2) <= 2) + do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK(arg2) <= 1) + do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK(arg2) == 0) + do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); +} + +void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)arg1, mem_idx); + + if (GET_LMASK(arg2) >= 1) + do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK(arg2) >= 2) + do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK(arg2) == 3) + do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); +} + +#if defined(TARGET_MIPS64) +/* "half" load and stores. We must do the memory access inline, + or fault handling won't work. */ + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK64(v) ((v) & 7) +#else +#define GET_LMASK64(v) (((v) & 7) ^ 7) +#endif + +target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + uint64_t tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); + + if (GET_LMASK64(arg2) <= 6) { + tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); + } + + if (GET_LMASK64(arg2) <= 5) { + tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); + } + + if (GET_LMASK64(arg2) <= 4) { + tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); + } + + if (GET_LMASK64(arg2) <= 3) { + tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx); + arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); + } + + if (GET_LMASK64(arg2) <= 2) { + tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); + } + + if (GET_LMASK64(arg2) <= 1) { + tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); + } + + if (GET_LMASK64(arg2) == 0) { + tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; + } + + return arg1; +} + +target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + uint64_t tmp; + + tmp = do_lbu(arg2, mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; + + if (GET_LMASK64(arg2) >= 1) { + tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); + } + + if (GET_LMASK64(arg2) >= 2) { + tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); + } + + if (GET_LMASK64(arg2) >= 3) { + tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); + } + + if (GET_LMASK64(arg2) >= 4) { + tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx); + arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); + } + + if (GET_LMASK64(arg2) >= 5) { + tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx); + arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); + } + + if (GET_LMASK64(arg2) >= 6) { + tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx); + arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); + } + + if (GET_LMASK64(arg2) == 7) { + tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx); + arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); + } + + return arg1; +} + +void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx); + + if (GET_LMASK64(arg2) <= 6) + do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); + + if (GET_LMASK64(arg2) <= 5) + do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); + + if (GET_LMASK64(arg2) <= 4) + do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); + + if (GET_LMASK64(arg2) <= 3) + do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); + + if (GET_LMASK64(arg2) <= 2) + do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK64(arg2) <= 1) + do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK64(arg2) <= 0) + do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); +} + +void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx) +{ + do_sb(arg2, (uint8_t)arg1, mem_idx); + + if (GET_LMASK64(arg2) >= 1) + do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + + if (GET_LMASK64(arg2) >= 2) + do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + + if (GET_LMASK64(arg2) >= 3) + do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + + if (GET_LMASK64(arg2) >= 4) + do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); + + if (GET_LMASK64(arg2) >= 5) + do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); + + if (GET_LMASK64(arg2) >= 6) + do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); + + if (GET_LMASK64(arg2) == 7) + do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); +} +#endif /* TARGET_MIPS64 */ + +#ifndef CONFIG_USER_ONLY +/* CP0 helpers */ +target_ulong helper_mfc0_mvpcontrol (void) +{ + return env->mvp->CP0_MVPControl; +} + +target_ulong helper_mfc0_mvpconf0 (void) +{ + return env->mvp->CP0_MVPConf0; +} + +target_ulong helper_mfc0_mvpconf1 (void) +{ + return env->mvp->CP0_MVPConf1; +} + +target_ulong helper_mfc0_random (void) +{ + return (int32_t)cpu_mips_get_random(env); +} + +target_ulong helper_mfc0_tcstatus (void) +{ + return env->active_tc.CP0_TCStatus; +} + +target_ulong helper_mftc0_tcstatus(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCStatus; + else + return env->tcs[other_tc].CP0_TCStatus; +} + +target_ulong helper_mfc0_tcbind (void) +{ + return env->active_tc.CP0_TCBind; +} + +target_ulong helper_mftc0_tcbind(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCBind; + else + return env->tcs[other_tc].CP0_TCBind; +} + +target_ulong helper_mfc0_tcrestart (void) +{ + return env->active_tc.PC; +} + +target_ulong helper_mftc0_tcrestart(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.PC; + else + return env->tcs[other_tc].PC; +} + +target_ulong helper_mfc0_tchalt (void) +{ + return env->active_tc.CP0_TCHalt; +} + +target_ulong helper_mftc0_tchalt(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCHalt; + else + return env->tcs[other_tc].CP0_TCHalt; +} + +target_ulong helper_mfc0_tccontext (void) +{ + return env->active_tc.CP0_TCContext; +} + +target_ulong helper_mftc0_tccontext(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCContext; + else + return env->tcs[other_tc].CP0_TCContext; +} + +target_ulong helper_mfc0_tcschedule (void) +{ + return env->active_tc.CP0_TCSchedule; +} + +target_ulong helper_mftc0_tcschedule(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCSchedule; + else + return env->tcs[other_tc].CP0_TCSchedule; +} + +target_ulong helper_mfc0_tcschefback (void) +{ + return env->active_tc.CP0_TCScheFBack; +} + +target_ulong helper_mftc0_tcschefback(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.CP0_TCScheFBack; + else + return env->tcs[other_tc].CP0_TCScheFBack; +} + +target_ulong helper_mfc0_count (void) +{ + return (int32_t)cpu_mips_get_count(env); +} + +target_ulong helper_mftc0_entryhi(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus; + + if (other_tc == env->current_tc) + tcstatus = env->active_tc.CP0_TCStatus; + else + tcstatus = env->tcs[other_tc].CP0_TCStatus; + + return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff); +} + +target_ulong helper_mftc0_status(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + target_ulong t0; + int32_t tcstatus; + + if (other_tc == env->current_tc) + tcstatus = env->active_tc.CP0_TCStatus; + else + tcstatus = env->tcs[other_tc].CP0_TCStatus; + + t0 = env->CP0_Status & ~0xf1000018; + t0 |= tcstatus & (0xf << CP0TCSt_TCU0); + t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); + t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); + + return t0; +} + +target_ulong helper_mfc0_lladdr (void) +{ + return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); +} + +target_ulong helper_mfc0_watchlo (uint32_t sel) +{ + return (int32_t)env->CP0_WatchLo[sel]; +} + +target_ulong helper_mfc0_watchhi (uint32_t sel) +{ + return env->CP0_WatchHi[sel]; +} + +target_ulong helper_mfc0_debug (void) +{ + target_ulong t0 = env->CP0_Debug; + if (env->hflags & MIPS_HFLAG_DM) + t0 |= 1 << CP0DB_DM; + + return t0; +} + +target_ulong helper_mftc0_debug(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus; + + if (other_tc == env->current_tc) + tcstatus = env->active_tc.CP0_Debug_tcstatus; + else + tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus; + + /* XXX: Might be wrong, check with EJTAG spec. */ + return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_dmfc0_tcrestart (void) +{ + return env->active_tc.PC; +} + +target_ulong helper_dmfc0_tchalt (void) +{ + return env->active_tc.CP0_TCHalt; +} + +target_ulong helper_dmfc0_tccontext (void) +{ + return env->active_tc.CP0_TCContext; +} + +target_ulong helper_dmfc0_tcschedule (void) +{ + return env->active_tc.CP0_TCSchedule; +} + +target_ulong helper_dmfc0_tcschefback (void) +{ + return env->active_tc.CP0_TCScheFBack; +} + +target_ulong helper_dmfc0_lladdr (void) +{ + return env->lladdr >> env->CP0_LLAddr_shift; +} + +target_ulong helper_dmfc0_watchlo (uint32_t sel) +{ + return env->CP0_WatchLo[sel]; +} +#endif /* TARGET_MIPS64 */ + +void helper_mtc0_index (target_ulong arg1) +{ + int num = 1; + unsigned int tmp = env->tlb->nb_tlb; + + do { + tmp >>= 1; + num <<= 1; + } while (tmp); + env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); +} + +void helper_mtc0_mvpcontrol (target_ulong arg1) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) + mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | + (1 << CP0MVPCo_EVP); + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0MVPCo_STLB); + newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); + + // TODO: Enable/disable shared TLB, enable/disable VPEs. + + env->mvp->CP0_MVPControl = newval; +} + +void helper_mtc0_vpecontrol (target_ulong arg1) +{ + uint32_t mask; + uint32_t newval; + + mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | + (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); + newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); + + /* Yield scheduler intercept not implemented. */ + /* Gating storage scheduler intercept not implemented. */ + + // TODO: Enable/disable TCs. + + env->CP0_VPEControl = newval; +} + +void helper_mtc0_vpeconf0 (target_ulong arg1) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) + mask |= (0xff << CP0VPEC0_XTC); + mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + } + newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); + + // TODO: TC exclusive handling due to ERL/EXL. + + env->CP0_VPEConf0 = newval; +} + +void helper_mtc0_vpeconf1 (target_ulong arg1) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | + (0xff << CP0VPEC1_NCP1); + newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); + + /* UDI not implemented. */ + /* CP2 not implemented. */ + + // TODO: Handle FPU (CP1) binding. + + env->CP0_VPEConf1 = newval; +} + +void helper_mtc0_yqmask (target_ulong arg1) +{ + /* Yield qualifier inputs not implemented. */ + env->CP0_YQMask = 0x00000000; +} + +void helper_mtc0_vpeopt (target_ulong arg1) +{ + env->CP0_VPEOpt = arg1 & 0x0000ffff; +} + +void helper_mtc0_entrylo0 (target_ulong arg1) +{ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; +} + +void helper_mtc0_tcstatus (target_ulong arg1) +{ + uint32_t mask = env->CP0_TCStatus_rw_bitmask; + uint32_t newval; + + newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); + + // TODO: Sync with CP0_Status. + + env->active_tc.CP0_TCStatus = newval; +} + +void helper_mttc0_tcstatus (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + // TODO: Sync with CP0_Status. + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCStatus = arg1; + else + env->tcs[other_tc].CP0_TCStatus = arg1; +} + +void helper_mtc0_tcbind (target_ulong arg1) +{ + uint32_t mask = (1 << CP0TCBd_TBE); + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0TCBd_CurVPE); + newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); + env->active_tc.CP0_TCBind = newval; +} + +void helper_mttc0_tcbind (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask = (1 << CP0TCBd_TBE); + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0TCBd_CurVPE); + if (other_tc == env->current_tc) { + newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); + env->active_tc.CP0_TCBind = newval; + } else { + newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); + env->tcs[other_tc].CP0_TCBind = newval; + } +} + +void helper_mtc0_tcrestart (target_ulong arg1) +{ + env->active_tc.PC = arg1; + env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); + env->lladdr = 0ULL; + /* MIPS16 not implemented. */ +} + +void helper_mttc0_tcrestart (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) { + env->active_tc.PC = arg1; + env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); + env->lladdr = 0ULL; + /* MIPS16 not implemented. */ + } else { + env->tcs[other_tc].PC = arg1; + env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); + env->lladdr = 0ULL; + /* MIPS16 not implemented. */ + } +} + +void helper_mtc0_tchalt (target_ulong arg1) +{ + env->active_tc.CP0_TCHalt = arg1 & 0x1; + + // TODO: Halt TC / Restart (if allocated+active) TC. +} + +void helper_mttc0_tchalt (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + // TODO: Halt TC / Restart (if allocated+active) TC. + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCHalt = arg1; + else + env->tcs[other_tc].CP0_TCHalt = arg1; +} + +void helper_mtc0_tccontext (target_ulong arg1) +{ + env->active_tc.CP0_TCContext = arg1; +} + +void helper_mttc0_tccontext (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCContext = arg1; + else + env->tcs[other_tc].CP0_TCContext = arg1; +} + +void helper_mtc0_tcschedule (target_ulong arg1) +{ + env->active_tc.CP0_TCSchedule = arg1; +} + +void helper_mttc0_tcschedule (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCSchedule = arg1; + else + env->tcs[other_tc].CP0_TCSchedule = arg1; +} + +void helper_mtc0_tcschefback (target_ulong arg1) +{ + env->active_tc.CP0_TCScheFBack = arg1; +} + +void helper_mttc0_tcschefback (target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.CP0_TCScheFBack = arg1; + else + env->tcs[other_tc].CP0_TCScheFBack = arg1; +} + +void helper_mtc0_entrylo1 (target_ulong arg1) +{ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; +} + +void helper_mtc0_context (target_ulong arg1) +{ + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); +} + +void helper_mtc0_pagemask (target_ulong arg1) +{ + /* 1k pages not implemented */ + env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); +} + +void helper_mtc0_pagegrain (target_ulong arg1) +{ + /* SmartMIPS not implemented */ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_PageGrain = 0; +} + +void helper_mtc0_wired (target_ulong arg1) +{ + env->CP0_Wired = arg1 % env->tlb->nb_tlb; +} + +void helper_mtc0_srsconf0 (target_ulong arg1) +{ + env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; +} + +void helper_mtc0_srsconf1 (target_ulong arg1) +{ + env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; +} + +void helper_mtc0_srsconf2 (target_ulong arg1) +{ + env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; +} + +void helper_mtc0_srsconf3 (target_ulong arg1) +{ + env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; +} + +void helper_mtc0_srsconf4 (target_ulong arg1) +{ + env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; +} + +void helper_mtc0_hwrena (target_ulong arg1) +{ + env->CP0_HWREna = arg1 & 0x0000000F; +} + +void helper_mtc0_count (target_ulong arg1) +{ + cpu_mips_store_count(env, arg1); +} + +void helper_mtc0_entryhi (target_ulong arg1) +{ + target_ulong old, val; + + /* 1k pages not implemented */ + val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); +#if defined(TARGET_MIPS64) + val &= env->SEGMask; +#endif + old = env->CP0_EntryHi; + env->CP0_EntryHi = val; + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff; + env->active_tc.CP0_TCStatus = tcst | (val & 0xff); + } + /* If the ASID changes, flush qemu's TLB. */ + if ((old & 0xFF) != (val & 0xFF)) + cpu_mips_tlb_flush(env, 1); +} + +void helper_mttc0_entryhi(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus; + + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff); + if (other_tc == env->current_tc) { + tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff); + env->active_tc.CP0_TCStatus = tcstatus; + } else { + tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff); + env->tcs[other_tc].CP0_TCStatus = tcstatus; + } +} + +void helper_mtc0_compare (target_ulong arg1) +{ + cpu_mips_store_compare(env, arg1); +} + +void helper_mtc0_status (target_ulong arg1) +{ + uint32_t val, old; + uint32_t mask = env->CP0_Status_rw_bitmask; + + val = arg1 & mask; + old = env->CP0_Status; + env->CP0_Status = (env->CP0_Status & ~mask) | val; + compute_hflags(env); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", + old, old & env->CP0_Cause & CP0Ca_IP_mask, + val, val & env->CP0_Cause & CP0Ca_IP_mask, + env->CP0_Cause); + switch (env->hflags & MIPS_HFLAG_KSU) { + case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; + case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; + case MIPS_HFLAG_KM: qemu_log("\n"); break; + default: cpu_abort(env, "Invalid MMU mode!\n"); break; + } + } + cpu_mips_update_irq(env); +} + +void helper_mttc0_status(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus; + + env->CP0_Status = arg1 & ~0xf1000018; + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0)); + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); + if (other_tc == env->current_tc) + env->active_tc.CP0_TCStatus = tcstatus; + else + env->tcs[other_tc].CP0_TCStatus = tcstatus; +} + +void helper_mtc0_intctl (target_ulong arg1) +{ + /* vectored interrupts not implemented, no performance counters. */ + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0); +} + +void helper_mtc0_srsctl (target_ulong arg1) +{ + uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); +} + +void helper_mtc0_cause (target_ulong arg1) +{ + uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; + + if (env->insn_flags & ISA_MIPS32R2) + mask |= 1 << CP0Ca_DC; + + env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) + cpu_mips_stop_count(env); + else + cpu_mips_start_count(env); + } + + /* Handle the software interrupt as an hardware one, as they + are very similar */ + if (arg1 & CP0Ca_IP_mask) { + cpu_mips_update_irq(env); + } +} + +void helper_mtc0_ebase (target_ulong arg1) +{ + /* vectored interrupts not implemented */ + /* Multi-CPU not implemented */ + env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000); +} + +void helper_mtc0_config0 (target_ulong arg1) +{ + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); +} + +void helper_mtc0_config2 (target_ulong arg1) +{ + /* tertiary/secondary caches not implemented */ + env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); +} + +void helper_mtc0_lladdr (target_ulong arg1) +{ + target_long mask = env->CP0_LLAddr_rw_bitmask; + arg1 = arg1 << env->CP0_LLAddr_shift; + env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); +} + +void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel) +{ + /* Watch exceptions for instructions, data loads, data stores + not implemented. */ + env->CP0_WatchLo[sel] = (arg1 & ~0x7); +} + +void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel) +{ + env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); +} + +void helper_mtc0_xcontext (target_ulong arg1) +{ + target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; + env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); +} + +void helper_mtc0_framemask (target_ulong arg1) +{ + env->CP0_Framemask = arg1; /* XXX */ +} + +void helper_mtc0_debug (target_ulong arg1) +{ + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); + if (arg1 & (1 << CP0DB_DM)) + env->hflags |= MIPS_HFLAG_DM; + else + env->hflags &= ~MIPS_HFLAG_DM; +} + +void helper_mttc0_debug(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); + + /* XXX: Might be wrong, check with EJTAG spec. */ + if (other_tc == env->current_tc) + env->active_tc.CP0_Debug_tcstatus = val; + else + env->tcs[other_tc].CP0_Debug_tcstatus = val; + env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +void helper_mtc0_performance0 (target_ulong arg1) +{ + env->CP0_Performance0 = arg1 & 0x000007ff; +} + +void helper_mtc0_taglo (target_ulong arg1) +{ + env->CP0_TagLo = arg1 & 0xFFFFFCF6; +} + +void helper_mtc0_datalo (target_ulong arg1) +{ + env->CP0_DataLo = arg1; /* XXX */ +} + +void helper_mtc0_taghi (target_ulong arg1) +{ + env->CP0_TagHi = arg1; /* XXX */ +} + +void helper_mtc0_datahi (target_ulong arg1) +{ + env->CP0_DataHi = arg1; /* XXX */ +} + +/* MIPS MT functions */ +target_ulong helper_mftgpr(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.gpr[sel]; + else + return env->tcs[other_tc].gpr[sel]; +} + +target_ulong helper_mftlo(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.LO[sel]; + else + return env->tcs[other_tc].LO[sel]; +} + +target_ulong helper_mfthi(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.HI[sel]; + else + return env->tcs[other_tc].HI[sel]; +} + +target_ulong helper_mftacx(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.ACX[sel]; + else + return env->tcs[other_tc].ACX[sel]; +} + +target_ulong helper_mftdsp(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + return env->active_tc.DSPControl; + else + return env->tcs[other_tc].DSPControl; +} + +void helper_mttgpr(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.gpr[sel] = arg1; + else + env->tcs[other_tc].gpr[sel] = arg1; +} + +void helper_mttlo(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.LO[sel] = arg1; + else + env->tcs[other_tc].LO[sel] = arg1; +} + +void helper_mtthi(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.HI[sel] = arg1; + else + env->tcs[other_tc].HI[sel] = arg1; +} + +void helper_mttacx(target_ulong arg1, uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.ACX[sel] = arg1; + else + env->tcs[other_tc].ACX[sel] = arg1; +} + +void helper_mttdsp(target_ulong arg1) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if (other_tc == env->current_tc) + env->active_tc.DSPControl = arg1; + else + env->tcs[other_tc].DSPControl = arg1; +} + +/* MIPS MT functions */ +target_ulong helper_dmt(target_ulong arg1) +{ + // TODO + arg1 = 0; + // rt = arg1 + + return arg1; +} + +target_ulong helper_emt(target_ulong arg1) +{ + // TODO + arg1 = 0; + // rt = arg1 + + return arg1; +} + +target_ulong helper_dvpe(target_ulong arg1) +{ + // TODO + arg1 = 0; + // rt = arg1 + + return arg1; +} + +target_ulong helper_evpe(target_ulong arg1) +{ + // TODO + arg1 = 0; + // rt = arg1 + + return arg1; +} +#endif /* !CONFIG_USER_ONLY */ + +void helper_fork(target_ulong arg1, target_ulong arg2) +{ + // arg1 = rt, arg2 = rs + arg1 = 0; + // TODO: store to TC register +} + +target_ulong helper_yield(target_ulong arg1) +{ + if (arg1 < 0) { + /* No scheduling policy implemented. */ + if (arg1 != -2) { + if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && + env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; + helper_raise_exception(EXCP_THREAD); + } + } + } else if (arg1 == 0) { + if (0 /* TODO: TC underflow */) { + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + helper_raise_exception(EXCP_THREAD); + } else { + // TODO: Deallocate TC + } + } else if (arg1 > 0) { + /* Yield qualifier inputs not implemented. */ + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; + helper_raise_exception(EXCP_THREAD); + } + return env->CP0_YQMask; +} + +#ifndef CONFIG_USER_ONLY +/* TLB management */ +void cpu_mips_tlb_flush (CPUState *env, int flush_global) +{ + /* Flush qemu's TLB and discard all shadowed entries. */ + tlb_flush (env, flush_global); + env->tlb->tlb_in_use = env->tlb->nb_tlb; +} + +static void r4k_mips_tlb_flush_extra (CPUState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb->tlb_in_use > first) { + r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); + } +} + +static void r4k_fill_tlb (int idx) +{ + r4k_tlb_t *tlb; + + /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ + tlb = &env->tlb->mmu.r4k.tlb[idx]; + tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + tlb->VPN &= env->SEGMask; +#endif + tlb->ASID = env->CP0_EntryHi & 0xFF; + tlb->PageMask = env->CP0_PageMask; + tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; + tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; + tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; + tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; + tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; + tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; + tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; + tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; +} + +void r4k_helper_tlbwi (void) +{ + int idx; + + idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + + /* Discard cached TLB entries. We could avoid doing this if the + tlbwi is just upgrading access permissions on the current entry; + that might be a further win. */ + r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); + + r4k_invalidate_tlb(env, idx, 0); + r4k_fill_tlb(idx); +} + +void r4k_helper_tlbwr (void) +{ + int r = cpu_mips_get_random(env); + + r4k_invalidate_tlb(env, r, 1); + r4k_fill_tlb(r); +} + +void r4k_helper_tlbp (void) +{ + r4k_tlb_t *tlb; + target_ulong mask; + target_ulong tag; + target_ulong VPN; + uint8_t ASID; + int i; + + ASID = env->CP0_EntryHi & 0xFF; + for (i = 0; i < env->tlb->nb_tlb; i++) { + tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag = env->CP0_EntryHi & ~mask; + VPN = tlb->VPN & ~mask; + /* Check ASID, virtual page number & size */ + if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { + /* TLB match */ + env->CP0_Index = i; + break; + } + } + if (i == env->tlb->nb_tlb) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { + tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag = env->CP0_EntryHi & ~mask; + VPN = tlb->VPN & ~mask; + /* Check ASID, virtual page number & size */ + if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { + r4k_mips_tlb_flush_extra (env, i); + break; + } + } + + env->CP0_Index |= 0x80000000; + } +} + +void r4k_helper_tlbr (void) +{ + r4k_tlb_t *tlb; + uint8_t ASID; + int idx; + + ASID = env->CP0_EntryHi & 0xFF; + idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb = &env->tlb->mmu.r4k.tlb[idx]; + + /* If this will change the current ASID, flush qemu's TLB. */ + if (ASID != tlb->ASID) + cpu_mips_tlb_flush (env, 1); + + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + + env->CP0_EntryHi = tlb->VPN | tlb->ASID; + env->CP0_PageMask = tlb->PageMask; + env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | + (tlb->C0 << 3) | (tlb->PFN[0] >> 6); + env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | + (tlb->C1 << 3) | (tlb->PFN[1] >> 6); +} + +void helper_tlbwi(void) +{ + env->tlb->helper_tlbwi(); +} + +void helper_tlbwr(void) +{ + env->tlb->helper_tlbwr(); +} + +void helper_tlbp(void) +{ + env->tlb->helper_tlbp(); +} + +void helper_tlbr(void) +{ + env->tlb->helper_tlbr(); +} + +/* Specials */ +target_ulong helper_di (void) +{ + target_ulong t0 = env->CP0_Status; + + env->CP0_Status = t0 & ~(1 << CP0St_IE); + cpu_mips_update_irq(env); + + return t0; +} + +target_ulong helper_ei (void) +{ + target_ulong t0 = env->CP0_Status; + + env->CP0_Status = t0 | (1 << CP0St_IE); + cpu_mips_update_irq(env); + + return t0; +} + +static void debug_pre_eret (void) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + if (env->hflags & MIPS_HFLAG_DM) + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + qemu_log("\n"); + } +} + +static void debug_post_eret (void) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + if (env->hflags & MIPS_HFLAG_DM) + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + switch (env->hflags & MIPS_HFLAG_KSU) { + case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; + case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; + case MIPS_HFLAG_KM: qemu_log("\n"); break; + default: cpu_abort(env, "Invalid MMU mode!\n"); break; + } + } +} + +void helper_eret (void) +{ + debug_pre_eret(); + if (env->CP0_Status & (1 << CP0St_ERL)) { + env->active_tc.PC = env->CP0_ErrorEPC; + env->CP0_Status &= ~(1 << CP0St_ERL); + } else { + env->active_tc.PC = env->CP0_EPC; + env->CP0_Status &= ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(); + env->lladdr = 1; +} + +void helper_deret (void) +{ + debug_pre_eret(); + env->active_tc.PC = env->CP0_DEPC; + env->hflags &= MIPS_HFLAG_DM; + compute_hflags(env); + debug_post_eret(); + env->lladdr = 1; +} +#endif /* !CONFIG_USER_ONLY */ + +target_ulong helper_rdhwr_cpunum(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 0))) + return env->CP0_EBase & 0x3ff; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +target_ulong helper_rdhwr_synci_step(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 1))) + return env->SYNCI_Step; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +target_ulong helper_rdhwr_cc(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 2))) + return env->CP0_Count; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +target_ulong helper_rdhwr_ccres(void) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 3))) + return env->CCRes; + else + helper_raise_exception(EXCP_RI); + + return 0; +} + +void helper_pmon (int function) +{ + function /= 2; + switch (function) { + case 2: /* TODO: char inbyte(int waitflag); */ + if (env->active_tc.gpr[4] == 0) + env->active_tc.gpr[2] = -1; + /* Fall through */ + case 11: /* TODO: char inbyte (void); */ + env->active_tc.gpr[2] = -1; + break; + case 3: + case 12: + printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); + break; + case 17: + break; + case 158: + { + unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4]; + printf("%s", fmt); + } + break; + } +} + +void helper_wait (void) +{ + env->halted = 1; + helper_raise_exception(EXCP_HLT); +} + +#if !defined(CONFIG_USER_ONLY) + +static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); + +#define MMUSUFFIX _mmu +#define ALIGNED_ONLY + +#define SHIFT 0 +#include "softmmu_template.h" + +#define SHIFT 1 +#include "softmmu_template.h" + +#define SHIFT 2 +#include "softmmu_template.h" + +#define SHIFT 3 +#include "softmmu_template.h" + +static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) +{ + env->CP0_BadVAddr = addr; + do_restore_state (retaddr); + helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); +} + +void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) +{ + TranslationBlock *tb; + CPUState *saved_env; + unsigned long pc; + int ret; + + /* XXX: hack to restore env in all cases, even if not called from + generated code */ + saved_env = env; + env = cpu_single_env; + ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); + if (ret) { + if (retaddr) { + /* now we have a real cpu fault */ + pc = (unsigned long)retaddr; + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc); + } + } + helper_raise_exception_err(env->exception_index, env->error_code); + } + env = saved_env; +} + +void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, + int unused, int size) +{ + if (is_exec) + helper_raise_exception(EXCP_IBE); + else + helper_raise_exception(EXCP_DBE); +} +/* + * The following functions are address translation helper functions + * for fast memory access in QEMU. + */ +static unsigned long v2p_mmu(target_ulong addr, int is_user) +{ + int index; + target_ulong tlb_addr; + target_phys_addr_t physaddr; + void *retaddr; + + index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); +redo: + tlb_addr = env->tlb_table[is_user][index].addr_read; + if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + physaddr = addr + env->tlb_table[is_user][index].addend; + } else { + /* the page is not in the TLB : fill it */ + retaddr = GETPC(); + tlb_fill(addr, 0, is_user, retaddr); + goto redo; + } + return physaddr; +} + +/* + * translation from virtual address of simulated OS + * to the address of simulation host (not the physical + * address of simulated OS. + */ +target_phys_addr_t v2p(target_ulong ptr, int is_user) +{ + CPUState *saved_env; + int index; + target_ulong addr; + target_phys_addr_t physaddr; + + saved_env = env; + env = cpu_single_env; + addr = ptr; + index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + if (__builtin_expect(env->tlb_table[is_user][index].addr_read != + (addr & TARGET_PAGE_MASK), 0)) { + physaddr = v2p_mmu(addr, is_user); + } else { + physaddr = (target_phys_addr_t)addr + env->tlb_table[is_user][index].addend; + } + env = saved_env; + return physaddr; +} + +/* copy a string from the simulated virtual space to a buffer in QEMU */ +void vstrcpy(target_ulong ptr, char *buf, int max) +{ + char *phys = 0; + unsigned long page = 0; + + if (buf == NULL) return; + + while (max) { + if ((ptr & TARGET_PAGE_MASK) != page) { + phys = (char *)v2p(ptr, 0); + page = ptr & TARGET_PAGE_MASK; + } + *buf = *phys; + if (*phys == '\0') + return; + ptr ++; + buf ++; + phys ++; + max --; + } +} + +#endif /* !CONFIG_USER_ONLY */ + +/* Complex FPU operations which may need stack space. */ + +#define FLOAT_ONE32 make_float32(0x3f8 << 20) +#define FLOAT_ONE64 make_float64(0x3ffULL << 52) +#define FLOAT_TWO32 make_float32(1 << 30) +#define FLOAT_TWO64 make_float64(1ULL << 62) +#define FLOAT_QNAN32 0x7fbfffff +#define FLOAT_QNAN64 0x7ff7ffffffffffffULL +#define FLOAT_SNAN32 0x7fffffff +#define FLOAT_SNAN64 0x7fffffffffffffffULL + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +static unsigned int ieee_rm[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; + +#define RESTORE_ROUNDING_MODE \ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) + +#define RESTORE_FLUSH_MODE \ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); + +target_ulong helper_cfc1 (uint32_t reg) +{ + target_ulong arg1; + + switch (reg) { + case 0: + arg1 = (int32_t)env->active_fpu.fcr0; + break; + case 25: + arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); + break; + case 26: + arg1 = env->active_fpu.fcr31 & 0x0003f07c; + break; + case 28: + arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); + break; + default: + arg1 = (int32_t)env->active_fpu.fcr31; + break; + } + + return arg1; +} + +void helper_ctc1 (target_ulong arg1, uint32_t reg) +{ + switch(reg) { + case 25: + if (arg1 & 0xffffff00) + return; + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | + ((arg1 & 0x1) << 23); + break; + case 26: + if (arg1 & 0x007c0000) + return; + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); + break; + case 28: + if (arg1 & 0x007c0000) + return; + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | + ((arg1 & 0x4) << 22); + break; + case 31: + if (arg1 & 0x007c0000) + return; + env->active_fpu.fcr31 = arg1; + break; + default: + return; + } + /* set rounding mode */ + RESTORE_ROUNDING_MODE; + /* set flush-to-zero mode */ + RESTORE_FLUSH_MODE; + set_float_exception_flags(0, &env->active_fpu.fp_status); + if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) + helper_raise_exception(EXCP_FPE); +} + +static inline char ieee_ex_to_mips(char xcpt) +{ + return (xcpt & float_flag_inexact) >> 5 | + (xcpt & float_flag_underflow) >> 3 | + (xcpt & float_flag_overflow) >> 1 | + (xcpt & float_flag_divbyzero) << 1 | + (xcpt & float_flag_invalid) << 4; +} + +static inline char mips_ex_to_ieee(char xcpt) +{ + return (xcpt & FP_INEXACT) << 5 | + (xcpt & FP_UNDERFLOW) << 3 | + (xcpt & FP_OVERFLOW) << 1 | + (xcpt & FP_DIV0) >> 1 | + (xcpt & FP_INVALID) >> 4; +} + +static inline void update_fcr31(void) +{ + int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); + + SET_FP_CAUSE(env->active_fpu.fcr31, tmp); + if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) + helper_raise_exception(EXCP_FPE); + else + UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); +} + +/* Float support. + Single precition routines have a "s" suffix, double precision a + "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", + paired single lower "pl", paired single upper "pu". */ + +/* unary operations, modifying fp status */ +uint64_t helper_float_sqrt_d(uint64_t fdt0) +{ + return float64_sqrt(fdt0, &env->active_fpu.fp_status); +} + +uint32_t helper_float_sqrt_s(uint32_t fst0) +{ + return float32_sqrt(fst0, &env->active_fpu.fp_status); +} + +uint64_t helper_float_cvtd_s(uint32_t fst0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint64_t helper_float_cvtd_w(uint32_t wt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint64_t helper_float_cvtd_l(uint64_t dt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint64_t helper_float_cvtl_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_cvtl_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_cvtps_pw(uint64_t dt0) +{ + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_cvtpw_ps(uint64_t fdt0) +{ + uint32_t wt2; + uint32_t wth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FLOAT_SNAN32; + wth2 = FLOAT_SNAN32; + } + return ((uint64_t)wth2 << 32) | wt2; +} + +uint32_t helper_float_cvts_d(uint64_t fdt0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint32_t helper_float_cvts_w(uint32_t wt0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint32_t helper_float_cvts_l(uint64_t dt0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint32_t helper_float_cvts_pl(uint32_t wt0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = wt0; + update_fcr31(); + return wt2; +} + +uint32_t helper_float_cvts_pu(uint32_t wth0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = wth0; + update_fcr31(); + return wt2; +} + +uint32_t helper_float_cvtw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_cvtw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_roundl_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_roundl_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_roundw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_roundw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_truncl_d(uint64_t fdt0) +{ + uint64_t dt2; + + dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_truncl_s(uint32_t fst0) +{ + uint64_t dt2; + + dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_truncw_d(uint64_t fdt0) +{ + uint32_t wt2; + + wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_truncw_s(uint32_t fst0) +{ + uint32_t wt2; + + wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_ceill_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_ceill_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_ceilw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_ceilw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint64_t helper_float_floorl_d(uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint64_t helper_float_floorl_s(uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + dt2 = FLOAT_SNAN64; + return dt2; +} + +uint32_t helper_float_floorw_d(uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +uint32_t helper_float_floorw_s(uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); + RESTORE_ROUNDING_MODE; + update_fcr31(); + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + wt2 = FLOAT_SNAN32; + return wt2; +} + +/* unary operations, not modifying fp status */ +#define FLOAT_UNOP(name) \ +uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ +{ \ + return float64_ ## name(fdt0); \ +} \ +uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ +{ \ + return float32_ ## name(fst0); \ +} \ +uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ +{ \ + uint32_t wt0; \ + uint32_t wth0; \ + \ + wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ + wth0 = float32_ ## name(fdt0 >> 32); \ + return ((uint64_t)wth0 << 32) | wt0; \ +} +FLOAT_UNOP(abs) +FLOAT_UNOP(chs) +#undef FLOAT_UNOP + +/* MIPS specific unary operations */ +uint64_t helper_float_recip_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_recip_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_rsqrt_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_rsqrt_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_recip1_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_recip1_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_recip1_ps(uint64_t fdt0) +{ + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_rsqrt1_d(uint64_t fdt0) +{ + uint64_t fdt2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_rsqrt1_s(uint32_t fst0) +{ + uint32_t fst2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) +{ + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); + fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +#define FLOAT_OP(name, p) void helper_float_##name##_##p(void) + +/* binary operations */ +#define FLOAT_BINOP(name) \ +uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ +{ \ + uint64_t dt2; \ + \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ + update_fcr31(); \ + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ + dt2 = FLOAT_QNAN64; \ + return dt2; \ +} \ + \ +uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ +{ \ + uint32_t wt2; \ + \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ + update_fcr31(); \ + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ + wt2 = FLOAT_QNAN32; \ + return wt2; \ +} \ + \ +uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ +{ \ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 = fdt0 >> 32; \ + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 = fdt1 >> 32; \ + uint32_t wt2; \ + uint32_t wth2; \ + \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ + wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ + update_fcr31(); \ + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ + wt2 = FLOAT_QNAN32; \ + wth2 = FLOAT_QNAN32; \ + } \ + return ((uint64_t)wth2 << 32) | wt2; \ +} + +FLOAT_BINOP(add) +FLOAT_BINOP(sub) +FLOAT_BINOP(mul) +FLOAT_BINOP(div) +#undef FLOAT_BINOP + +/* ternary operations */ +#define FLOAT_TERNOP(name1, name2) \ +uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ + return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ +} \ + \ +uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ + uint32_t fst2) \ +{ \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ +} \ + \ +uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 = fdt0 >> 32; \ + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 = fdt1 >> 32; \ + uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ + uint32_t fsth2 = fdt2 >> 32; \ + \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ + return ((uint64_t)fsth2 << 32) | fst2; \ +} + +FLOAT_TERNOP(mul, add) +FLOAT_TERNOP(mul, sub) +#undef FLOAT_TERNOP + +/* negated ternary operations */ +#define FLOAT_NTERNOP(name1, name2) \ +uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ + fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ + return float64_chs(fdt2); \ +} \ + \ +uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ + uint32_t fst2) \ +{ \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ + return float32_chs(fst2); \ +} \ + \ +uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ + uint64_t fdt2) \ +{ \ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 = fdt0 >> 32; \ + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 = fdt1 >> 32; \ + uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ + uint32_t fsth2 = fdt2 >> 32; \ + \ + fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ + fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ + fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ + fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ + fst2 = float32_chs(fst2); \ + fsth2 = float32_chs(fsth2); \ + return ((uint64_t)fsth2 << 32) | fst2; \ +} + +FLOAT_NTERNOP(mul, add) +FLOAT_NTERNOP(mul, sub) +#undef FLOAT_NTERNOP + +/* MIPS specific binary operations */ +uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); + fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); + update_fcr31(); + return fdt2; +} + +uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) +{ + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); + update_fcr31(); + return fst2; +} + +uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); + fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fst1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fst2; + uint32_t fsth2; + + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); + update_fcr31(); + return ((uint64_t)fsth2 << 32) | fst2; +} + +/* compare operations */ +#define FOP_COND_D(op, cond) \ +void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + int c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} \ +void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + int c; \ + fdt0 = float64_abs(fdt0); \ + fdt1 = float64_abs(fdt1); \ + c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} + +static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) +{ + if (float64_is_signaling_nan(a) || + float64_is_signaling_nan(b) || + (sig && (float64_is_any_nan(a) || float64_is_any_nan(b)))) { + float_raise(float_flag_invalid, status); + return 1; + } else if (float64_is_any_nan(a) || float64_is_any_nan(b)) { + return 1; + } else { + return 0; + } +} + +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0)) +FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)) +FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0)) +FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)) +FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) + +#define FOP_COND_S(op, cond) \ +void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +{ \ + int c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} \ +void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +{ \ + int c; \ + fst0 = float32_abs(fst0); \ + fst1 = float32_abs(fst1); \ + c = cond; \ + update_fcr31(); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} + +static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) +{ + if (float32_is_signaling_nan(a) || + float32_is_signaling_nan(b) || + (sig && (float32_is_any_nan(a) || float32_is_any_nan(b)))) { + float_raise(float_flag_invalid, status); + return 1; + } else if (float32_is_any_nan(a) || float32_is_any_nan(b)) { + return 1; + } else { + return 0; + } +} + +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0)) +FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)) +FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0)) +FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)) +FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) +FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) + +#define FOP_COND_PS(op, condl, condh) \ +void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ + uint32_t fsth0 = float32_abs(fdt0 >> 32); \ + uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ + uint32_t fsth1 = float32_abs(fdt1 >> 32); \ + int cl = condl; \ + int ch = condh; \ + \ + update_fcr31(); \ + if (cl) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ + if (ch) \ + SET_FP_COND(cc + 1, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc + 1, env->active_fpu); \ +} \ +void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +{ \ + uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ + uint32_t fsth0 = float32_abs(fdt0 >> 32); \ + uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ + uint32_t fsth1 = float32_abs(fdt1 >> 32); \ + int cl = condl; \ + int ch = condh; \ + \ + update_fcr31(); \ + if (cl) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ + if (ch) \ + SET_FP_COND(cc + 1, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc + 1, env->active_fpu); \ +} + +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0), + (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0)) +FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)) +FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +/* NOTE: the comma operator will make "cond" to eval to false, + * but float*_is_unordered() is still called. */ +FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0), + (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0)) +FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)) +FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), + !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), + float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) diff --git a/target-mips/translate.c b/target-mips/translate.c new file mode 100644 index 0000000..853aafd --- /dev/null +++ b/target-mips/translate.c @@ -0,0 +1,8713 @@ +/* + * MIPS32 emulation for qemu: main translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdarg.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <inttypes.h> + +#include "cpu.h" +#include "exec-all.h" +#include "disas.h" +#include "tcg-op.h" +#include "qemu-common.h" + +#include "helper.h" +#define GEN_HELPER 1 +#include "helper.h" + +//#define MIPS_DEBUG_DISAS +//#define MIPS_DEBUG_SIGN_EXTENSIONS + +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +enum { + /* indirect opcode tables */ + OPC_SPECIAL = (0x00 << 26), + OPC_REGIMM = (0x01 << 26), + OPC_CP0 = (0x10 << 26), + OPC_CP1 = (0x11 << 26), + OPC_CP2 = (0x12 << 26), + OPC_CP3 = (0x13 << 26), + OPC_SPECIAL2 = (0x1C << 26), + OPC_SPECIAL3 = (0x1F << 26), + /* arithmetic with immediate */ + OPC_ADDI = (0x08 << 26), + OPC_ADDIU = (0x09 << 26), + OPC_SLTI = (0x0A << 26), + OPC_SLTIU = (0x0B << 26), + /* logic with immediate */ + OPC_ANDI = (0x0C << 26), + OPC_ORI = (0x0D << 26), + OPC_XORI = (0x0E << 26), + OPC_LUI = (0x0F << 26), + /* arithmetic with immediate */ + OPC_DADDI = (0x18 << 26), + OPC_DADDIU = (0x19 << 26), + /* Jump and branches */ + OPC_J = (0x02 << 26), + OPC_JAL = (0x03 << 26), + OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */ + OPC_BEQL = (0x14 << 26), + OPC_BNE = (0x05 << 26), + OPC_BNEL = (0x15 << 26), + OPC_BLEZ = (0x06 << 26), + OPC_BLEZL = (0x16 << 26), + OPC_BGTZ = (0x07 << 26), + OPC_BGTZL = (0x17 << 26), + OPC_JALX = (0x1D << 26), /* MIPS 16 only */ + /* Load and stores */ + OPC_LDL = (0x1A << 26), + OPC_LDR = (0x1B << 26), + OPC_LB = (0x20 << 26), + OPC_LH = (0x21 << 26), + OPC_LWL = (0x22 << 26), + OPC_LW = (0x23 << 26), + OPC_LBU = (0x24 << 26), + OPC_LHU = (0x25 << 26), + OPC_LWR = (0x26 << 26), + OPC_LWU = (0x27 << 26), + OPC_SB = (0x28 << 26), + OPC_SH = (0x29 << 26), + OPC_SWL = (0x2A << 26), + OPC_SW = (0x2B << 26), + OPC_SDL = (0x2C << 26), + OPC_SDR = (0x2D << 26), + OPC_SWR = (0x2E << 26), + OPC_LL = (0x30 << 26), + OPC_LLD = (0x34 << 26), + OPC_LD = (0x37 << 26), + OPC_SC = (0x38 << 26), + OPC_SCD = (0x3C << 26), + OPC_SD = (0x3F << 26), + /* Floating point load/store */ + OPC_LWC1 = (0x31 << 26), + OPC_LWC2 = (0x32 << 26), + OPC_LDC1 = (0x35 << 26), + OPC_LDC2 = (0x36 << 26), + OPC_SWC1 = (0x39 << 26), + OPC_SWC2 = (0x3A << 26), + OPC_SDC1 = (0x3D << 26), + OPC_SDC2 = (0x3E << 26), + /* MDMX ASE specific */ + OPC_MDMX = (0x1E << 26), + /* Cache and prefetch */ + OPC_CACHE = (0x2F << 26), + OPC_PREF = (0x33 << 26), + /* Reserved major opcode */ + OPC_MAJOR3B_RESERVED = (0x3B << 26), +}; + +/* MIPS special opcodes */ +#define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + /* Shifts */ + OPC_SLL = 0x00 | OPC_SPECIAL, + /* NOP is SLL r0, r0, 0 */ + /* SSNOP is SLL r0, r0, 1 */ + /* EHB is SLL r0, r0, 3 */ + OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ + OPC_SRA = 0x03 | OPC_SPECIAL, + OPC_SLLV = 0x04 | OPC_SPECIAL, + OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ + OPC_SRAV = 0x07 | OPC_SPECIAL, + OPC_DSLLV = 0x14 | OPC_SPECIAL, + OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ + OPC_DSRAV = 0x17 | OPC_SPECIAL, + OPC_DSLL = 0x38 | OPC_SPECIAL, + OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ + OPC_DSRA = 0x3B | OPC_SPECIAL, + OPC_DSLL32 = 0x3C | OPC_SPECIAL, + OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ + OPC_DSRA32 = 0x3F | OPC_SPECIAL, + /* Multiplication / division */ + OPC_MULT = 0x18 | OPC_SPECIAL, + OPC_MULTU = 0x19 | OPC_SPECIAL, + OPC_DIV = 0x1A | OPC_SPECIAL, + OPC_DIVU = 0x1B | OPC_SPECIAL, + OPC_DMULT = 0x1C | OPC_SPECIAL, + OPC_DMULTU = 0x1D | OPC_SPECIAL, + OPC_DDIV = 0x1E | OPC_SPECIAL, + OPC_DDIVU = 0x1F | OPC_SPECIAL, + /* 2 registers arithmetic / logic */ + OPC_ADD = 0x20 | OPC_SPECIAL, + OPC_ADDU = 0x21 | OPC_SPECIAL, + OPC_SUB = 0x22 | OPC_SPECIAL, + OPC_SUBU = 0x23 | OPC_SPECIAL, + OPC_AND = 0x24 | OPC_SPECIAL, + OPC_OR = 0x25 | OPC_SPECIAL, + OPC_XOR = 0x26 | OPC_SPECIAL, + OPC_NOR = 0x27 | OPC_SPECIAL, + OPC_SLT = 0x2A | OPC_SPECIAL, + OPC_SLTU = 0x2B | OPC_SPECIAL, + OPC_DADD = 0x2C | OPC_SPECIAL, + OPC_DADDU = 0x2D | OPC_SPECIAL, + OPC_DSUB = 0x2E | OPC_SPECIAL, + OPC_DSUBU = 0x2F | OPC_SPECIAL, + /* Jumps */ + OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */ + OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ + /* Traps */ + OPC_TGE = 0x30 | OPC_SPECIAL, + OPC_TGEU = 0x31 | OPC_SPECIAL, + OPC_TLT = 0x32 | OPC_SPECIAL, + OPC_TLTU = 0x33 | OPC_SPECIAL, + OPC_TEQ = 0x34 | OPC_SPECIAL, + OPC_TNE = 0x36 | OPC_SPECIAL, + /* HI / LO registers load & stores */ + OPC_MFHI = 0x10 | OPC_SPECIAL, + OPC_MTHI = 0x11 | OPC_SPECIAL, + OPC_MFLO = 0x12 | OPC_SPECIAL, + OPC_MTLO = 0x13 | OPC_SPECIAL, + /* Conditional moves */ + OPC_MOVZ = 0x0A | OPC_SPECIAL, + OPC_MOVN = 0x0B | OPC_SPECIAL, + + OPC_MOVCI = 0x01 | OPC_SPECIAL, + + /* Special */ + OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */ + OPC_SYSCALL = 0x0C | OPC_SPECIAL, + OPC_BREAK = 0x0D | OPC_SPECIAL, + OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */ + OPC_SYNC = 0x0F | OPC_SPECIAL, + + OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL, + OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, + OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, + OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL, + OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL, + OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, + OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, +}; + +/* Multiplication variants of the vr54xx. */ +#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6)) + +enum { + OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, + OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU, + OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT, + OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU, + OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, + OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, + OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT, + OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU, + OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT, + OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU, + OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT, + OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU, + OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, + OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, +}; + +/* REGIMM (rt field) opcodes */ +#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16)) + +enum { + OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, + OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, + OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, + OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, + OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, + OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, + OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, + OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, + OPC_TGEI = (0x08 << 16) | OPC_REGIMM, + OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, + OPC_TLTI = (0x0A << 16) | OPC_REGIMM, + OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, + OPC_TEQI = (0x0C << 16) | OPC_REGIMM, + OPC_TNEI = (0x0E << 16) | OPC_REGIMM, + OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, +}; + +/* Special2 opcodes */ +#define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + /* Multiply & xxx operations */ + OPC_MADD = 0x00 | OPC_SPECIAL2, + OPC_MADDU = 0x01 | OPC_SPECIAL2, + OPC_MUL = 0x02 | OPC_SPECIAL2, + OPC_MSUB = 0x04 | OPC_SPECIAL2, + OPC_MSUBU = 0x05 | OPC_SPECIAL2, + /* Misc */ + OPC_CLZ = 0x20 | OPC_SPECIAL2, + OPC_CLO = 0x21 | OPC_SPECIAL2, + OPC_DCLZ = 0x24 | OPC_SPECIAL2, + OPC_DCLO = 0x25 | OPC_SPECIAL2, + /* Special */ + OPC_SDBBP = 0x3F | OPC_SPECIAL2, +}; + +/* Special3 opcodes */ +#define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + OPC_EXT = 0x00 | OPC_SPECIAL3, + OPC_DEXTM = 0x01 | OPC_SPECIAL3, + OPC_DEXTU = 0x02 | OPC_SPECIAL3, + OPC_DEXT = 0x03 | OPC_SPECIAL3, + OPC_INS = 0x04 | OPC_SPECIAL3, + OPC_DINSM = 0x05 | OPC_SPECIAL3, + OPC_DINSU = 0x06 | OPC_SPECIAL3, + OPC_DINS = 0x07 | OPC_SPECIAL3, + OPC_FORK = 0x08 | OPC_SPECIAL3, + OPC_YIELD = 0x09 | OPC_SPECIAL3, + OPC_BSHFL = 0x20 | OPC_SPECIAL3, + OPC_DBSHFL = 0x24 | OPC_SPECIAL3, + OPC_RDHWR = 0x3B | OPC_SPECIAL3, +}; + +/* BSHFL opcodes */ +#define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) + +enum { + OPC_WSBH = (0x02 << 6) | OPC_BSHFL, + OPC_SEB = (0x10 << 6) | OPC_BSHFL, + OPC_SEH = (0x18 << 6) | OPC_BSHFL, +}; + +/* DBSHFL opcodes */ +#define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) + +enum { + OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, + OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, +}; + +/* Coprocessor 0 (rs field) */ +#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) + +enum { + OPC_MFC0 = (0x00 << 21) | OPC_CP0, + OPC_DMFC0 = (0x01 << 21) | OPC_CP0, + OPC_MTC0 = (0x04 << 21) | OPC_CP0, + OPC_DMTC0 = (0x05 << 21) | OPC_CP0, + OPC_MFTR = (0x08 << 21) | OPC_CP0, + OPC_RDPGPR = (0x0A << 21) | OPC_CP0, + OPC_MFMC0 = (0x0B << 21) | OPC_CP0, + OPC_MTTR = (0x0C << 21) | OPC_CP0, + OPC_WRPGPR = (0x0E << 21) | OPC_CP0, + OPC_C0 = (0x10 << 21) | OPC_CP0, + OPC_C0_FIRST = (0x10 << 21) | OPC_CP0, + OPC_C0_LAST = (0x1F << 21) | OPC_CP0, +}; + +/* MFMC0 opcodes */ +#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF) + +enum { + OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, + OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, + OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, + OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, + OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, + OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, +}; + +/* Coprocessor 0 (with rs == C0) */ +#define MASK_C0(op) MASK_CP0(op) | (op & 0x3F) + +enum { + OPC_TLBR = 0x01 | OPC_C0, + OPC_TLBWI = 0x02 | OPC_C0, + OPC_TLBWR = 0x06 | OPC_C0, + OPC_TLBP = 0x08 | OPC_C0, + OPC_RFE = 0x10 | OPC_C0, + OPC_ERET = 0x18 | OPC_C0, + OPC_DERET = 0x1F | OPC_C0, + OPC_WAIT = 0x20 | OPC_C0, +}; + +/* Coprocessor 1 (rs field) */ +#define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) + +enum { + OPC_MFC1 = (0x00 << 21) | OPC_CP1, + OPC_DMFC1 = (0x01 << 21) | OPC_CP1, + OPC_CFC1 = (0x02 << 21) | OPC_CP1, + OPC_MFHC1 = (0x03 << 21) | OPC_CP1, + OPC_MTC1 = (0x04 << 21) | OPC_CP1, + OPC_DMTC1 = (0x05 << 21) | OPC_CP1, + OPC_CTC1 = (0x06 << 21) | OPC_CP1, + OPC_MTHC1 = (0x07 << 21) | OPC_CP1, + OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ + OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1, + OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1, + OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */ + OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */ + OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */ + OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */ + OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */ + OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */ + OPC_PS_FMT = (0x16 << 21) | OPC_CP1, /* 22: fmt=paired single fp */ +}; + +#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F) +#define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16)) + +enum { + OPC_BC1F = (0x00 << 16) | OPC_BC1, + OPC_BC1T = (0x01 << 16) | OPC_BC1, + OPC_BC1FL = (0x02 << 16) | OPC_BC1, + OPC_BC1TL = (0x03 << 16) | OPC_BC1, +}; + +enum { + OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2, + OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2, +}; + +enum { + OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4, + OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, +}; + +#define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) + +enum { + OPC_MFC2 = (0x00 << 21) | OPC_CP2, + OPC_DMFC2 = (0x01 << 21) | OPC_CP2, + OPC_CFC2 = (0x02 << 21) | OPC_CP2, + OPC_MFHC2 = (0x03 << 21) | OPC_CP2, + OPC_MTC2 = (0x04 << 21) | OPC_CP2, + OPC_DMTC2 = (0x05 << 21) | OPC_CP2, + OPC_CTC2 = (0x06 << 21) | OPC_CP2, + OPC_MTHC2 = (0x07 << 21) | OPC_CP2, + OPC_BC2 = (0x08 << 21) | OPC_CP2, +}; + +#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F) + +enum { + OPC_LWXC1 = 0x00 | OPC_CP3, + OPC_LDXC1 = 0x01 | OPC_CP3, + OPC_LUXC1 = 0x05 | OPC_CP3, + OPC_SWXC1 = 0x08 | OPC_CP3, + OPC_SDXC1 = 0x09 | OPC_CP3, + OPC_SUXC1 = 0x0D | OPC_CP3, + OPC_PREFX = 0x0F | OPC_CP3, + OPC_ALNV_PS = 0x1E | OPC_CP3, + OPC_MADD_S = 0x20 | OPC_CP3, + OPC_MADD_D = 0x21 | OPC_CP3, + OPC_MADD_PS = 0x26 | OPC_CP3, + OPC_MSUB_S = 0x28 | OPC_CP3, + OPC_MSUB_D = 0x29 | OPC_CP3, + OPC_MSUB_PS = 0x2E | OPC_CP3, + OPC_NMADD_S = 0x30 | OPC_CP3, + OPC_NMADD_D = 0x31 | OPC_CP3, + OPC_NMADD_PS= 0x36 | OPC_CP3, + OPC_NMSUB_S = 0x38 | OPC_CP3, + OPC_NMSUB_D = 0x39 | OPC_CP3, + OPC_NMSUB_PS= 0x3E | OPC_CP3, +}; + +/* global register indices */ +static TCGv_ptr cpu_env; +static TCGv cpu_gpr[32], cpu_PC; +static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC]; +static TCGv cpu_dspctrl, btarget, bcond; +static TCGv_i32 hflags; +static TCGv_i32 fpu_fcr0, fpu_fcr31; + +#include "gen-icount.h" + +#define gen_helper_0i(name, arg) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg); \ + gen_helper_##name(helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_1i(name, arg1, arg2) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ + gen_helper_##name(arg1, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_2i(name, arg1, arg2, arg3) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ + gen_helper_##name(arg1, arg2, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \ + TCGv_i32 helper_tmp = tcg_const_i32(arg4); \ + gen_helper_##name(arg1, arg2, arg3, helper_tmp); \ + tcg_temp_free_i32(helper_tmp); \ + } while(0) + +typedef struct DisasContext { + struct TranslationBlock *tb; + target_ulong pc, saved_pc; + uint32_t opcode; + int singlestep_enabled; + /* Routine used to access memory */ + int mem_idx; + uint32_t hflags, saved_hflags; + int bstate; + target_ulong btarget; +} DisasContext; + +enum { + BS_NONE = 0, /* We go out of the TB without reaching a branch or an + * exception condition */ + BS_STOP = 1, /* We want to stop translation for any reason */ + BS_BRANCH = 2, /* We reached a branch condition */ + BS_EXCP = 3, /* We reached an exception condition */ +}; + +static const char *regnames[] = + { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; + +static const char *regnames_HI[] = + { "HI0", "HI1", "HI2", "HI3", }; + +static const char *regnames_LO[] = + { "LO0", "LO1", "LO2", "LO3", }; + +static const char *regnames_ACX[] = + { "ACX0", "ACX1", "ACX2", "ACX3", }; + +static const char *fregnames[] = + { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; + +#ifdef MIPS_DEBUG_DISAS +#define MIPS_DEBUG(fmt, ...) \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, \ + TARGET_FMT_lx ": %08x " fmt "\n", \ + ctx->pc, ctx->opcode , ## __VA_ARGS__) +#define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) +#else +#define MIPS_DEBUG(fmt, ...) do { } while(0) +#define LOG_DISAS(...) do { } while (0) +#endif + +#define MIPS_INVAL(op) \ +do { \ + MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \ + ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ +} while (0) + +/* General purpose registers moves. */ +static inline void gen_load_gpr (TCGv t, int reg) +{ + if (reg == 0) + tcg_gen_movi_tl(t, 0); + else + tcg_gen_mov_tl(t, cpu_gpr[reg]); +} + +static inline void gen_store_gpr (TCGv t, int reg) +{ + if (reg != 0) + tcg_gen_mov_tl(cpu_gpr[reg], t); +} + +/* Moves to/from ACX register. */ +static inline void gen_load_ACX (TCGv t, int reg) +{ + tcg_gen_mov_tl(t, cpu_ACX[reg]); +} + +static inline void gen_store_ACX (TCGv t, int reg) +{ + tcg_gen_mov_tl(cpu_ACX[reg], t); +} + +/* Moves to/from shadow registers. */ +static inline void gen_load_srsgpr (int from, int to) +{ + TCGv t0 = tcg_temp_new(); + + if (from == 0) + tcg_gen_movi_tl(t0, 0); + else { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_ptr addr = tcg_temp_new_ptr(); + + tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); + tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); + tcg_gen_andi_i32(t2, t2, 0xf); + tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); + tcg_gen_ext_i32_ptr(addr, t2); + tcg_gen_add_ptr(addr, cpu_env, addr); + + tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); + tcg_temp_free_ptr(addr); + tcg_temp_free_i32(t2); + } + gen_store_gpr(t0, to); + tcg_temp_free(t0); +} + +static inline void gen_store_srsgpr (int from, int to) +{ + if (to != 0) { + TCGv t0 = tcg_temp_new(); + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_ptr addr = tcg_temp_new_ptr(); + + gen_load_gpr(t0, from); + tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); + tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); + tcg_gen_andi_i32(t2, t2, 0xf); + tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); + tcg_gen_ext_i32_ptr(addr, t2); + tcg_gen_add_ptr(addr, cpu_env, addr); + + tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); + tcg_temp_free_ptr(addr); + tcg_temp_free_i32(t2); + tcg_temp_free(t0); + } +} + +/* Floating point register moves. */ +static inline void gen_load_fpr32 (TCGv_i32 t, int reg) +{ + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); +} + +static inline void gen_store_fpr32 (TCGv_i32 t, int reg) +{ + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); +} + +static inline void gen_load_fpr32h (TCGv_i32 t, int reg) +{ + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); +} + +static inline void gen_store_fpr32h (TCGv_i32 t, int reg) +{ + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); +} + +static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) +{ + if (ctx->hflags & MIPS_HFLAG_F64) { + tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + gen_load_fpr32(t0, reg & ~1); + gen_load_fpr32(t1, reg | 1); + tcg_gen_concat_i32_i64(t, t0, t1); + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + } +} + +static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) +{ + if (ctx->hflags & MIPS_HFLAG_F64) { + tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(t1, t); + gen_store_fpr32(t1, reg & ~1); + tcg_gen_shri_i64(t0, t, 32); + tcg_gen_trunc_i64_i32(t1, t0); + gen_store_fpr32(t1, reg | 1); + tcg_temp_free_i32(t1); + tcg_temp_free_i64(t0); + } +} + +static inline int get_fp_bit (int cc) +{ + if (cc) + return 24 + cc; + else + return 23; +} + +#define FOP_CONDS(type, fmt, bits) \ +static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \ + TCGv_i##bits b, int cc) \ +{ \ + switch (n) { \ + case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\ + case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\ + case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\ + case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\ + case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\ + case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\ + case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\ + case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\ + case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\ + case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\ + case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\ + case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\ + case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\ + case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\ + case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\ + case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\ + default: abort(); \ + } \ +} + +FOP_CONDS(, d, 64) +FOP_CONDS(abs, d, 64) +FOP_CONDS(, s, 32) +FOP_CONDS(abs, s, 32) +FOP_CONDS(, ps, 64) +FOP_CONDS(abs, ps, 64) +#undef FOP_CONDS + +/* Tests */ +#define OP_COND(name, cond) \ +static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \ +{ \ + int l1 = gen_new_label(); \ + int l2 = gen_new_label(); \ + \ + tcg_gen_brcond_tl(cond, t0, t1, l1); \ + tcg_gen_movi_tl(ret, 0); \ + tcg_gen_br(l2); \ + gen_set_label(l1); \ + tcg_gen_movi_tl(ret, 1); \ + gen_set_label(l2); \ +} +OP_COND(eq, TCG_COND_EQ); +OP_COND(ne, TCG_COND_NE); +OP_COND(ge, TCG_COND_GE); +OP_COND(geu, TCG_COND_GEU); +OP_COND(lt, TCG_COND_LT); +OP_COND(ltu, TCG_COND_LTU); +#undef OP_COND + +#define OP_CONDI(name, cond) \ +static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \ +{ \ + int l1 = gen_new_label(); \ + int l2 = gen_new_label(); \ + \ + tcg_gen_brcondi_tl(cond, t0, val, l1); \ + tcg_gen_movi_tl(ret, 0); \ + tcg_gen_br(l2); \ + gen_set_label(l1); \ + tcg_gen_movi_tl(ret, 1); \ + gen_set_label(l2); \ +} +OP_CONDI(lti, TCG_COND_LT); +OP_CONDI(ltiu, TCG_COND_LTU); +#undef OP_CONDI + +#define OP_CONDZ(name, cond) \ +static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \ +{ \ + int l1 = gen_new_label(); \ + int l2 = gen_new_label(); \ + \ + tcg_gen_brcondi_tl(cond, t0, 0, l1); \ + tcg_gen_movi_tl(ret, 0); \ + tcg_gen_br(l2); \ + gen_set_label(l1); \ + tcg_gen_movi_tl(ret, 1); \ + gen_set_label(l2); \ +} +OP_CONDZ(gez, TCG_COND_GE); +OP_CONDZ(gtz, TCG_COND_GT); +OP_CONDZ(lez, TCG_COND_LE); +OP_CONDZ(ltz, TCG_COND_LT); +#undef OP_CONDZ + +static inline void gen_save_pc(target_ulong pc) +{ + tcg_gen_movi_tl(cpu_PC, pc); +} + +static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) +{ + LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); + if (do_save_pc && ctx->pc != ctx->saved_pc) { + gen_save_pc(ctx->pc); + ctx->saved_pc = ctx->pc; + } + if (ctx->hflags != ctx->saved_hflags) { + tcg_gen_movi_i32(hflags, ctx->hflags); + ctx->saved_hflags = ctx->hflags; + switch (ctx->hflags & MIPS_HFLAG_BMASK) { + case MIPS_HFLAG_BR: + break; + case MIPS_HFLAG_BC: + case MIPS_HFLAG_BL: + case MIPS_HFLAG_B: + tcg_gen_movi_tl(btarget, ctx->btarget); + break; + } + } +} + +static inline void restore_cpu_state (CPUState *env, DisasContext *ctx) +{ + ctx->saved_hflags = ctx->hflags; + switch (ctx->hflags & MIPS_HFLAG_BMASK) { + case MIPS_HFLAG_BR: + break; + case MIPS_HFLAG_BC: + case MIPS_HFLAG_BL: + case MIPS_HFLAG_B: + ctx->btarget = env->btarget; + break; + } +} + +static inline void +generate_exception_err (DisasContext *ctx, int excp, int err) +{ + TCGv_i32 texcp = tcg_const_i32(excp); + TCGv_i32 terr = tcg_const_i32(err); + save_cpu_state(ctx, 1); + gen_helper_raise_exception_err(texcp, terr); + tcg_temp_free_i32(terr); + tcg_temp_free_i32(texcp); +} + +static inline void +generate_exception (DisasContext *ctx, int excp) +{ + save_cpu_state(ctx, 1); + gen_helper_0i(raise_exception, excp); +} + +/* Addresses computation */ +static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) +{ + tcg_gen_add_tl(ret, arg0, arg1); + +#if defined(TARGET_MIPS64) + /* For compatibility with 32-bit code, data reference in user mode + with Status_UX = 0 should be casted to 32-bit and sign extended. + See the MIPS64 PRA manual, section 4.10. */ + if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && + !(ctx->hflags & MIPS_HFLAG_UX)) { + tcg_gen_ext32s_i64(ret, ret); + } +#endif +} + +static inline void check_cp0_enabled(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) + generate_exception_err(ctx, EXCP_CpU, 0); +} + +static inline void check_cp1_enabled(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) + generate_exception_err(ctx, EXCP_CpU, 1); +} + +/* Verify that the processor is running with COP1X instructions enabled. + This is associated with the nabla symbol in the MIPS32 and MIPS64 + opcode tables. */ + +static inline void check_cop1x(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) + generate_exception(ctx, EXCP_RI); +} + +/* Verify that the processor is running with 64-bit floating-point + operations enabled. */ + +static inline void check_cp1_64bitmode(DisasContext *ctx) +{ + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) + generate_exception(ctx, EXCP_RI); +} + +/* + * Verify if floating point register is valid; an operation is not defined + * if bit 0 of any register specification is set and the FR bit in the + * Status register equals zero, since the register numbers specify an + * even-odd pair of adjacent coprocessor general registers. When the FR bit + * in the Status register equals one, both even and odd register numbers + * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. + * + * Multiple 64 bit wide registers can be checked by calling + * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); + */ +static inline void check_cp1_registers(DisasContext *ctx, int regs) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) + generate_exception(ctx, EXCP_RI); +} + +/* This code generates a "reserved instruction" exception if the + CPU does not support the instruction set corresponding to flags. */ +static inline void check_insn(CPUState *env, DisasContext *ctx, int flags) +{ + if (unlikely(!(env->insn_flags & flags))) + generate_exception(ctx, EXCP_RI); +} + +/* This code generates a "reserved instruction" exception if 64-bit + instructions are not enabled. */ +static inline void check_mips_64(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) + generate_exception(ctx, EXCP_RI); +} + +/* load/store instructions. */ +#define OP_LD(insn,fname) \ +static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ +{ \ + tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ +} +OP_LD(lb,ld8s); +OP_LD(lbu,ld8u); +OP_LD(lh,ld16s); +OP_LD(lhu,ld16u); +OP_LD(lw,ld32s); +#if defined(TARGET_MIPS64) +OP_LD(lwu,ld32u); +OP_LD(ld,ld64); +#endif +#undef OP_LD + +#define OP_ST(insn,fname) \ +static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \ +{ \ + tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \ +} +OP_ST(sb,st8); +OP_ST(sh,st16); +OP_ST(sw,st32); +#if defined(TARGET_MIPS64) +OP_ST(sd,st64); +#endif +#undef OP_ST + +#ifdef CONFIG_USER_ONLY +#define OP_LD_ATOMIC(insn,fname) \ +static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ +{ \ + TCGv t0 = tcg_temp_new(); \ + tcg_gen_mov_tl(t0, arg1); \ + tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ + tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \ + tcg_temp_free(t0); \ +} +#else +#define OP_LD_ATOMIC(insn,fname) \ +static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ +{ \ + gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \ +} +#endif +OP_LD_ATOMIC(ll,ld32s); +#if defined(TARGET_MIPS64) +OP_LD_ATOMIC(lld,ld64); +#endif +#undef OP_LD_ATOMIC + +#ifdef CONFIG_USER_ONLY +#define OP_ST_ATOMIC(insn,fname,ldname,almask) \ +static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ +{ \ + TCGv t0 = tcg_temp_new(); \ + int l1 = gen_new_label(); \ + int l2 = gen_new_label(); \ + \ + tcg_gen_andi_tl(t0, arg2, almask); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \ + tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ + generate_exception(ctx, EXCP_AdES); \ + gen_set_label(l1); \ + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \ + tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \ + tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \ + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \ + tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \ + gen_helper_0i(raise_exception, EXCP_SC); \ + gen_set_label(l2); \ + tcg_gen_movi_tl(t0, 0); \ + gen_store_gpr(t0, rt); \ + tcg_temp_free(t0); \ +} +#else +#define OP_ST_ATOMIC(insn,fname,ldname,almask) \ +static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \ +{ \ + TCGv t0 = tcg_temp_new(); \ + gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \ + gen_store_gpr(t0, rt); \ + tcg_temp_free(t0); \ +} +#endif +OP_ST_ATOMIC(sc,st32,ld32s,0x3); +#if defined(TARGET_MIPS64) +OP_ST_ATOMIC(scd,st64,ld64,0x7); +#endif +#undef OP_ST_ATOMIC + +/* Load and store */ +static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, + int base, int16_t offset) +{ + const char *opn = "ldst"; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + if (base == 0) { + tcg_gen_movi_tl(t0, offset); + } else if (offset == 0) { + gen_load_gpr(t0, base); + } else { + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + } + /* Don't do NOP if destination is zero: we must perform the actual + memory access. */ + switch (opc) { +#if defined(TARGET_MIPS64) + case OPC_LWU: + save_cpu_state(ctx, 0); + op_ldst_lwu(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lwu"; + break; + case OPC_LD: + save_cpu_state(ctx, 0); + op_ldst_ld(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "ld"; + break; + case OPC_LLD: + save_cpu_state(ctx, 0); + op_ldst_lld(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lld"; + break; + case OPC_SD: + save_cpu_state(ctx, 0); + gen_load_gpr(t1, rt); + op_ldst_sd(t1, t0, ctx); + opn = "sd"; + break; + case OPC_LDL: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "ldl"; + break; + case OPC_SDL: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_2i(sdl, t1, t0, ctx->mem_idx); + opn = "sdl"; + break; + case OPC_LDR: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "ldr"; + break; + case OPC_SDR: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_2i(sdr, t1, t0, ctx->mem_idx); + opn = "sdr"; + break; +#endif + case OPC_LW: + save_cpu_state(ctx, 0); + op_ldst_lw(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lw"; + break; + case OPC_SW: + save_cpu_state(ctx, 0); + gen_load_gpr(t1, rt); + op_ldst_sw(t1, t0, ctx); + opn = "sw"; + break; + case OPC_LH: + save_cpu_state(ctx, 0); + op_ldst_lh(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lh"; + break; + case OPC_SH: + save_cpu_state(ctx, 0); + gen_load_gpr(t1, rt); + op_ldst_sh(t1, t0, ctx); + opn = "sh"; + break; + case OPC_LHU: + save_cpu_state(ctx, 0); + op_ldst_lhu(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lhu"; + break; + case OPC_LB: + save_cpu_state(ctx, 0); + op_ldst_lb(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lb"; + break; + case OPC_SB: + save_cpu_state(ctx, 0); + gen_load_gpr(t1, rt); + op_ldst_sb(t1, t0, ctx); + opn = "sb"; + break; + case OPC_LBU: + save_cpu_state(ctx, 0); + op_ldst_lbu(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "lbu"; + break; + case OPC_LWL: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "lwl"; + break; + case OPC_SWL: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_2i(swl, t1, t0, ctx->mem_idx); + opn = "swr"; + break; + case OPC_LWR: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx); + gen_store_gpr(t1, rt); + opn = "lwr"; + break; + case OPC_SWR: + save_cpu_state(ctx, 1); + gen_load_gpr(t1, rt); + gen_helper_2i(swr, t1, t0, ctx->mem_idx); + opn = "swr"; + break; + case OPC_LL: + save_cpu_state(ctx, 1); + op_ldst_ll(t0, t0, ctx); + gen_store_gpr(t0, rt); + opn = "ll"; + break; + } + MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* Store conditional */ +static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, + int base, int16_t offset) +{ + const char *opn = "st_cond"; + TCGv t0, t1; + + t0 = tcg_temp_local_new(); + + if (base == 0) { + tcg_gen_movi_tl(t0, offset); + } else if (offset == 0) { + gen_load_gpr(t0, base); + } else { + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + } + /* Don't do NOP if destination is zero: we must perform the actual + memory access. */ + + t1 = tcg_temp_local_new(); + gen_load_gpr(t1, rt); + switch (opc) { +#if defined(TARGET_MIPS64) + case OPC_SCD: + save_cpu_state(ctx, 0); + op_ldst_scd(t1, t0, rt, ctx); + opn = "scd"; + break; +#endif + case OPC_SC: + save_cpu_state(ctx, 1); + op_ldst_sc(t1, t0, rt, ctx); + opn = "sc"; + break; + } + MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); + tcg_temp_free(t1); + tcg_temp_free(t0); +} + +/* Load and store */ +static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, + int base, int16_t offset) +{ + const char *opn = "flt_ldst"; + TCGv t0 = tcg_temp_new(); + + if (base == 0) { + tcg_gen_movi_tl(t0, offset); + } else if (offset == 0) { + gen_load_gpr(t0, base); + } else { + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + } + /* Don't do NOP if destination is zero: we must perform the actual + memory access. */ + switch (opc) { + case OPC_LWC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, ft); + tcg_temp_free_i32(fp0); + } + opn = "lwc1"; + break; + case OPC_SWC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv t1 = tcg_temp_new(); + + gen_load_fpr32(fp0, ft); + tcg_gen_extu_i32_tl(t1, fp0); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); + tcg_temp_free(t1); + tcg_temp_free_i32(fp0); + } + opn = "swc1"; + break; + case OPC_LDC1: + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); + gen_store_fpr64(ctx, fp0, ft); + tcg_temp_free_i64(fp0); + } + opn = "ldc1"; + break; + case OPC_SDC1: + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, ft); + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); + tcg_temp_free_i64(fp0); + } + opn = "sdc1"; + break; + default: + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + goto out; + } + MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]); + out: + tcg_temp_free(t0); +} + +/* Arithmetic with immediate operand */ +static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) +{ + target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ + const char *opn = "imm arith"; + + if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { + /* If no destination, treat it as a NOP. + For addi, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + switch (opc) { + case OPC_ADDI: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + tcg_gen_addi_tl(t0, t1, uimm); + tcg_gen_ext32s_tl(t0, t0); + + tcg_gen_xori_tl(t1, t1, ~uimm); + tcg_gen_xori_tl(t2, t0, uimm); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + tcg_gen_ext32s_tl(t0, t0); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + opn = "addi"; + break; + case OPC_ADDIU: + if (rs != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } else { + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } + opn = "addiu"; + break; +#if defined(TARGET_MIPS64) + case OPC_DADDI: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + tcg_gen_addi_tl(t0, t1, uimm); + + tcg_gen_xori_tl(t1, t1, ~uimm); + tcg_gen_xori_tl(t2, t0, uimm); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + opn = "daddi"; + break; + case OPC_DADDIU: + if (rs != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + } else { + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } + opn = "daddiu"; + break; +#endif + } + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); +} + +/* Logic with immediate operand */ +static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) +{ + target_ulong uimm; + const char *opn = "imm logic"; + + if (rt == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + uimm = (uint16_t)imm; + switch (opc) { + case OPC_ANDI: + if (likely(rs != 0)) + tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + else + tcg_gen_movi_tl(cpu_gpr[rt], 0); + opn = "andi"; + break; + case OPC_ORI: + if (rs != 0) + tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + else + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + opn = "ori"; + break; + case OPC_XORI: + if (likely(rs != 0)) + tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); + else + tcg_gen_movi_tl(cpu_gpr[rt], uimm); + opn = "xori"; + break; + case OPC_LUI: + tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); + opn = "lui"; + break; + } + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); +} + +/* Set on less than with immediate operand */ +static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) +{ + target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ + const char *opn = "imm arith"; + TCGv t0; + + if (rt == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + switch (opc) { + case OPC_SLTI: + gen_op_lti(cpu_gpr[rt], t0, uimm); + opn = "slti"; + break; + case OPC_SLTIU: + gen_op_ltiu(cpu_gpr[rt], t0, uimm); + opn = "sltiu"; + break; + } + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); + tcg_temp_free(t0); +} + +/* Shifts with immediate operand */ +static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) +{ + target_ulong uimm = ((uint16_t)imm) & 0x1f; + const char *opn = "imm shift"; + TCGv t0; + + if (rt == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + switch (opc) { + case OPC_SLL: + tcg_gen_shli_tl(t0, t0, uimm); + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); + opn = "sll"; + break; + case OPC_SRA: + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); + opn = "sra"; + break; + case OPC_SRL: + switch ((ctx->opcode >> 21) & 0x1f) { + case 0: + if (uimm != 0) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); + } else { + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); + } + opn = "srl"; + break; + case 1: + /* rotr is decoded as srl on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + if (uimm != 0) { + TCGv_i32 t1 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t1, t0); + tcg_gen_rotri_i32(t1, t1, uimm); + tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); + tcg_temp_free_i32(t1); + } else { + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); + } + opn = "rotr"; + } else { + if (uimm != 0) { + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); + } else { + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); + } + opn = "srl"; + } + break; + default: + MIPS_INVAL("invalid srl flag"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#if defined(TARGET_MIPS64) + case OPC_DSLL: + tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); + opn = "dsll"; + break; + case OPC_DSRA: + tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); + opn = "dsra"; + break; + case OPC_DSRL: + switch ((ctx->opcode >> 21) & 0x1f) { + case 0: + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); + opn = "dsrl"; + break; + case 1: + /* drotr is decoded as dsrl on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + if (uimm != 0) { + tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); + } else { + tcg_gen_mov_tl(cpu_gpr[rt], t0); + } + opn = "drotr"; + } else { + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); + opn = "dsrl"; + } + break; + default: + MIPS_INVAL("invalid dsrl flag"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_DSLL32: + tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "dsll32"; + break; + case OPC_DSRA32: + tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "dsra32"; + break; + case OPC_DSRL32: + switch ((ctx->opcode >> 21) & 0x1f) { + case 0: + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "dsrl32"; + break; + case 1: + /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "drotr32"; + } else { + tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); + opn = "dsrl32"; + } + break; + default: + MIPS_INVAL("invalid dsrl32 flag"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#endif + } + MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); + tcg_temp_free(t0); +} + +/* Arithmetic */ +static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "arith"; + + if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB + && opc != OPC_DADD && opc != OPC_DSUB) { + /* If no destination, treat it as a NOP. + For add & sub, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + + switch (opc) { + case OPC_ADD: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_add_tl(t0, t1, t2); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_xor_tl(t1, t1, t2); + tcg_gen_not_tl(t1, t1); + tcg_gen_xor_tl(t2, t0, t2); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "add"; + break; + case OPC_ADDU: + if (rs != 0 && rt != 0) { + tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "addu"; + break; + case OPC_SUB: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_sub_tl(t0, t1, t2); + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_xor_tl(t2, t1, t2); + tcg_gen_xor_tl(t1, t0, t1); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of different sign, first operand and result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "sub"; + break; + case OPC_SUBU: + if (rs != 0 && rt != 0) { + tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else if (rs == 0 && rt != 0) { + tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "subu"; + break; +#if defined(TARGET_MIPS64) + case OPC_DADD: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_add_tl(t0, t1, t2); + tcg_gen_xor_tl(t1, t1, t2); + tcg_gen_not_tl(t1, t1); + tcg_gen_xor_tl(t2, t0, t2); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of same sign, result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "dadd"; + break; + case OPC_DADDU: + if (rs != 0 && rt != 0) { + tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "daddu"; + break; + case OPC_DSUB: + { + TCGv t0 = tcg_temp_local_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + int l1 = gen_new_label(); + + gen_load_gpr(t1, rs); + gen_load_gpr(t2, rt); + tcg_gen_sub_tl(t0, t1, t2); + tcg_gen_xor_tl(t2, t1, t2); + tcg_gen_xor_tl(t1, t0, t1); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); + tcg_temp_free(t1); + /* operands of different sign, first operand and result different sign */ + generate_exception(ctx, EXCP_OVERFLOW); + gen_set_label(l1); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + opn = "dsub"; + break; + case OPC_DSUBU: + if (rs != 0 && rt != 0) { + tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "dsubu"; + break; +#endif + case OPC_MUL: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "mul"; + break; + } + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); +} + +/* Conditional move */ +static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt) +{ + const char *opn = "cond move"; + int l1; + + if (rd == 0) { + /* If no destination, treat it as a NOP. + For add & sub, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + + l1 = gen_new_label(); + switch (opc) { + case OPC_MOVN: + if (likely(rt != 0)) + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1); + else + tcg_gen_br(l1); + opn = "movn"; + break; + case OPC_MOVZ: + if (likely(rt != 0)) + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1); + opn = "movz"; + break; + } + if (rs != 0) + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + else + tcg_gen_movi_tl(cpu_gpr[rd], 0); + gen_set_label(l1); + + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); +} + +/* Logic */ +static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt) +{ + const char *opn = "logic"; + + if (rd == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + switch (opc) { + case OPC_AND: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "and"; + break; + case OPC_NOR: + if (rs != 0 && rt != 0) { + tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); + } + opn = "nor"; + break; + case OPC_OR: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "or"; + break; + case OPC_XOR: + if (likely(rs != 0 && rt != 0)) { + tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); + } else if (rs == 0 && rt != 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); + } else if (rs != 0 && rt == 0) { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } else { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } + opn = "xor"; + break; + } + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); +} + +/* Set on lower than */ +static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt) +{ + const char *opn = "slt"; + TCGv t0, t1; + + if (rd == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + switch (opc) { + case OPC_SLT: + gen_op_lt(cpu_gpr[rd], t0, t1); + opn = "slt"; + break; + case OPC_SLTU: + gen_op_ltu(cpu_gpr[rd], t0, t1); + opn = "sltu"; + break; + } + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* Shifts */ +static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "shifts"; + TCGv t0, t1; + + if (rd == 0) { + /* If no destination, treat it as a NOP. + For add & sub, we must generate the overflow exception when needed. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + switch (opc) { + case OPC_SLLV: + tcg_gen_andi_tl(t0, t0, 0x1f); + tcg_gen_shl_tl(t0, t1, t0); + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + opn = "sllv"; + break; + case OPC_SRAV: + tcg_gen_ext32s_tl(t1, t1); + tcg_gen_andi_tl(t0, t0, 0x1f); + tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); + opn = "srav"; + break; + case OPC_SRLV: + switch ((ctx->opcode >> 6) & 0x1f) { + case 0: + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_andi_tl(t0, t0, 0x1f); + tcg_gen_shr_tl(t0, t1, t0); + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + opn = "srlv"; + break; + case 1: + /* rotrv is decoded as srlv on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_andi_i32(t2, t2, 0x1f); + tcg_gen_rotr_i32(t2, t3, t2); + tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + opn = "rotrv"; + } else { + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_andi_tl(t0, t0, 0x1f); + tcg_gen_shr_tl(t0, t1, t0); + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + opn = "srlv"; + } + break; + default: + MIPS_INVAL("invalid srlv flag"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#if defined(TARGET_MIPS64) + case OPC_DSLLV: + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); + opn = "dsllv"; + break; + case OPC_DSRAV: + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); + opn = "dsrav"; + break; + case OPC_DSRLV: + switch ((ctx->opcode >> 6) & 0x1f) { + case 0: + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); + opn = "dsrlv"; + break; + case 1: + /* drotrv is decoded as dsrlv on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); + opn = "drotrv"; + } else { + tcg_gen_andi_tl(t0, t0, 0x3f); + tcg_gen_shr_tl(t0, t1, t0); + opn = "dsrlv"; + } + break; + default: + MIPS_INVAL("invalid dsrlv flag"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#endif + } + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* Arithmetic on HI/LO registers */ +static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) +{ + const char *opn = "hilo"; + + if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + switch (opc) { + case OPC_MFHI: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]); + opn = "mfhi"; + break; + case OPC_MFLO: + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]); + opn = "mflo"; + break; + case OPC_MTHI: + if (reg != 0) + tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]); + else + tcg_gen_movi_tl(cpu_HI[0], 0); + opn = "mthi"; + break; + case OPC_MTLO: + if (reg != 0) + tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]); + else + tcg_gen_movi_tl(cpu_LO[0], 0); + opn = "mtlo"; + break; + } + MIPS_DEBUG("%s %s", opn, regnames[reg]); +} + +static void gen_muldiv (DisasContext *ctx, uint32_t opc, + int rs, int rt) +{ + const char *opn = "mul/div"; + TCGv t0, t1; + + switch (opc) { + case OPC_DIV: + case OPC_DIVU: +#if defined(TARGET_MIPS64) + case OPC_DDIV: + case OPC_DDIVU: +#endif + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + break; + default: + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + break; + } + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + switch (opc) { + case OPC_DIV: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); + + tcg_gen_mov_tl(cpu_LO[0], t0); + tcg_gen_movi_tl(cpu_HI[0], 0); + tcg_gen_br(l1); + gen_set_label(l2); + tcg_gen_div_tl(cpu_LO[0], t0, t1); + tcg_gen_rem_tl(cpu_HI[0], t0, t1); + tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); + tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); + gen_set_label(l1); + } + opn = "div"; + break; + case OPC_DIVU: + { + int l1 = gen_new_label(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_divu_tl(cpu_LO[0], t0, t1); + tcg_gen_remu_tl(cpu_HI[0], t0, t1); + tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); + tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); + gen_set_label(l1); + } + opn = "divu"; + break; + case OPC_MULT: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "mult"; + break; + case OPC_MULTU: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "multu"; + break; +#if defined(TARGET_MIPS64) + case OPC_DDIV: + { + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); + tcg_gen_mov_tl(cpu_LO[0], t0); + tcg_gen_movi_tl(cpu_HI[0], 0); + tcg_gen_br(l1); + gen_set_label(l2); + tcg_gen_div_i64(cpu_LO[0], t0, t1); + tcg_gen_rem_i64(cpu_HI[0], t0, t1); + gen_set_label(l1); + } + opn = "ddiv"; + break; + case OPC_DDIVU: + { + int l1 = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_divu_i64(cpu_LO[0], t0, t1); + tcg_gen_remu_i64(cpu_HI[0], t0, t1); + gen_set_label(l1); + } + opn = "ddivu"; + break; + case OPC_DMULT: + gen_helper_dmult(t0, t1); + opn = "dmult"; + break; + case OPC_DMULTU: + gen_helper_dmultu(t0, t1); + opn = "dmultu"; + break; +#endif + case OPC_MADD: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "madd"; + break; + case OPC_MADDU: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "maddu"; + break; + case OPC_MSUB: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_sub_i64(t2, t3, t2); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "msub"; + break; + case OPC_MSUBU: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_sub_i64(t2, t3, t2); + tcg_temp_free_i64(t3); + tcg_gen_trunc_i64_tl(t0, t2); + tcg_gen_shri_i64(t2, t2, 32); + tcg_gen_trunc_i64_tl(t1, t2); + tcg_temp_free_i64(t2); + tcg_gen_ext32s_tl(cpu_LO[0], t0); + tcg_gen_ext32s_tl(cpu_HI[0], t1); + } + opn = "msubu"; + break; + default: + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + goto out; + } + MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "mul vr54xx"; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case OPC_VR54XX_MULS: + gen_helper_muls(t0, t0, t1); + opn = "muls"; + break; + case OPC_VR54XX_MULSU: + gen_helper_mulsu(t0, t0, t1); + opn = "mulsu"; + break; + case OPC_VR54XX_MACC: + gen_helper_macc(t0, t0, t1); + opn = "macc"; + break; + case OPC_VR54XX_MACCU: + gen_helper_maccu(t0, t0, t1); + opn = "maccu"; + break; + case OPC_VR54XX_MSAC: + gen_helper_msac(t0, t0, t1); + opn = "msac"; + break; + case OPC_VR54XX_MSACU: + gen_helper_msacu(t0, t0, t1); + opn = "msacu"; + break; + case OPC_VR54XX_MULHI: + gen_helper_mulhi(t0, t0, t1); + opn = "mulhi"; + break; + case OPC_VR54XX_MULHIU: + gen_helper_mulhiu(t0, t0, t1); + opn = "mulhiu"; + break; + case OPC_VR54XX_MULSHI: + gen_helper_mulshi(t0, t0, t1); + opn = "mulshi"; + break; + case OPC_VR54XX_MULSHIU: + gen_helper_mulshiu(t0, t0, t1); + opn = "mulshiu"; + break; + case OPC_VR54XX_MACCHI: + gen_helper_macchi(t0, t0, t1); + opn = "macchi"; + break; + case OPC_VR54XX_MACCHIU: + gen_helper_macchiu(t0, t0, t1); + opn = "macchiu"; + break; + case OPC_VR54XX_MSACHI: + gen_helper_msachi(t0, t0, t1); + opn = "msachi"; + break; + case OPC_VR54XX_MSACHIU: + gen_helper_msachiu(t0, t0, t1); + opn = "msachiu"; + break; + default: + MIPS_INVAL("mul vr54xx"); + generate_exception(ctx, EXCP_RI); + goto out; + } + gen_store_gpr(t0, rd); + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); + + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_cl (DisasContext *ctx, uint32_t opc, + int rd, int rs) +{ + const char *opn = "CLx"; + TCGv t0; + + if (rd == 0) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + t0 = tcg_temp_new(); + gen_load_gpr(t0, rs); + switch (opc) { + case OPC_CLO: + gen_helper_clo(cpu_gpr[rd], t0); + opn = "clo"; + break; + case OPC_CLZ: + gen_helper_clz(cpu_gpr[rd], t0); + opn = "clz"; + break; +#if defined(TARGET_MIPS64) + case OPC_DCLO: + gen_helper_dclo(cpu_gpr[rd], t0); + opn = "dclo"; + break; + case OPC_DCLZ: + gen_helper_dclz(cpu_gpr[rd], t0); + opn = "dclz"; + break; +#endif + } + MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); + tcg_temp_free(t0); +} + +/* Traps */ +static void gen_trap (DisasContext *ctx, uint32_t opc, + int rs, int rt, int16_t imm) +{ + int cond; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + cond = 0; + /* Load needed operands */ + switch (opc) { + case OPC_TEQ: + case OPC_TGE: + case OPC_TGEU: + case OPC_TLT: + case OPC_TLTU: + case OPC_TNE: + /* Compare two registers */ + if (rs != rt) { + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + cond = 1; + } + break; + case OPC_TEQI: + case OPC_TGEI: + case OPC_TGEIU: + case OPC_TLTI: + case OPC_TLTIU: + case OPC_TNEI: + /* Compare register to immediate */ + if (rs != 0 || imm != 0) { + gen_load_gpr(t0, rs); + tcg_gen_movi_tl(t1, (int32_t)imm); + cond = 1; + } + break; + } + if (cond == 0) { + switch (opc) { + case OPC_TEQ: /* rs == rs */ + case OPC_TEQI: /* r0 == 0 */ + case OPC_TGE: /* rs >= rs */ + case OPC_TGEI: /* r0 >= 0 */ + case OPC_TGEU: /* rs >= rs unsigned */ + case OPC_TGEIU: /* r0 >= 0 unsigned */ + /* Always trap */ + generate_exception(ctx, EXCP_TRAP); + break; + case OPC_TLT: /* rs < rs */ + case OPC_TLTI: /* r0 < 0 */ + case OPC_TLTU: /* rs < rs unsigned */ + case OPC_TLTIU: /* r0 < 0 unsigned */ + case OPC_TNE: /* rs != rs */ + case OPC_TNEI: /* r0 != 0 */ + /* Never trap: treat as NOP. */ + break; + } + } else { + int l1 = gen_new_label(); + + switch (opc) { + case OPC_TEQ: + case OPC_TEQI: + tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); + break; + case OPC_TGE: + case OPC_TGEI: + tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1); + break; + case OPC_TGEU: + case OPC_TGEIU: + tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1); + break; + case OPC_TLT: + case OPC_TLTI: + tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); + break; + case OPC_TLTU: + case OPC_TLTIU: + tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); + break; + case OPC_TNE: + case OPC_TNEI: + tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1); + break; + } + generate_exception(ctx, EXCP_TRAP); + gen_set_label(l1); + } + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) +{ + TranslationBlock *tb; + tb = ctx->tb; + if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && + likely(!ctx->singlestep_enabled)) { + tcg_gen_goto_tb(n); + gen_save_pc(dest); + tcg_gen_exit_tb((long)tb + n); + } else { + gen_save_pc(dest); + if (ctx->singlestep_enabled) { + save_cpu_state(ctx, 0); + gen_helper_0i(raise_exception, EXCP_DEBUG); + } + tcg_gen_exit_tb(0); + } +} + +/* Branches (before delay slot) */ +static void gen_compute_branch (DisasContext *ctx, uint32_t opc, + int rs, int rt, int32_t offset) +{ + target_ulong btgt = -1; + int blink = 0; + int bcond_compute = 0; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { +#ifdef MIPS_DEBUG_DISAS + LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc); +#endif + generate_exception(ctx, EXCP_RI); + goto out; + } + + /* Load needed operands */ + switch (opc) { + case OPC_BEQ: + case OPC_BEQL: + case OPC_BNE: + case OPC_BNEL: + /* Compare two registers */ + if (rs != rt) { + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + bcond_compute = 1; + } + btgt = ctx->pc + 4 + offset; + break; + case OPC_BGEZ: + case OPC_BGEZAL: + case OPC_BGEZALL: + case OPC_BGEZL: + case OPC_BGTZ: + case OPC_BGTZL: + case OPC_BLEZ: + case OPC_BLEZL: + case OPC_BLTZ: + case OPC_BLTZAL: + case OPC_BLTZALL: + case OPC_BLTZL: + /* Compare to zero */ + if (rs != 0) { + gen_load_gpr(t0, rs); + bcond_compute = 1; + } + btgt = ctx->pc + 4 + offset; + break; + case OPC_J: + case OPC_JAL: + /* Jump to immediate */ + btgt = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset; + break; + case OPC_JR: + case OPC_JALR: + /* Jump to register */ + if (offset != 0 && offset != 16) { + /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the + others are reserved. */ + MIPS_INVAL("jump hint"); + generate_exception(ctx, EXCP_RI); + goto out; + } + gen_load_gpr(btarget, rs); + break; + default: + MIPS_INVAL("branch/jump"); + generate_exception(ctx, EXCP_RI); + goto out; + } + if (bcond_compute == 0) { + /* No condition to be computed */ + switch (opc) { + case OPC_BEQ: /* rx == rx */ + case OPC_BEQL: /* rx == rx likely */ + case OPC_BGEZ: /* 0 >= 0 */ + case OPC_BGEZL: /* 0 >= 0 likely */ + case OPC_BLEZ: /* 0 <= 0 */ + case OPC_BLEZL: /* 0 <= 0 likely */ + /* Always take */ + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("balways"); + break; + case OPC_BGEZAL: /* 0 >= 0 */ + case OPC_BGEZALL: /* 0 >= 0 likely */ + /* Always take and link */ + blink = 31; + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("balways and link"); + break; + case OPC_BNE: /* rx != rx */ + case OPC_BGTZ: /* 0 > 0 */ + case OPC_BLTZ: /* 0 < 0 */ + /* Treat as NOP. */ + MIPS_DEBUG("bnever (NOP)"); + goto out; + case OPC_BLTZAL: /* 0 < 0 */ + tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8); + MIPS_DEBUG("bnever and link"); + goto out; + case OPC_BLTZALL: /* 0 < 0 likely */ + tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8); + /* Skip the instruction in the delay slot */ + MIPS_DEBUG("bnever, link and skip"); + ctx->pc += 4; + goto out; + case OPC_BNEL: /* rx != rx likely */ + case OPC_BGTZL: /* 0 > 0 likely */ + case OPC_BLTZL: /* 0 < 0 likely */ + /* Skip the instruction in the delay slot */ + MIPS_DEBUG("bnever and skip"); + ctx->pc += 4; + goto out; + case OPC_J: + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("j " TARGET_FMT_lx, btgt); + break; + case OPC_JAL: + blink = 31; + ctx->hflags |= MIPS_HFLAG_B; + MIPS_DEBUG("jal " TARGET_FMT_lx, btgt); + break; + case OPC_JR: + ctx->hflags |= MIPS_HFLAG_BR; + MIPS_DEBUG("jr %s", regnames[rs]); + break; + case OPC_JALR: + blink = rt; + ctx->hflags |= MIPS_HFLAG_BR; + MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]); + break; + default: + MIPS_INVAL("branch/jump"); + generate_exception(ctx, EXCP_RI); + goto out; + } + } else { + switch (opc) { + case OPC_BEQ: + gen_op_eq(bcond, t0, t1); + MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto not_likely; + case OPC_BEQL: + gen_op_eq(bcond, t0, t1); + MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto likely; + case OPC_BNE: + gen_op_ne(bcond, t0, t1); + MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto not_likely; + case OPC_BNEL: + gen_op_ne(bcond, t0, t1); + MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx, + regnames[rs], regnames[rt], btgt); + goto likely; + case OPC_BGEZ: + gen_op_gez(bcond, t0); + MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BGEZL: + gen_op_gez(bcond, t0); + MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BGEZAL: + gen_op_gez(bcond, t0); + MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt); + blink = 31; + goto not_likely; + case OPC_BGEZALL: + gen_op_gez(bcond, t0); + blink = 31; + MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BGTZ: + gen_op_gtz(bcond, t0); + MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BGTZL: + gen_op_gtz(bcond, t0); + MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BLEZ: + gen_op_lez(bcond, t0); + MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BLEZL: + gen_op_lez(bcond, t0); + MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BLTZ: + gen_op_ltz(bcond, t0); + MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto not_likely; + case OPC_BLTZL: + gen_op_ltz(bcond, t0); + MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); + goto likely; + case OPC_BLTZAL: + gen_op_ltz(bcond, t0); + blink = 31; + MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt); + not_likely: + ctx->hflags |= MIPS_HFLAG_BC; + break; + case OPC_BLTZALL: + gen_op_ltz(bcond, t0); + blink = 31; + MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt); + likely: + ctx->hflags |= MIPS_HFLAG_BL; + break; + default: + MIPS_INVAL("conditional branch/jump"); + generate_exception(ctx, EXCP_RI); + goto out; + } + } + MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx, + blink, ctx->hflags, btgt); + + ctx->btarget = btgt; + if (blink > 0) { + tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + 8); + } + + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* special3 bitfield operations */ +static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, + int rs, int lsb, int msb) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + target_ulong mask; + + gen_load_gpr(t1, rs); + switch (opc) { + case OPC_EXT: + if (lsb + msb > 31) + goto fail; + tcg_gen_shri_tl(t0, t1, lsb); + if (msb != 31) { + tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); + } else { + tcg_gen_ext32s_tl(t0, t0); + } + break; +#if defined(TARGET_MIPS64) + case OPC_DEXTM: + tcg_gen_shri_tl(t0, t1, lsb); + if (msb != 31) { + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1); + } + break; + case OPC_DEXTU: + tcg_gen_shri_tl(t0, t1, lsb + 32); + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); + break; + case OPC_DEXT: + tcg_gen_shri_tl(t0, t1, lsb); + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); + break; +#endif + case OPC_INS: + if (lsb > msb) + goto fail; + mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb; + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_ext32s_tl(t0, t0); + break; +#if defined(TARGET_MIPS64) + case OPC_DINSM: + if (lsb > msb) + goto fail; + mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb; + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + break; + case OPC_DINSU: + if (lsb > msb) + goto fail; + mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32); + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb + 32); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + break; + case OPC_DINS: + if (lsb > msb) + goto fail; + gen_load_gpr(t0, rt); + mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb; + gen_load_gpr(t0, rt); + tcg_gen_andi_tl(t0, t0, ~mask); + tcg_gen_shli_tl(t1, t1, lsb); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_or_tl(t0, t0, t1); + break; +#endif + default: +fail: + MIPS_INVAL("bitops"); + generate_exception(ctx, EXCP_RI); + tcg_temp_free(t0); + tcg_temp_free(t1); + return; + } + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) +{ + TCGv t0; + + if (rd == 0) { + /* If no destination, treat it as a NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + gen_load_gpr(t0, rt); + switch (op2) { + case OPC_WSBH: + { + TCGv t1 = tcg_temp_new(); + + tcg_gen_shri_tl(t1, t0, 8); + tcg_gen_andi_tl(t1, t1, 0x00FF00FF); + tcg_gen_shli_tl(t0, t0, 8); + tcg_gen_andi_tl(t0, t0, ~0x00FF00FF); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + } + break; + case OPC_SEB: + tcg_gen_ext8s_tl(cpu_gpr[rd], t0); + break; + case OPC_SEH: + tcg_gen_ext16s_tl(cpu_gpr[rd], t0); + break; +#if defined(TARGET_MIPS64) + case OPC_DSBH: + { + TCGv t1 = tcg_temp_new(); + + tcg_gen_shri_tl(t1, t0, 8); + tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL); + tcg_gen_shli_tl(t0, t0, 8); + tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL); + tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t1); + } + break; + case OPC_DSHD: + { + TCGv t1 = tcg_temp_new(); + + tcg_gen_shri_tl(t1, t0, 16); + tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL); + tcg_gen_shli_tl(t0, t0, 16); + tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL); + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_shri_tl(t1, t0, 32); + tcg_gen_shli_tl(t0, t0, 32); + tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t1); + } + break; +#endif + default: + MIPS_INVAL("bsfhl"); + generate_exception(ctx, EXCP_RI); + tcg_temp_free(t0); + return; + } + tcg_temp_free(t0); +} + +#ifndef CONFIG_USER_ONLY +/* CP0 (MMU and control) */ +static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_ld_i32(t0, cpu_env, off); + tcg_gen_ext_i32_tl(arg, t0); + tcg_temp_free_i32(t0); +} + +static inline void gen_mfc0_load64 (TCGv arg, target_ulong off) +{ + tcg_gen_ld_tl(arg, cpu_env, off); + tcg_gen_ext32s_tl(arg, arg); +} + +static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t0, arg); + tcg_gen_st_i32(t0, cpu_env, off); + tcg_temp_free_i32(t0); +} + +static inline void gen_mtc0_store64 (TCGv arg, target_ulong off) +{ + tcg_gen_ext32s_tl(arg, arg); + tcg_gen_st_tl(arg, cpu_env, off); +} + +static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS32); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index)); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf0(arg); + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf1(arg); + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + gen_helper_mfc0_random(arg); + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl)); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0)); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1)); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask)); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt)); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context)); + tcg_gen_ext32s_tl(arg, arg); + rn = "Context"; + break; + case 1: +// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask)); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain)); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired)); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0)); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2)); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3)); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna)); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr)); + tcg_gen_ext32s_tl(arg, arg); + rn = "BadVAddr"; + break; + default: + goto die; + } + break; + case 9: + switch (sel) { + case 0: + /* Mark as an IO operation because we read the time. */ + if (use_icount) + gen_io_start(); + gen_helper_mfc0_count(arg); + if (use_icount) { + gen_io_end(); + ctx->bstate = BS_STOP; + } + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 10: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare)); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 12: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl)); + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap)); + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause)); + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); + tcg_gen_ext32s_tl(arg, arg); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid)); + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase)); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0)); + rn = "Config"; + break; + case 1: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1)); + rn = "Config1"; + break; + case 2: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2)); + rn = "Config2"; + break; + case 3: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); + rn = "Config3"; + break; + /* 4,5 are reserved */ + /* 6,7 are implementation dependent */ + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6)); + rn = "Config6"; + break; + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7)); + rn = "Config7"; + break; + default: + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_mfc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mfc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ...7: + gen_helper_1i(mfc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: +#if defined(TARGET_MIPS64) + check_insn(env, ctx, ISA_MIPS3); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext)); + tcg_gen_ext32s_tl(arg, arg); + rn = "XContext"; + break; +#endif + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask)); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "'Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mfc0_debug(arg); /* EJTAG support */ + rn = "Debug"; + break; + case 1: +// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */ + rn = "TraceControl"; +// break; + case 2: +// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */ + rn = "TraceControl2"; +// break; + case 3: +// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */ + rn = "UserTraceData"; +// break; + case 4: +// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */ + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); + tcg_gen_ext32s_tl(arg, arg); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0)); + rn = "Performance0"; + break; + case 1: +// gen_helper_mfc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_mfc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_mfc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_mfc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_mfc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_mfc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_mfc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "ECC"; + break; + case 27: + switch (sel) { + case 0 ... 3: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo)); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo)); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi)); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi)); + rn = "DataHi"; + break; + default: + goto die; + } + break; + case 30: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); + tcg_gen_ext32s_tl(arg, arg); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + break; + default: + goto die; + } + LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); + return; + +die: + LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} + +static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS32); + + if (use_icount) + gen_io_start(); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_helper_mtc0_index(arg); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + /* ignored */ + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpecontrol(arg); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf0(arg); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf1(arg); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_yqmask(arg); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeopt(arg); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo0(arg); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo1(arg); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + gen_helper_mtc0_context(arg); + rn = "Context"; + break; + case 1: +// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_helper_mtc0_pagemask(arg); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_pagegrain(arg); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_helper_mtc0_wired(arg); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf0(arg); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf1(arg); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf2(arg); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf3(arg); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf4(arg); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_hwrena(arg); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + /* ignored */ + rn = "BadVAddr"; + break; + case 9: + switch (sel) { + case 0: + gen_helper_mtc0_count(arg); + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 10: + switch (sel) { + case 0: + gen_helper_mtc0_entryhi(arg); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_helper_mtc0_compare(arg); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 12: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_mtc0_status(arg); + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_intctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap)); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_mtc0_cause(arg); + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC)); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + /* ignored */ + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_ebase(arg); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_helper_mtc0_config0(arg); + rn = "Config"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 1: + /* ignored, read only */ + rn = "Config1"; + break; + case 2: + gen_helper_mtc0_config2(arg); + rn = "Config2"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 3: + /* ignored, read only */ + rn = "Config3"; + break; + /* 4,5 are reserved */ + /* 6,7 are implementation dependent */ + case 6: + /* ignored */ + rn = "Config6"; + break; + case 7: + /* ignored */ + rn = "Config7"; + break; + default: + rn = "Invalid config selector"; + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_mtc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: +#if defined(TARGET_MIPS64) + check_insn(env, ctx, ISA_MIPS3); + gen_helper_mtc0_xcontext(arg); + rn = "XContext"; + break; +#endif + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_helper_mtc0_framemask(arg); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + /* ignored */ + rn = "Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mtc0_debug(arg); /* EJTAG support */ + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Debug"; + break; + case 1: +// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ + rn = "TraceControl"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// break; + case 2: +// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ + rn = "TraceControl2"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// break; + case 3: + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ + rn = "UserTraceData"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; +// break; + case 4: +// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC)); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_helper_mtc0_performance0(arg); + rn = "Performance0"; + break; + case 1: +// gen_helper_mtc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_mtc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_mtc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_mtc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_mtc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_mtc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_mtc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + /* ignored */ + rn = "ECC"; + break; + case 27: + switch (sel) { + case 0 ... 3: + /* ignored */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taglo(arg); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datalo(arg); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taghi(arg); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datahi(arg); + rn = "DataHi"; + break; + default: + rn = "invalid sel"; + goto die; + } + break; + case 30: + switch (sel) { + case 0: + gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC)); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + default: + goto die; + } + LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); + /* For simplicity assume that all writes can cause interrupts. */ + if (use_icount) { + gen_io_end(); + ctx->bstate = BS_STOP; + } + return; + +die: + LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} + +#if defined(TARGET_MIPS64) +static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS64); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index)); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf0(arg); + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_mvpconf1(arg); + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + gen_helper_mfc0_random(arg); + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl)); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0)); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1)); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask)); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt)); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0)); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mfc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_dmfc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1)); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context)); + rn = "Context"; + break; + case 1: +// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask)); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain)); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired)); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0)); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2)); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3)); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna)); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr)); + rn = "BadVAddr"; + break; + default: + goto die; + } + break; + case 9: + switch (sel) { + case 0: + /* Mark as an IO operation because we read the time. */ + if (use_icount) + gen_io_start(); + gen_helper_mfc0_count(arg); + if (use_icount) { + gen_io_end(); + ctx->bstate = BS_STOP; + } + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 10: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi)); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare)); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + break; + case 12: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl)); + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap)); + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause)); + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid)); + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase)); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0)); + rn = "Config"; + break; + case 1: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1)); + rn = "Config1"; + break; + case 2: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2)); + rn = "Config2"; + break; + case 3: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); + rn = "Config3"; + break; + /* 6,7 are implementation dependent */ + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6)); + rn = "Config6"; + break; + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7)); + rn = "Config7"; + break; + default: + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_dmfc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(dmfc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mfc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS3); + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext)); + rn = "XContext"; + break; + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask)); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "'Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mfc0_debug(arg); /* EJTAG support */ + rn = "Debug"; + break; + case 1: +// gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */ + rn = "TraceControl"; +// break; + case 2: +// gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */ + rn = "TraceControl2"; +// break; + case 3: +// gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */ + rn = "UserTraceData"; +// break; + case 4: +// gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */ + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0)); + rn = "Performance0"; + break; + case 1: +// gen_helper_dmfc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_dmfc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_dmfc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_dmfc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_dmfc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_dmfc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_dmfc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "ECC"; + break; + case 27: + switch (sel) { + /* ignored */ + case 0 ... 3: + tcg_gen_movi_tl(arg, 0); /* unimplemented */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo)); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo)); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi)); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi)); + rn = "DataHi"; + break; + default: + goto die; + } + break; + case 30: + switch (sel) { + case 0: + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + break; + default: + goto die; + } + LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); + return; + +die: + LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} + +static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) +{ + const char *rn = "invalid"; + + if (sel != 0) + check_insn(env, ctx, ISA_MIPS64); + + if (use_icount) + gen_io_start(); + + switch (reg) { + case 0: + switch (sel) { + case 0: + gen_helper_mtc0_index(arg); + rn = "Index"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_mvpcontrol(arg); + rn = "MVPControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + /* ignored */ + rn = "MVPConf1"; + break; + default: + goto die; + } + break; + case 1: + switch (sel) { + case 0: + /* ignored */ + rn = "Random"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpecontrol(arg); + rn = "VPEControl"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf0(arg); + rn = "VPEConf0"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeconf1(arg); + rn = "VPEConf1"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_yqmask(arg); + rn = "YQMask"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule)); + rn = "VPESchedule"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); + rn = "VPEScheFBack"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_vpeopt(arg); + rn = "VPEOpt"; + break; + default: + goto die; + } + break; + case 2: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo0(arg); + rn = "EntryLo0"; + break; + case 1: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcstatus(arg); + rn = "TCStatus"; + break; + case 2: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcbind(arg); + rn = "TCBind"; + break; + case 3: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcrestart(arg); + rn = "TCRestart"; + break; + case 4: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tchalt(arg); + rn = "TCHalt"; + break; + case 5: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tccontext(arg); + rn = "TCContext"; + break; + case 6: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschedule(arg); + rn = "TCSchedule"; + break; + case 7: + check_insn(env, ctx, ASE_MT); + gen_helper_mtc0_tcschefback(arg); + rn = "TCScheFBack"; + break; + default: + goto die; + } + break; + case 3: + switch (sel) { + case 0: + gen_helper_mtc0_entrylo1(arg); + rn = "EntryLo1"; + break; + default: + goto die; + } + break; + case 4: + switch (sel) { + case 0: + gen_helper_mtc0_context(arg); + rn = "Context"; + break; + case 1: +// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ + rn = "ContextConfig"; +// break; + default: + goto die; + } + break; + case 5: + switch (sel) { + case 0: + gen_helper_mtc0_pagemask(arg); + rn = "PageMask"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_pagegrain(arg); + rn = "PageGrain"; + break; + default: + goto die; + } + break; + case 6: + switch (sel) { + case 0: + gen_helper_mtc0_wired(arg); + rn = "Wired"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf0(arg); + rn = "SRSConf0"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf1(arg); + rn = "SRSConf1"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf2(arg); + rn = "SRSConf2"; + break; + case 4: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf3(arg); + rn = "SRSConf3"; + break; + case 5: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsconf4(arg); + rn = "SRSConf4"; + break; + default: + goto die; + } + break; + case 7: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_hwrena(arg); + rn = "HWREna"; + break; + default: + goto die; + } + break; + case 8: + /* ignored */ + rn = "BadVAddr"; + break; + case 9: + switch (sel) { + case 0: + gen_helper_mtc0_count(arg); + rn = "Count"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 10: + switch (sel) { + case 0: + gen_helper_mtc0_entryhi(arg); + rn = "EntryHi"; + break; + default: + goto die; + } + break; + case 11: + switch (sel) { + case 0: + gen_helper_mtc0_compare(arg); + rn = "Compare"; + break; + /* 6,7 are implementation dependent */ + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 12: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_mtc0_status(arg); + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Status"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_intctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "IntCtl"; + break; + case 2: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_srsctl(arg); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSCtl"; + break; + case 3: + check_insn(env, ctx, ISA_MIPS32R2); + gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap)); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "SRSMap"; + break; + default: + goto die; + } + break; + case 13: + switch (sel) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_mtc0_cause(arg); + rn = "Cause"; + break; + default: + goto die; + } + break; + case 14: + switch (sel) { + case 0: + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); + rn = "EPC"; + break; + default: + goto die; + } + break; + case 15: + switch (sel) { + case 0: + /* ignored */ + rn = "PRid"; + break; + case 1: + check_insn(env, ctx, ISA_MIPS32R2); + gen_helper_mtc0_ebase(arg); + rn = "EBase"; + break; + default: + goto die; + } + break; + case 16: + switch (sel) { + case 0: + gen_helper_mtc0_config0(arg); + rn = "Config"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 1: + /* ignored, read only */ + rn = "Config1"; + break; + case 2: + gen_helper_mtc0_config2(arg); + rn = "Config2"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case 3: + /* ignored */ + rn = "Config3"; + break; + /* 6,7 are implementation dependent */ + default: + rn = "Invalid config selector"; + goto die; + } + break; + case 17: + switch (sel) { + case 0: + gen_helper_mtc0_lladdr(arg); + rn = "LLAddr"; + break; + default: + goto die; + } + break; + case 18: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchlo, arg, sel); + rn = "WatchLo"; + break; + default: + goto die; + } + break; + case 19: + switch (sel) { + case 0 ... 7: + gen_helper_1i(mtc0_watchhi, arg, sel); + rn = "WatchHi"; + break; + default: + goto die; + } + break; + case 20: + switch (sel) { + case 0: + check_insn(env, ctx, ISA_MIPS3); + gen_helper_mtc0_xcontext(arg); + rn = "XContext"; + break; + default: + goto die; + } + break; + case 21: + /* Officially reserved, but sel 0 is used for R1x000 framemask */ + switch (sel) { + case 0: + gen_helper_mtc0_framemask(arg); + rn = "Framemask"; + break; + default: + goto die; + } + break; + case 22: + /* ignored */ + rn = "Diagnostic"; /* implementation dependent */ + break; + case 23: + switch (sel) { + case 0: + gen_helper_mtc0_debug(arg); /* EJTAG support */ + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; + rn = "Debug"; + break; + case 1: +// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceControl"; +// break; + case 2: +// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceControl2"; +// break; + case 3: +// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "UserTraceData"; +// break; + case 4: +// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + rn = "TraceBPC"; +// break; + default: + goto die; + } + break; + case 24: + switch (sel) { + case 0: + /* EJTAG support */ + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); + rn = "DEPC"; + break; + default: + goto die; + } + break; + case 25: + switch (sel) { + case 0: + gen_helper_mtc0_performance0(arg); + rn = "Performance0"; + break; + case 1: +// gen_helper_mtc0_performance1(arg); + rn = "Performance1"; +// break; + case 2: +// gen_helper_mtc0_performance2(arg); + rn = "Performance2"; +// break; + case 3: +// gen_helper_mtc0_performance3(arg); + rn = "Performance3"; +// break; + case 4: +// gen_helper_mtc0_performance4(arg); + rn = "Performance4"; +// break; + case 5: +// gen_helper_mtc0_performance5(arg); + rn = "Performance5"; +// break; + case 6: +// gen_helper_mtc0_performance6(arg); + rn = "Performance6"; +// break; + case 7: +// gen_helper_mtc0_performance7(arg); + rn = "Performance7"; +// break; + default: + goto die; + } + break; + case 26: + /* ignored */ + rn = "ECC"; + break; + case 27: + switch (sel) { + case 0 ... 3: + /* ignored */ + rn = "CacheErr"; + break; + default: + goto die; + } + break; + case 28: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taglo(arg); + rn = "TagLo"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datalo(arg); + rn = "DataLo"; + break; + default: + goto die; + } + break; + case 29: + switch (sel) { + case 0: + case 2: + case 4: + case 6: + gen_helper_mtc0_taghi(arg); + rn = "TagHi"; + break; + case 1: + case 3: + case 5: + case 7: + gen_helper_mtc0_datahi(arg); + rn = "DataHi"; + break; + default: + rn = "invalid sel"; + goto die; + } + break; + case 30: + switch (sel) { + case 0: + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); + rn = "ErrorEPC"; + break; + default: + goto die; + } + break; + case 31: + switch (sel) { + case 0: + /* EJTAG support */ + gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE)); + rn = "DESAVE"; + break; + default: + goto die; + } + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + default: + goto die; + } + LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); + /* For simplicity assume that all writes can cause interrupts. */ + if (use_icount) { + gen_io_end(); + ctx->bstate = BS_STOP; + } + return; + +die: + LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); + generate_exception(ctx, EXCP_RI); +} +#endif /* TARGET_MIPS64 */ + +static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, + int u, int sel, int h) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + TCGv t0 = tcg_temp_local_new(); + + if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && + ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != + (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) + tcg_gen_movi_tl(t0, -1); + else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > + (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + tcg_gen_movi_tl(t0, -1); + else if (u == 0) { + switch (rt) { + case 2: + switch (sel) { + case 1: + gen_helper_mftc0_tcstatus(t0); + break; + case 2: + gen_helper_mftc0_tcbind(t0); + break; + case 3: + gen_helper_mftc0_tcrestart(t0); + break; + case 4: + gen_helper_mftc0_tchalt(t0); + break; + case 5: + gen_helper_mftc0_tccontext(t0); + break; + case 6: + gen_helper_mftc0_tcschedule(t0); + break; + case 7: + gen_helper_mftc0_tcschefback(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + break; + case 10: + switch (sel) { + case 0: + gen_helper_mftc0_entryhi(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + case 12: + switch (sel) { + case 0: + gen_helper_mftc0_status(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + case 23: + switch (sel) { + case 0: + gen_helper_mftc0_debug(t0); + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + break; + } + break; + default: + gen_mfc0(env, ctx, t0, rt, sel); + } + } else switch (sel) { + /* GPR registers. */ + case 0: + gen_helper_1i(mftgpr, t0, rt); + break; + /* Auxiliary CPU registers */ + case 1: + switch (rt) { + case 0: + gen_helper_1i(mftlo, t0, 0); + break; + case 1: + gen_helper_1i(mfthi, t0, 0); + break; + case 2: + gen_helper_1i(mftacx, t0, 0); + break; + case 4: + gen_helper_1i(mftlo, t0, 1); + break; + case 5: + gen_helper_1i(mfthi, t0, 1); + break; + case 6: + gen_helper_1i(mftacx, t0, 1); + break; + case 8: + gen_helper_1i(mftlo, t0, 2); + break; + case 9: + gen_helper_1i(mfthi, t0, 2); + break; + case 10: + gen_helper_1i(mftacx, t0, 2); + break; + case 12: + gen_helper_1i(mftlo, t0, 3); + break; + case 13: + gen_helper_1i(mfthi, t0, 3); + break; + case 14: + gen_helper_1i(mftacx, t0, 3); + break; + case 16: + gen_helper_mftdsp(t0); + break; + default: + goto die; + } + break; + /* Floating point (COP1). */ + case 2: + /* XXX: For now we support only a single FPU context. */ + if (h == 0) { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, rt); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } else { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, rt); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } + break; + case 3: + /* XXX: For now we support only a single FPU context. */ + gen_helper_1i(cfc1, t0, rt); + break; + /* COP2: Not implemented. */ + case 4: + case 5: + /* fall through */ + default: + goto die; + } + LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + return; + +die: + tcg_temp_free(t0); + LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); + generate_exception(ctx, EXCP_RI); +} + +static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, + int u, int sel, int h) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + TCGv t0 = tcg_temp_local_new(); + + gen_load_gpr(t0, rt); + if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && + ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != + (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) + /* NOP */ ; + else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > + (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + /* NOP */ ; + else if (u == 0) { + switch (rd) { + case 2: + switch (sel) { + case 1: + gen_helper_mttc0_tcstatus(t0); + break; + case 2: + gen_helper_mttc0_tcbind(t0); + break; + case 3: + gen_helper_mttc0_tcrestart(t0); + break; + case 4: + gen_helper_mttc0_tchalt(t0); + break; + case 5: + gen_helper_mttc0_tccontext(t0); + break; + case 6: + gen_helper_mttc0_tcschedule(t0); + break; + case 7: + gen_helper_mttc0_tcschefback(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + break; + case 10: + switch (sel) { + case 0: + gen_helper_mttc0_entryhi(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + case 12: + switch (sel) { + case 0: + gen_helper_mttc0_status(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + case 23: + switch (sel) { + case 0: + gen_helper_mttc0_debug(t0); + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + break; + } + break; + default: + gen_mtc0(env, ctx, t0, rd, sel); + } + } else switch (sel) { + /* GPR registers. */ + case 0: + gen_helper_1i(mttgpr, t0, rd); + break; + /* Auxiliary CPU registers */ + case 1: + switch (rd) { + case 0: + gen_helper_1i(mttlo, t0, 0); + break; + case 1: + gen_helper_1i(mtthi, t0, 0); + break; + case 2: + gen_helper_1i(mttacx, t0, 0); + break; + case 4: + gen_helper_1i(mttlo, t0, 1); + break; + case 5: + gen_helper_1i(mtthi, t0, 1); + break; + case 6: + gen_helper_1i(mttacx, t0, 1); + break; + case 8: + gen_helper_1i(mttlo, t0, 2); + break; + case 9: + gen_helper_1i(mtthi, t0, 2); + break; + case 10: + gen_helper_1i(mttacx, t0, 2); + break; + case 12: + gen_helper_1i(mttlo, t0, 3); + break; + case 13: + gen_helper_1i(mtthi, t0, 3); + break; + case 14: + gen_helper_1i(mttacx, t0, 3); + break; + case 16: + gen_helper_mttdsp(t0); + break; + default: + goto die; + } + break; + /* Floating point (COP1). */ + case 2: + /* XXX: For now we support only a single FPU context. */ + if (h == 0) { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, rd); + tcg_temp_free_i32(fp0); + } else { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32h(fp0, rd); + tcg_temp_free_i32(fp0); + } + break; + case 3: + /* XXX: For now we support only a single FPU context. */ + gen_helper_1i(ctc1, t0, rd); + break; + /* COP2: Not implemented. */ + case 4: + case 5: + /* fall through */ + default: + goto die; + } + LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); + tcg_temp_free(t0); + return; + +die: + tcg_temp_free(t0); + LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); + generate_exception(ctx, EXCP_RI); +} + +static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd) +{ + const char *opn = "ldst"; + + switch (opc) { + case OPC_MFC0: + if (rt == 0) { + /* Treat as NOP. */ + return; + } + gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); + opn = "mfc0"; + break; + case OPC_MTC0: + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7); + tcg_temp_free(t0); + } + opn = "mtc0"; + break; +#if defined(TARGET_MIPS64) + case OPC_DMFC0: + check_insn(env, ctx, ISA_MIPS3); + if (rt == 0) { + /* Treat as NOP. */ + return; + } + gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); + opn = "dmfc0"; + break; + case OPC_DMTC0: + check_insn(env, ctx, ISA_MIPS3); + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7); + tcg_temp_free(t0); + } + opn = "dmtc0"; + break; +#endif + case OPC_MFTR: + check_insn(env, ctx, ASE_MT); + if (rd == 0) { + /* Treat as NOP. */ + return; + } + gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, + ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); + opn = "mftr"; + break; + case OPC_MTTR: + check_insn(env, ctx, ASE_MT); + gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, + ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); + opn = "mttr"; + break; + case OPC_TLBWI: + opn = "tlbwi"; + if (!env->tlb->helper_tlbwi) + goto die; + gen_helper_tlbwi(); + break; + case OPC_TLBWR: + opn = "tlbwr"; + if (!env->tlb->helper_tlbwr) + goto die; + gen_helper_tlbwr(); + break; + case OPC_TLBP: + opn = "tlbp"; + if (!env->tlb->helper_tlbp) + goto die; + gen_helper_tlbp(); + break; + case OPC_TLBR: + opn = "tlbr"; + if (!env->tlb->helper_tlbr) + goto die; + gen_helper_tlbr(); + break; + case OPC_ERET: + opn = "eret"; + check_insn(env, ctx, ISA_MIPS2); + gen_helper_eret(); + ctx->bstate = BS_EXCP; + break; + case OPC_DERET: + opn = "deret"; + check_insn(env, ctx, ISA_MIPS32); + if (!(ctx->hflags & MIPS_HFLAG_DM)) { + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + } else { + gen_helper_deret(); + ctx->bstate = BS_EXCP; + } + break; + case OPC_WAIT: + opn = "wait"; + check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + /* If we get an exception, we want to restart at next instruction */ + ctx->pc += 4; + save_cpu_state(ctx, 1); + ctx->pc -= 4; + gen_helper_wait(); + ctx->bstate = BS_EXCP; + break; + default: + die: + MIPS_INVAL(opn); + generate_exception(ctx, EXCP_RI); + return; + } + MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); +} +#endif /* !CONFIG_USER_ONLY */ + +/* CP1 Branches (before delay slot) */ +static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, + int32_t cc, int32_t offset) +{ + target_ulong btarget; + const char *opn = "cp1 cond branch"; + TCGv_i32 t0 = tcg_temp_new_i32(); + + if (cc != 0) + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + + btarget = ctx->pc + 4 + offset; + + switch (op) { + case OPC_BC1F: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1f"; + goto not_likely; + case OPC_BC1FL: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1fl"; + goto likely; + case OPC_BC1T: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1t"; + goto not_likely; + case OPC_BC1TL: + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + opn = "bc1tl"; + likely: + ctx->hflags |= MIPS_HFLAG_BL; + break; + case OPC_BC1FANY2: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any2f"; + goto not_likely; + case OPC_BC1TANY2: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any2t"; + goto not_likely; + case OPC_BC1FANY4: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any4f"; + goto not_likely; + case OPC_BC1TANY4: + { + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); + tcg_gen_or_i32(t0, t0, t1); + tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); + tcg_gen_or_i32(t0, t0, t1); + tcg_temp_free_i32(t1); + tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extu_i32_tl(bcond, t0); + } + opn = "bc1any4t"; + not_likely: + ctx->hflags |= MIPS_HFLAG_BC; + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + goto out; + } + MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn, + ctx->hflags, btarget); + ctx->btarget = btarget; + + out: + tcg_temp_free_i32(t0); +} + +/* Coprocessor 1 (FPU) */ + +#define FOP(func, fmt) (((fmt) << 21) | (func)) + +static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) +{ + const char *opn = "cp1 move"; + TCGv t0 = tcg_temp_new(); + + switch (opc) { + case OPC_MFC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } + gen_store_gpr(t0, rt); + opn = "mfc1"; + break; + case OPC_MTC1: + gen_load_gpr(t0, rt); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, fs); + tcg_temp_free_i32(fp0); + } + opn = "mtc1"; + break; + case OPC_CFC1: + gen_helper_1i(cfc1, t0, fs); + gen_store_gpr(t0, rt); + opn = "cfc1"; + break; + case OPC_CTC1: + gen_load_gpr(t0, rt); + gen_helper_1i(ctc1, t0, fs); + opn = "ctc1"; + break; +#if defined(TARGET_MIPS64) + case OPC_DMFC1: + gen_load_fpr64(ctx, t0, fs); + gen_store_gpr(t0, rt); + opn = "dmfc1"; + break; + case OPC_DMTC1: + gen_load_gpr(t0, rt); + gen_store_fpr64(ctx, t0, fs); + opn = "dmtc1"; + break; +#endif + case OPC_MFHC1: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + tcg_gen_ext_i32_tl(t0, fp0); + tcg_temp_free_i32(fp0); + } + gen_store_gpr(t0, rt); + opn = "mfhc1"; + break; + case OPC_MTHC1: + gen_load_gpr(t0, rt); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32h(fp0, fs); + tcg_temp_free_i32(fp0); + } + opn = "mthc1"; + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + goto out; + } + MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]); + + out: + tcg_temp_free(t0); +} + +static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) +{ + int l1; + TCGCond cond; + TCGv_i32 t0; + + if (rd == 0) { + /* Treat as NOP. */ + return; + } + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + l1 = gen_new_label(); + t0 = tcg_temp_new_i32(); + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + tcg_temp_free_i32(t0); + if (rs == 0) { + tcg_gen_movi_tl(cpu_gpr[rd], 0); + } else { + tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); + } + gen_set_label(l1); +} + +static inline void gen_movcf_s (int fs, int fd, int cc, int tf) +{ + int cond; + TCGv_i32 t0 = tcg_temp_new_i32(); + int l1 = gen_new_label(); + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + gen_load_fpr32(t0, fs); + gen_store_fpr32(t0, fd); + gen_set_label(l1); + tcg_temp_free_i32(t0); +} + +static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) +{ + int cond; + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i64 fp0; + int l1 = gen_new_label(); + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + tcg_temp_free_i32(t0); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); +} + +static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) +{ + int cond; + TCGv_i32 t0 = tcg_temp_new_i32(); + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + if (tf) + cond = TCG_COND_EQ; + else + cond = TCG_COND_NE; + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); + tcg_gen_brcondi_i32(cond, t0, 0, l1); + gen_load_fpr32(t0, fs); + gen_store_fpr32(t0, fd); + gen_set_label(l1); + + tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1)); + tcg_gen_brcondi_i32(cond, t0, 0, l2); + gen_load_fpr32h(t0, fs); + gen_store_fpr32h(t0, fd); + tcg_temp_free_i32(t0); + gen_set_label(l2); +} + + +static void gen_farith (DisasContext *ctx, uint32_t op1, + int ft, int fs, int fd, int cc) +{ + const char *opn = "farith"; + const char *condnames[] = { + "c.f", + "c.un", + "c.eq", + "c.ueq", + "c.olt", + "c.ult", + "c.ole", + "c.ule", + "c.sf", + "c.ngle", + "c.seq", + "c.ngl", + "c.lt", + "c.nge", + "c.le", + "c.ngt", + }; + const char *condnames_abs[] = { + "cabs.f", + "cabs.un", + "cabs.eq", + "cabs.ueq", + "cabs.olt", + "cabs.ult", + "cabs.ole", + "cabs.ule", + "cabs.sf", + "cabs.ngle", + "cabs.seq", + "cabs.ngl", + "cabs.lt", + "cabs.nge", + "cabs.le", + "cabs.ngt", + }; + enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP; + uint32_t func = ctx->opcode & 0x3f; + + switch (ctx->opcode & FOP(0x3f, 0x1f)) { + case FOP(0, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_add_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "add.s"; + optype = BINOP; + break; + case FOP(1, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_sub_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "sub.s"; + optype = BINOP; + break; + case FOP(2, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_mul_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "mul.s"; + optype = BINOP; + break; + case FOP(3, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_div_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "div.s"; + optype = BINOP; + break; + case FOP(4, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_sqrt_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "sqrt.s"; + break; + case FOP(5, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_abs_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "abs.s"; + break; + case FOP(6, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "mov.s"; + break; + case FOP(7, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_chs_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "neg.s"; + break; + case FOP(8, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_roundl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "round.l.s"; + break; + case FOP(9, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_truncl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "trunc.l.s"; + break; + case FOP(10, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_ceill_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "ceil.l.s"; + break; + case FOP(11, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_floorl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "floor.l.s"; + break; + case FOP(12, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_roundw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "round.w.s"; + break; + case FOP(13, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_truncw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "trunc.w.s"; + break; + case FOP(14, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_ceilw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "ceil.w.s"; + break; + case FOP(15, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_floorw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "floor.w.s"; + break; + case FOP(17, 16): + gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1); + opn = "movcf.s"; + break; + case FOP(18, 16): + { + int l1 = gen_new_label(); + TCGv_i32 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + } + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(fp0, fs); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + gen_set_label(l1); + } + opn = "movz.s"; + break; + case FOP(19, 16): + { + int l1 = gen_new_label(); + TCGv_i32 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i32(); + gen_load_fpr32(fp0, fs); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + gen_set_label(l1); + } + } + opn = "movn.s"; + break; + case FOP(21, 16): + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_recip_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "recip.s"; + break; + case FOP(22, 16): + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_rsqrt_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "rsqrt.s"; + break; + case FOP(28, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, fd); + gen_helper_float_recip2_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "recip2.s"; + break; + case FOP(29, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_recip1_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "recip1.s"; + break; + case FOP(30, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_rsqrt1_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "rsqrt1.s"; + break; + case FOP(31, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_helper_float_rsqrt2_s(fp0, fp0, fp1); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "rsqrt2.s"; + break; + case FOP(33, 16): + check_cp1_registers(ctx, fd); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_cvtd_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.d.s"; + break; + case FOP(36, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_cvtw_s(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.w.s"; + break; + case FOP(37, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_cvtl_s(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.l.s"; + break; + case FOP(38, 16): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp64 = tcg_temp_new_i64(); + TCGv_i32 fp32_0 = tcg_temp_new_i32(); + TCGv_i32 fp32_1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp32_0, fs); + gen_load_fpr32(fp32_1, ft); + tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1); + tcg_temp_free_i32(fp32_1); + tcg_temp_free_i32(fp32_0); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.ps.s"; + break; + case FOP(48, 16): + case FOP(49, 16): + case FOP(50, 16): + case FOP(51, 16): + case FOP(52, 16): + case FOP(53, 16): + case FOP(54, 16): + case FOP(55, 16): + case FOP(56, 16): + case FOP(57, 16): + case FOP(58, 16): + case FOP(59, 16): + case FOP(60, 16): + case FOP(61, 16): + case FOP(62, 16): + case FOP(63, 16): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + if (ctx->opcode & (1 << 6)) { + check_cop1x(ctx); + gen_cmpabs_s(func-48, fp0, fp1, cc); + opn = condnames_abs[func-48]; + } else { + gen_cmp_s(func-48, fp0, fp1, cc); + opn = condnames[func-48]; + } + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + break; + case FOP(0, 17): + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_add_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "add.d"; + optype = BINOP; + break; + case FOP(1, 17): + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_sub_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "sub.d"; + optype = BINOP; + break; + case FOP(2, 17): + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_mul_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mul.d"; + optype = BINOP; + break; + case FOP(3, 17): + check_cp1_registers(ctx, fs | ft | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_div_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "div.d"; + optype = BINOP; + break; + case FOP(4, 17): + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_sqrt_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "sqrt.d"; + break; + case FOP(5, 17): + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_abs_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "abs.d"; + break; + case FOP(6, 17): + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mov.d"; + break; + case FOP(7, 17): + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_chs_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "neg.d"; + break; + case FOP(8, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_roundl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "round.l.d"; + break; + case FOP(9, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_truncl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "trunc.l.d"; + break; + case FOP(10, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_ceill_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "ceil.l.d"; + break; + case FOP(11, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_floorl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "floor.l.d"; + break; + case FOP(12, 17): + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_roundw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "round.w.d"; + break; + case FOP(13, 17): + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_truncw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "trunc.w.d"; + break; + case FOP(14, 17): + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_ceilw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "ceil.w.d"; + break; + case FOP(15, 17): + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_floorw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "floor.w.d"; + break; + case FOP(17, 17): + gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); + opn = "movcf.d"; + break; + case FOP(18, 17): + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + } + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + opn = "movz.d"; + break; + case FOP(19, 17): + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + } + opn = "movn.d"; + break; + case FOP(21, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_recip_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip.d"; + break; + case FOP(22, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_rsqrt_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt.d"; + break; + case FOP(28, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_recip2_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip2.d"; + break; + case FOP(29, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_recip1_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip1.d"; + break; + case FOP(30, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_rsqrt1_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt1.d"; + break; + case FOP(31, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_rsqrt2_d(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt2.d"; + break; + case FOP(48, 17): + case FOP(49, 17): + case FOP(50, 17): + case FOP(51, 17): + case FOP(52, 17): + case FOP(53, 17): + case FOP(54, 17): + case FOP(55, 17): + case FOP(56, 17): + case FOP(57, 17): + case FOP(58, 17): + case FOP(59, 17): + case FOP(60, 17): + case FOP(61, 17): + case FOP(62, 17): + case FOP(63, 17): + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + if (ctx->opcode & (1 << 6)) { + check_cop1x(ctx); + check_cp1_registers(ctx, fs | ft); + gen_cmpabs_d(func-48, fp0, fp1, cc); + opn = condnames_abs[func-48]; + } else { + check_cp1_registers(ctx, fs | ft); + gen_cmp_d(func-48, fp0, fp1, cc); + opn = condnames[func-48]; + } + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + } + break; + case FOP(32, 17): + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_cvts_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "cvt.s.d"; + break; + case FOP(36, 17): + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_cvtw_d(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "cvt.w.d"; + break; + case FOP(37, 17): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtl_d(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.l.d"; + break; + case FOP(32, 20): + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_cvts_w(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.s.w"; + break; + case FOP(33, 20): + check_cp1_registers(ctx, fd); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(fp32, fs); + gen_helper_float_cvtd_w(fp64, fp32); + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + opn = "cvt.d.w"; + break; + case FOP(32, 21): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + gen_helper_float_cvts_l(fp32, fp64); + tcg_temp_free_i64(fp64); + gen_store_fpr32(fp32, fd); + tcg_temp_free_i32(fp32); + } + opn = "cvt.s.l"; + break; + case FOP(33, 21): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtd_l(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.d.l"; + break; + case FOP(38, 20): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtps_pw(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.ps.pw"; + break; + case FOP(0, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_add_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "add.ps"; + break; + case FOP(1, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_sub_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "sub.ps"; + break; + case FOP(2, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_mul_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mul.ps"; + break; + case FOP(5, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_abs_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "abs.ps"; + break; + case FOP(6, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mov.ps"; + break; + case FOP(7, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_chs_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "neg.ps"; + break; + case FOP(17, 22): + check_cp1_64bitmode(ctx); + gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1); + opn = "movcf.ps"; + break; + case FOP(18, 22): + check_cp1_64bitmode(ctx); + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + opn = "movz.ps"; + break; + case FOP(19, 22): + check_cp1_64bitmode(ctx); + { + int l1 = gen_new_label(); + TCGv_i64 fp0; + + if (ft != 0) { + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); + fp0 = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + gen_set_label(l1); + } + } + opn = "movn.ps"; + break; + case FOP(24, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, ft); + gen_load_fpr64(ctx, fp1, fs); + gen_helper_float_addr_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "addr.ps"; + break; + case FOP(26, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, ft); + gen_load_fpr64(ctx, fp1, fs); + gen_helper_float_mulr_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "mulr.ps"; + break; + case FOP(28, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, fd); + gen_helper_float_recip2_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip2.ps"; + break; + case FOP(29, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_recip1_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "recip1.ps"; + break; + case FOP(30, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_rsqrt1_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt1.ps"; + break; + case FOP(31, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_helper_float_rsqrt2_ps(fp0, fp0, fp1); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "rsqrt2.ps"; + break; + case FOP(32, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + gen_helper_float_cvts_pu(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.s.pu"; + break; + case FOP(36, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_helper_float_cvtpw_ps(fp0, fp0); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "cvt.pw.ps"; + break; + case FOP(40, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_helper_float_cvts_pl(fp0, fp0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "cvt.s.pl"; + break; + case FOP(44, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_store_fpr32h(fp0, fd); + gen_store_fpr32(fp1, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "pll.ps"; + break; + case FOP(45, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32h(fp1, ft); + gen_store_fpr32(fp1, fd); + gen_store_fpr32h(fp0, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "plu.ps"; + break; + case FOP(46, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_store_fpr32(fp1, fd); + gen_store_fpr32h(fp0, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "pul.ps"; + break; + case FOP(47, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + + gen_load_fpr32h(fp0, fs); + gen_load_fpr32h(fp1, ft); + gen_store_fpr32(fp1, fd); + gen_store_fpr32h(fp0, fd); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + } + opn = "puu.ps"; + break; + case FOP(48, 22): + case FOP(49, 22): + case FOP(50, 22): + case FOP(51, 22): + case FOP(52, 22): + case FOP(53, 22): + case FOP(54, 22): + case FOP(55, 22): + case FOP(56, 22): + case FOP(57, 22): + case FOP(58, 22): + case FOP(59, 22): + case FOP(60, 22): + case FOP(61, 22): + case FOP(62, 22): + case FOP(63, 22): + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + if (ctx->opcode & (1 << 6)) { + gen_cmpabs_ps(func-48, fp0, fp1, cc); + opn = condnames_abs[func-48]; + } else { + gen_cmp_ps(func-48, fp0, fp1, cc); + opn = condnames[func-48]; + } + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + } + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + return; + } + switch (optype) { + case BINOP: + MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]); + break; + case CMPOP: + MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]); + break; + default: + MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]); + break; + } +} + +/* Coprocessor 3 (FPU) */ +static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, + int fd, int fs, int base, int index) +{ + const char *opn = "extended float load/store"; + int store = 0; + TCGv t0 = tcg_temp_new(); + + if (base == 0) { + gen_load_gpr(t0, index); + } else if (index == 0) { + gen_load_gpr(t0, base); + } else { + gen_load_gpr(t0, index); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); + } + /* Don't do NOP if destination is zero: we must perform the actual + memory access. */ + save_cpu_state(ctx, 0); + switch (opc) { + case OPC_LWXC1: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); + tcg_gen_trunc_tl_i32(fp0, t0); + gen_store_fpr32(fp0, fd); + tcg_temp_free_i32(fp0); + } + opn = "lwxc1"; + break; + case OPC_LDXC1: + check_cop1x(ctx); + check_cp1_registers(ctx, fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "ldxc1"; + break; + case OPC_LUXC1: + check_cp1_64bitmode(ctx); + tcg_gen_andi_tl(t0, t0, ~0x7); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + opn = "luxc1"; + break; + case OPC_SWXC1: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv t1 = tcg_temp_new(); + + gen_load_fpr32(fp0, fs); + tcg_gen_extu_i32_tl(t1, fp0); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); + tcg_temp_free_i32(fp0); + tcg_temp_free(t1); + } + opn = "swxc1"; + store = 1; + break; + case OPC_SDXC1: + check_cop1x(ctx); + check_cp1_registers(ctx, fs); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); + tcg_temp_free_i64(fp0); + } + opn = "sdxc1"; + store = 1; + break; + case OPC_SUXC1: + check_cp1_64bitmode(ctx); + tcg_gen_andi_tl(t0, t0, ~0x7); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); + tcg_temp_free_i64(fp0); + } + opn = "suxc1"; + store = 1; + break; + } + tcg_temp_free(t0); + MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd], + regnames[index], regnames[base]); +} + +static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, + int fd, int fr, int fs, int ft) +{ + const char *opn = "flt3_arith"; + + switch (opc) { + case OPC_ALNV_PS: + check_cp1_64bitmode(ctx); + { + TCGv t0 = tcg_temp_local_new(); + TCGv_i32 fp = tcg_temp_new_i32(); + TCGv_i32 fph = tcg_temp_new_i32(); + int l1 = gen_new_label(); + int l2 = gen_new_label(); + + gen_load_gpr(t0, fr); + tcg_gen_andi_tl(t0, t0, 0x7); + + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); + gen_load_fpr32(fp, fs); + gen_load_fpr32h(fph, fs); + gen_store_fpr32(fp, fd); + gen_store_fpr32h(fph, fd); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); + tcg_temp_free(t0); +#ifdef TARGET_WORDS_BIGENDIAN + gen_load_fpr32(fp, fs); + gen_load_fpr32h(fph, ft); + gen_store_fpr32h(fp, fd); + gen_store_fpr32(fph, fd); +#else + gen_load_fpr32h(fph, fs); + gen_load_fpr32(fp, ft); + gen_store_fpr32(fph, fd); + gen_store_fpr32h(fp, fd); +#endif + gen_set_label(l2); + tcg_temp_free_i32(fp); + tcg_temp_free_i32(fph); + } + opn = "alnv.ps"; + break; + case OPC_MADD_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_muladd_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "madd.s"; + break; + case OPC_MADD_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_muladd_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "madd.d"; + break; + case OPC_MADD_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "madd.ps"; + break; + case OPC_MSUB_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "msub.s"; + break; + case OPC_MSUB_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "msub.d"; + break; + case OPC_MSUB_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "msub.ps"; + break; + case OPC_NMADD_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "nmadd.s"; + break; + case OPC_NMADD_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmadd.d"; + break; + case OPC_NMADD_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmadd.ps"; + break; + case OPC_NMSUB_S: + check_cop1x(ctx); + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + TCGv_i32 fp1 = tcg_temp_new_i32(); + TCGv_i32 fp2 = tcg_temp_new_i32(); + + gen_load_fpr32(fp0, fs); + gen_load_fpr32(fp1, ft); + gen_load_fpr32(fp2, fr); + gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2); + tcg_temp_free_i32(fp0); + tcg_temp_free_i32(fp1); + gen_store_fpr32(fp2, fd); + tcg_temp_free_i32(fp2); + } + opn = "nmsub.s"; + break; + case OPC_NMSUB_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmsub.d"; + break; + case OPC_NMSUB_PS: + check_cp1_64bitmode(ctx); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + TCGv_i64 fp1 = tcg_temp_new_i64(); + TCGv_i64 fp2 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_load_fpr64(ctx, fp1, ft); + gen_load_fpr64(ctx, fp2, fr); + gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2); + tcg_temp_free_i64(fp0); + tcg_temp_free_i64(fp1); + gen_store_fpr64(ctx, fp2, fd); + tcg_temp_free_i64(fp2); + } + opn = "nmsub.ps"; + break; + default: + MIPS_INVAL(opn); + generate_exception (ctx, EXCP_RI); + return; + } + MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr], + fregnames[fs], fregnames[ft]); +} + +/* ISA extensions (ASEs) */ +/* MIPS16 extension to MIPS32 */ +/* SmartMIPS extension to MIPS32 */ + +#if defined(TARGET_MIPS64) + +/* MDMX extension to MIPS64 */ + +#endif + +static void decode_opc (CPUState *env, DisasContext *ctx) +{ + int32_t offset; + int rs, rt, rd, sa; + uint32_t op, op1, op2; + int16_t imm; + + /* make sure instructions are on a word boundary */ + if (ctx->pc & 0x3) { + env->CP0_BadVAddr = ctx->pc; + generate_exception(ctx, EXCP_AdEL); + return; + } + + /* Handle blikely not taken case */ + if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) { + int l1 = gen_new_label(); + + MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4); + tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); + tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); + gen_goto_tb(ctx, 1, ctx->pc + 4); + gen_set_label(l1); + } + + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + tcg_gen_debug_insn_start(ctx->pc); + + op = MASK_OP_MAJOR(ctx->opcode); + rs = (ctx->opcode >> 21) & 0x1f; + rt = (ctx->opcode >> 16) & 0x1f; + rd = (ctx->opcode >> 11) & 0x1f; + sa = (ctx->opcode >> 6) & 0x1f; + imm = (int16_t)ctx->opcode; + switch (op) { + case OPC_SPECIAL: + op1 = MASK_SPECIAL(ctx->opcode); + switch (op1) { + case OPC_SLL: /* Shift with immediate */ + case OPC_SRA: + case OPC_SRL: + gen_shift_imm(env, ctx, op1, rd, rt, sa); + break; + case OPC_MOVN: /* Conditional move */ + case OPC_MOVZ: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + gen_cond_move(env, op1, rd, rs, rt); + break; + case OPC_ADD ... OPC_SUBU: + gen_arith(env, ctx, op1, rd, rs, rt); + break; + case OPC_SLLV: /* Shifts */ + case OPC_SRLV: + case OPC_SRAV: + gen_shift(env, ctx, op1, rd, rs, rt); + break; + case OPC_SLT: /* Set on less than */ + case OPC_SLTU: + gen_slt(env, op1, rd, rs, rt); + break; + case OPC_AND: /* Logic*/ + case OPC_OR: + case OPC_NOR: + case OPC_XOR: + gen_logic(env, op1, rd, rs, rt); + break; + case OPC_MULT ... OPC_DIVU: + if (sa) { + check_insn(env, ctx, INSN_VR54XX); + op1 = MASK_MUL_VR54XX(ctx->opcode); + gen_mul_vr54xx(ctx, op1, rd, rs, rt); + } else + gen_muldiv(ctx, op1, rs, rt); + break; + case OPC_JR ... OPC_JALR: + gen_compute_branch(ctx, op1, rs, rd, sa); + return; + case OPC_TGE ... OPC_TEQ: /* Traps */ + case OPC_TNE: + gen_trap(ctx, op1, rs, rt, -1); + break; + case OPC_MFHI: /* Move from HI/LO */ + case OPC_MFLO: + gen_HILO(ctx, op1, rd); + break; + case OPC_MTHI: + case OPC_MTLO: /* Move to HI/LO */ + gen_HILO(ctx, op1, rs); + break; + case OPC_PMON: /* Pmon entry point, also R4010 selsl */ +#ifdef MIPS_STRICT_STANDARD + MIPS_INVAL("PMON / selsl"); + generate_exception(ctx, EXCP_RI); +#else + gen_helper_0i(pmon, sa); +#endif + break; + case OPC_SYSCALL: + generate_exception(ctx, EXCP_SYSCALL); + ctx->bstate = BS_STOP; + break; + case OPC_BREAK: + generate_exception(ctx, EXCP_BREAK); + break; + case OPC_SPIM: +#ifdef MIPS_STRICT_STANDARD + MIPS_INVAL("SPIM"); + generate_exception(ctx, EXCP_RI); +#else + /* Implemented as RI exception for now. */ + MIPS_INVAL("spim (unofficial)"); + generate_exception(ctx, EXCP_RI); +#endif + break; + case OPC_SYNC: + /* Treat as NOP. */ + break; + + case OPC_MOVCI: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, + (ctx->opcode >> 16) & 1); + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + +#if defined(TARGET_MIPS64) + /* MIPS64 specific opcodes */ + case OPC_DSLL: + case OPC_DSRA: + case OPC_DSRL: + case OPC_DSLL32: + case OPC_DSRA32: + case OPC_DSRL32: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_shift_imm(env, ctx, op1, rd, rt, sa); + break; + case OPC_DADD ... OPC_DSUBU: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_arith(env, ctx, op1, rd, rs, rt); + break; + case OPC_DSLLV: + case OPC_DSRAV: + case OPC_DSRLV: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_shift(env, ctx, op1, rd, rs, rt); + break; + case OPC_DMULT ... OPC_DDIVU: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_muldiv(ctx, op1, rs, rt); + break; +#endif + default: /* Invalid */ + MIPS_INVAL("special"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_SPECIAL2: + op1 = MASK_SPECIAL2(ctx->opcode); + switch (op1) { + case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */ + case OPC_MSUB ... OPC_MSUBU: + check_insn(env, ctx, ISA_MIPS32); + gen_muldiv(ctx, op1, rs, rt); + break; + case OPC_MUL: + gen_arith(env, ctx, op1, rd, rs, rt); + break; + case OPC_CLO: + case OPC_CLZ: + check_insn(env, ctx, ISA_MIPS32); + gen_cl(ctx, op1, rd, rs); + break; + case OPC_SDBBP: + /* XXX: not clear which exception should be raised + * when in debug mode... + */ + check_insn(env, ctx, ISA_MIPS32); + if (!(ctx->hflags & MIPS_HFLAG_DM)) { + generate_exception(ctx, EXCP_DBp); + } else { + generate_exception(ctx, EXCP_DBp); + } + /* Treat as NOP. */ + break; +#if defined(TARGET_MIPS64) + case OPC_DCLO: + case OPC_DCLZ: + check_insn(env, ctx, ISA_MIPS64); + check_mips_64(ctx); + gen_cl(ctx, op1, rd, rs); + break; +#endif + default: /* Invalid */ + MIPS_INVAL("special2"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_SPECIAL3: + op1 = MASK_SPECIAL3(ctx->opcode); + switch (op1) { + case OPC_EXT: + case OPC_INS: + check_insn(env, ctx, ISA_MIPS32R2); + gen_bitops(ctx, op1, rt, rs, sa, rd); + break; + case OPC_BSHFL: + check_insn(env, ctx, ISA_MIPS32R2); + op2 = MASK_BSHFL(ctx->opcode); + gen_bshfl(ctx, op2, rt, rd); + break; + case OPC_RDHWR: + check_insn(env, ctx, ISA_MIPS32R2); + { + TCGv t0 = tcg_temp_new(); + + switch (rd) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_cpunum(t0); + gen_store_gpr(t0, rt); + break; + case 1: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_synci_step(t0); + gen_store_gpr(t0, rt); + break; + case 2: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_cc(t0); + gen_store_gpr(t0, rt); + break; + case 3: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_ccres(t0); + gen_store_gpr(t0, rt); + break; + case 29: +#if defined(CONFIG_USER_ONLY) + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value)); + gen_store_gpr(t0, rt); + break; +#else + /* XXX: Some CPUs implement this in hardware. + Not supported yet. */ +#endif + default: /* Invalid */ + MIPS_INVAL("rdhwr"); + generate_exception(ctx, EXCP_RI); + break; + } + tcg_temp_free(t0); + } + break; + case OPC_FORK: + check_insn(env, ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + gen_helper_fork(t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case OPC_YIELD: + check_insn(env, ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + + save_cpu_state(ctx, 1); + gen_load_gpr(t0, rs); + gen_helper_yield(t0, t0); + gen_store_gpr(t0, rd); + tcg_temp_free(t0); + } + break; +#if defined(TARGET_MIPS64) + case OPC_DEXTM ... OPC_DEXT: + case OPC_DINSM ... OPC_DINS: + check_insn(env, ctx, ISA_MIPS64R2); + check_mips_64(ctx); + gen_bitops(ctx, op1, rt, rs, sa, rd); + break; + case OPC_DBSHFL: + check_insn(env, ctx, ISA_MIPS64R2); + check_mips_64(ctx); + op2 = MASK_DBSHFL(ctx->opcode); + gen_bshfl(ctx, op2, rt, rd); + break; +#endif + default: /* Invalid */ + MIPS_INVAL("special3"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_REGIMM: + op1 = MASK_REGIMM(ctx->opcode); + switch (op1) { + case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */ + case OPC_BLTZAL ... OPC_BGEZALL: + gen_compute_branch(ctx, op1, rs, -1, imm << 2); + return; + case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */ + case OPC_TNEI: + gen_trap(ctx, op1, rs, -1, imm); + break; + case OPC_SYNCI: + check_insn(env, ctx, ISA_MIPS32R2); + /* Treat as NOP. */ + break; + default: /* Invalid */ + MIPS_INVAL("regimm"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_CP0: + check_cp0_enabled(ctx); + op1 = MASK_CP0(ctx->opcode); + switch (op1) { + case OPC_MFC0: + case OPC_MTC0: + case OPC_MFTR: + case OPC_MTTR: +#if defined(TARGET_MIPS64) + case OPC_DMFC0: + case OPC_DMTC0: +#endif +#ifndef CONFIG_USER_ONLY + gen_cp0(env, ctx, op1, rt, rd); +#endif /* !CONFIG_USER_ONLY */ + break; + case OPC_C0_FIRST ... OPC_C0_LAST: +#ifndef CONFIG_USER_ONLY + gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); +#endif /* !CONFIG_USER_ONLY */ + break; + case OPC_MFMC0: +#ifndef CONFIG_USER_ONLY + { + TCGv t0 = tcg_temp_new(); + + op2 = MASK_MFMC0(ctx->opcode); + switch (op2) { + case OPC_DMT: + check_insn(env, ctx, ASE_MT); + gen_helper_dmt(t0, t0); + gen_store_gpr(t0, rt); + break; + case OPC_EMT: + check_insn(env, ctx, ASE_MT); + gen_helper_emt(t0, t0); + gen_store_gpr(t0, rt); + break; + case OPC_DVPE: + check_insn(env, ctx, ASE_MT); + gen_helper_dvpe(t0, t0); + gen_store_gpr(t0, rt); + break; + case OPC_EVPE: + check_insn(env, ctx, ASE_MT); + gen_helper_evpe(t0, t0); + gen_store_gpr(t0, rt); + break; + case OPC_DI: + check_insn(env, ctx, ISA_MIPS32R2); + save_cpu_state(ctx, 1); + gen_helper_di(t0); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + case OPC_EI: + check_insn(env, ctx, ISA_MIPS32R2); + save_cpu_state(ctx, 1); + gen_helper_ei(t0); + gen_store_gpr(t0, rt); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; + break; + default: /* Invalid */ + MIPS_INVAL("mfmc0"); + generate_exception(ctx, EXCP_RI); + break; + } + tcg_temp_free(t0); + } +#endif /* !CONFIG_USER_ONLY */ + break; + case OPC_RDPGPR: + check_insn(env, ctx, ISA_MIPS32R2); + gen_load_srsgpr(rt, rd); + break; + case OPC_WRPGPR: + check_insn(env, ctx, ISA_MIPS32R2); + gen_store_srsgpr(rt, rd); + break; + default: + MIPS_INVAL("cp0"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_ADDI: /* Arithmetic with immediate opcode */ + case OPC_ADDIU: + gen_arith_imm(env, ctx, op, rt, rs, imm); + break; + case OPC_SLTI: /* Set on less than with immediate opcode */ + case OPC_SLTIU: + gen_slt_imm(env, op, rt, rs, imm); + break; + case OPC_ANDI: /* Arithmetic with immediate opcode */ + case OPC_LUI: + case OPC_ORI: + case OPC_XORI: + gen_logic_imm(env, op, rt, rs, imm); + break; + case OPC_J ... OPC_JAL: /* Jump */ + offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; + gen_compute_branch(ctx, op, rs, rt, offset); + return; + case OPC_BEQ ... OPC_BGTZ: /* Branch */ + case OPC_BEQL ... OPC_BGTZL: + gen_compute_branch(ctx, op, rs, rt, imm << 2); + return; + case OPC_LB ... OPC_LWR: /* Load and stores */ + case OPC_SB ... OPC_SW: + case OPC_SWR: + case OPC_LL: + gen_ldst(ctx, op, rt, rs, imm); + break; + case OPC_SC: + gen_st_cond(ctx, op, rt, rs, imm); + break; + case OPC_CACHE: + check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + /* Treat as NOP. */ + break; + case OPC_PREF: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + /* Treat as NOP. */ + break; + + /* Floating point (COP1). */ + case OPC_LWC1: + case OPC_LDC1: + case OPC_SWC1: + case OPC_SDC1: + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + gen_flt_ldst(ctx, op, rt, rs, imm); + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + + case OPC_CP1: + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + op1 = MASK_CP1(ctx->opcode); + switch (op1) { + case OPC_MFHC1: + case OPC_MTHC1: + check_insn(env, ctx, ISA_MIPS32R2); + case OPC_MFC1: + case OPC_CFC1: + case OPC_MTC1: + case OPC_CTC1: + gen_cp1(ctx, op1, rt, rd); + break; +#if defined(TARGET_MIPS64) + case OPC_DMFC1: + case OPC_DMTC1: + check_insn(env, ctx, ISA_MIPS3); + gen_cp1(ctx, op1, rt, rd); + break; +#endif + case OPC_BC1ANY2: + case OPC_BC1ANY4: + check_cop1x(ctx); + check_insn(env, ctx, ASE_MIPS3D); + /* fall through */ + case OPC_BC1: + gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), + (rt >> 2) & 0x7, imm << 2); + return; + case OPC_S_FMT: + case OPC_D_FMT: + case OPC_W_FMT: + case OPC_L_FMT: + case OPC_PS_FMT: + gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa, + (imm >> 8) & 0x7); + break; + default: + MIPS_INVAL("cp1"); + generate_exception (ctx, EXCP_RI); + break; + } + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + + /* COP2. */ + case OPC_LWC2: + case OPC_LDC2: + case OPC_SWC2: + case OPC_SDC2: + case OPC_CP2: + /* COP2: Not implemented. */ + generate_exception_err(ctx, EXCP_CpU, 2); + break; + + case OPC_CP3: + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + op1 = MASK_CP3(ctx->opcode); + switch (op1) { + case OPC_LWXC1: + case OPC_LDXC1: + case OPC_LUXC1: + case OPC_SWXC1: + case OPC_SDXC1: + case OPC_SUXC1: + gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); + break; + case OPC_PREFX: + /* Treat as NOP. */ + break; + case OPC_ALNV_PS: + case OPC_MADD_S: + case OPC_MADD_D: + case OPC_MADD_PS: + case OPC_MSUB_S: + case OPC_MSUB_D: + case OPC_MSUB_PS: + case OPC_NMADD_S: + case OPC_NMADD_D: + case OPC_NMADD_PS: + case OPC_NMSUB_S: + case OPC_NMSUB_D: + case OPC_NMSUB_PS: + gen_flt3_arith(ctx, op1, sa, rs, rd, rt); + break; + default: + MIPS_INVAL("cp3"); + generate_exception (ctx, EXCP_RI); + break; + } + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } + break; + +#if defined(TARGET_MIPS64) + /* MIPS64 opcodes */ + case OPC_LWU: + case OPC_LDL ... OPC_LDR: + case OPC_SDL ... OPC_SDR: + case OPC_LLD: + case OPC_LD: + case OPC_SD: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_ldst(ctx, op, rt, rs, imm); + break; + case OPC_SCD: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_st_cond(ctx, op, rt, rs, imm); + break; + case OPC_DADDI: + case OPC_DADDIU: + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_arith_imm(env, ctx, op, rt, rs, imm); + break; +#endif + case OPC_JALX: + check_insn(env, ctx, ASE_MIPS16); + /* MIPS16: Not implemented. */ + case OPC_MDMX: + check_insn(env, ctx, ASE_MDMX); + /* MDMX: Not implemented. */ + default: /* Invalid */ + MIPS_INVAL("major opcode"); + generate_exception(ctx, EXCP_RI); + break; + } + if (ctx->hflags & MIPS_HFLAG_BMASK) { + int hflags = ctx->hflags & MIPS_HFLAG_BMASK; + /* Branches completion */ + ctx->hflags &= ~MIPS_HFLAG_BMASK; + ctx->bstate = BS_BRANCH; + save_cpu_state(ctx, 0); + /* FIXME: Need to clear can_do_io. */ + switch (hflags) { + case MIPS_HFLAG_B: + /* unconditional branch */ + MIPS_DEBUG("unconditional branch"); + gen_goto_tb(ctx, 0, ctx->btarget); + break; + case MIPS_HFLAG_BL: + /* blikely taken case */ + MIPS_DEBUG("blikely branch taken"); + gen_goto_tb(ctx, 0, ctx->btarget); + break; + case MIPS_HFLAG_BC: + /* Conditional branch */ + MIPS_DEBUG("conditional branch"); + { + int l1 = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); + gen_goto_tb(ctx, 1, ctx->pc + 4); + gen_set_label(l1); + gen_goto_tb(ctx, 0, ctx->btarget); + } + break; + case MIPS_HFLAG_BR: + /* unconditional branch to register */ + MIPS_DEBUG("branch to register"); + tcg_gen_mov_tl(cpu_PC, btarget); + if (ctx->singlestep_enabled) { + save_cpu_state(ctx, 0); + gen_helper_0i(raise_exception, EXCP_DEBUG); + } + tcg_gen_exit_tb(0); + break; + default: + MIPS_DEBUG("unknown branch"); + break; + } + } +} + +static inline void +gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, + int search_pc) +{ + DisasContext ctx; + target_ulong pc_start; + uint16_t *gen_opc_end; + CPUBreakpoint *bp; + int j, lj = -1; + int num_insns; + int max_insns; + + if (search_pc) + qemu_log("search pc %d\n", search_pc); + + pc_start = tb->pc; + gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; + ctx.pc = pc_start; + ctx.saved_pc = -1; + ctx.singlestep_enabled = env->singlestep_enabled; + ctx.tb = tb; + ctx.bstate = BS_NONE; + /* Restore delay slot state from the tb context. */ + ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */ + restore_cpu_state(env, &ctx); +#ifdef CONFIG_USER_ONLY + ctx.mem_idx = MIPS_HFLAG_UM; +#else + ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU; +#endif + num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) + max_insns = CF_COUNT_MASK; +#ifdef DEBUG_DISAS + qemu_log_mask(CPU_LOG_TB_CPU, "------------------------------------------------\n"); + /* FIXME: This may print out stale hflags from env... */ + log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0); +#endif + LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); + gen_icount_start(); + while (ctx.bstate == BS_NONE) { + if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { + QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (bp->pc == ctx.pc) { + save_cpu_state(&ctx, 1); + ctx.bstate = BS_BRANCH; + gen_helper_0i(raise_exception, EXCP_DEBUG); + /* Include the breakpoint location or the tb won't + * be flushed when it must be. */ + ctx.pc += 4; + goto done_generating; + } + } + } + + if (search_pc) { + j = gen_opc_ptr - gen_opc_buf; + if (lj < j) { + lj++; + while (lj < j) + gen_opc_instr_start[lj++] = 0; + } + gen_opc_pc[lj] = ctx.pc; + gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; + gen_opc_instr_start[lj] = 1; + gen_opc_icount[lj] = num_insns; + } + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + gen_io_start(); + ctx.opcode = ldl_code(ctx.pc); + decode_opc(env, &ctx); + ctx.pc += 4; + num_insns++; + + /* Execute a branch and its delay slot as a single instruction. + This is what GDB expects and is consistent with what the + hardware does (e.g. if a delay slot instruction faults, the + reported PC is the PC of the branch). */ + if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) + break; + + if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) + break; + + if (gen_opc_ptr >= gen_opc_end) + break; + + if (num_insns >= max_insns) + break; + + if (singlestep) + break; + } + if (tb->cflags & CF_LAST_IO) + gen_io_end(); + if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) { + save_cpu_state(&ctx, ctx.bstate == BS_NONE); + gen_helper_0i(raise_exception, EXCP_DEBUG); + } else { + switch (ctx.bstate) { + case BS_STOP: + gen_helper_interrupt_restart(); + gen_goto_tb(&ctx, 0, ctx.pc); + break; + case BS_NONE: + save_cpu_state(&ctx, 0); + gen_goto_tb(&ctx, 0, ctx.pc); + break; + case BS_EXCP: + gen_helper_interrupt_restart(); + tcg_gen_exit_tb(0); + break; + case BS_BRANCH: + default: + break; + } + } +done_generating: + gen_icount_end(tb, num_insns); + *gen_opc_ptr = INDEX_op_end; + if (search_pc) { + j = gen_opc_ptr - gen_opc_buf; + lj++; + while (lj <= j) + gen_opc_instr_start[lj++] = 0; + } else { + tb->size = ctx.pc - pc_start; + tb->icount = num_insns; + } +#ifdef DEBUG_DISAS + LOG_DISAS("\n"); + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { + qemu_log("IN: %s\n", lookup_symbol(pc_start)); + log_target_disas(pc_start, ctx.pc - pc_start, 0); + qemu_log("\n"); + } + qemu_log_mask(CPU_LOG_TB_CPU, "---------------- %d %08x\n", ctx.bstate, ctx.hflags); +#endif +} + +void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) +{ + gen_intermediate_code_internal(env, tb, 0); +} + +void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) +{ + gen_intermediate_code_internal(env, tb, 1); +} + +static void fpu_dump_state(CPUState *env, FILE *f, + int (*fpu_fprintf)(FILE *f, const char *fmt, ...), + int flags) +{ + int i; + int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); + +#define printfpr(fp) \ + do { \ + if (is_fpu64) \ + fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \ + (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \ + else { \ + fpr_t tmp; \ + tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \ + tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \ + fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \ + tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \ + } \ + } while(0) + + + fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { + fpu_fprintf(f, "%3s: ", fregnames[i]); + printfpr(&env->active_fpu.fpr[i]); + } + +#undef printfpr +} + +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) +/* Debug help: The architecture requires 32bit code to maintain proper + sign-extended values on 64bit machines. */ + +#define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff)) + +static void +cpu_mips_check_sign_extensions (CPUState *env, FILE *f, + int (*cpu_fprintf)(FILE *f, const char *fmt, ...), + int flags) +{ + int i; + + if (!SIGN_EXT_P(env->active_tc.PC)) + cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->active_tc.PC); + if (!SIGN_EXT_P(env->active_tc.HI[0])) + cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->active_tc.HI[0]); + if (!SIGN_EXT_P(env->active_tc.LO[0])) + cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->active_tc.LO[0]); + if (!SIGN_EXT_P(env->btarget)) + cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget); + + for (i = 0; i < 32; i++) { + if (!SIGN_EXT_P(env->active_tc.gpr[i])) + cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->active_tc.gpr[i]); + } + + if (!SIGN_EXT_P(env->CP0_EPC)) + cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC); + if (!SIGN_EXT_P(env->lladdr)) + cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->lladdr); +} +#endif + +void cpu_dump_state (CPUState *env, FILE *f, + int (*cpu_fprintf)(FILE *f, const char *fmt, ...), + int flags) +{ + int i; + + cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], + env->hflags, env->btarget, env->bcond); + for (i = 0; i < 32; i++) { + if ((i & 3) == 0) + cpu_fprintf(f, "GPR%02d:", i); + cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]); + if ((i & 3) == 3) + cpu_fprintf(f, "\n"); + } + + cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n", + env->CP0_Config0, env->CP0_Config1, env->lladdr); + if (env->hflags & MIPS_HFLAG_FPU) + fpu_dump_state(env, f, cpu_fprintf, flags); +#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) + cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); +#endif +} + +static void mips_tcg_init(void) +{ + int i; + static int inited; + + /* Initialize various static tables. */ + if (inited) + return; + + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); + TCGV_UNUSED(cpu_gpr[0]); + for (i = 1; i < 32; i++) + cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.gpr[i]), + regnames[i]); + cpu_PC = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.PC), "PC"); + for (i = 0; i < MIPS_DSP_ACC; i++) { + cpu_HI[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.HI[i]), + regnames_HI[i]); + cpu_LO[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.LO[i]), + regnames_LO[i]); + cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.ACX[i]), + regnames_ACX[i]); + } + cpu_dspctrl = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, active_tc.DSPControl), + "DSPControl"); + bcond = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, bcond), "bcond"); + btarget = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUState, btarget), "btarget"); + hflags = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, hflags), "hflags"); + + fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, active_fpu.fcr0), + "fcr0"); + fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, active_fpu.fcr31), + "fcr31"); + + /* register helpers */ +#define GEN_HELPER 2 +#include "helper.h" + + inited = 1; +} + +#include "translate_init.c" + +CPUMIPSState *cpu_mips_init (const char *cpu_model) +{ + CPUMIPSState *env; + const mips_def_t *def; + + def = cpu_mips_find_by_name(cpu_model); + if (!def) + return NULL; + env = qemu_mallocz(sizeof(CPUMIPSState)); + env->cpu_model = def; + env->cpu_model_str = cpu_model; + + cpu_exec_init(env); +#ifndef CONFIG_USER_ONLY + mmu_init(env, def); +#endif + mvp_init(env, def); + mips_tcg_init(); + cpu_reset(env); + qemu_init_vcpu(env); + return env; +} + +void cpu_reset (CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } + + memset(env, 0, offsetof(CPUMIPSState, breakpoints)); + tlb_flush(env, 1); + + /* Reset registers to their default values */ + env->CP0_PRid = env->cpu_model->CP0_PRid; + env->CP0_Config0 = env->cpu_model->CP0_Config0; +#ifdef TARGET_WORDS_BIGENDIAN + env->CP0_Config0 |= (1 << CP0C0_BE); +#endif + env->CP0_Config1 = env->cpu_model->CP0_Config1; + env->CP0_Config2 = env->cpu_model->CP0_Config2; + env->CP0_Config3 = env->cpu_model->CP0_Config3; + env->CP0_Config6 = env->cpu_model->CP0_Config6; + env->CP0_Config7 = env->cpu_model->CP0_Config7; + env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask + << env->cpu_model->CP0_LLAddr_shift; + env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; + env->SYNCI_Step = env->cpu_model->SYNCI_Step; + env->CCRes = env->cpu_model->CCRes; + env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; + env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; + env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; + env->current_tc = 0; + env->SEGBITS = env->cpu_model->SEGBITS; + env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); +#if defined(TARGET_MIPS64) + if (env->cpu_model->insn_flags & ISA_MIPS3) { + env->SEGMask |= 3ULL << 62; + } +#endif + env->PABITS = env->cpu_model->PABITS; + env->PAMask = (target_ulong)((1ULL << env->cpu_model->PABITS) - 1); + env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; + env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; + env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; + env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; + env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; + env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; + env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; + env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; + env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; + env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; + env->insn_flags = env->cpu_model->insn_flags; + + fpu_init(env, env->cpu_model); + +#if defined(CONFIG_USER_ONLY) + env->hflags = MIPS_HFLAG_UM; + /* Enable access to the SYNCI_Step register. */ + env->CP0_HWREna |= (1 << 1); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + env->hflags |= MIPS_HFLAG_FPU; + } +#ifdef TARGET_MIPS64 + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->hflags |= MIPS_HFLAG_F64; + } +#endif +#else + if (env->hflags & MIPS_HFLAG_BMASK) { + /* If the exception was raised from a delay slot, + come back to the jump. */ + env->CP0_ErrorEPC = env->active_tc.PC - 4; + } else { + env->CP0_ErrorEPC = env->active_tc.PC; + } + env->active_tc.PC = (int32_t)0xBFC00000; + env->CP0_Random = env->tlb->nb_tlb - 1; + env->tlb->tlb_in_use = env->tlb->nb_tlb; + env->CP0_Wired = 0; + /* SMP not implemented */ + env->CP0_EBase = 0x80000000; + env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); + /* vectored interrupts not implemented, timer on int 7, + no performance counters. */ + env->CP0_IntCtl = 0xe0000000; + { + int i; + + for (i = 0; i < 7; i++) { + env->CP0_WatchLo[i] = 0; + env->CP0_WatchHi[i] = 0x80000000; + } + env->CP0_WatchLo[7] = 0; + env->CP0_WatchHi[7] = 0; + } + /* Count register increments in debug mode, EJTAG version 1 */ + env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); + env->hflags = MIPS_HFLAG_CP0; +#endif +#if defined(TARGET_MIPS64) + if (env->cpu_model->insn_flags & ISA_MIPS3) { + env->hflags |= MIPS_HFLAG_64; + } +#endif + env->exception_index = EXCP_NONE; +} + +void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) +{ + env->active_tc.PC = gen_opc_pc[pc_pos]; + env->hflags &= ~MIPS_HFLAG_BMASK; + env->hflags |= gen_opc_hflags[pc_pos]; +} diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c new file mode 100644 index 0000000..3978908 --- /dev/null +++ b/target-mips/translate_init.c @@ -0,0 +1,554 @@ +/* + * MIPS emulation for qemu: CPU initialisation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2007 Herve Poussineau + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +/* CPU / CPU family specific config register values. */ + +/* Have config1, uncached coherency */ +#define MIPS_CONFIG0 \ + ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) + +/* Have config2, no coprocessor2 attached, no MDMX support attached, + no performance counters, watch registers present, + no code compression, EJTAG present, no FPU */ +#define MIPS_CONFIG1 \ +((1 << CP0C1_M) | \ + (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ + (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ + (0 << CP0C1_FP)) + +/* Have config3, no tertiary/secondary caches implemented */ +#define MIPS_CONFIG2 \ +((1 << CP0C2_M)) + +/* No config4, no DSP ASE, no large physaddr (PABITS), + no external interrupt controller, no vectored interupts, + no 1kb pages, no SmartMIPS ASE, no trace logic */ +#define MIPS_CONFIG3 \ +((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ + (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ + (0 << CP0C3_SM) | (0 << CP0C3_TL)) + +/* Define a implementation number of 1. + Define a major version 1, minor version 0. */ +#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) + +/* MMU types, the first four entries have the same layout as the + CP0C0_MT field. */ +enum mips_mmu_types { + MMU_TYPE_NONE, + MMU_TYPE_R4000, + MMU_TYPE_RESERVED, + MMU_TYPE_FMT, + MMU_TYPE_R3000, + MMU_TYPE_R6000, + MMU_TYPE_R8000 +}; + +struct mips_def_t { + const char *name; + int32_t CP0_PRid; + int32_t CP0_Config0; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config6; + int32_t CP0_Config7; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + int32_t SYNCI_Step; + int32_t CCRes; + int32_t CP0_Status_rw_bitmask; + int32_t CP0_TCStatus_rw_bitmask; + int32_t CP0_SRSCtl; + int32_t CP1_fcr0; + int32_t SEGBITS; + int32_t PABITS; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; + int insn_flags; + enum mips_mmu_types mmu_type; +}; + +/*****************************************************************************/ +/* MIPS CPU definitions */ +static const mips_def_t mips_defs[] = +{ + { + .name = "4Kc", + .CP0_PRid = 0x00018000, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4Km", + .CP0_PRid = 0x00018300, + /* Config1 implemented, fixed mapping MMU, + no virtual icache, uncached coherency. */ + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "4KEcR1", + .CP0_PRid = 0x00018400, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4KEmR1", + .CP0_PRid = 0x00018500, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "4KEc", + .CP0_PRid = 0x00019000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "4KEm", + .CP0_PRid = 0x00019100, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { + .name = "24Kc", + .CP0_PRid = 0x00019300, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x1278FF1F, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "24Kf", + .CP0_PRid = 0x00019300, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x3678FF1F, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "34Kf", + .CP0_PRid = 0x00019500, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + /* No DSP implemented. */ + .CP0_Status_rw_bitmask = 0x3678FF1F, + /* No DSP implemented. */ + .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | + (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | + (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | + (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | + (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | + (0xff << CP0TCSt_TASID), + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), + .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), + .CP0_SRSConf0_rw_bitmask = 0x3fffffff, + .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | + (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), + .CP0_SRSConf1_rw_bitmask = 0x3fffffff, + .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | + (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), + .CP0_SRSConf2_rw_bitmask = 0x3fffffff, + .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | + (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), + .CP0_SRSConf3_rw_bitmask = 0x3fffffff, + .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | + (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), + .CP0_SRSConf4_rw_bitmask = 0x3fffffff, + .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | + (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, + .mmu_type = MMU_TYPE_R4000, + }, +#if defined(TARGET_MIPS64) + { + .name = "R4000", + .CP0_PRid = 0x00000400, + /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ + .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + /* Note: Config1 is only used internally, the R4000 has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3678FFFF, + /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 36, + .insn_flags = CPU_MIPS3, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "VR5432", + .CP0_PRid = 0x00005400, + /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ + .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3678FFFF, + /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 32, + .insn_flags = CPU_VR54XX, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5Kc", + .CP0_PRid = 0x00018100, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x32F8FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5Kf", + .CP0_PRid = 0x00018100, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36F8FFFF, + /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | + (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "20Kc", + /* We emulate a later version of the 20Kc, earlier ones had a broken + WAIT instruction. */ + .CP0_PRid = 0x000182a0, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 1, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_D) | (1 << FCR0_S) | + (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 36, + .insn_flags = CPU_MIPS64 | ASE_MIPS3D, + .mmu_type = MMU_TYPE_R4000, + }, + { + /* A generic CPU providing MIPS64 Release 2 features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "MIPS64R2-generic", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + /* The architectural limit is 59, but we have hardcoded 36 bit + in some places... + .PABITS = 59, */ /* the architectural limit */ + .PABITS = 36, + .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, + .mmu_type = MMU_TYPE_R4000, + }, +#endif +}; + +static const mips_def_t *cpu_mips_find_by_name (const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { + if (strcasecmp(name, mips_defs[i].name) == 0) { + return &mips_defs[i]; + } + } + return NULL; +} + +void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { + (*cpu_fprintf)(f, "MIPS '%s'\n", + mips_defs[i].name); + } +} + +#ifndef CONFIG_USER_ONLY +static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &no_mmu_map_address; +} + +static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &fixed_mmu_map_address; +} + +static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->map_address = &r4k_map_address; + env->tlb->helper_tlbwi = r4k_helper_tlbwi; + env->tlb->helper_tlbwr = r4k_helper_tlbwr; + env->tlb->helper_tlbp = r4k_helper_tlbp; + env->tlb->helper_tlbr = r4k_helper_tlbr; +} + +static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); + + switch (def->mmu_type) { + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env, "MMU type not supported\n"); + } +} +#endif /* CONFIG_USER_ONLY */ + +static void fpu_init (CPUMIPSState *env, const mips_def_t *def) +{ + int i; + + for (i = 0; i < MIPS_FPU_MAX; i++) + env->fpus[i].fcr0 = def->CP1_fcr0; + + memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); +} + +static void mvp_init (CPUMIPSState *env, const mips_def_t *def) +{ + env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); + + /* MVPConf1 implemented, TLB sharable, no gating storage support, + programmable cache partitioning implemented, number of allocatable + and sharable TLB entries, MVP has allocatable TCs, 2 VPEs + implemented, 5 TCs implemented. */ + env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | + (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | +// TODO: actually do 2 VPEs. +// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | +// (0x04 << CP0MVPC0_PTC); + (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | + (0x04 << CP0MVPC0_PTC); +#if !defined(CONFIG_USER_ONLY) + /* Usermode has no TLB support */ + env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); +#endif + + /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, + no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ + env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | + (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | + (0x1 << CP0MVPC1_PCP1); +} diff --git a/vl-android.c b/vl-android.c index 8071052..1513541 100644 --- a/vl-android.c +++ b/vl-android.c @@ -55,6 +55,7 @@ #include "android/hw-pipe-net.h" #include "android/hw-qemud.h" #include "android/camera/camera-service.h" +#include "android/multitouch-port.h" #include "android/charmap.h" #include "android/globals.h" #include "android/utils/bufprint.h" @@ -67,6 +68,7 @@ #include "android/utils/timezone.h" #include "android/snapshot.h" #include "android/opengles.h" +#include "android/multitouch-screen.h" #include "targphys.h" #include "tcpdump.h" @@ -2269,7 +2271,7 @@ char *qemu_find_file(int type, const char *name) buf = qemu_find_file_with_subdir(data_dir, "../usr/share/pc-bios/", name); /* Finally, try this for standalone builds under external/qemu */ if (buf == NULL) - buf = qemu_find_file_with_subdir(data_dir, "../../../prebuilt/common/pc-bios/", name); + buf = qemu_find_file_with_subdir(data_dir, "../../../prebuilts/qemu-kernel/x86/pc-bios/", name); } #endif return buf; @@ -2380,7 +2382,7 @@ net_slirp_forward(const char *optarg) char *dst_net, *dst_mask, *dst_port; char *redirect_ip, *redirect_port; uint32_t dnet, dmask, rip; - unsigned short dlport, dhport, rport; + unsigned short dlport = 0, dhport = 0, rport; dst_net = strtok(p, ":"); @@ -2446,7 +2448,7 @@ slirp_allow(const char *optarg, u_int8_t proto) char *argument = strdup(optarg), *p = argument; char *dst_ip_str, *dst_port_str; uint32_t dst_ip; - unsigned short dst_lport, dst_hport; + unsigned short dst_lport = 0, dst_hport = 0; dst_ip_str = strtok(p, ":"); dst_port_str = strtok(NULL, ":"); @@ -3575,10 +3577,10 @@ int main(int argc, char **argv, char **envp) uint64_t sysBytes = android_hw->disk_systemPartition_size; if (sysBytes == 0) { - PANIC("Invalid system partition size: %" PRUd64, sysBytes); + PANIC("Invalid system partition size: %" PRIu64, sysBytes); } - snprintf(tmp,sizeof(tmp),"system,size=0x%" PRUx64, sysBytes); + snprintf(tmp,sizeof(tmp),"system,size=0x%" PRIx64, sysBytes); if (sysImage && *sysImage) { if (filelock_create(sysImage) == NULL) { @@ -3610,10 +3612,10 @@ int main(int argc, char **argv, char **envp) uint64_t dataBytes = android_hw->disk_dataPartition_size; if (dataBytes == 0) { - PANIC("Invalid data partition size: %" PRUd64, dataBytes); + PANIC("Invalid data partition size: %" PRIu64, dataBytes); } - snprintf(tmp,sizeof(tmp),"userdata,size=0x%" PRUx64, dataBytes); + snprintf(tmp,sizeof(tmp),"userdata,size=0x%" PRIx64, dataBytes); if (dataImage && *dataImage) { if (filelock_create(dataImage) == NULL) { @@ -3763,10 +3765,21 @@ int main(int argc, char **argv, char **envp) //android_hw_opengles_init(); /* Initialize fake camera */ - if (android_hw->hw_fakeCamera) { - boot_property_add("qemu.sf.fake_camera", android_hw->hw_fakeCamera); + if (strcmp(android_hw->hw_camera_back, "emulated") && + strcmp(android_hw->hw_camera_front, "emulated")) { + /* Fake camera is not used for camera emulation. */ + boot_property_add("qemu.sf.fake_camera", "none"); } else { - boot_property_add("qemu.sf.fake_camera", "back"); + /* Fake camera is used for at least one camera emulation. */ + if (!strcmp(android_hw->hw_camera_back, "emulated") && + !strcmp(android_hw->hw_camera_front, "emulated")) { + /* Fake camera is used for both, front and back camera emulation. */ + boot_property_add("qemu.sf.fake_camera", "both"); + } else if (!strcmp(android_hw->hw_camera_back, "emulated")) { + boot_property_add("qemu.sf.fake_camera", "back"); + } else { + boot_property_add("qemu.sf.fake_camera", "front"); + } } /* Initialize camera emulation. */ @@ -3833,7 +3846,7 @@ int main(int argc, char **argv, char **envp) const char* partPath = android_hw->disk_cachePartition_path; uint64_t partSize = android_hw->disk_cachePartition_size; - snprintf(tmp,sizeof(tmp),"cache,size=0x%" PRUx64, partSize); + snprintf(tmp,sizeof(tmp),"cache,size=0x%" PRIx64, partSize); if (partPath && *partPath && strcmp(partPath, "<temp>") != 0) { if (filelock_create(partPath) == NULL) { @@ -3854,23 +3867,40 @@ int main(int argc, char **argv, char **envp) nand_add_dev(tmp); } - /* qemu.gles will be read by the OpenGLES emulation libraries. - * If set to 0, the software GLES renderer will be used as a fallback. - * If the parameter is undefined, this means the system image runs - * inside an emulator that doesn't support GPU emulation at all. - */ + /* qemu.gles will be read by the OpenGL ES emulation libraries. + * If set to 0, the software GL ES renderer will be used as a fallback. + * If the parameter is undefined, this means the system image runs + * inside an emulator that doesn't support GPU emulation at all. + * + * We always start the GL ES renderer so we can gather stats on the + * underlying GL implementation. If GL ES acceleration is disabled, + * we just shut it down again once we have the strings. */ { - int gles_emul = 0; - - if (android_hw->hw_gpu_enabled) { - if (android_initOpenglesEmulation() == 0) { - gles_emul = 1; - android_startOpenglesRenderer(android_hw->hw_lcd_width, android_hw->hw_lcd_height); + int qemu_gles = 0; + + /* Set framebuffer change notification callback when starting + * GLES emulation. Currently only multi-touch emulation is + * interested in FB changes (to transmit them to the device), so + * the callback is set within MT emulation. */ + if (android_initOpenglesEmulation() == 0 && + android_startOpenglesRenderer(android_hw->hw_lcd_width, + android_hw->hw_lcd_height, + multitouch_opengles_fb_update, NULL) == 0) + { + android_getOpenglesHardwareStrings( + android_gl_vendor, sizeof(android_gl_vendor), + android_gl_renderer, sizeof(android_gl_renderer), + android_gl_version, sizeof(android_gl_version)); + if (android_hw->hw_gpu_enabled) { + qemu_gles = 1; } else { - dwarning("Could not initialize OpenglES emulation, using software renderer."); + android_stopOpenglesRenderer(); + qemu_gles = 0; } + } else { + dwarning("Could not initialize OpenglES emulation, using software renderer."); } - if (gles_emul) { + if (qemu_gles) { stralloc_add_str(kernel_params, " qemu.gles=1"); } else { stralloc_add_str(kernel_params, " qemu.gles=0"); @@ -4143,6 +4173,7 @@ int main(int argc, char **argv, char **envp) { int ret; + hax_set_ramsize(ram_size); ret = hax_init(smp_cpus); fprintf(stderr, "HAX is %s and emulator runs in %s mode\n", !ret ? "working" :"not working", !ret ? "fast virt" : "emulation"); @@ -4257,6 +4288,11 @@ int main(int argc, char **argv, char **envp) initrd_filename, cpu_model); + /* Initialize multi-touch emulation. */ + if (androidHwConfig_isScreenMultiTouch(android_hw)) { + mts_port_create(NULL); + } + stralloc_reset(kernel_params); stralloc_reset(kernel_config); } |