diff options
Diffstat (limited to 'hw/arm_gic.c')
| -rw-r--r-- | hw/arm_gic.c | 61 |
1 files changed, 23 insertions, 38 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 54e99f4..563397d 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -14,26 +14,27 @@ //#define DEBUG_GIC #ifdef DEBUG_GIC -#define DPRINTF(fmt, args...) \ -do { printf("arm_gic: " fmt , ##args); } while (0) +#define DPRINTF(fmt, ...) \ +do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) #else -#define DPRINTF(fmt, args...) do {} while(0) +#define DPRINTF(fmt, ...) do {} while(0) #endif #ifdef NVIC static const uint8_t gic_id[] = { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; -#define GIC_DIST_OFFSET 0 /* The NVIC has 16 internal vectors. However these are not exposed through the normal GIC interface. */ #define GIC_BASE_IRQ 32 #else static const uint8_t gic_id[] = { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -#define GIC_DIST_OFFSET 0x1000 #define GIC_BASE_IRQ 0 #endif +#define FROM_SYSBUSGIC(type, dev) \ + DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev)) + typedef struct gic_irq_state { /* ??? The documentation seems to imply the enable bits are global, even @@ -41,7 +42,7 @@ typedef struct gic_irq_state unsigned enabled:1; unsigned pending:NCPU; unsigned active:NCPU; - unsigned level:1; + unsigned level:NCPU; unsigned model:1; /* 0 = N:N, 1 = 1:N */ unsigned trigger:1; /* nonzero = edge triggered. */ } gic_irq_state; @@ -76,7 +77,7 @@ typedef struct gic_irq_state typedef struct gic_state { - uint32_t base; + SysBusDevice busdev; qemu_irq parent_irq[NCPU]; int enabled; int cpu_enabled[NCPU]; @@ -94,10 +95,7 @@ typedef struct gic_state int running_priority[NCPU]; int current_pending[NCPU]; - qemu_irq *in; -#ifdef NVIC - void *nvic; -#endif + int iomemtype; } gic_state; /* TODO: Many places that call this routine could be optimized. */ @@ -252,7 +250,6 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) cpu = gic_get_current_cpu(); cm = 1 << cpu; - offset -= s->base + GIC_DIST_OFFSET; if (offset < 0x100) { #ifndef NVIC if (offset == 0) @@ -347,7 +344,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) } return res; bad_reg: - cpu_abort(cpu_single_env, "gic_dist_readb: Bad offset %x\n", (int)offset); + hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); return 0; } @@ -365,9 +362,9 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) #ifdef NVIC gic_state *s = (gic_state *)opaque; uint32_t addr; - addr = offset - s->base; + addr = offset; if (addr < 0x100 || addr > 0xd00) - return nvic_readl(s->nvic, addr); + return nvic_readl(s, addr); #endif val = gic_dist_readw(opaque, offset); val |= gic_dist_readw(opaque, offset + 2) << 16; @@ -383,7 +380,6 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, int cpu; cpu = gic_get_current_cpu(); - offset -= s->base + GIC_DIST_OFFSET; if (offset < 0x100) { #ifdef NVIC goto bad_reg; @@ -510,7 +506,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, gic_update(s); return; bad_reg: - cpu_abort(cpu_single_env, "gic_dist_writeb: Bad offset %x\n", (int)offset); + hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); } static void gic_dist_writew(void *opaque, target_phys_addr_t offset, @@ -526,13 +522,13 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset, gic_state *s = (gic_state *)opaque; #ifdef NVIC uint32_t addr; - addr = offset - s->base; + addr = offset; if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { - nvic_writel(s->nvic, addr, value); + nvic_writel(s, addr, value); return; } #endif - if (offset - s->base == GIC_DIST_OFFSET + 0xf00) { + if (offset == 0xf00) { int cpu; int irq; int mask; @@ -592,8 +588,7 @@ static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; default: - cpu_abort(cpu_single_env, "gic_cpu_read: Bad offset %x\n", - (int)offset); + hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); return 0; } } @@ -614,8 +609,7 @@ static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, cpu, value & 0x3ff); default: - cpu_abort(cpu_single_env, "gic_cpu_write: Bad offset %x\n", - (int)offset); + hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); return; } gic_update(s); @@ -723,25 +717,16 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq) +static void gic_init(gic_state *s) { - gic_state *s; - int iomemtype; int i; - s = (gic_state *)qemu_mallocz(sizeof(gic_state)); - if (!s) - return NULL; - s->in = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ); + qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32); for (i = 0; i < NCPU; i++) { - s->parent_irq[i] = parent_irq[i]; + sysbus_init_irq(&s->busdev, &s->parent_irq[i]); } - iomemtype = cpu_register_io_memory(0, gic_dist_readfn, - gic_dist_writefn, s); - cpu_register_physical_memory(base + GIC_DIST_OFFSET, 0x00001000, - iomemtype); - s->base = base; + s->iomemtype = cpu_register_io_memory(gic_dist_readfn, + gic_dist_writefn, s); gic_reset(s); register_savevm("arm_gic", -1, 1, gic_save, gic_load, s); - return s; } |