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-rw-r--r--hw/goldfish_events_device.c96
-rw-r--r--hw/goldfish_fb.c21
-rw-r--r--hw/goldfish_nand.c4
-rw-r--r--hw/goldfish_pipe.c48
-rw-r--r--hw/goldfish_pipe.h15
-rw-r--r--hw/mips-bios.h8
-rw-r--r--hw/mips.h43
-rw-r--r--hw/mips_int.c45
-rw-r--r--hw/mips_r4k.c311
-rw-r--r--hw/mips_timer.c109
10 files changed, 657 insertions, 43 deletions
diff --git a/hw/goldfish_events_device.c b/hw/goldfish_events_device.c
index a5b2a21..dad76ad 100644
--- a/hw/goldfish_events_device.c
+++ b/hw/goldfish_events_device.c
@@ -13,6 +13,7 @@
#include "android/hw-events.h"
#include "android/charmap.h"
#include "android/globals.h" /* for android_hw */
+#include "android/multitouch-screen.h"
#include "irq.h"
#include "user-events.h"
#include "console.h"
@@ -68,6 +69,18 @@ typedef struct
size_t abs_info_count;
} events_state;
+/* An entry in the array of ABS_XXX values */
+typedef struct ABSEntry {
+ /* Minimum ABS_XXX value. */
+ uint32_t min;
+ /* Maximum ABS_XXX value. */
+ uint32_t max;
+ /* 'fuzz;, and 'flat' ABS_XXX values are always zero here. */
+ uint32_t fuzz;
+ uint32_t flat;
+} ABSEntry;
+
+
/* modify this each time you change the events_device structure. you
* will also need to upadte events_state_load and events_state_save
*/
@@ -258,20 +271,27 @@ static void events_put_mouse(void *opaque, int dx, int dy, int dz, int buttons_s
* in android/skin/trackball.c and android/skin/window.c
*/
if (dz == 0) {
- enqueue_event(s, EV_ABS, ABS_X, dx);
- enqueue_event(s, EV_ABS, ABS_Y, dy);
- enqueue_event(s, EV_ABS, ABS_Z, dz);
- enqueue_event(s, EV_KEY, BTN_TOUCH, buttons_state&1);
+ if (androidHwConfig_isScreenMultiTouch(android_hw)) {
+ /* Convert mouse event into multi-touch event */
+ multitouch_update_pointer(MTES_MOUSE, 0, dx, dy,
+ (buttons_state & 1) ? 0x81 : 0);
+ } else if (androidHwConfig_isScreenTouch(android_hw)) {
+ enqueue_event(s, EV_ABS, ABS_X, dx);
+ enqueue_event(s, EV_ABS, ABS_Y, dy);
+ enqueue_event(s, EV_ABS, ABS_Z, dz);
+ enqueue_event(s, EV_KEY, BTN_TOUCH, buttons_state&1);
+ enqueue_event(s, EV_SYN, 0, 0);
+ }
} else {
enqueue_event(s, EV_REL, REL_X, dx);
enqueue_event(s, EV_REL, REL_Y, dy);
+ enqueue_event(s, EV_SYN, 0, 0);
}
- enqueue_event(s, EV_SYN, 0, 0);
}
static void events_put_generic(void* opaque, int type, int code, int value)
{
- events_state *s = (events_state *) opaque;
+ events_state *s = (events_state *) opaque;
enqueue_event(s, type, code, value);
}
@@ -382,11 +402,13 @@ void events_dev_init(uint32_t base, qemu_irq irq)
if (config->hw_trackBall) {
events_set_bit(s, EV_KEY, BTN_MOUSE);
}
- if (config->hw_touchScreen) {
+ if (androidHwConfig_isScreenTouch(config)) {
events_set_bit(s, EV_KEY, BTN_TOUCH);
}
- if (config->hw_camera) {
+ if (strcmp(config->hw_camera_back, "none") ||
+ strcmp(config->hw_camera_front, "none")) {
+ /* Camera emulation is enabled. */
events_set_bit(s, EV_KEY, KEY_CAMERA);
}
@@ -431,13 +453,13 @@ void events_dev_init(uint32_t base, qemu_irq irq)
*
* EV_ABS events are sent when the touchscreen is pressed
*/
- if (config->hw_touchScreen) {
- int32_t* values;
+ if (!androidHwConfig_isScreenNoTouch(config)) {
+ ABSEntry* abs_values;
events_set_bit (s, EV_SYN, EV_ABS );
events_set_bits(s, EV_ABS, ABS_X, ABS_Z);
/* Allocate the absinfo to report the min/max bounds for each
- * absolute dimension. The array must contain 3 tuples
+ * absolute dimension. The array must contain 3, or ABS_MAX tuples
* of (min,max,fuzz,flat) 32-bit values.
*
* min and max are the bounds
@@ -448,33 +470,39 @@ void events_dev_init(uint32_t base, qemu_irq irq)
* There is no need to save/restore this array in a snapshot
* since the values only depend on the hardware configuration.
*/
- s->abs_info_count = 3*4;
- s->abs_info = values = malloc(sizeof(uint32_t)*s->abs_info_count);
-
- /* ABS_X min/max/fuzz/flat */
- values[0] = 0;
- values[1] = config->hw_lcd_width-1;
- values[2] = 0;
- values[3] = 0;
- values += 4;
-
- /* ABS_Y */
- values[0] = 0;
- values[1] = config->hw_lcd_height-1;
- values[2] = 0;
- values[3] = 0;
- values += 4;
-
- /* ABS_Z */
- values[0] = 0;
- values[1] = 1;
- values[2] = 0;
- values[3] = 0;
+ s->abs_info_count = androidHwConfig_isScreenMultiTouch(config) ? ABS_MAX * 4 : 3 * 4;
+ const int abs_size = sizeof(uint32_t) * s->abs_info_count;
+ s->abs_info = malloc(abs_size);
+ memset(s->abs_info, 0, abs_size);
+ abs_values = (ABSEntry*)s->abs_info;
+
+ abs_values[ABS_X].max = config->hw_lcd_width-1;
+ abs_values[ABS_Y].max = config->hw_lcd_height-1;
+ abs_values[ABS_Z].max = 1;
+
+ if (androidHwConfig_isScreenMultiTouch(config)) {
+ /*
+ * Setup multitouch.
+ */
+ events_set_bit(s, EV_ABS, ABS_MT_SLOT);
+ events_set_bit(s, EV_ABS, ABS_MT_POSITION_X);
+ events_set_bit(s, EV_ABS, ABS_MT_POSITION_Y);
+ events_set_bit(s, EV_ABS, ABS_MT_TRACKING_ID);
+ events_set_bit(s, EV_ABS, ABS_MT_TOUCH_MAJOR);
+ events_set_bit(s, EV_ABS, ABS_MT_PRESSURE);
+
+ abs_values[ABS_MT_SLOT].max = multitouch_get_max_slot();
+ abs_values[ABS_MT_TRACKING_ID].max = abs_values[ABS_MT_SLOT].max + 1;
+ abs_values[ABS_MT_POSITION_X].max = abs_values[ABS_X].max;
+ abs_values[ABS_MT_POSITION_Y].max = abs_values[ABS_Y].max;
+ abs_values[ABS_MT_TOUCH_MAJOR].max = 0x7fffffff; // TODO: Make it less random
+ abs_values[ABS_MT_PRESSURE].max = 0x100; // TODO: Make it less random
+ }
}
/* configure EV_SW array
*
- * EW_SW events are sent to indicate that the keyboard lid
+ * EV_SW events are sent to indicate that the keyboard lid
* was closed or opened (done when we switch layouts through
* KP-7 or KP-9).
*
diff --git a/hw/goldfish_fb.c b/hw/goldfish_fb.c
index d74d797..16450b3 100644
--- a/hw/goldfish_fb.c
+++ b/hw/goldfish_fb.c
@@ -319,7 +319,11 @@ compute_fb_update_rect_linear(FbUpdateState* fbs,
xx1 = 0;
DUFF4(width, {
- if (src[xx1] != dst[xx1])
+ uint16_t spix = src[xx1];
+#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
+ spix = (uint16_t)((spix << 8) | (spix >> 8));
+#endif
+ if (spix != dst[xx1])
break;
xx1++;
});
@@ -332,8 +336,8 @@ compute_fb_update_rect_linear(FbUpdateState* fbs,
break;
xx2--;
});
-#if HOST_WORDS_BIGENDIAN
- /* Convert the guest little-endian pixels into big-endian ones */
+#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
+ /* Convert the guest pixels into host ones */
int xx = xx1;
DUFF4(xx2-xx1+1,{
unsigned spix = src[xx];
@@ -382,7 +386,12 @@ compute_fb_update_rect_linear(FbUpdateState* fbs,
xx1 = 0;
DUFF4(width, {
- if (src[xx1] != dst[xx1]) {
+ uint32_t spix = src[xx1];
+#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
+ spix = (spix << 16) | (spix >> 16);
+ spix = ((spix << 8) & 0xff00ff00) | ((spix >> 8) & 0x00ff00ff);
+#endif
+ if (spix != dst[xx1]) {
break;
}
xx1++;
@@ -397,8 +406,8 @@ compute_fb_update_rect_linear(FbUpdateState* fbs,
}
xx2--;
});
-#if HOST_WORDS_BIGENDIAN
- /* Convert the guest little-endian pixels into big-endian ones */
+#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
+ /* Convert the guest pixels into host ones */
int xx = xx1;
DUFF4(xx2-xx1+1,{
uint32_t spix = src[xx];
diff --git a/hw/goldfish_nand.c b/hw/goldfish_nand.c
index 31e814b..55f77f6 100644
--- a/hw/goldfish_nand.c
+++ b/hw/goldfish_nand.c
@@ -140,7 +140,7 @@ typedef struct {
* 2: saving actual disk contents as well
* 3: use the correct data length and truncate to avoid padding.
*/
-#define NAND_DEV_STATE_SAVE_VERSION 3
+#define NAND_DEV_STATE_SAVE_VERSION 4
#define QFIELD_STRUCT nand_dev_controller_state
QFIELD_BEGIN(nand_dev_controller_state_fields)
@@ -149,6 +149,8 @@ QFIELD_BEGIN(nand_dev_controller_state_fields)
QFIELD_INT32(addr_high),
QFIELD_INT32(transfer_size),
QFIELD_INT32(data),
+ QFIELD_INT32(batch_addr_low),
+ QFIELD_INT32(batch_addr_high),
QFIELD_INT32(result),
QFIELD_END
diff --git a/hw/goldfish_pipe.c b/hw/goldfish_pipe.c
index 97daefb..276ac9a 100644
--- a/hw/goldfish_pipe.c
+++ b/hw/goldfish_pipe.c
@@ -55,7 +55,7 @@
/* Maximum length of pipe service name, in characters (excluding final 0) */
#define MAX_PIPE_SERVICE_NAME_SIZE 255
-#define GOLDFISH_PIPE_SAVE_VERSION 1
+#define GOLDFISH_PIPE_SAVE_VERSION 2
/***********************************************************************
***********************************************************************
@@ -960,9 +960,9 @@ struct PipeDevice {
uint32_t status;
uint32_t channel;
uint32_t wakes;
+ uint64_t params_addr;
};
-
static void
pipeDevice_doCommand( PipeDevice* dev, uint32_t command )
{
@@ -1097,6 +1097,42 @@ static void pipe_dev_write(void *opaque, target_phys_addr_t offset, uint32_t val
s->channel = value;
break;
+ case PIPE_REG_PARAMS_ADDR_HIGH:
+ s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL << 32) ) |
+ ((uint64_t)value << 32);
+ break;
+
+ case PIPE_REG_PARAMS_ADDR_LOW:
+ s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL) ) | value;
+ break;
+
+ case PIPE_REG_ACCESS_PARAMS:
+ {
+ struct access_params aps;
+ uint32_t cmd;
+
+ /* Don't touch aps.result if anything wrong */
+ if (s->params_addr == 0)
+ break;
+
+ cpu_physical_memory_read(s->params_addr, (void*)&aps,
+ sizeof(struct access_params));
+
+ /* sync pipe device state from batch buffer */
+ s->channel = aps.channel;
+ s->size = aps.size;
+ s->address = aps.address;
+ cmd = aps.cmd;
+ if ((cmd != PIPE_CMD_READ_BUFFER) && (cmd != PIPE_CMD_WRITE_BUFFER))
+ break;
+
+ pipeDevice_doCommand(s, cmd);
+ aps.result = s->status;
+ cpu_physical_memory_write(s->params_addr, (void*)&aps,
+ sizeof(struct access_params));
+ }
+ break;
+
default:
D("%s: offset=%d (0x%x) value=%d (0x%x)\n", __FUNCTION__, offset,
offset, value, value);
@@ -1136,6 +1172,12 @@ static uint32_t pipe_dev_read(void *opaque, target_phys_addr_t offset)
DR("%s: wakes %d", __FUNCTION__, dev->wakes);
return dev->wakes;
+ case PIPE_REG_PARAMS_ADDR_HIGH:
+ return dev->params_addr >> 32;
+
+ case PIPE_REG_PARAMS_ADDR_LOW:
+ return dev->params_addr & 0xFFFFFFFFUL;
+
default:
D("%s: offset=%d (0x%x)\n", __FUNCTION__, offset, offset);
}
@@ -1165,6 +1207,7 @@ goldfish_pipe_save( QEMUFile* file, void* opaque )
qemu_put_be32(file, dev->status);
qemu_put_be32(file, dev->channel);
qemu_put_be32(file, dev->wakes);
+ qemu_put_be64(file, dev->params_addr);
/* Count the number of pipe connections */
int count = 0;
@@ -1193,6 +1236,7 @@ goldfish_pipe_load( QEMUFile* file, void* opaque, int version_id )
dev->status = qemu_get_be32(file);
dev->channel = qemu_get_be32(file);
dev->wakes = qemu_get_be32(file);
+ dev->params_addr = qemu_get_be64(file);
/* Count the number of pipe connections */
int count = qemu_get_sbe32(file);
diff --git a/hw/goldfish_pipe.h b/hw/goldfish_pipe.h
index f08cef8..10efa96 100644
--- a/hw/goldfish_pipe.h
+++ b/hw/goldfish_pipe.h
@@ -153,6 +153,11 @@ extern void goldfish_pipe_wake( void* hwpipe, unsigned flags );
#define PIPE_REG_SIZE 0x0c /* read/write: buffer size */
#define PIPE_REG_ADDRESS 0x10 /* write: physical address */
#define PIPE_REG_WAKES 0x14 /* read: wake flags */
+/* read/write: parameter buffer address */
+#define PIPE_REG_PARAMS_ADDR_LOW 0x18
+#define PIPE_REG_PARAMS_ADDR_HIGH 0x1c
+/* write: access with paremeter buffer */
+#define PIPE_REG_ACCESS_PARAMS 0x20
/* list of commands for PIPE_REG_COMMAND */
#define PIPE_CMD_OPEN 1 /* open new channel */
@@ -189,4 +194,14 @@ extern void goldfish_pipe_wake( void* hwpipe, unsigned flags );
void pipe_dev_init(void);
+struct access_params{
+ uint32_t channel;
+ uint32_t size;
+ uint32_t address;
+ uint32_t cmd;
+ uint32_t result;
+ /* reserved for future extension */
+ uint32_t flags;
+};
+
#endif /* _HW_GOLDFISH_PIPE_H */
diff --git a/hw/mips-bios.h b/hw/mips-bios.h
new file mode 100644
index 0000000..b4b88ac
--- /dev/null
+++ b/hw/mips-bios.h
@@ -0,0 +1,8 @@
+#include "cpu.h"
+
+#define BIOS_SIZE (4 * 1024 * 1024)
+#ifdef TARGET_WORDS_BIGENDIAN
+#define BIOS_FILENAME "mips_bios.bin"
+#else
+#define BIOS_FILENAME "mipsel_bios.bin"
+#endif
diff --git a/hw/mips.h b/hw/mips.h
new file mode 100644
index 0000000..5fd72bb
--- /dev/null
+++ b/hw/mips.h
@@ -0,0 +1,43 @@
+#ifndef HW_MIPS_H
+#define HW_MIPS_H
+/* Definitions for mips board emulation. */
+
+/* gt64xxx.c */
+PCIBus *pci_gt64120_init(qemu_irq *pic);
+
+/* ds1225y.c */
+void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
+void ds1225y_set_protection(void *opaque, int protection);
+
+/* g364fb.c */
+int g364fb_mm_init(target_phys_addr_t vram_base,
+ target_phys_addr_t ctrl_base, int it_shift,
+ qemu_irq irq);
+
+/* mipsnet.c */
+void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
+
+/* jazz_led.c */
+extern void jazz_led_init(target_phys_addr_t base);
+
+/* mips_int.c */
+extern void cpu_mips_irq_init_cpu(CPUState *env);
+
+/* mips_timer.c */
+extern void cpu_mips_clock_init(CPUState *);
+
+/* rc4030.c */
+typedef struct rc4030DMAState *rc4030_dma;
+void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
+void rc4030_dma_read(void *dma, uint8_t *buf, int len);
+void rc4030_dma_write(void *dma, uint8_t *buf, int len);
+
+void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
+ qemu_irq **irqs, rc4030_dma **dmas);
+
+/* dp8393x.c */
+void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+ qemu_irq irq, void* mem_opaque,
+ void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
+
+#endif
diff --git a/hw/mips_int.c b/hw/mips_int.c
new file mode 100644
index 0000000..ad48b4f
--- /dev/null
+++ b/hw/mips_int.c
@@ -0,0 +1,45 @@
+#include "hw.h"
+#include "mips.h"
+#include "cpu.h"
+
+/* Raise IRQ to CPU if necessary. It must be called every time the active
+ IRQ may change */
+void cpu_mips_update_irq(CPUState *env)
+{
+ if ((env->CP0_Status & (1 << CP0St_IE)) &&
+ !(env->CP0_Status & (1 << CP0St_EXL)) &&
+ !(env->CP0_Status & (1 << CP0St_ERL)) &&
+ !(env->hflags & MIPS_HFLAG_DM)) {
+ if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
+ !(env->interrupt_request & CPU_INTERRUPT_HARD)) {
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+ } else
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+}
+
+static void cpu_mips_irq_request(void *opaque, int irq, int level)
+{
+ CPUState *env = (CPUState *)opaque;
+
+ if (irq < 0 || irq > 7)
+ return;
+
+ if (level) {
+ env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
+ } else {
+ env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
+ }
+ cpu_mips_update_irq(env);
+}
+
+void cpu_mips_irq_init_cpu(CPUState *env)
+{
+ qemu_irq *qi;
+ int i;
+
+ qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
+ for (i = 0; i < 8; i++) {
+ env->irq[i] = qi[i];
+ }
+}
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
new file mode 100644
index 0000000..b69d7c3
--- /dev/null
+++ b/hw/mips_r4k.c
@@ -0,0 +1,311 @@
+/*
+ * QEMU/MIPS pseudo-board
+ *
+ * emulates a simple machine with ISA-like bus.
+ * ISA IO space mapped to the 0x14000000 (PHYS) and
+ * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
+ * All peripherial devices are attached to this "bus" with
+ * the standard PC ISA addresses.
+*/
+#include "hw.h"
+#include "mips.h"
+#include "pc.h"
+#include "isa.h"
+#include "net.h"
+#include "sysemu.h"
+#include "boards.h"
+#include "flash.h"
+#include "qemu-log.h"
+#include "mips-bios.h"
+#include "ide.h"
+#include "loader.h"
+#include "elf.h"
+
+#define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff)
+
+#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
+
+#define MAX_IDE_BUS 2
+
+static const int ide_iobase[2] = { 0x1f0, 0x170 };
+static const int ide_iobase2[2] = { 0x3f6, 0x376 };
+static const int ide_irq[2] = { 14, 15 };
+
+static PITState *pit; /* PIT i8254 */
+
+/* i8254 PIT is attached to the IRQ0 at PIC i8259 */
+
+static struct _loaderparams {
+ int ram_size;
+ const char *kernel_filename;
+ const char *kernel_cmdline;
+ const char *initrd_filename;
+} loaderparams;
+
+static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ if ((addr & 0xffff) == 0 && val == 42)
+ qemu_system_reset_request ();
+ else if ((addr & 0xffff) == 4 && val == 42)
+ qemu_system_shutdown_request ();
+}
+
+static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
+{
+ return 0;
+}
+
+static CPUWriteMemoryFunc * const mips_qemu_write[] = {
+ &mips_qemu_writel,
+ &mips_qemu_writel,
+ &mips_qemu_writel,
+};
+
+static CPUReadMemoryFunc * const mips_qemu_read[] = {
+ &mips_qemu_readl,
+ &mips_qemu_readl,
+ &mips_qemu_readl,
+};
+
+static int mips_qemu_iomemtype = 0;
+
+typedef struct ResetData {
+ CPUState *env;
+ uint64_t vector;
+} ResetData;
+
+static int64_t load_kernel(void)
+{
+ int64_t entry, kernel_low, kernel_high;
+ long kernel_size, initrd_size, params_size;
+ ram_addr_t initrd_offset;
+ uint32_t *params_buf;
+ int big_endian;
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ big_endian = 1;
+#else
+ big_endian = 0;
+#endif
+ kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
+ (uint64_t *)&entry, (uint64_t *)&kernel_low,
+ (uint64_t *)&kernel_high, big_endian, ELF_MACHINE, 1);
+ if (kernel_size >= 0) {
+ if ((entry & ~0x7fffffffULL) == 0x80000000)
+ entry = (int32_t)entry;
+ } else {
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ loaderparams.kernel_filename);
+ exit(1);
+ }
+
+ /* load initrd */
+ initrd_size = 0;
+ initrd_offset = 0;
+ if (loaderparams.initrd_filename) {
+ initrd_size = get_image_size (loaderparams.initrd_filename);
+ if (initrd_size > 0) {
+ initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
+ if (initrd_offset + initrd_size > ram_size) {
+ fprintf(stderr,
+ "qemu: memory too small for initial ram disk '%s'\n",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+ initrd_size = load_image_targphys(loaderparams.initrd_filename,
+ initrd_offset,
+ ram_size - initrd_offset);
+ }
+ if (initrd_size == (target_ulong) -1) {
+ fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
+ loaderparams.initrd_filename);
+ exit(1);
+ }
+ }
+
+ /* Store command line. */
+ params_size = 264;
+ params_buf = qemu_malloc(params_size);
+
+ params_buf[0] = tswap32(ram_size);
+ params_buf[1] = tswap32(0x12345678);
+
+ if (initrd_size > 0) {
+ snprintf((char *)params_buf + 8, 256, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
+ PHYS_TO_VIRT((uint32_t)initrd_offset),
+ initrd_size, loaderparams.kernel_cmdline);
+ } else {
+ snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline);
+ }
+
+ rom_add_blob_fixed("params", params_buf, params_size,
+ (16 << 20) - 264);
+
+ return entry;
+}
+
+static void main_cpu_reset(void *opaque)
+{
+ ResetData *s = (ResetData *)opaque;
+ CPUState *env = s->env;
+
+ cpu_reset(env);
+ env->active_tc.PC = s->vector;
+}
+
+static const int sector_len = 32 * 1024;
+static
+void mips_r4k_init (ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ char *filename;
+ ram_addr_t ram_offset;
+ ram_addr_t bios_offset;
+ int bios_size;
+ CPUState *env;
+ ResetData *reset_info;
+ RTCState *rtc_state;
+ int i;
+ qemu_irq *i8259;
+ DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ DriveInfo *dinfo;
+
+ /* init CPUs */
+ if (cpu_model == NULL) {
+#ifdef TARGET_MIPS64
+ cpu_model = "R4000";
+#else
+ cpu_model = "24Kf";
+#endif
+ }
+ env = cpu_init(cpu_model);
+ if (!env) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ reset_info = qemu_mallocz(sizeof(ResetData));
+ reset_info->env = env;
+ reset_info->vector = env->active_tc.PC;
+ qemu_register_reset(main_cpu_reset, reset_info);
+
+ /* allocate RAM */
+ if (ram_size > (256 << 20)) {
+ fprintf(stderr,
+ "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
+ ((unsigned int)ram_size / (1 << 20)));
+ exit(1);
+ }
+ ram_offset = qemu_ram_alloc(ram_size);
+
+ cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+
+ if (!mips_qemu_iomemtype) {
+ mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
+ mips_qemu_write, NULL);
+ }
+ cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
+
+ /* Try to load a BIOS image. If this fails, we continue regardless,
+ but initialize the hardware ourselves. When a kernel gets
+ preloaded we also initialize the hardware, since the BIOS wasn't
+ run. */
+ if (bios_name == NULL)
+ bios_name = BIOS_FILENAME;
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ bios_size = get_image_size(filename);
+ } else {
+ bios_size = -1;
+ }
+ if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
+ bios_offset = qemu_ram_alloc(BIOS_SIZE);
+ cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
+ bios_offset | IO_MEM_ROM);
+
+ load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
+ } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
+ uint32_t mips_rom = 0x00400000;
+ bios_offset = qemu_ram_alloc(mips_rom);
+ if (!pflash_cfi01_register(0x1fc00000, bios_offset,
+ dinfo->bdrv, sector_len, mips_rom / sector_len,
+ 4, 0, 0, 0, 0)) {
+ fprintf(stderr, "qemu: Error registering flash memory.\n");
+ }
+ }
+ else {
+ /* not fatal */
+ fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
+ bios_name);
+ }
+ if (filename) {
+ qemu_free(filename);
+ }
+
+ if (kernel_filename) {
+ loaderparams.ram_size = ram_size;
+ loaderparams.kernel_filename = kernel_filename;
+ loaderparams.kernel_cmdline = kernel_cmdline;
+ loaderparams.initrd_filename = initrd_filename;
+ reset_info->vector = load_kernel();
+ }
+
+ /* Init CPU internal devices */
+ cpu_mips_irq_init_cpu(env);
+ cpu_mips_clock_init(env);
+
+ /* The PIC is attached to the MIPS CPU INT0 pin */
+ i8259 = i8259_init(env->irq[2]);
+ isa_bus_new(NULL);
+ isa_bus_irqs(i8259);
+
+ rtc_state = rtc_init(2000);
+
+ /* Register 64 KB of ISA IO space at 0x14000000 */
+ isa_mmio_init(0x14000000, 0x00010000);
+ isa_mem_base = 0x10000000;
+
+ pit = pit_init(0x40, i8259[0]);
+
+ for(i = 0; i < MAX_SERIAL_PORTS; i++) {
+ if (serial_hds[i]) {
+ serial_isa_init(i, serial_hds[i]);
+ }
+ }
+
+ isa_vga_init();
+
+ if (nd_table[0].vlan)
+ isa_ne2000_init(0x300, 9, &nd_table[0]);
+
+ if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
+ fprintf(stderr, "qemu: too many IDE bus\n");
+ exit(1);
+ }
+
+ for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
+ hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
+ }
+
+ for(i = 0; i < MAX_IDE_BUS; i++)
+ isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
+ hd[MAX_IDE_DEVS * i],
+ hd[MAX_IDE_DEVS * i + 1]);
+
+ isa_create_simple("i8042");
+}
+
+static QEMUMachine mips_machine = {
+ .name = "mips",
+ .desc = "mips r4k platform",
+ .init = mips_r4k_init,
+};
+
+static void mips_machine_init(void)
+{
+ qemu_register_machine(&mips_machine);
+}
+
+machine_init(mips_machine_init);
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
new file mode 100644
index 0000000..6bae90b
--- /dev/null
+++ b/hw/mips_timer.c
@@ -0,0 +1,109 @@
+#include "hw.h"
+#include "mips.h"
+#include "qemu-timer.h"
+
+#define TIMER_FREQ 100 * 1000 * 1000
+
+/* XXX: do not use a global */
+uint32_t cpu_mips_get_random (CPUState *env)
+{
+ static uint32_t lfsr = 1;
+ static uint32_t prev_idx = 0;
+ uint32_t idx;
+ /* Don't return same value twice, so get another value */
+ do {
+ lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
+ idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+ } while (idx == prev_idx);
+ prev_idx = idx;
+ return idx;
+}
+
+/* MIPS R4K timer */
+uint32_t cpu_mips_get_count (CPUState *env)
+{
+ if (env->CP0_Cause & (1 << CP0Ca_DC))
+ return env->CP0_Count;
+ else
+ return env->CP0_Count +
+ (uint32_t)muldiv64(qemu_get_clock(vm_clock),
+ TIMER_FREQ, get_ticks_per_sec());
+}
+
+static void cpu_mips_timer_update(CPUState *env)
+{
+ uint64_t now, next;
+ uint32_t wait;
+
+ now = qemu_get_clock(vm_clock);
+ wait = env->CP0_Compare - env->CP0_Count -
+ (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
+ next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
+ qemu_mod_timer(env->timer, next);
+}
+
+void cpu_mips_store_count (CPUState *env, uint32_t count)
+{
+ if (env->CP0_Cause & (1 << CP0Ca_DC))
+ env->CP0_Count = count;
+ else {
+ /* Store new count register */
+ env->CP0_Count =
+ count - (uint32_t)muldiv64(qemu_get_clock(vm_clock),
+ TIMER_FREQ, get_ticks_per_sec());
+ /* Update timer timer */
+ cpu_mips_timer_update(env);
+ }
+}
+
+void cpu_mips_store_compare (CPUState *env, uint32_t value)
+{
+ env->CP0_Compare = value;
+ if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
+ cpu_mips_timer_update(env);
+ if (env->insn_flags & ISA_MIPS32R2)
+ env->CP0_Cause &= ~(1 << CP0Ca_TI);
+ qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+}
+
+void cpu_mips_start_count(CPUState *env)
+{
+ cpu_mips_store_count(env, env->CP0_Count);
+}
+
+void cpu_mips_stop_count(CPUState *env)
+{
+ /* Store the current value */
+ env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock),
+ TIMER_FREQ, get_ticks_per_sec());
+}
+
+static void mips_timer_cb (void *opaque)
+{
+ CPUState *env;
+
+ env = opaque;
+#if 0
+ qemu_log("%s\n", __func__);
+#endif
+
+ if (env->CP0_Cause & (1 << CP0Ca_DC))
+ return;
+
+ /* ??? This callback should occur when the counter is exactly equal to
+ the comparator value. Offset the count by one to avoid immediately
+ retriggering the callback before any virtual time has passed. */
+ env->CP0_Count++;
+ cpu_mips_timer_update(env);
+ env->CP0_Count--;
+ if (env->insn_flags & ISA_MIPS32R2)
+ env->CP0_Cause |= 1 << CP0Ca_TI;
+ qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+}
+
+void cpu_mips_clock_init (CPUState *env)
+{
+ env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
+ env->CP0_Compare = 0;
+ cpu_mips_store_count(env, 1);
+}
generated by cgit v1.1 at 2025-08-04 03:51:48 +0000