From 55ff318b4e5382074e2049c996cb6df1041aff1b Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Fri, 3 Aug 2012 14:35:52 -0700 Subject: [MIPS] Speed up software refill handler Emulating each instruction of the software refill handler has a significant impact on the overall performance of QEMU because of the overhead of emulating the various CP0 instructions to accurately reflect the machine state. Running the software TLB handler takes the equivalent of 1000's of machine cycles. This patch implements a pseudo hardware TLB refill handler that significantly reduces the impact of refilling the TLB to bring it more inline with what would be observed on a real target. Signed-off-by: Steven Hill Signed-off-by: Chris Dearman Signed-off-by: Yajin --- target-mips/cpu.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'target-mips/cpu.h') diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7c04fbe..46519e3 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -39,7 +39,6 @@ struct r4k_tlb_t { typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; struct CPUMIPSTLBContext { uint32_t nb_tlb; - uint32_t tlb_in_use; int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type); void (*helper_tlbwi) (void); void (*helper_tlbwr) (void); @@ -630,7 +629,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu); #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault void do_interrupt (CPUState *env); -void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address, int rw); -- cgit v1.1