From 3fdb405597f0e062a9bb8af20199c5e67f0f764c Mon Sep 17 00:00:00 2001 From: Martin Storsjo Date: Fri, 13 Apr 2012 14:17:30 +0300 Subject: avcenc: Fix the gcc inline assembly constraints Use +r for registers whose value is used as input to the block. Also switch input registers to output registers with +r, for registers that are modified by the assembly block (SUB_SAD in sad_inline.h). Without this, the inline assembly fails on modern gcc versions (tested on gcc 4.6), where the intended input value never is loaded into the registers, causing segfaults at runtime. Currently this assembly isn't used, but this change makes it work properly if enabled. Change-Id: I37c247cd5c8aff213445e31ab3bd33d8f0f37e05 --- .../codecs/avc/enc/src/sad_halfpel_inline.h | 4 ++-- media/libstagefright/codecs/avc/enc/src/sad_inline.h | 14 +++++++------- media/libstagefright/codecs/avc/enc/src/sad_mb_offset.h | 16 ++++++++-------- 3 files changed, 17 insertions(+), 17 deletions(-) (limited to 'media/libstagefright') diff --git a/media/libstagefright/codecs/avc/enc/src/sad_halfpel_inline.h b/media/libstagefright/codecs/avc/enc/src/sad_halfpel_inline.h index 4eb9b00..0c5a5a3 100644 --- a/media/libstagefright/codecs/avc/enc/src/sad_halfpel_inline.h +++ b/media/libstagefright/codecs/avc/enc/src/sad_halfpel_inline.h @@ -81,7 +81,7 @@ extern "C" "rsbs %1, %1, %2, asr #1\n\t" "rsbmi %1, %1, #0\n\t" "add %0, %0, %1" - : "=r"(sad), "=r"(tmp) + : "+r"(sad), "+r"(tmp) : "r"(tmp2) ); @@ -94,7 +94,7 @@ extern "C" "rsbs %1, %2, %1, asr #2\n\t" "rsbmi %1, %1, #0\n\t" "add %0, %0, %1" - : "=r"(sad), "=r"(tmp) + : "+r"(sad), "+r"(tmp) : "r"(tmp2) ); diff --git a/media/libstagefright/codecs/avc/enc/src/sad_inline.h b/media/libstagefright/codecs/avc/enc/src/sad_inline.h index 6695d63..a540d86 100644 --- a/media/libstagefright/codecs/avc/enc/src/sad_inline.h +++ b/media/libstagefright/codecs/avc/enc/src/sad_inline.h @@ -347,8 +347,8 @@ SadMBOffset1: "rsbs %1, %1, %2\n\t" "rsbmi %1, %1, #0\n\t" "add %0, %0, %1" - : "=r"(sad) - : "r"(tmp), "r"(tmp2) + : "+r"(sad), "+r"(tmp) + : "r"(tmp2) ); return sad; } @@ -366,7 +366,7 @@ SadMBOffset1: "RSB %1, %1, %1, lsl #8\n\t" "ADD %0, %0, %1, asr #7\n\t" "EOR %0, %0, %1, asr #7" - : "=r"(src1), "=&r"(x7) + : "+r"(src1), "=&r"(x7) : "r"(src2), "r"(mask) ); @@ -385,7 +385,7 @@ SadMBOffset1: "RSB %1, %1, %1, lsl #8\n\t" "SUB %0, %0, %1, asr #7\n\t" "EOR %0, %0, %1, asr #7" - : "=r"(src1), "=&r"(x7) + : "+r"(src1), "=&r"(x7) : "r"(src2), "r"(mask) ); @@ -399,7 +399,7 @@ SadMBOffset1: "SBC %0, %0, %3\n\t" \ "BIC %3, %4, %3\n\t" \ "ADD %2, %2, %3, lsr #8" \ - : "=&r" (x5), "=&r" (x10), "=&r" (x4), "=&r" (x11) \ + : "+r" (x5), "+r" (x10), "+r" (x4), "+r" (x11) \ : "r" (x6) \ ); @@ -467,10 +467,10 @@ LOOP_SAD0: /****** process 8 pixels ******/ x11 = *((int32*)(ref + 4)); - __asm__ volatile("LDR %0, [%1], %2": "=&r"(x10), "=r"(ref): "r"(lx)); + __asm__ volatile("LDR %0, [%1], %2": "=&r"(x10), "+r"(ref): "r"(lx)); //x10 = *((int32*)ref); ref+=lx; x14 = *((int32*)(blk + 4)); - __asm__ volatile("LDR %0, [%1], #16": "=&r"(x12), "=r"(blk)); + __asm__ volatile("LDR %0, [%1], #16": "=&r"(x12), "+r"(blk)); /* process x11 & x14 */ x11 = sad_4pixel(x11, x14, x9); diff --git a/media/libstagefright/codecs/avc/enc/src/sad_mb_offset.h b/media/libstagefright/codecs/avc/enc/src/sad_mb_offset.h index 0165360..33297ab 100644 --- a/media/libstagefright/codecs/avc/enc/src/sad_mb_offset.h +++ b/media/libstagefright/codecs/avc/enc/src/sad_mb_offset.h @@ -239,7 +239,7 @@ LOOP_SAD2: #elif (NUMBER==1) LOOP_SAD1: #endif - __asm__ volatile("BIC %0, %0, #3": "=r"(ref)); + __asm__ volatile("BIC %0, %0, #3": "+r"(ref)); /****** process 8 pixels ******/ x11 = *((int32*)(ref + 12)); x12 = *((int32*)(ref + 16)); @@ -252,7 +252,7 @@ LOOP_SAD1: "BIC %0, %0, %1, lsl #24\n\t" "MVN %1, %1, lsr #8\n\t" "BIC %1, %1, %2, lsl #24" - : "=&r"(x10), "=&r"(x11) + : "+r"(x10), "+r"(x11) : "r"(x12) ); #elif (SHIFT==16) @@ -261,7 +261,7 @@ LOOP_SAD1: "BIC %0, %0, %1, lsl #16\n\t" "MVN %1, %1, lsr #16\n\t" "BIC %1, %1, %2, lsl #16" - : "=&r"(x10), "=&r"(x11) + : "+r"(x10), "+r"(x11) : "r"(x12) ); #elif (SHIFT==24) @@ -270,7 +270,7 @@ LOOP_SAD1: "BIC %0, %0, %1, lsl #8\n\t" "MVN %1, %1, lsr #24\n\t" "BIC %1, %1, %2, lsl #8" - : "=&r"(x10), "=&r"(x11) + : "+r"(x10), "+r"(x11) : "r"(x12) ); #endif @@ -297,7 +297,7 @@ LOOP_SAD1: "BIC %0, %0, %1, lsl #24\n\t" "MVN %1, %1, lsr #8\n\t" "BIC %1, %1, %2, lsl #24" - : "=&r"(x10), "=&r"(x11) + : "+r"(x10), "+r"(x11) : "r"(x12) ); #elif (SHIFT==16) @@ -306,7 +306,7 @@ LOOP_SAD1: "BIC %0, %0, %1, lsl #16\n\t" "MVN %1, %1, lsr #16\n\t" "BIC %1, %1, %2, lsl #16" - : "=&r"(x10), "=&r"(x11) + : "+r"(x10), "+r"(x11) : "r"(x12) ); #elif (SHIFT==24) @@ -315,11 +315,11 @@ LOOP_SAD1: "BIC %0, %0, %1, lsl #8\n\t" "MVN %1, %1, lsr #24\n\t" "BIC %1, %1, %2, lsl #8" - : "=&r"(x10), "=&r"(x11) + : "+r"(x10), "+r"(x11) : "r"(x12) ); #endif - __asm__ volatile("LDR %0, [%1], #16": "=&r"(x12), "=r"(blk)); + __asm__ volatile("LDR %0, [%1], #16": "=&r"(x12), "+r"(blk)); /* process x11 & x14 */ x11 = sad_4pixelN(x11, x14, x9); -- cgit v1.1