diff options
Diffstat (limited to 'gcbv/mirror')
| -rw-r--r-- | gcbv/mirror/gcbv.c | 4156 | ||||
| -rw-r--r-- | gcbv/mirror/gcdbglog.c | 1696 | ||||
| -rw-r--r-- | gcbv/mirror/include/cache-2dmanager.h | 103 | ||||
| -rw-r--r-- | gcbv/mirror/include/gcdbglog.h | 412 | ||||
| -rw-r--r-- | gcbv/mirror/include/gcerror.h | 254 | ||||
| -rw-r--r-- | gcbv/mirror/include/gcioctl.h | 263 | ||||
| -rw-r--r-- | gcbv/mirror/include/gclist.h | 630 | ||||
| -rw-r--r-- | gcbv/mirror/include/gcreg.h | 8827 | ||||
| -rw-r--r-- | gcbv/mirror/include/gcx.h | 100 |
9 files changed, 16441 insertions, 0 deletions
diff --git a/gcbv/mirror/gcbv.c b/gcbv/mirror/gcbv.c new file mode 100644 index 0000000..9f913ae --- /dev/null +++ b/gcbv/mirror/gcbv.c @@ -0,0 +1,4156 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "gcmain.h" + +#define GCZONE_NONE 0 +#define GCZONE_ALL (~0U) +#define GCZONE_MAPPING (1 << 0) +#define GCZONE_BUFFER (1 << 1) +#define GCZONE_FIXUP (1 << 2) +#define GCZONE_FORMAT (1 << 3) +#define GCZONE_COLOR (1 << 4) +#define GCZONE_BLEND (1 << 5) +#define GCZONE_DEST (1 << 6) +#define GCZONE_SURF (1 << 7) +#define GCZONE_DO_FILL (1 << 8) +#define GCZONE_DO_BLIT (1 << 9) +#define GCZONE_DO_FILTER (1 << 10) +#define GCZONE_CLIP (1 << 11) +#define GCZONE_BATCH (1 << 12) +#define GCZONE_BLIT (1 << 13) +#define GCZONE_CACHE (1 << 14) + +GCDBG_FILTERDEF(gcbv, GCZONE_NONE, + "mapping", + "buffer", + "fixup", + "format", + "color", + "blend", + "dest", + "surf", + "do_fill", + "do_blit", + "do_filter", + "clip", + "batch", + "blit", + "cache") + + +/******************************************************************************* +** Miscellaneous defines and macros. +*/ + +#define EQ_SIZE(rect1, rect2) \ +( \ + (rect1.width == rect2.width) && (rect1.height == rect2.height) \ +) + +#define STRUCTSIZE(structptr, lastmember) \ +( \ + (size_t) &structptr->lastmember + \ + sizeof(structptr->lastmember) - \ + (size_t) structptr \ +) + +#define GET_MAP_HANDLE(map) \ +( \ + ((struct bvbuffmapinfo *) map->handle)->handle \ +) + +#define GC_CLIP_RESET_LEFT ((unsigned short) 0) +#define GC_CLIP_RESET_TOP ((unsigned short) 0) +#define GC_CLIP_RESET_RIGHT ((unsigned short) ((1 << 15) - 1)) +#define GC_CLIP_RESET_BOTTOM ((unsigned short) ((1 << 15) - 1)) + +#define GC_BASE_ALIGN 64 + +#define GPU_CMD_SIZE (sizeof(unsigned int) * 2) + +#define GC_BUFFER_RESERVE \ +( \ + sizeof(struct gcmopipesel) + \ + sizeof(struct gcmommumaster) + \ + sizeof(struct gcmommuflush) + \ + sizeof(struct gcmosignal) + \ + sizeof(struct gccmdend) \ +) + +#if GCDEBUG_ENABLE +#define GCDUMPSCHEDULE() { \ + struct list_head *__temphead__; \ + struct gcschedunmap *__tempunmap__; \ + GCDBG(GCZONE_MAPPING, "scheduled unmaps:\n"); \ + list_for_each(__temphead__, &batch->unmap) { \ + __tempunmap__ = list_entry(__temphead__, \ + struct gcschedunmap, \ + link); \ + GCDBG(GCZONE_MAPPING, \ + " handle = 0x%08X\n", \ + (unsigned int) __tempunmap__->handle); \ + } \ +} +#else +#define GCDUMPSCHEDULE() +#endif + + +/******************************************************************************* +** Internal structures. +*/ + +/* Used by blitters to define an array of valid sources. */ +struct srcinfo { + int index; + union bvinbuff buf; + struct bvsurfgeom *geom; + struct bvrect *rect; +}; + +/* bvbuffmap struct attachment. */ +struct bvbuffmapinfo { + /* Mapped handle for the buffer. */ + unsigned long handle; + + /* Number of times the client explicitly mapped this buffer. */ + int usermap; + + /* Number of times implicit mapping happened. */ + int automap; +}; + +/* Operation finalization call. */ +struct gcbatch; +typedef enum bverror (*gcbatchend) (struct bvbltparams *bltparams, + struct gcbatch *batch); + +/* Blit states. */ +struct gcblit { + unsigned int srccount; + unsigned int multisrc; + unsigned short rop; +}; + +/* Batch header. */ +struct gcbatch { + /* Used to ID structure version. */ + unsigned int structsize; + + /* Batch change flags. */ + unsigned long batchflags; + + /* Pointer to the function to finalize the current operation. */ + gcbatchend batchend; + + /* State of the current operation. */ + struct gcblit gcblit; + + /* Clipping deltas; used to correct the source coordinates for + * single source blits. */ + int deltaleft; + int deltatop; + int deltaright; + int deltabottom; + + /* Destination format. */ + struct bvformatxlate *dstformat; + + /* Destination rectangle coordinates. */ + unsigned short dstleft; + unsigned short dsttop; + unsigned short dstright; + unsigned short dstbottom; + + /* Destination base address alignment offset in pixels. */ + unsigned int dstoffset; + +#if GCDEBUG_ENABLE + /* Rectangle validation storage. */ + struct bvrect prevdstrect; + struct bvrect prevsrc1rect; + struct bvrect prevsrc2rect; + struct bvrect prevmaskrect; +#endif + + /* Total size of the command buffer. */ + unsigned int size; + + /* Command buffer list. */ + struct gcbuffer *bufhead; + struct gcbuffer *buftail; + + /* Scheduled implicit unmappings (gcschedunmap). */ + struct list_head unmap; +}; + +/* Vacant batch header. */ +struct gcvacbatch { + struct gcvacbatch *next; +}; + +/* Callback information. */ +struct gccallbackinfo { + /* BLTsville callback function. */ + void (*callbackfn) (struct bvcallbackerror *err, + unsigned long callbackdata); + + /* Callback data. */ + unsigned long callbackdata; + + /* Previous/next callback information. */ + struct list_head link; +}; + +/* Driver context. */ +struct gccontext { + /* Last generated error message. */ + char bverrorstr[128]; + + /* Dynamically allocated structure cache. */ + struct list_head vac_unmap; /* gcschedunmap */ + struct bvbuffmap *vac_buffmap; + struct gcbuffer *vac_buffers; + struct gcfixup *vac_fixups; + struct gcvacbatch *vac_batches; + + /* Callback lists. */ + struct list_head callbacklist; + struct list_head callbackvac; + + /* Access locks. */ + GCLOCK_TYPE batchlock; + GCLOCK_TYPE bufferlock; + GCLOCK_TYPE fixuplock; + GCLOCK_TYPE maplock; + GCLOCK_TYPE callbacklock; +}; + +static struct gccontext gccontext; + + +/******************************************************************************* + * Debugging. + */ + +#if GCDEBUG_ENABLE +#define GCDUMPBATCH(batch) \ + dumpbatch(batch) + +static void dumpbatch(struct gcbatch *batch) +{ + if ((GCDBGFILTER.zone & GCZONE_BATCH) != 0) { + struct gcbuffer *buffer; + unsigned int i, size; + struct gcfixup *fixup; + + GCDBG(GCZONE_BATCH, "BATCH DUMP (0x%08X)\n", + (unsigned int) batch); + + buffer = batch->bufhead; + while (buffer != NULL) { + fixup = buffer->fixuphead; + while (fixup != NULL) { + GCDBG(GCZONE_BATCH, + " Fixup table @ 0x%08X, count = %d:\n", + (unsigned int) fixup, fixup->count); + + for (i = 0; i < fixup->count; i += 1) { + GCDBG(GCZONE_BATCH, " [%02d]" + " buffer offset = 0x%08X," + " surface offset = 0x%08X\n", + i, + fixup->fixup[i].dataoffset * 4, + fixup->fixup[i].surfoffset); + } + + fixup = fixup->next; + } + + size = (unsigned char *) buffer->tail + - (unsigned char *) buffer->head; + GCDUMPBUFFER(GCZONE_BUFFER, buffer->head, 0, size); + + buffer = buffer->next; + } + } +} +#else +# define GCDUMPBATCH(...) +#endif + + +/******************************************************************************* + * Error handling. + */ + +#define SETERROR(message) \ +do { \ + snprintf(gccontext.bverrorstr, sizeof(gccontext.bverrorstr), \ + "%s(%d): " message, __func__, __LINE__); \ + GCDUMPSTRING("%s\n", gccontext.bverrorstr); \ +} while (0) + +#define SETERRORARG(message, arg) \ +do { \ + snprintf(gccontext.bverrorstr, sizeof(gccontext.bverrorstr), \ + "%s(%d): " message, __func__, __LINE__, arg); \ + GCDUMPSTRING("%s\n", gccontext.bverrorstr); \ +} while (0) + +#define BVSETERROR(error, message) \ +do { \ + SETERROR(message); \ + bverror = error; \ +} while (0) + +#define BVSETERRORARG(error, message, arg) \ +do { \ + SETERRORARG(message, arg); \ + bverror = error; \ +} while (0) + +#define BVSETBLTERROR(error, message) \ +do { \ + BVSETERROR(error, message); \ + bltparams->errdesc = gccontext.bverrorstr; \ +} while (0) + +#define BVSETBLTERRORARG(error, message, arg) \ +do { \ + BVSETERRORARG(error, message, arg); \ + bltparams->errdesc = gccontext.bverrorstr; \ +} while (0) + +#define BVSETSURFERROR(errorid, errordesc) \ +do { \ + snprintf(gccontext.bverrorstr, sizeof(gccontext.bverrorstr), \ + g_surferr[errorid].message, __func__, __LINE__, errordesc.id); \ + GCDUMPSTRING("%s\n", gccontext.bverrorstr); \ + bverror = errordesc.base + g_surferr[errorid].offset; \ +} while (0) + +#define BVSETBLTSURFERROR(errorid, errordesc) \ +do { \ + BVSETSURFERROR(errorid, errordesc); \ + bltparams->errdesc = gccontext.bverrorstr; \ +} while (0) + +#define GCBVERR_DESC 0 +#define GCBVERR_DESC_VERS 1 +#define GCBVERR_DESC_VIRTADDR 2 +#define GCBVERR_TILE 3 +#define GCBVERR_TILE_VERS 4 +#define GCBVERR_TILE_VIRTADDR 5 +#define GCBVERR_GEOM 6 +#define GCBVERR_GEOM_VERS 7 +#define GCBVERR_GEOM_FORMAT 8 + +struct bvsurferrorid { + char *id; + enum bverror base; +}; + +struct bvsurferror { + unsigned int offset; + char *message; +}; + +static struct bvsurferror g_surferr[] = { + /* GCBVERR_DESC */ + { 0, "%s(%d): %s desc structure is not set" }, + + /* GCBVERR_DESC_VERS */ + { 100, "%s(%d): %s desc structure has invalid size" }, + + /* GCBVERR_DESC_VIRTADDR */ + { 200, "%s(%d): %s desc virtual pointer is not set" }, + + /* GCBVERR_TILE: FIXME/TODO define error code */ + { 0, "%s(%d): %s tileparams structure is not set" }, + + /* GCBVERR_TILE_VERS */ + { 3000, "%s(%d): %s tileparams structure has invalid size" }, + + /* GCBVERR_TILE_VIRTADDR: FIXME/TODO define error code */ + { 200, "%s(%d): %s tileparams virtual pointer is not set" }, + + /* GCBVERR_GEOM */ + { 1000, "%s(%d): %s geom structure is not set" }, + + /* GCBVERR_GEOM_VERS */ + { 1100, "%s(%d): %s geom structure has invalid size" }, + + /* GCBVERR_GEOM_FORMAT */ + { 1200, "%s(%d): %s invalid format specified" }, +}; + +static struct bvsurferrorid g_destsurferr = { "dst", BVERR_DSTDESC }; +static struct bvsurferrorid g_src1surferr = { "src1", BVERR_SRC1DESC }; +static struct bvsurferrorid g_src2surferr = { "src2", BVERR_SRC2DESC }; +static struct bvsurferrorid g_masksurferr = { "mask", BVERR_MASKDESC }; + + +/******************************************************************************* + * Callback info management. + */ + +static enum bverror get_callbackinfo(struct gccallbackinfo **gccallbackinfo) +{ + enum bverror bverror; + struct gccallbackinfo *temp; + + /* Lock access to callback info lists. */ + GCLOCK(&gccontext.callbacklock); + + if (list_empty(&gccontext.callbackvac)) { + temp = gcalloc(struct gccallbackinfo, + sizeof(struct gccallbackinfo)); + if (temp == NULL) { + bverror = BVERR_OOM; + goto exit; + } + list_add(&temp->link, &gccontext.callbacklist); + } else { + struct list_head *head; + head = gccontext.callbackvac.next; + temp = list_entry(head, struct gccallbackinfo, link); + list_move(head, &gccontext.callbacklist); + } + + *gccallbackinfo = temp; + bverror = BVERR_NONE; + +exit: + /* Unlock access to callback info lists. */ + GCUNLOCK(&gccontext.callbacklock); + + return bverror; +} + +static void free_callback(struct gccallbackinfo *gccallbackinfo) +{ + /* Lock access to callback info lists. */ + GCLOCK(&gccontext.callbacklock); + + list_move(&gccallbackinfo->link, &gccontext.callbackvac); + + /* Unlock access to callback info lists. */ + GCUNLOCK(&gccontext.callbacklock); +} + +void gccallback(void *callbackparam) +{ + struct gccallbackinfo *gccallbackinfo; + + GCENTER(GCZONE_BLIT); + + gccallbackinfo = (struct gccallbackinfo *) callbackparam; + GCDBG(GCZONE_BLIT, "bltsville_callback = 0x%08X\n", + (unsigned int) gccallbackinfo->callbackfn); + GCDBG(GCZONE_BLIT, "bltsville_param = 0x%08X\n", + (unsigned int) gccallbackinfo->callbackdata); + + gccallbackinfo->callbackfn(NULL, gccallbackinfo->callbackdata); + free_callback(gccallbackinfo); + + GCEXIT(GCZONE_BLIT); +} + + +/******************************************************************************* + * Memory management. + */ + +static enum bverror do_map(struct bvbuffdesc *bvbuffdesc, + struct gcbatch *batch, + struct bvbuffmap **map) +{ + static const int mapsize + = sizeof(struct bvbuffmap) + + sizeof(struct bvbuffmapinfo); + + enum bverror bverror; + struct bvbuffmap *bvbuffmap; + struct bvbuffmapinfo *bvbuffmapinfo; + struct bvphysdesc *bvphysdesc; + bool mappedbyothers; + struct gcmap gcmap; + unsigned int offset; + struct gcschedunmap *gcschedunmap; + + GCENTERARG(GCZONE_MAPPING, "bvbuffdesc = 0x%08X\n", + (unsigned int) bvbuffdesc); + + /* Lock access to the mapping list. */ + GCLOCK(&gccontext.maplock); + + /* Try to find existing mapping. */ + bvbuffmap = bvbuffdesc->map; + while (bvbuffmap != NULL) { + if (bvbuffmap->bv_unmap == bv_unmap) + break; + bvbuffmap = bvbuffmap->nextmap; + } + + /* Not mapped yet? */ + if (bvbuffmap == NULL) { + /* New mapping, allocate a record. */ + if (gccontext.vac_buffmap == NULL) { + bvbuffmap = gcalloc(struct bvbuffmap, mapsize); + if (bvbuffmap == NULL) { + BVSETERROR(BVERR_OOM, + "failed to allocate mapping record"); + goto fail; + } + + bvbuffmap->structsize = sizeof(struct bvbuffmap); + bvbuffmap->bv_unmap = bv_unmap; + bvbuffmap->handle = (unsigned long) (bvbuffmap + 1); + } else { + bvbuffmap = gccontext.vac_buffmap; + gccontext.vac_buffmap = bvbuffmap->nextmap; + } + + /* Setup buffer mapping. Here we need to check and make sure + * that the buffer starts at a location that is supported by + * the hw. If it is not, offset is computed and the buffer is + * extended by the value of the offset. */ + gcmap.gcerror = GCERR_NONE; + gcmap.handle = 0; + + if (bvbuffdesc->auxtype == BVAT_PHYSDESC) { + bvphysdesc = (struct bvphysdesc *) bvbuffdesc->auxptr; + + if (bvphysdesc->structsize < + STRUCTSIZE(bvphysdesc, pageoffset)) { + BVSETERROR(BVERR_BUFFERDESC_VERS, + "unsupported bvphysdesc version"); + goto fail; + } + + gcmap.buf.offset = bvphysdesc->pageoffset + & ~(GC_BASE_ALIGN - 1); + offset = bvphysdesc->pageoffset + & (GC_BASE_ALIGN - 1); + gcmap.pagesize = bvphysdesc->pagesize; + gcmap.pagearray = bvphysdesc->pagearray; + + GCDBG(GCZONE_MAPPING, "new mapping (%s):\n", + (batch == NULL) ? "explicit" : "implicit"); + GCDBG(GCZONE_MAPPING, "pagesize = %lu\n", + bvphysdesc->pagesize); + GCDBG(GCZONE_MAPPING, "pagearray = 0x%08X\n", + (unsigned int) bvphysdesc->pagearray); + GCDBG(GCZONE_MAPPING, "specified pageoffset = %lu\n", + bvphysdesc->pageoffset); + GCDBG(GCZONE_MAPPING, "aligned pageoffset = %d\n", + gcmap.buf.offset); + } else { + gcmap.buf.logical + = (void *) ((unsigned int) bvbuffdesc->virtaddr + & ~(GC_BASE_ALIGN - 1)); + offset = (unsigned int) bvbuffdesc->virtaddr + & (GC_BASE_ALIGN - 1); + gcmap.pagesize = 0; + gcmap.pagearray = NULL; + + GCDBG(GCZONE_MAPPING, "new mapping (%s):\n", + (batch == NULL) ? "explicit" : "implicit"); + GCDBG(GCZONE_MAPPING, "specified virtaddr = 0x%08X\n", + (unsigned int) bvbuffdesc->virtaddr); + GCDBG(GCZONE_MAPPING, "aligned virtaddr = 0x%08X\n", + (unsigned int) gcmap.buf.logical); + } + + gcmap.size = offset + bvbuffdesc->length; + + GCDBG(GCZONE_MAPPING, "surface offset = %d\n", offset); + GCDBG(GCZONE_MAPPING, "mapping size = %d\n", gcmap.size); + + gc_map_wrapper(&gcmap); + if (gcmap.gcerror != GCERR_NONE) { + BVSETERROR(BVERR_OOM, + "unable to allocate gccore memory"); + goto fail; + } + + /* Set map handle. */ + bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle; + bvbuffmapinfo->handle = gcmap.handle; + + /* Initialize reference counters. */ + if (batch == NULL) { + /* Explicit mapping. */ + bvbuffmapinfo->usermap = 1; + bvbuffmapinfo->automap = 0; + } else { + /* Implicit mapping; if there are existing mappings + * from other implementations, mark this an explicit + * mapping as well. */ + mappedbyothers = (bvbuffdesc->map != NULL); + GCDBG(GCZONE_MAPPING, "%smapped by others.\n", + mappedbyothers ? "" : "not "); + + bvbuffmapinfo->usermap = mappedbyothers ? 1 : 0; + bvbuffmapinfo->automap = 1; + } + + /* Add the record to the list of mappings. */ + bvbuffmap->nextmap = bvbuffdesc->map; + bvbuffdesc->map = bvbuffmap; + } else { + /* Mapping already exists. */ + bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle; + + /* Advance reference counters. */ + if (batch == NULL) { + /* Explicit mapping. */ + GCDBG(GCZONE_MAPPING, "explicit map.\n"); + bvbuffmapinfo->usermap += 1; + } else { + /* Implicit mapping. */ + GCDBG(GCZONE_MAPPING, "implicit map.\n"); + bvbuffmapinfo->automap += 1; + } + + GCDBG(GCZONE_MAPPING, "mapping exists.\n"); + } + + GCDBG(GCZONE_MAPPING, "bvbuffmap = 0x%08X\n", + (unsigned int) bvbuffmap); + GCDBG(GCZONE_MAPPING, "explicit count = %d\n", + bvbuffmapinfo->usermap); + GCDBG(GCZONE_MAPPING, "implicit count = %d\n", + bvbuffmapinfo->automap); + + /* Schedule for unmapping. */ + if (batch != NULL) { + if (list_empty(&gccontext.vac_unmap)) { + gcschedunmap = gcalloc(struct gcschedunmap, + sizeof(struct gcschedunmap)); + if (gcschedunmap == NULL) { + BVSETERROR(BVERR_OOM, + "failed to schedule unmapping"); + goto fail; + } + list_add(&gcschedunmap->link, &batch->unmap); + } else { + struct list_head *head; + head = gccontext.vac_unmap.next; + gcschedunmap = list_entry(head, + struct gcschedunmap, + link); + list_move(&gcschedunmap->link, &batch->unmap); + } + + gcschedunmap->handle = (unsigned long) bvbuffdesc; + + GCDBG(GCZONE_MAPPING, "scheduled for unmapping.\n"); + GCDUMPSCHEDULE(); + } + + /* Set the map pointer. */ + *map = bvbuffmap; + + /* Unlock access to the mapping list. */ + GCUNLOCK(&gccontext.maplock); + + GCEXITARG(GCZONE_MAPPING, "handle = 0x%08X\n", + bvbuffmapinfo->handle); + return BVERR_NONE; + +fail: + if (bvbuffmap != NULL) { + bvbuffmap->nextmap = gccontext.vac_buffmap; + gccontext.vac_buffmap = bvbuffmap; + } + + /* Unlock access to the mapping list. */ + GCUNLOCK(&gccontext.maplock); + + GCEXITARG(GCZONE_MAPPING, "bverror = %d\n", bverror); + return bverror; +} + +static void unmap_implicit(struct gcbatch *batch) +{ + struct list_head *head, *temphead; + struct gcschedunmap *gcschedunmap; + struct bvbuffdesc *bvbuffdesc; + struct bvbuffmap *prev, *bvbuffmap; + struct bvbuffmapinfo *bvbuffmapinfo; + + GCENTER(GCZONE_MAPPING); + + /* Lock access to the mapping list. */ + GCLOCK(&gccontext.maplock); + + /* Dump the schedule. */ + GCDUMPSCHEDULE(); + + /* Scan scheduled unmappings and remove the ones that are still + * in use. */ + list_for_each_safe(head, temphead, &batch->unmap) { + gcschedunmap = list_entry(head, struct gcschedunmap, link); + + /* Cast the handle. */ + bvbuffdesc = (struct bvbuffdesc *) gcschedunmap->handle; + + /* Find our mapping. */ + prev = NULL; + bvbuffmap = bvbuffdesc->map; + while (bvbuffmap != NULL) { + if (bvbuffmap->bv_unmap == bv_unmap) + break; + prev = bvbuffmap; + bvbuffmap = bvbuffmap->nextmap; + } + + /* Not found? */ + if (bvbuffmap == NULL) { + GCERR("mapping not found for bvbuffdesc 0x%08X.\n", + (unsigned int) bvbuffdesc); + + /* Remove scheduled unmapping. */ + list_move(head, &gccontext.vac_unmap); + continue; + } + + /* Get the info structure. */ + bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle; + + GCDBG(GCZONE_MAPPING, "head = 0x%08X\n", + (unsigned int) gcschedunmap); + GCDBG(GCZONE_MAPPING, " bvbuffmap = 0x%08X\n", + (unsigned int) bvbuffmap); + GCDBG(GCZONE_MAPPING, " handle = 0x%08X\n", + bvbuffmapinfo->handle); + + /* Implicit unmapping. */ + bvbuffmapinfo->automap -= 1; + if (bvbuffmapinfo->automap < 0) { + GCERR("implicit count negative.\n"); + bvbuffmapinfo->automap = 0; + } + + GCDBG(GCZONE_MAPPING, " explicit count = %d\n", + bvbuffmapinfo->usermap); + GCDBG(GCZONE_MAPPING, " implicit count = %d\n", + bvbuffmapinfo->automap); + + /* Still referenced? */ + if (bvbuffmapinfo->usermap || bvbuffmapinfo->automap) { + GCDBG(GCZONE_MAPPING, " still referenced.\n"); + + /* Remove scheduled unmapping. */ + list_move(head, &gccontext.vac_unmap); + continue; + } + + GCDBG(GCZONE_MAPPING, " ready for unmapping.\n"); + + /* Set the handle. */ + gcschedunmap->handle = bvbuffmapinfo->handle; + + /* Remove from the buffer descriptor. */ + if (prev == NULL) + bvbuffdesc->map = bvbuffmap->nextmap; + else + prev->nextmap = bvbuffmap->nextmap; + + /* Add to the vacant list. */ + bvbuffmap->nextmap = gccontext.vac_buffmap; + gccontext.vac_buffmap = bvbuffmap; + } + + /* Dump the schedule. */ + GCDUMPSCHEDULE(); + + /* Unlock access to the mapping list. */ + GCUNLOCK(&gccontext.maplock); + + GCEXIT(GCZONE_MAPPING); +} + + +/******************************************************************************* + * Batch memory manager. + */ + +static enum bverror allocate_batch(struct gcbatch **batch); +static void free_batch(struct gcbatch *batch); +static enum bverror append_buffer(struct gcbatch *batch); + +static enum bverror do_end(struct bvbltparams *bltparams, + struct gcbatch *batch) +{ + return BVERR_NONE; +} + +static enum bverror allocate_batch(struct gcbatch **batch) +{ + enum bverror bverror; + struct gcbatch *temp; + + GCENTER(GCZONE_BATCH); + + /* Lock access to batch management. */ + GCLOCK(&gccontext.batchlock); + + if (gccontext.vac_batches == NULL) { + temp = gcalloc(struct gcbatch, sizeof(struct gcbatch)); + if (temp == NULL) { + BVSETERROR(BVERR_OOM, + "batch header allocation failed"); + goto exit; + } + + GCDBG(GCZONE_BATCH, "allocated new batch = 0x%08X\n", + (unsigned int) temp); + } else { + temp = (struct gcbatch *) gccontext.vac_batches; + gccontext.vac_batches = gccontext.vac_batches->next; + + GCDBG(GCZONE_BATCH, "reusing batch = 0x%08X\n", + (unsigned int) temp); + } + + memset(temp, 0, sizeof(struct gcbatch)); + temp->structsize = sizeof(struct gcbatch); + temp->batchend = do_end; + INIT_LIST_HEAD(&temp->unmap); + + bverror = append_buffer(temp); + if (bverror != BVERR_NONE) { + free_batch(temp); + goto exit; + } + + *batch = temp; + + GCDBG(GCZONE_BATCH, "batch allocated = 0x%08X\n", (unsigned int) temp); + +exit: + /* Unlock access to batch management. */ + GCUNLOCK(&gccontext.batchlock); + + GCEXITARG(GCZONE_BATCH, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +static void free_batch(struct gcbatch *batch) +{ + struct gcbuffer *buffer; + + GCENTERARG(GCZONE_BATCH, "batch = 0x%08X\n", (unsigned int) batch); + + /* Lock access. */ + GCLOCK(&gccontext.batchlock); + GCLOCK(&gccontext.bufferlock); + GCLOCK(&gccontext.fixuplock); + GCLOCK(&gccontext.maplock); + + list_splice_init(&batch->unmap, &gccontext.vac_unmap); + + buffer = batch->bufhead; + if (buffer != NULL) { + do { + if (buffer->fixuphead != NULL) { + buffer->fixuptail->next = gccontext.vac_fixups; + gccontext.vac_fixups = buffer->fixuphead; + } + buffer = buffer->next; + } while (buffer != NULL); + + batch->buftail->next = gccontext.vac_buffers; + gccontext.vac_buffers = batch->bufhead; + } + + ((struct gcvacbatch *) batch)->next = gccontext.vac_batches; + gccontext.vac_batches = (struct gcvacbatch *) batch; + + /* Unlock access. */ + GCUNLOCK(&gccontext.maplock); + GCUNLOCK(&gccontext.fixuplock); + GCUNLOCK(&gccontext.bufferlock); + GCUNLOCK(&gccontext.batchlock); + + GCEXIT(GCZONE_BATCH); +} + +static enum bverror append_buffer(struct gcbatch *batch) +{ + enum bverror bverror; + struct gcbuffer *temp; + + GCENTERARG(GCZONE_BUFFER, "batch = 0x%08X\n", (unsigned int) batch); + + /* Lock access to buffer management. */ + GCLOCK(&gccontext.bufferlock); + + if (gccontext.vac_buffers == NULL) { + temp = gcalloc(struct gcbuffer, GC_BUFFER_SIZE); + if (temp == NULL) { + BVSETERROR(BVERR_OOM, + "command buffer allocation failed"); + goto exit; + } + + GCDBG(GCZONE_BUFFER, "allocated new buffer = 0x%08X\n", + (unsigned int) temp); + } else { + temp = gccontext.vac_buffers; + gccontext.vac_buffers = temp->next; + + GCDBG(GCZONE_BUFFER, "reusing buffer = 0x%08X\n", + (unsigned int) temp); + } + + memset(temp, 0, sizeof(struct gcbuffer)); + temp->head = + temp->tail = (unsigned int *) (temp + 1); + temp->available = GC_BUFFER_SIZE - max(sizeof(struct gcbuffer), + GC_BUFFER_RESERVE); + + if (batch->bufhead == NULL) + batch->bufhead = temp; + else + batch->buftail->next = temp; + batch->buftail = temp; + + GCDBG(GCZONE_BUFFER, "new buffer appended = 0x%08X\n", + (unsigned int) temp); + + bverror = BVERR_NONE; + +exit: + /* Unlock access to buffer management. */ + GCUNLOCK(&gccontext.bufferlock); + + GCEXITARG(GCZONE_BUFFER, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +static enum bverror add_fixup(struct gcbatch *batch, unsigned int *fixup, + unsigned int surfoffset) +{ + enum bverror bverror; + struct gcbuffer *buffer; + struct gcfixup *temp; + + GCENTERARG(GCZONE_FIXUP, "batch = 0x%08X, fixup ptr = 0x%08X\n", + (unsigned int) batch, (unsigned int) fixup); + + /* Lock access to fixup management. */ + GCLOCK(&gccontext.fixuplock); + + buffer = batch->buftail; + temp = buffer->fixuptail; + + GCDBG(GCZONE_FIXUP, "buffer = 0x%08X, fixup struct = 0x%08X\n", + (unsigned int) buffer, (unsigned int) temp); + + if ((temp == NULL) || (temp->count == GC_FIXUP_MAX)) { + if (gccontext.vac_fixups == NULL) { + temp = gcalloc(struct gcfixup, sizeof(struct gcfixup)); + if (temp == NULL) { + BVSETERROR(BVERR_OOM, + "fixup allocation failed"); + goto exit; + } + + GCDBG(GCZONE_FIXUP, + "new fixup struct allocated = 0x%08X\n", + (unsigned int) temp); + } else { + temp = gccontext.vac_fixups; + gccontext.vac_fixups = temp->next; + + GCDBG(GCZONE_FIXUP, "fixup struct reused = 0x%08X\n", + (unsigned int) temp); + } + + temp->next = NULL; + temp->count = 0; + + if (buffer->fixuphead == NULL) + buffer->fixuphead = temp; + else + buffer->fixuptail->next = temp; + buffer->fixuptail = temp; + + GCDBG(GCZONE_FIXUP, "new fixup struct allocated = 0x%08X\n", + (unsigned int) temp); + + } else { + GCDBG(GCZONE_FIXUP, "fixups accumulated = %d\n", temp->count); + } + + temp->fixup[temp->count].dataoffset = fixup - buffer->head; + temp->fixup[temp->count].surfoffset = surfoffset; + temp->count += 1; + + GCDBG(GCZONE_FIXUP, "fixup offset = 0x%08X\n", fixup - buffer->head); + GCDBG(GCZONE_FIXUP, "surface offset = 0x%08X\n", surfoffset); + + bverror = BVERR_NONE; + +exit: + /* Unlock access to fixup management. */ + GCUNLOCK(&gccontext.fixuplock); + + GCEXITARG(GCZONE_FIXUP, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +static enum bverror claim_buffer(struct gcbatch *batch, + unsigned int size, + void **buffer) +{ + enum bverror bverror; + struct gcbuffer *curbuf; + + GCENTERARG(GCZONE_BUFFER, "batch = 0x%08X, size = %d\n", + (unsigned int) batch, size); + + /* Get the current command buffer. */ + curbuf = batch->buftail; + + GCDBG(GCZONE_BUFFER, "buffer = 0x%08X, available = %d\n", + (unsigned int) curbuf, curbuf->available); + + if (curbuf->available < size) { + bverror = append_buffer(batch); + if (bverror != BVERR_NONE) + goto exit; + + curbuf = batch->buftail; + } + + if (curbuf->available < size) { + GCDBG(GCZONE_BUFFER, "requested size is too large.\n"); + BVSETERROR(BVERR_OOM, + "command buffer allocation failed"); + goto exit; + } + + *buffer = curbuf->tail; + curbuf->tail = (unsigned int *) ((unsigned char *) curbuf->tail + size); + curbuf->available -= size; + batch->size += size; + bverror = BVERR_NONE; + +exit: + GCEXITARG(GCZONE_BUFFER, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + + +/******************************************************************************* + * Pixel format parser. + */ + +/* FIXME/TODO: change to use BLTsvile defines. */ + +#if defined(OCDFMTDEF_ALPHA_SHIFT) +# undef OCDFMTDEF_ALPHA_SHIFT +#endif + +#if defined(OCDFMTDEF_ALPHA_MASK) +# undef OCDFMTDEF_ALPHA_MASK +#endif + +#define OCDFMTDEF_ALPHA_SHIFT 18 +#define OCDFMTDEF_ALPHA_MASK (1 << OCDFMTDEF_ALPHA_SHIFT) + +#define OCDFMTDEF_PLACEMENT_SHIFT 9 +#define OCDFMTDEF_PLACEMENT_MASK (3 << OCDFMTDEF_PLACEMENT_SHIFT) + +#define OCDFMTDEF_BITS_SHIFT 3 +#define OCDFMTDEF_BITS_MASK (3 << OCDFMTDEF_BITS_SHIFT) + +#define OCDFMTDEF_BITS12 (0 << OCDFMTDEF_BITS_SHIFT) +#define OCDFMTDEF_BITS15 (1 << OCDFMTDEF_BITS_SHIFT) +#define OCDFMTDEF_BITS16 (2 << OCDFMTDEF_BITS_SHIFT) +#define OCDFMTDEF_BITS24 (3 << OCDFMTDEF_BITS_SHIFT) + +struct bvcomponent { + unsigned int shift; + unsigned int size; + unsigned int mask; +}; + +struct bvcsrgb { + struct bvcomponent r; + struct bvcomponent g; + struct bvcomponent b; + struct bvcomponent a; +}; + +struct bvformatxlate { + unsigned bitspp; + unsigned format; + unsigned swizzle; + struct bvcsrgb rgba; +}; + +#define BVFORMATRGBA(BPP, Format, Swizzle, R, G, B, A) \ +{ \ + BPP, \ + GCREG_DE_FORMAT_ ## Format, \ + GCREG_DE_SWIZZLE_ ## Swizzle, \ + { R, G, B, A } \ +} + +#define BVCOMP(Shift, Size) \ + { Shift, Size, ((1 << Size) - 1) << Shift } + +#define BVRED(Shift, Size) \ + BVCOMP(Shift, Size) + +#define BVGREEN(Shift, Size) \ + BVCOMP(Shift, Size) + +#define BVBLUE(Shift, Size) \ + BVCOMP(Shift, Size) + +#define BVALPHA(Shift, Size) \ + BVCOMP(Shift, Size) + +#define BVFORMATINVALID \ + { 0, 0, 0, { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 } } } + +static struct bvformatxlate g_format_nv12 = { + .bitspp = 8, + .format = GCREG_DE_FORMAT_NV12, +}; + +static struct bvformatxlate formatxlate[] = { + /* #0: OCDFMT_xRGB12 + BITS=12 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, X4R4G4B4, ARGB, + BVRED(8, 4), BVGREEN(4, 4), BVBLUE(0, 4), BVALPHA(12, 0)), + + /* #1: OCDFMT_RGBx12 + BITS=12 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, X4R4G4B4, RGBA, + BVRED(12, 4), BVGREEN(8, 4), BVBLUE(4, 4), BVALPHA(0, 0)), + + /* #2: OCDFMT_xBGR12 + BITS=12 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, X4R4G4B4, ABGR, + BVRED(0, 4), BVGREEN(4, 4), BVBLUE(8, 4), BVALPHA(12, 0)), + + /* #3: OCDFMT_BGRx12 + BITS=12 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, X4R4G4B4, BGRA, + BVRED(4, 4), BVGREEN(8, 4), BVBLUE(12, 4), BVALPHA(0, 0)), + + /* #4: OCDFMT_ARGB12 + BITS=12 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, A4R4G4B4, ARGB, + BVRED(8, 4), BVGREEN(4, 4), BVBLUE(0, 4), BVALPHA(12, 4)), + + /* #5: OCDFMT_RGBA12 + BITS=12 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, A4R4G4B4, RGBA, + BVRED(12, 4), BVGREEN(8, 4), BVBLUE(4, 4), BVALPHA(0, 4)), + + /* #6: OCDFMT_ABGR12 + BITS=12 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, A4R4G4B4, ABGR, + BVRED(0, 4), BVGREEN(4, 4), BVBLUE(8, 4), BVALPHA(12, 4)), + + /* #7: OCDFMT_BGRA12 + BITS=12 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, A4R4G4B4, BGRA, + BVRED(4, 4), BVGREEN(8, 4), BVBLUE(12, 4), BVALPHA(0, 4)), + + /***********************************************/ + + /* #8: OCDFMT_xRGB15 + BITS=15 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, X1R5G5B5, ARGB, + BVRED(10, 5), BVGREEN(5, 5), BVBLUE(0, 5), BVALPHA(15, 0)), + + /* #9: OCDFMT_RGBx15 + BITS=15 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, X1R5G5B5, RGBA, + BVRED(11, 5), BVGREEN(6, 5), BVBLUE(1, 5), BVALPHA(0, 0)), + + /* #10: OCDFMT_xBGR15 + BITS=15 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, X1R5G5B5, ABGR, + BVRED(0, 5), BVGREEN(5, 5), BVBLUE(10, 5), BVALPHA(15, 0)), + + /* #11: OCDFMT_BGRx15 + BITS=15 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, X1R5G5B5, BGRA, + BVRED(1, 5), BVGREEN(6, 5), BVBLUE(11, 5), BVALPHA(0, 0)), + + /* #12: OCDFMT_ARGB15 + BITS=15 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, A1R5G5B5, ARGB, + BVRED(10, 5), BVGREEN(5, 5), BVBLUE(0, 5), BVALPHA(15, 1)), + + /* #13: OCDFMT_RGBA15 + BITS=15 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, A1R5G5B5, RGBA, + BVRED(11, 5), BVGREEN(6, 5), BVBLUE(1, 5), BVALPHA(0, 1)), + + /* #14: OCDFMT_ABGR15 + BITS=15 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, A1R5G5B5, ABGR, + BVRED(0, 5), BVGREEN(5, 5), BVBLUE(10, 5), BVALPHA(15, 1)), + + /* #15: OCDFMT_BGRA15 + BITS=15 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, A1R5G5B5, BGRA, + BVRED(1, 5), BVGREEN(6, 5), BVBLUE(11, 5), BVALPHA(0, 1)), + + /***********************************************/ + + /* #16: OCDFMT_RGB16 + BITS=16 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, R5G6B5, ARGB, + BVRED(11, 5), BVGREEN(5, 6), BVBLUE(0, 5), BVALPHA(0, 0)), + + /* #17: OCDFMT_RGB16 + BITS=16 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, R5G6B5, ARGB, + BVRED(11, 5), BVGREEN(5, 6), BVBLUE(0, 5), BVALPHA(0, 0)), + + /* #18: OCDFMT_BGR16 + BITS=16 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(16, R5G6B5, ABGR, + BVRED(0, 5), BVGREEN(5, 6), BVBLUE(11, 5), BVALPHA(0, 0)), + + /* #19: OCDFMT_BGR16 + BITS=16 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(16, R5G6B5, ABGR, + BVRED(0, 5), BVGREEN(5, 6), BVBLUE(11, 5), BVALPHA(0, 0)), + + /* #20 */ + BVFORMATINVALID, + + /* #21 */ + BVFORMATINVALID, + + /* #22 */ + BVFORMATINVALID, + + /* #23 */ + BVFORMATINVALID, + + /***********************************************/ + + /* #24: OCDFMT_xRGB24 + BITS=24 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(32, X8R8G8B8, BGRA, + BVRED(8, 8), BVGREEN(16, 8), BVBLUE(24, 8), BVALPHA(0, 0)), + + /* #25: OCDFMT_RGBx24 + BITS=24 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(32, X8R8G8B8, ABGR, + BVRED(0, 8), BVGREEN(8, 8), BVBLUE(16, 8), BVALPHA(24, 0)), + + /* #26: OCDFMT_xBGR24 + BITS=24 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(32, X8R8G8B8, RGBA, + BVRED(24, 8), BVGREEN(16, 8), BVBLUE(8, 8), BVALPHA(0, 0)), + + /* #27: OCDFMT_BGRx24 + BITS=24 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(32, X8R8G8B8, ARGB, + BVRED(16, 8), BVGREEN(8, 8), BVBLUE(0, 8), BVALPHA(24, 0)), + + /* #28: OCDFMT_ARGB24 + BITS=24 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(32, A8R8G8B8, BGRA, + BVRED(8, 8), BVGREEN(16, 8), BVBLUE(24, 8), BVALPHA(0, 8)), + + /* #29: OCDFMT_RGBA24 + BITS=24 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(32, A8R8G8B8, ABGR, + BVRED(0, 8), BVGREEN(8, 8), BVBLUE(16, 8), BVALPHA(24, 8)), + + /* #30: OCDFMT_ABGR24 + BITS=24 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=0 */ + BVFORMATRGBA(32, A8R8G8B8, RGBA, + BVRED(24, 8), BVGREEN(16, 8), BVBLUE(8, 8), BVALPHA(0, 8)), + + /* #31: OCDFMT_BGRA24 + BITS=24 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=1 */ + BVFORMATRGBA(32, A8R8G8B8, ARGB, + BVRED(16, 8), BVGREEN(8, 8), BVBLUE(0, 8), BVALPHA(24, 8)), +}; + +static int parse_format(enum ocdformat ocdformat, struct bvformatxlate **format) +{ + static unsigned int containers[] = { + 8, /* OCDFMTDEF_CONTAINER_8BIT */ + 16, /* OCDFMTDEF_CONTAINER_16BIT */ + 24, /* OCDFMTDEF_CONTAINER_24BIT */ + 32, /* OCDFMTDEF_CONTAINER_32BIT */ + ~0U, /* reserved */ + 48, /* OCDFMTDEF_CONTAINER_48BIT */ + ~0U, /* reserved */ + 64 /* OCDFMTDEF_CONTAINER_64BIT */ + }; + + unsigned int cs; + unsigned int bits; + unsigned int swizzle; + unsigned int alpha; + unsigned int index; + unsigned int cont; + + GCDBG(GCZONE_FORMAT, "ocdformat = 0x%08X\n", ocdformat); + + switch (ocdformat) { + case OCDFMT_NV12: + GCDBG(GCZONE_FORMAT, "OCDFMT_NV12\n"); + *format = &g_format_nv12; + return 1; + + default: + break; + } + + cs = (ocdformat & OCDFMTDEF_CS_MASK) >> OCDFMTDEF_CS_SHIFT; + bits = (ocdformat & OCDFMTDEF_COMPONENTSIZEMINUS1_MASK) + >> OCDFMTDEF_COMPONENTSIZEMINUS1_SHIFT; + cont = (ocdformat & OCDFMTDEF_CONTAINER_MASK) + >> OCDFMTDEF_CONTAINER_SHIFT; + + switch (cs) { + case (OCDFMTDEF_CS_RGB >> OCDFMTDEF_CS_SHIFT): + GCDBG(GCZONE_FORMAT, "OCDFMTDEF_CS_RGB\n"); + GCDBG(GCZONE_FORMAT, "bits = %d\n", bits); + GCDBG(GCZONE_FORMAT, "cont = %d\n", cont); + + if ((ocdformat & OCDFMTDEF_LAYOUT_MASK) != OCDFMTDEF_PACKED) + return 0; + + swizzle = (ocdformat & OCDFMTDEF_PLACEMENT_MASK) + >> OCDFMTDEF_PLACEMENT_SHIFT; + alpha = (ocdformat & OCDFMTDEF_ALPHA_MASK) + >> OCDFMTDEF_ALPHA_SHIFT; + + GCDBG(GCZONE_FORMAT, "swizzle = %d\n", swizzle); + GCDBG(GCZONE_FORMAT, "alpha = %d\n", alpha); + + index = swizzle | (alpha << 2); + + switch (bits) { + case 12 - 1: + index |= OCDFMTDEF_BITS12; + break; + + case 15 - 1: + index |= OCDFMTDEF_BITS15; + break; + + case 16 - 1: + index |= OCDFMTDEF_BITS16; + break; + + case 24 - 1: + index |= OCDFMTDEF_BITS24; + break; + + default: + return 0; + } + + GCDBG(GCZONE_FORMAT, "index = %d\n", index); + break; + + default: + return 0; + } + + if (formatxlate[index].bitspp != containers[cont]) + return 0; + + *format = &formatxlate[index]; + + GCDBG(GCZONE_FORMAT, "format record = 0x%08X\n", + (unsigned int) &formatxlate[index]); + GCDBG(GCZONE_FORMAT, " bpp = %d\n", formatxlate[index].bitspp); + GCDBG(GCZONE_FORMAT, " format = %d\n", formatxlate[index].format); + GCDBG(GCZONE_FORMAT, " swizzle = %d\n", formatxlate[index].swizzle); + + return 1; +} + +static inline unsigned int extract_component(unsigned int pixel, + struct bvcomponent *desc) +{ + unsigned int component; + unsigned int component8; + + component = (pixel & desc->mask) >> desc->shift; + GCDBG(GCZONE_COLOR, "mask=0x%08X, shift=%d, component=0x%08X\n", + desc->mask, desc->shift, component); + + switch (desc->size) { + case 0: + component8 = 0xFF; + GCDBG(GCZONE_COLOR, "component8=0x%08X\n", component8); + break; + + case 1: + component8 = component ? 0xFF : 0x00; + GCDBG(GCZONE_COLOR, "component8=0x%08X\n", component8); + break; + + case 4: + component8 = component | (component << 4); + GCDBG(GCZONE_COLOR, "component8=0x%08X\n", component8); + break; + + case 5: + component8 = (component << 3) | (component >> 2); + GCDBG(GCZONE_COLOR, "component8=0x%08X\n", component8); + break; + + case 6: + component8 = (component << 2) | (component >> 4); + GCDBG(GCZONE_COLOR, "component8=0x%08X\n", component8); + break; + + default: + component8 = component; + GCDBG(GCZONE_COLOR, "component8=0x%08X\n", component8); + } + + return component8; +} + +static unsigned int getinternalcolor(void *ptr, struct bvformatxlate *format) +{ + unsigned int srcpixel, dstpixel; + unsigned int r, g, b, a; + + switch (format->bitspp) { + case 16: + srcpixel = *(unsigned short *) ptr; + GCDBG(GCZONE_COLOR, "srcpixel=0x%08X\n", srcpixel); + break; + + case 32: + srcpixel = *(unsigned int *) ptr; + GCDBG(GCZONE_COLOR, "srcpixel=0x%08X\n", srcpixel); + break; + + default: + srcpixel = 0; + GCDBG(GCZONE_COLOR, "srcpixel=0x%08X\n", srcpixel); + } + + r = extract_component(srcpixel, &format->rgba.r); + g = extract_component(srcpixel, &format->rgba.g); + b = extract_component(srcpixel, &format->rgba.b); + a = extract_component(srcpixel, &format->rgba.a); + + GCDBG(GCZONE_COLOR, "(r,g,b,a)=0x%02X,0x%02X,0x%02X,0x%02X\n", + r, g, b, a); + + dstpixel = (a << 24) | (r << 16) | (g << 8) | b; + + GCDBG(GCZONE_COLOR, "dstpixel=0x%08X\n", dstpixel); + + return dstpixel; +} + + +/******************************************************************************* + * Alpha blending parser. + */ + +struct gcblendconfig { + unsigned char factor_mode; + unsigned char color_reverse; + + unsigned char src1used; + unsigned char src2used; +}; + +struct bvblendxlate { + unsigned char match1; + unsigned char match2; + + struct gcblendconfig k1; + struct gcblendconfig k2; +}; + +struct gcalpha { + unsigned int src_global_color; + unsigned int dst_global_color; + + unsigned char src_global_alpha_mode; + unsigned char dst_global_alpha_mode; + + struct gcblendconfig *k1; + struct gcblendconfig *k2; + + unsigned int src1used; + unsigned int src2used; +}; + +#define BVBLENDMATCH(Mode, Inverse, Normal) \ +( \ + BVBLENDDEF_ ## Mode | \ + BVBLENDDEF_ ## Inverse | \ + BVBLENDDEF_ ## Normal \ +) + +#define BVSRC1USE(Use) \ + Use + +#define BVSRC2USE(Use) \ + Use + +#define BVBLENDUNDEFINED() \ + { ~0, ~0, { 0, 0, 0, 0 }, { 0, 0, 0, 0 } } + +static struct bvblendxlate blendxlate[64] = { + /**********************************************************************/ + /* #0: color factor: 00 00 00 A:(1-C1,C1)=zero + alpha factor: zero ==> 00 00 00 */ + { + 0x00, + 0x00, + + { + GCREG_BLENDING_MODE_ZERO, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(0), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_ZERO, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(0), BVSRC2USE(0) + } + }, + + /* #1: color factor: 00 00 01 A:(1-C1,A1)=A1 + alpha factor: A1 ==> 00 00 01 or 00 10 01 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1), + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #2: color factor: 00 00 10 A:(1-C1,C2)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #3: color factor: 00 00 11 A:(1-C1,A2)=A2 + alpha factor: A2 ==> 00 00 11 or 00 10 11 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2), + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + }, + + /* #4: color factor: 00 01 00 A:(1-A1,C1)=1-A1 + alpha factor: 1-A1 ==> 00 01 00 or 00 01 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2), + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #5: color factor: 00 01 01 A:(1-A1,A1)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #6: color factor: 00 01 10 A:(1-A1,C2)=1-A1 + alpha factor: 1-A1 ==> 00 01 00 or 00 01 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2), + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #7: color factor: 00 01 11 A:(1-A1,A2)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #8: color factor: 00 10 00 A:(1-C2,C1)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #9: color factor: 00 10 01 A:(1-C2,A1)=A1 + alpha factor: A1 ==> 00 00 01 or 00 10 01 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1), + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #10: color factor: 00 10 10 A:(1-C2,C2)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #11: color factor: 00 10 11 A:(1-C2,A2)=A2 + alpha factor: A2 ==> 00 00 11 or 00 10 11 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2), + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_NORMAL, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + }, + + /* #12: color factor: 00 11 00 A:(1-A2,C1)=1-A2 + alpha factor: 1-A2 ==> 00 11 00 or 00 11 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2), + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + }, + + /* #13: color factor: 00 11 01 A:(1-A2,A1)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #14: color factor: 00 11 10 A:(1-A2,C2)=1-A2 + alpha factor: 1-A2 ==> 00 11 00 or 00 11 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2), + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + }, + + /* #15: color factor: 00 11 11 A:(1-A2,A2)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /**********************************************************************/ + /* #16: color factor: 01 00 00 MIN:(1-C1,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #17: color factor: 01 00 01 MIN:(1-C1,A1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #18: color factor: 01 00 10 MIN:(1-C1,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #19: color factor: 01 00 11 MIN:(1-C1,A2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #20: color factor: 01 01 00 MIN:(1-A1,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #21: color factor: 01 01 01 MIN:(1-A1,A1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #22: color factor: 01 01 10 MIN:(1-A1,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #23: color factor: 01 01 11 MIN:(1-A1,A2) + alpha factor: one ==> 11 11 11 */ + { + 0x3F, + 0x3F, + + { + GCREG_BLENDING_MODE_SATURATED_DEST_ALPHA, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_SATURATED_ALPHA, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #24: color factor: 01 10 00 MIN:(1-C2,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #25: color factor: 01 10 01 MIN:(1-C2,A1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #26: color factor: 01 10 10 MIN:(1-C2,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #27: color factor: 01 10 11 MIN:(1-C2,A2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #28: color factor: 01 11 00 MIN:(1-A2,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #29: color factor: 01 11 01 MIN:(1-A2,A1) + alpha factor: one ==> 11 11 11 */ + { + 0x3F, + 0x3F, + + { + GCREG_BLENDING_MODE_SATURATED_ALPHA, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_SATURATED_DEST_ALPHA, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #30: color factor: 01 11 10 MIN:(1-A2,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #31: color factor: 01 11 11 MIN:(1-A2,A2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /**********************************************************************/ + /* #32: color factor: 10 00 00 MAX:(1-C1,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #33: color factor: 10 00 01 MAX:(1-C1,A1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #34: color factor: 10 00 10 MAX:(1-C1,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #35: color factor: 10 00 11 MAX:(1-C1,A2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #36: color factor: 10 01 00 MAX:(1-A1,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #37: color factor: 10 01 01 MAX:(1-A1,A1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #38: color factor: 10 01 10 MAX:(1-A1,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #39: color factor: 10 01 11 MAX:(1-A1,A2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #40: color factor: 10 10 00 MAX:(1-C2,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #41: color factor: 10 10 01 MAX:(1-C2,A1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #42: color factor: 10 10 10 MAX:(1-C2,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #43: color factor: 10 10 11 MAX:(1-C2,A2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #44: color factor: 10 11 00 MAX:(1-A2,C1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #45: color factor: 10 11 01 MAX:(1-A2,A1) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #46: color factor: 10 11 10 MAX:(1-A2,C2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #47: color factor: 10 11 11 MAX:(1-A2,A2) ==> not supported + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /**********************************************************************/ + /* #48: color factor: 11 00 00 C:(1-C1,C1)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #49: color factor: 11 00 01 C:(1-C1,A1)=1-C1 + alpha factor: 1-A1 ==> 00 01 00 or 00 01 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2), + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #50: color factor: 11 00 10 C:(1-C1,C2)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #51: color factor: 11 00 11 C:(1-C1,A2)=1-C1 + alpha factor: 1-A1 ==> 00 01 00 or 00 01 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2), + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #52: color factor: 11 01 00 C:(1-A1,C1)=C1 + alpha factor: A1 ==> 00 00 01 or 00 10 01 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1), + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #53: color factor: 11 01 01 C:(1-A1,A1)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #54: color factor: 11 01 10 C:(1-A1,C2)=C2 + alpha factor: A2 ==> 00 00 11 or 00 10 11 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2), + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + }, + + /* #55: color factor: 11 01 11 C:(1-A1,A2)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #56: color factor: 11 10 00 C:(1-C2,C1)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #57: color factor: 11 10 01 C:(1-C2,A1)=1-C2 + alpha factor: 1-A2 ==> 00 11 00 or 00 11 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2), + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + }, + + /* #58: color factor: 11 10 10 C:(1-C2,C2)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #59: color factor: 11 10 11 C:(1-C2,A2)=1-C2 + alpha factor: 1-A2 ==> 00 11 00 or 00 11 10 */ + { + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1), + BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2), + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_COLOR_INVERSED, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(0) + } + }, + + /* #60: color factor: 11 11 00 C:(1-A2,C1)=C1 + alpha factor: A1 ==> 00 00 01 or 00 10 01 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1), + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1) + } + }, + + /* #61: color factor: 11 11 01 C:(1-A2,A1)=undefined + alpha factor: N/A */ + BVBLENDUNDEFINED(), + + /* #62: color factor: 11 11 10 C:(1-A2,C2)=C2 + alpha factor: A2 ==> 00 00 11 or 00 10 11 */ + { + BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2), + BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2), + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(1), + }, + + { + GCREG_BLENDING_MODE_COLOR, + GCREG_FACTOR_INVERSE_ENABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + }, + + /* #63: color factor: 11 11 11 C:(1-A2,A2)=one + alpha factor: one ==> 11 11 11 */ + { + 0x3F, + 0x3F, + + { + GCREG_BLENDING_MODE_ONE, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(1), BVSRC2USE(0), + }, + + { + GCREG_BLENDING_MODE_ONE, + GCREG_FACTOR_INVERSE_DISABLE, + BVSRC1USE(0), BVSRC2USE(1) + } + } +}; + +static enum bverror parse_blend(struct bvbltparams *bltparams, + enum bvblend blend, struct gcalpha *gca) +{ + enum bverror bverror; + unsigned int global; + unsigned int k1, k2, k3, k4; + struct bvblendxlate *k1_xlate; + struct bvblendxlate *k2_xlate; + unsigned int alpha; + + GCDBG(GCZONE_BLEND, "blend = 0x%08X (%s)\n", + blend, gc_bvblend_name(blend)); + + if ((blend & BVBLENDDEF_REMOTE) != 0) { + BVSETBLTERROR(BVERR_BLEND, "remote alpha not supported"); + goto exit; + } + + global = (blend & BVBLENDDEF_GLOBAL_MASK) >> BVBLENDDEF_GLOBAL_SHIFT; + + switch (global) { + case (BVBLENDDEF_GLOBAL_NONE >> BVBLENDDEF_GLOBAL_SHIFT): + GCDBG(GCZONE_BLEND, "BVBLENDDEF_GLOBAL_NONE\n"); + + gca->src_global_color = + gca->dst_global_color = 0; + + gca->src_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_NORMAL; + gca->dst_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_NORMAL; + break; + + case (BVBLENDDEF_GLOBAL_UCHAR >> BVBLENDDEF_GLOBAL_SHIFT): + GCDBG(GCZONE_BLEND, "BVBLENDDEF_GLOBAL_UCHAR\n"); + + gca->src_global_color = + gca->dst_global_color = + ((unsigned int) bltparams->globalalpha.size8) << 24; + + gca->src_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL; + gca->dst_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL; + break; + + case (BVBLENDDEF_GLOBAL_FLOAT >> BVBLENDDEF_GLOBAL_SHIFT): + GCDBG(GCZONE_BLEND, "BVBLENDDEF_GLOBAL_FLOAT\n"); + + alpha = gcfp2norm8(bltparams->globalalpha.fp); + + gca->src_global_color = + gca->dst_global_color = alpha << 24; + + gca->src_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL; + gca->dst_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL; + break; + + default: + BVSETBLTERROR(BVERR_BLEND, "invalid global alpha mode"); + goto exit; + } + + /* + Co = k1 x C1 + k2 x C2 + Ao = k3 x A1 + k4 x A2 + */ + + k1 = (blend >> 18) & 0x3F; + k2 = (blend >> 12) & 0x3F; + k3 = (blend >> 6) & 0x3F; + k4 = blend & 0x3F; + + GCDBG(GCZONE_BLEND, "k1 = %d\n", k1); + GCDBG(GCZONE_BLEND, "k2 = %d\n", k2); + GCDBG(GCZONE_BLEND, "k3 = %d\n", k3); + GCDBG(GCZONE_BLEND, "k4 = %d\n", k4); + + k1_xlate = &blendxlate[k1]; + k2_xlate = &blendxlate[k2]; + + if (((k3 != k1_xlate->match1) && (k3 != k1_xlate->match2)) || + ((k4 != k2_xlate->match1) && (k4 != k2_xlate->match2))) { + BVSETBLTERROR(BVERR_BLEND, + "not supported coefficient combination"); + goto exit; + } + + gca->k1 = &k1_xlate->k1; + gca->k2 = &k2_xlate->k2; + + gca->src1used = gca->k1->src1used | gca->k2->src1used; + gca->src2used = gca->k1->src2used | gca->k2->src2used; + + bverror = BVERR_NONE; + +exit: + return bverror; +} + + +/******************************************************************************* + * Surface compare and validation. + */ + +static inline bool equal_rects(struct bvrect *rect1, struct bvrect *rect2) +{ + if (rect1->left != rect2->left) + return false; + + if (rect1->top != rect2->top) + return false; + + if (rect1->width != rect2->width) + return false; + + if (rect1->height != rect2->height) + return false; + + return true; +} + +/* The function verifies whether the two buffer descriptors and rectangles + define the same physical area. */ +static bool same_phys_area(struct bvbuffdesc *surf1, struct bvrect *rect1, + struct bvbuffdesc *surf2, struct bvrect *rect2) +{ + struct bvphysdesc *physdesc1; + struct bvphysdesc *physdesc2; + + /* If pointers are the same, things are much easier. */ + if (surf1 == surf2) + /* Compare the rectangles. For simplicity we don't consider + cases with partially overlapping rectangles at this time. */ + return equal_rects(rect1, rect2); + + /* Assume diffrent areas if the types are different. */ + if (surf1->auxtype != surf2->auxtype) + return false; + + if (surf1->auxtype == BVAT_PHYSDESC) { + physdesc1 = (struct bvphysdesc *) surf1->auxptr; + physdesc2 = (struct bvphysdesc *) surf2->auxptr; + + /* Same physical descriptor? */ + if (physdesc1 == physdesc2) + return equal_rects(rect1, rect2); + + /* Same page array? */ + if (physdesc1->pagearray == physdesc2->pagearray) + return equal_rects(rect1, rect2); + + /* Pageoffsets must match since different buffers + * can share the same first page (eg nv12). + */ + if (physdesc1->pageoffset != physdesc2->pageoffset) + return false; + + /* Assume the same surface if first pages match. */ + if (physdesc1->pagearray[0] == physdesc2->pagearray[0]) + return equal_rects(rect1, rect2); + + } else { + if (surf1->virtaddr == surf2->virtaddr) + return equal_rects(rect1, rect2); + } + + return false; +} + +static bool valid_geom(struct bvbuffdesc *buffdesc, struct bvsurfgeom *geom, + struct bvformatxlate *format) +{ + unsigned int size; + + /* Compute the size of the surface. */ + size = (geom->width * geom->height * format->bitspp) / 8; + + /* Make sure the size is not greater then the surface. */ + if (size > buffdesc->length) { + GCERR("invalid geometry detected:\n"); + GCERR(" specified dimensions: %dx%d, %d bitspp\n", + geom->width, geom->height, format->bitspp); + GCERR(" surface size based on the dimensions: %d\n", + size); + GCERR(" specified surface size: %lu\n", + buffdesc->length); + return false; + } + + return true; +} + +static int verify_surface(unsigned int tile, + union bvinbuff *surf, + struct bvsurfgeom *geom) +{ + int ret; + + GCENTER(GCZONE_SURF); + + if (tile) { + if (surf->tileparams == NULL) { + ret = GCBVERR_TILE; + goto exit; + } + + if (surf->tileparams->structsize < + STRUCTSIZE(surf->tileparams, srcheight)) { + ret = GCBVERR_TILE_VERS; + goto exit; + } + + /* FIXME/TODO */ + ret = GCBVERR_TILE; + goto exit; + } else { + if (surf->desc == NULL) { + ret = GCBVERR_DESC; + goto exit; + } + + if (surf->desc->structsize < STRUCTSIZE(surf->desc, map)) { + ret = GCBVERR_DESC_VERS; + goto exit; + } + } + + if (geom == NULL) { + ret = GCBVERR_GEOM; + goto exit; + } + + if (geom->structsize < STRUCTSIZE(geom, palette)) { + ret = GCBVERR_GEOM_VERS; + goto exit; + } + + /* Validation successful. */ + ret = -1; + +exit: + GCEXITARG(GCZONE_SURF, "ret = %d\n", ret); + return ret; +} + +#if GCDEBUG_ENABLE +# define VERIFYBATCH(changeflags, prevrect, currrect) \ + verify_batch(changeflags, prevrect, currrect) + +static void verify_batch(unsigned int changeflags, + struct bvrect *prevrect, + struct bvrect *currrect) +{ + if ((changeflags & 1) == 0) { + /* Origin did not change. */ + if ((prevrect->left != currrect->left) || + (prevrect->top != currrect->top)) { + GCERR("origin changed\n"); + GCERR(" previous = %d,%d\n", + prevrect->left, prevrect->top); + GCERR(" current = %d,%d\n", + currrect->left, currrect->top); + } + } + + if ((changeflags & 2) == 0) { + /* Size did not change. */ + if ((prevrect->width != currrect->width) || + (prevrect->height != currrect->height)) { + GCERR("size changed\n"); + GCERR(" previous = %dx%d\n", + prevrect->width, prevrect->height); + GCERR(" current = %dx%d\n", + currrect->width, currrect->height); + } + } + + prevrect->left = currrect->left; + prevrect->top = currrect->top; + prevrect->width = currrect->width; + prevrect->height = currrect->height; +} +#else +# define VERIFYBATCH(...) +#endif + + +/******************************************************************************* + * Primitive renderers. + */ + +static enum bverror set_dst(struct bvbltparams *bltparams, + struct gcbatch *batch, + struct bvbuffmap *dstmap) +{ + enum bverror bverror = BVERR_NONE; + struct bvsurfgeom *dstgeom = bltparams->dstgeom; + struct gcmodst *gcmodst; + unsigned int dstoffset; + + GCENTER(GCZONE_DEST); + + /* Did destination surface change? */ + if ((batch->batchflags & BVBATCH_DST) == 0) + goto exit; + + GCDBG(GCZONE_DEST, "destination surface changed.\n"); + + /* Parse the destination format. */ + GCDBG(GCZONE_FORMAT, "parsing the destination format.\n"); + if (!parse_format(dstgeom->format, &batch->dstformat)) { + BVSETBLTERRORARG(BVERR_DSTGEOM_FORMAT, + "invalid destination format (%d)", + dstgeom->format); + goto exit; + } + + /* Validate geometry. */ + if (!valid_geom(bltparams->dstdesc, bltparams->dstgeom, + batch->dstformat)) { + BVSETBLTERROR(BVERR_DSTGEOM, + "destination geom exceeds surface size"); + goto exit; + } + + /* Compute the destination offset in pixels needed to compensate + for the surface base address misalignment if any. */ + dstoffset = (((unsigned int) bltparams->dstdesc->virtaddr + & (GC_BASE_ALIGN - 1)) * 8) + / batch->dstformat->bitspp; + + /* Have to reset clipping with the new offset. */ + if (dstoffset != batch->dstoffset) { + batch->dstoffset = dstoffset; + batch->batchflags |= BVBATCH_CLIPRECT_ORIGIN; + } + + /* Allocate command buffer. */ + bverror = claim_buffer(batch, sizeof(struct gcmodst), + (void **) &gcmodst); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, + "failed to allocate command buffer"); + goto exit; + } + + /* Add the address fixup. */ + add_fixup(batch, &gcmodst->address, 0); + + /* Set surface parameters. */ + gcmodst->address_ldst = gcmodst_address_ldst; + gcmodst->address = GET_MAP_HANDLE(dstmap); + gcmodst->stride = dstgeom->virtstride; + + /* Set surface width and height. */ + gcmodst->rotation.raw = 0; + gcmodst->rotation.reg.surf_width = dstgeom->width + dstoffset; + gcmodst->rotationheight_ldst = gcmodst_rotationheight_ldst; + gcmodst->rotationheight.raw = 0; + gcmodst->rotationheight.reg.height = dstgeom->height; + + GCDBG(GCZONE_DEST, "destination surface:\n"); + GCDBG(GCZONE_DEST, " dstvirtaddr = 0x%08X\n", + (unsigned int) bltparams->dstdesc->virtaddr); + GCDBG(GCZONE_DEST, " dstaddr = 0x%08X\n", + (unsigned int) GET_MAP_HANDLE(dstmap)); + GCDBG(GCZONE_DEST, " dstoffset = %d\n", dstoffset); + GCDBG(GCZONE_DEST, " dstsurf = %dx%d, stride = %ld\n", + dstgeom->width, dstgeom->height, dstgeom->virtstride); + +exit: + GCEXITARG(GCZONE_DEST, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +static enum bverror set_clip(struct bvbltparams *bltparams, + struct gcbatch *batch) +{ + enum bverror bverror = BVERR_NONE; + struct bvrect *dstrect = &bltparams->dstrect; + struct bvrect *cliprect = &bltparams->cliprect; + int destleft, desttop, destright, destbottom; + int clipleft, cliptop, clipright, clipbottom; + int clippedleft, clippedtop, clippedright, clippedbottom; + int clipleftadj, cliprightadj; + struct gcmoclip *gcmoclip; + + GCENTER(GCZONE_CLIP); + + /* Did clipping/destination rects change? */ + if ((batch->batchflags & (BVBATCH_CLIPRECT_ORIGIN | + BVBATCH_CLIPRECT_SIZE | + BVBATCH_DSTRECT_ORIGIN | + BVBATCH_DSTRECT_SIZE)) == 0) + goto exit; + + GCDBG(GCZONE_CLIP, "destination clipping changed.\n"); + + /* Determine destination rectangle. */ + destleft = dstrect->left; + desttop = dstrect->top; + destright = dstrect->left + dstrect->width; + destbottom = dstrect->top + dstrect->height; + + /* Determine clipping. */ + if ((bltparams->flags & BVFLAG_CLIP) == BVFLAG_CLIP) { + clipleft = cliprect->left; + cliptop = cliprect->top; + clipright = cliprect->left + cliprect->width; + clipbottom = cliprect->top + cliprect->height; + + if ((clipleft < GC_CLIP_RESET_LEFT) || + (cliptop < GC_CLIP_RESET_TOP) || + (clipright > GC_CLIP_RESET_RIGHT) || + (clipbottom > GC_CLIP_RESET_BOTTOM) || + (clipright < clipleft) || (clipbottom < cliptop)) { + BVSETBLTERROR(BVERR_CLIP_RECT, + "invalid clipping rectangle"); + goto exit; + } + } else { + clipleft = GC_CLIP_RESET_LEFT; + cliptop = GC_CLIP_RESET_TOP; + clipright = GC_CLIP_RESET_RIGHT; + clipbottom = GC_CLIP_RESET_BOTTOM; + } + + /* Compute clipping deltas and the adjusted destination rect. */ + if (clipleft <= destleft) { + batch->deltaleft = 0; + clippedleft = destleft; + } else { + batch->deltaleft = clipleft - destleft; + clippedleft = destleft + batch->deltaleft; + } + + if (cliptop <= desttop) { + batch->deltatop = 0; + clippedtop = desttop; + } else { + batch->deltatop = cliptop - desttop; + clippedtop = desttop + batch->deltatop; + } + + if (clipright >= destright) { + batch->deltaright = 0; + clippedright = destright; + } else { + batch->deltaright = clipright - destright; + clippedright = destright + batch->deltaright; + } + + if (clipbottom >= destbottom) { + batch->deltabottom = 0; + clippedbottom = destbottom; + } else { + batch->deltabottom = clipbottom - destbottom; + clippedbottom = destbottom + batch->deltabottom; + } + + /* Validate the rectangle. */ + if ((clippedright > (int) bltparams->dstgeom->width) || + (clippedbottom > (int) bltparams->dstgeom->height)) { + BVSETBLTERROR(BVERR_DSTRECT, + "destination rect exceeds surface size"); + goto exit; + } + + /* Set the destination rectangle. */ + batch->dstleft = clippedleft; + batch->dsttop = clippedtop; + batch->dstright = clippedright; + batch->dstbottom = clippedbottom; + + /* Allocate command buffer. */ + bverror = claim_buffer(batch, sizeof(struct gcmoclip), + (void **) &gcmoclip); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, + "failed to allocate command buffer"); + goto exit; + } + + /* Compute adjusted clipping. */ + clipleftadj = min(clipleft + (int) batch->dstoffset, + (int) GC_CLIP_RESET_RIGHT); + cliprightadj = min(clipright + (int) batch->dstoffset, + (int) GC_CLIP_RESET_RIGHT); + + /* Set clipping. */ + gcmoclip->lt_ldst = gcmoclip_lt_ldst; + gcmoclip->lt.raw = 0; + gcmoclip->lt.reg.left = clipleftadj; + gcmoclip->lt.reg.top = cliptop; + gcmoclip->rb.raw = 0; + gcmoclip->rb.reg.right = cliprightadj; + gcmoclip->rb.reg.bottom = clipbottom; + + GCDBG(GCZONE_CLIP, "destination rectangle:\n"); + GCDBG(GCZONE_CLIP, " dstrect = (%d,%d)-(%d,%d), %dx%d\n", + destleft, desttop, destright, destbottom, + destright - destleft, destbottom - desttop); + + GCDBG(GCZONE_CLIP, " clipping rect = (%d,%d)-(%d,%d), %dx%d\n", + clipleft, cliptop, clipright, clipbottom, + clipright - clipleft, clipbottom - cliptop); + + GCDBG(GCZONE_CLIP, + " adjusted clipping rect = (%d,%d)-(%d,%d), %dx%d\n", + clipleftadj, cliptop, cliprightadj, clipbottom, + cliprightadj - clipleftadj, clipbottom - cliptop); + + GCDBG(GCZONE_CLIP, " clipping delta = (%d,%d)-(%d,%d)\n", + batch->deltaleft, batch->deltatop, + batch->deltaright, batch->deltabottom); + + GCDBG(GCZONE_CLIP, " clipped dstrect = (%d,%d)-(%d,%d), %dx%d\n", + clippedleft, clippedtop, clippedright, clippedbottom, + clippedright - clippedleft, clippedbottom - clippedtop); + +exit: + GCEXITARG(GCZONE_CLIP, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +static enum bverror do_fill(struct bvbltparams *bltparams, + struct gcbatch *batch, + struct srcinfo *srcinfo) +{ + enum bverror bverror; + struct gcmofill *gcmofill; + unsigned char *fillcolorptr; + struct bvformatxlate *srcformat; + struct bvsurfgeom *dstgeom = bltparams->dstgeom; + struct bvbuffmap *dstmap = NULL; + + GCENTER(GCZONE_DO_FILL); + + /* Finish previous batch if any. */ + bverror = batch->batchend(bltparams, batch); + if (bverror != BVERR_NONE) + goto exit; + + /* Map the destination. */ + bverror = do_map(bltparams->dstdesc, batch, &dstmap); + if (bverror != BVERR_NONE) { + bltparams->errdesc = gccontext.bverrorstr; + goto exit; + } + + /* Set the new destination. */ + bverror = set_dst(bltparams, batch, dstmap); + if (bverror != BVERR_NONE) + goto exit; + + /* Update clipping/destination rect if necessary. */ + bverror = set_clip(bltparams, batch); + if (bverror != BVERR_NONE) + goto exit; + + /* Parse the source format. */ + GCDBG(GCZONE_FORMAT, "parsing the source format.\n"); + + if (!parse_format(srcinfo->geom->format, &srcformat)) { + BVSETBLTERRORARG((srcinfo->index == 0) + ? BVERR_SRC1GEOM_FORMAT + : BVERR_SRC2GEOM_FORMAT, + "invalid source format (%d)", + srcinfo->geom->format); + goto exit; + } + + /* Validate soource geometry. */ + if (!valid_geom(srcinfo->buf.desc, srcinfo->geom, srcformat)) { + BVSETBLTERRORARG((srcinfo->index == 0) + ? BVERR_SRC1GEOM + : BVERR_SRC2GEOM, + "source%d geom exceeds surface size", + srcinfo->index + 1); + goto exit; + } + + bverror = claim_buffer(batch, sizeof(struct gcmofill), + (void **) &gcmofill); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, "failed to allocate command buffer"); + goto exit; + } + + /*********************************************************************** + ** Set source. + */ + + /* Set surface dummy width and height. */ + gcmofill->src.rotation_ldst = gcmofillsrc_rotation_ldst; + gcmofill->src.rotation.raw = 0; + gcmofill->src.rotation.reg.surf_width = dstgeom->width; + gcmofill->src.config.raw = 0; + gcmofill->src.rotationheight_ldst = gcmofillsrc_rotationheight_ldst; + gcmofill->src.rotationheight.reg.height = dstgeom->height; + + /* Disable alpha blending. */ + gcmofill->src.alphacontrol_ldst = gcmofillsrc_alphacontrol_ldst; + gcmofill->src.alphacontrol.raw = 0; + gcmofill->src.alphacontrol.reg.enable = GCREG_ALPHA_CONTROL_ENABLE_OFF; + + /*********************************************************************** + ** Set fill color. + */ + + fillcolorptr + = (unsigned char *) srcinfo->buf.desc->virtaddr + + srcinfo->rect->top * srcinfo->geom->virtstride + + srcinfo->rect->left * srcformat->bitspp / 8; + + gcmofill->clearcolor_ldst = gcmofill_clearcolor_ldst; + gcmofill->clearcolor.raw = getinternalcolor(fillcolorptr, srcformat); + + /*********************************************************************** + ** Configure and start fill. + */ + + /* Set destination configuration. */ + gcmofill->start.config_ldst = gcmostart_config_ldst; + gcmofill->start.config.raw = 0; + gcmofill->start.config.reg.swizzle = batch->dstformat->swizzle; + gcmofill->start.config.reg.format = batch->dstformat->format; + gcmofill->start.config.reg.command = GCREG_DEST_CONFIG_COMMAND_CLEAR; + + /* Set ROP3. */ + gcmofill->start.rop_ldst = gcmostart_rop_ldst; + gcmofill->start.rop.raw = 0; + gcmofill->start.rop.reg.type = GCREG_ROP_TYPE_ROP3; + gcmofill->start.rop.reg.fg = (unsigned char) bltparams->op.rop; + + /* Set START_DE command. */ + gcmofill->start.startde.cmd.fld = gcfldstartde; + + /* Set destination rectangle. */ + gcmofill->start.rect.left = batch->dstleft + batch->dstoffset; + gcmofill->start.rect.top = batch->dsttop; + gcmofill->start.rect.right = batch->dstright + batch->dstoffset; + gcmofill->start.rect.bottom = batch->dstbottom; + +exit: + GCEXITARG(GCZONE_DO_FILL, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +static enum bverror do_blit_end(struct bvbltparams *bltparams, + struct gcbatch *batch) +{ + enum bverror bverror; + struct gcmomultisrc *gcmomultisrc; + struct gcmostart *gcmostart; + unsigned int buffersize; + + GCENTER(GCZONE_DO_BLIT); + + GCDBG(GCZONE_BATCH, "finalizing the blit, scrcount = %d\n", + batch->gcblit.srccount); + + /* Allocate command buffer. */ + buffersize + = sizeof(struct gcmomultisrc) + + sizeof(struct gcmostart); + + bverror = claim_buffer(batch, buffersize, + (void **) &gcmomultisrc); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, "failed to allocate command buffer"); + goto exit; + } + + /* Configure multi-source control. */ + gcmomultisrc->control_ldst = gcmomultisrc_control_ldst; + gcmomultisrc->control.raw = 0; + gcmomultisrc->control.reg.srccount = batch->gcblit.srccount - 1; + gcmomultisrc->control.reg.horblock + = GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL128; + + /* Skip to the next structure. */ + gcmostart = (struct gcmostart *) (gcmomultisrc + 1); + + /* Set destination configuration. */ + GCDBG(GCZONE_DO_BLIT, "format entry = 0x%08X\n", + (unsigned int) batch->dstformat); + GCDBG(GCZONE_DO_BLIT, " swizzle code = %d\n", + batch->dstformat->swizzle); + GCDBG(GCZONE_DO_BLIT, " format code = %d\n", + batch->dstformat->format); + + gcmostart->config_ldst = gcmostart_config_ldst; + gcmostart->config.raw = 0; + gcmostart->config.reg.swizzle = batch->dstformat->swizzle; + gcmostart->config.reg.format = batch->dstformat->format; + gcmostart->config.reg.command = batch->gcblit.multisrc + ? GCREG_DEST_CONFIG_COMMAND_MULTI_SOURCE_BLT + : GCREG_DEST_CONFIG_COMMAND_BIT_BLT; + + /* Set ROP. */ + gcmostart->rop_ldst = gcmostart_rop_ldst; + gcmostart->rop.raw = 0; + gcmostart->rop.reg.type = GCREG_ROP_TYPE_ROP3; + gcmostart->rop.reg.fg = (unsigned char) batch->gcblit.rop; + + /* Set START_DE command. */ + gcmostart->startde.cmd.fld = gcfldstartde; + + /* Set destination rectangle. */ + gcmostart->rect.left = batch->dstleft + batch->dstoffset; + gcmostart->rect.top = batch->dsttop; + gcmostart->rect.right = batch->dstright + batch->dstoffset; + gcmostart->rect.bottom = batch->dstbottom; + + /* Reset the finalizer. */ + batch->batchend = do_end; + + gc_debug_blt(batch->gcblit.srccount, + abs(batch->dstright - batch->dstleft), + abs(batch->dsttop - batch->dstbottom)); + +exit: + GCEXITARG(GCZONE_DO_BLIT, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + + +static inline int get_offset(struct bvbuffdesc *desc) +{ + int offset; + + if (desc->auxtype == BVAT_PHYSDESC) { + struct bvphysdesc *pdesc; + pdesc = (struct bvphysdesc *) desc->auxptr; + + offset = pdesc->pageoffset & + (GC_BASE_ALIGN - 1); + } else { + offset = (unsigned int) desc->virtaddr & + (GC_BASE_ALIGN - 1); + } + return offset; +} + +static enum bverror do_blit(struct bvbltparams *bltparams, + struct gcbatch *batch, + struct srcinfo *srcinfo, + unsigned int srccount, + struct gcalpha *gca) +{ + enum bverror bverror = BVERR_NONE; + + struct gcmosrc *gcmosrc; + struct gcmosrcalpha *gcmosrcalpha; + + unsigned int i, index; + + struct bvbuffmap *dstmap = NULL; + struct bvsurfgeom *dstgeom = bltparams->dstgeom; + struct bvrect *dstrect = &bltparams->dstrect; + + struct bvformatxlate *srcformat; + struct bvbuffmap *srcmap[2] = { NULL, NULL }; + struct bvbuffdesc *srcdesc; + struct bvsurfgeom *srcgeom; + struct bvrect *srcrect; + int srcleft, srctop, srcright, srcbottom; + int srcoffset, srcsurfleft, srcsurftop; + int srcshift, srcadjust, srcalign; + int multisrc; + + GCENTER(GCZONE_DO_BLIT); + + /* Did destination change? */ + if ((batch->batchflags & (BVBATCH_DST | + BVBATCH_CLIPRECT_ORIGIN | + BVBATCH_CLIPRECT_SIZE | + BVBATCH_DSTRECT_ORIGIN | + BVBATCH_DSTRECT_SIZE)) != 0) { + /* Finalize the previous blit if any. */ + bverror = batch->batchend(bltparams, batch); + if (bverror != BVERR_NONE) + goto exit; + } + + /* Map the destination. */ + bverror = do_map(bltparams->dstdesc, batch, &dstmap); + if (bverror != BVERR_NONE) { + bltparams->errdesc = gccontext.bverrorstr; + goto exit; + } + + /* Set the new destination. */ + bverror = set_dst(bltparams, batch, dstmap); + if (bverror != BVERR_NONE) + goto exit; + + /* Update clipping/destination rect if necessary. */ + bverror = set_clip(bltparams, batch); + if (bverror != BVERR_NONE) + goto exit; + + for (i = 0; i < srccount; i += 1) { + /*************************************************************** + ** Parse the source format. + */ + + srcdesc = srcinfo[i].buf.desc; + srcgeom = srcinfo[i].geom; + srcrect = srcinfo[i].rect; + + /* Parse the source format. */ + GCDBG(GCZONE_FORMAT, "parsing the source format.\n"); + + if (!parse_format(srcgeom->format, &srcformat)) { + BVSETBLTERRORARG((srcinfo[i].index == 0) + ? BVERR_SRC1GEOM_FORMAT + : BVERR_SRC2GEOM_FORMAT, + "invalid source format (%d)", + srcgeom->format); + goto exit; + } + + /* Validate soource geometry. */ + if (!valid_geom(srcdesc, srcgeom, srcformat)) { + BVSETBLTERRORARG((srcinfo->index == 0) + ? BVERR_SRC1GEOM + : BVERR_SRC2GEOM, + "source%d geom exceeds surface size", + srcinfo->index + 1); + goto exit; + } + + srcright = srcrect->left + srcrect->width + batch->deltaright; + srcbottom = srcrect->top + srcrect->height + batch->deltabottom; + + /* Validate the rectangle. */ + if ((srcright > (int) srcgeom->width) || + (srcbottom > (int) srcgeom->height)) { + BVSETBLTERRORARG((srcinfo->index == 0) + ? BVERR_SRC1RECT + : BVERR_SRC2RECT, + "source%d rect exceeds surface size", + srcinfo->index + 1); + goto exit; + } + + GCDBG(GCZONE_SURF, "source surface %d:\n", i); + GCDBG(GCZONE_SURF, " srcaddr[%d] = 0x%08X\n", + i, (unsigned int) srcdesc->virtaddr); + + GCDBG(GCZONE_SURF, " srcsurf = %dx%d, stride = %ld\n", + srcgeom->width, srcgeom->height, + srcgeom->virtstride); + + GCDBG(GCZONE_SURF, " srcrect = (%d,%d)-(%d,%d), %dx%d\n", + srcrect->left, srcrect->top, + srcrect->left + srcrect->width, + srcrect->top + srcrect->height, + srcrect->width, srcrect->height); + + /*************************************************************** + ** Determine source placement. + */ + + /* Compute the source offset in pixels needed to compensate + for the surface base address misalignment if any. */ + srcoffset = get_offset(srcdesc) * 8 / srcformat->bitspp; + + GCDBG(GCZONE_SURF, " source offset = %d\n", srcoffset); + + srcsurfleft = srcrect->left - dstrect->left + srcoffset; + srcsurftop = srcrect->top - dstrect->top; + + GCDBG(GCZONE_SURF, " source surfaceorigin = %d,%d\n", + srcsurfleft, srcsurftop); + + /* (srcsurfleft,srcsurftop) are the coordinates of the source + surface origin. PE requires alignment of the base + address. Compute the alignment requirement in pixels. */ + srcalign = 16 * 8 / srcformat->bitspp; + + GCDBG(GCZONE_SURF, " srcalign = %d\n", srcalign); + + /* Compute the number of pixels the origin has to be + aligned by. */ + srcadjust = srcsurfleft % srcalign; + + GCDBG(GCZONE_SURF, " srcadjust = %d\n", srcadjust); + + /* TODO: multisrc with nv12 format */ + multisrc = (srcformat->format == GCREG_DE_FORMAT_NV12) ? 0 : + (srcadjust == 0); + + GCDBG(GCZONE_DO_BLIT, " multisrc = %d\n", multisrc); + + if (multisrc) { + /* Adjust the origin. */ + srcsurfleft -= srcadjust; + + GCDBG(GCZONE_SURF, + " adjusted source surface origin = %d,%d\n", + srcsurfleft, srcsurftop); + + /* Adjust the source rectangle for the + * single source walker. + */ + srcleft = dstrect->left + batch->deltaleft + srcadjust; + srctop = dstrect->top + batch->deltatop; + + GCDBG(GCZONE_SURF, + " source %d rectangle origin = %d,%d\n", + i, srcleft, srctop); + + /* Compute the surface offset in bytes. */ + srcshift + = srcsurftop * (int) srcgeom->virtstride + + srcsurfleft * (int) srcformat->bitspp / 8; + + GCDBG(GCZONE_SURF, " srcshift = 0x%08X (%d)\n", + srcshift, srcshift); + } else { + srcadjust = srcoffset % srcalign; + + GCDBG(GCZONE_SURF, " single source srcadjust = %d\n", + srcadjust); + + srcleft = srcrect->left + batch->deltaleft + srcadjust; + srctop = srcrect->top + batch->deltatop; + + GCDBG(GCZONE_SURF, + " source %d rectangle origin = %d,%d\n", + i, srcleft, srctop); + + /* No shift needed for single source walker */ + srcshift = 0; + } + + /*************************************************************** + ** Finalize existing blit if necessary. + */ + + if ((batch->batchend != do_blit_end) || + (batch->gcblit.srccount == 4) || + !batch->gcblit.multisrc || !multisrc) { + /* Finalize the previous blit if any. */ + bverror = batch->batchend(bltparams, batch); + if (bverror != BVERR_NONE) + goto exit; + + /* Initialize the new batch. */ + batch->batchend = do_blit_end; + batch->gcblit.srccount = 0; + batch->gcblit.multisrc = multisrc; + batch->gcblit.rop = (gca != NULL) + ? 0xCC : bltparams->op.rop; + } + + /*************************************************************** + ** Map the source. + */ + + bverror = do_map(srcdesc, batch, &srcmap[i]); + if (bverror != BVERR_NONE) { + bltparams->errdesc = gccontext.bverrorstr; + goto exit; + } + + /*************************************************************** + ** Configure source. + */ + + /* Allocate command buffer. */ + bverror = claim_buffer(batch, sizeof(struct gcmosrc), + (void **) &gcmosrc); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, + "failed to allocate command buffer"); + goto exit; + } + + /* Shortcut to the register index. */ + index = batch->gcblit.srccount; + + add_fixup(batch, &gcmosrc->address, srcshift); + + /* Set surface parameters. */ + gcmosrc->address_ldst = gcmosrc_address_ldst[index]; + gcmosrc->address = GET_MAP_HANDLE(srcmap[i]); + + gcmosrc->stride_ldst = gcmosrc_stride_ldst[index]; + gcmosrc->stride = srcgeom->virtstride; + + gcmosrc->rotation_ldst = gcmosrc_rotation_ldst[index]; + gcmosrc->rotation.raw = 0; + gcmosrc->rotation.reg.surf_width + = dstrect->left + srcgeom->width; + + gcmosrc->config_ldst = gcmosrc_config_ldst[index]; + gcmosrc->config.raw = 0; + gcmosrc->config.reg.swizzle = srcformat->swizzle; + gcmosrc->config.reg.format = srcformat->format; + + gcmosrc->origin_ldst = gcmosrc_origin_ldst[index]; + if (multisrc) + gcmosrc->origin.reg = gcregsrcorigin_min; + else { + gcmosrc->origin.reg.x = srcleft; + gcmosrc->origin.reg.y = srctop; + } + + gcmosrc->size_ldst = gcmosrc_size_ldst[index]; + gcmosrc->size.reg = gcregsrcsize_max; + + gcmosrc->rotationheight_ldst + = gcmosrc_rotationheight_ldst[index]; + gcmosrc->rotationheight.reg.height + = dstrect->top + srcgeom->height; + + gcmosrc->rop_ldst = gcmosrc_rop_ldst[index]; + gcmosrc->rop.raw = 0; + gcmosrc->rop.reg.type = GCREG_ROP_TYPE_ROP3; + gcmosrc->rop.reg.fg = (unsigned char) batch->gcblit.rop; + + gcmosrc->mult_ldst = gcmosrc_mult_ldst[index]; + gcmosrc->mult.raw = 0; + gcmosrc->mult.reg.srcglobalpremul + = GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE; + + if ((srcgeom->format & OCDFMTDEF_NON_PREMULT) != 0) + gcmosrc->mult.reg.srcpremul + = GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE; + else + gcmosrc->mult.reg.srcpremul + = GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE; + + if ((dstgeom->format & OCDFMTDEF_NON_PREMULT) != 0) { + gcmosrc->mult.reg.dstpremul + = GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE; + + gcmosrc->mult.reg.dstdemul + = GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE; + } else { + gcmosrc->mult.reg.dstpremul + = GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE; + + gcmosrc->mult.reg.dstdemul + = GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE; + } + + if (srcformat->format == GCREG_DE_FORMAT_NV12) { + struct gcmosrcplanaryuv *yuv; + int uvshift; + + if (multisrc && srcsurftop % 2) { + /* We can't shift the uv plane by + * an odd number of rows. + */ + BVSETBLTERROR(BVERR_SRC1RECT, + "src/dst y coordinate combination not supported"); + goto exit; + } + + bverror = claim_buffer(batch, + sizeof(struct gcmosrcplanaryuv), + (void **) &yuv); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, + "failed to allocate command buffer for planar yuv"); + goto exit; + } + + yuv->uplaneaddress_ldst = + gcmosrc_uplaneaddress_ldst[index]; + yuv->uplanestride_ldst = + gcmosrc_uplanestride_ldst[index]; + yuv->vplaneaddress_ldst = + gcmosrc_vplaneaddress_ldst[index]; + yuv->vplanestride_ldst = + gcmosrc_vplanestride_ldst[index]; + + if (multisrc) { + /* uv plane is half height */ + uvshift = (srcsurftop / 2) * + (int) srcgeom->virtstride + + srcsurfleft * + (int) srcformat->bitspp / 8; + } else { + /* No shift needed for single source walker */ + uvshift = 0; + } + + GCDBG(GCZONE_SURF, " uvshift = 0x%08X (%d)\n", + uvshift, uvshift); + + /* add fixed offset from Y plane */ + uvshift += srcgeom->virtstride * srcgeom->height; + + GCDBG(GCZONE_SURF, " final uvshift = 0x%08X (%d)\n", + uvshift, uvshift); + + yuv->uplaneaddress = GET_MAP_HANDLE(srcmap[i]); + add_fixup(batch, &yuv->uplaneaddress, uvshift); + + yuv->uplanestride = srcgeom->virtstride; + + yuv->vplaneaddress = GET_MAP_HANDLE(srcmap[i]); + add_fixup(batch, &yuv->vplaneaddress, uvshift); + + yuv->vplanestride = srcgeom->virtstride; + } + + if ((gca != NULL) && ((srccount == 1) || (i > 0))) { + gcmosrc->alphacontrol_ldst + = gcmosrc_alphacontrol_ldst[index]; + gcmosrc->alphacontrol.raw = 0; + gcmosrc->alphacontrol.reg.enable + = GCREG_ALPHA_CONTROL_ENABLE_ON; + + /* Allocate command buffer. */ + bverror = claim_buffer(batch, + sizeof(struct gcmosrcalpha), + (void **) &gcmosrcalpha); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, + "failed to allocate command buffer"); + goto exit; + } + + gcmosrcalpha->alphamodes_ldst + = gcmosrcalpha_alphamodes_ldst[index]; + gcmosrcalpha->alphamodes.raw = 0; + gcmosrcalpha->alphamodes.reg.src_global_alpha + = gca->src_global_alpha_mode; + gcmosrcalpha->alphamodes.reg.dst_global_alpha + = gca->dst_global_alpha_mode; + + if (srccount == 1) { + GCDBG(GCZONE_BLEND, "k1 sets src blend.\n"); + GCDBG(GCZONE_BLEND, "k2 sets dst blend.\n"); + + gcmosrcalpha->alphamodes.reg.src_blend + = gca->k1->factor_mode; + gcmosrcalpha->alphamodes.reg.src_color_reverse + = gca->k1->color_reverse; + + gcmosrcalpha->alphamodes.reg.dst_blend + = gca->k2->factor_mode; + gcmosrcalpha->alphamodes.reg.dst_color_reverse + = gca->k2->color_reverse; + } else { + GCDBG(GCZONE_BLEND, "k1 sets dst blend.\n"); + GCDBG(GCZONE_BLEND, "k2 sets src blend.\n"); + + gcmosrcalpha->alphamodes.reg.src_blend + = gca->k2->factor_mode; + gcmosrcalpha->alphamodes.reg.src_color_reverse + = gca->k2->color_reverse; + + gcmosrcalpha->alphamodes.reg.dst_blend + = gca->k1->factor_mode; + gcmosrcalpha->alphamodes.reg.dst_color_reverse + = gca->k1->color_reverse; + } + + GCDBG(GCZONE_BLEND, "dst blend:\n"); + GCDBG(GCZONE_BLEND, " factor = %d\n", + gcmosrcalpha->alphamodes.reg.dst_blend); + GCDBG(GCZONE_BLEND, " inverse = %d\n", + gcmosrcalpha->alphamodes.reg.dst_color_reverse); + + GCDBG(GCZONE_BLEND, "src blend:\n"); + GCDBG(GCZONE_BLEND, " factor = %d\n", + gcmosrcalpha->alphamodes.reg.src_blend); + GCDBG(GCZONE_BLEND, " inverse = %d\n", + gcmosrcalpha->alphamodes.reg.src_color_reverse); + + gcmosrcalpha->srcglobal_ldst + = gcmosrcalpha_srcglobal_ldst[index]; + gcmosrcalpha->srcglobal.raw = gca->src_global_color; + + gcmosrcalpha->dstglobal_ldst + = gcmosrcalpha_dstglobal_ldst[index]; + gcmosrcalpha->dstglobal.raw = gca->dst_global_color; + } else { + GCDBG(GCZONE_BLEND, "blending disabled.\n"); + + gcmosrc->alphacontrol_ldst + = gcmosrc_alphacontrol_ldst[index]; + gcmosrc->alphacontrol.raw = 0; + gcmosrc->alphacontrol.reg.enable + = GCREG_ALPHA_CONTROL_ENABLE_OFF; + } + + batch->gcblit.srccount += 1; + } + +exit: + GCEXITARG(GCZONE_DO_BLIT, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +static enum bverror do_filter(struct bvbltparams *bltparams, + struct gcbatch *batch) +{ + enum bverror bverror; + GCENTER(GCZONE_DO_FILTER); + BVSETBLTERROR(BVERR_SRC1_HORZSCALE, "scaling not supported"); + GCEXITARG(GCZONE_DO_FILTER, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + + +/******************************************************************************* + * Library constructor and destructor. + */ + +void bv_init(void) +{ + GCDBG_REGISTER(gcbv); + GCLOCK_INIT(&gccontext.batchlock); + GCLOCK_INIT(&gccontext.bufferlock); + GCLOCK_INIT(&gccontext.fixuplock); + GCLOCK_INIT(&gccontext.maplock); + GCLOCK_INIT(&gccontext.callbacklock); + INIT_LIST_HEAD(&gccontext.callbacklist); + INIT_LIST_HEAD(&gccontext.callbackvac); + INIT_LIST_HEAD(&gccontext.vac_unmap); +} + +void bv_exit(void) +{ + struct list_head *head; + struct gcschedunmap *bufunmap; + struct bvbuffmap *bufmap; + struct gcbuffer *buffer; + struct gcfixup *fixup; + struct gcvacbatch *batch; + + while (!list_empty(&gccontext.vac_unmap)) { + head = gccontext.vac_unmap.next; + bufunmap = list_entry(head, struct gcschedunmap, link); + list_del(head); + gcfree(bufunmap); + } + + while (gccontext.vac_buffmap != NULL) { + bufmap = gccontext.vac_buffmap; + gccontext.vac_buffmap = bufmap->nextmap; + gcfree(bufmap); + } + + while (gccontext.vac_buffers != NULL) { + buffer = gccontext.vac_buffers; + gccontext.vac_buffers = buffer->next; + gcfree(buffer); + } + + while (gccontext.vac_fixups != NULL) { + fixup = gccontext.vac_fixups; + gccontext.vac_fixups = fixup->next; + gcfree(fixup); + } + + while (gccontext.vac_batches != NULL) { + batch = gccontext.vac_batches; + gccontext.vac_batches = batch->next; + gcfree(batch); + } +} + + +/******************************************************************************* + * Library API. + */ + +enum bverror bv_map(struct bvbuffdesc *buffdesc) +{ + enum bverror bverror; + struct bvbuffmap *bvbuffmap; + + GCENTERARG(GCZONE_MAPPING, "buffdesc = 0x%08X\n", + (unsigned int) buffdesc); + + if (buffdesc == NULL) { + BVSETERROR(BVERR_BUFFERDESC, "bvbuffdesc is NULL"); + goto exit; + } + + if (buffdesc->structsize < STRUCTSIZE(buffdesc, map)) { + BVSETERROR(BVERR_BUFFERDESC_VERS, "argument has invalid size"); + goto exit; + } + + bverror = do_map(buffdesc, NULL, &bvbuffmap); + +exit: + GCEXITARG(GCZONE_MAPPING, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +enum bverror bv_unmap(struct bvbuffdesc *buffdesc) +{ + enum bverror bverror = BVERR_NONE; + enum bverror otherbverror = BVERR_NONE; + struct bvbuffmap *prev = NULL; + struct bvbuffmap *bvbuffmap; + struct bvbuffmapinfo *bvbuffmapinfo; + struct gcmap gcmap; + + GCENTERARG(GCZONE_MAPPING, "buffdesc = 0x%08X\n", + (unsigned int) buffdesc); + + /* Lock access to the mapping list. */ + GCLOCK(&gccontext.maplock); + + if (buffdesc == NULL) { + BVSETERROR(BVERR_BUFFERDESC, "bvbuffdesc is NULL"); + goto exit; + } + + if (buffdesc->structsize < STRUCTSIZE(buffdesc, map)) { + BVSETERROR(BVERR_BUFFERDESC_VERS, "argument has invalid size"); + goto exit; + } + + /* Is the buffer mapped? */ + bvbuffmap = buffdesc->map; + if (bvbuffmap == NULL) { + GCDBG(GCZONE_MAPPING, "buffer isn't mapped.\n"); + goto exit; + } + + /* Try to find our mapping. */ + while (bvbuffmap != NULL) { + if (bvbuffmap->bv_unmap == bv_unmap) + break; + prev = bvbuffmap; + bvbuffmap = bvbuffmap->nextmap; + } + + /* Are there other implementations? */ + if ((prev != NULL) || (bvbuffmap->nextmap != NULL)) { + GCDBG(GCZONE_MAPPING, + "have mappings from other implementations.\n"); + + /* Was our mapping found? */ + if (bvbuffmap == NULL) { + GCDBG(GCZONE_MAPPING, + "no mapping from our implementation.\n"); + + /* No, call other implementations. */ + bverror = buffdesc->map->bv_unmap(buffdesc); + goto exit; + } + + if (bvbuffmap->structsize + < STRUCTSIZE(bvbuffmap, nextmap)) { + BVSETERROR(BVERR_BUFFERDESC_VERS, + "unsupported bvbuffdesc version"); + goto exit; + } + + /* Remove our mapping. */ + if (prev == NULL) + buffdesc->map = bvbuffmap->nextmap; + else + prev->nextmap = bvbuffmap->nextmap; + + /* Call other implementation. */ + otherbverror = buffdesc->map->bv_unmap(buffdesc); + + /* Add our mapping back. */ + bvbuffmap->nextmap = buffdesc->map; + buffdesc->map = bvbuffmap; + prev = NULL; + } else { + GCDBG(GCZONE_MAPPING, + "no mappings from other implementations.\n"); + } + + /* Get the info structure. */ + bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle; + + GCDBG(GCZONE_MAPPING, "bvbuffmap = 0x%08X\n", (unsigned int) bvbuffmap); + GCDBG(GCZONE_MAPPING, "handle = 0x%08X\n", bvbuffmapinfo->handle); + + /* Explicit unmapping. */ + if (bvbuffmapinfo->usermap == 0) + GCERR("explicit count is already zero.\n"); + bvbuffmapinfo->usermap = 0; + + GCDBG(GCZONE_MAPPING, "explicit count = %d\n", + bvbuffmapinfo->usermap); + GCDBG(GCZONE_MAPPING, "implicit count = %d\n", + bvbuffmapinfo->automap); + + /* Do we have implicit mappings? */ + if (bvbuffmapinfo->automap > 0) { + GCDBG(GCZONE_MAPPING, "have implicit unmappings.\n"); + goto exit; + } + + /* Unmap the buffer. */ + memset(&gcmap, 0, sizeof(gcmap)); + gcmap.handle = bvbuffmapinfo->handle; + gc_unmap_wrapper(&gcmap); + if (gcmap.gcerror != GCERR_NONE) { + BVSETERROR(BVERR_OOM, "unable to free gccore memory"); + goto exit; + } + + /* Remove from the buffer descriptor list. */ + if (prev == NULL) + buffdesc->map = bvbuffmap->nextmap; + else + prev->nextmap = bvbuffmap->nextmap; + + /* Invalidate the record. */ + bvbuffmap->structsize = 0; + + /* Add to the vacant list. */ + bvbuffmap->nextmap = gccontext.vac_buffmap; + gccontext.vac_buffmap = bvbuffmap; + +exit: + /* Unlock access to the mapping list. */ + GCUNLOCK(&gccontext.maplock); + + GCEXITARG(GCZONE_MAPPING, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +enum bverror bv_blt(struct bvbltparams *bltparams) +{ + enum bverror bverror = BVERR_NONE; + struct gcalpha *gca = NULL; + struct gcalpha _gca; + unsigned int op, type, blend, format; + unsigned int batchexec = 0; + bool nop = false; + struct gcbatch *batch; + int src1used, src2used, maskused; + struct srcinfo srcinfo[2]; + unsigned short rop; + struct gccommit gccommit; + int srccount, res; + + GCENTERARG(GCZONE_BLIT, "bltparams = 0x%08X\n", + (unsigned int) bltparams); + + /* Verify blt parameters structure. */ + if (bltparams == NULL) { + BVSETERROR(BVERR_BLTPARAMS_VERS, "bvbltparams is NULL"); + goto exit; + } + + if (bltparams->structsize < STRUCTSIZE(bltparams, callbackdata)) { + BVSETERROR(BVERR_BLTPARAMS_VERS, "argument has invalid size"); + goto exit; + } + + /* Reset the error message. */ + bltparams->errdesc = NULL; + + /* Verify the destination parameters structure. */ + GCDBG(GCZONE_SURF, "verifying destination parameters.\n"); + + res = verify_surface(0, (union bvinbuff *) &bltparams->dstdesc, + bltparams->dstgeom); + if (res != -1) { + BVSETBLTSURFERROR(res, g_destsurferr); + goto exit; + } + + /* Extract the operation flags. */ + op = (bltparams->flags & BVFLAG_OP_MASK) >> BVFLAG_OP_SHIFT; + type = (bltparams->flags & BVFLAG_BATCH_MASK) >> BVFLAG_BATCH_SHIFT; + + switch (type) { + case (BVFLAG_BATCH_NONE >> BVFLAG_BATCH_SHIFT): + bverror = allocate_batch(&batch); + if (bverror != BVERR_NONE) { + bltparams->errdesc = gccontext.bverrorstr; + goto exit; + } + + batchexec = 1; + batch->batchflags = 0x7FFFFFFF; + + GCDBG(GCZONE_BATCH, "BVFLAG_BATCH_NONE(0x%08X)\n", + (unsigned int) batch); + break; + + case (BVFLAG_BATCH_BEGIN >> BVFLAG_BATCH_SHIFT): + bverror = allocate_batch(&batch); + if (bverror != BVERR_NONE) { + bltparams->errdesc = gccontext.bverrorstr; + goto exit; + } + + bltparams->batch = (struct bvbatch *) batch; + + batchexec = 0; + bltparams->batchflags = + batch->batchflags = 0x7FFFFFFF; + + GCDBG(GCZONE_BATCH, "BVFLAG_BATCH_BEGIN(0x%08X)\n", + (unsigned int) batch); + break; + + case (BVFLAG_BATCH_CONTINUE >> BVFLAG_BATCH_SHIFT): + batch = (struct gcbatch *) bltparams->batch; + if (batch == NULL) { + BVSETBLTERROR(BVERR_BATCH, "batch is not initialized"); + goto exit; + } + + if (batch->structsize < STRUCTSIZE(batch, unmap)) { + BVSETBLTERROR(BVERR_BATCH, "invalid batch"); + goto exit; + } + + batchexec = 0; + batch->batchflags = bltparams->batchflags; + + GCDBG(GCZONE_BATCH, "BVFLAG_BATCH_CONTINUE(0x%08X)\n", + (unsigned int) batch); + break; + + case (BVFLAG_BATCH_END >> BVFLAG_BATCH_SHIFT): + batch = (struct gcbatch *) bltparams->batch; + if (batch == NULL) { + BVSETBLTERROR(BVERR_BATCH, "batch is not initialized"); + goto exit; + } + + if (batch->structsize < STRUCTSIZE(batch, unmap)) { + BVSETBLTERROR(BVERR_BATCH, "invalid batch"); + goto exit; + } + + batchexec = 1; + nop = (bltparams->batchflags & BVBATCH_ENDNOP) != 0; + batch->batchflags = bltparams->batchflags; + + GCDBG(GCZONE_BATCH, "BVFLAG_BATCH_END(0x%08X)\n", + (unsigned int) batch); + break; + + default: + BVSETBLTERROR(BVERR_BATCH, "unrecognized batch type"); + goto exit; + } + + GCDBG(GCZONE_BATCH, "batchflags=0x%08X\n", + (unsigned int) batch->batchflags); + + GCDUMPSCHEDULE(); + + if (!nop) { + /* Verify the batch change flags. */ + VERIFYBATCH(batch->batchflags >> 12, &batch->prevdstrect, + &bltparams->dstrect); + + switch (op) { + case (BVFLAG_ROP >> BVFLAG_OP_SHIFT): + GCDBG(GCZONE_BLIT, "BVFLAG_ROP\n"); + + rop = bltparams->op.rop; + src1used = ((rop & 0xCCCC) >> 2) + ^ (rop & 0x3333); + src2used = ((rop & 0xF0F0) >> 4) + ^ (rop & 0x0F0F); + maskused = ((rop & 0xFF00) >> 8) + ^ (rop & 0x00FF); + break; + + case (BVFLAG_BLEND >> BVFLAG_OP_SHIFT): + GCDBG(GCZONE_BLIT, "BVFLAG_BLEND\n"); + + blend = bltparams->op.blend; + format = (blend & BVBLENDDEF_FORMAT_MASK) + >> BVBLENDDEF_FORMAT_SHIFT; + + bverror = parse_blend(bltparams, blend, &_gca); + if (bverror != BVERR_NONE) + goto exit; + + gca = &_gca; + + switch (format) { + case (BVBLENDDEF_FORMAT_CLASSIC + >> BVBLENDDEF_FORMAT_SHIFT): + src1used = gca->src1used; + src2used = gca->src2used; + maskused = blend & BVBLENDDEF_REMOTE; + break; + + default: + BVSETBLTERROR(BVERR_BLEND, + "unrecognized blend format"); + goto exit; + } + break; + + case (BVFLAG_FILTER >> BVFLAG_OP_SHIFT): + GCDBG(GCZONE_BLIT, "BVFLAG_FILTER\n"); + BVSETBLTERROR(BVERR_OP, + "filter operation not supported"); + goto exit; + + default: + BVSETBLTERROR(BVERR_OP, "unrecognized operation"); + goto exit; + } + + srccount = 0; + + /* Verify the src1 parameters structure. */ + if (src1used) { + GCDBG(GCZONE_BLIT, "src1used\n"); + GCDBG(GCZONE_SURF, "verifying source1 parameters.\n"); + + res = verify_surface( + bltparams->flags & BVBATCH_TILE_SRC1, + &bltparams->src1, bltparams->src1geom); + if (res != -1) { + BVSETBLTSURFERROR(res, g_src1surferr); + goto exit; + } + + /* Verify the batch change flags. */ + VERIFYBATCH(batch->batchflags >> 14, + &batch->prevsrc1rect, + &bltparams->src1rect); + + /* Same as the destination? */ + if (same_phys_area(bltparams->src1.desc, + &bltparams->src1rect, + bltparams->dstdesc, + &bltparams->dstrect)) { + GCDBG(GCZONE_BLIT, "src1 is the same as dst\n"); + } else { + srcinfo[srccount].index = 0; + srcinfo[srccount].buf = bltparams->src1; + srcinfo[srccount].geom = bltparams->src1geom; + srcinfo[srccount].rect = &bltparams->src1rect; + + srccount += 1; + } + } + + /* Verify the src2 parameters structure. */ + if (src2used) { + GCDBG(GCZONE_BLIT, "src2used\n"); + GCDBG(GCZONE_SURF, "verifying source2 parameters.\n"); + + res = verify_surface( + bltparams->flags & BVBATCH_TILE_SRC2, + &bltparams->src2, bltparams->src2geom); + if (res != -1) { + BVSETBLTSURFERROR(res, g_src2surferr); + goto exit; + } + + /* Verify the batch change flags. */ + VERIFYBATCH(batch->batchflags >> 16, + &batch->prevsrc2rect, + &bltparams->src2rect); + + /* Same as the destination? */ + if (same_phys_area(bltparams->src2.desc, + &bltparams->src2rect, + bltparams->dstdesc, + &bltparams->dstrect)) { + GCDBG(GCZONE_BLIT, "src2 is the same as dst\n"); + } else { + srcinfo[srccount].index = 1; + srcinfo[srccount].buf = bltparams->src2; + srcinfo[srccount].geom = bltparams->src2geom; + srcinfo[srccount].rect = &bltparams->src2rect; + + srccount += 1; + } + } + + /* Verify the mask parameters structure. */ + if (maskused) { + GCDBG(GCZONE_BLIT, "maskused\n"); + GCDBG(GCZONE_SURF, "verifying mask parameters.\n"); + + res = verify_surface( + bltparams->flags & BVBATCH_TILE_MASK, + &bltparams->mask, bltparams->maskgeom); + if (res != -1) { + BVSETBLTSURFERROR(res, g_masksurferr); + goto exit; + } + + /* Verify the batch change flags. */ + VERIFYBATCH(batch->batchflags >> 18, + &batch->prevmaskrect, + &bltparams->maskrect); + + BVSETERROR(BVERR_OP, + "operation with mask not supported"); + goto exit; + } + + GCDBG(GCZONE_BLIT, "srccount = %d\n", srccount); + + switch (srccount) { + case 0: + bverror = do_blit(bltparams, batch, NULL, 0, gca); + if (bverror != BVERR_NONE) + goto exit; + break; + + case 1: + if (EQ_SIZE((*srcinfo[0].rect), bltparams->dstrect)) + bverror = do_blit(bltparams, batch, + srcinfo, 1, gca); + else if ((srcinfo[0].rect->width == 1) && + (srcinfo[0].rect->height == 1)) + bverror = do_fill(bltparams, batch, srcinfo); + else + bverror = do_filter(bltparams, batch); + if (bverror != BVERR_NONE) + goto exit; + break; + + case 2: + if (EQ_SIZE((*srcinfo[0].rect), bltparams->dstrect)) + if (EQ_SIZE((*srcinfo[1].rect), + bltparams->dstrect)) + bverror = do_blit(bltparams, batch, + srcinfo, 2, gca); + else + BVSETBLTERROR(BVERR_SRC2_HORZSCALE, + "scaling not supported"); + else + if (EQ_SIZE((*srcinfo[1].rect), + bltparams->dstrect)) + BVSETBLTERROR(BVERR_SRC1_HORZSCALE, + "scaling not supported"); + else + BVSETBLTERROR(BVERR_SRC1_HORZSCALE, + "scaling not supported"); + if (bverror != BVERR_NONE) + goto exit; + } + } + + if (batchexec) { + struct gcmoflush *flush; + + GCDBG(GCZONE_BLIT, "preparing to submit the batch.\n"); + + /* Finalize the current operation. */ + bverror = batch->batchend(bltparams, batch); + if (bverror != BVERR_NONE) + goto exit; + + /* Add PE flush. */ + GCDBG(GCZONE_BLIT, "appending the flush.\n"); + bverror = claim_buffer(batch, sizeof(struct gcmoflush), + (void **) &flush); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, + "failed to allocate command buffer"); + goto exit; + } + + flush->flush_ldst = gcmoflush_flush_ldst; + flush->flush.reg = gcregflush_pe2D; + + /* Process asynchronous operation. */ + if ((bltparams->flags & BVFLAG_ASYNC) == 0) { + GCDBG(GCZONE_BLIT, "synchronous batch.\n"); + gccommit.callback = NULL; + gccommit.callbackparam = NULL; + gccommit.asynchronous = false; + } else { + struct gccallbackinfo *gccallbackinfo; + + GCDBG(GCZONE_BLIT, "asynchronous batch (0x%08X):\n", + bltparams->flags); + + if (bltparams->callbackfn == NULL) { + GCDBG(GCZONE_BLIT, "no callback given.\n"); + gccommit.callback = NULL; + gccommit.callbackparam = NULL; + } else { + bverror = get_callbackinfo(&gccallbackinfo); + if (bverror != BVERR_NONE) { + BVSETBLTERROR(BVERR_OOM, + "callback allocation failed"); + goto exit; + } + + gccallbackinfo->callbackfn + = bltparams->callbackfn; + gccallbackinfo->callbackdata + = bltparams->callbackdata; + + gccommit.callback = gccallback; + gccommit.callbackparam = gccallbackinfo; + + GCDBG(GCZONE_BLIT, + "gcbv_callback = 0x%08X\n", + (unsigned int) gccommit.callback); + GCDBG(GCZONE_BLIT, + "gcbv_param = 0x%08X\n", + (unsigned int) gccommit.callbackparam); + GCDBG(GCZONE_BLIT, + "bltsville_callback = 0x%08X\n", + (unsigned int) + gccallbackinfo->callbackfn); + GCDBG(GCZONE_BLIT, + "bltsville_param = 0x%08X\n", + (unsigned int) + gccallbackinfo->callbackdata); + } + + gccommit.asynchronous = true; + } + + /* Process scheduled unmappings. */ + unmap_implicit(batch); + + INIT_LIST_HEAD(&gccommit.unmap); + list_splice_init(&batch->unmap, &gccommit.unmap); + + /* Pass the batch for execution. */ + GCDUMPBATCH(batch); + + gccommit.gcerror = GCERR_NONE; + gccommit.entrypipe = GCPIPE_2D; + gccommit.exitpipe = GCPIPE_2D; + gccommit.buffer = batch->bufhead; + + GCDBG(GCZONE_BLIT, "submitting the batch.\n"); + gc_commit_wrapper(&gccommit); + + /* Move the list of mappings back to batch. */ + list_splice_init(&gccommit.unmap, &batch->unmap); + + /* Error? */ + if (gccommit.gcerror != GCERR_NONE) { + switch (gccommit.gcerror) { + case GCERR_OODM: + case GCERR_CTX_ALLOC: + BVSETBLTERROR(BVERR_OOM, + "unable to allocate gccore memory"); + goto exit; + default: + BVSETBLTERROR(BVERR_RSRC, + "gccore error"); + + goto exit; + } + } + + GCDBG(GCZONE_BLIT, "batch is submitted.\n"); + } + +exit: + if ((batch != NULL) && batchexec) { + GCDUMPSCHEDULE(); + free_batch(batch); + bltparams->batch = NULL; + } + + GCEXITARG(GCZONE_BLIT, "bv%s = %d\n", + (bverror == BVERR_NONE) ? "result" : "error", bverror); + return bverror; +} + +enum bverror bv_cache(struct bvcopparams *copparams) +{ + enum bverror bverror = BVERR_NONE; + unsigned int bytespp = 0; /* bytes per pixel */ + unsigned long vert_offset, horiz_offset; + + struct c2dmrgn rgn[3]; + int container_size = 0; + + unsigned long subsample; + unsigned long vendor; + unsigned long layout; + unsigned long size; + unsigned long container; + + subsample = copparams->geom->format & OCDFMTDEF_SUBSAMPLE_MASK; + vendor = copparams->geom->format & OCDFMTDEF_VENDOR_MASK; + layout = copparams->geom->format & OCDFMTDEF_LAYOUT_MASK; + size = copparams->geom->format & OCDFMTDEF_COMPONENTSIZEMINUS1_MASK; + container = copparams->geom->format & OCDFMTDEF_CONTAINER_MASK; + + if (vendor != OCDFMTDEF_VENDOR_ALL) { + bverror = BVERR_FORMAT; + goto exit; + } + + switch (container) { + case OCDFMTDEF_CONTAINER_8BIT: + container_size = 8; + break; + case OCDFMTDEF_CONTAINER_16BIT: + container_size = 16; + break; + case OCDFMTDEF_CONTAINER_24BIT: + container_size = 24; + break; + case OCDFMTDEF_CONTAINER_32BIT: + container_size = 32; + break; + case OCDFMTDEF_CONTAINER_48BIT: + container_size = 48; + break; + case OCDFMTDEF_CONTAINER_64BIT: + container_size = 64; + break; + } + + switch (layout) { + case OCDFMTDEF_PACKED: + switch (subsample) { + case OCDFMTDEF_SUBSAMPLE_NONE: + if (size >= 8) { + bytespp = container_size / 8; + } else { + GCERR("format not supported.\n"); + bverror = BVERR_FORMAT; + goto exit; + } + break; + + case OCDFMTDEF_SUBSAMPLE_422_YCbCr: + bytespp = (container_size / 2) / 8; + break; + + case OCDFMTDEF_SUBSAMPLE_420_YCbCr: + bverror = BVERR_FORMAT; + goto exit; + break; + + case OCDFMTDEF_SUBSAMPLE_411_YCbCr: + bverror = BVERR_FORMAT; + goto exit; + break; + + default: + bverror = BVERR_FORMAT; + goto exit; + } + + rgn[0].span = copparams->rect->width * bytespp; + rgn[0].lines = copparams->rect->height; + rgn[0].stride = copparams->geom->virtstride; + horiz_offset = copparams->rect->left * bytespp; + vert_offset = copparams->rect->top; + + rgn[0].start = (void *) ((unsigned long) + copparams->desc->virtaddr + + vert_offset * rgn[0].stride + + horiz_offset); + + gcbvcacheop(1, rgn, copparams->cacheop); + break; + + case OCDFMTDEF_2_PLANE_YCbCr: + /* 1 byte per pixel */ + rgn[0].span = copparams->rect->width; + rgn[0].lines = copparams->rect->height; + rgn[0].stride = copparams->geom->virtstride; + rgn[0].start = (void *) + ((unsigned long) copparams->desc->virtaddr + + copparams->rect->top * rgn[0].stride + + copparams->rect->left); + + rgn[1].span = copparams->rect->width; + rgn[1].lines = copparams->rect->height / 2; + rgn[1].stride = copparams->geom->virtstride; + rgn[1].start = rgn[0].start + + copparams->geom->height * rgn[0].stride; + + GCDBG(GCZONE_CACHE, + "virtaddr %p start[0] 0x%08x start[1] 0x%08x\n", + copparams->desc->virtaddr, rgn[0].start, rgn[1].start); + + gcbvcacheop(2, rgn, copparams->cacheop); + break; + + default: + GCERR("format 0x%x (%d) not supported.\n", + copparams->geom->format, copparams->geom->format); + bverror = BVERR_FORMAT; + break; + } + +exit: + if (bverror != BVERR_NONE) + GCERR("bverror = %d\n", bverror); + + return bverror; +} diff --git a/gcbv/mirror/gcdbglog.c b/gcbv/mirror/gcdbglog.c new file mode 100644 index 0000000..7a1a125 --- /dev/null +++ b/gcbv/mirror/gcdbglog.c @@ -0,0 +1,1696 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stdarg.h> +#include <stdio.h> +#include <unistd.h> +#include <gcx.h> +#include "gcmain.h" + + +#if GCDEBUG_ENABLE + +/******************************************************************************* + * Debug switches. + */ + +/* Dumping enable default state. */ +#define GC_DUMP_ENABLE 0 + +/* Ignore all zones as if they were all enabled in all modules. */ +#define GC_IGNORE_ZONES 0 + +/* When enabled, all output is collected into a buffer with a predefined size. + * GC_DUMP_BUFFER_SIZE determines the size of the buffer and GC_ENABLE_OVERFLOW + * controls what happens when the buffer gets full. */ +#define GC_BUFFERED_OUTPUT 0 + +/* Debug output buffer size. */ +#define GC_DUMP_BUFFER_SIZE (200 * 1024) + +/* If disabled, the contents of the buffer will be dumped to the console when + * the buffer gets full. + * If enabled, wrap around mode is enabled where when the buffer gets full, + * the oldest entries are overwritten with the new entrie. To dump the buffer + * to the console gc_dump_flush must be called explicitly. */ +#define GC_ENABLE_OVERFLOW 1 + +/* Specifies how many prints are accumulated in the buffer before the buffer is + * flushed. Set to zero to disable auto dumping mode. */ +#define GC_FLUSH_COUNT 0 + +/* Specifies the maximum number of threads that will be tracked in an attempt + * to visually separate messages from different threads. To disable thread + * tracking, set to 0 or 1. */ +#define GC_THREAD_COUNT 20 + +/* Specifies spacing for thread messages. */ +#define GC_THREAD_INDENT 0 + +/* When set to non-zero, specifies how many prints are accumulated in the + * buffer before the buffer is flushed. */ +#define GC_SHOW_DUMP_LINE 1 + +/* If enabled, each print statement will be preceeded with the current + * process ID. */ +#define GC_SHOW_PID 1 + +/* If enabled, internal logging validation code is turned on. */ +#define GC_DEBUG_SELF 0 + +/* Maximum length of a dump string. */ +#define GC_MAXSTR_LENGTH 256 + + +/******************************************************************************* + * Miscellaneous macros. + */ + +#define GC_PTR2INT(p) \ +( \ + (unsigned int) (p) \ +) + +#define GC_ALIGN(n, align) \ +( \ + ((n) + ((align) - 1)) & ~((align) - 1) \ +) + +#define GC_PTRALIGNMENT(p, alignment) \ +( \ + GC_ALIGN(GC_PTR2INT(p), alignment) - GC_PTR2INT(p) \ +) + +#define GC_VARARG_ALIGNMENT sizeof(unsigned long long) + +#if defined(GCDBGFILTER) +#undef GCDBGFILTER +#endif + +#define GCDBGFILTER \ + (*filter) + +#if GC_IGNORE_ZONES +#define GC_VERIFY_ENABLE(filter, zone) \ + (g_initdone) +#else +#define GC_VERIFY_ENABLE(filter, zone) \ + (g_initdone && ((filter == NULL) || ((filter->zone & zone) != 0))) +#endif + +#if GC_SHOW_DUMP_LINE +#define GC_DUMPLINE_FORMAT "[%12d] " +#endif + +#if GC_SHOW_PID +#define GC_PID_FORMAT "[pid=%04X] " +#endif + +#define GC_EOL_RESERVE 1 + +/******************************************************************************* + * Dump item header definition. + */ + +enum itemtype { + GC_BUFITEM_NONE, + GC_BUFITEM_STRING, + GC_BUFITEM_BUFFER +}; + +/* Common item head/buffer terminator. */ +struct itemhead { + enum itemtype type; +}; + + +/******************************************************************************* + * Supported dump items. + */ + +/* GC_BUFITEM_STRING: buffered string. */ +struct itemstring { + enum itemtype itemtype; + int indent; + +#if GC_SHOW_PID + pid_t pid; +#endif + +#if GC_SHOW_DUMP_LINE + unsigned int dumpline; +#endif + + const char *message; + va_list messagedata; + unsigned int datasize; +}; + +/* GC_BUFITEM_BUFFER: buffered memory. */ +enum buffertype { + GC_BUFTYPE_GENERIC, + GC_BUFTYPE_COMMAND, + GC_BUFTYPE_SURFACE +}; + +#define GC_GENERIC_DATA_COUNT 8 +#define GC_SURFACE_DATA_COUNT 64 + +struct itembuffer { + enum itemtype itemtype; + enum buffertype buffertype; + int indent; + + unsigned int surfwidth; + unsigned int surfheight; + unsigned int surfbpp; + unsigned int x1, y1; + unsigned int x2, y2; + + unsigned int datasize; + unsigned int gpuaddr; +}; + + +/******************************************************************************* + * Debug output buffer. + */ + +struct threadinfo { + pid_t pid; + int msgindent; + int threadindent; +}; + +struct buffout { + int enable; + +#if GC_THREAD_COUNT > 1 + unsigned int threadcount; + struct threadinfo threadinfo[1 + GC_THREAD_COUNT]; +#else + struct threadinfo threadinfo[1]; +#endif + +#if GC_SHOW_DUMP_LINE + unsigned int dumpline; +#endif + +#if GC_BUFFERED_OUTPUT + int start; + int index; + int count; + unsigned char *buffer; +#endif +}; + +static struct buffout g_outputbuffer = { + .enable = GC_DUMP_ENABLE +}; + + +/******************************************************************************* + * Globals. + */ + +static unsigned int g_initdone; +static GCDEFINE_LOCK(g_lockmutex); +static struct list_head gc_filterlist = LIST_HEAD_INIT(gc_filterlist); + + +/******************************************************************************* + * Item size functions. + */ + +#if GC_BUFFERED_OUTPUT +static int get_item_size_terminator(struct itemhead *item) +{ + return sizeof(struct itemhead); +} + +static int get_item_size_string(struct itemhead *item) +{ + struct itemstring *itemstring = (struct itemstring *) item; + unsigned int vlen = *((unsigned char **) &itemstring->messagedata) + - ((unsigned char *) itemstring); + return vlen + itemstring->datasize; +} + +static int get_item_size_buffer(struct itemhead *item) +{ + struct itembuffer *itembuffer = (struct itembuffer *) item; + return sizeof(struct itembuffer) + itembuffer->datasize; +} + +#if GC_ENABLE_OVERFLOW +typedef int (*getitemsize) (struct itemhead *item); + +static getitemsize g_itemsize[] = { + get_item_size_terminator, + get_item_size_string, + get_item_size_buffer +}; +#endif +#endif + + +/******************************************************************************* + * Printing functions. + */ + +#define GC_PRINTK(s, fmt, ...) \ + printf(fmt, ##__VA_ARGS__); \ + +#if GC_DEBUG_SELF +# define GC_DEBUGMSG(fmt, ...) \ + GC_PRINTK(NULL, "[%s:%d] " fmt, __func__, __LINE__, \ + ##__VA_ARGS__) +#else +# define GC_DEBUGMSG(...) {} +#endif + +static struct threadinfo *get_threadinfo(struct buffout *buffout) +{ +#if GC_THREAD_COUNT > 1 + struct threadinfo *threadinfo; + unsigned int i, count; + pid_t pid; + + /* Get current pid. */ + pid = gettid(); + + /* Try to locate thread record. */ + count = buffout->threadcount + 1; + for (i = 1; i < count; i += 1) + if (buffout->threadinfo[i].pid == pid) + return &buffout->threadinfo[i]; + + /* Not found, still have room? */ + if (buffout->threadcount < GC_THREAD_COUNT) { + threadinfo = &buffout->threadinfo[count]; + threadinfo->pid = pid; + threadinfo->msgindent = 0; + threadinfo->threadindent = buffout->threadcount + * GC_THREAD_INDENT; + buffout->threadcount += 1; + return threadinfo; + } + + /* Too many threads, use the common entry. */ + GC_PRINTK(NULL, "%s(%d) [ERROR] reached the maximum thread number.\n", + __func__, __LINE__); + threadinfo = buffout->threadinfo; + threadinfo->pid = pid; + return threadinfo; +#else + struct threadinfo *threadinfo; + threadinfo = buffout->threadinfo; + +#if GC_SHOW_PID + threadinfo->pid = pid; +#else + threadinfo->pid = 0; +#endif + + return threadinfo; +#endif +} + +static int gc_get_indent(int indent, char *buffer, int buffersize) +{ + static const int MAX_INDENT = 80; + int len, _indent; + + _indent = indent % MAX_INDENT; + if (_indent > buffersize) + _indent = buffersize - 1; + + for (len = 0; len < _indent; len += 1) + buffer[len] = ' '; + + buffer[len] = '\0'; + return len; +} + +static void gc_print_string(struct seq_file *s, struct itemstring *str) +{ + int len = 0; + char buffer[GC_MAXSTR_LENGTH]; + +#if GC_SHOW_DUMP_LINE + len += snprintf(buffer + len, sizeof(buffer) - len - GC_EOL_RESERVE, + GC_DUMPLINE_FORMAT, str->dumpline); +#endif + +#if GC_SHOW_PID + len += snprintf(buffer + len, sizeof(buffer) - len - GC_EOL_RESERVE, + GC_PID_FORMAT, str->pid); +#endif + + /* Append the indent string. */ + len += gc_get_indent(str->indent, buffer + len, + sizeof(buffer) - len - GC_EOL_RESERVE); + + /* Format the string. */ + len += vsnprintf(buffer + len, sizeof(buffer) - len - GC_EOL_RESERVE, + str->message, str->messagedata); + + /* Add end-of-line if missing. */ + if (buffer[len - 1] != '\n') + buffer[len++] = '\n'; + buffer[len] = '\0'; + + /* Print the string. */ + GC_PRINTK(s, "%s", buffer); +} + +static void gc_print_generic(struct seq_file *s, struct itembuffer *item, + unsigned char *data) +{ + char buffer[GC_MAXSTR_LENGTH]; + unsigned int i, indent, len; + + /* Append the indent string. */ + indent = gc_get_indent(item->indent, buffer, sizeof(buffer)); + + /* Print the title. */ + GC_PRINTK(s, "%sBUFFER @ 0x%08X\n", + buffer, item->gpuaddr); + + /* Print the buffer. */ + for (i = 0, len = indent; i < item->datasize; i += 4) { + if ((i % GC_GENERIC_DATA_COUNT) == 0) { + if (i != 0) { + /* Print the string. */ + GC_PRINTK(s, "%s\n", buffer); + + /* Reset the line. */ + len = indent; + } + + len += snprintf(buffer + len, sizeof(buffer) - len, + "0x%08X: ", item->gpuaddr + i); + } + + /* Append the data value. */ + len += snprintf(buffer + len, sizeof(buffer) - len, + " 0x%08X", *(unsigned int *) (data + i)); + } + + /* Print the last partial string. */ + if ((i % GC_SURFACE_DATA_COUNT) != 0) + GC_PRINTK(s, "%s\n", buffer); +} + +static char *gc_module_name(unsigned int index) +{ + switch (index) { + case GCREG_COMMAND_STALL_STALL_SOURCE_FRONT_END: + return "FE"; + + case GCREG_COMMAND_STALL_STALL_SOURCE_PIXEL_ENGINE: + return "PE"; + + case GCREG_COMMAND_STALL_STALL_SOURCE_DRAWING_ENGINE: + return "DE"; + + default: + return "*INVALID*"; + } +} + +static void gc_print_command(struct seq_file *s, struct itembuffer *item, + unsigned char *data) +{ + char buffer[GC_MAXSTR_LENGTH]; + unsigned int *data32; + unsigned int i, j, datacount; + unsigned int command, count, addr; + unsigned int delay, src, dst; + unsigned int x1, y1, x2, y2; + + /* Append the indent string. */ + gc_get_indent(item->indent, buffer, sizeof(buffer)); + + /* Print the title. */ + GC_PRINTK(s, "%sCOMMAND BUFFER @ 0x%08X\n", buffer, item->gpuaddr); + GC_PRINTK(s, "%s size = %d\n", buffer, item->datasize); + + datacount = (item->datasize + 3) / 4; + data32 = (unsigned int *) data; + for (i = 0; i < datacount;) { + command = (data32[i] >> 27) & 0x1F; + + switch (command) { + case GCREG_COMMAND_OPCODE_LOAD_STATE: + count = (data32[i] >> 16) & 0x3F; + addr = data32[i] & 0xFFFF; + GC_PRINTK(s, "%s 0x%08X: 0x%08X STATE(0x%04X, %d)\n", + buffer, item->gpuaddr + (i << 2), + data32[i], addr, count); + i += 1; + + count |= 1; + for (j = 0; j < count; i += 1, j += 1) + GC_PRINTK(s, "%s%14c0x%08X\n", + buffer, ' ', data32[i]); + break; + + case GCREG_COMMAND_OPCODE_END: + GC_PRINTK(s, "%s 0x%08X: 0x%08X END()\n", + buffer, item->gpuaddr + (i << 2), + data32[i]); + i += 1; + + GC_PRINTK(s, "%s%14c0x%08X\n", + buffer, ' ', data32[i]); + i += 1; + break; + + case GCREG_COMMAND_OPCODE_NOP: + GC_PRINTK(s, "%s 0x%08X: 0x%08X NOP()\n", + buffer, item->gpuaddr + (i << 2), + data32[i]); + i += 1; + + GC_PRINTK(s, "%s" "%14c0x%08X\n", + buffer, ' ', data32[i]); + i += 1; + break; + + case GCREG_COMMAND_OPCODE_STARTDE: + count = (data32[i] >> 8) & 0xFF; + GC_PRINTK(s, "%s 0x%08X: 0x%08X STARTDE(%d)\n", + buffer, item->gpuaddr + (i << 2), + data32[i], count); + i += 1; + + GC_PRINTK(s, "%s" "%14c0x%08X\n", + buffer, ' ', data32[i]); + i += 1; + + for (j = 0; j < count; j += 1) { + x1 = data32[i] & 0xFFFF; + y1 = (data32[i] >> 16) & 0xFFFF; + GC_PRINTK(s, "%s%14c0x%08X LT(%d,%d)\n", + buffer, ' ', data32[i], x1, y1); + i += 1; + + x2 = data32[i] & 0xFFFF; + y2 = (data32[i] >> 16) & 0xFFFF; + GC_PRINTK(s, "%s%14c0x%08X RB(%d,%d)\n", + buffer, ' ', data32[i], x2, y2); + i += 1; + } + break; + + case GCREG_COMMAND_OPCODE_WAIT: + delay = data32[i] & 0xFFFF; + GC_PRINTK(s, "%s 0x%08X: 0x%08X WAIT(%d)\n", + buffer, item->gpuaddr + (i << 2), + data32[i], delay); + i += 1; + + GC_PRINTK(s, "%s%14c0x%08X\n", buffer, ' ', data32[i]); + i += 1; + break; + + case GCREG_COMMAND_OPCODE_LINK: + count = data32[i] & 0xFFFF; + addr = data32[i + 1]; + GC_PRINTK(s, "%s 0x%08X: 0x%08X " + "LINK(0x%08X-0x%08X, %d)\n", + buffer, item->gpuaddr + (i << 2), + data32[i], addr, addr + count * 8, + count); + i += 1; + + GC_PRINTK(s, "%s%14c0x%08X\n", buffer, ' ', data32[i]); + i += 1; + break; + + case GCREG_COMMAND_OPCODE_STALL: + src = data32[i + 1] & 0x1F; + dst = (data32[i + 1] >> 8) & 0x1F; + + GC_PRINTK(s, "%s 0x%08X: 0x%08X STALL(%s-%s)\n", + buffer, item->gpuaddr + (i << 2), + data32[i], + gc_module_name(src), + gc_module_name(dst)); + i += 1; + + GC_PRINTK(s, "%s" "%14c0x%08X\n", + buffer, ' ', data32[i]); + i += 1; + break; + + default: + GC_PRINTK(s, "%s 0x%08X: 0x%08X UNKNOWN COMMAND\n", + buffer, item->gpuaddr + (i << 2), + data32[i]); + i += 2; + } + } +} + +static void gc_flush_line(struct seq_file *s, char *buffer, + unsigned int indent, unsigned int *len, + unsigned int count, unsigned char checksum) +{ + unsigned int _len; + char countstr[10]; + + /* Correct data count. */ + count %= GC_SURFACE_DATA_COUNT; + if (count == 0) + count = GC_SURFACE_DATA_COUNT; + + snprintf(countstr, sizeof(countstr), "%02X", count); + buffer[indent + 1] = countstr[0]; + buffer[indent + 2] = countstr[1]; + + /* Append the checksum. */ + _len = *len; + _len += snprintf(buffer + _len, sizeof(buffer) - _len, + "%02X", checksum); + + /* Print the string. */ + GC_PRINTK(s, "%s\n", buffer); + + /* Reset the length. */ + *len = indent; +} + +static void gc_print_surface(struct seq_file *s, struct itembuffer *itembuffer, + unsigned char *data) +{ + char buffer[GC_MAXSTR_LENGTH]; + unsigned int i, indent, len; + unsigned int prevupper32 = ~0U; + unsigned int currupper32; + unsigned int offset, address; + unsigned int width, height; + + /* Append the indent string. */ + indent = gc_get_indent(itembuffer->indent, buffer, sizeof(buffer)); + + /* Print the title. */ + GC_PRINTK(s, "%sIMAGE SURFACE @ 0x%08X\n", + buffer, itembuffer->gpuaddr); + + GC_PRINTK(s, "%s surface size = %dx%d\n", + buffer, itembuffer->surfwidth, itembuffer->surfheight); + + GC_PRINTK(s, "%s surface colordepth = %d\n", + buffer, itembuffer->surfbpp); + + GC_PRINTK(s, "%s dumping rectangle = (%d,%d)-(%d,%d)\n", + buffer, itembuffer->x1, itembuffer->y1, + itembuffer->x2, itembuffer->y2); + + /* Add TGA header. */ + width = itembuffer->x2 - itembuffer->x1; + height = itembuffer->y2 - itembuffer->y1; + GC_PRINTK(s, ":12000000000002000000000000000000" + "%02X%02X%02X%02X%02X2000\n", + (width & 0xFF), ((width >> 8) & 0xFF), + (height & 0xFF), ((height >> 8) & 0xFF), + itembuffer->surfbpp * 8); + + /* TGA skip header. */ + offset = 18; + + /* Print the buffer. */ + for (i = 0, len = indent; i < itembuffer->datasize; i += 1) { + /* Determine the current address. */ + address = offset + i; + + /* Determine the current higher 16 bits of the address. */ + currupper32 = address >> 16; + + /* Did it change? */ + if (currupper32 != prevupper32) { + /* Print the previous data if any. */ + if ((i % GC_SURFACE_DATA_COUNT) != 0) + gc_flush_line(s, buffer, indent, &len, i, 0); + + /* Set new upper address. */ + prevupper32 = currupper32; + GC_PRINTK(s, ":02000004%04X00\n", prevupper32); + + /* Add the line prefix. */ + len += snprintf(buffer + len, + sizeof(buffer) - len - 2, + ":xx%04X00", address & 0xFFFF); + } else if ((i % GC_SURFACE_DATA_COUNT) == 0) { + len += snprintf(buffer + len, + sizeof(buffer) - len - 2, + ":xx%04X00", address & 0xFFFF); + } + + /* Append the data value. */ + len += snprintf(buffer + len, + sizeof(buffer) - len - 2, + "%02X", data[i]); + + /* End of line? */ + if (((i + 1) % GC_SURFACE_DATA_COUNT) == 0) + gc_flush_line(s, buffer, indent, &len, i + 1, 0); + } + + /* Print the last partial string. */ + if ((i % GC_SURFACE_DATA_COUNT) != 0) + gc_flush_line(s, buffer, indent, &len, i, 0); + + /* End of dump. */ + GC_PRINTK(s, ":00000001FF\n"); +} + +typedef void (*printbuffer) (struct seq_file *s, struct itembuffer *itembuffer, + unsigned char *data); + +static printbuffer g_printbuffer[] = { + gc_print_generic, + gc_print_command, + gc_print_surface +}; + +static void gc_print_buffer(struct seq_file *s, struct itembuffer *itembuffer, + unsigned char *data) +{ + if (((int) itembuffer->buffertype < 0) || + (itembuffer->buffertype >= countof(g_printbuffer))) { + GC_PRINTK(s, "BUFFER ENTRY 0x%08X\n", + (unsigned int) itembuffer); + GC_PRINTK(s, "INVALID BUFFER TYPE %d\n", + itembuffer->buffertype); + } else { + g_printbuffer[itembuffer->buffertype](s, itembuffer, data); + } +} + + +/******************************************************************************* + * Print function wrappers. + */ + +#if GC_BUFFERED_OUTPUT +static unsigned int gc_print_none(struct seq_file *s, struct buffout *buffout, + struct itemhead *item) +{ + /* Return the size of the node. */ + return get_item_size_terminator(item); +} + +static unsigned int gc_print_string_wrapper(struct seq_file *s, + struct buffout *buffout, + struct itemhead *item) +{ + /* Print the message. */ + gc_print_string(s, (struct itemstring *) item); + + /* Return the size of the node. */ + return get_item_size_string(item); +} + +static unsigned int gc_print_buffer_wrapper(struct seq_file *s, + struct buffout *buffout, + struct itemhead *item) +{ + unsigned char *data; + struct itembuffer *itembuffer = (struct itembuffer *) item; + + /* Compute data address. */ + data = (unsigned char *) (itembuffer + 1); + + /* Print the message. */ + gc_print_buffer(s, (struct itembuffer *) item, data); + + /* Return the size of the node. */ + return get_item_size_buffer(item); +} + +typedef unsigned int (*printitem) (struct seq_file *s, struct buffout *buffout, + struct itemhead *item); + +static printitem g_printarray[] = { + gc_print_none, + gc_print_string_wrapper, + gc_print_buffer_wrapper +}; +#endif + + +/******************************************************************************* + * Private functions. + */ + +unsigned int gc_get_bpp(unsigned int format) +{ + unsigned int bpp; + + switch (format) { + case GCREG_DE_FORMAT_INDEX8: + case GCREG_DE_FORMAT_A8: + bpp = 1; + break; + + case GCREG_DE_FORMAT_X4R4G4B4: + case GCREG_DE_FORMAT_A4R4G4B4: + case GCREG_DE_FORMAT_X1R5G5B5: + case GCREG_DE_FORMAT_A1R5G5B5: + case GCREG_DE_FORMAT_R5G6B5: + case GCREG_DE_FORMAT_YUY2: + case GCREG_DE_FORMAT_UYVY: + case GCREG_DE_FORMAT_RG16: + bpp = 2; + break; + + case GCREG_DE_FORMAT_X8R8G8B8: + case GCREG_DE_FORMAT_A8R8G8B8: + bpp = 4; + break; + + default: + bpp = 0; + } + + return bpp; +} + +#if GC_BUFFERED_OUTPUT +static void gc_buffer_flush(struct seq_file *s, struct buffout *buffout) +{ + int i, skip; + struct itemhead *item; + + if (buffout->count == 0) + return; + + GC_PRINTK(s, "****************************************" + "****************************************\n"); + GC_PRINTK(s, "FLUSHING DEBUG OUTPUT BUFFER (%d elements).\n", + buffout->count); + +#if !GC_ENABLE_OVERFLOW + { + int occupied = (100 * (buffout->index - buffout->start)) + / GC_DUMP_BUFFER_SIZE; + if (buffout->start != 0) + GC_PRINTK(s, " START = %d\n", buffout->start); + GC_PRINTK(s, " INDEX = %d\n", buffout->index); + GC_PRINTK(s, " BUFFER USE = %d%%\n", occupied); + } +#endif + + GC_PRINTK(s, "****************************************" + "****************************************\n"); + + item = (struct itemhead *) &buffout->buffer[buffout->start]; + GC_DEBUGMSG("start=%d.\n", buffout->start); + + for (i = 0; i < buffout->count; i += 1) { + GC_DEBUGMSG("printing item %d of type %d @ 0x%08X.\n", + i, item->type, (unsigned int) item); + skip = (*g_printarray[item->type]) (s, buffout, item); + + item = (struct itemhead *) ((unsigned char *) item + skip); + GC_DEBUGMSG("next item @ 0x%08X.\n", (unsigned int) item); + + if (item->type == GC_BUFITEM_NONE) { + GC_DEBUGMSG("reached the end of buffer.\n"); + item = (struct itemhead *) buffout->buffer; + } + } + + GC_DEBUGMSG("resetting the buffer.\n"); + buffout->start = 0; + buffout->index = 0; + buffout->count = 0; +} + +static struct itemhead *gc_allocate_item(struct buffout *buffout, int size) +{ + struct itemhead *item, *next; + int endofbuffer = (buffout->index + size + >= GC_DUMP_BUFFER_SIZE - sizeof(struct itemhead)); + +#if GC_ENABLE_OVERFLOW + int skip, bufferoverflow; + + bufferoverflow = (buffout->index < buffout->start) && + (buffout->index + size >= buffout->start); + + if (endofbuffer || bufferoverflow) { + if (endofbuffer) { + if (buffout->index < buffout->start) { + item = (struct itemhead *) + &buffout->buffer[buffout->start]; + + while (item->type != GC_BUFITEM_NONE) { + skip = (*g_itemsize[item->type]) (item); + + buffout->start += skip; + buffout->count -= 1; + + item->type = GC_BUFITEM_NONE; + item = (struct itemhead *) + ((unsigned char *) item + skip); + } + + buffout->start = 0; + } + + buffout->index = 0; + } + + item = (struct itemhead *) &buffout->buffer[buffout->start]; + + while (buffout->start - buffout->index <= size) { + skip = (*g_itemsize[item->type]) (item); + + buffout->start += skip; + buffout->count -= 1; + + item->type = GC_BUFITEM_NONE; + item = (struct itemhead *) + ((unsigned char *) item + skip); + + if (item->type == GC_BUFITEM_NONE) { + buffout->start = 0; + break; + } + } + } +#else + if (endofbuffer) { + GC_PRINTK(NULL, "message buffer full; " + "forcing message flush.\n\n"); + gc_buffer_flush(NULL, buffout); + } +#endif + + item = (struct itemhead *) &buffout->buffer[buffout->index]; + + buffout->index += size; + buffout->count += 1; + + next = (struct itemhead *) ((unsigned char *) item + size); + next->type = GC_BUFITEM_NONE; + + return item; +} + +static void gc_append_string(struct buffout *buffout, + struct itemstring *itemstring) +{ + unsigned char *messagedata; + struct itemstring *item; + unsigned int alignment; + int size, freesize; + int allocsize; + + /* Determine the maximum item size. */ + allocsize = sizeof(struct itemstring) + itemstring->datasize + + GC_VARARG_ALIGNMENT; + + /* Allocate the item. */ + item = (struct itemstring *) gc_allocate_item(buffout, allocsize); + GC_DEBUGMSG("allocated %d bytes @ 0x%08X.\n", + allocsize, (unsigned int) item); + + /* Compute the initial message data pointer. */ + messagedata = (unsigned char *) (item + 1); + + /* Align the data pointer as necessary. */ + alignment = GC_PTRALIGNMENT(messagedata, GC_VARARG_ALIGNMENT); + messagedata += alignment; + GC_DEBUGMSG("messagedata @ 0x%08X.\n", (unsigned int) messagedata); + + /* Set item data. */ + item->itemtype = GC_BUFITEM_STRING; + item->indent = itemstring->indent; + item->message = itemstring->message; + item->messagedata = *(va_list *) &messagedata; + item->datasize = itemstring->datasize; + +#if GC_SHOW_PID + item->pid = itemstring->pid; +#endif + +#if GC_SHOW_DUMP_LINE + item->dumpline = itemstring->dumpline; +#endif + + /* Copy argument value. */ + if (itemstring->datasize != 0) { + GC_DEBUGMSG("copying %d bytes of messagedata.\n", + itemstring->datasize); + memcpy(messagedata, + *(unsigned char **) &itemstring->messagedata, + itemstring->datasize); + } + + /* Compute the actual node size. */ + size = sizeof(struct itemstring) + itemstring->datasize + alignment; + GC_DEBUGMSG("adjusted item size=%d.\n", size); + + /* Free extra memory if any. */ + freesize = allocsize - size; + GC_DEBUGMSG("freesize=%d.\n", freesize); + + if (freesize != 0) { + struct itemhead *next; + buffout->index -= freesize; + next = (struct itemhead *) ((unsigned char *) item + size); + next->type = GC_BUFITEM_NONE; + } + +#if GC_BUFFERED_OUTPUT && GC_FLUSH_COUNT + if (buffout->count >= GC_FLUSH_COUNT) { + GC_PRINTK(NULL, "reached %d message count; " + "forcing message flush.\n\n", buffout->count); + gc_buffer_flush(NULL, buffout); + } +#endif +} + +static void gc_append_buffer(struct buffout *buffout, + struct itembuffer *itembuffer, + unsigned int *data) +{ + struct itembuffer *item; + int allocsize; + + /* Determine the item size. */ + allocsize = sizeof(struct itembuffer) + itembuffer->datasize; + + /* Allocate the item. */ + item = (struct itembuffer *) gc_allocate_item(buffout, allocsize); + GC_DEBUGMSG("allocated %d bytes @ 0x%08X.\n", + allocsize, (unsigned int) item); + + /* Set item data. */ + *item = *itembuffer; + + /* Copy data. */ + memcpy(item + 1, data, itembuffer->datasize); + +#if GC_BUFFERED_OUTPUT && GC_FLUSH_COUNT + if (buffout->count >= GC_FLUSH_COUNT) { + GC_PRINTK(NULL, "reached %d message count; " + "forcing message flush.\n\n", buffout->count); + gc_buffer_flush(NULL, buffout); + } +#endif +} +#endif + +static void gc_print(struct buffout *buffout, unsigned int argsize, + const char *message, va_list args) +{ + struct itemstring itemstring; + struct threadinfo *threadinfo; + + GCLOCK(&g_lockmutex); + + /* Locate thead entry. */ + threadinfo = get_threadinfo(buffout); + + /* Form the indent string. */ + if (strncmp(message, "--", 2) == 0) + threadinfo->msgindent -= 2; + + /* Fill in the sructure. */ + itemstring.itemtype = GC_BUFITEM_STRING; + itemstring.indent = threadinfo->msgindent + + threadinfo->threadindent; + itemstring.message = message; + itemstring.messagedata = args; + itemstring.datasize = argsize; + +#if GC_SHOW_PID + itemstring.pid = threadinfo->pid; +#endif + +#if GC_SHOW_DUMP_LINE + itemstring.dumpline = ++buffout->dumpline; +#endif + + /* Print the message. */ +#if GC_BUFFERED_OUTPUT + gc_append_string(buffout, &itemstring); +#else + gc_print_string(NULL, &itemstring); +#endif + + /* Check increasing indent. */ + if (strncmp(message, "++", 2) == 0) + threadinfo->msgindent += 2; + + GCUNLOCK(&g_lockmutex); +} + + +/******************************************************************************* + * Dumping functions. + */ + +void gc_dump_string(struct gcdbgfilter *filter, unsigned int zone, + const char *message, ...) +{ + va_list args; + unsigned int i, count, argsize; + + if (!g_outputbuffer.enable) + return; + + if (message == NULL) + GC_DEBUGMSG("message is NULL.\n"); + + if (GC_VERIFY_ENABLE(filter, zone)) { + for (i = 0, count = 0; message[i]; i += 1) + if (message[i] == '%') + count += 1; + + argsize = count * sizeof(unsigned int); + GC_DEBUGMSG("argsize=%d.\n", argsize); + + va_start(args, message); + gc_print(&g_outputbuffer, argsize, message, args); + va_end(args); + } +} +EXPORT_SYMBOL(gc_dump_string); + +void gc_dump_string_sized(struct gcdbgfilter *filter, unsigned int zone, + unsigned int argsize, const char *message, ...) +{ + va_list args; + + if (!g_outputbuffer.enable) + return; + + if (GC_VERIFY_ENABLE(filter, zone)) { + va_start(args, message); + gc_print(&g_outputbuffer, argsize, message, args); + va_end(args); + } +} +EXPORT_SYMBOL(gc_dump_string_sized); + +void gc_dump_cmd_buffer(struct gcdbgfilter *filter, unsigned int zone, + void *ptr, unsigned int gpuaddr, unsigned int datasize) +{ + struct itembuffer itembuffer; + struct threadinfo *threadinfo; + + if (!g_outputbuffer.enable) + return; + + if (GC_VERIFY_ENABLE(filter, zone)) { + GCLOCK(&g_lockmutex); + + /* Locate thead entry. */ + threadinfo = get_threadinfo(&g_outputbuffer); + + /* Fill in the sructure. */ + itembuffer.itemtype = GC_BUFITEM_BUFFER; + itembuffer.buffertype = GC_BUFTYPE_COMMAND; + itembuffer.indent = threadinfo->msgindent + + threadinfo->threadindent; + itembuffer.datasize = datasize; + itembuffer.gpuaddr = gpuaddr; + + /* Print the message. */ +#if GC_BUFFERED_OUTPUT + gc_append_buffer(NULL, &g_outputbuffer, &itembuffer, + (unsigned int *) ptr); +#else + gc_print_buffer(NULL, &itembuffer, + (unsigned char *) ptr); +#endif + + GCUNLOCK(&g_lockmutex); + } +} +EXPORT_SYMBOL(gc_dump_cmd_buffer); + +void gc_dump_buffer(struct gcdbgfilter *filter, unsigned int zone, + void *ptr, unsigned int gpuaddr, + unsigned int datasize) +{ + struct itembuffer itembuffer; + struct threadinfo *threadinfo; + + if (!g_outputbuffer.enable) + return; + + if (GC_VERIFY_ENABLE(filter, zone)) { + GCLOCK(&g_lockmutex); + + /* Locate thead entry. */ + threadinfo = get_threadinfo(&g_outputbuffer); + + /* Fill in the sructure. */ + itembuffer.itemtype = GC_BUFITEM_BUFFER; + itembuffer.buffertype = GC_BUFTYPE_GENERIC; + itembuffer.indent = threadinfo->msgindent + + threadinfo->threadindent; + itembuffer.datasize = datasize; + itembuffer.gpuaddr = gpuaddr; + + /* Print the message. */ +#if GC_BUFFERED_OUTPUT + gc_append_buffer(NULL, &g_outputbuffer, &itembuffer, + (unsigned int *) ptr); +#else + gc_print_buffer(NULL, &itembuffer, + (unsigned char *) ptr); +#endif + + GCUNLOCK(&g_lockmutex); + } +} +EXPORT_SYMBOL(gc_dump_buffer); + + +/******************************************************************************* + * Dumping control functions. + */ + +void gc_dump_enable(void) +{ + GCLOCK(&g_lockmutex); + + g_outputbuffer.enable = 1; + GC_PRINTK(NULL, "gcx dumping is enabled.\n"); + + GCUNLOCK(&g_lockmutex); +} +EXPORT_SYMBOL(gc_dump_enable); + +void gc_dump_disable(void) +{ + GCLOCK(&g_lockmutex); + + g_outputbuffer.enable = 0; + GC_PRINTK(NULL, "gcx dumping is disabled.\n"); + + GCUNLOCK(&g_lockmutex); +} +EXPORT_SYMBOL(gc_dump_disable); + +void gc_dump_show_enabled(struct seq_file *s) +{ + struct list_head *filterhead; + struct gcdbgfilter *filter; + unsigned int i, zone; + + GCLOCK(&g_lockmutex); + + GC_PRINTK(s, "gcx logging is %s\n", g_outputbuffer.enable + ? "enabled" : "disabled"); + + list_for_each(filterhead, &gc_filterlist) { + filter = list_entry(filterhead, struct gcdbgfilter, + link); + + GC_PRINTK(s, "gcx filter '%s':\n", filter->filtername); + GC_PRINTK(s, " zone mask = 0x%08X%s\n", filter->zone, + (filter->zone == 0) + ? " (all disabled)" : ""); + + for (i = 0; filter->zonename[i] != NULL; i++) { + zone = 1 << i; + GC_PRINTK(s, " 0x%08X: %10s%s\n", + zone, filter->zonename[i], + ((filter->zone & zone) != 0) + ? " (enabled)" : ""); + } + } + + GCUNLOCK(&g_lockmutex); +} +EXPORT_SYMBOL(gc_dump_show_enabled); + +void gc_dump_filter_enable(const char *filtername, int zone) +{ + struct list_head *filterhead; + struct gcdbgfilter *filter; + unsigned int filterfound = 0; + unsigned int havesetzones = 0; + + GCLOCK(&g_lockmutex); + + GC_PRINTK(NULL, "modifying zone mask for filter %s:\n", filtername); + + list_for_each(filterhead, &gc_filterlist) { + filter = list_entry(filterhead, struct gcdbgfilter, + link); + + if (strcasecmp(filtername, filter->filtername) == 0) { + GC_PRINTK(NULL, " 0x%08X --> 0x%08X\n", + filter->zone, zone); + filter->zone = zone; + filterfound = 1; + } + + if (filter->zone != 0) + havesetzones = 1; + } + + GCUNLOCK(&g_lockmutex); + + if (!filterfound) + GC_PRINTK(NULL, " couldn't find filter %s.\n", filtername); + + if (havesetzones && !g_outputbuffer.enable) + gc_dump_enable(); + else if (!havesetzones && g_outputbuffer.enable) + gc_dump_disable(); +} +EXPORT_SYMBOL(gc_dump_filter_enable); + +void gc_dbg_add_client(struct gcdbgfilter *filter) +{ + list_add(&filter->link, &gc_filterlist); +} +EXPORT_SYMBOL(gc_dbg_add_client); + +void gc_dump_flush(struct seq_file *s) +{ +#if GC_BUFFERED_OUTPUT + GCLOCK(&g_lockmutex); + + /* + * Not dumping through debugfs for now because we have + * too much data and it'd require us to implement the + * seq_file iterator interface. + */ + gc_buffer_flush(NULL, &g_outputbuffer); + + GCUNLOCK(&g_lockmutex); +#endif +} +EXPORT_SYMBOL(gc_dump_flush); + +void gc_dump_reset(void) +{ +#if GC_BUFFERED_OUTPUT + GCLOCK(&g_lockmutex); + + g_outputbuffer.start = 0; + g_outputbuffer.index = 0; + g_outputbuffer.count = 0; + + GC_PRINTK(NULL, "gcx logging buffer is reset.\n"); + + GCUNLOCK(&g_lockmutex); +#endif +} +EXPORT_SYMBOL(gc_dump_reset); + + +/******************************************************************************* + * Command buffer parser. + */ + +int gc_parse_command_buffer(unsigned int *buffer, unsigned int size, + struct gccommandinfo *info) +{ + int res; + unsigned int i, j, itemcount, index, oldsrc; + unsigned int command, count, addr; + + memset(info, 0, sizeof(struct gccommandinfo)); + info->command = ~0U; + + oldsrc = 0; + + itemcount = (size + 3) / 4; + for (i = 0; i < itemcount;) { + command = (buffer[i] >> 27) & 0x1F; + + switch (command) { + case GCREG_COMMAND_OPCODE_LOAD_STATE: + count = (buffer[i] >> 16) & 0x3F; + addr = buffer[i] & 0xFFFF; + i += 1; + + for (j = 0; j < count; j += 1) { + switch (addr) { + case gcregDestAddressRegAddrs: + info->dst.surf.address = buffer[i]; + break; + + case gcregDestStrideRegAddrs: + info->dst.surf.stride = buffer[i]; + break; + + case gcregDestRotationConfigRegAddrs: + info->dst.surf.width + = buffer[i] & 0xFFFF; + break; + + case gcregDstRotationHeightRegAddrs: + info->dst.surf.height + = buffer[i] & 0xFFFF; + break; + + case gcregDestConfigRegAddrs: + info->command + = (buffer[i] >> 12) & 0xF; + + info->dst.surf.swizzle + = (buffer[i] >> 16) & 0x3; + + info->dst.surf.format + = buffer[i] & 0x1F; + + info->dst.surf.bpp = gc_get_bpp( + info->dst.surf.format); + break; + + case gcregSrcAddressRegAddrs: + info->src[0].surf.address = buffer[i]; + oldsrc = 1; + break; + + case gcregSrcStrideRegAddrs: + info->src[0].surf.stride = buffer[i]; + break; + + case gcregSrcRotationConfigRegAddrs: + info->src[0].surf.width + = buffer[i] & 0xFFFF; + break; + + case gcregSrcRotationHeightRegAddrs: + info->src[0].surf.height + = buffer[i] & 0xFFFF; + break; + + case gcregSrcConfigRegAddrs: + info->src[0].surf.swizzle + = (buffer[i] >> 20) & 0x3; + + info->src[0].surf.format + = (buffer[i] >> 24) & 0x1F; + + info->src[0].surf.bpp = gc_get_bpp( + info->src[0].surf.format); + break; + + case gcregSrcOriginRegAddrs: + info->src[0].rect.l + = buffer[i] & 0xFFFF; + + info->src[0].rect.t + = (buffer[i] >> 16) & 0xFFFF; + break; + + case gcregSrcSizeRegAddrs: + info->src[0].rect.r + = buffer[i] & 0xFFFF; + + info->src[0].rect.b + = (buffer[i] >> 16) & 0xFFFF; + break; + + case gcregBlock4SrcAddressRegAddrs: + case gcregBlock4SrcAddressRegAddrs + 1: + case gcregBlock4SrcAddressRegAddrs + 2: + case gcregBlock4SrcAddressRegAddrs + 3: + index = addr & 3; + info->src[index].surf.address + = buffer[i]; + break; + + case gcregBlock4SrcStrideRegAddrs: + case gcregBlock4SrcStrideRegAddrs + 1: + case gcregBlock4SrcStrideRegAddrs + 2: + case gcregBlock4SrcStrideRegAddrs + 3: + index = addr & 3; + info->src[index].surf.stride + = buffer[i]; + break; + + case gcregBlock4SrcRotationConfigRegAddrs: + case gcregBlock4SrcRotationConfigRegAddrs + 1: + case gcregBlock4SrcRotationConfigRegAddrs + 2: + case gcregBlock4SrcRotationConfigRegAddrs + 3: + index = addr & 3; + info->src[index].surf.width + = buffer[i] & 0xFFFF; + break; + + case gcregBlock4SrcRotationHeightRegAddrs: + case gcregBlock4SrcRotationHeightRegAddrs + 1: + case gcregBlock4SrcRotationHeightRegAddrs + 2: + case gcregBlock4SrcRotationHeightRegAddrs + 3: + index = addr & 3; + info->src[0].surf.height + = buffer[i] & 0xFFFF; + break; + + case gcregBlock4SrcConfigRegAddrs: + case gcregBlock4SrcConfigRegAddrs + 1: + case gcregBlock4SrcConfigRegAddrs + 2: + case gcregBlock4SrcConfigRegAddrs + 3: + index = addr & 3; + info->src[index].surf.swizzle + = (buffer[i] >> 20) & 0x3; + + info->src[index].surf.format + = (buffer[i] >> 24) & 0x1F; + + info->src[index].surf.bpp = gc_get_bpp( + info->src[index].surf.format); + break; + + case gcregBlock4SrcOriginRegAddrs: + case gcregBlock4SrcOriginRegAddrs + 1: + case gcregBlock4SrcOriginRegAddrs + 2: + case gcregBlock4SrcOriginRegAddrs + 3: + index = addr & 3; + info->src[index].rect.l + = buffer[i] & 0xFFFF; + + info->src[index].rect.t + = (buffer[i] >> 16) & 0xFFFF; + break; + + case gcregBlock4SrcSizeRegAddrs: + case gcregBlock4SrcSizeRegAddrs + 1: + case gcregBlock4SrcSizeRegAddrs + 2: + case gcregBlock4SrcSizeRegAddrs + 3: + index = addr & 3; + info->src[index].rect.r + = buffer[i] & 0xFFFF; + + info->src[index].rect.b + = (buffer[i] >> 16) & 0xFFFF; + break; + + case gcregDEMultiSourceRegAddrs: + info->srccount = (buffer[i] & 0x7) + 1; + break; + } + + addr += 1; + i += 1; + } + + i += ((~count) & 1); + break; + + case GCREG_COMMAND_OPCODE_END: + case GCREG_COMMAND_OPCODE_NOP: + case GCREG_COMMAND_OPCODE_WAIT: + case GCREG_COMMAND_OPCODE_LINK: + case GCREG_COMMAND_OPCODE_STALL: + i += 2; + break; + + case GCREG_COMMAND_OPCODE_STARTDE: + info->dst.rectcount = (buffer[i] >> 8) & 0xFF; + i += 2; + + for (j = 0; j < info->dst.rectcount; j += 1) { + info->dst.rect[j].l + = buffer[i] & 0xFFFF; + info->dst.rect[j].t + = (buffer[i] >> 16) & 0xFFFF; + i += 1; + + info->dst.rect[j].r + = buffer[i] & 0xFFFF; + info->dst.rect[j].b + = (buffer[i] >> 16) & 0xFFFF; + i += 1; + } + break; + + default: + res = 0; + gc_dump_string(NULL, 0, + "bad command (%d) " + "while parsing the command stream", + command); + goto exit; + } + + } + + /* Enable old source. */ + if ((info->srccount == 0) && oldsrc) + info->srccount = 1; + + /* Success. */ + res = 1; + +exit: + return res; +} +EXPORT_SYMBOL(gc_parse_command_buffer); + + +/******************************************************************************* + * Bltsville debugging. + */ + +char *gc_bvblend_name(enum bvblend blend) +{ + switch (blend) { + case BVBLEND_CLEAR: return "BVBLEND_CLEAR"; + case BVBLEND_SRC1: return "BVBLEND_SRC1"; + case BVBLEND_SRC2: return "BVBLEND_SRC2"; + case BVBLEND_SRC1OVER: return "BVBLEND_SRC1OVER"; + case BVBLEND_SRC2OVER: return "BVBLEND_SRC2OVER"; + case BVBLEND_SRC1IN: return "BVBLEND_SRC1IN"; + case BVBLEND_SRC2IN: return "BVBLEND_SRC2IN"; + case BVBLEND_SRC1OUT: return "BVBLEND_SRC1OUT"; + case BVBLEND_SRC2OUT: return "BVBLEND_SRC2OUT"; + case BVBLEND_SRC1ATOP: return "BVBLEND_SRC1ATOP"; + case BVBLEND_SRC2ATOP: return "BVBLEND_SRC2ATOP"; + case BVBLEND_XOR: return "BVBLEND_XOR"; + case BVBLEND_PLUS: return "BVBLEND_PLUS"; + case BVBLEND_NORMAL: return "BVBLEND_NORMAL"; + case BVBLEND_LIGHTEN: return "BVBLEND_LIGHTEN"; + case BVBLEND_DARKEN: return "BVBLEND_DARKEN"; + case BVBLEND_MULTIPLY: return "BVBLEND_MULTIPLY"; + case BVBLEND_AVERAGE: return "BVBLEND_AVERAGE"; + case BVBLEND_ADD: return "BVBLEND_ADD"; + case BVBLEND_SUBTRACT: return "BVBLEND_SUBTRACT"; + case BVBLEND_DIFFERENCE: return "BVBLEND_DIFFERENCE"; + case BVBLEND_NEGATE: return "BVBLEND_NEGATE"; + case BVBLEND_SCREEN: return "BVBLEND_SCREEN"; + case BVBLEND_EXCLUSION: return "BVBLEND_EXCLUSION"; + case BVBLEND_OVERLAY: return "BVBLEND_OVERLAY"; + case BVBLEND_SOFT_LIGHT: return "BVBLEND_SOFT_LIGHT"; + case BVBLEND_HARD_LIGHT: return "BVBLEND_HARD_LIGHT"; + case BVBLEND_COLOR_DODGE: return "BVBLEND_COLOR_DODGE"; + case BVBLEND_COLOR_BURN: return "BVBLEND_COLOR_BURN"; + case BVBLEND_LINEAR_LIGHT: return "BVBLEND_LINEAR_LIGHT"; + case BVBLEND_VIVID_LIGHT: return "BVBLEND_VIVID_LIGHT"; + case BVBLEND_PIN_LIGHT: return "BVBLEND_PIN_LIGHT"; + case BVBLEND_HARD_MIX: return "BVBLEND_HARD_MIX"; + case BVBLEND_REFLECT: return "BVBLEND_REFLECT"; + case BVBLEND_GLOW: return "BVBLEND_GLOW"; + case BVBLEND_PHOENIX: return "BVBLEND_PHOENIX"; + default: return "[UNKNOWN]"; + } +} +EXPORT_SYMBOL(gc_bvblend_name); + + +/******************************************************************************* + * Initialization/cleanup. + */ + +void gcdbg_init(void) +{ +#if GC_BUFFERED_OUTPUT + /* Allocate the debug buffer. */ + g_outputbuffer.buffer = kmalloc(GC_DUMP_BUFFER_SIZE, GFP_KERNEL); + if (g_outputbuffer.buffer == NULL) { + GC_PRINTK(NULL, "failed to allocate dump buffer.\n"); + return; + } +#endif + + g_initdone = 1; +} + +void gcdbg_exit(void) +{ +#if GC_BUFFERED_OUTPUT + if (g_outputbuffer.buffer != NULL) { + kfree(g_outputbuffer.buffer); + g_outputbuffer.buffer = NULL; + } +#endif + + g_initdone = 0; +} + +#endif /* GCDEBUG_ENABLE */ diff --git a/gcbv/mirror/include/cache-2dmanager.h b/gcbv/mirror/include/cache-2dmanager.h new file mode 100644 index 0000000..a013514 --- /dev/null +++ b/gcbv/mirror/include/cache-2dmanager.h @@ -0,0 +1,103 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef CACHE_2DMANAGER_H_ +#define CACHE_2DMANAGER_H_ + +/* The value below only applies to OMAP4 */ +#define L1CACHE_SIZE 32768 +#define L2CACHE_SIZE 1048576 + +#define L1THRESHOLD L1CACHE_SIZE +#define L2THRESHOLD L2CACHE_SIZE + +struct c2dmrgn { + char *start; /* addr of upper left of rect */ + size_t span; /* bytes to be operated on per line */ + size_t lines; /* lines to be operated on */ + long stride; /* bytes per line */ +}; + +/* + * c2dm_l1cache(count, rgns, dir) + * + * L1 Cache operations in 2D + * + * - count - number of regions + * - rgns - array of regions + * - dir - cache operation direction + * + */ +void c2dm_l1cache(int count, struct c2dmrgn rgns[], int dir); + +/* + * c2dm_l2cache(count, rgns, dir) + * + * L2 Cache operations in 2D + * + * - count - number of regions + * - rgns - array of regions + * - dir - cache operation direction + * + */ +void c2dm_l2cache(int count, struct c2dmrgn rgns[], int dir); + + +#endif /* CACHE_2DMANAGER_H_ */ diff --git a/gcbv/mirror/include/gcdbglog.h b/gcbv/mirror/include/gcdbglog.h new file mode 100644 index 0000000..23df118 --- /dev/null +++ b/gcbv/mirror/include/gcdbglog.h @@ -0,0 +1,412 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GCDBGLOG_H +#define GCDBGLOG_H + +#include "gclist.h" +#include <bltsville.h> +struct gcmmucontext; + + +/******************************************************************************* + * Debug logging switches. + */ + +/* Enables internal gccore logging backend. */ +#if !defined(GCDEBUG_ENABLE) +#define GCDEBUG_ENABLE 0 /* Enabled for development branch only. */ +#endif + +/* Enables linux builtin logging backend. */ +#if !defined(GCDEBUG_LINUXLOGS) +#define GCDEBUG_LINUXLOGS 0 +#endif + +#if GCDEBUG_ENABLE && GCDEBUG_LINUXLOGS +#error GCDEBUG_ENABLE and GCDEBUG_LINUXLOGS cannot be enabled simultaneously. +#endif + + +/******************************************************************************* + * Dumping interface macro for release mode. + */ + +#if !GCDEBUG_ENABLE && !GCDEBUG_LINUXLOGS +#define GCDBG_INIT(...) +#define GCDBG_EXIT(...) +#define GCDBG_FILTERDEF(...) +#define GCDBG_REGISTER(...) +#define GCENTER(...) +#define GCEXIT(...) +#define GCENTERARG(...) +#define GCEXITARG(...) +#define GCDBG(...) {} +#define GCERR(...) {} +#define GCDUMPSTRING(...) {} +#define GCDUMPBUFFER(...) {} +#define GCDUMPARENA(...) {} +#define GCDUMPARENAS(...) {} +#define GCGPUSTATUS(...) {} +#endif + +#if !GCDEBUG_ENABLE +#define GCDBG_REPORT_MISSING() \ + printf("gcx logging is not integrated.\n") + +#define GCDBG_SHOWENABLED(s) \ + GCDBG_REPORT_MISSING() + +#define GCDBG_ENABLEDUMP() \ + GCDBG_REPORT_MISSING() + +#define GCDBG_DISABLEDUMP() \ + GCDBG_REPORT_MISSING() + +#define GCDBG_SETFILTER(filtername, zone) \ + GCDBG_REPORT_MISSING() + +#define GCDBG_FLUSHDUMP(s) \ + GCDBG_REPORT_MISSING() + +#define GCDBG_RESETDUMP() \ + GCDBG_REPORT_MISSING() + +#endif + + +/******************************************************************************* + * Dumping macros not specific to a particular logging backend. + */ + +#if GCDEBUG_ENABLE || GCDEBUG_LINUXLOGS + +#define GC_MOD_PREFIX \ + GC_DEV_NAME ": %s(%d) " + +#define GCDUMPARENA(zone, text, arena) \ +do { \ + GCDBG(zone, text " @ 0x%08X:\n", (unsigned int) arena); \ + GCDBG(zone, " number of pages = %u\n", \ + (arena)->count); \ + GCDBG(zone, " from (absolute/mtlb/stlb) = 0x%08X / %u / %u\n", \ + (arena)->start.absolute, \ + (arena)->start.loc.mtlb, \ + (arena)->start.loc.stlb); \ + GCDBG(zone, " to (absolute/mtlb/stlb) = 0x%08X / %u / %u\n", \ + (arena)->end.absolute, \ + (arena)->end.loc.mtlb, \ + (arena)->end.loc.stlb); \ +} while (false) + +#define GCDUMPARENAS(zone, text, arenahead) \ +do { \ + GCDBG(zone, "%s:\n", text); \ + \ + if (list_empty(arenahead)) { \ + GCDBG(zone, " no arenas defined in the list.\n"); \ + } else { \ + struct list_head *entry; \ + struct gcmmuarena *arena; \ + \ + list_for_each(entry, arenahead) { \ + arena = list_entry(entry, struct gcmmuarena, link); \ + GCDUMPARENA(zone, "arena", arena); \ + } \ + } \ +} while (false) + +#endif + +#define GC_FUNC_ENTER "++" +#define GC_FUNC_EXIT "--" + + +/******************************************************************************* + * Dumping macros for internal gccore logging backend. + */ + +#if GCDEBUG_ENABLE + +#define GCDBGFILTER \ + g_gcdbgfilter + +#define GCDBG_INIT() \ + gcdbg_init() + +#define GCDBG_EXIT() \ + gcdbg_exit() + +#define GCDBG_FILTERDEF(name, initzone, ...) \ + static struct gcdbgfilter GCDBGFILTER = { \ + .link = LIST_HEAD_INIT(GCDBGFILTER.link), \ + .filtername = #name, \ + .zone = initzone, \ + .zonename = { __VA_ARGS__, NULL } \ + }; \ + \ + struct gcdbgfilter *name ## _dbgfilter(void) \ + { \ + return &GCDBGFILTER; \ + } + +#define GCDBG_REGISTER(name) \ +do { \ + struct gcdbgfilter *name ## _dbgfilter(void); \ + gc_dbg_add_client(name ## _dbgfilter()); \ +} while (0) + +#define GCDBG_SHOWENABLED(s) \ + gc_dump_show_enabled(s) + +#define GCDBG_ENABLEDUMP() \ + gc_dump_enable() + +#define GCDBG_DISABLEDUMP() \ + gc_dump_disable() + +#define GCDBG_SETFILTER(filtername, zone) \ + gc_dump_filter_enable(filtername, zone) + +#define GCDBG_FLUSHDUMP(s) \ + gc_dump_flush(s) + +#define GCDBG_RESETDUMP() \ + gc_dump_reset() + +#define GCENTER(zone) \ + gc_dump_string(&GCDBGFILTER, zone, GC_FUNC_ENTER GC_MOD_PREFIX "\n", \ + __func__, __LINE__) + +#define GCEXIT(zone) \ + gc_dump_string(&GCDBGFILTER, zone, GC_FUNC_EXIT GC_MOD_PREFIX "\n", \ + __func__, __LINE__) + +#define GCENTERARG(zone, msg, ...) \ + gc_dump_string(&GCDBGFILTER, zone, GC_FUNC_ENTER GC_MOD_PREFIX msg, \ + __func__, __LINE__, ##__VA_ARGS__) + +#define GCEXITARG(zone, msg, ...) \ + gc_dump_string(&GCDBGFILTER, zone, GC_FUNC_EXIT GC_MOD_PREFIX msg, \ + __func__, __LINE__, ##__VA_ARGS__) + +#define GCDBG(zone, msg, ...) \ + gc_dump_string(&GCDBGFILTER, zone, GC_MOD_PREFIX msg, \ + __func__, __LINE__, ##__VA_ARGS__) + +#define GCERR(msg, ...) \ + gc_dump_string(NULL, 0, GC_MOD_PREFIX "[ERROR] " msg, \ + __func__, __LINE__, ##__VA_ARGS__) + +#define GCDUMPSTRING(msg, ...) \ + gc_dump_string(NULL, 0, msg, ##__VA_ARGS__) + +#define GCDUMPBUFFER(zone, ptr, gpuaddr, datasize) \ + gc_dump_cmd_buffer(&GCDBGFILTER, zone, ptr, gpuaddr, datasize) + +#endif + + +/******************************************************************************* + * Dumping macros for linux builtin logging backend. + */ + +#if GCDEBUG_LINUXLOGS + +#define GCDBG_INIT() +#define GCDBG_EXIT() +#define GCDBG_FILTERDEF(...) +#define GCDBG_REGISTER(...) + +#define GCENTER(zone) \ + GCDBG(zone, GC_FUNC_ENTER " %s(%d)\n", __func__, __LINE__) + +#define GCEXIT(zone) \ + GCDBG(zone, GC_FUNC_EXIT " %s(%d)\n", __func__, __LINE__) + +#define GCENTERARG(zone, msg, ...) \ + GCDBG(zone, GC_FUNC_ENTER " %s(%d) " msg "\n", \ + __func__, __LINE__, ##__VA_ARGS__) + +#define GCEXITARG(zone, msg, ...) \ + GCDBG(zone, GC_FUNC_EXIT " %s(%d) " msg "\n", \ + __func__, __LINE__, ##__VA_ARGS__) + +#define GCDBG(zone, msg, ...) \ + dev_dbg(gc_get_dev(), msg, ##__VA_ARGS__) + +#define GCERR(msg, ...) \ + GCDBG(0, msg, ##__VA_ARGS__) + +#define GCDUMPSTRING(msg, ...) \ + GCDBG(0, msg, ##__VA_ARGS__) + +#define GCDUMPBUFFER(...) {} +#define GCGPUSTATUS(...) {} + +#endif + + +/******************************************************************************* + * Command buffer parser. + */ + +struct gcrect { + int l; + int t; + int r; + int b; +}; + +struct gcsurfaceinfo { + unsigned int width; + unsigned int height; + unsigned int address; + unsigned int stride; + unsigned int swizzle; + unsigned int format; + unsigned int bpp; +}; + +struct gcsourceinfo { + struct gcsurfaceinfo surf; + struct gcrect rect; +}; + +struct gcdestinfo { + struct gcsurfaceinfo surf; + unsigned int rectcount; + struct gcrect rect[256]; +}; + +struct gccommandinfo { + unsigned int command; + unsigned int srccount; + struct gcsourceinfo src[4]; + struct gcdestinfo dst; +}; + +/* Parse the specified command buffer and fill in the structure. */ +int gc_parse_command_buffer(unsigned int *buffer, unsigned int size, + struct gccommandinfo *info); + + +/******************************************************************************* + * Filter structure. + */ + +struct gcdbgfilter { + struct list_head link; + char *filtername; + unsigned int zone; + const char *zonename[]; +}; + + +/******************************************************************************* + * Debug init/exit functions. + */ + +void gcdbg_init(void); +void gcdbg_exit(void); + + +/******************************************************************************* + * Dumping functions. + */ + +/* String dumping. */ +void gc_dump_string(struct gcdbgfilter *filter, unsigned int zone, + const char *message, ...); +void gc_dump_string_sized(struct gcdbgfilter *filter, unsigned int zone, + unsigned int argsize, const char *message, ...); + +/* Dump command buffer. */ +void gc_dump_cmd_buffer(struct gcdbgfilter *filter, unsigned int zone, + void *ptr, unsigned int gpuaddr, unsigned int datasize); + +/* Dump generic buffer. */ +void gc_dump_buffer(struct gcdbgfilter *filter, unsigned int zone, + void *ptr, unsigned int gpuaddr, unsigned int datasize); + + +/******************************************************************************* + * Bltsville debugging. + */ + +char *gc_bvblend_name(enum bvblend blend); + + +/******************************************************************************* + * Dumping control. + */ + +struct seq_file; + +struct device *gc_get_dev(void); +void gc_dump_show_enabled(struct seq_file *s); +void gc_dump_enable(void); +void gc_dump_disable(void); +void gc_dump_filter_enable(const char *filtername, int zone); +void gc_dump_flush(struct seq_file *s); +void gc_dump_reset(void); +void gc_dbg_add_client(struct gcdbgfilter *filter); + +#endif diff --git a/gcbv/mirror/include/gcerror.h b/gcbv/mirror/include/gcerror.h new file mode 100644 index 0000000..35b074d --- /dev/null +++ b/gcbv/mirror/include/gcerror.h @@ -0,0 +1,254 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GCERROR_H +#define GCERROR_H + +#define GCERR_SETGRP(error, group) \ +( \ + (enum gcerror) \ + ((error & GCERR_GENERIC_MASK) | group) \ +) + +#define GCERR_GENERIC(error) \ +( \ + (error & GCERR_GENERIC_MASK) << GCERR_GENERIC_SHIFT \ +) + +#define GCERR_GROUP(error) \ +( \ + (error & GCERR_GROUP_MASK) << GCERR_GROUP_SHIFT \ +) + +enum gcerror { + /*********************************************************************** + ** No error / success. + */ + GCERR_NONE = 0, + + /*********************************************************************** + ** Error code zones. + */ + + /* Generic error code zone. These errors inform of the low level + reason of the faulure, but don't carry information about which + logical part of the code generated the error. */ + GCERR_GENERIC_SIZE = 12, + GCERR_GENERIC_SHIFT = 0, + GCERR_GENERIC_MASK + = ((1 << GCERR_GENERIC_SIZE) - 1) << GCERR_GENERIC_SHIFT, + + /* Group error code zone. These errors inform about the logical part + of the code where the error occurred. */ + GCERR_GROUP_SIZE = (32 - GCERR_GENERIC_SIZE), + GCERR_GROUP_SHIFT = GCERR_GENERIC_SIZE, + GCERR_GROUP_MASK + = ((1 << GCERR_GROUP_SIZE) - 1) << GCERR_GROUP_SHIFT, + + /*********************************************************************** + ** Generic zone errors. + */ + + GCERR_OODM /* Out of dynamic memory. */ + = GCERR_GENERIC(1), + + GCERR_OOPM /* Out of paged memory. */ + = GCERR_GENERIC(2), + + GCERR_PMMAP /* Paged memory mapping. */ + = GCERR_GENERIC(3), + + GCERR_USER_READ /* Reading user input. */ + = GCERR_GENERIC(4), + + GCERR_USER_WRITE /* Writing user output. */ + = GCERR_GENERIC(5), + + GCERR_INTERRUPTED /* Interrupted by a signal. */ + = GCERR_GENERIC(6), + + GCERR_TIMEOUT /* Timeout. */ + = GCERR_GENERIC(7), + + GCERR_NOT_FOUND /* Data/entry not found. */ + = GCERR_GENERIC(8), + + GCERR_IOCTL /* IOCTL failed. */ + = GCERR_GENERIC(9), + + /*********************************************************************** + ** Group zone errors. + */ + + /**** Context errors. */ + GCERR_CTX_ALLOC /* Context allocation. */ + = GCERR_GROUP(0x01000), + + GCERR_CTX_CHANGE /* Lock/unlock error. */ + = GCERR_GROUP(0x01010), + + GCERR_CTX_NULL /* Context not set. */ + = GCERR_GROUP(0x01020), + + /**** Command queue errors. */ + GCERR_CMD_ENTRY_PIPE /* Entry pipe is invalid. */ + = GCERR_GROUP(0x02000), + + GCERR_CMD_EXIT_PIPE /* Exit pipe is invalid. */ + = GCERR_GROUP(0x02010), + + GCERR_CMD_MAPPED /* Command buffer mapping error. */ + = GCERR_GROUP(0x02020), + + GCERR_CMD_CONSISTENCY /* Inconsistent mapping. */ + = GCERR_GROUP(0x02030), + + GCERR_CMD_ALLOC /* Buffer allocation. */ + = GCERR_GROUP(0x02040), + + GCERR_CMD_QUEUE_ALLOC /* Buffer queue allocation. */ + = GCERR_GROUP(0x02050), + + GCERR_CMD_EVENT_ALLOC /* Event allocation. */ + = GCERR_GROUP(0x02060), + + GCERR_CMD_INT_ALLOC /* Interrupt allocation. */ + = GCERR_GROUP(0x02070), + + GCERR_CMD_ISR /* ISR initialization. */ + = GCERR_GROUP(0x02080), + + GCERR_CMD_THREAD /* Thread initialization. */ + = GCERR_GROUP(0x02090), + + /**** MMU errors. */ + GCERR_MMU_CTXT_BAD /* Invalid context. */ + = GCERR_GROUP(0x03000), + + GCERR_MMU_MTLB_ALLOC /* MTLB allocation. */ + = GCERR_GROUP(0x03010), + + GCERR_MMU_MTLB_SET /* MTLB setting. */ + = GCERR_GROUP(0x03020), + + GCERR_MMU_STLB_ALLOC /* STLB allocation. */ + = GCERR_GROUP(0x03030), + + GCERR_MMU_STLBIDX_ALLOC /* STLB index allocation. */ + = GCERR_GROUP(0x03040), + + GCERR_MMU_ARENA_ALLOC /* Vacant arena allocation. */ + = GCERR_GROUP(0x03050), + + GCERR_MMU_OOM /* No available arenas to allocate. */ + = GCERR_GROUP(0x03060), + + GCERR_MMU_SAFE_ALLOC /* Safe zone allocation. */ + = GCERR_GROUP(0x03070), + + GCERR_MMU_INIT /* MMU initialization. */ + = GCERR_GROUP(0x03080), + + GCERR_MMU_ARG /* Invalid argument. */ + = GCERR_GROUP(0x03090), + + GCERR_MMU_CLIENT /* Client initialization. */ + = GCERR_GROUP(0x030A0), + + GCERR_MMU_BUFFER_BAD /* Invalid buffer to map. */ + = GCERR_GROUP(0x030B0), + + GCERR_MMU_PAGE_BAD /* Bad page within the buffer. */ + = GCERR_GROUP(0x030C0), + + GCERR_MMU_DESC_ALLOC /* Bad page within the buffer. */ + = GCERR_GROUP(0x030D0), + + GCERR_MMU_PHYS_ALLOC /* Bad page within the buffer. */ + = GCERR_GROUP(0x030E0), + + GCERR_MMU_OFFSET /* Bad buffer offset. */ + = GCERR_GROUP(0x030F0), + + /**** Power management. */ + GCERR_POWER_MODE /* Invlalid power mode requested. */ + = GCERR_GROUP(0x04000), + + GCERR_POWER_CLOCK_ON /* Failed to enable clock. */ + = GCERR_GROUP(0x04010), + + GCERR_POWER_IRQ_ON /* Failed to install IRQ handler. */ + = GCERR_GROUP(0x04020), + + GCERR_POWER_PULSE /* Pulse skipping error. */ + = GCERR_GROUP(0x04030), + + /**** GCIOCTL module errors. */ + GCERR_IOCTL_CTX_ALLOC /* Context wrapper allocation. */ + = GCERR_GROUP(0x11000), + + GCERR_IOCTL_BUF_ALLOC /* Command buffer allocation. */ + = GCERR_GROUP(0x11010), + + GCERR_IOCTL_FIXUP_ALLOC /* Fixup buffer allocation. */ + = GCERR_GROUP(0x11020), +}; + +#endif diff --git a/gcbv/mirror/include/gcioctl.h b/gcbv/mirror/include/gcioctl.h new file mode 100644 index 0000000..9a105ab --- /dev/null +++ b/gcbv/mirror/include/gcioctl.h @@ -0,0 +1,263 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GCIOCTL_H +#define GCIOCTL_H + +#include "gclist.h" +#include "gcerror.h" +#include "cache-2dmanager.h" +#include <bverror.h> + +/* IOCTL parameters. */ +#define GCIOCTL_TYPE 0x5D +#define GCIOCTL_BASE 0x5D + + +/******************************************************************************* + * Commit API entry. + */ + +#define GCIOCTL_COMMIT _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x10, struct gccommit) + +/* GPU graphics pipe definition. */ +enum gcpipe { + GCPIPE_UNKNOWN, + GCPIPE_2D, + GCPIPE_3D +}; + +/* Commit header; contains pointers to the head and the tail of a linked list + of command buffers to execute. */ +struct gccommit { + /* Return status code. */ + enum gcerror gcerror; + + /* Entry graphics pipe specifies the pipe the GPU is expected to be in + * for successfull execution of the specified command buffers in this + * call. Exit graphics pipe specifies the state of the GPU after the + * buffers are executed. */ + enum gcpipe entrypipe; + enum gcpipe exitpipe; + + /* Pointer to the list of command buffers to be executed. */ + struct gcbuffer *buffer; + + /* Pointer to the callback function to be called when the GPU completes + * execution of all buffers specified in this call. This member can be + * NULL if no callback is desired. callbackparam specifies data to be + * passed to the callback. */ + void (*callback) (void *callbackparam); + void *callbackparam; + unsigned long handle; + + /* If asynchronous is set to true, the call returns immediately without + * waiting until all specified buffers have been executed. If set to + * false, the call does not return until execution is finished. */ + bool asynchronous; + + /* Scheduled unmappings (gcschedunmap). */ + struct list_head unmap; +}; + +/* Command buffer header. */ +#define GC_BUFFER_SIZE (32 * 1024) +struct gcbuffer { + /* Pointers to the head and tail of the command buffer fixup list. */ + struct gcfixup *fixuphead; + struct gcfixup *fixuptail; + + /* Number of pixels to be rendered. */ + unsigned int pixelcount; + + /* Pointers to the head and tail of the command buffer list. */ + unsigned int *head; + unsigned int *tail; + + /* Number of bytes available in the buffer for allocation. */ + unsigned int available; + + /* Pointer to the next commmand buffer. + * TODO: change to kernel style linked list. */ + struct gcbuffer *next; +}; + +/* Fixup entry. */ +struct gcfixupentry { + /* Offset into the commmand buffer where fixup is to be performed. */ + unsigned int dataoffset; + + /* Offset to be added to the translated address. */ + unsigned int surfoffset; +}; + +/* Address fixup array. */ +#define GC_FIXUP_MAX 1024 +struct gcfixup { + /* Pointer to the next fixup array. + * TODO: change to kernel style linked list. */ + struct gcfixup *next; + + /* Fixup array. */ + unsigned int count; + struct gcfixupentry fixup[GC_FIXUP_MAX]; +}; + +/* Defines a link list of scheduled unmappings. */ +struct gcschedunmap { + /* Map handle. */ + unsigned long handle; + + /* Previous/next unmapping info. */ + struct list_head link; +}; + + +/******************************************************************************* + * Map/unmap API entries. + */ + +#define GCIOCTL_MAP _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x20, struct gcmap) +#define GCIOCTL_UNMAP _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x21, struct gcmap) + +struct gcmap { + /* Return status code. */ + enum gcerror gcerror; + + /* Mapped handle of the buffer. */ + unsigned long handle; + + union { + /* Pointer to the buffer to be mapped; + * used when pagearray is not provided (set to NULL). */ + void *logical; + + /* Page offset of the buffer to be mapped; + * used when pagearray is provided. */ + unsigned int offset; + } buf; + + /* Size of a physical page, 0 for default. */ + unsigned int pagesize; + + /* Pointer to array of physical pages. */ + unsigned long *pagearray; + + /* Size of the buffer to be mappped. */ + unsigned int size; +}; + + +/***************************************************************************** + * Cache manipulation API entries. + */ + +#define GCIOCTL_CACHE _IOW(GCIOCTL_TYPE, GCIOCTL_BASE + 0x30, \ + struct gccachexfer) + +struct gccachexfer { + /* Number of regions. */ + int count; + + /* The most regions that we deal with is 3. */ + struct c2dmrgn rgn[3]; + + /* Direction of data. */ + int dir; +}; + + +/******************************************************************************* + * Callback API entry. + */ + +#define GCIOCTL_CALLBACK_ALLOC _IOW(GCIOCTL_TYPE, GCIOCTL_BASE + 0x40, \ + struct gccmdcallback) +#define GCIOCTL_CALLBACK_FREE _IOW(GCIOCTL_TYPE, GCIOCTL_BASE + 0x41, \ + struct gccmdcallback) +#define GCIOCTL_CALLBACK_WAIT _IOW(GCIOCTL_TYPE, GCIOCTL_BASE + 0x42, \ + struct gccmdcallbackwait) + +struct gccmdcallback { + /* Error code. */ + enum gcerror gcerror; + + /* Callback handle. */ + unsigned long handle; +}; + +struct gccmdcallbackwait { + /* Error code. */ + enum gcerror gcerror; + + /* Callback handle. */ + unsigned long handle; + + /* Timeout in milliseconds. */ + unsigned long timeoutms; + + /* OUT: if the call succeeds, callback and callbackparam are + * initialized with the callback to call. */ + void (*callback) (void *callbackparam); + void *callbackparam; +}; + + +#endif diff --git a/gcbv/mirror/include/gclist.h b/gcbv/mirror/include/gclist.h new file mode 100644 index 0000000..33c9743 --- /dev/null +++ b/gcbv/mirror/include/gclist.h @@ -0,0 +1,630 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _GCLIST_H +#define _GCLIST_H +#ifdef __cplusplus +extern "C" { +#endif + +/* Adaptation of Linux kernel double linked list. */ + +#define LIST_POISON1 ((void *) 0x00100100) +#define LIST_POISON2 ((void *) 0x00200200) + +#if !defined(countof) +#define countof(a) \ + (sizeof(a) / sizeof(a[0])) +#endif + +#if !defined(offsetof) +#define offsetof(type, member) \ + ((size_t) &((type *) 0)->member) +#endif + +#if !defined(containerof) +#define containerof(ptr, type, member) \ + ((type *) ((char *) ptr - offsetof(type, member))) +#endif + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +static void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} + +/* Insert a new entry between two known consecutive entries. + * This is only for internal list manipulation where we know + * the prev/next entries already! */ +static void __list_add(struct list_head *entry, + struct list_head *prev, + struct list_head *next) +{ + next->prev = entry; + entry->next = next; + entry->prev = prev; + prev->next = entry; +} + +/** + * list_add - add a new entry + * @newentry: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static void list_add(struct list_head *newentry, + struct list_head *head) +{ + __list_add(newentry, head, head->next); +} + + +/** + * list_add_tail - add a new entry + * @newentry: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static void list_add_tail(struct list_head *newentry, + struct list_head *head) +{ + __list_add(newentry, head->prev, head); +} + +/* Delete a list entry by making the prev/next entries point to each other. + * This is only for internal list manipulation where we know + * the prev/next entries already! */ +static void __list_del(struct list_head *prev, + struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty() on entry does not return true after this, + * the entry is in an undefined state. + */ +static void __list_del_entry(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); +} + +static void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = LIST_POISON1; + entry->prev = LIST_POISON2; +} + +/** + * list_replace - replace old entry by new one + * @oldentry : the element to be replaced + * @newentry : the new element to insert + * + * If @old was empty, it will be overwritten. + */ +static void list_replace(struct list_head *oldentry, + struct list_head *newentry) +{ + newentry->next = oldentry->next; + newentry->next->prev = newentry; + newentry->prev = oldentry->prev; + newentry->prev->next = newentry; +} + +static void list_replace_init(struct list_head *oldentry, + struct list_head *newentry) +{ + list_replace(oldentry, newentry); + INIT_LIST_HEAD(oldentry); +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static void list_del_init(struct list_head *entry) +{ + __list_del_entry(entry); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static void list_move(struct list_head *list, + struct list_head *head) +{ + __list_del_entry(list); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del_entry(list); + list_add_tail(list, head); +} + +/** + * list_is_last - tests whether @list is the last entry in list @head + * @list: the entry to test + * @head: the head of the list + */ +static int list_is_last(const struct list_head *list, + const struct list_head *head) +{ + return list->next == head; +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static int list_empty(const struct list_head *head) +{ + return (head->next == NULL) || (head->next == head); +} + +/** + * list_empty_careful - tests whether a list is empty and not being modified + * @head: the list to test + * + * Description: + * tests whether a list is empty _and_ checks that no other CPU might be + * in the process of modifying either member (next or prev) + * + * NOTE: using list_empty_careful() without synchronization + * can only be safe if the only activity that can happen + * to the list entry is list_del_init(). Eg. it cannot be used + * if another CPU could re-list_add() it. + */ +static int list_empty_careful(const struct list_head *head) +{ + struct list_head *next = head->next; + return (next == head) && (next == head->prev); +} + +/** + * list_rotate_left - rotate the list to the left + * @head: the head of the list + */ +static void list_rotate_left(struct list_head *head) +{ + struct list_head *first; + + if (!list_empty(head)) { + first = head->next; + list_move_tail(first, head); + } +} + +/** + * list_is_singular - tests whether a list has just one entry. + * @head: the list to test. + */ +static int list_is_singular(const struct list_head *head) +{ + return !list_empty(head) && (head->next == head->prev); +} + +static void __list_cut_position(struct list_head *list, + struct list_head *head, + struct list_head *entry) +{ + struct list_head *new_first = entry->next; + list->next = head->next; + list->next->prev = list; + list->prev = entry; + entry->next = list; + head->next = new_first; + new_first->prev = head; +} + +/** + * list_cut_position - cut a list into two + * @list: a new list to add all removed entries + * @head: a list with entries + * @entry: an entry within head, could be the head itself + * and if so we won't cut the list + * + * This helper moves the initial part of @head, up to and + * including @entry, from @head to @list. You should + * pass on @entry an element you know is on @head. @list + * should be an empty list or a list you do not care about + * losing its data. + */ +static void list_cut_position(struct list_head *list, + struct list_head *head, + struct list_head *entry) +{ + if (list_empty(head)) + return; + if (list_is_singular(head) && + (head->next != entry && head != entry)) + return; + if (entry == head) + INIT_LIST_HEAD(list); + else + __list_cut_position(list, head, entry); +} + +static void __list_splice(const struct list_head *list, + struct list_head *prev, + struct list_head *next) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + + first->prev = prev; + prev->next = first; + + last->next = next; + next->prev = last; +} + +/** + * list_splice - join two lists, this is designed for stacks + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static void list_splice(const struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head, head->next); +} + +/** + * list_splice_tail - join two lists, each list being a queue + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static void list_splice_tail(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head->prev, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head, head->next); + INIT_LIST_HEAD(list); + } +} + +/** + * list_splice_tail_init - join two lists and reinitialise the emptied list + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * Each of the lists is a queue. + * The list at @list is reinitialised + */ +static void list_splice_tail_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head->prev, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + containerof(ptr, type, member) + +/** + * list_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * __list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + * + * This variant doesn't differ from list_for_each() any more. + * We don't do prefetching in either case. + */ +#define __list_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop cursor. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_prev_safe - iterate over a list backwards safe against removal + * of list entry + * @pos: the &struct list_head to use as a loop cursor. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; \ + pos != (head); \ + pos = n, n = pos->prev) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_reverse - iterate backwards over list of given type. + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_reverse(pos, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_prepare_entry - prepare a pos entry for use in + * list_for_each_entry_continue() + * @pos: the type * to use as a start point + * @head: the head of the list + * @member: the name of the list_struct within the struct. + * + * Prepares a pos entry for use as a start point in + * list_for_each_entry_continue(). + */ +#define list_prepare_entry(pos, head, member) \ + ((pos) ? : list_entry(head, typeof(*pos), member)) + +/** + * list_for_each_entry_continue - continue iteration over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Continue to iterate over list of given type, continuing after + * the current position. + */ + #define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Start to iterate over list of given type backwards, continuing after + * the current position. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, typeof(*pos), member)) + +/** + * list_for_each_entry_from - iterate over list of given type from the current + * point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing from current position. + */ +#define list_for_each_entry_from(pos, head, member) \ + for (; &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against + * removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_continue - continue list iteration safe against + * removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type, continuing after current point, + * safe against removal of list entry. + */ +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_from - iterate over list from current point + * safe against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate over list of given type from current point, safe against + * removal of list entry. + */ +#define list_for_each_entry_safe_from(pos, n, head, member) \ + for (n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_safe_reverse - iterate backwards over list safe + * against removal + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + * + * Iterate backwards over list of given type, safe against removal + * of list entry. + */ +#define list_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = list_entry((head)->prev, typeof(*pos), member), \ + n = list_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.prev, typeof(*n), member)) + +/** + * list_safe_reset_next - reset a stale list_for_each_entry_safe loop + * @pos: the loop cursor used in the list_for_each_entry_safe loop + * @n: temporary storage used in list_for_each_entry_safe + * @member: the name of the list_struct within the struct. + * + * list_safe_reset_next is not safe to use in general if the list may be + * modified concurrently (eg. the lock is dropped in the loop body). An + * exception to this is if the cursor element (pos) is pinned in the list, + * and list_safe_reset_next is called after re-taking the lock and before + * completing the current iteration of the loop body. + */ +#define list_safe_reset_next(pos, n, member) \ + n = list_entry(pos->member.next, typeof(*pos), member) + +#ifdef __cplusplus +} +#endif +#endif diff --git a/gcbv/mirror/include/gcreg.h b/gcbv/mirror/include/gcreg.h new file mode 100644 index 0000000..9aa128f --- /dev/null +++ b/gcbv/mirror/include/gcreg.h @@ -0,0 +1,8827 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __gcreg_h +#define __gcreg_h + +/******************************************************************************* +** Register access macros. +*/ + +#define GCREGSTART(reg_field) \ +( \ + 0 ? reg_field \ +) + +#define GCREGEND(reg_field) \ +( \ + 1 ? reg_field \ +) + +#define GCREGSIZE(reg_field) \ +( \ + GCREGEND(reg_field) - GCREGSTART(reg_field) + 1 \ +) + +#define GCREGALIGN(data, reg_field) \ +( \ + ((unsigned int) (data)) << GCREGSTART(reg_field) \ +) + +#define GCREGMASK(reg_field) \ +( \ + GCREGALIGN(~0UL >> (32 - GCREGSIZE(reg_field)), reg_field) \ +) + +#define GCSETFIELDVAL(data, reg, field, value) \ +( \ + (((unsigned int) (data)) & ~GCREGMASK(reg##_##field)) \ + | (GCREGALIGN(reg##_##field##_##value, reg##_##field) \ + & GCREGMASK(reg##_##field)) \ +) + +#define GCSETFIELD(data, reg, field, value) \ +( \ + (((unsigned int) (data)) & ~GCREGMASK(reg##_##field)) \ + | (GCREGALIGN((unsigned int) (value), reg##_##field) \ + & GCREGMASK(reg##_##field)) \ +) + +#define GCGETFIELD(data, reg, field) \ +( \ + (((unsigned int) (data)) & GCREGMASK(reg##_##field)) \ + >> GCREGSTART(reg##_##field) \ +) + +#define GCREGVALUE(reg, field, val) \ +( \ + reg##_##field##_##val \ +) + +/******************************************************************************* +** Register gcregHiClockControl +*/ + +#define GCREG_HI_CLOCK_CONTROL_Address 0x00000 +#define GCREG_HI_CLOCK_CONTROL_MSB 15 +#define GCREG_HI_CLOCK_CONTROL_LSB 0 +#define GCREG_HI_CLOCK_CONTROL_BLK 0 +#define GCREG_HI_CLOCK_CONTROL_Count 1 +#define GCREG_HI_CLOCK_CONTROL_FieldMask 0x000A17FE +#define GCREG_HI_CLOCK_CONTROL_ReadMask 0x000A17FE +#define GCREG_HI_CLOCK_CONTROL_WriteMask 0x000817FE +#define GCREG_HI_CLOCK_CONTROL_ResetValue 0x00000100 + +/* Disable 3D clock. */ +#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS 0 : 0 +#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS_End 0 +#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS_Start 0 +#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS_Type U01 + +/* Disable 2D clock. */ +#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS 1 : 1 +#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS_End 1 +#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS_Start 1 +#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS_Type U01 + +#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL 8 : 2 +#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL_End 8 +#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL_Start 2 +#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL_Type U07 + +#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 9 : 9 +#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_End 9 +#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_Start 9 +#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_Type U01 + +/* Disables clock gating for rams. */ +#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 10 : 10 +#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING_End 10 +#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING_Start 10 +#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING_Type U01 + +/* Disable debug registers. If this bit is 1, debug regs are clock gated. */ +#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 11 : 11 +#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS_End 11 +#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS_Start 11 +#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS_Type U01 + +/* Soft resets the IP. */ +#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET 12 : 12 +#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET_End 12 +#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET_Start 12 +#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET_Type U01 + +/* 3D pipe is idle. */ +#define GCREG_HI_CLOCK_CONTROL_IDLE_3D 16 : 16 +#define GCREG_HI_CLOCK_CONTROL_IDLE_3D_End 16 +#define GCREG_HI_CLOCK_CONTROL_IDLE_3D_Start 16 +#define GCREG_HI_CLOCK_CONTROL_IDLE_3D_Type U01 + +/* 2D pipe is idle. */ +#define GCREG_HI_CLOCK_CONTROL_IDLE_2D 17 : 17 +#define GCREG_HI_CLOCK_CONTROL_IDLE_2D_End 17 +#define GCREG_HI_CLOCK_CONTROL_IDLE_2D_Start 17 +#define GCREG_HI_CLOCK_CONTROL_IDLE_2D_Type U01 + +/* VG pipe is idle. */ +#define GCREG_HI_CLOCK_CONTROL_IDLE_VG 18 : 18 +#define GCREG_HI_CLOCK_CONTROL_IDLE_VG_End 18 +#define GCREG_HI_CLOCK_CONTROL_IDLE_VG_Start 18 +#define GCREG_HI_CLOCK_CONTROL_IDLE_VG_Type U01 + +/* Isolate GPU bit */ +#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU 19 : 19 +#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU_End 19 +#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU_Start 19 +#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU_Type U01 + +union gcclockcontrol { + struct { + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_CLK3D_DIS */ + unsigned int disable3d:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_CLK2D_DIS */ + unsigned int disable2d:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_FSCALE_VAL */ + unsigned int pulsecount:7; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD */ + unsigned int pulseset:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING */ + unsigned int ramgate:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS */ + unsigned int disabledbg:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_SOFT_RESET */ + unsigned int reset:1; + + /* gcregHiClockControl: + reserved */ + unsigned int _reserved_13_15:3; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_IDLE_3D */ + unsigned int idle3d:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_IDLE_2D */ + unsigned int idle2d:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_IDLE_VG */ + unsigned int idlevg:1; + + /* gcregHiClockControl: + GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU */ + unsigned int isolate:1; + + /* gcregHiClockControl: + reserved */ + unsigned int _reserved_20_31:12; + } reg; + + unsigned int raw; +}; + +/******************************************************************************* +** Register gcregHiIdle +*/ + +#define GCREG_HI_IDLE_Address 0x00004 +#define GCREG_HI_IDLE_MSB 15 +#define GCREG_HI_IDLE_LSB 0 +#define GCREG_HI_IDLE_BLK 0 +#define GCREG_HI_IDLE_Count 1 +#define GCREG_HI_IDLE_FieldMask 0x80000007 +#define GCREG_HI_IDLE_ReadMask 0x80000007 +#define GCREG_HI_IDLE_WriteMask 0x00000000 +#define GCREG_HI_IDLE_ResetValue 0x00000007 + +/* FE is idle. */ +#define GCREG_HI_IDLE_IDLE_FE 0 : 0 +#define GCREG_HI_IDLE_IDLE_FE_End 0 +#define GCREG_HI_IDLE_IDLE_FE_Start 0 +#define GCREG_HI_IDLE_IDLE_FE_Type U01 + +/* DE is idle. */ +#define GCREG_HI_IDLE_IDLE_DE 1 : 1 +#define GCREG_HI_IDLE_IDLE_DE_End 1 +#define GCREG_HI_IDLE_IDLE_DE_Start 1 +#define GCREG_HI_IDLE_IDLE_DE_Type U01 + +/* PE is idle. */ +#define GCREG_HI_IDLE_IDLE_PE 2 : 2 +#define GCREG_HI_IDLE_IDLE_PE_End 2 +#define GCREG_HI_IDLE_IDLE_PE_Start 2 +#define GCREG_HI_IDLE_IDLE_PE_Type U01 + +/* AXI is in low power mode. */ +#define GCREG_HI_IDLE_AXI_LP 31 : 31 +#define GCREG_HI_IDLE_AXI_LP_End 31 +#define GCREG_HI_IDLE_AXI_LP_Start 31 +#define GCREG_HI_IDLE_AXI_LP_Type U01 + +union gcidle { + struct { + /* gcregHiIdle: GCREG_HI_IDLE_IDLE_FE */ + unsigned int fe:1; + + /* gcregHiIdle: GCREG_HI_IDLE_IDLE_DE */ + unsigned int de:1; + + /* gcregHiIdle: GCREG_HI_IDLE_IDLE_PE */ + unsigned int pe:1; + + /* gcregHiIdle: reserved */ + unsigned int _reserved_3_30:28; + + /* gcregHiIdle: GCREG_HI_IDLE_AXI_LP */ + unsigned int axilp:1; + } reg; + + unsigned int raw; +}; + +/******************************************************************************* +** Register gcregAxiConfig +*/ + +#define GCREG_AXI_CONFIG_Address 0x00008 +#define GCREG_AXI_CONFIG_MSB 15 +#define GCREG_AXI_CONFIG_LSB 0 +#define GCREG_AXI_CONFIG_BLK 0 +#define GCREG_AXI_CONFIG_Count 1 +#define GCREG_AXI_CONFIG_FieldMask 0x0000FFFF +#define GCREG_AXI_CONFIG_ReadMask 0x0000FFFF +#define GCREG_AXI_CONFIG_WriteMask 0x0000FFFF +#define GCREG_AXI_CONFIG_ResetValue 0x00000000 + +#define GCREG_AXI_CONFIG_AWID 3 : 0 +#define GCREG_AXI_CONFIG_AWID_End 3 +#define GCREG_AXI_CONFIG_AWID_Start 0 +#define GCREG_AXI_CONFIG_AWID_Type U04 + +#define GCREG_AXI_CONFIG_ARID 7 : 4 +#define GCREG_AXI_CONFIG_ARID_End 7 +#define GCREG_AXI_CONFIG_ARID_Start 4 +#define GCREG_AXI_CONFIG_ARID_Type U04 + +#define GCREG_AXI_CONFIG_AWCACHE 11 : 8 +#define GCREG_AXI_CONFIG_AWCACHE_End 11 +#define GCREG_AXI_CONFIG_AWCACHE_Start 8 +#define GCREG_AXI_CONFIG_AWCACHE_Type U04 + +#define GCREG_AXI_CONFIG_ARCACHE 15 : 12 +#define GCREG_AXI_CONFIG_ARCACHE_End 15 +#define GCREG_AXI_CONFIG_ARCACHE_Start 12 +#define GCREG_AXI_CONFIG_ARCACHE_Type U04 + +/******************************************************************************* +** Register gcregAxiStatus +*/ + +#define GCREG_AXI_STATUS_Address 0x0000C +#define GCREG_AXI_STATUS_MSB 15 +#define GCREG_AXI_STATUS_LSB 0 +#define GCREG_AXI_STATUS_BLK 0 +#define GCREG_AXI_STATUS_Count 1 +#define GCREG_AXI_STATUS_FieldMask 0x000003FF +#define GCREG_AXI_STATUS_ReadMask 0x000003FF +#define GCREG_AXI_STATUS_WriteMask 0x00000000 +#define GCREG_AXI_STATUS_ResetValue 0x00000000 + +#define GCREG_AXI_STATUS_DET_RD_ERR 9 : 9 +#define GCREG_AXI_STATUS_DET_RD_ERR_End 9 +#define GCREG_AXI_STATUS_DET_RD_ERR_Start 9 +#define GCREG_AXI_STATUS_DET_RD_ERR_Type U01 + +#define GCREG_AXI_STATUS_DET_WR_ERR 8 : 8 +#define GCREG_AXI_STATUS_DET_WR_ERR_End 8 +#define GCREG_AXI_STATUS_DET_WR_ERR_Start 8 +#define GCREG_AXI_STATUS_DET_WR_ERR_Type U01 + +#define GCREG_AXI_STATUS_RD_ERR_ID 7 : 4 +#define GCREG_AXI_STATUS_RD_ERR_ID_End 7 +#define GCREG_AXI_STATUS_RD_ERR_ID_Start 4 +#define GCREG_AXI_STATUS_RD_ERR_ID_Type U04 + +#define GCREG_AXI_STATUS_WR_ERR_ID 3 : 0 +#define GCREG_AXI_STATUS_WR_ERR_ID_End 3 +#define GCREG_AXI_STATUS_WR_ERR_ID_Start 0 +#define GCREG_AXI_STATUS_WR_ERR_ID_Type U04 + +/******************************************************************************* +** Register gcregIntrAcknowledge +*/ + +/* Interrupt acknowledge register. Each bit represents a corresponding event +** being triggered. Reading from this register clears the outstanding interrupt. +*/ + +#define GCREG_INTR_ACKNOWLEDGE_Address 0x00010 +#define GCREG_INTR_ACKNOWLEDGE_MSB 15 +#define GCREG_INTR_ACKNOWLEDGE_LSB 0 +#define GCREG_INTR_ACKNOWLEDGE_BLK 0 +#define GCREG_INTR_ACKNOWLEDGE_Count 1 +#define GCREG_INTR_ACKNOWLEDGE_FieldMask 0xFFFFFFFF +#define GCREG_INTR_ACKNOWLEDGE_ReadMask 0xFFFFFFFF +#define GCREG_INTR_ACKNOWLEDGE_WriteMask 0x00000000 +#define GCREG_INTR_ACKNOWLEDGE_ResetValue 0x00000000 + +#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC 31 : 0 +#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC_End 31 +#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC_Start 0 +#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC_Type U32 + +/******************************************************************************* +** Register gcregIntrEnbl +*/ + +/* Interrupt enable register. Each bit enables a corresponding event. */ + +#define GCREG_INTR_ENBL_Address 0x00014 +#define GCREG_INTR_ENBL_MSB 15 +#define GCREG_INTR_ENBL_LSB 0 +#define GCREG_INTR_ENBL_BLK 0 +#define GCREG_INTR_ENBL_Count 1 +#define GCREG_INTR_ENBL_FieldMask 0xFFFFFFFF +#define GCREG_INTR_ENBL_ReadMask 0xFFFFFFFF +#define GCREG_INTR_ENBL_WriteMask 0xFFFFFFFF +#define GCREG_INTR_ENBL_ResetValue 0x00000000 + +#define GCREG_INTR_ENBL_INTR_ENBL_VEC 31 : 0 +#define GCREG_INTR_ENBL_INTR_ENBL_VEC_End 31 +#define GCREG_INTR_ENBL_INTR_ENBL_VEC_Start 0 +#define GCREG_INTR_ENBL_INTR_ENBL_VEC_Type U32 + +/******************************************************************************* +** Register GCFeatures +*/ + +/* Shows which features are enabled in this chip. This register has no set +** reset value. It varies with the implementation. +*/ + +#define GC_FEATURES_Address 0x0001C +#define GC_FEATURES_MSB 15 +#define GC_FEATURES_LSB 0 +#define GC_FEATURES_BLK 0 +#define GC_FEATURES_Count 1 +#define GC_FEATURES_FieldMask 0xFFFFFFFF +#define GC_FEATURES_ReadMask 0xFFFFFFFF +#define GC_FEATURES_WriteMask 0x00000000 +#define GC_FEATURES_ResetValue 0x00000000 + +/* Fast clear. */ +#define GC_FEATURES_FAST_CLEAR 0 : 0 +#define GC_FEATURES_FAST_CLEAR_End 0 +#define GC_FEATURES_FAST_CLEAR_Start 0 +#define GC_FEATURES_FAST_CLEAR_Type U01 +#define GC_FEATURES_FAST_CLEAR_NONE 0x0 +#define GC_FEATURES_FAST_CLEAR_AVAILABLE 0x1 + +/* Full-screen anti-aliasing. */ +#define GC_FEATURES_SPECIAL_ANTI_ALIASING 1 : 1 +#define GC_FEATURES_SPECIAL_ANTI_ALIASING_End 1 +#define GC_FEATURES_SPECIAL_ANTI_ALIASING_Start 1 +#define GC_FEATURES_SPECIAL_ANTI_ALIASING_Type U01 +#define GC_FEATURES_SPECIAL_ANTI_ALIASING_NONE 0x0 +#define GC_FEATURES_SPECIAL_ANTI_ALIASING_AVAILABLE 0x1 + +/* 3D pipe. */ +#define GC_FEATURES_PIPE_3D 2 : 2 +#define GC_FEATURES_PIPE_3D_End 2 +#define GC_FEATURES_PIPE_3D_Start 2 +#define GC_FEATURES_PIPE_3D_Type U01 +#define GC_FEATURES_PIPE_3D_NONE 0x0 +#define GC_FEATURES_PIPE_3D_AVAILABLE 0x1 + +/* DXT texture compression. */ +#define GC_FEATURES_DXT_TEXTURE_COMPRESSION 3 : 3 +#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_End 3 +#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_Start 3 +#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_Type U01 +#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_NONE 0x0 +#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_AVAILABLE 0x1 + +/* Debug registers. */ +#define GC_FEATURES_DEBUG_MODE 4 : 4 +#define GC_FEATURES_DEBUG_MODE_End 4 +#define GC_FEATURES_DEBUG_MODE_Start 4 +#define GC_FEATURES_DEBUG_MODE_Type U01 +#define GC_FEATURES_DEBUG_MODE_NONE 0x0 +#define GC_FEATURES_DEBUG_MODE_AVAILABLE 0x1 + +/* Depth and color compression. */ +#define GC_FEATURES_ZCOMPRESSION 5 : 5 +#define GC_FEATURES_ZCOMPRESSION_End 5 +#define GC_FEATURES_ZCOMPRESSION_Start 5 +#define GC_FEATURES_ZCOMPRESSION_Type U01 +#define GC_FEATURES_ZCOMPRESSION_NONE 0x0 +#define GC_FEATURES_ZCOMPRESSION_AVAILABLE 0x1 + +/* YUV 4:2:0 support in filter blit. */ +#define GC_FEATURES_YUV420_FILTER 6 : 6 +#define GC_FEATURES_YUV420_FILTER_End 6 +#define GC_FEATURES_YUV420_FILTER_Start 6 +#define GC_FEATURES_YUV420_FILTER_Type U01 +#define GC_FEATURES_YUV420_FILTER_NONE 0x0 +#define GC_FEATURES_YUV420_FILTER_AVAILABLE 0x1 + +/* MSAA support. */ +#define GC_FEATURES_MSAA 7 : 7 +#define GC_FEATURES_MSAA_End 7 +#define GC_FEATURES_MSAA_Start 7 +#define GC_FEATURES_MSAA_Type U01 +#define GC_FEATURES_MSAA_NONE 0x0 +#define GC_FEATURES_MSAA_AVAILABLE 0x1 + +/* Shows if there is a display controller in the IP. */ +#define GC_FEATURES_DC 8 : 8 +#define GC_FEATURES_DC_End 8 +#define GC_FEATURES_DC_Start 8 +#define GC_FEATURES_DC_Type U01 +#define GC_FEATURES_DC_NONE 0x0 +#define GC_FEATURES_DC_AVAILABLE 0x1 + +/* Shows if there is 2D engine. */ +#define GC_FEATURES_PIPE_2D 9 : 9 +#define GC_FEATURES_PIPE_2D_End 9 +#define GC_FEATURES_PIPE_2D_Start 9 +#define GC_FEATURES_PIPE_2D_Type U01 +#define GC_FEATURES_PIPE_2D_NONE 0x0 +#define GC_FEATURES_PIPE_2D_AVAILABLE 0x1 + +/* ETC1 texture compression. */ +#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION 10 : 10 +#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_End 10 +#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_Start 10 +#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_Type U01 +#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_NONE 0x0 +#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_AVAILABLE 0x1 + +/* Shows if the IP has HD scaler. */ +#define GC_FEATURES_FAST_SCALER 11 : 11 +#define GC_FEATURES_FAST_SCALER_End 11 +#define GC_FEATURES_FAST_SCALER_Start 11 +#define GC_FEATURES_FAST_SCALER_Type U01 +#define GC_FEATURES_FAST_SCALER_NONE 0x0 +#define GC_FEATURES_FAST_SCALER_AVAILABLE 0x1 + +/* Shows if the IP has HDR support. */ +#define GC_FEATURES_HIGH_DYNAMIC_RANGE 12 : 12 +#define GC_FEATURES_HIGH_DYNAMIC_RANGE_End 12 +#define GC_FEATURES_HIGH_DYNAMIC_RANGE_Start 12 +#define GC_FEATURES_HIGH_DYNAMIC_RANGE_Type U01 +#define GC_FEATURES_HIGH_DYNAMIC_RANGE_NONE 0x0 +#define GC_FEATURES_HIGH_DYNAMIC_RANGE_AVAILABLE 0x1 + +/* YUV 4:2:0 tiler is available. */ +#define GC_FEATURES_YUV420_TILER 13 : 13 +#define GC_FEATURES_YUV420_TILER_End 13 +#define GC_FEATURES_YUV420_TILER_Start 13 +#define GC_FEATURES_YUV420_TILER_Type U01 +#define GC_FEATURES_YUV420_TILER_NONE 0x0 +#define GC_FEATURES_YUV420_TILER_AVAILABLE 0x1 + +/* Second level clock gating is available. */ +#define GC_FEATURES_MODULE_CG 14 : 14 +#define GC_FEATURES_MODULE_CG_End 14 +#define GC_FEATURES_MODULE_CG_Start 14 +#define GC_FEATURES_MODULE_CG_Type U01 +#define GC_FEATURES_MODULE_CG_NONE 0x0 +#define GC_FEATURES_MODULE_CG_AVAILABLE 0x1 + +/* IP is configured to have minimum area. */ +#define GC_FEATURES_MIN_AREA 15 : 15 +#define GC_FEATURES_MIN_AREA_End 15 +#define GC_FEATURES_MIN_AREA_Start 15 +#define GC_FEATURES_MIN_AREA_Type U01 +#define GC_FEATURES_MIN_AREA_NONE 0x0 +#define GC_FEATURES_MIN_AREA_AVAILABLE 0x1 + +/* IP does not have early-Z. */ +#define GC_FEATURES_NO_EZ 16 : 16 +#define GC_FEATURES_NO_EZ_End 16 +#define GC_FEATURES_NO_EZ_Start 16 +#define GC_FEATURES_NO_EZ_Type U01 +#define GC_FEATURES_NO_EZ_NONE 0x0 +#define GC_FEATURES_NO_EZ_AVAILABLE 0x1 + +/* IP does not have 422 texture input format. */ +#define GC_FEATURES_NO422_TEXTURE 17 : 17 +#define GC_FEATURES_NO422_TEXTURE_End 17 +#define GC_FEATURES_NO422_TEXTURE_Start 17 +#define GC_FEATURES_NO422_TEXTURE_Type U01 +#define GC_FEATURES_NO422_TEXTURE_NONE 0x0 +#define GC_FEATURES_NO422_TEXTURE_AVAILABLE 0x1 + +/* IP supports interleaving depth and color buffers. */ +#define GC_FEATURES_BUFFER_INTERLEAVING 18 : 18 +#define GC_FEATURES_BUFFER_INTERLEAVING_End 18 +#define GC_FEATURES_BUFFER_INTERLEAVING_Start 18 +#define GC_FEATURES_BUFFER_INTERLEAVING_Type U01 +#define GC_FEATURES_BUFFER_INTERLEAVING_NONE 0x0 +#define GC_FEATURES_BUFFER_INTERLEAVING_AVAILABLE 0x1 + +/* Supports byte write in 2D. */ +#define GC_FEATURES_BYTE_WRITE_2D 19 : 19 +#define GC_FEATURES_BYTE_WRITE_2D_End 19 +#define GC_FEATURES_BYTE_WRITE_2D_Start 19 +#define GC_FEATURES_BYTE_WRITE_2D_Type U01 +#define GC_FEATURES_BYTE_WRITE_2D_NONE 0x0 +#define GC_FEATURES_BYTE_WRITE_2D_AVAILABLE 0x1 + +/* IP does not have 2D scaler. */ +#define GC_FEATURES_NO_SCALER 20 : 20 +#define GC_FEATURES_NO_SCALER_End 20 +#define GC_FEATURES_NO_SCALER_Start 20 +#define GC_FEATURES_NO_SCALER_Type U01 +#define GC_FEATURES_NO_SCALER_NONE 0x0 +#define GC_FEATURES_NO_SCALER_AVAILABLE 0x1 + +/* YUY2 averaging support in resolve. */ +#define GC_FEATURES_YUY2_AVERAGING 21 : 21 +#define GC_FEATURES_YUY2_AVERAGING_End 21 +#define GC_FEATURES_YUY2_AVERAGING_Start 21 +#define GC_FEATURES_YUY2_AVERAGING_Type U01 +#define GC_FEATURES_YUY2_AVERAGING_NONE 0x0 +#define GC_FEATURES_YUY2_AVERAGING_AVAILABLE 0x1 + +/* PE cache is half. */ +#define GC_FEATURES_HALF_PE_CACHE 22 : 22 +#define GC_FEATURES_HALF_PE_CACHE_End 22 +#define GC_FEATURES_HALF_PE_CACHE_Start 22 +#define GC_FEATURES_HALF_PE_CACHE_Type U01 +#define GC_FEATURES_HALF_PE_CACHE_NONE 0x0 +#define GC_FEATURES_HALF_PE_CACHE_AVAILABLE 0x1 + +/* TX cache is half. */ +#define GC_FEATURES_HALF_TX_CACHE 23 : 23 +#define GC_FEATURES_HALF_TX_CACHE_End 23 +#define GC_FEATURES_HALF_TX_CACHE_Start 23 +#define GC_FEATURES_HALF_TX_CACHE_Type U01 +#define GC_FEATURES_HALF_TX_CACHE_NONE 0x0 +#define GC_FEATURES_HALF_TX_CACHE_AVAILABLE 0x1 + +/* YUY2 support in PE and YUY2 to RGB conversion in resolve. */ +#define GC_FEATURES_YUY2_RENDER_TARGET 24 : 24 +#define GC_FEATURES_YUY2_RENDER_TARGET_End 24 +#define GC_FEATURES_YUY2_RENDER_TARGET_Start 24 +#define GC_FEATURES_YUY2_RENDER_TARGET_Type U01 +#define GC_FEATURES_YUY2_RENDER_TARGET_NONE 0x0 +#define GC_FEATURES_YUY2_RENDER_TARGET_AVAILABLE 0x1 + +/* 32 bit memory address support. */ +#define GC_FEATURES_MEM32_BIT_SUPPORT 25 : 25 +#define GC_FEATURES_MEM32_BIT_SUPPORT_End 25 +#define GC_FEATURES_MEM32_BIT_SUPPORT_Start 25 +#define GC_FEATURES_MEM32_BIT_SUPPORT_Type U01 +#define GC_FEATURES_MEM32_BIT_SUPPORT_NONE 0x0 +#define GC_FEATURES_MEM32_BIT_SUPPORT_AVAILABLE 0x1 + +/* VG pipe is present. */ +#define GC_FEATURES_PIPE_VG 26 : 26 +#define GC_FEATURES_PIPE_VG_End 26 +#define GC_FEATURES_PIPE_VG_Start 26 +#define GC_FEATURES_PIPE_VG_Type U01 +#define GC_FEATURES_PIPE_VG_NONE 0x0 +#define GC_FEATURES_PIPE_VG_AVAILABLE 0x1 + +/* VG tesselator is present. */ +#define GC_FEATURES_VGTS 27 : 27 +#define GC_FEATURES_VGTS_End 27 +#define GC_FEATURES_VGTS_Start 27 +#define GC_FEATURES_VGTS_Type U01 +#define GC_FEATURES_VGTS_NONE 0x0 +#define GC_FEATURES_VGTS_AVAILABLE 0x1 + +/* FE 2.0 is present. */ +#define GC_FEATURES_FE20 28 : 28 +#define GC_FEATURES_FE20_End 28 +#define GC_FEATURES_FE20_Start 28 +#define GC_FEATURES_FE20_Type U01 +#define GC_FEATURES_FE20_NONE 0x0 +#define GC_FEATURES_FE20_AVAILABLE 0x1 + +/* 3D PE has byte write capability. */ +#define GC_FEATURES_BYTE_WRITE_3D 29 : 29 +#define GC_FEATURES_BYTE_WRITE_3D_End 29 +#define GC_FEATURES_BYTE_WRITE_3D_Start 29 +#define GC_FEATURES_BYTE_WRITE_3D_Type U01 +#define GC_FEATURES_BYTE_WRITE_3D_NONE 0x0 +#define GC_FEATURES_BYTE_WRITE_3D_AVAILABLE 0x1 + +/* Supports resolveing into YUV target. */ +#define GC_FEATURES_RS_YUV_TARGET 30 : 30 +#define GC_FEATURES_RS_YUV_TARGET_End 30 +#define GC_FEATURES_RS_YUV_TARGET_Start 30 +#define GC_FEATURES_RS_YUV_TARGET_Type U01 +#define GC_FEATURES_RS_YUV_TARGET_NONE 0x0 +#define GC_FEATURES_RS_YUV_TARGET_AVAILABLE 0x1 + +/* Supports 20 bit index. */ +#define GC_FEATURES_FE20_BIT_INDEX 31 : 31 +#define GC_FEATURES_FE20_BIT_INDEX_End 31 +#define GC_FEATURES_FE20_BIT_INDEX_Start 31 +#define GC_FEATURES_FE20_BIT_INDEX_Type U01 +#define GC_FEATURES_FE20_BIT_INDEX_NONE 0x0 +#define GC_FEATURES_FE20_BIT_INDEX_AVAILABLE 0x1 + +/******************************************************************************* +** Register GCChipId +*/ + +/* Shows the ID for the chip in BCD. This register has no set reset value. +** It varies with the implementation. +*/ + +#define GC_CHIP_ID_Address 0x00020 +#define GC_CHIP_ID_MSB 15 +#define GC_CHIP_ID_LSB 0 +#define GC_CHIP_ID_BLK 0 +#define GC_CHIP_ID_Count 1 +#define GC_CHIP_ID_FieldMask 0xFFFFFFFF +#define GC_CHIP_ID_ReadMask 0xFFFFFFFF +#define GC_CHIP_ID_WriteMask 0x00000000 +#define GC_CHIP_ID_ResetValue 0x00000000 + +/* Id. */ +#define GC_CHIP_ID_ID 31 : 0 +#define GC_CHIP_ID_ID_End 31 +#define GC_CHIP_ID_ID_Start 0 +#define GC_CHIP_ID_ID_Type U32 + +/******************************************************************************* +** Register GCChipRev +*/ + +/* Shows the revision for the chip in BCD. This register has no set reset +** value. It varies with the implementation. +*/ + +#define GC_CHIP_REV_Address 0x00024 +#define GC_CHIP_REV_MSB 15 +#define GC_CHIP_REV_LSB 0 +#define GC_CHIP_REV_BLK 0 +#define GC_CHIP_REV_Count 1 +#define GC_CHIP_REV_FieldMask 0xFFFFFFFF +#define GC_CHIP_REV_ReadMask 0xFFFFFFFF +#define GC_CHIP_REV_WriteMask 0x00000000 +#define GC_CHIP_REV_ResetValue 0x00000000 + +/* Revision. */ +#define GC_CHIP_REV_REV 31 : 0 +#define GC_CHIP_REV_REV_End 31 +#define GC_CHIP_REV_REV_Start 0 +#define GC_CHIP_REV_REV_Type U32 + +/******************************************************************************* +** Register GCChipDate +*/ + +/* Shows the release date for the IP. This register has no set reset value. +** It varies with the implementation. +*/ + +#define GC_CHIP_DATE_Address 0x00028 +#define GC_CHIP_DATE_MSB 15 +#define GC_CHIP_DATE_LSB 0 +#define GC_CHIP_DATE_BLK 0 +#define GC_CHIP_DATE_Count 1 +#define GC_CHIP_DATE_FieldMask 0xFFFFFFFF +#define GC_CHIP_DATE_ReadMask 0xFFFFFFFF +#define GC_CHIP_DATE_WriteMask 0x00000000 +#define GC_CHIP_DATE_ResetValue 0x00000000 + +/* Date. */ +#define GC_CHIP_DATE_DATE 31 : 0 +#define GC_CHIP_DATE_DATE_End 31 +#define GC_CHIP_DATE_DATE_Start 0 +#define GC_CHIP_DATE_DATE_Type U32 + +/******************************************************************************* +** Register GCChipTime +*/ + +/* Shows the release time for the IP. This register has no set reset value. +** It varies with the implementation. +*/ + +#define GC_CHIP_TIME_Address 0x0002C +#define GC_CHIP_TIME_MSB 15 +#define GC_CHIP_TIME_LSB 0 +#define GC_CHIP_TIME_BLK 0 +#define GC_CHIP_TIME_Count 1 +#define GC_CHIP_TIME_FieldMask 0xFFFFFFFF +#define GC_CHIP_TIME_ReadMask 0xFFFFFFFF +#define GC_CHIP_TIME_WriteMask 0x00000000 +#define GC_CHIP_TIME_ResetValue 0x00000000 + +/* Time. */ +#define GC_CHIP_TIME_TIME 31 : 0 +#define GC_CHIP_TIME_TIME_End 31 +#define GC_CHIP_TIME_TIME_Start 0 +#define GC_CHIP_TIME_TIME_Type U32 + +/******************************************************************************* +** Register GCMinorFeatures0 +*/ + +/* Shows which minor features are enabled in this chip. This register has no +** set reset value. It varies with the implementation. +*/ + +#define GC_MINOR_FEATURES0_Address 0x00034 +#define GC_MINOR_FEATURES0_MSB 15 +#define GC_MINOR_FEATURES0_LSB 0 +#define GC_MINOR_FEATURES0_BLK 0 +#define GC_MINOR_FEATURES0_Count 1 +#define GC_MINOR_FEATURES0_FieldMask 0xFFFFFFFF +#define GC_MINOR_FEATURES0_ReadMask 0xFFFFFFFF +#define GC_MINOR_FEATURES0_WriteMask 0x00000000 +#define GC_MINOR_FEATURES0_ResetValue 0x00000000 + +/* Y flipping capability is added to resolve. */ +#define GC_MINOR_FEATURES0_FLIP_Y 0 : 0 +#define GC_MINOR_FEATURES0_FLIP_Y_End 0 +#define GC_MINOR_FEATURES0_FLIP_Y_Start 0 +#define GC_MINOR_FEATURES0_FLIP_Y_Type U01 +#define GC_MINOR_FEATURES0_FLIP_Y_NONE 0x0 +#define GC_MINOR_FEATURES0_FLIP_Y_AVAILABLE 0x1 + +/* Dual Return Bus from HI to clients. */ +#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS 1 : 1 +#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_End 1 +#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_Start 1 +#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_Type U01 +#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_NONE 0x0 +#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_AVAILABLE 0x1 + +/* Configurable endianness support. */ +#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG 2 : 2 +#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_End 2 +#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_Start 2 +#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_Type U01 +#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_NONE 0x0 +#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_AVAILABLE 0x1 + +/* Supports 8Kx8K textures. */ +#define GC_MINOR_FEATURES0_TEXTURE8_K 3 : 3 +#define GC_MINOR_FEATURES0_TEXTURE8_K_End 3 +#define GC_MINOR_FEATURES0_TEXTURE8_K_Start 3 +#define GC_MINOR_FEATURES0_TEXTURE8_K_Type U01 +#define GC_MINOR_FEATURES0_TEXTURE8_K_NONE 0x0 +#define GC_MINOR_FEATURES0_TEXTURE8_K_AVAILABLE 0x1 + +/* Driver hack is not needed. */ +#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER 4 : 4 +#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_End 4 +#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_Start 4 +#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_Type U01 +#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_NONE 0x0 +#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_AVAILABLE 0x1 + +/* Special LOD calculation when MSAA is on. */ +#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD 5 : 5 +#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_End 5 +#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_Start 5 +#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_Type U01 +#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_NONE 0x0 +#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_AVAILABLE 0x1 + +/* Proper flush is done in fast clear cache. */ +#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH 6 : 6 +#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_End 6 +#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_Start 6 +#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_Type U01 +#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_NONE 0x0 +#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_AVAILABLE 0x1 + +/* 2D PE 2.0 is present. */ +#define GC_MINOR_FEATURES0_2DPE20 7 : 7 +#define GC_MINOR_FEATURES0_2DPE20_End 7 +#define GC_MINOR_FEATURES0_2DPE20_Start 7 +#define GC_MINOR_FEATURES0_2DPE20_Type U01 +#define GC_MINOR_FEATURES0_2DPE20_NONE 0x0 +#define GC_MINOR_FEATURES0_2DPE20_AVAILABLE 0x1 + +/* Reserved. */ +#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE 8 : 8 +#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_End 8 +#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_Start 8 +#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_Type U01 +#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_NONE 0x0 +#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_AVAILABLE 0x1 + +/* Supports 8K render target. */ +#define GC_MINOR_FEATURES0_RENDER_8K 9 : 9 +#define GC_MINOR_FEATURES0_RENDER_8K_End 9 +#define GC_MINOR_FEATURES0_RENDER_8K_Start 9 +#define GC_MINOR_FEATURES0_RENDER_8K_Type U01 +#define GC_MINOR_FEATURES0_RENDER_8K_NONE 0x0 +#define GC_MINOR_FEATURES0_RENDER_8K_AVAILABLE 0x1 + +/* 2 bits are used instead of 4 bits for tile status. */ +#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS 10 : 10 +#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_End 10 +#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_Start 10 +#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_Type U01 +#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_NONE 0x0 +#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_AVAILABLE 0x1 + +/* Use 2 separate tile status buffers in interleaved mode. */ +#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED 11 : 11 +#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_End 11 +#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_Start 11 +#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_Type U01 +#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_NONE 0x0 +#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_AVAILABLE 0x1 + +/* 32x32 super tile is available. */ +#define GC_MINOR_FEATURES0_SUPER_TILED_32X32 12 : 12 +#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_End 12 +#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_Start 12 +#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_Type U01 +#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_NONE 0x0 +#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_AVAILABLE 0x1 + +/* Major updates to VG pipe (TS buffer tiling. State masking.). */ +#define GC_MINOR_FEATURES0_VG_20 13 : 13 +#define GC_MINOR_FEATURES0_VG_20_End 13 +#define GC_MINOR_FEATURES0_VG_20_Start 13 +#define GC_MINOR_FEATURES0_VG_20_Type U01 +#define GC_MINOR_FEATURES0_VG_20_NONE 0x0 +#define GC_MINOR_FEATURES0_VG_20_AVAILABLE 0x1 + +/* New commands added to the tessellator. */ +#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS 14 : 14 +#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_End 14 +#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_Start 14 +#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_Type U01 +#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_NONE 0x0 +#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_AVAILABLE 0x1 + +/* If this bit is not set, the FIFO counter should be set to 50. Else, the ** +** default should remain. */ +#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED 15 : 15 +#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_End 15 +#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_Start 15 +#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_Type U01 +#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_NONE 0x0 +#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_AVAILABLE 0x1 + +/* Floor, ceil, and sign instructions are available. */ +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0 16 : 16 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_End 16 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_Start 16 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_Type U01 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_NONE 0x0 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_AVAILABLE 0x1 + +/* VG filter is available. */ +#define GC_MINOR_FEATURES0_VG_FILTER 17 : 17 +#define GC_MINOR_FEATURES0_VG_FILTER_End 17 +#define GC_MINOR_FEATURES0_VG_FILTER_Start 17 +#define GC_MINOR_FEATURES0_VG_FILTER_Type U01 +#define GC_MINOR_FEATURES0_VG_FILTER_NONE 0x0 +#define GC_MINOR_FEATURES0_VG_FILTER_AVAILABLE 0x1 + +/* Minor updates to VG pipe (Event generation from VG, TS, PE). Tiled image ** +** support. */ +#define GC_MINOR_FEATURES0_VG_21 18 : 18 +#define GC_MINOR_FEATURES0_VG_21_End 18 +#define GC_MINOR_FEATURES0_VG_21_Start 18 +#define GC_MINOR_FEATURES0_VG_21_Type U01 +#define GC_MINOR_FEATURES0_VG_21_NONE 0x0 +#define GC_MINOR_FEATURES0_VG_21_AVAILABLE 0x1 + +/* W is sent to SH from RA. */ +#define GC_MINOR_FEATURES0_SHADER_GETS_W 19 : 19 +#define GC_MINOR_FEATURES0_SHADER_GETS_W_End 19 +#define GC_MINOR_FEATURES0_SHADER_GETS_W_Start 19 +#define GC_MINOR_FEATURES0_SHADER_GETS_W_Type U01 +#define GC_MINOR_FEATURES0_SHADER_GETS_W_NONE 0x0 +#define GC_MINOR_FEATURES0_SHADER_GETS_W_AVAILABLE 0x1 + +/* Sqrt, sin, cos instructions are available. */ +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1 20 : 20 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_End 20 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_Start 20 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_Type U01 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_NONE 0x0 +#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_AVAILABLE 0x1 + +/* Unavailable registers will return 0. */ +#define GC_MINOR_FEATURES0_DEFAULT_REG0 21 : 21 +#define GC_MINOR_FEATURES0_DEFAULT_REG0_End 21 +#define GC_MINOR_FEATURES0_DEFAULT_REG0_Start 21 +#define GC_MINOR_FEATURES0_DEFAULT_REG0_Type U01 +#define GC_MINOR_FEATURES0_DEFAULT_REG0_NONE 0x0 +#define GC_MINOR_FEATURES0_DEFAULT_REG0_AVAILABLE 0x1 + +/* New style MC with separate paths for color and depth. */ +#define GC_MINOR_FEATURES0_MC_20 22 : 22 +#define GC_MINOR_FEATURES0_MC_20_End 22 +#define GC_MINOR_FEATURES0_MC_20_Start 22 +#define GC_MINOR_FEATURES0_MC_20_Type U01 +#define GC_MINOR_FEATURES0_MC_20_NONE 0x0 +#define GC_MINOR_FEATURES0_MC_20_AVAILABLE 0x1 + +/* Put the MSAA data into sideband fifo. */ +#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND 23 : 23 +#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_End 23 +#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_Start 23 +#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_Type U01 +#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_NONE 0x0 +#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES0_BUG_FIXES0 24 : 24 +#define GC_MINOR_FEATURES0_BUG_FIXES0_End 24 +#define GC_MINOR_FEATURES0_BUG_FIXES0_Start 24 +#define GC_MINOR_FEATURES0_BUG_FIXES0_Type U01 +#define GC_MINOR_FEATURES0_BUG_FIXES0_NONE 0x0 +#define GC_MINOR_FEATURES0_BUG_FIXES0_AVAILABLE 0x1 + +/* VAA is available or not. */ +#define GC_MINOR_FEATURES0_VAA 25 : 25 +#define GC_MINOR_FEATURES0_VAA_End 25 +#define GC_MINOR_FEATURES0_VAA_Start 25 +#define GC_MINOR_FEATURES0_VAA_Type U01 +#define GC_MINOR_FEATURES0_VAA_NONE 0x0 +#define GC_MINOR_FEATURES0_VAA_AVAILABLE 0x1 + +/* Shader supports bypass mode when MSAA is enabled. */ +#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA 26 : 26 +#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_End 26 +#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_Start 26 +#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_Type U01 +#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_NONE 0x0 +#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_AVAILABLE 0x1 + +/* Hierarchiccal Z is supported. */ +#define GC_MINOR_FEATURES0_HIERARCHICAL_Z 27 : 27 +#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_End 27 +#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_Start 27 +#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_Type U01 +#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_NONE 0x0 +#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_AVAILABLE 0x1 + +/* New texture unit is available. */ +#define GC_MINOR_FEATURES0_NEW_TEXTURE 28 : 28 +#define GC_MINOR_FEATURES0_NEW_TEXTURE_End 28 +#define GC_MINOR_FEATURES0_NEW_TEXTURE_Start 28 +#define GC_MINOR_FEATURES0_NEW_TEXTURE_Type U01 +#define GC_MINOR_FEATURES0_NEW_TEXTURE_NONE 0x0 +#define GC_MINOR_FEATURES0_NEW_TEXTURE_AVAILABLE 0x1 + +/* 2D engine supports A8 target. */ +#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT 29 : 29 +#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_End 29 +#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_Start 29 +#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_Type U01 +#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_NONE 0x0 +#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_AVAILABLE 0x1 + +/* Correct stencil behavior in depth only. */ +#define GC_MINOR_FEATURES0_CORRECT_STENCIL 30 : 30 +#define GC_MINOR_FEATURES0_CORRECT_STENCIL_End 30 +#define GC_MINOR_FEATURES0_CORRECT_STENCIL_Start 30 +#define GC_MINOR_FEATURES0_CORRECT_STENCIL_Type U01 +#define GC_MINOR_FEATURES0_CORRECT_STENCIL_NONE 0x0 +#define GC_MINOR_FEATURES0_CORRECT_STENCIL_AVAILABLE 0x1 + +/* Enhance VR and add a mode to walk 16 pixels in 16-bit mode in Vertical ** +** pass to improve $ hit rate when rotating 90/270. */ +#define GC_MINOR_FEATURES0_ENHANCE_VR 31 : 31 +#define GC_MINOR_FEATURES0_ENHANCE_VR_End 31 +#define GC_MINOR_FEATURES0_ENHANCE_VR_Start 31 +#define GC_MINOR_FEATURES0_ENHANCE_VR_Type U01 +#define GC_MINOR_FEATURES0_ENHANCE_VR_NONE 0x0 +#define GC_MINOR_FEATURES0_ENHANCE_VR_AVAILABLE 0x1 + +/******************************************************************************* +** Register GCMinorFeatures1 +*/ + +/* Shows which features are enabled in this chip. This register has no set +** reset value. It varies with the implementation. +*/ + +#define GC_MINOR_FEATURES1_Address 0x00074 +#define GC_MINOR_FEATURES1_MSB 15 +#define GC_MINOR_FEATURES1_LSB 0 +#define GC_MINOR_FEATURES1_BLK 0 +#define GC_MINOR_FEATURES1_Count 1 +#define GC_MINOR_FEATURES1_FieldMask 0xFFFFFFFF +#define GC_MINOR_FEATURES1_ReadMask 0xFFFFFFFF +#define GC_MINOR_FEATURES1_WriteMask 0x00000000 +#define GC_MINOR_FEATURES1_ResetValue 0x00000000 + +/* Resolve UV swizzle. */ +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE 0 : 0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_End 0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_Start 0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_Type U01 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_NONE 0x0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_AVAILABLE 0x1 + +/* V2 compression. */ +#define GC_MINOR_FEATURES1_V2_COMPRESSION 1 : 1 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_End 1 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_Start 1 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_Type U01 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_NONE 0x0 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_AVAILABLE 0x1 + +/* Double buffering support for VG (second TS-->VG semaphore is present). */ +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER 2 : 2 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_End 2 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_Start 2 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_Type U01 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_NONE 0x0 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES1 3 : 3 +#define GC_MINOR_FEATURES1_BUG_FIXES1_End 3 +#define GC_MINOR_FEATURES1_BUG_FIXES1_Start 3 +#define GC_MINOR_FEATURES1_BUG_FIXES1_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES1_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES1_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES2 4 : 4 +#define GC_MINOR_FEATURES1_BUG_FIXES2_End 4 +#define GC_MINOR_FEATURES1_BUG_FIXES2_Start 4 +#define GC_MINOR_FEATURES1_BUG_FIXES2_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES2_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES2_AVAILABLE 0x1 + +/* Texture has stride and memory addressing. */ +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE 5 : 5 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_End 5 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_Start 5 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_Type U01 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_NONE 0x0 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES3 6 : 6 +#define GC_MINOR_FEATURES1_BUG_FIXES3_End 6 +#define GC_MINOR_FEATURES1_BUG_FIXES3_Start 6 +#define GC_MINOR_FEATURES1_BUG_FIXES3_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES3_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES3_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE 7 : 7 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_End 7 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_Start 7 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_Type U01 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_NONE 0x0 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS 8 : 8 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_End 8 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_Start 8 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_Type U01 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_NONE 0x0 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES4 9 : 9 +#define GC_MINOR_FEATURES1_BUG_FIXES4_End 9 +#define GC_MINOR_FEATURES1_BUG_FIXES4_Start 9 +#define GC_MINOR_FEATURES1_BUG_FIXES4_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES4_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES4_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_L2_WINDOWING 10 : 10 +#define GC_MINOR_FEATURES1_L2_WINDOWING_End 10 +#define GC_MINOR_FEATURES1_L2_WINDOWING_Start 10 +#define GC_MINOR_FEATURES1_L2_WINDOWING_Type U01 +#define GC_MINOR_FEATURES1_L2_WINDOWING_NONE 0x0 +#define GC_MINOR_FEATURES1_L2_WINDOWING_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE 11 : 11 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_End 11 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_Start 11 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_Type U01 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_NONE 0x0 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_PIXEL_DITHER 12 : 12 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_End 12 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_Start 12 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_Type U01 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_NONE 0x0 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE 13 : 13 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_End 13 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_Start 13 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_Type U01 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_NONE 0x0 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT 14 : 14 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_End 14 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_Start 14 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_Type U01 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_NONE 0x0 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_AVAILABLE 0x1 + +/* EEZ and HZ are correct. */ +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH 15 : 15 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_End 15 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_Start 15 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_Type U01 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_NONE 0x0 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_AVAILABLE 0x1 + +/* Dither and filter+alpha available. */ +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D 16 : 16 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_End 16 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_Start 16 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_Type U01 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_NONE 0x0 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES5 17 : 17 +#define GC_MINOR_FEATURES1_BUG_FIXES5_End 17 +#define GC_MINOR_FEATURES1_BUG_FIXES5_Start 17 +#define GC_MINOR_FEATURES1_BUG_FIXES5_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES5_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES5_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NEW_2D 18 : 18 +#define GC_MINOR_FEATURES1_NEW_2D_End 18 +#define GC_MINOR_FEATURES1_NEW_2D_Start 18 +#define GC_MINOR_FEATURES1_NEW_2D_Type U01 +#define GC_MINOR_FEATURES1_NEW_2D_NONE 0x0 +#define GC_MINOR_FEATURES1_NEW_2D_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC 19 : 19 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_End 19 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_Start 19 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_Type U01 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_NONE 0x0 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT 20 : 20 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_End 20 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_Start 20 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_Type U01 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_NONE 0x0 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO 21 : 21 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_End 21 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_Start 21 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_Type U01 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_NONE 0x0 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT 22 : 22 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_End 22 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_Start 22 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_Type U01 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_NONE 0x0 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_HALTI0 23 : 23 +#define GC_MINOR_FEATURES1_HALTI0_End 23 +#define GC_MINOR_FEATURES1_HALTI0_Start 23 +#define GC_MINOR_FEATURES1_HALTI0_Type U01 +#define GC_MINOR_FEATURES1_HALTI0_NONE 0x0 +#define GC_MINOR_FEATURES1_HALTI0_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG 24 : 24 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_End 24 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_Start 24 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_Type U01 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_NONE 0x0 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX 25 : 25 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_End 25 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_Start 25 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_Type U01 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_NONE 0x0 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET 26 : 26 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_End 26 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_Start 26 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_Type U01 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_NONE 0x0 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK 27 : 27 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_End 27 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_Start 27 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_Type U01 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_NONE 0x0 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_MMU 28 : 28 +#define GC_MINOR_FEATURES1_MMU_End 28 +#define GC_MINOR_FEATURES1_MMU_Start 28 +#define GC_MINOR_FEATURES1_MMU_Type U01 +#define GC_MINOR_FEATURES1_MMU_NONE 0x0 +#define GC_MINOR_FEATURES1_MMU_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_WIDE_LINE 29 : 29 +#define GC_MINOR_FEATURES1_WIDE_LINE_End 29 +#define GC_MINOR_FEATURES1_WIDE_LINE_Start 29 +#define GC_MINOR_FEATURES1_WIDE_LINE_Type U01 +#define GC_MINOR_FEATURES1_WIDE_LINE_NONE 0x0 +#define GC_MINOR_FEATURES1_WIDE_LINE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES6 30 : 30 +#define GC_MINOR_FEATURES1_BUG_FIXES6_End 30 +#define GC_MINOR_FEATURES1_BUG_FIXES6_Start 30 +#define GC_MINOR_FEATURES1_BUG_FIXES6_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES6_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES6_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL 31 : 31 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_End 31 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_Start 31 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_Type U01 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_NONE 0x0 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_AVAILABLE 0x1 + +/******************************************************************************* +** Register GCResetMemCounters +*/ + +/* Writing 1 will reset the counters and stop counting. Write 0 to start +** counting again. This register is write only so it has no reset value. +*/ + +#define GC_RESET_MEM_COUNTERS_Address 0x0003C +#define GC_RESET_MEM_COUNTERS_MSB 15 +#define GC_RESET_MEM_COUNTERS_LSB 0 +#define GC_RESET_MEM_COUNTERS_BLK 0 +#define GC_RESET_MEM_COUNTERS_Count 1 +#define GC_RESET_MEM_COUNTERS_FieldMask 0x00000001 +#define GC_RESET_MEM_COUNTERS_ReadMask 0x00000000 +#define GC_RESET_MEM_COUNTERS_WriteMask 0x00000001 +#define GC_RESET_MEM_COUNTERS_ResetValue 0x00000000 + +#define GC_RESET_MEM_COUNTERS_RESET 0 : 0 +#define GC_RESET_MEM_COUNTERS_RESET_End 0 +#define GC_RESET_MEM_COUNTERS_RESET_Start 0 +#define GC_RESET_MEM_COUNTERS_RESET_Type U01 + +/******************************************************************************* +** Register gcTotalReads +*/ + +/* Total reads in terms of 64bits. */ + +#define GC_TOTAL_READS_Address 0x00040 +#define GC_TOTAL_READS_MSB 15 +#define GC_TOTAL_READS_LSB 0 +#define GC_TOTAL_READS_BLK 0 +#define GC_TOTAL_READS_Count 1 +#define GC_TOTAL_READS_FieldMask 0xFFFFFFFF +#define GC_TOTAL_READS_ReadMask 0xFFFFFFFF +#define GC_TOTAL_READS_WriteMask 0x00000000 +#define GC_TOTAL_READS_ResetValue 0x00000000 + +#define GC_TOTAL_READS_COUNT 31 : 0 +#define GC_TOTAL_READS_COUNT_End 31 +#define GC_TOTAL_READS_COUNT_Start 0 +#define GC_TOTAL_READS_COUNT_Type U32 + +/******************************************************************************* +** Register gcTotalWrites +*/ + +/* Total writes in terms of 64bits. */ + +#define GC_TOTAL_WRITES_Address 0x00044 +#define GC_TOTAL_WRITES_MSB 15 +#define GC_TOTAL_WRITES_LSB 0 +#define GC_TOTAL_WRITES_BLK 0 +#define GC_TOTAL_WRITES_Count 1 +#define GC_TOTAL_WRITES_FieldMask 0xFFFFFFFF +#define GC_TOTAL_WRITES_ReadMask 0xFFFFFFFF +#define GC_TOTAL_WRITES_WriteMask 0x00000000 +#define GC_TOTAL_WRITES_ResetValue 0x00000000 + +#define GC_TOTAL_WRITES_COUNT 31 : 0 +#define GC_TOTAL_WRITES_COUNT_End 31 +#define GC_TOTAL_WRITES_COUNT_Start 0 +#define GC_TOTAL_WRITES_COUNT_Type U32 + +/******************************************************************************* +** Register gcTotalWriteBursts +*/ + +/* Total write Data Count in terms of 64bits value. */ + +#define GC_TOTAL_WRITE_BURSTS_Address 0x0004C +#define GC_TOTAL_WRITE_BURSTS_MSB 15 +#define GC_TOTAL_WRITE_BURSTS_LSB 0 +#define GC_TOTAL_WRITE_BURSTS_BLK 0 +#define GC_TOTAL_WRITE_BURSTS_Count 1 +#define GC_TOTAL_WRITE_BURSTS_FieldMask 0xFFFFFFFF +#define GC_TOTAL_WRITE_BURSTS_ReadMask 0xFFFFFFFF +#define GC_TOTAL_WRITE_BURSTS_WriteMask 0x00000000 +#define GC_TOTAL_WRITE_BURSTS_ResetValue 0x00000000 + +#define GC_TOTAL_WRITE_BURSTS_COUNT 31 : 0 +#define GC_TOTAL_WRITE_BURSTS_COUNT_End 31 +#define GC_TOTAL_WRITE_BURSTS_COUNT_Start 0 +#define GC_TOTAL_WRITE_BURSTS_COUNT_Type U32 + +/******************************************************************************* +** Register gcTotalWriteReqs +*/ + +/* Total write Request Count. */ + +#define GC_TOTAL_WRITE_REQS_Address 0x00050 +#define GC_TOTAL_WRITE_REQS_MSB 15 +#define GC_TOTAL_WRITE_REQS_LSB 0 +#define GC_TOTAL_WRITE_REQS_BLK 0 +#define GC_TOTAL_WRITE_REQS_Count 1 +#define GC_TOTAL_WRITE_REQS_FieldMask 0xFFFFFFFF +#define GC_TOTAL_WRITE_REQS_ReadMask 0xFFFFFFFF +#define GC_TOTAL_WRITE_REQS_WriteMask 0x00000000 +#define GC_TOTAL_WRITE_REQS_ResetValue 0x00000000 + +#define GC_TOTAL_WRITE_REQS_COUNT 31 : 0 +#define GC_TOTAL_WRITE_REQS_COUNT_End 31 +#define GC_TOTAL_WRITE_REQS_COUNT_Start 0 +#define GC_TOTAL_WRITE_REQS_COUNT_Type U32 + +/******************************************************************************* +** Register gcTotalReadBursts +*/ + +/* Total Read Data Count in terms of 64bits. */ + +#define GC_TOTAL_READ_BURSTS_Address 0x00058 +#define GC_TOTAL_READ_BURSTS_MSB 15 +#define GC_TOTAL_READ_BURSTS_LSB 0 +#define GC_TOTAL_READ_BURSTS_BLK 0 +#define GC_TOTAL_READ_BURSTS_Count 1 +#define GC_TOTAL_READ_BURSTS_FieldMask 0xFFFFFFFF +#define GC_TOTAL_READ_BURSTS_ReadMask 0xFFFFFFFF +#define GC_TOTAL_READ_BURSTS_WriteMask 0x00000000 +#define GC_TOTAL_READ_BURSTS_ResetValue 0x00000000 + +#define GC_TOTAL_READ_BURSTS_COUNT 31 : 0 +#define GC_TOTAL_READ_BURSTS_COUNT_End 31 +#define GC_TOTAL_READ_BURSTS_COUNT_Start 0 +#define GC_TOTAL_READ_BURSTS_COUNT_Type U32 + +/******************************************************************************* +** Register gcTotalReadReqs +*/ + +/* Total Read Request Count. */ + +#define GC_TOTAL_READ_REQS_Address 0x0005C +#define GC_TOTAL_READ_REQS_MSB 15 +#define GC_TOTAL_READ_REQS_LSB 0 +#define GC_TOTAL_READ_REQS_BLK 0 +#define GC_TOTAL_READ_REQS_Count 1 +#define GC_TOTAL_READ_REQS_FieldMask 0xFFFFFFFF +#define GC_TOTAL_READ_REQS_ReadMask 0xFFFFFFFF +#define GC_TOTAL_READ_REQS_WriteMask 0x00000000 +#define GC_TOTAL_READ_REQS_ResetValue 0x00000000 + +#define GC_TOTAL_READ_REQS_COUNT 31 : 0 +#define GC_TOTAL_READ_REQS_COUNT_End 31 +#define GC_TOTAL_READ_REQS_COUNT_Start 0 +#define GC_TOTAL_READ_REQS_COUNT_Type U32 + +/******************************************************************************* +** Register gcTotalReadLasts +*/ + +/* Total RLAST Count. This is used to match with GCTotalReadReqs. */ + +#define GC_TOTAL_READ_LASTS_Address 0x00060 +#define GC_TOTAL_READ_LASTS_MSB 15 +#define GC_TOTAL_READ_LASTS_LSB 0 +#define GC_TOTAL_READ_LASTS_BLK 0 +#define GC_TOTAL_READ_LASTS_Count 1 +#define GC_TOTAL_READ_LASTS_FieldMask 0xFFFFFFFF +#define GC_TOTAL_READ_LASTS_ReadMask 0xFFFFFFFF +#define GC_TOTAL_READ_LASTS_WriteMask 0x00000000 +#define GC_TOTAL_READ_LASTS_ResetValue 0x00000000 + +#define GC_TOTAL_READ_LASTS_COUNT 31 : 0 +#define GC_TOTAL_READ_LASTS_COUNT_End 31 +#define GC_TOTAL_READ_LASTS_COUNT_Start 0 +#define GC_TOTAL_READ_LASTS_COUNT_Type U32 + +/******************************************************************************* +** Register gcGpOut0 +*/ + +/* General Purpose output register0. R/W but not connected to anywhere. */ + +#define GC_GP_OUT0_Address 0x00064 +#define GC_GP_OUT0_MSB 15 +#define GC_GP_OUT0_LSB 0 +#define GC_GP_OUT0_BLK 0 +#define GC_GP_OUT0_Count 1 +#define GC_GP_OUT0_FieldMask 0xFFFFFFFF +#define GC_GP_OUT0_ReadMask 0xFFFFFFFF +#define GC_GP_OUT0_WriteMask 0xFFFFFFFF +#define GC_GP_OUT0_ResetValue 0x00000000 + +#define GC_GP_OUT0_COUNT 31 : 0 +#define GC_GP_OUT0_COUNT_End 31 +#define GC_GP_OUT0_COUNT_Start 0 +#define GC_GP_OUT0_COUNT_Type U32 + +/******************************************************************************* +** Register gcGpOut1 +*/ + +/* General Purpose output register1. R/W but not connected to anywhere. */ + +#define GC_GP_OUT1_Address 0x00068 +#define GC_GP_OUT1_MSB 15 +#define GC_GP_OUT1_LSB 0 +#define GC_GP_OUT1_BLK 0 +#define GC_GP_OUT1_Count 1 +#define GC_GP_OUT1_FieldMask 0xFFFFFFFF +#define GC_GP_OUT1_ReadMask 0xFFFFFFFF +#define GC_GP_OUT1_WriteMask 0xFFFFFFFF +#define GC_GP_OUT1_ResetValue 0x00000000 + +#define GC_GP_OUT1_COUNT 31 : 0 +#define GC_GP_OUT1_COUNT_End 31 +#define GC_GP_OUT1_COUNT_Start 0 +#define GC_GP_OUT1_COUNT_Type U32 + +/******************************************************************************* +** Register gcGpOut2 +*/ + +/* General Purpose output register2. R/W but not connected to anywhere. */ + +#define GC_GP_OUT2_Address 0x0006C +#define GC_GP_OUT2_MSB 15 +#define GC_GP_OUT2_LSB 0 +#define GC_GP_OUT2_BLK 0 +#define GC_GP_OUT2_Count 1 +#define GC_GP_OUT2_FieldMask 0xFFFFFFFF +#define GC_GP_OUT2_ReadMask 0xFFFFFFFF +#define GC_GP_OUT2_WriteMask 0xFFFFFFFF +#define GC_GP_OUT2_ResetValue 0x00000000 + +#define GC_GP_OUT2_COUNT 31 : 0 +#define GC_GP_OUT2_COUNT_End 31 +#define GC_GP_OUT2_COUNT_Start 0 +#define GC_GP_OUT2_COUNT_Type U32 + +/******************************************************************************* +** Register gcAxiControl +*/ + +/* Special Handling on AXI Bus */ + +#define GC_AXI_CONTROL_Address 0x00070 +#define GC_AXI_CONTROL_MSB 15 +#define GC_AXI_CONTROL_LSB 0 +#define GC_AXI_CONTROL_BLK 0 +#define GC_AXI_CONTROL_Count 1 +#define GC_AXI_CONTROL_FieldMask 0x00000001 +#define GC_AXI_CONTROL_ReadMask 0x00000001 +#define GC_AXI_CONTROL_WriteMask 0x00000001 +#define GC_AXI_CONTROL_ResetValue 0x00000000 + +#define GC_AXI_CONTROL_WR_FULL_BURST_MODE 0 : 0 +#define GC_AXI_CONTROL_WR_FULL_BURST_MODE_End 0 +#define GC_AXI_CONTROL_WR_FULL_BURST_MODE_Start 0 +#define GC_AXI_CONTROL_WR_FULL_BURST_MODE_Type U01 +#define GC_AXI_CONTROL_WR_FULL_BURST_MODE_NO_BURST_RESET_VALUE 0x0 +#define GC_AXI_CONTROL_WR_FULL_BURST_MODE_BURST_RESET_VALUE 0x1 + +/******************************************************************************* +** Register GCMinorFeatures1 +*/ + +/* Shows which features are enabled in this chip. This register has no set + reset value. It varies with the implementation. */ + +#define GC_MINOR_FEATURES1_Address 0x00074 +#define GC_MINOR_FEATURES1_MSB 15 +#define GC_MINOR_FEATURES1_LSB 0 +#define GC_MINOR_FEATURES1_BLK 0 +#define GC_MINOR_FEATURES1_Count 1 +#define GC_MINOR_FEATURES1_FieldMask 0xFFFFFFFF +#define GC_MINOR_FEATURES1_ReadMask 0xFFFFFFFF +#define GC_MINOR_FEATURES1_WriteMask 0x00000000 +#define GC_MINOR_FEATURES1_ResetValue 0x00000000 + +/* Resolve UV swizzle. */ +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE 0 : 0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_End 0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_Start 0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_Type U01 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_NONE 0x0 +#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_AVAILABLE 0x1 + +/* V2 compression. */ +#define GC_MINOR_FEATURES1_V2_COMPRESSION 1 : 1 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_End 1 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_Start 1 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_Type U01 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_NONE 0x0 +#define GC_MINOR_FEATURES1_V2_COMPRESSION_AVAILABLE 0x1 + +/* Double buffering support for VG (second TS-->VG semaphore is present). */ +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER 2 : 2 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_End 2 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_Start 2 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_Type U01 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_NONE 0x0 +#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES1 3 : 3 +#define GC_MINOR_FEATURES1_BUG_FIXES1_End 3 +#define GC_MINOR_FEATURES1_BUG_FIXES1_Start 3 +#define GC_MINOR_FEATURES1_BUG_FIXES1_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES1_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES1_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES2 4 : 4 +#define GC_MINOR_FEATURES1_BUG_FIXES2_End 4 +#define GC_MINOR_FEATURES1_BUG_FIXES2_Start 4 +#define GC_MINOR_FEATURES1_BUG_FIXES2_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES2_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES2_AVAILABLE 0x1 + +/* Texture has stride and memory addressing. */ +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE 5 : 5 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_End 5 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_Start 5 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_Type U01 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_NONE 0x0 +#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES3 6 : 6 +#define GC_MINOR_FEATURES1_BUG_FIXES3_End 6 +#define GC_MINOR_FEATURES1_BUG_FIXES3_Start 6 +#define GC_MINOR_FEATURES1_BUG_FIXES3_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES3_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES3_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE 7 : 7 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_End 7 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_Start 7 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_Type U01 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_NONE 0x0 +#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS 8 : 8 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_End 8 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_Start 8 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_Type U01 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_NONE 0x0 +#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES4 9 : 9 +#define GC_MINOR_FEATURES1_BUG_FIXES4_End 9 +#define GC_MINOR_FEATURES1_BUG_FIXES4_Start 9 +#define GC_MINOR_FEATURES1_BUG_FIXES4_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES4_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES4_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_L2_WINDOWING 10 : 10 +#define GC_MINOR_FEATURES1_L2_WINDOWING_End 10 +#define GC_MINOR_FEATURES1_L2_WINDOWING_Start 10 +#define GC_MINOR_FEATURES1_L2_WINDOWING_Type U01 +#define GC_MINOR_FEATURES1_L2_WINDOWING_NONE 0x0 +#define GC_MINOR_FEATURES1_L2_WINDOWING_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE 11 : 11 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_End 11 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_Start 11 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_Type U01 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_NONE 0x0 +#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_PIXEL_DITHER 12 : 12 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_End 12 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_Start 12 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_Type U01 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_NONE 0x0 +#define GC_MINOR_FEATURES1_PIXEL_DITHER_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE 13 : 13 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_End 13 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_Start 13 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_Type U01 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_NONE 0x0 +#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT 14 : 14 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_End 14 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_Start 14 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_Type U01 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_NONE 0x0 +#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_AVAILABLE 0x1 + +/* EEZ and HZ are correct. */ +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH 15 : 15 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_End 15 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_Start 15 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_Type U01 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_NONE 0x0 +#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_AVAILABLE 0x1 + +/* Dither and filter+alpha available. */ +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D 16 : 16 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_End 16 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_Start 16 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_Type U01 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_NONE 0x0 +#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES5 17 : 17 +#define GC_MINOR_FEATURES1_BUG_FIXES5_End 17 +#define GC_MINOR_FEATURES1_BUG_FIXES5_Start 17 +#define GC_MINOR_FEATURES1_BUG_FIXES5_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES5_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES5_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NEW_2D 18 : 18 +#define GC_MINOR_FEATURES1_NEW_2D_End 18 +#define GC_MINOR_FEATURES1_NEW_2D_Start 18 +#define GC_MINOR_FEATURES1_NEW_2D_Type U01 +#define GC_MINOR_FEATURES1_NEW_2D_NONE 0x0 +#define GC_MINOR_FEATURES1_NEW_2D_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC 19 : 19 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_End 19 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_Start 19 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_Type U01 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_NONE 0x0 +#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT 20 : 20 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_End 20 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_Start 20 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_Type U01 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_NONE 0x0 +#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO 21 : 21 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_End 21 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_Start 21 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_Type U01 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_NONE 0x0 +#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT 22 : 22 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_End 22 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_Start 22 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_Type U01 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_NONE 0x0 +#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_HALTI0 23 : 23 +#define GC_MINOR_FEATURES1_HALTI0_End 23 +#define GC_MINOR_FEATURES1_HALTI0_Start 23 +#define GC_MINOR_FEATURES1_HALTI0_Type U01 +#define GC_MINOR_FEATURES1_HALTI0_NONE 0x0 +#define GC_MINOR_FEATURES1_HALTI0_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG 24 : 24 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_End 24 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_Start 24 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_Type U01 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_NONE 0x0 +#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX 25 : 25 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_End 25 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_Start 25 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_Type U01 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_NONE 0x0 +#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET 26 : 26 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_End 26 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_Start 26 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_Type U01 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_NONE 0x0 +#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK 27 : 27 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_End 27 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_Start 27 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_Type U01 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_NONE 0x0 +#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_MMU 28 : 28 +#define GC_MINOR_FEATURES1_MMU_End 28 +#define GC_MINOR_FEATURES1_MMU_Start 28 +#define GC_MINOR_FEATURES1_MMU_Type U01 +#define GC_MINOR_FEATURES1_MMU_NONE 0x0 +#define GC_MINOR_FEATURES1_MMU_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_WIDE_LINE 29 : 29 +#define GC_MINOR_FEATURES1_WIDE_LINE_End 29 +#define GC_MINOR_FEATURES1_WIDE_LINE_Start 29 +#define GC_MINOR_FEATURES1_WIDE_LINE_Type U01 +#define GC_MINOR_FEATURES1_WIDE_LINE_NONE 0x0 +#define GC_MINOR_FEATURES1_WIDE_LINE_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_BUG_FIXES6 30 : 30 +#define GC_MINOR_FEATURES1_BUG_FIXES6_End 30 +#define GC_MINOR_FEATURES1_BUG_FIXES6_Start 30 +#define GC_MINOR_FEATURES1_BUG_FIXES6_Type U01 +#define GC_MINOR_FEATURES1_BUG_FIXES6_NONE 0x0 +#define GC_MINOR_FEATURES1_BUG_FIXES6_AVAILABLE 0x1 + +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL 31 : 31 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_End 31 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_Start 31 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_Type U01 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_NONE 0x0 +#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_AVAILABLE 0x1 + +/******************************************************************************* +** Register gcTotalCycles +*/ + +/* Total cycles. This register is a free running counter. It can be reset by +** writing 0 to it. +*/ + +#define GC_TOTAL_CYCLES_Address 0x00078 +#define GC_TOTAL_CYCLES_MSB 15 +#define GC_TOTAL_CYCLES_LSB 0 +#define GC_TOTAL_CYCLES_BLK 0 +#define GC_TOTAL_CYCLES_Count 1 +#define GC_TOTAL_CYCLES_FieldMask 0xFFFFFFFF +#define GC_TOTAL_CYCLES_ReadMask 0xFFFFFFFF +#define GC_TOTAL_CYCLES_WriteMask 0xFFFFFFFF +#define GC_TOTAL_CYCLES_ResetValue 0x00000000 + +#define GC_TOTAL_CYCLES_CYCLES 31 : 0 +#define GC_TOTAL_CYCLES_CYCLES_End 31 +#define GC_TOTAL_CYCLES_CYCLES_Start 0 +#define GC_TOTAL_CYCLES_CYCLES_Type U32 + +/******************************************************************************* +** Register gcTotalIdleCycles +*/ + +/* Total cycles where the GPU is idle. It is reset when gcTotalCycles register +** is written to. It looks at all the blocks but FE when determining the IP is +** idle. +*/ + +#define GC_TOTAL_IDLE_CYCLES_Address 0x0007C +#define GC_TOTAL_IDLE_CYCLES_MSB 15 +#define GC_TOTAL_IDLE_CYCLES_LSB 0 +#define GC_TOTAL_IDLE_CYCLES_BLK 0 +#define GC_TOTAL_IDLE_CYCLES_Count 1 +#define GC_TOTAL_IDLE_CYCLES_FieldMask 0xFFFFFFFF +#define GC_TOTAL_IDLE_CYCLES_ReadMask 0xFFFFFFFF +#define GC_TOTAL_IDLE_CYCLES_WriteMask 0xFFFFFFFF +#define GC_TOTAL_IDLE_CYCLES_ResetValue 0x00000000 + +#define GC_TOTAL_IDLE_CYCLES_CYCLES 31 : 0 +#define GC_TOTAL_IDLE_CYCLES_CYCLES_End 31 +#define GC_TOTAL_IDLE_CYCLES_CYCLES_Start 0 +#define GC_TOTAL_IDLE_CYCLES_CYCLES_Type U32 + +/******************************************************************************* +** Command opcodes. +*/ + +#define GCREG_COMMAND_OPCODE_LOAD_STATE 0x01 +#define GCREG_COMMAND_OPCODE_END 0x02 +#define GCREG_COMMAND_OPCODE_NOP 0x03 +#define GCREG_COMMAND_OPCODE_STARTDE 0x04 +#define GCREG_COMMAND_OPCODE_WAIT 0x07 +#define GCREG_COMMAND_OPCODE_LINK 0x08 +#define GCREG_COMMAND_OPCODE_STALL 0x09 +#define GCREG_COMMAND_OPCODE_CALL 0x0A +#define GCREG_COMMAND_OPCODE_RETURN 0x0B + +/******************************************************************************* +** Command gcregCommandLoadState +*/ + +/* When enabled, convert 16.16 fixed point into 32-bit floating point. */ +#define GCREG_COMMAND_LOAD_STATE_FLOAT 26 : 26 +#define GCREG_COMMAND_LOAD_STATE_FLOAT_End 26 +#define GCREG_COMMAND_LOAD_STATE_FLOAT_Start 26 +#define GCREG_COMMAND_LOAD_STATE_FLOAT_Type U01 +#define GCREG_COMMAND_LOAD_STATE_FLOAT_NORMAL 0x0 +#define GCREG_COMMAND_LOAD_STATE_FLOAT_FIXED16_DOT16 0x1 + +/* Number of states. 0 = 1024. */ +#define GCREG_COMMAND_LOAD_STATE_COUNT 25 : 16 +#define GCREG_COMMAND_LOAD_STATE_COUNT_End 25 +#define GCREG_COMMAND_LOAD_STATE_COUNT_Start 16 +#define GCREG_COMMAND_LOAD_STATE_COUNT_Type U10 + +/* Starting state address. */ +#define GCREG_COMMAND_LOAD_STATE_ADDRESS 15 : 0 +#define GCREG_COMMAND_LOAD_STATE_ADDRESS_End 15 +#define GCREG_COMMAND_LOAD_STATE_ADDRESS_Start 0 +#define GCREG_COMMAND_LOAD_STATE_ADDRESS_Type U16 + +#define GCREG_COMMAND_LOAD_STATE_OPCODE 31 : 27 +#define GCREG_COMMAND_LOAD_STATE_OPCODE_End 31 +#define GCREG_COMMAND_LOAD_STATE_OPCODE_Start 27 +#define GCREG_COMMAND_LOAD_STATE_OPCODE_Type U05 + +struct gccmdldstate { + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_ADDRESS */ + unsigned int address:16; + + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COUNT */ + unsigned int count:10; + + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_FLOAT */ + unsigned int fixed:1; + + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_OPCODE */ + unsigned int opcode:5; +}; + +#define GCLDSTATE(Address, Count) \ +{ \ + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_ADDRESS */ \ + Address, \ + \ + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COUNT */ \ + Count, \ + \ + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_FLOAT */ \ + GCREG_COMMAND_LOAD_STATE_FLOAT_NORMAL, \ + \ + /* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_OPCODE */ \ + GCREG_COMMAND_OPCODE_LOAD_STATE \ +} + +/******************************************************************************* +** Command gcregCommandEnd +*/ + +/* Send event when END is completed. */ +#define GCREG_COMMAND_END_EVENT 8 : 8 +#define GCREG_COMMAND_END_EVENT_End 8 +#define GCREG_COMMAND_END_EVENT_Start 8 +#define GCREG_COMMAND_END_EVENT_Type U01 +#define GCREG_COMMAND_END_EVENT_DISABLE 0x0 +#define GCREG_COMMAND_END_EVENT_ENABLE 0x1 + +/* Event ID to be send. */ +#define GCREG_COMMAND_END_EVENT_ID 4 : 0 +#define GCREG_COMMAND_END_EVENT_ID_End 4 +#define GCREG_COMMAND_END_EVENT_ID_Start 0 +#define GCREG_COMMAND_END_EVENT_ID_Type U05 + +#define GCREG_COMMAND_END_OPCODE 31 : 27 +#define GCREG_COMMAND_END_OPCODE_End 31 +#define GCREG_COMMAND_END_OPCODE_Start 27 +#define GCREG_COMMAND_END_OPCODE_Type U05 + +struct gcfldend { + /* gcregCommandEnd:GCREG_COMMAND_END_EVENT_ID */ + unsigned int signalid:5; + + /* gcregCommandEnd:reserved */ + unsigned int _reserved_5_7:3; + + /* gcregCommandEnd:GCREG_COMMAND_END_EVENT_ENABLE */ + unsigned int signal:1; + + /* gcregCommandEnd:reserved */ + unsigned int _reserved_9_26:18; + + /* gcregCommandEnd:GCREG_COMMAND_END_OPCODE */ + unsigned int opcode:5; +}; + +struct gccmdend { + union { + struct gcfldend fld; + unsigned int raw; + } + cmd; + + /* Alignment filler. */ + unsigned int _filler; +}; + +static const struct gccmdend gccmdend_const = { + /* cmd */ + { + /* fld */ + { + /* gcregCommandEnd:GCREG_COMMAND_END_EVENT_ID */ + 0, + + /* gcregCommandEnd:reserved */ + 0, + + /* gcregCommandEnd:GCREG_COMMAND_END_EVENT */ + GCREG_COMMAND_END_EVENT_DISABLE, + + /* gcregCommandEnd:reserved */ + 0, + + /* gcregCommandEnd:GCREG_COMMAND_END_OPCODE */ + GCREG_COMMAND_OPCODE_END + } + }, + + /* Alignment filler. */ + 0 +}; + +/******************************************************************************* +** Command gcregCommandNop +*/ + +#define GCREG_COMMAND_NOP_OPCODE 31 : 27 +#define GCREG_COMMAND_NOP_OPCODE_End 31 +#define GCREG_COMMAND_NOP_OPCODE_Start 27 +#define GCREG_COMMAND_NOP_OPCODE_Type U05 + +struct gcfldnop { + /* gcregCommandNop:reserve */ + unsigned int _reserved_0_26:27; + + /* gcregCommandNop:GCREG_COMMAND_NOP_OPCODE */ + unsigned int opcode:5; +}; + +struct gccmdnop { + union { + struct gcfldnop fld; + unsigned int raw; + } + cmd; + + /* Alignment filler. */ + unsigned int _filler; +}; + +static const struct gccmdnop gccmdnop_const = { + /* cmd */ + { + /* fld */ + { + /* gcregCommandNop:reserve */ + 0, + + /* gcregCommandNop:GCREG_COMMAND_NOP_OPCODE */ + GCREG_COMMAND_OPCODE_NOP + } + }, + + /* Alignment filler. */ + 0 +}; + +/******************************************************************************* +** Command gcregCommandStartDE +*/ + +/* Offset Command +** ~~~~~~~~~~~~~~ */ + +/* Number of 32-bit data words to send. +** The data follows the rectangles, aligned at 64-bit. +*/ +#define GCREG_COMMAND_STARTDE_DATA_COUNT 26 : 16 +#define GCREG_COMMAND_STARTDE_DATA_COUNT_End 26 +#define GCREG_COMMAND_STARTDE_DATA_COUNT_Start 16 +#define GCREG_COMMAND_STARTDE_DATA_COUNT_Type U11 + +/* Number of rectangles to send. +** The rectangles follow the command, aligned at 64-bit. +*/ +#define GCREG_COMMAND_STARTDE_COUNT 15 : 8 +#define GCREG_COMMAND_STARTDE_COUNT_End 15 +#define GCREG_COMMAND_STARTDE_COUNT_Start 8 +#define GCREG_COMMAND_STARTDE_COUNT_Type U08 + +#define GCREG_COMMAND_STARTDE_OPCODE 31 : 27 +#define GCREG_COMMAND_STARTDE_OPCODE_End 31 +#define GCREG_COMMAND_STARTDE_OPCODE_Start 27 +#define GCREG_COMMAND_STARTDE_OPCODE_Type U05 + +struct gcfldstartde { + /* gcregCommandStartDE:reserved */ + unsigned int _reserved_0_7:8; + + /* gcregCommandStartDE:GCREG_COMMAND_STARTDE_COUNT */ + unsigned int rectcount:8; + + /* gcregCommandStartDE:GCREG_COMMAND_STARTDE_DATA_COUNT */ + unsigned int datacount:11; + + /* gcregCommandStartDE:GCREG_COMMAND_STARTDE_OPCODE */ + unsigned int opcode:5; +}; + +struct gccmdstartde { + union { + struct gcfldstartde fld; + unsigned int raw; + } cmd; + + /* Alignment filler. */ + unsigned int _filler; +}; + +static const struct gcfldstartde gcfldstartde = { + /* gcregCommandStartDE:reserved */ + 0, + + /* gcregCommandStartDE:GCREG_COMMAND_STARTDE_COUNT */ + 1, + + /* gcregCommandStartDE:GCREG_COMMAND_STARTDE_DATA_COUNT */ + 0, + + /* gcregCommandStartDE:GCREG_COMMAND_STARTDE_OPCODE */ + GCREG_COMMAND_OPCODE_STARTDE +}; + +/* Offset TopLeft +** ~~~~~~~~~~~~~~ */ + +#define GCREG_COMMAND_TOP_LEFT_Y 31 : 16 +#define GCREG_COMMAND_TOP_LEFT_Y_End 31 +#define GCREG_COMMAND_TOP_LEFT_Y_Start 16 +#define GCREG_COMMAND_TOP_LEFT_Y_Type U16 + +#define GCREG_COMMAND_TOP_LEFT_X 15 : 0 +#define GCREG_COMMAND_TOP_LEFT_X_End 15 +#define GCREG_COMMAND_TOP_LEFT_X_Start 0 +#define GCREG_COMMAND_TOP_LEFT_X_Type U16 + +/* Offset BottomRight +** ~~~~~~~~~~~~~~~~~~ */ + +#define GCREG_COMMAND_BOTTOM_RIGHT_Y 31 : 16 +#define GCREG_COMMAND_BOTTOM_RIGHT_Y_End 31 +#define GCREG_COMMAND_BOTTOM_RIGHT_Y_Start 16 +#define GCREG_COMMAND_BOTTOM_RIGHT_Y_Type U16 + +#define GCREG_COMMAND_BOTTOM_RIGHT_X 15 : 0 +#define GCREG_COMMAND_BOTTOM_RIGHT_X_End 15 +#define GCREG_COMMAND_BOTTOM_RIGHT_X_Start 0 +#define GCREG_COMMAND_BOTTOM_RIGHT_X_Type U16 + +struct gccmdstartderect { + /* GCREG_COMMAND_TOP_LEFT_X */ + unsigned int left:16; + + /* GCREG_COMMAND_TOP_LEFT_Y */ + unsigned int top:16; + + /* GCREG_COMMAND_BOTTOM_RIGHT_X */ + unsigned int right:16; + + /* GCREG_COMMAND_BOTTOM_RIGHT_Y */ + unsigned int bottom:16; +}; + +/******************************************************************************* +** Command gcregCommandWait +*/ + +/* Number of cycles to wait until the next command gets fetched. */ +#define GCREG_COMMAND_WAIT_DELAY 15 : 0 +#define GCREG_COMMAND_WAIT_DELAY_End 15 +#define GCREG_COMMAND_WAIT_DELAY_Start 0 +#define GCREG_COMMAND_WAIT_DELAY_Type U16 + +#define GCREG_COMMAND_WAIT_OPCODE 31 : 27 +#define GCREG_COMMAND_WAIT_OPCODE_End 31 +#define GCREG_COMMAND_WAIT_OPCODE_Start 27 +#define GCREG_COMMAND_WAIT_OPCODE_Type U05 + +struct gcfldwait { + /* gcregCommandWait:GCREG_COMMAND_WAIT_DELAY */ + unsigned int delay:16; + + /* gcregCommandWait:reserved */ + unsigned int _reserved_16_26:11; + + /* gcregCommandWait:GCREG_COMMAND_WAIT_OPCODE */ + unsigned int opcode:5; +}; + +struct gccmdwait { + union { + struct gcfldwait fld; + unsigned int raw; + } cmd; + + /* Alignment filler. */ + unsigned int _filler; +}; + +static const struct gcfldwait gcfldwait200 = { + /* gcregCommandWait:GCREG_COMMAND_WAIT_DELAY */ + 200, + + /* gcregCommandWait:reserved */ + 0, + + /* gcregCommandWait:GCREG_COMMAND_WAIT_OPCODE */ + GCREG_COMMAND_OPCODE_WAIT +}; + +/******************************************************************************* +** Command gcregCommandLink +*/ + +/* Number of 64-bit words to fetch. Make sure this number is not too low, +** nothing else will be fetched. So, make sure that the last command in the +** new command buffer is either an END, a LINK, a CALL, or a RETURN. +*/ +#define GCREG_COMMAND_LINK_PREFETCH 15 : 0 +#define GCREG_COMMAND_LINK_PREFETCH_End 15 +#define GCREG_COMMAND_LINK_PREFETCH_Start 0 +#define GCREG_COMMAND_LINK_PREFETCH_Type U16 + +#define GCREG_COMMAND_LINK_OPCODE 31 : 27 +#define GCREG_COMMAND_LINK_OPCODE_End 31 +#define GCREG_COMMAND_LINK_OPCODE_Start 27 +#define GCREG_COMMAND_LINK_OPCODE_Type U05 + +/* Offset Address +** ~~~~~~~~~~~~~~ */ +#define GCREG_COMMAND_LINK_ADDRESS_Index 1 +#define GCREG_COMMAND_LINK_ADDRESS_CmdAddrs 0x0F0D + +#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS 31 : 0 +#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS_End 30 +#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS_Start 0 +#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS_Type U31 + +struct gcfldlink { + /* gcregCommandLink:GCREG_COMMAND_LINK_PREFETCH */ + unsigned int count:16; + + /* gcregCommandLink:reserved */ + unsigned int _reserved_16_26:11; + + /* gcregCommandLink:GCREG_COMMAND_LINK_OPCODE */ + unsigned int opcode:5; +}; + +struct gccmdlink { + union { + struct gcfldlink fld; + unsigned int raw; + } cmd; + + /* gcregCommandLink:GCREG_COMMAND_LINK_ADDRESS_ADDRESS */ + unsigned int address; +}; + +static const struct gcfldlink gcfldlink2 = { + /* gcregCommandLink:GCREG_COMMAND_LINK_PREFETCH */ + 2, + + /* gcregCommandLink:reserved */ + 0, + + /* gcregCommandLink:GCREG_COMMAND_LINK_OPCODE */ + GCREG_COMMAND_OPCODE_LINK +}; + +static const struct gcfldlink gcfldlink4 = { + /* gcregCommandLink:GCREG_COMMAND_LINK_PREFETCH */ + 4, + + /* gcregCommandLink:reserved */ + 0, + + /* gcregCommandLink:GCREG_COMMAND_LINK_OPCODE */ + GCREG_COMMAND_OPCODE_LINK +}; + +/******************************************************************************* +** Command gcregCommandStall +*/ + +/* Offset Command +** ~~~~~~~~~~~~~~ */ +#define GCREG_COMMAND_STALL_OPCODE 31 : 27 +#define GCREG_COMMAND_STALL_OPCODE_End 31 +#define GCREG_COMMAND_STALL_OPCODE_Start 27 +#define GCREG_COMMAND_STALL_OPCODE_Type U05 + +/* Offset Stall +** ~~~~~~~~~~~~ */ +#define GCREG_COMMAND_STALL_STALL_SOURCE 4 : 0 +#define GCREG_COMMAND_STALL_STALL_SOURCE_End 4 +#define GCREG_COMMAND_STALL_STALL_SOURCE_Start 0 +#define GCREG_COMMAND_STALL_STALL_SOURCE_Type U05 +#define GCREG_COMMAND_STALL_STALL_SOURCE_FRONT_END 0x01 +#define GCREG_COMMAND_STALL_STALL_SOURCE_PIXEL_ENGINE 0x07 +#define GCREG_COMMAND_STALL_STALL_SOURCE_DRAWING_ENGINE 0x0B + +#define GCREG_COMMAND_STALL_STALL_DESTINATION 12 : 8 +#define GCREG_COMMAND_STALL_STALL_DESTINATION_End 12 +#define GCREG_COMMAND_STALL_STALL_DESTINATION_Start 8 +#define GCREG_COMMAND_STALL_STALL_DESTINATION_Type U05 +#define GCREG_COMMAND_STALL_STALL_DESTINATION_FRONT_END 0x01 +#define GCREG_COMMAND_STALL_STALL_DESTINATION_PIXEL_ENGINE 0x07 +#define GCREG_COMMAND_STALL_STALL_DESTINATION_DRAWING_ENGINE 0x0B + +struct gcfldstall { + /* gcregCommandStall:reserved */ + unsigned int _reserved_0_26:27; + + /* gcregCommandStall:GCREG_COMMAND_STALL_OPCODE */ + unsigned int opcode:5; +}; + +struct gcfldstallarg { + /* gcregCommandStall:GCREG_COMMAND_STALL_STALL_SOURCE */ + unsigned int src:5; + + /* gcregCommandStall:reserved */ + unsigned int _reserved_5_7:3; + + /* gcregCommandStall:GCREG_COMMAND_STALL_STALL_DESTINATION */ + unsigned int dst:5; + + /* gcregCommandStall:reserved */ + unsigned int _reserved_13_31:19; +}; + +struct gccmdstall { + union { + struct gcfldstall fld; + unsigned int raw; + } cmd; + + union { + struct gcfldstallarg fld; + unsigned int raw; + } arg; +}; + +static const struct gcfldstall gcfldstall = { + /* gcregCommandStall:reserved */ + 0, + + /* gcregCommandStall:GCREG_COMMAND_STALL_OPCODE */ + GCREG_COMMAND_OPCODE_STALL +}; + +static const struct gcfldstallarg gcfldstall_fe_pe = { + /* gcregCommandStall:GCREG_COMMAND_STALL_STALL_SOURCE */ + GCREG_COMMAND_STALL_STALL_SOURCE_FRONT_END, + + /* gcregCommandStall:reserved */ + 0, + + /* gcregCommandStall:GCREG_COMMAND_STALL_STALL_DESTINATION */ + GCREG_COMMAND_STALL_STALL_DESTINATION_PIXEL_ENGINE, + + /* gcregCommandStall:reserved */ + 0 +}; + +/******************************************************************************* +** Command gcregCommandCall +*/ + +/* Offset Command +** ~~~~~~~~~~~~~~ */ + +/* Number of 64-bit words to fetch. Make sure this number is not too low, +** nothing else will be fetched. So, make sure that the last command in the +** new command buffer is either an END, a LINK, a CALL, or a RETURN. +*/ +#define GCREG_COMMAND_CALL_PREFETCH 15 : 0 +#define GCREG_COMMAND_CALL_PREFETCH_End 15 +#define GCREG_COMMAND_CALL_PREFETCH_Start 0 +#define GCREG_COMMAND_CALL_PREFETCH_Type U16 + +#define GCREG_COMMAND_CALL_OPCODE 31 : 27 +#define GCREG_COMMAND_CALL_OPCODE_End 31 +#define GCREG_COMMAND_CALL_OPCODE_Start 27 +#define GCREG_COMMAND_CALL_OPCODE_Type U05 + +/* Offset Address +** ~~~~~~~~~~~~~~ */ + +#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS 31 : 0 +#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS_End 30 +#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS_Start 0 +#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS_Type U31 + +/* Offset ReturnPrefetch +** ~~~~~~~~~~~~~~~~~~~~~ */ + +/* Number of 64-bit words to fetch after a Return has been issued. Make sure ** +** this number if not too low nothing else will be fetched. So, make sure ** +** the last command in this prefetch block is either an END, a LINK, a CALL, ** +** or a RETURN. */ +#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH 15 : 0 +#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH_End 15 +#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH_Start 0 +#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH_Type U16 + +/* Offset ReturnAddress +** ~~~~~~~~~~~~~~~~~~~~ */ + +#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS 31 : 0 +#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS_End 30 +#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS_Start 0 +#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS_Type U31 + +struct gccmdcall { + /* gcregCommandCall:GCREG_COMMAND_CALL_PREFETCH */ + unsigned int count:16; + + /* gcregCommandCall:reserved */ + unsigned int _reserved_16_26:11; + + /* gcregCommandCall:GCREG_COMMAND_CALL_OPCODE */ + unsigned int opcode:5; + + /* gcregCommandCall:GCREG_COMMAND_CALL_ADDRESS_ADDRESS */ + unsigned int address; + + /* gcregCommandCall:GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH */ + unsigned int retcount; + + /* gcregCommandCall:GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS */ + unsigned int retaddress; +}; + +/******************************************************************************* +** Command gccmdCommandReturn +*/ + +#define GCREG_COMMAND_RETURN_OPCODE 31 : 27 +#define GCREG_COMMAND_RETURN_OPCODE_End 31 +#define GCREG_COMMAND_RETURN_OPCODE_Start 27 +#define GCREG_COMMAND_RETURN_OPCODE_Type U05 + +struct gcfldret { + /* gccmdCommandReturn:reserve */ + unsigned int _reserved_0_26:27; + + /* gccmdCommandReturn:GCREG_COMMAND_RETURN_OPCODE */ + unsigned int opcode:5; +}; + +struct gccmdret { + union { + struct gcfldret fld; + unsigned int raw; + } + cmd; + + /* Alignment filler. */ + unsigned int _filler; +}; + +static const struct gcfldret gcfldret = { + /* gccmdCommandReturn:reserve */ + 0, + + /* gccmdCommandReturn:GCREG_COMMAND_RETURN_OPCODE */ + GCREG_COMMAND_OPCODE_RETURN +}; + +/******************************************************************************* +** State gcregStall +*/ + +#define gcregStallRegAddrs 0x0F00 +#define GCREG_STALL_Count 1 +#define GCREG_STALL_ResetValue 0x00000000 + +#define GCREG_STALL_FLIP0 30 : 30 +#define GCREG_STALL_FLIP0_End 30 +#define GCREG_STALL_FLIP0_Start 30 +#define GCREG_STALL_FLIP0_Type U01 + +#define GCREG_STALL_FLIP1 31 : 31 +#define GCREG_STALL_FLIP1_End 31 +#define GCREG_STALL_FLIP1_Start 31 +#define GCREG_STALL_FLIP1_Type U01 + +#define GCREG_STALL_SOURCE 4 : 0 +#define GCREG_STALL_SOURCE_End 4 +#define GCREG_STALL_SOURCE_Start 0 +#define GCREG_STALL_SOURCE_Type U05 +#define GCREG_STALL_SOURCE_FRONT_END 0x01 +#define GCREG_STALL_SOURCE_PIXEL_ENGINE 0x07 +#define GCREG_STALL_SOURCE_DRAWING_ENGINE 0x0B + +#define GCREG_STALL_DESTINATION 12 : 8 +#define GCREG_STALL_DESTINATION_End 12 +#define GCREG_STALL_DESTINATION_Start 8 +#define GCREG_STALL_DESTINATION_Type U05 +#define GCREG_STALL_DESTINATION_FRONT_END 0x01 +#define GCREG_STALL_DESTINATION_PIXEL_ENGINE 0x07 +#define GCREG_STALL_DESTINATION_DRAWING_ENGINE 0x0B + +/******************************************************************************* +** State gcregPipeSelect +*/ + +/* Select the current graphics pipe. */ + +#define gcregPipeSelectRegAddrs 0x0E00 +#define GCREG_PIPE_SELECT_MSB 15 +#define GCREG_PIPE_SELECT_LSB 0 +#define GCREG_PIPE_SELECT_BLK 0 +#define GCREG_PIPE_SELECT_Count 1 +#define GCREG_PIPE_SELECT_FieldMask 0x00000001 +#define GCREG_PIPE_SELECT_ReadMask 0x00000001 +#define GCREG_PIPE_SELECT_WriteMask 0x00000001 +#define GCREG_PIPE_SELECT_ResetValue 0x00000000 + +/* Selects the pipe to send states and data to. Make sure the PE is idle ** +** before you switch pipes. */ +#define GCREG_PIPE_SELECT_PIPE 0 : 0 +#define GCREG_PIPE_SELECT_PIPE_End 0 +#define GCREG_PIPE_SELECT_PIPE_Start 0 +#define GCREG_PIPE_SELECT_PIPE_Type U01 +#define GCREG_PIPE_SELECT_PIPE_PIPE3D 0x0 +#define GCREG_PIPE_SELECT_PIPE_PIPE2D 0x1 + +struct gcregpipeselect { + /* gcregPipeSelectRegAddrs:GCREG_PIPE_SELECT_PIPE */ + unsigned int pipe:1; + + /* gcregPipeSelectRegAddrs:reserved */ + unsigned int _reserved_1_31:31; +}; + +static const struct gcregpipeselect gcregpipeselect_2D = { + /* gcregPipeSelectRegAddrs:GCREG_PIPE_SELECT_PIPE */ + GCREG_PIPE_SELECT_PIPE_PIPE2D, + + /* gcregPipeSelectRegAddrs:reserved */ + 0 +}; + +static const struct gcregpipeselect gcregpipeselect_3D = { + /* gcregPipeSelectRegAddrs:GCREG_PIPE_SELECT_PIPE */ + GCREG_PIPE_SELECT_PIPE_PIPE3D, + + /* gcregPipeSelectRegAddrs:reserved */ + 0 +}; + +/******************************************************************************* +** State gcregEvent +*/ + +/* Send an event. */ + +#define gcregEventRegAddrs 0x0E01 +#define GCREG_EVENT_MSB 15 +#define GCREG_EVENT_LSB 0 +#define GCREG_EVENT_BLK 0 +#define GCREG_EVENT_Count 1 +#define GCREG_EVENT_FieldMask 0x0000007F +#define GCREG_EVENT_ReadMask 0x0000007F +#define GCREG_EVENT_WriteMask 0x0000007F +#define GCREG_EVENT_ResetValue 0x00000000 + +/* 5-bit event ID to send. */ +#define GCREG_EVENT_EVENT_ID 4 : 0 +#define GCREG_EVENT_EVENT_ID_End 4 +#define GCREG_EVENT_EVENT_ID_Start 0 +#define GCREG_EVENT_EVENT_ID_Type U05 + +/* The event is sent by the FE. */ +#define GCREG_EVENT_FE_SRC 5 : 5 +#define GCREG_EVENT_FE_SRC_End 5 +#define GCREG_EVENT_FE_SRC_Start 5 +#define GCREG_EVENT_FE_SRC_Type U01 +#define GCREG_EVENT_FE_SRC_DISABLE 0x0 +#define GCREG_EVENT_FE_SRC_ENABLE 0x1 + +/* The event is sent by the PE. */ +#define GCREG_EVENT_PE_SRC 6 : 6 +#define GCREG_EVENT_PE_SRC_End 6 +#define GCREG_EVENT_PE_SRC_Start 6 +#define GCREG_EVENT_PE_SRC_Type U01 +#define GCREG_EVENT_PE_SRC_DISABLE 0x0 +#define GCREG_EVENT_PE_SRC_ENABLE 0x1 + +struct gcregevent { + /* gcregEventRegAddrs:GCREG_EVENT_EVENT_ID */ + unsigned int id:5; + + /* gcregEventRegAddrs:GCREG_EVENT_FE_SRC */ + unsigned int fe:1; + + /* gcregEventRegAddrs:GCREG_EVENT_PE_SRC */ + unsigned int pe:1; + + /* gcregEventRegAddrs:reserved */ + unsigned int _reserved_7_31:25; +}; + +/******************************************************************************* +** State gcregSemaphore +*/ + +/* A sempahore state arms the semaphore in the destination. */ + +#define gcregSemaphoreRegAddrs 0x0E02 +#define GCREG_SEMAPHORE_MSB 15 +#define GCREG_SEMAPHORE_LSB 0 +#define GCREG_SEMAPHORE_BLK 0 +#define GCREG_SEMAPHORE_Count 1 +#define GCREG_SEMAPHORE_FieldMask 0x00001F1F +#define GCREG_SEMAPHORE_ReadMask 0x00001F1F +#define GCREG_SEMAPHORE_WriteMask 0x00001F1F +#define GCREG_SEMAPHORE_ResetValue 0x00000000 + +#define GCREG_SEMAPHORE_SOURCE 4 : 0 +#define GCREG_SEMAPHORE_SOURCE_End 4 +#define GCREG_SEMAPHORE_SOURCE_Start 0 +#define GCREG_SEMAPHORE_SOURCE_Type U05 +#define GCREG_SEMAPHORE_SOURCE_FRONT_END 0x01 +#define GCREG_SEMAPHORE_SOURCE_PIXEL_ENGINE 0x07 +#define GCREG_SEMAPHORE_SOURCE_DRAWING_ENGINE 0x0B + +#define GCREG_SEMAPHORE_DESTINATION 12 : 8 +#define GCREG_SEMAPHORE_DESTINATION_End 12 +#define GCREG_SEMAPHORE_DESTINATION_Start 8 +#define GCREG_SEMAPHORE_DESTINATION_Type U05 +#define GCREG_SEMAPHORE_DESTINATION_FRONT_END 0x01 +#define GCREG_SEMAPHORE_DESTINATION_PIXEL_ENGINE 0x07 +#define GCREG_SEMAPHORE_DESTINATION_DRAWING_ENGINE 0x0B + +struct gcregsemaphore { + /* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_SOURCE */ + unsigned int src:5; + + /* gcregSemaphoreRegAddrs:reserved */ + unsigned int _reserved_5_7:3; + + /* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_DESTINATION */ + unsigned int dst:5; + + /* gcregSemaphoreRegAddrs:reserved */ + unsigned int _reserved_13_31:19; +}; + +static const struct gcregsemaphore gcregsema_fe_pe = { + /* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_SOURCE */ + GCREG_SEMAPHORE_SOURCE_FRONT_END, + + /* gcregSemaphoreRegAddrs:reserved */ + 0, + + /* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_DESTINATION */ + GCREG_SEMAPHORE_DESTINATION_PIXEL_ENGINE, + + /* gcregSemaphoreRegAddrs:reserved */ + 0 +}; + + +/******************************************************************************* +** State gcregFlush +*/ + +/* Flush the current pipe. */ + +#define gcregFlushRegAddrs 0x0E03 +#define GCREG_FLUSH_MSB 15 +#define GCREG_FLUSH_LSB 0 +#define GCREG_FLUSH_BLK 0 +#define GCREG_FLUSH_Count 1 +#define GCREG_FLUSH_FieldMask 0x00000008 +#define GCREG_FLUSH_ReadMask 0x00000008 +#define GCREG_FLUSH_WriteMask 0x00000008 +#define GCREG_FLUSH_ResetValue 0x00000000 + +/* Flush the 2D pixel cache. */ +#define GCREG_FLUSH_PE2D_CACHE 3 : 3 +#define GCREG_FLUSH_PE2D_CACHE_End 3 +#define GCREG_FLUSH_PE2D_CACHE_Start 3 +#define GCREG_FLUSH_PE2D_CACHE_Type U01 +#define GCREG_FLUSH_PE2D_CACHE_DISABLE 0x0 +#define GCREG_FLUSH_PE2D_CACHE_ENABLE 0x1 + +struct gcregflush { + /* gcregFlushRegAddrs:reserved */ + unsigned int _reserved_0_2:3; + + /* gcregFlushRegAddrs:GCREG_FLUSH_PE2D_CACHE */ + unsigned int enable:1; + + /* gcregFlushRegAddrs:reserved */ + unsigned int _reserved_4_31:28; +}; + +static const struct gcregflush gcregflush_pe2D = { + /* gcregFlushRegAddrs:reserved */ + 0, + + /* gcregFlushRegAddrs:GCREG_FLUSH_PE2D_CACHE */ + GCREG_FLUSH_PE2D_CACHE_ENABLE, + + /* gcregFlushRegAddrs:reserved */ + 0 +}; + +/******************************************************************************* +** State gcregMMUFlush +*/ + +/* Flush the virtual addrses lookup cache inside the MC. */ + +#define gcregMMUFlushRegAddrs 0x0E04 +#define gcregMMU_FLUSH_MSB 15 +#define gcregMMU_FLUSH_LSB 0 +#define gcregMMU_FLUSH_BLK 0 +#define gcregMMU_FLUSH_Count 1 +#define gcregMMU_FLUSH_FieldMask 0x00000009 +#define gcregMMU_FLUSH_ReadMask 0x00000009 +#define gcregMMU_FLUSH_WriteMask 0x00000009 +#define gcregMMU_FLUSH_ResetValue 0x00000000 + +/* Flush the FE address translation caches. */ +#define gcregMMU_FLUSH_FEMMU 0 : 0 +#define gcregMMU_FLUSH_FEMMU_End 0 +#define gcregMMU_FLUSH_FEMMU_Start 0 +#define gcregMMU_FLUSH_FEMMU_Type U01 +#define gcregMMU_FLUSH_FEMMU_DISABLE 0x0 +#define gcregMMU_FLUSH_FEMMU_ENABLE 0x1 + +/* Flush the PE render target address translation caches. */ +#define gcregMMU_FLUSH_PEMMU 3 : 3 +#define gcregMMU_FLUSH_PEMMU_End 3 +#define gcregMMU_FLUSH_PEMMU_Start 3 +#define gcregMMU_FLUSH_PEMMU_Type U01 +#define gcregMMU_FLUSH_PEMMU_DISABLE 0x0 +#define gcregMMU_FLUSH_PEMMU_ENABLE 0x1 + +/******************************************************************************* +** Register gcregCmdBufferAddr +*/ + +/* Base address for the command buffer. The address must be 64-bit aligned +** and it is always physical. This register cannot be read. To check the value +** of the current fetch address use gcregFEDebugCurCmdAdr. Since this is a write +** only register is has no reset value. +*/ + +#define GCREG_CMD_BUFFER_ADDR_Address 0x00654 +#define GCREG_CMD_BUFFER_ADDR_MSB 15 +#define GCREG_CMD_BUFFER_ADDR_LSB 0 +#define GCREG_CMD_BUFFER_ADDR_BLK 0 +#define GCREG_CMD_BUFFER_ADDR_Count 1 +#define GCREG_CMD_BUFFER_ADDR_FieldMask 0xFFFFFFFF +#define GCREG_CMD_BUFFER_ADDR_ReadMask 0x00000000 +#define GCREG_CMD_BUFFER_ADDR_WriteMask 0xFFFFFFFC +#define GCREG_CMD_BUFFER_ADDR_ResetValue 0x00000000 + +#define GCREG_CMD_BUFFER_ADDR_ADDRESS 31 : 0 +#define GCREG_CMD_BUFFER_ADDR_ADDRESS_End 30 +#define GCREG_CMD_BUFFER_ADDR_ADDRESS_Start 0 +#define GCREG_CMD_BUFFER_ADDR_ADDRESS_Type U31 + +/******************************************************************************* +** Register gcregCmdBufferCtrl +*/ + +/* Since this is a write only register is has no reset value. */ + +#define GCREG_CMD_BUFFER_CTRL_Address 0x00658 +#define GCREG_CMD_BUFFER_CTRL_MSB 15 +#define GCREG_CMD_BUFFER_CTRL_LSB 0 +#define GCREG_CMD_BUFFER_CTRL_BLK 0 +#define GCREG_CMD_BUFFER_CTRL_Count 1 +#define GCREG_CMD_BUFFER_CTRL_FieldMask 0x0001FFFF +#define GCREG_CMD_BUFFER_CTRL_ReadMask 0x00010000 +#define GCREG_CMD_BUFFER_CTRL_WriteMask 0x0001FFFF +#define GCREG_CMD_BUFFER_CTRL_ResetValue 0x00000000 + +/* Number of 64-bit words to fetch from the command buffer. */ +#define GCREG_CMD_BUFFER_CTRL_PREFETCH 15 : 0 +#define GCREG_CMD_BUFFER_CTRL_PREFETCH_End 15 +#define GCREG_CMD_BUFFER_CTRL_PREFETCH_Start 0 +#define GCREG_CMD_BUFFER_CTRL_PREFETCH_Type U16 + +/* Enable the command parser. */ +#define GCREG_CMD_BUFFER_CTRL_ENABLE 16 : 16 +#define GCREG_CMD_BUFFER_CTRL_ENABLE_End 16 +#define GCREG_CMD_BUFFER_CTRL_ENABLE_Start 16 +#define GCREG_CMD_BUFFER_CTRL_ENABLE_Type U01 +#define GCREG_CMD_BUFFER_CTRL_ENABLE_DISABLE 0x0 +#define GCREG_CMD_BUFFER_CTRL_ENABLE_ENABLE 0x1 + +/******************************************************************************* +** Register gcregFEDebugState +*/ + +#define GCREG_FE_DEBUG_STATE_Address 0x00660 +#define GCREG_FE_DEBUG_STATE_MSB 15 +#define GCREG_FE_DEBUG_STATE_LSB 0 +#define GCREG_FE_DEBUG_STATE_BLK 0 +#define GCREG_FE_DEBUG_STATE_Count 1 +#define GCREG_FE_DEBUG_STATE_FieldMask 0x0003FF1F +#define GCREG_FE_DEBUG_STATE_ReadMask 0x0003FF1F +#define GCREG_FE_DEBUG_STATE_WriteMask 0x00000000 +#define GCREG_FE_DEBUG_STATE_ResetValue 0x00000000 + +#define GCREG_FE_DEBUG_STATE_CMD_STATE 4 : 0 +#define GCREG_FE_DEBUG_STATE_CMD_STATE_End 4 +#define GCREG_FE_DEBUG_STATE_CMD_STATE_Start 0 +#define GCREG_FE_DEBUG_STATE_CMD_STATE_Type U05 + +#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE 9 : 8 +#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE_End 9 +#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE_Start 8 +#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE_Type U02 + +#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE 11 : 10 +#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE_End 11 +#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE_Start 10 +#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE_Type U02 + +#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE 13 : 12 +#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE_End 13 +#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE_Start 12 +#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE_Type U02 + +#define GCREG_FE_DEBUG_STATE_CAL_STATE 15 : 14 +#define GCREG_FE_DEBUG_STATE_CAL_STATE_End 15 +#define GCREG_FE_DEBUG_STATE_CAL_STATE_Start 14 +#define GCREG_FE_DEBUG_STATE_CAL_STATE_Type U02 + +#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE 17 : 16 +#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE_End 17 +#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE_Start 16 +#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE_Type U02 + +/******************************************************************************* +** Register gcregFEDebugCurCmdAdr +*/ + +/* This is the command decoder address. The address is always physical so +** the MSB should always be 0. It has no reset value. +*/ + +#define GCREG_FE_DEBUG_CUR_CMD_ADR_Address 0x00664 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_MSB 15 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_LSB 0 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_BLK 0 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_Count 1 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_FieldMask 0xFFFFFFF8 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_ReadMask 0xFFFFFFF8 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_WriteMask 0x00000000 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_ResetValue 0x00000000 + +#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR 31 : 3 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR_End 31 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR_Start 3 +#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR_Type U29 + +/******************************************************************************* +** Register gcregFEDebugCmdLowReg +*/ + +#define GCREG_FE_DEBUG_CMD_LOW_REG_Address 0x00668 +#define GCREG_FE_DEBUG_CMD_LOW_REG_MSB 15 +#define GCREG_FE_DEBUG_CMD_LOW_REG_LSB 0 +#define GCREG_FE_DEBUG_CMD_LOW_REG_BLK 0 +#define GCREG_FE_DEBUG_CMD_LOW_REG_Count 1 +#define GCREG_FE_DEBUG_CMD_LOW_REG_FieldMask 0xFFFFFFFF +#define GCREG_FE_DEBUG_CMD_LOW_REG_ReadMask 0xFFFFFFFF +#define GCREG_FE_DEBUG_CMD_LOW_REG_WriteMask 0x00000000 +#define GCREG_FE_DEBUG_CMD_LOW_REG_ResetValue 0x00000000 + +/* Command register used by CmdState. */ +#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG 31 : 0 +#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG_End 31 +#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG_Start 0 +#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG_Type U32 + +/******************************************************************************* +** Register gcregFEDebugCmdHiReg +*/ + +#define GCREG_FE_DEBUG_CMD_HI_REG_Address 0x0066C +#define GCREG_FE_DEBUG_CMD_HI_REG_MSB 15 +#define GCREG_FE_DEBUG_CMD_HI_REG_LSB 0 +#define GCREG_FE_DEBUG_CMD_HI_REG_BLK 0 +#define GCREG_FE_DEBUG_CMD_HI_REG_Count 1 +#define GCREG_FE_DEBUG_CMD_HI_REG_FieldMask 0xFFFFFFFF +#define GCREG_FE_DEBUG_CMD_HI_REG_ReadMask 0xFFFFFFFF +#define GCREG_FE_DEBUG_CMD_HI_REG_WriteMask 0x00000000 +#define GCREG_FE_DEBUG_CMD_HI_REG_ResetValue 0x00000000 + +/* Command register used by CmdState. */ +#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG 31 : 0 +#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG_End 31 +#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG_Start 0 +#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG_Type U32 + +/******************************************************************************* +** State gcregMMUSafeAddress +*/ + +/* A 64-byte address that will acts as a 'safe' zone. Any address that would +** cause an exception is routed to this safe zone. Reads will happend and +** writes will go to this address, but with a write-enable of 0. This +** register can only be programmed once after a reset - any attempt to write +** to this register after the initial write-after-reset will be ignored. +*/ + +#define gcregMMUSafeAddressRegAddrs 0x0060 +#define GCREG_MMU_SAFE_ADDRESS_MSB 15 +#define GCREG_MMU_SAFE_ADDRESS_LSB 0 +#define GCREG_MMU_SAFE_ADDRESS_BLK 0 +#define GCREG_MMU_SAFE_ADDRESS_Count 1 +#define GCREG_MMU_SAFE_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_MMU_SAFE_ADDRESS_ReadMask 0xFFFFFFC0 +#define GCREG_MMU_SAFE_ADDRESS_WriteMask 0xFFFFFFC0 +#define GCREG_MMU_SAFE_ADDRESS_ResetValue 0x00000000 + +#define GCREG_MMU_SAFE_ADDRESS_ADDRESS 31 : 0 +#define GCREG_MMU_SAFE_ADDRESS_ADDRESS_End 31 +#define GCREG_MMU_SAFE_ADDRESS_ADDRESS_Start 0 +#define GCREG_MMU_SAFE_ADDRESS_ADDRESS_Type U32 + +/******************************************************************************* +** State gcregMMUConfiguration +*/ + +/* This register controls the master TLB of the MMU. */ + +#define gcregMMUConfigurationRegAddrs 0x0061 +#define GCREG_MMU_CONFIGURATION_MSB 15 +#define GCREG_MMU_CONFIGURATION_LSB 0 +#define GCREG_MMU_CONFIGURATION_BLK 0 +#define GCREG_MMU_CONFIGURATION_Count 1 +#define GCREG_MMU_CONFIGURATION_FieldMask 0xFFFFFD99 +#define GCREG_MMU_CONFIGURATION_ReadMask 0xFFFFFD99 +#define GCREG_MMU_CONFIGURATION_WriteMask 0xFFFFFD99 +#define GCREG_MMU_CONFIGURATION_ResetValue 0x00000000 + +/* Upper bits of the page aligned (depending on the mode) master TLB. */ +#define GCREG_MMU_CONFIGURATION_ADDRESS 31 : 10 +#define GCREG_MMU_CONFIGURATION_ADDRESS_End 31 +#define GCREG_MMU_CONFIGURATION_ADDRESS_Start 10 +#define GCREG_MMU_CONFIGURATION_ADDRESS_Type U22 + +/* Mask for Address field. */ +#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS 8 : 8 +#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_End 8 +#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_Start 8 +#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_Type U01 +#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_ENABLED 0x0 +#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_MASKED 0x1 + +/* Mask Flush field. */ +#define GCREG_MMU_CONFIGURATION_MASK_FLUSH 7 : 7 +#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_End 7 +#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_Start 7 +#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_Type U01 +#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_ENABLED 0x0 +#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_MASKED 0x1 + +/* Flush the MMU caches. */ +#define GCREG_MMU_CONFIGURATION_FLUSH 4 : 4 +#define GCREG_MMU_CONFIGURATION_FLUSH_End 4 +#define GCREG_MMU_CONFIGURATION_FLUSH_Start 4 +#define GCREG_MMU_CONFIGURATION_FLUSH_Type U01 +#define GCREG_MMU_CONFIGURATION_FLUSH_FLUSH 0x1 + +/* Mask Mode field. */ +#define GCREG_MMU_CONFIGURATION_MASK_MODE 3 : 3 +#define GCREG_MMU_CONFIGURATION_MASK_MODE_End 3 +#define GCREG_MMU_CONFIGURATION_MASK_MODE_Start 3 +#define GCREG_MMU_CONFIGURATION_MASK_MODE_Type U01 +#define GCREG_MMU_CONFIGURATION_MASK_MODE_ENABLED 0x0 +#define GCREG_MMU_CONFIGURATION_MASK_MODE_MASKED 0x1 + +/* Set the mode for the Master TLB. */ +#define GCREG_MMU_CONFIGURATION_MODE 0 : 0 +#define GCREG_MMU_CONFIGURATION_MODE_End 0 +#define GCREG_MMU_CONFIGURATION_MODE_Start 0 +#define GCREG_MMU_CONFIGURATION_MODE_Type U01 +/* The Master TLB is 4kB in size and contains 1024 entries. Each page can be ** +** 4kB or 64kB in size. */ +#define GCREG_MMU_CONFIGURATION_MODE_MODE4_K 0x0 +/* The Master TLB is 1kB in size and contains 256 entries. Each page can be ** +** 4kB, 64kB, 1MB or 16MB in size. */ +#define GCREG_MMU_CONFIGURATION_MODE_MODE1_K 0x1 + +struct gcregmmuconfiguration { + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MODE */ + unsigned int master:1; + + /* gcregMMUConfiguration:reserved */ + unsigned int _reserved_1_2:2; + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_MODE */ + unsigned int master_mask:1; + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_FLUSH */ + unsigned int flush:1; + + /* gcregMMUConfiguration:reserved */ + unsigned int _reserved_5_6:2; + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_FLUSH */ + unsigned int flush_mask:1; + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_ADDRESS */ + unsigned int address_mask:1; + + /* gcregMMUConfiguration:reserved */ + unsigned int _reserved_9:1; + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_ADDRESS */ + unsigned int address:22; +}; + +static const struct gcregmmuconfiguration gcregmmu_flush = { + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MODE */ + 0, + + /* gcregMMUConfiguration:reserved */ + 0, + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_MODE */ + GCREG_MMU_CONFIGURATION_MASK_MODE_MASKED, + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_FLUSH */ + GCREG_MMU_CONFIGURATION_FLUSH_FLUSH, + + /* gcregMMUConfiguration:reserved */ + 0, + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_FLUSH */ + GCREG_MMU_CONFIGURATION_MASK_FLUSH_ENABLED, + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_ADDRESS */ + GCREG_MMU_CONFIGURATION_MASK_ADDRESS_MASKED, + + /* gcregMMUConfiguration:reserved */ + 0, + + /* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_ADDRESS */ + 0 +}; + +/******************************************************************************* +** Register gcregMMUStatus +*/ + +/* Status register that holds which MMU generated an exception. */ + +#define GCREG_MMU_STATUS_Address 0x00188 +#define GCREG_MMU_STATUS_MSB 15 +#define GCREG_MMU_STATUS_LSB 0 +#define GCREG_MMU_STATUS_BLK 0 +#define GCREG_MMU_STATUS_Count 1 +#define GCREG_MMU_STATUS_FieldMask 0x00003333 +#define GCREG_MMU_STATUS_ReadMask 0x00003333 +#define GCREG_MMU_STATUS_WriteMask 0x00000000 +#define GCREG_MMU_STATUS_ResetValue 0x00000000 + +/* MMU 3 caused an exception and the fourth gcregMMUException register holds ** +** the offending address. */ +#define GCREG_MMU_STATUS_EXCEPTION3 13 : 12 +#define GCREG_MMU_STATUS_EXCEPTION3_End 13 +#define GCREG_MMU_STATUS_EXCEPTION3_Start 12 +#define GCREG_MMU_STATUS_EXCEPTION3_Type U02 +#define GCREG_MMU_STATUS_EXCEPTION3_SLAVE_NOT_PRESENT 0x1 +#define GCREG_MMU_STATUS_EXCEPTION3_PAGE_NOT_PRESENT 0x2 +#define GCREG_MMU_STATUS_EXCEPTION3_WRITE_VIOLATION 0x3 + +/* MMU 2 caused an exception and the third gcregMMUException register holds ** +** the offending address. */ +#define GCREG_MMU_STATUS_EXCEPTION2 9 : 8 +#define GCREG_MMU_STATUS_EXCEPTION2_End 9 +#define GCREG_MMU_STATUS_EXCEPTION2_Start 8 +#define GCREG_MMU_STATUS_EXCEPTION2_Type U02 +#define GCREG_MMU_STATUS_EXCEPTION2_SLAVE_NOT_PRESENT 0x1 +#define GCREG_MMU_STATUS_EXCEPTION2_PAGE_NOT_PRESENT 0x2 +#define GCREG_MMU_STATUS_EXCEPTION2_WRITE_VIOLATION 0x3 + +/* MMU 1 caused an exception and the second gcregMMUException register holds ** +** the offending address. */ +#define GCREG_MMU_STATUS_EXCEPTION1 5 : 4 +#define GCREG_MMU_STATUS_EXCEPTION1_End 5 +#define GCREG_MMU_STATUS_EXCEPTION1_Start 4 +#define GCREG_MMU_STATUS_EXCEPTION1_Type U02 +#define GCREG_MMU_STATUS_EXCEPTION1_SLAVE_NOT_PRESENT 0x1 +#define GCREG_MMU_STATUS_EXCEPTION1_PAGE_NOT_PRESENT 0x2 +#define GCREG_MMU_STATUS_EXCEPTION1_WRITE_VIOLATION 0x3 + +/* MMU 0 caused an exception and the first gcregMMUException register holds ** +** the offending address. */ +#define GCREG_MMU_STATUS_EXCEPTION0 1 : 0 +#define GCREG_MMU_STATUS_EXCEPTION0_End 1 +#define GCREG_MMU_STATUS_EXCEPTION0_Start 0 +#define GCREG_MMU_STATUS_EXCEPTION0_Type U02 +#define GCREG_MMU_STATUS_EXCEPTION0_SLAVE_NOT_PRESENT 0x1 +#define GCREG_MMU_STATUS_EXCEPTION0_PAGE_NOT_PRESENT 0x2 +#define GCREG_MMU_STATUS_EXCEPTION0_WRITE_VIOLATION 0x3 + +/******************************************************************************* +** Register gcregMMUControl +*/ + +/* Control register that enables the MMU (only time shot). */ + +#define GCREG_MMU_CONTROL_Address 0x0018C +#define GCREG_MMU_CONTROL_MSB 15 +#define GCREG_MMU_CONTROL_LSB 0 +#define GCREG_MMU_CONTROL_BLK 0 +#define GCREG_MMU_CONTROL_Count 1 +#define GCREG_MMU_CONTROL_FieldMask 0x00000001 +#define GCREG_MMU_CONTROL_ReadMask 0x00000000 +#define GCREG_MMU_CONTROL_WriteMask 0x00000001 +#define GCREG_MMU_CONTROL_ResetValue 0x00000000 + +/* Enable the MMU. For security reasons, once the MMU is enabled it cannot ** +** be disabled anymore. */ +#define GCREG_MMU_CONTROL_ENABLE 0 : 0 +#define GCREG_MMU_CONTROL_ENABLE_End 0 +#define GCREG_MMU_CONTROL_ENABLE_Start 0 +#define GCREG_MMU_CONTROL_ENABLE_Type U01 +#define GCREG_MMU_CONTROL_ENABLE_ENABLE 0x1 + +/******************************************************************************* +** State/Register gcregMMUException (4 in total) +*/ + +/* Up to 4 registers that will hold the original address that generated an +** exception. Use load state form for exception resolution. +*/ + +#define gcregMMUExceptionRegAddrs 0x0064 +#define GCREG_MMU_EXCEPTION_Address 0x00190 +#define GCREG_MMU_EXCEPTION_MSB 15 +#define GCREG_MMU_EXCEPTION_LSB 2 +#define GCREG_MMU_EXCEPTION_BLK 2 +#define GCREG_MMU_EXCEPTION_Count 4 +#define GCREG_MMU_EXCEPTION_FieldMask 0xFFFFFFFF +#define GCREG_MMU_EXCEPTION_ReadMask 0xFFFFFFFF +#define GCREG_MMU_EXCEPTION_WriteMask 0xFFFFFFFF +#define GCREG_MMU_EXCEPTION_ResetValue 0x00000000 + +#define GCREG_MMU_EXCEPTION_ADDRESS 31 : 0 +#define GCREG_MMU_EXCEPTION_ADDRESS_End 31 +#define GCREG_MMU_EXCEPTION_ADDRESS_Start 0 +#define GCREG_MMU_EXCEPTION_ADDRESS_Type U32 + +/******************************************************************************* +** Register gcModulePowerControls +*/ + +/* Control register for module level power controls. */ + +#define GC_MODULE_POWER_CONTROLS_Address 0x00100 +#define GC_MODULE_POWER_CONTROLS_MSB 15 +#define GC_MODULE_POWER_CONTROLS_LSB 0 +#define GC_MODULE_POWER_CONTROLS_BLK 0 +#define GC_MODULE_POWER_CONTROLS_Count 1 +#define GC_MODULE_POWER_CONTROLS_FieldMask 0xFFFF00F7 +#define GC_MODULE_POWER_CONTROLS_ReadMask 0xFFFF00F7 +#define GC_MODULE_POWER_CONTROLS_WriteMask 0xFFFF00F7 +#define GC_MODULE_POWER_CONTROLS_ResetValue 0x00140020 + +/* Enables module level clock gating. */ +#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0 : 0 +#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING_End 0 +#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING_Start 0 +#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING_Type U01 + +/* Disables module level clock gating for stall condition. */ +#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 1 : 1 +#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_End 1 +#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_Start 1 +#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_Type U01 + +/* Disables module level clock gating for starve/idle condition. */ +#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 2 : 2 +#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_End 2 +#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_Start 2 +#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_Type U01 + +/* Number of clock cycles to wait after turning on the clock. */ +#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER 7 : 4 +#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER_End 7 +#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER_Start 4 +#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER_Type U04 + +/* Counter value for clock gating the module if the module is idle for this ** +** amount of clock cycles. */ +#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER 31 : 16 +#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER_End 31 +#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER_Start 16 +#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER_Type U16 + +/******************************************************************************* +** Register gcModulePowerModuleControl +*/ + +/* Module level control registers. */ + +#define GC_MODULE_POWER_MODULE_CONTROL_Address 0x00104 +#define GC_MODULE_POWER_MODULE_CONTROL_MSB 15 +#define GC_MODULE_POWER_MODULE_CONTROL_LSB 0 +#define GC_MODULE_POWER_MODULE_CONTROL_BLK 0 +#define GC_MODULE_POWER_MODULE_CONTROL_Count 1 +#define GC_MODULE_POWER_MODULE_CONTROL_FieldMask 0x00000007 +#define GC_MODULE_POWER_MODULE_CONTROL_ReadMask 0x00000007 +#define GC_MODULE_POWER_MODULE_CONTROL_WriteMask 0x00000007 +#define GC_MODULE_POWER_MODULE_CONTROL_ResetValue 0x00000000 + +/* Disables module level clock gating for FE. */ +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE 0 : 0 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE_End 0 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE_Start 0 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE_Type U01 + +/* Disables module level clock gating for DE. */ +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE 1 : 1 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE_End 1 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE_Start 1 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE_Type U01 + +/* Disables module level clock gating for PE. */ +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE 2 : 2 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE_End 2 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE_Start 2 +#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE_Type U01 + +/******************************************************************************* +** Register gcModulePowerModuleStatus +*/ + +/* Module level control status. */ + +#define GC_MODULE_POWER_MODULE_STATUS_Address 0x00108 +#define GC_MODULE_POWER_MODULE_STATUS_MSB 15 +#define GC_MODULE_POWER_MODULE_STATUS_LSB 0 +#define GC_MODULE_POWER_MODULE_STATUS_BLK 0 +#define GC_MODULE_POWER_MODULE_STATUS_Count 1 +#define GC_MODULE_POWER_MODULE_STATUS_FieldMask 0x00000007 +#define GC_MODULE_POWER_MODULE_STATUS_ReadMask 0x00000007 +#define GC_MODULE_POWER_MODULE_STATUS_WriteMask 0x00000000 +#define GC_MODULE_POWER_MODULE_STATUS_ResetValue 0x00000000 + +/* Module level clock gating is ON for FE. */ +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0 : 0 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE_End 0 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE_Start 0 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE_Type U01 + +/* Module level clock gating is ON for DE. */ +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE 1 : 1 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE_End 1 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE_Start 1 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE_Type U01 + +/* Module level clock gating is ON for PE. */ +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE 2 : 2 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE_End 2 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE_Start 2 +#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE_Type U01 + +/******************************************************************************* +** State gcregSrcAddress +*/ + +/* 32-bit aligned base address of the source surface. */ + +#define gcregSrcAddressRegAddrs 0x0480 +#define GCREG_SRC_ADDRESS_MSB 15 +#define GCREG_SRC_ADDRESS_LSB 0 +#define GCREG_SRC_ADDRESS_BLK 0 +#define GCREG_SRC_ADDRESS_Count 1 +#define GCREG_SRC_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_SRC_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_SRC_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_SRC_ADDRESS_ResetValue 0x00000000 + +#define GCREG_SRC_ADDRESS_ADDRESS 31 : 0 +#define GCREG_SRC_ADDRESS_ADDRESS_End 30 +#define GCREG_SRC_ADDRESS_ADDRESS_Start 0 +#define GCREG_SRC_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregSrcStride +*/ + +/* Stride of the source surface in bytes. To calculate the stride multiply +** the surface width in pixels (8-pixel aligned) by the number of bytes per +** pixel. +*/ + +#define gcregSrcStrideRegAddrs 0x0481 +#define GCREG_SRC_STRIDE_MSB 15 +#define GCREG_SRC_STRIDE_LSB 0 +#define GCREG_SRC_STRIDE_BLK 0 +#define GCREG_SRC_STRIDE_Count 1 +#define GCREG_SRC_STRIDE_FieldMask 0x0003FFFF +#define GCREG_SRC_STRIDE_ReadMask 0x0003FFFC +#define GCREG_SRC_STRIDE_WriteMask 0x0003FFFC +#define GCREG_SRC_STRIDE_ResetValue 0x00000000 + +#define GCREG_SRC_STRIDE_STRIDE 17 : 0 +#define GCREG_SRC_STRIDE_STRIDE_End 17 +#define GCREG_SRC_STRIDE_STRIDE_Start 0 +#define GCREG_SRC_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State gcregSrcRotationConfig +*/ + +/* 90 degree rotation configuration for the source surface. Width field +** specifies the width of the surface in pixels. +*/ + +#define gcregSrcRotationConfigRegAddrs 0x0482 +#define GCREG_SRC_ROTATION_CONFIG_MSB 15 +#define GCREG_SRC_ROTATION_CONFIG_LSB 0 +#define GCREG_SRC_ROTATION_CONFIG_BLK 0 +#define GCREG_SRC_ROTATION_CONFIG_Count 1 +#define GCREG_SRC_ROTATION_CONFIG_FieldMask 0x0001FFFF +#define GCREG_SRC_ROTATION_CONFIG_ReadMask 0x0001FFFF +#define GCREG_SRC_ROTATION_CONFIG_WriteMask 0x0001FFFF +#define GCREG_SRC_ROTATION_CONFIG_ResetValue 0x00000000 + +#define GCREG_SRC_ROTATION_CONFIG_WIDTH 15 : 0 +#define GCREG_SRC_ROTATION_CONFIG_WIDTH_End 15 +#define GCREG_SRC_ROTATION_CONFIG_WIDTH_Start 0 +#define GCREG_SRC_ROTATION_CONFIG_WIDTH_Type U16 + +#define GCREG_SRC_ROTATION_CONFIG_ROTATION 16 : 16 +#define GCREG_SRC_ROTATION_CONFIG_ROTATION_End 16 +#define GCREG_SRC_ROTATION_CONFIG_ROTATION_Start 16 +#define GCREG_SRC_ROTATION_CONFIG_ROTATION_Type U01 +#define GCREG_SRC_ROTATION_CONFIG_ROTATION_DISABLE 0x0 +#define GCREG_SRC_ROTATION_CONFIG_ROTATION_ENABLE 0x1 + +struct gcregsrcrotationconfig { + /* gcregSrcRotationConfigRegAddrs:GCREG_SRC_ROTATION_CONFIG_WIDTH */ + unsigned int surf_width:16; + + /* gcregSrcRotationConfigRegAddrs:GCREG_SRC_ROTATION_CONFIG_ROTATION */ + unsigned int enable:1; + + /* gcregSrcRotationConfigRegAddrs:reserved */ + unsigned int _reserved_17_31:15; +}; + +/******************************************************************************* +** State gcregSrcConfig +*/ + +/* Source surface configuration register. */ + +#define gcregSrcConfigRegAddrs 0x0483 +#define GCREG_SRC_CONFIG_MSB 15 +#define GCREG_SRC_CONFIG_LSB 0 +#define GCREG_SRC_CONFIG_BLK 0 +#define GCREG_SRC_CONFIG_Count 1 +#define GCREG_SRC_CONFIG_FieldMask 0xFF31B1FF +#define GCREG_SRC_CONFIG_ReadMask 0xFF31B1FF +#define GCREG_SRC_CONFIG_WriteMask 0xFF31B1FF +#define GCREG_SRC_CONFIG_ResetValue 0x00000000 + +/* Control source endianess. */ +#define GCREG_SRC_CONFIG_ENDIAN_CONTROL 31 : 30 +#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_End 31 +#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_Start 30 +#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_Type U02 +#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_NO_SWAP 0x0 +#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_SWAP_WORD 0x1 +#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_SWAP_DWORD 0x2 + +/* Disable 420 L2 cache NOTE: the field is valid for chips with 420 L2 cache ** +** defined. */ +#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE 29 : 29 +#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_End 29 +#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_Start 29 +#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_Type U01 +#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_ENABLED 0x0 +#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_DISABLED 0x1 + +/* Defines the pixel format of the source surface. */ +#define GCREG_SRC_CONFIG_SOURCE_FORMAT 28 : 24 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_End 28 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_Start 24 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_Type U05 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_X4R4G4B4 0x00 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_A4R4G4B4 0x01 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_X1R5G5B5 0x02 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_A1R5G5B5 0x03 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_R5G6B5 0x04 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_X8R8G8B8 0x05 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 0x06 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_YUY2 0x07 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_UYVY 0x08 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_INDEX8 0x09 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_MONOCHROME 0x0A +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_YV12 0x0F +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_A8 0x10 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_NV12 0x11 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_NV16 0x12 +#define GCREG_SRC_CONFIG_SOURCE_FORMAT_RG16 0x13 + +/* Color channel swizzles. */ +#define GCREG_SRC_CONFIG_SWIZZLE 21 : 20 +#define GCREG_SRC_CONFIG_SWIZZLE_End 21 +#define GCREG_SRC_CONFIG_SWIZZLE_Start 20 +#define GCREG_SRC_CONFIG_SWIZZLE_Type U02 +#define GCREG_SRC_CONFIG_SWIZZLE_ARGB 0x0 +#define GCREG_SRC_CONFIG_SWIZZLE_RGBA 0x1 +#define GCREG_SRC_CONFIG_SWIZZLE_ABGR 0x2 +#define GCREG_SRC_CONFIG_SWIZZLE_BGRA 0x3 + +/* Mono expansion: if 0, transparency color will be 0, otherwise transparency ** +** color will be 1. */ +#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY 15 : 15 +#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_End 15 +#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_Start 15 +#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_Type U01 +#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND 0x0 +#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND 0x1 + +/* Mono expansion or masked blit: stream packing in pixels. Determines how ** +** many horizontal pixels are there per each 32-bit chunk. For example, if ** +** set to Packed8, each 32-bit chunk is 8-pixel wide, which also means that ** +** it defines 4 vertical lines of pixels. */ +#define GCREG_SRC_CONFIG_PACK 13 : 12 +#define GCREG_SRC_CONFIG_PACK_End 13 +#define GCREG_SRC_CONFIG_PACK_Start 12 +#define GCREG_SRC_CONFIG_PACK_Type U02 +#define GCREG_SRC_CONFIG_PACK_PACKED8 0x0 +#define GCREG_SRC_CONFIG_PACK_PACKED16 0x1 +#define GCREG_SRC_CONFIG_PACK_PACKED32 0x2 +#define GCREG_SRC_CONFIG_PACK_UNPACKED 0x3 + +/* Source data location: set to STREAM for mono expansion blits or masked ** +** blits. For mono expansion blits the complete bitmap comes from the command ** +** stream. For masked blits the source data comes from the memory and the ** +** mask from the command stream. */ +#define GCREG_SRC_CONFIG_LOCATION 8 : 8 +#define GCREG_SRC_CONFIG_LOCATION_End 8 +#define GCREG_SRC_CONFIG_LOCATION_Start 8 +#define GCREG_SRC_CONFIG_LOCATION_Type U01 +#define GCREG_SRC_CONFIG_LOCATION_MEMORY 0x0 +#define GCREG_SRC_CONFIG_LOCATION_STREAM 0x1 + +/* Source linear/tiled address computation control. */ +#define GCREG_SRC_CONFIG_TILED 7 : 7 +#define GCREG_SRC_CONFIG_TILED_End 7 +#define GCREG_SRC_CONFIG_TILED_Start 7 +#define GCREG_SRC_CONFIG_TILED_Type U01 +#define GCREG_SRC_CONFIG_TILED_DISABLED 0x0 +#define GCREG_SRC_CONFIG_TILED_ENABLED 0x1 + +/* If set to ABSOLUTE, the source coordinates are treated as absolute ** +** coordinates inside the source surface. If set to RELATIVE, the source ** +** coordinates are treated as the offsets from the destination coordinates ** +** with the source size equal to the size of the destination. */ +#define GCREG_SRC_CONFIG_SRC_RELATIVE 6 : 6 +#define GCREG_SRC_CONFIG_SRC_RELATIVE_End 6 +#define GCREG_SRC_CONFIG_SRC_RELATIVE_Start 6 +#define GCREG_SRC_CONFIG_SRC_RELATIVE_Type U01 +#define GCREG_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE 0x0 +#define GCREG_SRC_CONFIG_SRC_RELATIVE_RELATIVE 0x1 + +struct gcregsrcconfig { + /* gcregSrcConfigRegAddrs:reserved */ + unsigned int _reserved_0_5:6; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_SRC_RELATIVE */ + unsigned int relative:1; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_TILED */ + unsigned int tiled:1; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_LOCATION */ + unsigned int stream:1; + + /* gcregSrcConfigRegAddrs:reserved */ + unsigned int _reserved_9_11:3; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_PACK */ + unsigned int monopack:2; + + /* gcregSrcConfigRegAddrs:reserved */ + unsigned int _reserved_14:1; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_MONO_TRANSPARENCY */ + unsigned int monotransp:1; + + /* gcregSrcConfigRegAddrs:reserved */ + unsigned int _reserved_16_19:4; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_SWIZZLE */ + unsigned int swizzle:2; + + /* gcregSrcConfigRegAddrs:reserved */ + unsigned int _reserved_22_23:2; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_SOURCE_FORMAT */ + unsigned int format:5; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_DISABLE420_L2_CACHE */ + unsigned int disable420L2cache:1; + + /* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_ENDIAN_CONTROL */ + unsigned int endian:2; +}; + +/******************************************************************************* +** State gcregSrcOrigin +*/ + +/* Absolute or relative (see SRC_RELATIVE field of gcregSrcConfig register) X +** and Y coordinates in pixels of the top left corner of the source rectangle +** within the source surface. +*/ + +#define gcregSrcOriginRegAddrs 0x0484 +#define GCREG_SRC_ORIGIN_MSB 15 +#define GCREG_SRC_ORIGIN_LSB 0 +#define GCREG_SRC_ORIGIN_BLK 0 +#define GCREG_SRC_ORIGIN_Count 1 +#define GCREG_SRC_ORIGIN_FieldMask 0xFFFFFFFF +#define GCREG_SRC_ORIGIN_ReadMask 0xFFFFFFFF +#define GCREG_SRC_ORIGIN_WriteMask 0xFFFFFFFF +#define GCREG_SRC_ORIGIN_ResetValue 0x00000000 + +#define GCREG_SRC_ORIGIN_Y 31 : 16 +#define GCREG_SRC_ORIGIN_Y_End 31 +#define GCREG_SRC_ORIGIN_Y_Start 16 +#define GCREG_SRC_ORIGIN_Y_Type U16 + +#define GCREG_SRC_ORIGIN_X 15 : 0 +#define GCREG_SRC_ORIGIN_X_End 15 +#define GCREG_SRC_ORIGIN_X_Start 0 +#define GCREG_SRC_ORIGIN_X_Type U16 + +struct gcregsrcorigin { + /* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_X */ + unsigned int x:16; + + /* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_Y */ + unsigned int y:16; +}; + +static const struct gcregsrcorigin gcregsrcorigin_min = { + /* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_X */ + 0, + + /* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_Y */ + 0 +}; + +/******************************************************************************* +** State gcregSrcSize +*/ + +/* Width and height of the source rectangle in pixels. If the source is +** relative (see SRC_RELATIVE field of gcregSrcConfig register) or a regular +** bitblt is being performed without stretching, this register is ignored and +** the source size is assumed to be the same as the destination. +*/ + +#define gcregSrcSizeRegAddrs 0x0485 +#define GCREG_SRC_SIZE_MSB 15 +#define GCREG_SRC_SIZE_LSB 0 +#define GCREG_SRC_SIZE_BLK 0 +#define GCREG_SRC_SIZE_Count 1 +#define GCREG_SRC_SIZE_FieldMask 0xFFFFFFFF +#define GCREG_SRC_SIZE_ReadMask 0xFFFFFFFF +#define GCREG_SRC_SIZE_WriteMask 0xFFFFFFFF +#define GCREG_SRC_SIZE_ResetValue 0x00000000 + +#define GCREG_SRC_SIZE_Y 31 : 16 +#define GCREG_SRC_SIZE_Y_End 31 +#define GCREG_SRC_SIZE_Y_Start 16 +#define GCREG_SRC_SIZE_Y_Type U16 + +#define GCREG_SRC_SIZE_X 15 : 0 +#define GCREG_SRC_SIZE_X_End 15 +#define GCREG_SRC_SIZE_X_Start 0 +#define GCREG_SRC_SIZE_X_Type U16 + +struct gcregsrcsize { + /* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_X */ + unsigned int width:16; + + /* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_Y */ + unsigned int height:16; +}; + +static const struct gcregsrcsize gcregsrcsize_max = { + /* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_X */ + 32767, + + /* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_Y */ + 32767 +}; + +/******************************************************************************* +** State gcregSrcColorBg +*/ + +/* In mono expansion defines the source color if the mono pixel is 0. The color +** must be set in A8R8G8B8 format. In color blits defines the source +** transparency color and must be of the same format as the source surface. +*/ + +#define gcregSrcColorBgRegAddrs 0x0486 +#define GCREG_SRC_COLOR_BG_MSB 15 +#define GCREG_SRC_COLOR_BG_LSB 0 +#define GCREG_SRC_COLOR_BG_BLK 0 +#define GCREG_SRC_COLOR_BG_Count 1 +#define GCREG_SRC_COLOR_BG_FieldMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_BG_ReadMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_BG_WriteMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_BG_ResetValue 0x00000000 + +#define GCREG_SRC_COLOR_BG_ALPHA 31 : 24 +#define GCREG_SRC_COLOR_BG_ALPHA_End 31 +#define GCREG_SRC_COLOR_BG_ALPHA_Start 24 +#define GCREG_SRC_COLOR_BG_ALPHA_Type U08 + +#define GCREG_SRC_COLOR_BG_RED 23 : 16 +#define GCREG_SRC_COLOR_BG_RED_End 23 +#define GCREG_SRC_COLOR_BG_RED_Start 16 +#define GCREG_SRC_COLOR_BG_RED_Type U08 + +#define GCREG_SRC_COLOR_BG_GREEN 15 : 8 +#define GCREG_SRC_COLOR_BG_GREEN_End 15 +#define GCREG_SRC_COLOR_BG_GREEN_Start 8 +#define GCREG_SRC_COLOR_BG_GREEN_Type U08 + +#define GCREG_SRC_COLOR_BG_BLUE 7 : 0 +#define GCREG_SRC_COLOR_BG_BLUE_End 7 +#define GCREG_SRC_COLOR_BG_BLUE_Start 0 +#define GCREG_SRC_COLOR_BG_BLUE_Type U08 + +/******************************************************************************* +** State gcregSrcColorFg +*/ + +/* In mono expansion defines the source color if the mono pixel is 1. The color +** must be set in A8R8G8B8. +*/ + +#define gcregSrcColorFgRegAddrs 0x0487 +#define GCREG_SRC_COLOR_FG_MSB 15 +#define GCREG_SRC_COLOR_FG_LSB 0 +#define GCREG_SRC_COLOR_FG_BLK 0 +#define GCREG_SRC_COLOR_FG_Count 1 +#define GCREG_SRC_COLOR_FG_FieldMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_FG_ReadMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_FG_WriteMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_FG_ResetValue 0x00000000 + +#define GCREG_SRC_COLOR_FG_ALPHA 31 : 24 +#define GCREG_SRC_COLOR_FG_ALPHA_End 31 +#define GCREG_SRC_COLOR_FG_ALPHA_Start 24 +#define GCREG_SRC_COLOR_FG_ALPHA_Type U08 + +#define GCREG_SRC_COLOR_FG_RED 23 : 16 +#define GCREG_SRC_COLOR_FG_RED_End 23 +#define GCREG_SRC_COLOR_FG_RED_Start 16 +#define GCREG_SRC_COLOR_FG_RED_Type U08 + +#define GCREG_SRC_COLOR_FG_GREEN 15 : 8 +#define GCREG_SRC_COLOR_FG_GREEN_End 15 +#define GCREG_SRC_COLOR_FG_GREEN_Start 8 +#define GCREG_SRC_COLOR_FG_GREEN_Type U08 + +#define GCREG_SRC_COLOR_FG_BLUE 7 : 0 +#define GCREG_SRC_COLOR_FG_BLUE_End 7 +#define GCREG_SRC_COLOR_FG_BLUE_Start 0 +#define GCREG_SRC_COLOR_FG_BLUE_Type U08 + +/******************************************************************************* +** State gcregStretchFactorLow +*/ + +#define gcregStretchFactorLowRegAddrs 0x0488 +#define GCREG_STRETCH_FACTOR_LOW_MSB 15 +#define GCREG_STRETCH_FACTOR_LOW_LSB 0 +#define GCREG_STRETCH_FACTOR_LOW_BLK 0 +#define GCREG_STRETCH_FACTOR_LOW_Count 1 +#define GCREG_STRETCH_FACTOR_LOW_FieldMask 0x7FFFFFFF +#define GCREG_STRETCH_FACTOR_LOW_ReadMask 0x7FFFFFFF +#define GCREG_STRETCH_FACTOR_LOW_WriteMask 0x7FFFFFFF +#define GCREG_STRETCH_FACTOR_LOW_ResetValue 0x00000000 + +/* Horizontal stretch factor in 15.16 fixed point format. The value is ** +** calculated using the following formula: factor = ((srcWidth - 1) << 16) / ** +** (dstWidth - 1). Stretch blit uses only the integer part of the value, ** +** while Filter blit uses all 31 bits. */ +#define GCREG_STRETCH_FACTOR_LOW_X 30 : 0 +#define GCREG_STRETCH_FACTOR_LOW_X_End 30 +#define GCREG_STRETCH_FACTOR_LOW_X_Start 0 +#define GCREG_STRETCH_FACTOR_LOW_X_Type U31 + +/******************************************************************************* +** State gcregStretchFactorHigh +*/ + +#define gcregStretchFactorHighRegAddrs 0x0489 +#define GCREG_STRETCH_FACTOR_HIGH_MSB 15 +#define GCREG_STRETCH_FACTOR_HIGH_LSB 0 +#define GCREG_STRETCH_FACTOR_LOW_HIGH_BLK 0 +#define GCREG_STRETCH_FACTOR_HIGH_Count 1 +#define GCREG_STRETCH_FACTOR_HIGH_FieldMask 0x7FFFFFFF +#define GCREG_STRETCH_FACTOR_HIGH_ReadMask 0x7FFFFFFF +#define GCREG_STRETCH_FACTOR_HIGH_WriteMask 0x7FFFFFFF +#define GCREG_STRETCH_FACTOR_HIGH_ResetValue 0x00000000 + +/* Vertical stretch factor in 15.16 fixed point format. The value is ** +** calculated using the following formula: factor = ((srcHeight - 1) << 16) / ** +** (dstHeight - 1). Stretch blit uses only the integer part of the value, ** +** while Filter blit uses all 31 bits. */ +#define GCREG_STRETCH_FACTOR_HIGH_Y 30 : 0 +#define GCREG_STRETCH_FACTOR_HIGH_Y_End 30 +#define GCREG_STRETCH_FACTOR_HIGH_Y_Start 0 +#define GCREG_STRETCH_FACTOR_HIGH_Y_Type U31 + +/******************************************************************************* +** State gcregDestAddress +*/ + +/* 32-bit aligned base address of the destination surface. */ + +#define gcregDestAddressRegAddrs 0x048A +#define GCREG_DEST_ADDRESS_MSB 15 +#define GCREG_DEST_ADDRESS_LSB 0 +#define GCREG_DEST_ADDRESS_BLK 0 +#define GCREG_DEST_ADDRESS_Count 1 +#define GCREG_DEST_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_DEST_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_DEST_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_DEST_ADDRESS_ResetValue 0x00000000 + +#define GCREG_DEST_ADDRESS_ADDRESS 31 : 0 +#define GCREG_DEST_ADDRESS_ADDRESS_End 30 +#define GCREG_DEST_ADDRESS_ADDRESS_Start 0 +#define GCREG_DEST_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregDestStride +*/ + +/* Stride of the destination surface in bytes. To calculate the stride +** multiply the surface width in pixels (8-pixel aligned) by the number of +** bytes per pixel. +*/ + +#define gcregDestStrideRegAddrs 0x048B +#define GCREG_DEST_STRIDE_MSB 15 +#define GCREG_DEST_STRIDE_LSB 0 +#define GCREG_DEST_STRIDE_BLK 0 +#define GCREG_DEST_STRIDE_Count 1 +#define GCREG_DEST_STRIDE_FieldMask 0x0003FFFF +#define GCREG_DEST_STRIDE_ReadMask 0x0003FFFC +#define GCREG_DEST_STRIDE_WriteMask 0x0003FFFC +#define GCREG_DEST_STRIDE_ResetValue 0x00000000 + +#define GCREG_DEST_STRIDE_STRIDE 17 : 0 +#define GCREG_DEST_STRIDE_STRIDE_End 17 +#define GCREG_DEST_STRIDE_STRIDE_Start 0 +#define GCREG_DEST_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State gcregDestRotationConfig +*/ + +/* 90 degree rotation configuration for the destination surface. Width field +** specifies the width of the surface in pixels. +*/ + +#define gcregDestRotationConfigRegAddrs 0x048C +#define GCREG_DEST_ROTATION_CONFIG_MSB 15 +#define GCREG_DEST_ROTATION_CONFIG_LSB 0 +#define GCREG_DEST_ROTATION_CONFIG_BLK 0 +#define GCREG_DEST_ROTATION_CONFIG_Count 1 +#define GCREG_DEST_ROTATION_CONFIG_FieldMask 0x0001FFFF +#define GCREG_DEST_ROTATION_CONFIG_ReadMask 0x0001FFFF +#define GCREG_DEST_ROTATION_CONFIG_WriteMask 0x0001FFFF +#define GCREG_DEST_ROTATION_CONFIG_ResetValue 0x00000000 + +#define GCREG_DEST_ROTATION_CONFIG_WIDTH 15 : 0 +#define GCREG_DEST_ROTATION_CONFIG_WIDTH_End 15 +#define GCREG_DEST_ROTATION_CONFIG_WIDTH_Start 0 +#define GCREG_DEST_ROTATION_CONFIG_WIDTH_Type U16 + +#define GCREG_DEST_ROTATION_CONFIG_ROTATION 16 : 16 +#define GCREG_DEST_ROTATION_CONFIG_ROTATION_End 16 +#define GCREG_DEST_ROTATION_CONFIG_ROTATION_Start 16 +#define GCREG_DEST_ROTATION_CONFIG_ROTATION_Type U01 +#define GCREG_DEST_ROTATION_CONFIG_ROTATION_DISABLE 0x0 +#define GCREG_DEST_ROTATION_CONFIG_ROTATION_ENABLE 0x1 + +struct gcregdstrotationconfig { + /* gcregDestRotationConfigRegAddrs:GCREG_DEST_ROTATION_CONFIG_WIDTH */ + unsigned int surf_width:16; + + /* gcregDestRotationConfigRegAddrs:GCREG_DEST_ROTATION_CONFIG_ROTATION*/ + unsigned int enable:1; + + /* gcregDestRotationConfigRegAddrs:reserved */ + unsigned int _reserved_17_31:15; +}; + +/******************************************************************************* +** State gcregDestConfig +*/ + +/* Destination surface configuration register. */ + +#define gcregDestConfigRegAddrs 0x048D +#define GCREG_DEST_CONFIG_MSB 15 +#define GCREG_DEST_CONFIG_LSB 0 +#define GCREG_DEST_CONFIG_BLK 0 +#define GCREG_DEST_CONFIG_Count 1 +#define GCREG_DEST_CONFIG_FieldMask 0x0733F11F +#define GCREG_DEST_CONFIG_ReadMask 0x0733F11F +#define GCREG_DEST_CONFIG_WriteMask 0x0733F11F +#define GCREG_DEST_CONFIG_ResetValue 0x00000000 + +/* MinorTile. */ +#define GCREG_DEST_CONFIG_MINOR_TILED 26 : 26 +#define GCREG_DEST_CONFIG_MINOR_TILED_End 26 +#define GCREG_DEST_CONFIG_MINOR_TILED_Start 26 +#define GCREG_DEST_CONFIG_MINOR_TILED_Type U01 +#define GCREG_DEST_CONFIG_MINOR_TILED_DISABLED 0x0 +#define GCREG_DEST_CONFIG_MINOR_TILED_ENABLED 0x1 + +/* Performance fix for de. */ +#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX 25 : 25 +#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_End 25 +#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_Start 25 +#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_Type U01 +#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_DISABLED 0x1 +#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_ENABLED 0x0 + +/* Control GDI Strecth Blit. */ +#define GCREG_DEST_CONFIG_GDI_STRE 24 : 24 +#define GCREG_DEST_CONFIG_GDI_STRE_End 24 +#define GCREG_DEST_CONFIG_GDI_STRE_Start 24 +#define GCREG_DEST_CONFIG_GDI_STRE_Type U01 +#define GCREG_DEST_CONFIG_GDI_STRE_DISABLED 0x0 +#define GCREG_DEST_CONFIG_GDI_STRE_ENABLED 0x1 + +/* Control destination endianess. */ +#define GCREG_DEST_CONFIG_ENDIAN_CONTROL 21 : 20 +#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_End 21 +#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_Start 20 +#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_Type U02 +#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_NO_SWAP 0x0 +#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_SWAP_WORD 0x1 +#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_SWAP_DWORD 0x2 + +/* Color channel swizzles. */ +#define GCREG_DEST_CONFIG_SWIZZLE 17 : 16 +#define GCREG_DEST_CONFIG_SWIZZLE_End 17 +#define GCREG_DEST_CONFIG_SWIZZLE_Start 16 +#define GCREG_DEST_CONFIG_SWIZZLE_Type U02 +#define GCREG_DEST_CONFIG_SWIZZLE_ARGB 0x0 +#define GCREG_DEST_CONFIG_SWIZZLE_RGBA 0x1 +#define GCREG_DEST_CONFIG_SWIZZLE_ABGR 0x2 +#define GCREG_DEST_CONFIG_SWIZZLE_BGRA 0x3 + +/* Determines the type of primitive to be rendered. BIT_BLT_REVERSED and ** +** INVALID_COMMAND values are defined for internal use and should not be ** +** used. */ +#define GCREG_DEST_CONFIG_COMMAND 15 : 12 +#define GCREG_DEST_CONFIG_COMMAND_End 15 +#define GCREG_DEST_CONFIG_COMMAND_Start 12 +#define GCREG_DEST_CONFIG_COMMAND_Type U04 +#define GCREG_DEST_CONFIG_COMMAND_CLEAR 0x0 +#define GCREG_DEST_CONFIG_COMMAND_LINE 0x1 +#define GCREG_DEST_CONFIG_COMMAND_BIT_BLT 0x2 +#define GCREG_DEST_CONFIG_COMMAND_BIT_BLT_REVERSED 0x3 +#define GCREG_DEST_CONFIG_COMMAND_STRETCH_BLT 0x4 +#define GCREG_DEST_CONFIG_COMMAND_HOR_FILTER_BLT 0x5 +#define GCREG_DEST_CONFIG_COMMAND_VER_FILTER_BLT 0x6 +#define GCREG_DEST_CONFIG_COMMAND_ONE_PASS_FILTER_BLT 0x7 +#define GCREG_DEST_CONFIG_COMMAND_MULTI_SOURCE_BLT 0x8 + +/* Destination linear/tiled address computation control. Reserved field for ** +** future expansion. */ +#define GCREG_DEST_CONFIG_TILED 8 : 8 +#define GCREG_DEST_CONFIG_TILED_End 8 +#define GCREG_DEST_CONFIG_TILED_Start 8 +#define GCREG_DEST_CONFIG_TILED_Type U01 +#define GCREG_DEST_CONFIG_TILED_DISABLED 0x0 +#define GCREG_DEST_CONFIG_TILED_ENABLED 0x1 + +/* Defines the pixel format of the destination surface. */ +#define GCREG_DEST_CONFIG_FORMAT 4 : 0 +#define GCREG_DEST_CONFIG_FORMAT_End 4 +#define GCREG_DEST_CONFIG_FORMAT_Start 0 +#define GCREG_DEST_CONFIG_FORMAT_Type U05 +#define GCREG_DEST_CONFIG_FORMAT_X4R4G4B4 0x00 +#define GCREG_DEST_CONFIG_FORMAT_A4R4G4B4 0x01 +#define GCREG_DEST_CONFIG_FORMAT_X1R5G5B5 0x02 +#define GCREG_DEST_CONFIG_FORMAT_A1R5G5B5 0x03 +#define GCREG_DEST_CONFIG_FORMAT_R5G6B5 0x04 +#define GCREG_DEST_CONFIG_FORMAT_X8R8G8B8 0x05 +#define GCREG_DEST_CONFIG_FORMAT_A8R8G8B8 0x06 +#define GCREG_DEST_CONFIG_FORMAT_YUY2 0x07 +#define GCREG_DEST_CONFIG_FORMAT_UYVY 0x08 +#define GCREG_DEST_CONFIG_FORMAT_INDEX8 0x09 +#define GCREG_DEST_CONFIG_FORMAT_MONOCHROME 0x0A +#define GCREG_DEST_CONFIG_FORMAT_YV12 0x0F +#define GCREG_DEST_CONFIG_FORMAT_A8 0x10 +#define GCREG_DEST_CONFIG_FORMAT_NV12 0x11 +#define GCREG_DEST_CONFIG_FORMAT_NV16 0x12 +#define GCREG_DEST_CONFIG_FORMAT_RG16 0x13 + +struct gcregdstconfig { + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_FORMAT */ + unsigned int format:5; + + /* gcregDestConfigRegAddrs:reserved */ + unsigned int _reserved_5_7:3; + + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_TILED */ + unsigned int tiled:1; + + /* gcregDestConfigRegAddrs:reserved */ + unsigned int _reserved_9_11:3; + + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_COMMAND */ + unsigned int command:4; + + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_SWIZZLE */ + unsigned int swizzle:2; + + /* gcregDestConfigRegAddrs:reserved */ + unsigned int _reserved_18_19:2; + + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_ENDIAN_CONTROL */ + unsigned int endian:2; + + /* gcregDestConfigRegAddrs:reserved */ + unsigned int _reserved_22_23:2; + + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_GDI_STRE */ + unsigned int gdi:1; + + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_INTER_TILE_PER_FIX */ + unsigned int inner_tile_fix:1; + + /* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_MINOR_TILED */ + unsigned int minor_tile:1; + + /* gcregDestConfigRegAddrs:reserved */ + unsigned int _reserved_27_31:5; +}; + +/******************************************************************************* +** State gcregFilterKernel +*/ + +/* Filter blit coefficient table. The algorithm uses 5 bits of pixel +** coordinate's fraction to index the kernel array, which makes it a 32-entry +** array. Each entry consists of 9 kernel values. In practice we store only a +** half of the table, because the other half is a mirror of the first, +** therefore: +** rows_to_store = 32 / 2 + 1 = 17 +** values_to_store = rows_to_store * 9 = 153 +** even_value_count = (values_to_store + 1) & ~1 = 154 +** dword_count = even_value_count / 2 = 77 +*/ + +#define gcregFilterKernelRegAddrs 0x0600 +#define GCREG_FILTER_KERNEL_MSB 15 +#define GCREG_FILTER_KERNEL_LSB 7 +#define GCREG_FILTER_KERNEL_BLK 7 +#define GCREG_FILTER_KERNEL_Count 128 +#define GCREG_FILTER_KERNEL_FieldMask 0xFFFFFFFF +#define GCREG_FILTER_KERNEL_ReadMask 0xFFFFFFFF +#define GCREG_FILTER_KERNEL_WriteMask 0xFFFFFFFF +#define GCREG_FILTER_KERNEL_ResetValue 0x00000000 + +#define GCREG_FILTER_KERNEL_COEFFICIENT0 15 : 0 +#define GCREG_FILTER_KERNEL_COEFFICIENT0_End 15 +#define GCREG_FILTER_KERNEL_COEFFICIENT0_Start 0 +#define GCREG_FILTER_KERNEL_COEFFICIENT0_Type U16 + +#define GCREG_FILTER_KERNEL_COEFFICIENT1 31 : 16 +#define GCREG_FILTER_KERNEL_COEFFICIENT1_End 31 +#define GCREG_FILTER_KERNEL_COEFFICIENT1_Start 16 +#define GCREG_FILTER_KERNEL_COEFFICIENT1_Type U16 + +/******************************************************************************* +** State gcregHoriFilterKernel +*/ + +/* One Pass filter Filter blit hori coefficient table. */ + +#define gcregHoriFilterKernelRegAddrs 0x0A00 +#define GCREG_HORI_FILTER_KERNEL_MSB 15 +#define GCREG_HORI_FILTER_KERNEL_LSB 7 +#define GCREG_HORI_FILTER_KERNEL_BLK 7 +#define GCREG_HORI_FILTER_KERNEL_Count 128 +#define GCREG_HORI_FILTER_KERNEL_FieldMask 0xFFFFFFFF +#define GCREG_HORI_FILTER_KERNEL_ReadMask 0xFFFFFFFF +#define GCREG_HORI_FILTER_KERNEL_WriteMask 0xFFFFFFFF +#define GCREG_HORI_FILTER_KERNEL_ResetValue 0x00000000 + +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0 15 : 0 +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0_End 15 +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0_Start 0 +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0_Type U16 + +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1 31 : 16 +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1_End 31 +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1_Start 16 +#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1_Type U16 + +/******************************************************************************* +** State gcregVertiFilterKernel +*/ + +/* One Pass Filter blit vertical coefficient table. */ + +#define gcregVertiFilterKernelRegAddrs 0x0A80 +#define GCREG_VERTI_FILTER_KERNEL_MSB 15 +#define GCREG_VERTI_FILTER_KERNEL_LSB 7 +#define GCREG_VERTI_FILTER_KERNEL_BLK 7 +#define GCREG_VERTI_FILTER_KERNEL_Count 128 +#define GCREG_VERTI_FILTER_KERNEL_FieldMask 0xFFFFFFFF +#define GCREG_VERTI_FILTER_KERNEL_ReadMask 0xFFFFFFFF +#define GCREG_VERTI_FILTER_KERNEL_WriteMask 0xFFFFFFFF +#define GCREG_VERTI_FILTER_KERNEL_ResetValue 0x00000000 + +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0 15 : 0 +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0_End 15 +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0_Start 0 +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0_Type U16 + +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1 31 : 16 +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1_End 31 +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1_Start 16 +#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1_Type U16 + +/******************************************************************************* +** State gcregVRSourceImageLow +*/ + +/* Bounding box of the source image. */ + +#define gcregVRSourceImageLowRegAddrs 0x04A6 +#define GCREG_VR_SOURCE_IMAGE_LOW_Address 0x01298 +#define GCREG_VR_SOURCE_IMAGE_LOW_MSB 15 +#define GCREG_VR_SOURCE_IMAGE_LOW_LSB 0 +#define GCREG_VR_SOURCE_IMAGE_LOW_BLK 0 +#define GCREG_VR_SOURCE_IMAGE_LOW_Count 1 +#define GCREG_VR_SOURCE_IMAGE_LOW_FieldMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_IMAGE_LOW_ReadMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_IMAGE_LOW_WriteMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_IMAGE_LOW_ResetValue 0x00000000 + +#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT 15 : 0 +#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT_End 15 +#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT_Start 0 +#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT_Type U16 + +#define GCREG_VR_SOURCE_IMAGE_LOW_TOP 31 : 16 +#define GCREG_VR_SOURCE_IMAGE_LOW_TOP_End 31 +#define GCREG_VR_SOURCE_IMAGE_LOW_TOP_Start 16 +#define GCREG_VR_SOURCE_IMAGE_LOW_TOP_Type U16 + +/******************************************************************************* +** State gcregVRSourceImageHigh +*/ + +#define gcregVRSourceImageHighRegAddrs 0x04A7 +#define GCREG_VR_SOURCE_IMAGE_HIGH_MSB 15 +#define GCREG_VR_SOURCE_IMAGE_HIGH_LSB 0 +#define GCREG_VR_SOURCE_IMAGE_LOW_HIGH_BLK 0 +#define GCREG_VR_SOURCE_IMAGE_HIGH_Count 1 +#define GCREG_VR_SOURCE_IMAGE_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_IMAGE_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_IMAGE_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_IMAGE_HIGH_ResetValue 0x00000000 + +#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT 15 : 0 +#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT_End 15 +#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT_Start 0 +#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT_Type U16 + +#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM 31 : 16 +#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM_End 31 +#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM_Start 16 +#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM_Type U16 + +/******************************************************************************* +** State gcregVRSourceOriginLow +*/ + +/* Fractional origin of the source window to be rendered within the source +** image. +*/ + +#define gcregVRSourceOriginLowRegAddrs 0x04A8 +#define GCREG_VR_SOURCE_ORIGIN_LOW_MSB 15 +#define GCREG_VR_SOURCE_ORIGIN_LOW_LSB 0 +#define GCREG_VR_SOURCE_ORIGIN_LOW_BLK 0 +#define GCREG_VR_SOURCE_ORIGIN_LOW_Count 1 +#define GCREG_VR_SOURCE_ORIGIN_LOW_FieldMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_ORIGIN_LOW_ReadMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_ORIGIN_LOW_WriteMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_ORIGIN_LOW_ResetValue 0x00000000 + +#define GCREG_VR_SOURCE_ORIGIN_LOW_X 31 : 0 +#define GCREG_VR_SOURCE_ORIGIN_LOW_X_End 31 +#define GCREG_VR_SOURCE_ORIGIN_LOW_X_Start 0 +#define GCREG_VR_SOURCE_ORIGIN_LOW_X_Type U32 + +/******************************************************************************* +** State gcregVRSourceOriginHigh +*/ + +#define gcregVRSourceOriginHighRegAddrs 0x04A9 +#define GCREG_VR_SOURCE_ORIGIN_HIGH_MSB 15 +#define GCREG_VR_SOURCE_ORIGIN_HIGH_LSB 0 +#define GCREG_VR_SOURCE_ORIGIN_LOW_HIGH_BLK 0 +#define GCREG_VR_SOURCE_ORIGIN_HIGH_Count 1 +#define GCREG_VR_SOURCE_ORIGIN_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_ORIGIN_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_ORIGIN_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_VR_SOURCE_ORIGIN_HIGH_ResetValue 0x00000000 + +#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y 31 : 0 +#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y_End 31 +#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y_Start 0 +#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y_Type U32 + +/******************************************************************************* +** State gcregVRTargetWindowLow +*/ + +/* Bounding box of the destination window to be rendered within the +** destination image. +*/ + +#define gcregVRTargetWindowLowRegAddrs 0x04AA +#define GCREG_VR_TARGET_WINDOW_LOW_Address 0x012A8 +#define GCREG_VR_TARGET_WINDOW_LOW_MSB 15 +#define GCREG_VR_TARGET_WINDOW_LOW_LSB 0 +#define GCREG_VR_TARGET_WINDOW_LOW_BLK 0 +#define GCREG_VR_TARGET_WINDOW_LOW_Count 1 +#define GCREG_VR_TARGET_WINDOW_LOW_FieldMask 0xFFFFFFFF +#define GCREG_VR_TARGET_WINDOW_LOW_ReadMask 0xFFFFFFFF +#define GCREG_VR_TARGET_WINDOW_LOW_WriteMask 0xFFFFFFFF +#define GCREG_VR_TARGET_WINDOW_LOW_ResetValue 0x00000000 + +#define GCREG_VR_TARGET_WINDOW_LOW_LEFT 15 : 0 +#define GCREG_VR_TARGET_WINDOW_LOW_LEFT_End 15 +#define GCREG_VR_TARGET_WINDOW_LOW_LEFT_Start 0 +#define GCREG_VR_TARGET_WINDOW_LOW_LEFT_Type U16 + +#define GCREG_VR_TARGET_WINDOW_LOW_TOP 31 : 16 +#define GCREG_VR_TARGET_WINDOW_LOW_TOP_End 31 +#define GCREG_VR_TARGET_WINDOW_LOW_TOP_Start 16 +#define GCREG_VR_TARGET_WINDOW_LOW_TOP_Type U16 + +/******************************************************************************* +** State gcregVRTargetWindowHigh +*/ + +#define gcregVRTargetWindowHighRegAddrs 0x04AB +#define GCREG_VR_TARGET_WINDOW_HIGH_MSB 15 +#define GCREG_VR_TARGET_WINDOW_HIGH_LSB 0 +#define GCREG_VR_TARGET_WINDOW_LOW_HIGH_BLK 0 +#define GCREG_VR_TARGET_WINDOW_HIGH_Count 1 +#define GCREG_VR_TARGET_WINDOW_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_VR_TARGET_WINDOW_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_VR_TARGET_WINDOW_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_VR_TARGET_WINDOW_HIGH_ResetValue 0x00000000 + +#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT 15 : 0 +#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT_End 15 +#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT_Start 0 +#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT_Type U16 + +#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM 31 : 16 +#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM_End 31 +#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM_Start 16 +#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM_Type U16 + +/******************************************************************************* +** State gcregVRConfig +*/ + +/* Video Rasterizer kick-off register. */ + +#define gcregVRConfigRegAddrs 0x04A5 +#define GCREG_VR_CONFIG_MSB 15 +#define GCREG_VR_CONFIG_LSB 0 +#define GCREG_VR_CONFIG_BLK 0 +#define GCREG_VR_CONFIG_Count 1 +#define GCREG_VR_CONFIG_FieldMask 0x0000000B +#define GCREG_VR_CONFIG_ReadMask 0x0000000B +#define GCREG_VR_CONFIG_WriteMask 0x0000000B +#define GCREG_VR_CONFIG_ResetValue 0x00000000 + +/* Kick-off command. */ +#define GCREG_VR_CONFIG_START 1 : 0 +#define GCREG_VR_CONFIG_START_End 1 +#define GCREG_VR_CONFIG_START_Start 0 +#define GCREG_VR_CONFIG_START_Type U02 +#define GCREG_VR_CONFIG_START_HORIZONTAL_BLIT 0x0 +#define GCREG_VR_CONFIG_START_VERTICAL_BLIT 0x1 +#define GCREG_VR_CONFIG_START_ONE_PASS_BLIT 0x2 + +#define GCREG_VR_CONFIG_MASK_START 3 : 3 +#define GCREG_VR_CONFIG_MASK_START_End 3 +#define GCREG_VR_CONFIG_MASK_START_Start 3 +#define GCREG_VR_CONFIG_MASK_START_Type U01 +#define GCREG_VR_CONFIG_MASK_START_ENABLED 0x0 +#define GCREG_VR_CONFIG_MASK_START_MASKED 0x1 + +/******************************************************************************* +** State gcregVRConfigEx +*/ + +/* Video Rasterizer configuration register. */ + +#define gcregVRConfigExRegAddrs 0x04B9 +#define GCREG_VR_CONFIG_EX_Address 0x012E4 +#define GCREG_VR_CONFIG_EX_MSB 15 +#define GCREG_VR_CONFIG_EX_LSB 0 +#define GCREG_VR_CONFIG_EX_BLK 0 +#define GCREG_VR_CONFIG_EX_Count 1 +#define GCREG_VR_CONFIG_EX_FieldMask 0x000001FB +#define GCREG_VR_CONFIG_EX_ReadMask 0x000001FB +#define GCREG_VR_CONFIG_EX_WriteMask 0x000001FB +#define GCREG_VR_CONFIG_EX_ResetValue 0x00000000 + +/* Line width in pixels for vertical pass. */ +#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH 1 : 0 +#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_End 1 +#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_Start 0 +#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_Type U02 +#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_AUTO 0x0 +#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_PIXELS16 0x1 +#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_PIXELS32 0x2 + +#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH 3 : 3 +#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_End 3 +#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_Start 3 +#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_Type U01 +#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_ENABLED 0x0 +#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_MASKED 0x1 + +/* one pass filter tap. */ +#define GCREG_VR_CONFIG_EX_FILTER_TAP 7 : 4 +#define GCREG_VR_CONFIG_EX_FILTER_TAP_End 7 +#define GCREG_VR_CONFIG_EX_FILTER_TAP_Start 4 +#define GCREG_VR_CONFIG_EX_FILTER_TAP_Type U04 + +#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP 8 : 8 +#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_End 8 +#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_Start 8 +#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_Type U01 +#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_ENABLED 0x0 +#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_MASKED 0x1 + +/******************************************************************************* +** State gcregBWConfig +*/ + +#define gcregBWConfigRegAddrs 0x04BC +#define GCREG_BW_CONFIG_MSB 15 +#define GCREG_BW_CONFIG_LSB 0 +#define GCREG_BW_CONFIG_BLK 0 +#define GCREG_BW_CONFIG_Count 1 +#define GCREG_BW_CONFIG_FieldMask 0x00009999 +#define GCREG_BW_CONFIG_ReadMask 0x00009999 +#define GCREG_BW_CONFIG_WriteMask 0x00009999 +#define GCREG_BW_CONFIG_ResetValue 0x00000000 + +/* One Pass Filter Block Config. */ +#define GCREG_BW_CONFIG_BLOCK_CONFIG 0 : 0 +#define GCREG_BW_CONFIG_BLOCK_CONFIG_End 0 +#define GCREG_BW_CONFIG_BLOCK_CONFIG_Start 0 +#define GCREG_BW_CONFIG_BLOCK_CONFIG_Type U01 +#define GCREG_BW_CONFIG_BLOCK_CONFIG_AUTO 0x0 +#define GCREG_BW_CONFIG_BLOCK_CONFIG_CUSTOMIZE 0x1 + +#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG 3 : 3 +#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_End 3 +#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_Start 3 +#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_Type U01 +#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_ENABLED 0x0 +#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_MASKED 0x1 + +/* block walk direction in one pass filter blit. */ +#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION 4 : 4 +#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_End 4 +#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_Start 4 +#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_Type U01 +#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_RIGHT_BOTTOM 0x0 +#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_BOTTOM_RIGHT 0x1 + +#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION 7 : 7 +#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_End 7 +#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_Start 7 +#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_Type U01 +#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_ENABLED 0x0 +#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_MASKED 0x1 + +/* block walk direction in one pass filter blit. */ +#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION 8 : 8 +#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_End 8 +#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_Start 8 +#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_Type U01 +#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_RIGHT_BOTTOM 0x0 +#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_BOTTOM_RIGHT 0x1 + +#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION 11 : 11 +#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_End 11 +#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_Start 11 +#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_Type U01 +#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_ENABLED 0x0 +#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_MASKED 0x1 + +/* block walk direction in one pass filter blit. */ +#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION 12 : 12 +#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_End 12 +#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_Start 12 +#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_Type U01 +#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_RIGHT_BOTTOM 0x0 +#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_BOTTOM_RIGHT 0x1 + +#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION 15 : 15 +#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_End 15 +#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_Start 15 +#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_Type U01 +#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_ENABLED 0x0 +#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_MASKED 0x1 + +/******************************************************************************* +** State gcregBWBlockSize +*/ + +/* Walker Block size. */ + +#define gcregBWBlockSizeRegAddrs 0x04BD +#define GCREG_BW_BLOCK_SIZE_MSB 15 +#define GCREG_BW_BLOCK_SIZE_LSB 0 +#define GCREG_BW_BLOCK_SIZE_BLK 0 +#define GCREG_BW_BLOCK_SIZE_Count 1 +#define GCREG_BW_BLOCK_SIZE_FieldMask 0xFFFFFFFF +#define GCREG_BW_BLOCK_SIZE_ReadMask 0xFFFFFFFF +#define GCREG_BW_BLOCK_SIZE_WriteMask 0xFFFFFFFF +#define GCREG_BW_BLOCK_SIZE_ResetValue 0x00000000 + +#define GCREG_BW_BLOCK_SIZE_WIDTH 15 : 0 +#define GCREG_BW_BLOCK_SIZE_WIDTH_End 15 +#define GCREG_BW_BLOCK_SIZE_WIDTH_Start 0 +#define GCREG_BW_BLOCK_SIZE_WIDTH_Type U16 + +#define GCREG_BW_BLOCK_SIZE_HEIGHT 31 : 16 +#define GCREG_BW_BLOCK_SIZE_HEIGHT_End 31 +#define GCREG_BW_BLOCK_SIZE_HEIGHT_Start 16 +#define GCREG_BW_BLOCK_SIZE_HEIGHT_Type U16 + +/******************************************************************************* +** State gcregBWTileSize +*/ + +/* Walker tile size. */ + +#define gcregBWTileSizeRegAddrs 0x04BE +#define GCREG_BW_TILE_SIZE_MSB 15 +#define GCREG_BW_TILE_SIZE_LSB 0 +#define GCREG_BW_TILE_SIZE_BLK 0 +#define GCREG_BW_TILE_SIZE_Count 1 +#define GCREG_BW_TILE_SIZE_FieldMask 0xFFFFFFFF +#define GCREG_BW_TILE_SIZE_ReadMask 0xFFFFFFFF +#define GCREG_BW_TILE_SIZE_WriteMask 0xFFFFFFFF +#define GCREG_BW_TILE_SIZE_ResetValue 0x00000000 + +#define GCREG_BW_TILE_SIZE_WIDTH 15 : 0 +#define GCREG_BW_TILE_SIZE_WIDTH_End 15 +#define GCREG_BW_TILE_SIZE_WIDTH_Start 0 +#define GCREG_BW_TILE_SIZE_WIDTH_Type U16 + +#define GCREG_BW_TILE_SIZE_HEIGHT 31 : 16 +#define GCREG_BW_TILE_SIZE_HEIGHT_End 31 +#define GCREG_BW_TILE_SIZE_HEIGHT_Start 16 +#define GCREG_BW_TILE_SIZE_HEIGHT_Type U16 + +/******************************************************************************* +** State gcregBWBlockMask +*/ + +/* Walker Block Mask. */ + +#define gcregBWBlockMaskRegAddrs 0x04BF +#define GCREG_BW_BLOCK_MASK_MSB 15 +#define GCREG_BW_BLOCK_MASK_LSB 0 +#define GCREG_BW_BLOCK_MASK_BLK 0 +#define GCREG_BW_BLOCK_MASK_Count 1 +#define GCREG_BW_BLOCK_MASK_FieldMask 0xFFFFFFFF +#define GCREG_BW_BLOCK_MASK_ReadMask 0xFFFFFFFF +#define GCREG_BW_BLOCK_MASK_WriteMask 0xFFFFFFFF +#define GCREG_BW_BLOCK_MASK_ResetValue 0x00000000 + +#define GCREG_BW_BLOCK_MASK_HORIZONTAL 15 : 0 +#define GCREG_BW_BLOCK_MASK_HORIZONTAL_End 15 +#define GCREG_BW_BLOCK_MASK_HORIZONTAL_Start 0 +#define GCREG_BW_BLOCK_MASK_HORIZONTAL_Type U16 + +#define GCREG_BW_BLOCK_MASK_VERTICAL 31 : 16 +#define GCREG_BW_BLOCK_MASK_VERTICAL_End 31 +#define GCREG_BW_BLOCK_MASK_VERTICAL_Start 16 +#define GCREG_BW_BLOCK_MASK_VERTICAL_Type U16 + +/******************************************************************************* +** State gcregIndexColorTable +*/ + +/* 256 color entries for the indexed color mode. Colors are assumed to be in +** the destination format and no color conversion is done on the values. +*/ + +#define gcregIndexColorTableRegAddrs 0x0700 +#define GCREG_INDEX_COLOR_TABLE_MSB 15 +#define GCREG_INDEX_COLOR_TABLE_LSB 8 +#define GCREG_INDEX_COLOR_TABLE_BLK 8 +#define GCREG_INDEX_COLOR_TABLE_Count 256 +#define GCREG_INDEX_COLOR_TABLE_FieldMask 0xFFFFFFFF +#define GCREG_INDEX_COLOR_TABLE_ReadMask 0xFFFFFFFF +#define GCREG_INDEX_COLOR_TABLE_WriteMask 0xFFFFFFFF +#define GCREG_INDEX_COLOR_TABLE_ResetValue 0x00000000 + +#define GCREG_INDEX_COLOR_TABLE_ALPHA 31 : 24 +#define GCREG_INDEX_COLOR_TABLE_ALPHA_End 31 +#define GCREG_INDEX_COLOR_TABLE_ALPHA_Start 24 +#define GCREG_INDEX_COLOR_TABLE_ALPHA_Type U08 + +#define GCREG_INDEX_COLOR_TABLE_RED 23 : 16 +#define GCREG_INDEX_COLOR_TABLE_RED_End 23 +#define GCREG_INDEX_COLOR_TABLE_RED_Start 16 +#define GCREG_INDEX_COLOR_TABLE_RED_Type U08 + +#define GCREG_INDEX_COLOR_TABLE_GREEN 15 : 8 +#define GCREG_INDEX_COLOR_TABLE_GREEN_End 15 +#define GCREG_INDEX_COLOR_TABLE_GREEN_Start 8 +#define GCREG_INDEX_COLOR_TABLE_GREEN_Type U08 + +#define GCREG_INDEX_COLOR_TABLE_BLUE 7 : 0 +#define GCREG_INDEX_COLOR_TABLE_BLUE_End 7 +#define GCREG_INDEX_COLOR_TABLE_BLUE_Start 0 +#define GCREG_INDEX_COLOR_TABLE_BLUE_Type U08 + +/******************************************************************************* +** State gcregIndexColorTable32 +*/ + +/* 256 color entries for the indexed color mode. Colors are assumed to be in +** the A8R8G8B8 format and no color conversion is done on the values. This +** register is used only with chips with PE20 feature available. +*/ + +#define gcregIndexColorTable32RegAddrs 0x0D00 +#define GCREG_INDEX_COLOR_TABLE32_MSB 15 +#define GCREG_INDEX_COLOR_TABLE32_LSB 8 +#define GCREG_INDEX_COLOR_TABLE32_BLK 8 +#define GCREG_INDEX_COLOR_TABLE32_Count 256 +#define GCREG_INDEX_COLOR_TABLE32_FieldMask 0xFFFFFFFF +#define GCREG_INDEX_COLOR_TABLE32_ReadMask 0xFFFFFFFF +#define GCREG_INDEX_COLOR_TABLE32_WriteMask 0xFFFFFFFF +#define GCREG_INDEX_COLOR_TABLE32_ResetValue 0x00000000 + +#define GCREG_INDEX_COLOR_TABLE32_ALPHA 31 : 24 +#define GCREG_INDEX_COLOR_TABLE32_ALPHA_End 31 +#define GCREG_INDEX_COLOR_TABLE32_ALPHA_Start 24 +#define GCREG_INDEX_COLOR_TABLE32_ALPHA_Type U08 + +#define GCREG_INDEX_COLOR_TABLE32_RED 23 : 16 +#define GCREG_INDEX_COLOR_TABLE32_RED_End 23 +#define GCREG_INDEX_COLOR_TABLE32_RED_Start 16 +#define GCREG_INDEX_COLOR_TABLE32_RED_Type U08 + +#define GCREG_INDEX_COLOR_TABLE32_GREEN 15 : 8 +#define GCREG_INDEX_COLOR_TABLE32_GREEN_End 15 +#define GCREG_INDEX_COLOR_TABLE32_GREEN_Start 8 +#define GCREG_INDEX_COLOR_TABLE32_GREEN_Type U08 + +#define GCREG_INDEX_COLOR_TABLE32_BLUE 7 : 0 +#define GCREG_INDEX_COLOR_TABLE32_BLUE_End 7 +#define GCREG_INDEX_COLOR_TABLE32_BLUE_Start 0 +#define GCREG_INDEX_COLOR_TABLE32_BLUE_Type U08 + +/******************************************************************************* +** State gcregRop +*/ + +/* Raster operation foreground and background codes. Even though ROP is not +** used in CLEAR, HOR_FILTER_BLT, VER_FILTER_BLT and alpha-eanbled BIT_BLTs, +** ROP code still has to be programmed, because the engine makes the decision +** whether source, destination and pattern are involved in the current +** operation and the correct decision is essential for the engine to complete +** the operation as expected. +*/ + +#define gcregRopRegAddrs 0x0497 +#define GCREG_ROP_MSB 15 +#define GCREG_ROP_LSB 0 +#define GCREG_ROP_BLK 0 +#define GCREG_ROP_Count 1 +#define GCREG_ROP_FieldMask 0x0030FFFF +#define GCREG_ROP_ReadMask 0x0030FFFF +#define GCREG_ROP_WriteMask 0x0030FFFF +#define GCREG_ROP_ResetValue 0x00000000 + +/* ROP type: ROP2, ROP3 or ROP4 */ +#define GCREG_ROP_TYPE 21 : 20 +#define GCREG_ROP_TYPE_End 21 +#define GCREG_ROP_TYPE_Start 20 +#define GCREG_ROP_TYPE_Type U02 +#define GCREG_ROP_TYPE_ROP2_PATTERN 0x0 +#define GCREG_ROP_TYPE_ROP2_SOURCE 0x1 +#define GCREG_ROP_TYPE_ROP3 0x2 +#define GCREG_ROP_TYPE_ROP4 0x3 + +/* Background ROP code is used for transparent pixels. */ +#define GCREG_ROP_ROP_BG 15 : 8 +#define GCREG_ROP_ROP_BG_End 15 +#define GCREG_ROP_ROP_BG_Start 8 +#define GCREG_ROP_ROP_BG_Type U08 + +/* Background ROP code is used for opaque pixels. */ +#define GCREG_ROP_ROP_FG 7 : 0 +#define GCREG_ROP_ROP_FG_End 7 +#define GCREG_ROP_ROP_FG_Start 0 +#define GCREG_ROP_ROP_FG_Type U08 + +struct gcregrop { + unsigned int fg:8; + unsigned int bg:8; + unsigned int _reserved_16_19:4; + unsigned int type:2; + unsigned int _reserved_22_31:10; +}; + +/******************************************************************************* +** State gcregClipTopLeft +*/ + +/* Top left corner of the clipping rectangle defined in pixels. Clipping is +** always on and everything beyond the clipping rectangle will be clipped +** out. Clipping is not used with filter blits. +*/ + +#define gcregClipTopLeftRegAddrs 0x0498 +#define GCREG_CLIP_TOP_LEFT_MSB 15 +#define GCREG_CLIP_TOP_LEFT_LSB 0 +#define GCREG_CLIP_TOP_LEFT_BLK 0 +#define GCREG_CLIP_TOP_LEFT_Count 1 +#define GCREG_CLIP_TOP_LEFT_FieldMask 0x7FFF7FFF +#define GCREG_CLIP_TOP_LEFT_ReadMask 0x7FFF7FFF +#define GCREG_CLIP_TOP_LEFT_WriteMask 0x7FFF7FFF +#define GCREG_CLIP_TOP_LEFT_ResetValue 0x00000000 + +#define GCREG_CLIP_TOP_LEFT_Y 30 : 16 +#define GCREG_CLIP_TOP_LEFT_Y_End 30 +#define GCREG_CLIP_TOP_LEFT_Y_Start 16 +#define GCREG_CLIP_TOP_LEFT_Y_Type U15 + +#define GCREG_CLIP_TOP_LEFT_X 14 : 0 +#define GCREG_CLIP_TOP_LEFT_X_End 14 +#define GCREG_CLIP_TOP_LEFT_X_Start 0 +#define GCREG_CLIP_TOP_LEFT_X_Type U15 + +struct gcregcliplt { + unsigned int left:15; + unsigned int _reserved_15:1; + unsigned int top:15; + unsigned int _reserved_31:1; +}; + +/******************************************************************************* +** State gcregClipBottomRight +*/ + +/* Bottom right corner of the clipping rectangle defined in pixels. Clipping +** is always on and everything beyond the clipping rectangle will be clipped +** out. Clipping is not used with filter blits. +*/ + +#define gcregClipBottomRightRegAddrs 0x0499 +#define GCREG_CLIP_BOTTOM_RIGHT_MSB 15 +#define GCREG_CLIP_BOTTOM_RIGHT_LSB 0 +#define GCREG_CLIP_BOTTOM_RIGHT_BLK 0 +#define GCREG_CLIP_BOTTOM_RIGHT_Count 1 +#define GCREG_CLIP_BOTTOM_RIGHT_FieldMask 0x7FFF7FFF +#define GCREG_CLIP_BOTTOM_RIGHT_ReadMask 0x7FFF7FFF +#define GCREG_CLIP_BOTTOM_RIGHT_WriteMask 0x7FFF7FFF +#define GCREG_CLIP_BOTTOM_RIGHT_ResetValue 0x00000000 + +#define GCREG_CLIP_BOTTOM_RIGHT_Y 30 : 16 +#define GCREG_CLIP_BOTTOM_RIGHT_Y_End 30 +#define GCREG_CLIP_BOTTOM_RIGHT_Y_Start 16 +#define GCREG_CLIP_BOTTOM_RIGHT_Y_Type U15 + +#define GCREG_CLIP_BOTTOM_RIGHT_X 14 : 0 +#define GCREG_CLIP_BOTTOM_RIGHT_X_End 14 +#define GCREG_CLIP_BOTTOM_RIGHT_X_Start 0 +#define GCREG_CLIP_BOTTOM_RIGHT_X_Type U15 + +struct gcregcliprb { + unsigned int right:15; + unsigned int _reserved_15:1; + unsigned int bottom:15; + unsigned int _reserved_31:1; +}; + +/******************************************************************************* +** State gcregConfig +*/ + +#define gcregConfigRegAddrs 0x049B +#define GCREG_CONFIG_MSB 15 +#define GCREG_CONFIG_LSB 0 +#define GCREG_CONFIG_BLK 0 +#define GCREG_CONFIG_Count 1 +#define GCREG_CONFIG_FieldMask 0x00370031 +#define GCREG_CONFIG_ReadMask 0x00370031 +#define GCREG_CONFIG_WriteMask 0x00370031 +#define GCREG_CONFIG_ResetValue 0x00000000 + +#define GCREG_CONFIG_MIRROR_BLT_MODE 5 : 4 +#define GCREG_CONFIG_MIRROR_BLT_MODE_End 5 +#define GCREG_CONFIG_MIRROR_BLT_MODE_Start 4 +#define GCREG_CONFIG_MIRROR_BLT_MODE_Type U02 +#define GCREG_CONFIG_MIRROR_BLT_MODE_NORMAL 0x0 +#define GCREG_CONFIG_MIRROR_BLT_MODE_HMIRROR 0x1 +#define GCREG_CONFIG_MIRROR_BLT_MODE_VMIRROR 0x2 +#define GCREG_CONFIG_MIRROR_BLT_MODE_FULL_MIRROR 0x3 + +#define GCREG_CONFIG_MIRROR_BLT_ENABLE 0 : 0 +#define GCREG_CONFIG_MIRROR_BLT_ENABLE_End 0 +#define GCREG_CONFIG_MIRROR_BLT_ENABLE_Start 0 +#define GCREG_CONFIG_MIRROR_BLT_ENABLE_Type U01 +#define GCREG_CONFIG_MIRROR_BLT_ENABLE_OFF 0x0 +#define GCREG_CONFIG_MIRROR_BLT_ENABLE_ON 0x1 + +/* Source select for the old walkers. */ +#define GCREG_CONFIG_SOURCE_SELECT 18 : 16 +#define GCREG_CONFIG_SOURCE_SELECT_End 18 +#define GCREG_CONFIG_SOURCE_SELECT_Start 16 +#define GCREG_CONFIG_SOURCE_SELECT_Type U03 + +/* Destination select for the old walkers. */ +#define GCREG_CONFIG_DESTINATION_SELECT 21 : 20 +#define GCREG_CONFIG_DESTINATION_SELECT_End 21 +#define GCREG_CONFIG_DESTINATION_SELECT_Start 20 +#define GCREG_CONFIG_DESTINATION_SELECT_Type U02 + +/******************************************************************************* +** State gcregSrcOriginFraction +*/ + +/* Fraction for the source origin. Together with values in gcregSrcOrigin +** these values form signed 16.16 fixed point origin for the source +** rectangle. Fractions are only used in filter blit in split frame mode. +*/ + +#define gcregSrcOriginFractionRegAddrs 0x049E +#define GCREG_SRC_ORIGIN_FRACTION_MSB 15 +#define GCREG_SRC_ORIGIN_FRACTION_LSB 0 +#define GCREG_SRC_ORIGIN_FRACTION_BLK 0 +#define GCREG_SRC_ORIGIN_FRACTION_Count 1 +#define GCREG_SRC_ORIGIN_FRACTION_FieldMask 0xFFFFFFFF +#define GCREG_SRC_ORIGIN_FRACTION_ReadMask 0xFFFFFFFF +#define GCREG_SRC_ORIGIN_FRACTION_WriteMask 0xFFFFFFFF +#define GCREG_SRC_ORIGIN_FRACTION_ResetValue 0x00000000 + +#define GCREG_SRC_ORIGIN_FRACTION_Y 31 : 16 +#define GCREG_SRC_ORIGIN_FRACTION_Y_End 31 +#define GCREG_SRC_ORIGIN_FRACTION_Y_Start 16 +#define GCREG_SRC_ORIGIN_FRACTION_Y_Type U16 + +#define GCREG_SRC_ORIGIN_FRACTION_X 15 : 0 +#define GCREG_SRC_ORIGIN_FRACTION_X_End 15 +#define GCREG_SRC_ORIGIN_FRACTION_X_Start 0 +#define GCREG_SRC_ORIGIN_FRACTION_X_Type U16 + +/******************************************************************************* +** State gcregAlphaControl +*/ + +#define gcregAlphaControlRegAddrs 0x049F +#define GCREG_ALPHA_CONTROL_MSB 15 +#define GCREG_ALPHA_CONTROL_LSB 0 +#define GCREG_ALPHA_CONTROL_BLK 0 +#define GCREG_ALPHA_CONTROL_Count 1 +#define GCREG_ALPHA_CONTROL_FieldMask 0xFFFF0001 +#define GCREG_ALPHA_CONTROL_ReadMask 0xFFFF0001 +#define GCREG_ALPHA_CONTROL_WriteMask 0xFFFF0001 +#define GCREG_ALPHA_CONTROL_ResetValue 0x00000000 + +#define GCREG_ALPHA_CONTROL_ENABLE 0 : 0 +#define GCREG_ALPHA_CONTROL_ENABLE_End 0 +#define GCREG_ALPHA_CONTROL_ENABLE_Start 0 +#define GCREG_ALPHA_CONTROL_ENABLE_Type U01 +#define GCREG_ALPHA_CONTROL_ENABLE_OFF 0x0 +#define GCREG_ALPHA_CONTROL_ENABLE_ON 0x1 + +struct gcregalphacontrol { + /* gcregAlphaControlRegAddrs:GCREG_ALPHA_CONTROL_ENABLE */ + unsigned int enable:1; + + /* gcregAlphaControlRegAddrs:reserved */ + unsigned int _reserved_1_31:31; +}; + +/******************************************************************************* +** State gcregAlphaModes +*/ + +#define gcregAlphaModesRegAddrs 0x04A0 +#define GCREG_ALPHA_MODES_MSB 15 +#define GCREG_ALPHA_MODES_LSB 0 +#define GCREG_ALPHA_MODES_BLK 0 +#define GCREG_ALPHA_MODES_Count 1 +#define GCREG_ALPHA_MODES_FieldMask 0xFF113311 +#define GCREG_ALPHA_MODES_ReadMask 0xFF113311 +#define GCREG_ALPHA_MODES_WriteMask 0xFF113311 +#define GCREG_ALPHA_MODES_ResetValue 0x00000000 + +#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE 0 : 0 +#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_End 0 +#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_Start 0 +#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_Type U01 +#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL 0x0 +#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED 0x1 + +#define GCREG_ALPHA_MODES_DST_ALPHA_MODE 4 : 4 +#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_End 4 +#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_Start 4 +#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_Type U01 +#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_NORMAL 0x0 +#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_INVERSED 0x1 + +#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE 9 : 8 +#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_End 9 +#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Start 8 +#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Type U02 +#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL 0x0 +#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL 0x1 +#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED 0x2 + +#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE 13 : 12 +#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_End 13 +#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Start 12 +#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Type U02 +#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL 0x0 +#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL 0x1 +#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED 0x2 + +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE 26 : 24 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_End 26 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_Start 24 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_Type U03 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_ZERO 0x0 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_ONE 0x1 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_NORMAL 0x2 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_INVERSED 0x3 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_COLOR 0x4 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_COLOR_INVERSED 0x5 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_ALPHA 0x6 +#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_DEST_ALPHA 0x7 + +/* Src Blending factor is calculate from Src alpha. */ +#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR 27 : 27 +#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_End 27 +#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_Start 27 +#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_Type U01 +#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLED 0x0 +#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLED 0x1 + +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE 30 : 28 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_End 30 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_Start 28 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_Type U03 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_ZERO 0x0 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_ONE 0x1 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_NORMAL 0x2 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_INVERSED 0x3 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_COLOR 0x4 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_COLOR_INVERSED 0x5 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_ALPHA 0x6 +#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_DEST_ALPHA 0x7 + +/* Dst Blending factor is calculate from Dst alpha. */ +#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR 31 : 31 +#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_End 31 +#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_Start 31 +#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_Type U01 +#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLED 0x0 +#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLED 0x1 + +struct gcregalphamodes { + /* gcregAlphaModes:GCREG_ALPHA_MODES_SRC_ALPHA_MODE */ + unsigned int src_inverse:1; + + /* gcregAlphaModes:reserved */ + unsigned int _reserved_1_3:3; + + /* gcregAlphaModes:GCREG_ALPHA_MODES_DST_ALPHA_MODE */ + unsigned int dst_inverse:1; + + /* gcregAlphaModes:reserved */ + unsigned int _reserved_5_7:3; + + /* gcregAlphaModes:GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE */ + unsigned int src_global_alpha:2; + + /* gcregAlphaModes:reserved */ + unsigned int _reserved_10_11:2; + + /* gcregAlphaModes:GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE */ + unsigned int dst_global_alpha:2; + + /* gcregAlphaModes:reserved */ + unsigned int _reserved_14_23:10; + + /* gcregAlphaModes:GCREG_ALPHA_MODES_SRC_BLENDING_MODE */ + unsigned int src_blend:3; + + /* gcregAlphaModes:GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR */ + unsigned int src_color_reverse:1; + + /* gcregAlphaModes:GCREG_ALPHA_MODES_DST_BLENDING_MODE */ + unsigned int dst_blend:3; + + /* gcregAlphaModes:GCREG_ALPHA_MODES_DST_ALPHA_FACTOR */ + unsigned int dst_color_reverse:1; +}; + +/******************************************************************************* +** State UPlaneAddress +*/ + +/* 32-bit aligned base address of the source U plane. */ + +#define gcregUPlaneAddressRegAddrs 0x04A1 +#define GCREG_UPLANE_ADDRESS_MSB 15 +#define GCREG_UPLANE_ADDRESS_LSB 0 +#define GCREG_UPLANE_ADDRESS_BLK 0 +#define GCREG_UPLANE_ADDRESS_Count 1 +#define GCREG_UPLANE_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_UPLANE_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_UPLANE_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_UPLANE_ADDRESS_ResetValue 0x00000000 + +#define GCREG_UPLANE_ADDRESS_ADDRESS 31 : 0 +#define GCREG_UPLANE_ADDRESS_ADDRESS_End 30 +#define GCREG_UPLANE_ADDRESS_ADDRESS_Start 0 +#define GCREG_UPLANE_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State UPlaneStride +*/ + +/* Stride of the source U plane in bytes. */ + +#define gcregUPlaneStrideRegAddrs 0x04A2 +#define GCREG_UPLANE_STRIDE_MSB 15 +#define GCREG_UPLANE_STRIDE_LSB 0 +#define GCREG_UPLANE_STRIDE_BLK 0 +#define GCREG_UPLANE_STRIDE_Count 1 +#define GCREG_UPLANE_STRIDE_FieldMask 0x0003FFFF +#define GCREG_UPLANE_STRIDE_ReadMask 0x0003FFFC +#define GCREG_UPLANE_STRIDE_WriteMask 0x0003FFFC +#define GCREG_UPLANE_STRIDE_ResetValue 0x00000000 + +#define GCREG_UPLANE_STRIDE_STRIDE 17 : 0 +#define GCREG_UPLANE_STRIDE_STRIDE_End 17 +#define GCREG_UPLANE_STRIDE_STRIDE_Start 0 +#define GCREG_UPLANE_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State VPlaneAddress +*/ + +/* 32-bit aligned base address of the source V plane. */ + +#define gcregVPlaneAddressRegAddrs 0x04A3 +#define GCREG_VPLANE_ADDRESS_MSB 15 +#define GCREG_VPLANE_ADDRESS_LSB 0 +#define GCREG_VPLANE_ADDRESS_BLK 0 +#define GCREG_VPLANE_ADDRESS_Count 1 +#define GCREG_VPLANE_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_VPLANE_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_VPLANE_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_VPLANE_ADDRESS_ResetValue 0x00000000 + +#define GCREG_VPLANE_ADDRESS_ADDRESS 31 : 0 +#define GCREG_VPLANE_ADDRESS_ADDRESS_End 30 +#define GCREG_VPLANE_ADDRESS_ADDRESS_Start 0 +#define GCREG_VPLANE_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State VPlaneStride +*/ + +/* Stride of the source V plane in bytes. */ + +#define gcregVPlaneStrideRegAddrs 0x04A4 +#define GCREG_VPLANE_STRIDE_MSB 15 +#define GCREG_VPLANE_STRIDE_LSB 0 +#define GCREG_VPLANE_STRIDE_BLK 0 +#define GCREG_VPLANE_STRIDE_Count 1 +#define GCREG_VPLANE_STRIDE_FieldMask 0x0003FFFF +#define GCREG_VPLANE_STRIDE_ReadMask 0x0003FFFC +#define GCREG_VPLANE_STRIDE_WriteMask 0x0003FFFC +#define GCREG_VPLANE_STRIDE_ResetValue 0x00000000 + +#define GCREG_VPLANE_STRIDE_STRIDE 17 : 0 +#define GCREG_VPLANE_STRIDE_STRIDE_End 17 +#define GCREG_VPLANE_STRIDE_STRIDE_Start 0 +#define GCREG_VPLANE_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State gcregPEConfig +*/ + +/* PE debug register. */ + +#define gcregPEConfigRegAddrs 0x04AC +#define GCREG_PE_CONFIG_Address 0x012B0 +#define GCREG_PE_CONFIG_MSB 15 +#define GCREG_PE_CONFIG_LSB 0 +#define GCREG_PE_CONFIG_BLK 0 +#define GCREG_PE_CONFIG_Count 1 +#define GCREG_PE_CONFIG_FieldMask 0x0000000B +#define GCREG_PE_CONFIG_ReadMask 0x0000000B +#define GCREG_PE_CONFIG_WriteMask 0x0000000B +#define GCREG_PE_CONFIG_ResetValue 0x00000000 + +#define GCREG_PE_CONFIG_DESTINATION_FETCH 1 : 0 +#define GCREG_PE_CONFIG_DESTINATION_FETCH_End 1 +#define GCREG_PE_CONFIG_DESTINATION_FETCH_Start 0 +#define GCREG_PE_CONFIG_DESTINATION_FETCH_Type U02 +#define GCREG_PE_CONFIG_DESTINATION_FETCH_DISABLE 0x0 +#define GCREG_PE_CONFIG_DESTINATION_FETCH_DEFAULT 0x1 +#define GCREG_PE_CONFIG_DESTINATION_FETCH_ALWAYS 0x2 + +#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH 3 : 3 +#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_End 3 +#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_Start 3 +#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_Type U01 +#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_ENABLED 0x0 +#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_MASKED 0x1 + +/******************************************************************************* +** State gcregDstRotationHeight +*/ + +/* 180/270 degree rotation configuration for the destination surface. Height +** field specifies the height of the surface in pixels. +*/ + +#define gcregDstRotationHeightRegAddrs 0x04AD +#define GCREG_DST_ROTATION_HEIGHT_MSB 15 +#define GCREG_DST_ROTATION_HEIGHT_LSB 0 +#define GCREG_DST_ROTATION_HEIGHT_BLK 0 +#define GCREG_DST_ROTATION_HEIGHT_Count 1 +#define GCREG_DST_ROTATION_HEIGHT_FieldMask 0x0000FFFF +#define GCREG_DST_ROTATION_HEIGHT_ReadMask 0x0000FFFF +#define GCREG_DST_ROTATION_HEIGHT_WriteMask 0x0000FFFF +#define GCREG_DST_ROTATION_HEIGHT_ResetValue 0x00000000 + +#define GCREG_DST_ROTATION_HEIGHT_HEIGHT 15 : 0 +#define GCREG_DST_ROTATION_HEIGHT_HEIGHT_End 15 +#define GCREG_DST_ROTATION_HEIGHT_HEIGHT_Start 0 +#define GCREG_DST_ROTATION_HEIGHT_HEIGHT_Type U16 + +struct gcregdstrotationheight { + /* gcregDstRotationHeightRegAddrs:GCREG_DST_ROTATION_HEIGHT_HEIGHT */ + unsigned int height:16; + + /* gcregDstRotationHeightRegAddrs:reserved */ + unsigned int _reserved_16_31:16; +}; + +/******************************************************************************* +** State gcregSrcRotationHeight +*/ + +/* 180/270 degree rotation configuration for the Source surface. Height field +** specifies the height of the surface in pixels. +*/ + +#define gcregSrcRotationHeightRegAddrs 0x04AE +#define GCREG_SRC_ROTATION_HEIGHT_MSB 15 +#define GCREG_SRC_ROTATION_HEIGHT_LSB 0 +#define GCREG_SRC_ROTATION_HEIGHT_BLK 0 +#define GCREG_SRC_ROTATION_HEIGHT_Count 1 +#define GCREG_SRC_ROTATION_HEIGHT_FieldMask 0x0000FFFF +#define GCREG_SRC_ROTATION_HEIGHT_ReadMask 0x0000FFFF +#define GCREG_SRC_ROTATION_HEIGHT_WriteMask 0x0000FFFF +#define GCREG_SRC_ROTATION_HEIGHT_ResetValue 0x00000000 + +#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT 15 : 0 +#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT_End 15 +#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT_Start 0 +#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT_Type U16 + +struct gcregsrcrotationheight { + /* gcregSrcRotationHeightRegAddrs:GCREG_SRC_ROTATION_HEIGHT_HEIGHT */ + unsigned int height:16; + + /* gcregSrcRotationHeightRegAddrs:reserved */ + unsigned int _reserved_16_31:16; +}; + +/******************************************************************************* +** State gcregRotAngle +*/ + +/* 0/90/180/270 degree rotation configuration for the Source surface. Height +** field specifies the height of the surface in pixels. +*/ + +#define gcregRotAngleRegAddrs 0x04AF +#define GCREG_ROT_ANGLE_MSB 15 +#define GCREG_ROT_ANGLE_LSB 0 +#define GCREG_ROT_ANGLE_BLK 0 +#define GCREG_ROT_ANGLE_Count 1 +#define GCREG_ROT_ANGLE_FieldMask 0x000BB33F +#define GCREG_ROT_ANGLE_ReadMask 0x000BB33F +#define GCREG_ROT_ANGLE_WriteMask 0x000BB33F +#define GCREG_ROT_ANGLE_ResetValue 0x00000000 + +#define GCREG_ROT_ANGLE_SRC 2 : 0 +#define GCREG_ROT_ANGLE_SRC_End 2 +#define GCREG_ROT_ANGLE_SRC_Start 0 +#define GCREG_ROT_ANGLE_SRC_Type U03 +#define GCREG_ROT_ANGLE_SRC_ROT0 0x0 +#define GCREG_ROT_ANGLE_SRC_FLIP_X 0x1 +#define GCREG_ROT_ANGLE_SRC_FLIP_Y 0x2 +#define GCREG_ROT_ANGLE_SRC_ROT90 0x4 +#define GCREG_ROT_ANGLE_SRC_ROT180 0x5 +#define GCREG_ROT_ANGLE_SRC_ROT270 0x6 + +#define GCREG_ROT_ANGLE_DST 5 : 3 +#define GCREG_ROT_ANGLE_DST_End 5 +#define GCREG_ROT_ANGLE_DST_Start 3 +#define GCREG_ROT_ANGLE_DST_Type U03 +#define GCREG_ROT_ANGLE_DST_ROT0 0x0 +#define GCREG_ROT_ANGLE_DST_FLIP_X 0x1 +#define GCREG_ROT_ANGLE_DST_FLIP_Y 0x2 +#define GCREG_ROT_ANGLE_DST_ROT90 0x4 +#define GCREG_ROT_ANGLE_DST_ROT180 0x5 +#define GCREG_ROT_ANGLE_DST_ROT270 0x6 + +#define GCREG_ROT_ANGLE_MASK_SRC 8 : 8 +#define GCREG_ROT_ANGLE_MASK_SRC_End 8 +#define GCREG_ROT_ANGLE_MASK_SRC_Start 8 +#define GCREG_ROT_ANGLE_MASK_SRC_Type U01 +#define GCREG_ROT_ANGLE_MASK_SRC_ENABLED 0x0 +#define GCREG_ROT_ANGLE_MASK_SRC_MASKED 0x1 + +#define GCREG_ROT_ANGLE_MASK_DST 9 : 9 +#define GCREG_ROT_ANGLE_MASK_DST_End 9 +#define GCREG_ROT_ANGLE_MASK_DST_Start 9 +#define GCREG_ROT_ANGLE_MASK_DST_Type U01 +#define GCREG_ROT_ANGLE_MASK_DST_ENABLED 0x0 +#define GCREG_ROT_ANGLE_MASK_DST_MASKED 0x1 + +#define GCREG_ROT_ANGLE_SRC_MIRROR 13 : 12 +#define GCREG_ROT_ANGLE_SRC_MIRROR_End 13 +#define GCREG_ROT_ANGLE_SRC_MIRROR_Start 12 +#define GCREG_ROT_ANGLE_SRC_MIRROR_Type U02 +#define GCREG_ROT_ANGLE_SRC_MIRROR_NONE 0x0 +#define GCREG_ROT_ANGLE_SRC_MIRROR_MIRROR_X 0x1 +#define GCREG_ROT_ANGLE_SRC_MIRROR_MIRROR_Y 0x2 +#define GCREG_ROT_ANGLE_SRC_MIRROR_MIRROR_XY 0x3 + +#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR 15 : 15 +#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_End 15 +#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_Start 15 +#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_Type U01 +#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_ENABLED 0x0 +#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_MASKED 0x1 + +#define GCREG_ROT_ANGLE_DST_MIRROR 17 : 16 +#define GCREG_ROT_ANGLE_DST_MIRROR_End 17 +#define GCREG_ROT_ANGLE_DST_MIRROR_Start 16 +#define GCREG_ROT_ANGLE_DST_MIRROR_Type U02 +#define GCREG_ROT_ANGLE_DST_MIRROR_NONE 0x0 +#define GCREG_ROT_ANGLE_DST_MIRROR_MIRROR_X 0x1 +#define GCREG_ROT_ANGLE_DST_MIRROR_MIRROR_Y 0x2 +#define GCREG_ROT_ANGLE_DST_MIRROR_MIRROR_XY 0x3 + +#define GCREG_ROT_ANGLE_MASK_DST_MIRROR 19 : 19 +#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_End 19 +#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_Start 19 +#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_Type U01 +#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_ENABLED 0x0 +#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_MASKED 0x1 + +/******************************************************************************* +** State gcregClearPixelValue32 +*/ + +/* Clear color value in A8R8G8B8 format. */ + +#define gcregClearPixelValue32RegAddrs 0x04B0 +#define GCREG_CLEAR_PIXEL_VALUE32_MSB 15 +#define GCREG_CLEAR_PIXEL_VALUE32_LSB 0 +#define GCREG_CLEAR_PIXEL_VALUE32_BLK 0 +#define GCREG_CLEAR_PIXEL_VALUE32_Count 1 +#define GCREG_CLEAR_PIXEL_VALUE32_FieldMask 0xFFFFFFFF +#define GCREG_CLEAR_PIXEL_VALUE32_ReadMask 0xFFFFFFFF +#define GCREG_CLEAR_PIXEL_VALUE32_WriteMask 0xFFFFFFFF +#define GCREG_CLEAR_PIXEL_VALUE32_ResetValue 0x00000000 + +#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA 31 : 24 +#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA_End 31 +#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA_Start 24 +#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA_Type U08 + +#define GCREG_CLEAR_PIXEL_VALUE32_RED 23 : 16 +#define GCREG_CLEAR_PIXEL_VALUE32_RED_End 23 +#define GCREG_CLEAR_PIXEL_VALUE32_RED_Start 16 +#define GCREG_CLEAR_PIXEL_VALUE32_RED_Type U08 + +#define GCREG_CLEAR_PIXEL_VALUE32_GREEN 15 : 8 +#define GCREG_CLEAR_PIXEL_VALUE32_GREEN_End 15 +#define GCREG_CLEAR_PIXEL_VALUE32_GREEN_Start 8 +#define GCREG_CLEAR_PIXEL_VALUE32_GREEN_Type U08 + +#define GCREG_CLEAR_PIXEL_VALUE32_BLUE 7 : 0 +#define GCREG_CLEAR_PIXEL_VALUE32_BLUE_End 7 +#define GCREG_CLEAR_PIXEL_VALUE32_BLUE_Start 0 +#define GCREG_CLEAR_PIXEL_VALUE32_BLUE_Type U08 + +struct gcregclearcolor { + /* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_BLUE */ + unsigned int b:8; + + /* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_GREEN */ + unsigned int g:8; + + /* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_RED */ + unsigned int r:8; + + /* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_ALPHA */ + unsigned int a:8; +}; + +/******************************************************************************* +** State gcregDestColorKey +*/ + +/* Defines the destination transparency color in destination format. */ + +#define gcregDestColorKeyRegAddrs 0x04B1 +#define GCREG_DEST_COLOR_KEY_MSB 15 +#define GCREG_DEST_COLOR_KEY_LSB 0 +#define GCREG_DEST_COLOR_KEY_BLK 0 +#define GCREG_DEST_COLOR_KEY_Count 1 +#define GCREG_DEST_COLOR_KEY_FieldMask 0xFFFFFFFF +#define GCREG_DEST_COLOR_KEY_ReadMask 0xFFFFFFFF +#define GCREG_DEST_COLOR_KEY_WriteMask 0xFFFFFFFF +#define GCREG_DEST_COLOR_KEY_ResetValue 0x00000000 + +#define GCREG_DEST_COLOR_KEY_ALPHA 31 : 24 +#define GCREG_DEST_COLOR_KEY_ALPHA_End 31 +#define GCREG_DEST_COLOR_KEY_ALPHA_Start 24 +#define GCREG_DEST_COLOR_KEY_ALPHA_Type U08 + +#define GCREG_DEST_COLOR_KEY_RED 23 : 16 +#define GCREG_DEST_COLOR_KEY_RED_End 23 +#define GCREG_DEST_COLOR_KEY_RED_Start 16 +#define GCREG_DEST_COLOR_KEY_RED_Type U08 + +#define GCREG_DEST_COLOR_KEY_GREEN 15 : 8 +#define GCREG_DEST_COLOR_KEY_GREEN_End 15 +#define GCREG_DEST_COLOR_KEY_GREEN_Start 8 +#define GCREG_DEST_COLOR_KEY_GREEN_Type U08 + +#define GCREG_DEST_COLOR_KEY_BLUE 7 : 0 +#define GCREG_DEST_COLOR_KEY_BLUE_End 7 +#define GCREG_DEST_COLOR_KEY_BLUE_Start 0 +#define GCREG_DEST_COLOR_KEY_BLUE_Type U08 + +/******************************************************************************* +** State gcregGlobalSrcColor +*/ + +/* Defines the global source color and alpha values. */ + +#define gcregGlobalSrcColorRegAddrs 0x04B2 +#define GCREG_GLOBAL_SRC_COLOR_MSB 15 +#define GCREG_GLOBAL_SRC_COLOR_LSB 0 +#define GCREG_GLOBAL_SRC_COLOR_BLK 0 +#define GCREG_GLOBAL_SRC_COLOR_Count 1 +#define GCREG_GLOBAL_SRC_COLOR_FieldMask 0xFFFFFFFF +#define GCREG_GLOBAL_SRC_COLOR_ReadMask 0xFFFFFFFF +#define GCREG_GLOBAL_SRC_COLOR_WriteMask 0xFFFFFFFF +#define GCREG_GLOBAL_SRC_COLOR_ResetValue 0x00000000 + +#define GCREG_GLOBAL_SRC_COLOR_ALPHA 31 : 24 +#define GCREG_GLOBAL_SRC_COLOR_ALPHA_End 31 +#define GCREG_GLOBAL_SRC_COLOR_ALPHA_Start 24 +#define GCREG_GLOBAL_SRC_COLOR_ALPHA_Type U08 + +#define GCREG_GLOBAL_SRC_COLOR_RED 23 : 16 +#define GCREG_GLOBAL_SRC_COLOR_RED_End 23 +#define GCREG_GLOBAL_SRC_COLOR_RED_Start 16 +#define GCREG_GLOBAL_SRC_COLOR_RED_Type U08 + +#define GCREG_GLOBAL_SRC_COLOR_GREEN 15 : 8 +#define GCREG_GLOBAL_SRC_COLOR_GREEN_End 15 +#define GCREG_GLOBAL_SRC_COLOR_GREEN_Start 8 +#define GCREG_GLOBAL_SRC_COLOR_GREEN_Type U08 + +#define GCREG_GLOBAL_SRC_COLOR_BLUE 7 : 0 +#define GCREG_GLOBAL_SRC_COLOR_BLUE_End 7 +#define GCREG_GLOBAL_SRC_COLOR_BLUE_Start 0 +#define GCREG_GLOBAL_SRC_COLOR_BLUE_Type U08 + +struct gcregglobalsrccolor { + /* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_BLUE */ + unsigned int b:8; + + /* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_GREEN */ + unsigned int g:8; + + /* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_RED */ + unsigned int r:8; + + /* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_ALPHA */ + unsigned int a:8; +}; + +/******************************************************************************* +** State gcregGlobalDestColor +*/ + +/* Defines the global destination color and alpha values. */ + +#define gcregGlobalDestColorRegAddrs 0x04B3 +#define GCREG_GLOBAL_DEST_COLOR_MSB 15 +#define GCREG_GLOBAL_DEST_COLOR_LSB 0 +#define GCREG_GLOBAL_DEST_COLOR_BLK 0 +#define GCREG_GLOBAL_DEST_COLOR_Count 1 +#define GCREG_GLOBAL_DEST_COLOR_FieldMask 0xFFFFFFFF +#define GCREG_GLOBAL_DEST_COLOR_ReadMask 0xFFFFFFFF +#define GCREG_GLOBAL_DEST_COLOR_WriteMask 0xFFFFFFFF +#define GCREG_GLOBAL_DEST_COLOR_ResetValue 0x00000000 + +#define GCREG_GLOBAL_DEST_COLOR_ALPHA 31 : 24 +#define GCREG_GLOBAL_DEST_COLOR_ALPHA_End 31 +#define GCREG_GLOBAL_DEST_COLOR_ALPHA_Start 24 +#define GCREG_GLOBAL_DEST_COLOR_ALPHA_Type U08 + +#define GCREG_GLOBAL_DEST_COLOR_RED 23 : 16 +#define GCREG_GLOBAL_DEST_COLOR_RED_End 23 +#define GCREG_GLOBAL_DEST_COLOR_RED_Start 16 +#define GCREG_GLOBAL_DEST_COLOR_RED_Type U08 + +#define GCREG_GLOBAL_DEST_COLOR_GREEN 15 : 8 +#define GCREG_GLOBAL_DEST_COLOR_GREEN_End 15 +#define GCREG_GLOBAL_DEST_COLOR_GREEN_Start 8 +#define GCREG_GLOBAL_DEST_COLOR_GREEN_Type U08 + +#define GCREG_GLOBAL_DEST_COLOR_BLUE 7 : 0 +#define GCREG_GLOBAL_DEST_COLOR_BLUE_End 7 +#define GCREG_GLOBAL_DEST_COLOR_BLUE_Start 0 +#define GCREG_GLOBAL_DEST_COLOR_BLUE_Type U08 + +struct gcregglobaldstcolor { + /* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_BLUE */ + unsigned int b:8; + + /* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_GREEN */ + unsigned int g:8; + + /* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_RED */ + unsigned int r:8; + + /* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_ALPHA */ + unsigned int a:8; +}; + +/******************************************************************************* +** State gcregColorMultiplyModes +*/ + +/* Color modes to multiply Source or Destination pixel color by alpha +** channel. Alpha can be from global color source or current pixel. +*/ + +#define gcregColorMultiplyModesRegAddrs 0x04B4 +#define GCREG_COLOR_MULTIPLY_MODES_MSB 15 +#define GCREG_COLOR_MULTIPLY_MODES_LSB 0 +#define GCREG_COLOR_MULTIPLY_MODES_BLK 0 +#define GCREG_COLOR_MULTIPLY_MODES_Count 1 +#define GCREG_COLOR_MULTIPLY_MODES_FieldMask 0x00100311 +#define GCREG_COLOR_MULTIPLY_MODES_ReadMask 0x00100311 +#define GCREG_COLOR_MULTIPLY_MODES_WriteMask 0x00100311 +#define GCREG_COLOR_MULTIPLY_MODES_ResetValue 0x00000000 + +#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY 0 : 0 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_End 0 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Start 0 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Type U01 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE 0x0 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE 0x1 + +#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY 4 : 4 +#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_End 4 +#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Start 4 +#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Type U01 +#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE 0x0 +#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE 0x1 + +#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY 9 : 8 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_End 9 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Start 8 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Type U02 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE 0x0 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA 0x1 +#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR 0x2 + +#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY 20 : 20 +#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_End 20 +#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Start 20 +#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Type U01 +#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE 0x0 +#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE 0x1 + +struct gcregcolormultiplymodes { + /* gcregColorMultiplyModesRegAddrs: + GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY */ + unsigned int srcpremul:1; + + /* gcregColorMultiplyModesRegAddrs: + reserved */ + unsigned int _reserved_1_3:3; + + /* gcregColorMultiplyModesRegAddrs: + GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY */ + unsigned int dstpremul:1; + + /* gcregColorMultiplyModesRegAddrs: + reserved */ + unsigned int _reserved_5_7:3; + + /* gcregColorMultiplyModesRegAddrs: + GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY */ + unsigned int srcglobalpremul:2; + + /* gcregColorMultiplyModesRegAddrs: + reserved */ + unsigned int _reserved_10_19:10; + + /* gcregColorMultiplyModesRegAddrs: + GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY */ + unsigned int dstdemul:1; + + /* gcregColorMultiplyModesRegAddrs: + reserved */ + unsigned int _reserved_21_31:11; +}; + +/******************************************************************************* +** State gcregPETransparency +*/ + +#define gcregPETransparencyRegAddrs 0x04B5 +#define GCREG_PE_TRANSPARENCY_MSB 15 +#define GCREG_PE_TRANSPARENCY_LSB 0 +#define GCREG_PE_TRANSPARENCY_BLK 0 +#define GCREG_PE_TRANSPARENCY_Count 1 +#define GCREG_PE_TRANSPARENCY_FieldMask 0xB3331333 +#define GCREG_PE_TRANSPARENCY_ReadMask 0xB3331333 +#define GCREG_PE_TRANSPARENCY_WriteMask 0xB3331333 +#define GCREG_PE_TRANSPARENCY_ResetValue 0x00000000 + +/* Source transparency mode. */ +#define GCREG_PE_TRANSPARENCY_SOURCE 1 : 0 +#define GCREG_PE_TRANSPARENCY_SOURCE_End 1 +#define GCREG_PE_TRANSPARENCY_SOURCE_Start 0 +#define GCREG_PE_TRANSPARENCY_SOURCE_Type U02 +#define GCREG_PE_TRANSPARENCY_SOURCE_OPAQUE 0x0 +#define GCREG_PE_TRANSPARENCY_SOURCE_MASK 0x1 +#define GCREG_PE_TRANSPARENCY_SOURCE_KEY 0x2 + +/* Pattern transparency mode. KEY transparency mode is reserved. */ +#define GCREG_PE_TRANSPARENCY_PATTERN 5 : 4 +#define GCREG_PE_TRANSPARENCY_PATTERN_End 5 +#define GCREG_PE_TRANSPARENCY_PATTERN_Start 4 +#define GCREG_PE_TRANSPARENCY_PATTERN_Type U02 +#define GCREG_PE_TRANSPARENCY_PATTERN_OPAQUE 0x0 +#define GCREG_PE_TRANSPARENCY_PATTERN_MASK 0x1 +#define GCREG_PE_TRANSPARENCY_PATTERN_KEY 0x2 + +/* Destination transparency mode. MASK transparency mode is reserved. */ +#define GCREG_PE_TRANSPARENCY_DESTINATION 9 : 8 +#define GCREG_PE_TRANSPARENCY_DESTINATION_End 9 +#define GCREG_PE_TRANSPARENCY_DESTINATION_Start 8 +#define GCREG_PE_TRANSPARENCY_DESTINATION_Type U02 +#define GCREG_PE_TRANSPARENCY_DESTINATION_OPAQUE 0x0 +#define GCREG_PE_TRANSPARENCY_DESTINATION_MASK 0x1 +#define GCREG_PE_TRANSPARENCY_DESTINATION_KEY 0x2 + +/* Mask field for Source/Pattern/Destination fields. */ +#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY 12 : 12 +#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_End 12 +#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_Start 12 +#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_Type U01 +#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_ENABLED 0x0 +#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_MASKED 0x1 + +/* Source usage override. */ +#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE 17 : 16 +#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_End 17 +#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_Start 16 +#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_Type U02 +#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT 0x0 +#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE 0x2 + +/* Pattern usage override. */ +#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE 21 : 20 +#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_End 21 +#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_Start 20 +#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_Type U02 +#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT 0x0 +#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE 0x2 + +/* Destination usage override. */ +#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE 25 : 24 +#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_End 25 +#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_Start 24 +#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_Type U02 +#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT 0x0 +#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE 0x2 + +/* 2D resource usage override mask field. */ +#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE 28 : 28 +#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_End 28 +#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Start 28 +#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Type U01 +#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_ENABLED 0x0 +#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_MASKED 0x1 + +/* DEB Color Key. */ +#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY 29 : 29 +#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_End 29 +#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_Start 29 +#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_Type U01 +#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_DISABLED 0x0 +#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_ENABLED 0x1 + +#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY 31 : 31 +#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_End 31 +#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_Start 31 +#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_Type U01 +#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_ENABLED 0x0 +#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_MASKED 0x1 + +/******************************************************************************* +** State gcregPEControl +*/ + +/* General purpose control register. */ + +#define gcregPEControlRegAddrs 0x04B6 +#define GCREG_PE_CONTROL_MSB 15 +#define GCREG_PE_CONTROL_LSB 0 +#define GCREG_PE_CONTROL_BLK 0 +#define GCREG_PE_CONTROL_Count 1 +#define GCREG_PE_CONTROL_FieldMask 0x00000999 +#define GCREG_PE_CONTROL_ReadMask 0x00000999 +#define GCREG_PE_CONTROL_WriteMask 0x00000999 +#define GCREG_PE_CONTROL_ResetValue 0x00000000 + +#define GCREG_PE_CONTROL_YUV 0 : 0 +#define GCREG_PE_CONTROL_YUV_End 0 +#define GCREG_PE_CONTROL_YUV_Start 0 +#define GCREG_PE_CONTROL_YUV_Type U01 +#define GCREG_PE_CONTROL_YUV_601 0x0 +#define GCREG_PE_CONTROL_YUV_709 0x1 + +#define GCREG_PE_CONTROL_MASK_YUV 3 : 3 +#define GCREG_PE_CONTROL_MASK_YUV_End 3 +#define GCREG_PE_CONTROL_MASK_YUV_Start 3 +#define GCREG_PE_CONTROL_MASK_YUV_Type U01 +#define GCREG_PE_CONTROL_MASK_YUV_ENABLED 0x0 +#define GCREG_PE_CONTROL_MASK_YUV_MASKED 0x1 + +#define GCREG_PE_CONTROL_UV_SWIZZLE 4 : 4 +#define GCREG_PE_CONTROL_UV_SWIZZLE_End 4 +#define GCREG_PE_CONTROL_UV_SWIZZLE_Start 4 +#define GCREG_PE_CONTROL_UV_SWIZZLE_Type U01 +#define GCREG_PE_CONTROL_UV_SWIZZLE_UV 0x0 +#define GCREG_PE_CONTROL_UV_SWIZZLE_VU 0x1 + +#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE 7 : 7 +#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_End 7 +#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_Start 7 +#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_Type U01 +#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_ENABLED 0x0 +#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_MASKED 0x1 + +/* YUV to RGB convert enable */ +#define GCREG_PE_CONTROL_YUVRGB 8 : 8 +#define GCREG_PE_CONTROL_YUVRGB_End 8 +#define GCREG_PE_CONTROL_YUVRGB_Start 8 +#define GCREG_PE_CONTROL_YUVRGB_Type U01 +#define GCREG_PE_CONTROL_YUVRGB_DISABLED 0x0 +#define GCREG_PE_CONTROL_YUVRGB_ENABLED 0x1 + +#define GCREG_PE_CONTROL_MASK_YUVRGB 11 : 11 +#define GCREG_PE_CONTROL_MASK_YUVRGB_End 11 +#define GCREG_PE_CONTROL_MASK_YUVRGB_Start 11 +#define GCREG_PE_CONTROL_MASK_YUVRGB_Type U01 +#define GCREG_PE_CONTROL_MASK_YUVRGB_ENABLED 0x0 +#define GCREG_PE_CONTROL_MASK_YUVRGB_MASKED 0x1 + +/******************************************************************************* +** State gcregSrcColorKeyHigh +*/ + +/* Defines the source transparency color in source format. */ + +#define gcregSrcColorKeyHighRegAddrs 0x04B7 +#define GCREG_SRC_COLOR_KEY_HIGH_Address 0x012DC +#define GCREG_SRC_COLOR_KEY_HIGH_MSB 15 +#define GCREG_SRC_COLOR_KEY_HIGH_LSB 0 +#define GCREG_SRC_COLOR_KEY_HIGH_BLK 0 +#define GCREG_SRC_COLOR_KEY_HIGH_Count 1 +#define GCREG_SRC_COLOR_KEY_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_KEY_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_KEY_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_SRC_COLOR_KEY_HIGH_ResetValue 0x00000000 + +#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA 31 : 24 +#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA_End 31 +#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA_Start 24 +#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA_Type U08 + +#define GCREG_SRC_COLOR_KEY_HIGH_RED 23 : 16 +#define GCREG_SRC_COLOR_KEY_HIGH_RED_End 23 +#define GCREG_SRC_COLOR_KEY_HIGH_RED_Start 16 +#define GCREG_SRC_COLOR_KEY_HIGH_RED_Type U08 + +#define GCREG_SRC_COLOR_KEY_HIGH_GREEN 15 : 8 +#define GCREG_SRC_COLOR_KEY_HIGH_GREEN_End 15 +#define GCREG_SRC_COLOR_KEY_HIGH_GREEN_Start 8 +#define GCREG_SRC_COLOR_KEY_HIGH_GREEN_Type U08 + +#define GCREG_SRC_COLOR_KEY_HIGH_BLUE 7 : 0 +#define GCREG_SRC_COLOR_KEY_HIGH_BLUE_End 7 +#define GCREG_SRC_COLOR_KEY_HIGH_BLUE_Start 0 +#define GCREG_SRC_COLOR_KEY_HIGH_BLUE_Type U08 + +/******************************************************************************* +** State gcregDestColorKeyHigh +*/ + +/* Defines the destination transparency color in destination format. */ + +#define gcregDestColorKeyHighRegAddrs 0x04B8 +#define GCREG_DEST_COLOR_KEY_HIGH_MSB 15 +#define GCREG_DEST_COLOR_KEY_HIGH_LSB 0 +#define GCREG_DEST_COLOR_KEY_HIGH_BLK 0 +#define GCREG_DEST_COLOR_KEY_HIGH_Count 1 +#define GCREG_DEST_COLOR_KEY_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_DEST_COLOR_KEY_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_DEST_COLOR_KEY_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_DEST_COLOR_KEY_HIGH_ResetValue 0x00000000 + +#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA 31 : 24 +#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA_End 31 +#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA_Start 24 +#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA_Type U08 + +#define GCREG_DEST_COLOR_KEY_HIGH_RED 23 : 16 +#define GCREG_DEST_COLOR_KEY_HIGH_RED_End 23 +#define GCREG_DEST_COLOR_KEY_HIGH_RED_Start 16 +#define GCREG_DEST_COLOR_KEY_HIGH_RED_Type U08 + +#define GCREG_DEST_COLOR_KEY_HIGH_GREEN 15 : 8 +#define GCREG_DEST_COLOR_KEY_HIGH_GREEN_End 15 +#define GCREG_DEST_COLOR_KEY_HIGH_GREEN_Start 8 +#define GCREG_DEST_COLOR_KEY_HIGH_GREEN_Type U08 + +#define GCREG_DEST_COLOR_KEY_HIGH_BLUE 7 : 0 +#define GCREG_DEST_COLOR_KEY_HIGH_BLUE_End 7 +#define GCREG_DEST_COLOR_KEY_HIGH_BLUE_Start 0 +#define GCREG_DEST_COLOR_KEY_HIGH_BLUE_Type U08 + +/******************************************************************************* +** State gcregPEDitherLow +*/ + +/* PE dither register. +** If you don't want dither, set all fields to their reset values. +*/ + +#define gcregPEDitherLowRegAddrs 0x04BA +#define GCREG_PE_DITHER_LOW_MSB 15 +#define GCREG_PE_DITHER_LOW_LSB 0 +#define GCREG_PE_DITHER_LOW_BLK 0 +#define GCREG_PE_DITHER_LOW_Count 1 +#define GCREG_PE_DITHER_LOW_FieldMask 0xFFFFFFFF +#define GCREG_PE_DITHER_LOW_ReadMask 0xFFFFFFFF +#define GCREG_PE_DITHER_LOW_WriteMask 0xFFFFFFFF +#define GCREG_PE_DITHER_LOW_ResetValue 0xFFFFFFFF + +/* X,Y = 0,0 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0 3 : 0 +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0_End 3 +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0_Start 0 +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0_Type U04 + +/* X,Y = 1,0 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0 7 : 4 +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0_End 7 +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0_Start 4 +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0_Type U04 + +/* X,Y = 2,0 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0 11 : 8 +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0_End 11 +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0_Start 8 +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0_Type U04 + +/* X,Y = 3,0 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0 15 : 12 +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0_End 15 +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0_Start 12 +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0_Type U04 + +/* X,Y = 0,1 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1 19 : 16 +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1_End 19 +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1_Start 16 +#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1_Type U04 + +/* X,Y = 1,1 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1 23 : 20 +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1_End 23 +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1_Start 20 +#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1_Type U04 + +/* X,Y = 2,1 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1 27 : 24 +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1_End 27 +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1_Start 24 +#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1_Type U04 + +/* X,Y = 3,1 */ +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1 31 : 28 +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1_End 31 +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1_Start 28 +#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1_Type U04 + +/******************************************************************************* +** State gcregPEDitherHigh +*/ + +#define gcregPEDitherHighRegAddrs 0x04BB +#define GCREG_PE_DITHER_HIGH_MSB 15 +#define GCREG_PE_DITHER_HIGH_LSB 0 +#define GCREG_PE_DITHER_LOW_HIGH_BLK 0 +#define GCREG_PE_DITHER_HIGH_Count 1 +#define GCREG_PE_DITHER_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_PE_DITHER_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_PE_DITHER_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_PE_DITHER_HIGH_ResetValue 0xFFFFFFFF + +/* X,Y = 0,2 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2 3 : 0 +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2_End 3 +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2_Start 0 +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2_Type U04 + +/* X,Y = 1,2 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2 7 : 4 +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2_End 7 +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2_Start 4 +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2_Type U04 + +/* X,Y = 2,2 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2 11 : 8 +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2_End 11 +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2_Start 8 +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2_Type U04 + +/* X,Y = 0,3 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2 15 : 12 +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2_End 15 +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2_Start 12 +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2_Type U04 + +/* X,Y = 1,3 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3 19 : 16 +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3_End 19 +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3_Start 16 +#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3_Type U04 + +/* X,Y = 2,3 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3 23 : 20 +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3_End 23 +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3_Start 20 +#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3_Type U04 + +/* X,Y = 3,3 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3 27 : 24 +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3_End 27 +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3_Start 24 +#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3_Type U04 + +/* X,Y = 3,2 */ +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3 31 : 28 +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3_End 31 +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3_Start 28 +#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3_Type U04 + +/******************************************************************************* +** State gcregSrcExConfig +*/ + +#define gcregSrcExConfigRegAddrs 0x04C0 +#define GCREG_SRC_EX_CONFIG_MSB 15 +#define GCREG_SRC_EX_CONFIG_LSB 0 +#define GCREG_SRC_EX_CONFIG_BLK 0 +#define GCREG_SRC_EX_CONFIG_Count 1 +#define GCREG_SRC_EX_CONFIG_FieldMask 0x00000109 +#define GCREG_SRC_EX_CONFIG_ReadMask 0x00000109 +#define GCREG_SRC_EX_CONFIG_WriteMask 0x00000109 +#define GCREG_SRC_EX_CONFIG_ResetValue 0x00000000 + +/* Source multi tiled address computation control. */ +#define GCREG_SRC_EX_CONFIG_MULTI_TILED 0 : 0 +#define GCREG_SRC_EX_CONFIG_MULTI_TILED_End 0 +#define GCREG_SRC_EX_CONFIG_MULTI_TILED_Start 0 +#define GCREG_SRC_EX_CONFIG_MULTI_TILED_Type U01 +#define GCREG_SRC_EX_CONFIG_MULTI_TILED_DISABLED 0x0 +#define GCREG_SRC_EX_CONFIG_MULTI_TILED_ENABLED 0x1 + +/* Source super tiled address computation control. */ +#define GCREG_SRC_EX_CONFIG_SUPER_TILED 3 : 3 +#define GCREG_SRC_EX_CONFIG_SUPER_TILED_End 3 +#define GCREG_SRC_EX_CONFIG_SUPER_TILED_Start 3 +#define GCREG_SRC_EX_CONFIG_SUPER_TILED_Type U01 +#define GCREG_SRC_EX_CONFIG_SUPER_TILED_DISABLED 0x0 +#define GCREG_SRC_EX_CONFIG_SUPER_TILED_ENABLED 0x1 + +/* Source super tiled address computation control. */ +#define GCREG_SRC_EX_CONFIG_MINOR_TILED 8 : 8 +#define GCREG_SRC_EX_CONFIG_MINOR_TILED_End 8 +#define GCREG_SRC_EX_CONFIG_MINOR_TILED_Start 8 +#define GCREG_SRC_EX_CONFIG_MINOR_TILED_Type U01 +#define GCREG_SRC_EX_CONFIG_MINOR_TILED_DISABLED 0x0 +#define GCREG_SRC_EX_CONFIG_MINOR_TILED_ENABLED 0x1 + +/******************************************************************************* +** State gcregSrcExAddress +*/ + +/* 32-bit aligned base address of the source extra surface. */ + +#define gcregSrcExAddressRegAddrs 0x04C1 +#define GCREG_SRC_EX_ADDRESS_MSB 15 +#define GCREG_SRC_EX_ADDRESS_LSB 0 +#define GCREG_SRC_EX_ADDRESS_BLK 0 +#define GCREG_SRC_EX_ADDRESS_Count 1 +#define GCREG_SRC_EX_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_SRC_EX_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_SRC_EX_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_SRC_EX_ADDRESS_ResetValue 0x00000000 + +#define GCREG_SRC_EX_ADDRESS_ADDRESS 31 : 0 +#define GCREG_SRC_EX_ADDRESS_ADDRESS_End 30 +#define GCREG_SRC_EX_ADDRESS_ADDRESS_Start 0 +#define GCREG_SRC_EX_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregDEMultiSource +*/ + +/* MutiSource control register. */ + +#define gcregDEMultiSourceRegAddrs 0x04C2 +#define GCREG_DE_MULTI_SOURCE_MSB 15 +#define GCREG_DE_MULTI_SOURCE_LSB 0 +#define GCREG_DE_MULTI_SOURCE_BLK 0 +#define GCREG_DE_MULTI_SOURCE_Count 1 +#define GCREG_DE_MULTI_SOURCE_FieldMask 0x00070707 +#define GCREG_DE_MULTI_SOURCE_ReadMask 0x00070707 +#define GCREG_DE_MULTI_SOURCE_WriteMask 0x00070707 +#define GCREG_DE_MULTI_SOURCE_ResetValue 0x00000000 + +/* Number of source surfaces minus 1. */ +#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE 2 : 0 +#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE_End 2 +#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE_Start 0 +#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE_Type U03 + +/* Number of pixels for horizontal block walker. */ +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK 10 : 8 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_End 10 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_Start 8 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_Type U03 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL16 0x0 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL32 0x1 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL64 0x2 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL128 0x3 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL256 0x4 +#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL512 0x5 + +/* Number of lines for vertical block walker. */ +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK 18 : 16 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_End 18 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_Start 16 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_Type U03 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE1 0x0 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE2 0x1 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE4 0x2 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE8 0x3 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE16 0x4 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE32 0x5 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE64 0x6 +#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE128 0x7 + +struct gcregmultisource { + /* gcregDEMultiSourceRegAddrs:GCREG_DE_MULTI_SOURCE_MAX_SOURCE */ + unsigned int srccount:3; + + /* gcregDEMultiSourceRegAddrs:reserved */ + unsigned int _reserved_3_7:5; + + /* gcregDEMultiSourceRegAddrs:GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK */ + unsigned int horblock:3; + + /* gcregDEMultiSourceRegAddrs:reserved */ + unsigned int _reserved_11_15:5; + + /* gcregDEMultiSourceRegAddrs:GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK */ + unsigned int verblock:3; + + /* gcregDEMultiSourceRegAddrs:reserved */ + unsigned int _reserved_19_31:13; +}; + +/******************************************************************************* +** State gcregDEYUVConversion +*/ + +/* Configure the YUV to YUV conversion. */ + +#define gcregDEYUVConversionRegAddrs 0x04C3 +#define GCREG_DEYUV_CONVERSION_MSB 15 +#define GCREG_DEYUV_CONVERSION_LSB 0 +#define GCREG_DEYUV_CONVERSION_BLK 0 +#define GCREG_DEYUV_CONVERSION_Count 1 +#define GCREG_DEYUV_CONVERSION_FieldMask 0xFFFFFFFF +#define GCREG_DEYUV_CONVERSION_ReadMask 0xFFFFFFFF +#define GCREG_DEYUV_CONVERSION_WriteMask 0xFFFFFFFF +#define GCREG_DEYUV_CONVERSION_ResetValue 0x00000000 + +/* Select the number of planes we need to process. */ +#define GCREG_DEYUV_CONVERSION_ENABLE 1 : 0 +#define GCREG_DEYUV_CONVERSION_ENABLE_End 1 +#define GCREG_DEYUV_CONVERSION_ENABLE_Start 0 +#define GCREG_DEYUV_CONVERSION_ENABLE_Type U02 +/* YUV to YUV conversion is turned off. */ +#define GCREG_DEYUV_CONVERSION_ENABLE_OFF 0x0 +/* YUV to YUV conversion is writing to 1 plane. */ +#define GCREG_DEYUV_CONVERSION_ENABLE_PLANE1 0x1 +/* YUV to YUV conversion is writing to 2 planes. */ +#define GCREG_DEYUV_CONVERSION_ENABLE_PLANE2 0x2 +/* YUV to YUV conversion is writing to 3 planes. */ +#define GCREG_DEYUV_CONVERSION_ENABLE_PLANE3 0x3 + +/* Number of channels to process - 1 for plane 1. */ +#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT 3 : 2 +#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT_End 3 +#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT_Start 2 +#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT_Type U02 + +/* Number of channels to process - 1 for plane 2. */ +#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT 5 : 4 +#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT_End 5 +#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT_Start 4 +#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT_Type U02 + +/* Number of channels to process - 1 for plane 3. */ +#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT 7 : 6 +#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT_End 7 +#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT_Start 6 +#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT_Type U02 + +/* Select which color channel to pick for B channel for plane 1. */ +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B 9 : 8 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_End 9 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_Start 8 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_ALPHA 0x3 + +/* Select which color channel to pick for G channel for plane 1. */ +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G 11 : 10 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_End 11 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_Start 10 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_ALPHA 0x3 + +/* Select which color channel to pick for R channel for plane 1. */ +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R 13 : 12 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_End 13 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_Start 12 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_ALPHA 0x3 + +/* Select which color channel to pick for A channel for plane 1. */ +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A 15 : 14 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_End 15 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_Start 14 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_ALPHA 0x3 + +/* Select which color channel to pick for B channel for plane 2. */ +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B 17 : 16 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_End 17 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_Start 16 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_ALPHA 0x3 + +/* Select which color channel to pick for G channel for plane 2. */ +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G 19 : 18 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_End 19 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_Start 18 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_ALPHA 0x3 + +/* Select which color channel to pick for R channel for plane 2. */ +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R 21 : 20 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_End 21 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_Start 20 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_ALPHA 0x3 + +/* Select which color channel to pick for A channel for plane 2. */ +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A 23 : 22 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_End 23 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_Start 22 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_ALPHA 0x3 + +/* Select which color channel to pick for B channel for plane 3. */ +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B 25 : 24 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_End 25 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_Start 24 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_ALPHA 0x3 + +/* Select which color channel to pick for G channel for plane 3. */ +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G 27 : 26 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_End 27 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_Start 26 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_ALPHA 0x3 + +/* Select which color channel to pick for R channel for plane 3. */ +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R 29 : 28 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_End 29 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_Start 28 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_ALPHA 0x3 + +/* Select which color channel to pick for A channel for plane 3. */ +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A 31 : 30 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_End 31 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_Start 30 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_Type U02 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_BLUE 0x0 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_GREEN 0x1 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_RED 0x2 +#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_ALPHA 0x3 + +/******************************************************************************* +** State gcregDEPlane2Address +*/ + +/* Address for plane 2 if gcregDEYUVConversion. +** Enable is set to Plane2 or Plane3. +*/ + +#define gcregDEPlane2AddressRegAddrs 0x04C4 +#define GCREG_DE_PLANE2_ADDRESS_Address 0x01310 +#define GCREG_DE_PLANE2_ADDRESS_MSB 15 +#define GCREG_DE_PLANE2_ADDRESS_LSB 0 +#define GCREG_DE_PLANE2_ADDRESS_BLK 0 +#define GCREG_DE_PLANE2_ADDRESS_Count 1 +#define GCREG_DE_PLANE2_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_DE_PLANE2_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_DE_PLANE2_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_DE_PLANE2_ADDRESS_ResetValue 0x00000000 + +#define GCREG_DE_PLANE2_ADDRESS_ADDRESS 31 : 0 +#define GCREG_DE_PLANE2_ADDRESS_ADDRESS_End 30 +#define GCREG_DE_PLANE2_ADDRESS_ADDRESS_Start 0 +#define GCREG_DE_PLANE2_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregDEPlane2Stride +*/ + +/* Stride for plane 2 if gcregDEYUVConversion. +** Enable is set to Plane2 or Plane3. +*/ + +#define gcregDEPlane2StrideRegAddrs 0x04C5 +#define GCREG_DE_PLANE2_STRIDE_MSB 15 +#define GCREG_DE_PLANE2_STRIDE_LSB 0 +#define GCREG_DE_PLANE2_STRIDE_BLK 0 +#define GCREG_DE_PLANE2_STRIDE_Count 1 +#define GCREG_DE_PLANE2_STRIDE_FieldMask 0x0003FFFF +#define GCREG_DE_PLANE2_STRIDE_ReadMask 0x0003FFFC +#define GCREG_DE_PLANE2_STRIDE_WriteMask 0x0003FFFC +#define GCREG_DE_PLANE2_STRIDE_ResetValue 0x00000000 + +#define GCREG_DE_PLANE2_STRIDE_STRIDE 17 : 0 +#define GCREG_DE_PLANE2_STRIDE_STRIDE_End 17 +#define GCREG_DE_PLANE2_STRIDE_STRIDE_Start 0 +#define GCREG_DE_PLANE2_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State gcregDEPlane3Address +*/ + +/* Address for plane 3 if gcregDEYUVConversion. +** Enable is set to Plane3. +*/ + +#define gcregDEPlane3AddressRegAddrs 0x04C6 +#define GCREG_DE_PLANE3_ADDRESS_MSB 15 +#define GCREG_DE_PLANE3_ADDRESS_LSB 0 +#define GCREG_DE_PLANE3_ADDRESS_BLK 0 +#define GCREG_DE_PLANE3_ADDRESS_Count 1 +#define GCREG_DE_PLANE3_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_DE_PLANE3_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_DE_PLANE3_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_DE_PLANE3_ADDRESS_ResetValue 0x00000000 + +#define GCREG_DE_PLANE3_ADDRESS_ADDRESS 31 : 0 +#define GCREG_DE_PLANE3_ADDRESS_ADDRESS_End 30 +#define GCREG_DE_PLANE3_ADDRESS_ADDRESS_Start 0 +#define GCREG_DE_PLANE3_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregDEPlane3Stride +*/ + +/* Stride for plane 3 if gcregDEYUVConversion. +** Enable is set to Plane3. +*/ + +#define gcregDEPlane3StrideRegAddrs 0x04C7 +#define GCREG_DE_PLANE3_STRIDE_MSB 15 +#define GCREG_DE_PLANE3_STRIDE_LSB 0 +#define GCREG_DE_PLANE3_STRIDE_BLK 0 +#define GCREG_DE_PLANE3_STRIDE_Count 1 +#define GCREG_DE_PLANE3_STRIDE_FieldMask 0x0003FFFF +#define GCREG_DE_PLANE3_STRIDE_ReadMask 0x0003FFFC +#define GCREG_DE_PLANE3_STRIDE_WriteMask 0x0003FFFC +#define GCREG_DE_PLANE3_STRIDE_ResetValue 0x00000000 + +#define GCREG_DE_PLANE3_STRIDE_STRIDE 17 : 0 +#define GCREG_DE_PLANE3_STRIDE_STRIDE_End 17 +#define GCREG_DE_PLANE3_STRIDE_STRIDE_Start 0 +#define GCREG_DE_PLANE3_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State gcregDEStallDE +*/ + +#define gcregDEStallDERegAddrs 0x04C8 +#define GCREG_DE_STALL_DE_MSB 15 +#define GCREG_DE_STALL_DE_LSB 0 +#define GCREG_DE_STALL_DE_BLK 0 +#define GCREG_DE_STALL_DE_Count 1 +#define GCREG_DE_STALL_DE_FieldMask 0x00000001 +#define GCREG_DE_STALL_DE_ReadMask 0x00000001 +#define GCREG_DE_STALL_DE_WriteMask 0x00000001 +#define GCREG_DE_STALL_DE_ResetValue 0x00000000 + +/* Stall de enable. */ +#define GCREG_DE_STALL_DE_ENABLE 0 : 0 +#define GCREG_DE_STALL_DE_ENABLE_End 0 +#define GCREG_DE_STALL_DE_ENABLE_Start 0 +#define GCREG_DE_STALL_DE_ENABLE_Type U01 +#define GCREG_DE_STALL_DE_ENABLE_DISABLED 0x0 +#define GCREG_DE_STALL_DE_ENABLE_ENABLED 0x1 + +/******************************************************************************* +** State gcregBlock4SrcAddress +*/ + +/* 32-bit aligned base address of the source surface. */ + +#define gcregBlock4SrcAddressRegAddrs 0x4A00 +#define GCREG_BLOCK4_SRC_ADDRESS_MSB 15 +#define GCREG_BLOCK4_SRC_ADDRESS_LSB 2 +#define GCREG_BLOCK4_SRC_ADDRESS_BLK 0 +#define GCREG_BLOCK4_SRC_ADDRESS_Count 4 +#define GCREG_BLOCK4_SRC_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK4_SRC_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK4_SRC_ADDRESS_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS 31 : 0 +#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS_End 30 +#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS_Start 0 +#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregBlock4SrcStride +*/ + +/* Stride of the source surface in bytes. To calculate the stride multiply +** the surface width in pixels by the number of bytes per pixel. +*/ + +#define gcregBlock4SrcStrideRegAddrs 0x4A04 +#define GCREG_BLOCK4_SRC_STRIDE_MSB 15 +#define GCREG_BLOCK4_SRC_STRIDE_LSB 2 +#define GCREG_BLOCK4_SRC_STRIDE_BLK 0 +#define GCREG_BLOCK4_SRC_STRIDE_Count 4 +#define GCREG_BLOCK4_SRC_STRIDE_FieldMask 0x0003FFFF +#define GCREG_BLOCK4_SRC_STRIDE_ReadMask 0x0003FFFC +#define GCREG_BLOCK4_SRC_STRIDE_WriteMask 0x0003FFFC +#define GCREG_BLOCK4_SRC_STRIDE_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_STRIDE_STRIDE 17 : 0 +#define GCREG_BLOCK4_SRC_STRIDE_STRIDE_End 17 +#define GCREG_BLOCK4_SRC_STRIDE_STRIDE_Start 0 +#define GCREG_BLOCK4_SRC_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State gcregBlock4SrcRotationConfig +*/ + +/* 90 degree rotation configuration for the source surface. Width field +** specifies the width of the surface in pixels. +*/ + +#define gcregBlock4SrcRotationConfigRegAddrs 0x4A08 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_MSB 15 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_LSB 2 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_BLK 0 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_Count 4 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_FieldMask 0x0001FFFF +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ReadMask 0x0001FFFF +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WriteMask 0x0001FFFF +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH 15 : 0 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH_End 15 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH_Start 0 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH_Type U16 + +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION 16 : 16 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_End 16 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_Start 16 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_Type U01 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_DISABLE 0x0 +#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_ENABLE 0x1 + +/******************************************************************************* +** State gcregBlock4SrcConfig +*/ + +/* Source surface configuration register. */ + +#define gcregBlock4SrcConfigRegAddrs 0x4A0C +#define GCREG_BLOCK4_SRC_CONFIG_MSB 15 +#define GCREG_BLOCK4_SRC_CONFIG_LSB 2 +#define GCREG_BLOCK4_SRC_CONFIG_BLK 0 +#define GCREG_BLOCK4_SRC_CONFIG_Count 4 +#define GCREG_BLOCK4_SRC_CONFIG_FieldMask 0xDF30B1C0 +#define GCREG_BLOCK4_SRC_CONFIG_ReadMask 0xDF30B1C0 +#define GCREG_BLOCK4_SRC_CONFIG_WriteMask 0xDF30B1C0 +#define GCREG_BLOCK4_SRC_CONFIG_ResetValue 0x00000000 + +/* Control source endianess. */ +#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL 31 : 30 +#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_End 31 +#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_Start 30 +#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_Type U02 +#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_NO_SWAP 0x0 +#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_SWAP_WORD 0x1 +#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_SWAP_DWORD 0x2 + +/* Defines the pixel format of the source surface. */ +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT 28 : 24 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_End 28 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_Start 24 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_Type U05 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_X4R4G4B4 0x00 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A4R4G4B4 0x01 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_X1R5G5B5 0x02 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A1R5G5B5 0x03 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_R5G6B5 0x04 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_X8R8G8B8 0x05 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 0x06 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_YUY2 0x07 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_UYVY 0x08 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_INDEX8 0x09 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_MONOCHROME 0x0A +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_YV12 0x0F +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A8 0x10 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_NV12 0x11 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_NV16 0x12 +#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_RG16 0x13 + +/* Color channel swizzles. */ +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE 21 : 20 +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_End 21 +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_Start 20 +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_Type U02 +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_ARGB 0x0 +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_RGBA 0x1 +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_ABGR 0x2 +#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_BGRA 0x3 + +/* Mono expansion: if 0, transparency color will be 0, otherwise transparency ** +** color will be 1. */ +#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY 15 : 15 +#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_End 15 +#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_Start 15 +#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_Type U01 +#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND 0x0 +#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND 0x1 + +/* Mono expansion or masked blit: stream packing in pixels. Determines how ** +** many horizontal pixels are there per each 32-bit chunk. For example, if ** +** set to Packed8, each 32-bit chunk is 8-pixel wide, which also means that ** +** it defines 4 vertical lines of pixels. */ +#define GCREG_BLOCK4_SRC_CONFIG_PACK 13 : 12 +#define GCREG_BLOCK4_SRC_CONFIG_PACK_End 13 +#define GCREG_BLOCK4_SRC_CONFIG_PACK_Start 12 +#define GCREG_BLOCK4_SRC_CONFIG_PACK_Type U02 +#define GCREG_BLOCK4_SRC_CONFIG_PACK_PACKED8 0x0 +#define GCREG_BLOCK4_SRC_CONFIG_PACK_PACKED16 0x1 +#define GCREG_BLOCK4_SRC_CONFIG_PACK_PACKED32 0x2 +#define GCREG_BLOCK4_SRC_CONFIG_PACK_UNPACKED 0x3 + +/* Source data location: set to STREAM for mono expansion blits or masked ** +** blits. For mono expansion blits the complete bitmap comes from the command ** +** stream. For masked blits the source data comes from the memory and the ** +** mask from the command stream. */ +#define GCREG_BLOCK4_SRC_CONFIG_LOCATION 8 : 8 +#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_End 8 +#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_Start 8 +#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_Type U01 +#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_MEMORY 0x0 +#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_STREAM 0x1 + +/* Source linear/tiled address computation control. */ +#define GCREG_BLOCK4_SRC_CONFIG_TILED 7 : 7 +#define GCREG_BLOCK4_SRC_CONFIG_TILED_End 7 +#define GCREG_BLOCK4_SRC_CONFIG_TILED_Start 7 +#define GCREG_BLOCK4_SRC_CONFIG_TILED_Type U01 +#define GCREG_BLOCK4_SRC_CONFIG_TILED_DISABLED 0x0 +#define GCREG_BLOCK4_SRC_CONFIG_TILED_ENABLED 0x1 + +/* If set to ABSOLUTE, the source coordinates are treated as absolute ** +** coordinates inside the source surface. If set to RELATIVE, the source ** +** coordinates are treated as the offsets from the destination coordinates ** +** with the source size equal to the size of the destination. */ +#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE 6 : 6 +#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_End 6 +#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_Start 6 +#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_Type U01 +#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE 0x0 +#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_RELATIVE 0x1 + +/******************************************************************************* +** State gcregBlock4SrcOrigin +*/ + +/* Absolute or relative (see SRC_RELATIVE field of gcregBlock4SrcConfig +** register) X and Y coordinates in pixels of the top left corner of the +** source rectangle within the source surface. +*/ + +#define gcregBlock4SrcOriginRegAddrs 0x4A10 +#define GCREG_BLOCK4_SRC_ORIGIN_MSB 15 +#define GCREG_BLOCK4_SRC_ORIGIN_LSB 2 +#define GCREG_BLOCK4_SRC_ORIGIN_BLK 0 +#define GCREG_BLOCK4_SRC_ORIGIN_Count 4 +#define GCREG_BLOCK4_SRC_ORIGIN_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_ORIGIN_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_ORIGIN_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_ORIGIN_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_ORIGIN_Y 31 : 16 +#define GCREG_BLOCK4_SRC_ORIGIN_Y_End 31 +#define GCREG_BLOCK4_SRC_ORIGIN_Y_Start 16 +#define GCREG_BLOCK4_SRC_ORIGIN_Y_Type U16 + +#define GCREG_BLOCK4_SRC_ORIGIN_X 15 : 0 +#define GCREG_BLOCK4_SRC_ORIGIN_X_End 15 +#define GCREG_BLOCK4_SRC_ORIGIN_X_Start 0 +#define GCREG_BLOCK4_SRC_ORIGIN_X_Type U16 + +/******************************************************************************* +** State gcregBlock4SrcSize +*/ + +/* Width and height of the source rectangle in pixels. If the source is +** relative (see SRC_RELATIVE field of gcregBlock4SrcConfig register) or a +** regular bitblt is being performed without stretching, this register is +** ignored and the source size is assumed to be the same as the destination. +*/ + +#define gcregBlock4SrcSizeRegAddrs 0x4A14 +#define GCREG_BLOCK4_SRC_SIZE_MSB 15 +#define GCREG_BLOCK4_SRC_SIZE_LSB 2 +#define GCREG_BLOCK4_SRC_SIZE_BLK 0 +#define GCREG_BLOCK4_SRC_SIZE_Count 4 +#define GCREG_BLOCK4_SRC_SIZE_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_SIZE_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_SIZE_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_SIZE_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_SIZE_Y 31 : 16 +#define GCREG_BLOCK4_SRC_SIZE_Y_End 31 +#define GCREG_BLOCK4_SRC_SIZE_Y_Start 16 +#define GCREG_BLOCK4_SRC_SIZE_Y_Type U16 + +#define GCREG_BLOCK4_SRC_SIZE_X 15 : 0 +#define GCREG_BLOCK4_SRC_SIZE_X_End 15 +#define GCREG_BLOCK4_SRC_SIZE_X_Start 0 +#define GCREG_BLOCK4_SRC_SIZE_X_Type U16 + +/******************************************************************************* +** State gcregBlock4SrcColorBg +*/ + +/* Select the color where source becomes transparent. It must be programmed +** in A8R8G8B8 format. +*/ + +#define gcregBlock4SrcColorBgRegAddrs 0x4A18 +#define GCREG_BLOCK4_SRC_COLOR_BG_MSB 15 +#define GCREG_BLOCK4_SRC_COLOR_BG_LSB 2 +#define GCREG_BLOCK4_SRC_COLOR_BG_BLK 0 +#define GCREG_BLOCK4_SRC_COLOR_BG_Count 4 +#define GCREG_BLOCK4_SRC_COLOR_BG_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_COLOR_BG_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_COLOR_BG_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_COLOR_BG_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA 31 : 24 +#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA_End 31 +#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA_Start 24 +#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA_Type U08 + +#define GCREG_BLOCK4_SRC_COLOR_BG_RED 23 : 16 +#define GCREG_BLOCK4_SRC_COLOR_BG_RED_End 23 +#define GCREG_BLOCK4_SRC_COLOR_BG_RED_Start 16 +#define GCREG_BLOCK4_SRC_COLOR_BG_RED_Type U08 + +#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN 15 : 8 +#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN_End 15 +#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN_Start 8 +#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN_Type U08 + +#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE 7 : 0 +#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE_End 7 +#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE_Start 0 +#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock4Rop +*/ + +/* Raster operation foreground and background codes. Even though ROP is not +** used in CLEAR, HOR_FILTER_BLT, VER_FILTER_BLT and alpha-eanbled BIT_BLTs, +** ROP code still has to be programmed, because the engine makes the decision +** whether source, destination and pattern are involved in the current +** operation and the correct decision is essential for the engine to complete +** the operation as expected. +*/ + +#define gcregBlock4RopRegAddrs 0x4A1C +#define GCREG_BLOCK4_ROP_MSB 15 +#define GCREG_BLOCK4_ROP_LSB 2 +#define GCREG_BLOCK4_ROP_BLK 0 +#define GCREG_BLOCK4_ROP_Count 4 +#define GCREG_BLOCK4_ROP_FieldMask 0x0030FFFF +#define GCREG_BLOCK4_ROP_ReadMask 0x0030FFFF +#define GCREG_BLOCK4_ROP_WriteMask 0x0030FFFF +#define GCREG_BLOCK4_ROP_ResetValue 0x00000000 + +/* ROP type: ROP2, ROP3 or ROP4 */ +#define GCREG_BLOCK4_ROP_TYPE 21 : 20 +#define GCREG_BLOCK4_ROP_TYPE_End 21 +#define GCREG_BLOCK4_ROP_TYPE_Start 20 +#define GCREG_BLOCK4_ROP_TYPE_Type U02 +#define GCREG_BLOCK4_ROP_TYPE_ROP2_PATTERN 0x0 +#define GCREG_BLOCK4_ROP_TYPE_ROP2_SOURCE 0x1 +#define GCREG_BLOCK4_ROP_TYPE_ROP3 0x2 +#define GCREG_BLOCK4_ROP_TYPE_ROP4 0x3 + +/* Background ROP code is used for transparent pixels. */ +#define GCREG_BLOCK4_ROP_ROP_BG 15 : 8 +#define GCREG_BLOCK4_ROP_ROP_BG_End 15 +#define GCREG_BLOCK4_ROP_ROP_BG_Start 8 +#define GCREG_BLOCK4_ROP_ROP_BG_Type U08 + +/* Background ROP code is used for opaque pixels. */ +#define GCREG_BLOCK4_ROP_ROP_FG 7 : 0 +#define GCREG_BLOCK4_ROP_ROP_FG_End 7 +#define GCREG_BLOCK4_ROP_ROP_FG_Start 0 +#define GCREG_BLOCK4_ROP_ROP_FG_Type U08 + +/******************************************************************************* +** State gcregBlock4AlphaControl +*/ + +#define gcregBlock4AlphaControlRegAddrs 0x4A20 +#define GCREG_BLOCK4_ALPHA_CONTROL_MSB 15 +#define GCREG_BLOCK4_ALPHA_CONTROL_LSB 2 +#define GCREG_BLOCK4_ALPHA_CONTROL_BLK 0 +#define GCREG_BLOCK4_ALPHA_CONTROL_Count 4 +#define GCREG_BLOCK4_ALPHA_CONTROL_FieldMask 0x00000001 +#define GCREG_BLOCK4_ALPHA_CONTROL_ReadMask 0x00000001 +#define GCREG_BLOCK4_ALPHA_CONTROL_WriteMask 0x00000001 +#define GCREG_BLOCK4_ALPHA_CONTROL_ResetValue 0x00000000 + +#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE 0 : 0 +#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_End 0 +#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_Start 0 +#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_Type U01 +#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_OFF 0x0 +#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_ON 0x1 + +/******************************************************************************* +** State gcregBlock4AlphaModes +*/ + +#define gcregBlock4AlphaModesRegAddrs 0x4A24 +#define GCREG_BLOCK4_ALPHA_MODES_MSB 15 +#define GCREG_BLOCK4_ALPHA_MODES_LSB 2 +#define GCREG_BLOCK4_ALPHA_MODES_BLK 0 +#define GCREG_BLOCK4_ALPHA_MODES_Count 4 +#define GCREG_BLOCK4_ALPHA_MODES_FieldMask 0xFF003311 +#define GCREG_BLOCK4_ALPHA_MODES_ReadMask 0xFF003311 +#define GCREG_BLOCK4_ALPHA_MODES_WriteMask 0xFF003311 +#define GCREG_BLOCK4_ALPHA_MODES_ResetValue 0x00000000 + +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE 0 : 0 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_End 0 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_Start 0 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_Type U01 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED 0x1 + +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE 4 : 4 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_End 4 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_Start 4 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_Type U01 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_INVERSED 0x1 + +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE 9 : 8 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_End 9 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Start 8 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Type U02 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL 0x1 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED 0x2 + +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE 13 : 12 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_End 13 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Start 12 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Type U02 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL 0x1 +#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED 0x2 + +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE 26 : 24 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_End 26 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_Start 24 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_Type U03 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_ZERO 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_ONE 0x1 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_NORMAL 0x2 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_INVERSED 0x3 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_COLOR 0x4 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_COLOR_INVERSED 0x5 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_ALPHA 0x6 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_DEST_ALPHA 0x7 + +/* Src Blending factor is calculate from Src alpha. */ +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR 27 : 27 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_End 27 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_Start 27 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_Type U01 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLED 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLED 0x1 + +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE 30 : 28 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_End 30 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_Start 28 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_Type U03 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_ZERO 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_ONE 0x1 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_NORMAL 0x2 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_INVERSED 0x3 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_COLOR 0x4 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_COLOR_INVERSED 0x5 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_ALPHA 0x6 +#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_DEST_ALPHA 0x7 + +/* Dst Blending factor is calculate from Dst alpha. */ +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR 31 : 31 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_End 31 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_Start 31 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_Type U01 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLED 0x0 +#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLED 0x1 + +/******************************************************************************* +** State gcregBlock4AddressU +*/ + +/* 32-bit aligned base address of the source U plane. */ + +#define gcregBlock4AddressURegAddrs 0x4A28 +#define GCREG_BLOCK4_ADDRESS_U_MSB 15 +#define GCREG_BLOCK4_ADDRESS_U_LSB 2 +#define GCREG_BLOCK4_ADDRESS_U_BLK 0 +#define GCREG_BLOCK4_ADDRESS_U_Count 4 +#define GCREG_BLOCK4_ADDRESS_U_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_ADDRESS_U_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK4_ADDRESS_U_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK4_ADDRESS_U_ResetValue 0x00000000 + +#define GCREG_BLOCK4_ADDRESS_U_ADDRESS 31 : 0 +#define GCREG_BLOCK4_ADDRESS_U_ADDRESS_End 30 +#define GCREG_BLOCK4_ADDRESS_U_ADDRESS_Start 0 +#define GCREG_BLOCK4_ADDRESS_U_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregBlock4StrideU +*/ + +/* Stride of the source U plane in bytes. */ + +#define gcregBlock4StrideURegAddrs 0x4A2C +#define GCREG_BLOCK4_STRIDE_U_MSB 15 +#define GCREG_BLOCK4_STRIDE_U_LSB 2 +#define GCREG_BLOCK4_STRIDE_U_BLK 0 +#define GCREG_BLOCK4_STRIDE_U_Count 4 +#define GCREG_BLOCK4_STRIDE_U_FieldMask 0x0003FFFF +#define GCREG_BLOCK4_STRIDE_U_ReadMask 0x0003FFFC +#define GCREG_BLOCK4_STRIDE_U_WriteMask 0x0003FFFC +#define GCREG_BLOCK4_STRIDE_U_ResetValue 0x00000000 + +#define GCREG_BLOCK4_STRIDE_U_STRIDE 17 : 0 +#define GCREG_BLOCK4_STRIDE_U_STRIDE_End 17 +#define GCREG_BLOCK4_STRIDE_U_STRIDE_Start 0 +#define GCREG_BLOCK4_STRIDE_U_STRIDE_Type U18 + +/******************************************************************************* +** State gcregBlock4AddressV +*/ + +/* 32-bit aligned base address of the source V plane. */ + +#define gcregBlock4AddressVRegAddrs 0x4A30 +#define GCREG_BLOCK4_ADDRESS_V_MSB 15 +#define GCREG_BLOCK4_ADDRESS_V_LSB 2 +#define GCREG_BLOCK4_ADDRESS_V_BLK 0 +#define GCREG_BLOCK4_ADDRESS_V_Count 4 +#define GCREG_BLOCK4_ADDRESS_V_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_ADDRESS_V_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK4_ADDRESS_V_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK4_ADDRESS_V_ResetValue 0x00000000 + +#define GCREG_BLOCK4_ADDRESS_V_ADDRESS 31 : 0 +#define GCREG_BLOCK4_ADDRESS_V_ADDRESS_End 30 +#define GCREG_BLOCK4_ADDRESS_V_ADDRESS_Start 0 +#define GCREG_BLOCK4_ADDRESS_V_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregBlock4StrideV +*/ + +/* Stride of the source V plane in bytes. */ + +#define gcregBlock4StrideVRegAddrs 0x4A34 +#define GCREG_BLOCK4_STRIDE_V_MSB 15 +#define GCREG_BLOCK4_STRIDE_V_LSB 2 +#define GCREG_BLOCK4_STRIDE_V_BLK 0 +#define GCREG_BLOCK4_STRIDE_V_Count 4 +#define GCREG_BLOCK4_STRIDE_V_FieldMask 0x0003FFFF +#define GCREG_BLOCK4_STRIDE_V_ReadMask 0x0003FFFC +#define GCREG_BLOCK4_STRIDE_V_WriteMask 0x0003FFFC +#define GCREG_BLOCK4_STRIDE_V_ResetValue 0x00000000 + +#define GCREG_BLOCK4_STRIDE_V_STRIDE 17 : 0 +#define GCREG_BLOCK4_STRIDE_V_STRIDE_End 17 +#define GCREG_BLOCK4_STRIDE_V_STRIDE_Start 0 +#define GCREG_BLOCK4_STRIDE_V_STRIDE_Type U18 + +/******************************************************************************* +** State gcregBlock4SrcRotationHeight +*/ + +/* 180/270 degree rotation configuration for the Source surface. Height field +** specifies the height of the surface in pixels. +*/ + +#define gcregBlock4SrcRotationHeightRegAddrs 0x4A38 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_MSB 15 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_LSB 2 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_BLK 0 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_Count 4 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_FieldMask 0x0000FFFF +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_ReadMask 0x0000FFFF +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_WriteMask 0x0000FFFF +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT 15 : 0 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT_End 15 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT_Start 0 +#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT_Type U16 + +/******************************************************************************* +** State gcregBlock4RotAngle +*/ + +/* 0/90/180/270 degree rotation configuration for the Source surface. Height +** field specifies the height of the surface in pixels. +*/ + +#define gcregBlock4RotAngleRegAddrs 0x4A3C +#define GCREG_BLOCK4_ROT_ANGLE_MSB 15 +#define GCREG_BLOCK4_ROT_ANGLE_LSB 2 +#define GCREG_BLOCK4_ROT_ANGLE_BLK 0 +#define GCREG_BLOCK4_ROT_ANGLE_Count 4 +#define GCREG_BLOCK4_ROT_ANGLE_FieldMask 0x000BB33F +#define GCREG_BLOCK4_ROT_ANGLE_ReadMask 0x000BB33F +#define GCREG_BLOCK4_ROT_ANGLE_WriteMask 0x000BB33F +#define GCREG_BLOCK4_ROT_ANGLE_ResetValue 0x00000000 + +#define GCREG_BLOCK4_ROT_ANGLE_SRC 2 : 0 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_End 2 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_Start 0 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_Type U03 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_ROT0 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_FLIP_X 0x1 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_FLIP_Y 0x2 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_ROT90 0x4 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_ROT180 0x5 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_ROT270 0x6 + +#define GCREG_BLOCK4_ROT_ANGLE_DST 5 : 3 +#define GCREG_BLOCK4_ROT_ANGLE_DST_End 5 +#define GCREG_BLOCK4_ROT_ANGLE_DST_Start 3 +#define GCREG_BLOCK4_ROT_ANGLE_DST_Type U03 +#define GCREG_BLOCK4_ROT_ANGLE_DST_ROT0 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_DST_FLIP_X 0x1 +#define GCREG_BLOCK4_ROT_ANGLE_DST_FLIP_Y 0x2 +#define GCREG_BLOCK4_ROT_ANGLE_DST_ROT90 0x4 +#define GCREG_BLOCK4_ROT_ANGLE_DST_ROT180 0x5 +#define GCREG_BLOCK4_ROT_ANGLE_DST_ROT270 0x6 + +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC 8 : 8 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_End 8 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_Start 8 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_Type U01 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_ENABLED 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MASKED 0x1 + +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST 9 : 9 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_End 9 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_Start 9 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_Type U01 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_ENABLED 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MASKED 0x1 + +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR 13 : 12 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_End 13 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_Start 12 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_Type U02 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_NONE 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_MIRROR_X 0x1 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_MIRROR_Y 0x2 +#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_MIRROR_XY 0x3 + +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR 15 : 15 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_End 15 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_Start 15 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_Type U01 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_ENABLED 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_MASKED 0x1 + +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR 17 : 16 +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_End 17 +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_Start 16 +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_Type U02 +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_NONE 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_MIRROR_X 0x1 +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_MIRROR_Y 0x2 +#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_MIRROR_XY 0x3 + +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR 19 : 19 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_End 19 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_Start 19 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_Type U01 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_ENABLED 0x0 +#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_MASKED 0x1 + +/******************************************************************************* +** State gcregBlock4GlobalSrcColor +*/ + +/* Defines the global source color and alpha values. */ + +#define gcregBlock4GlobalSrcColorRegAddrs 0x4A40 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_MSB 15 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_LSB 2 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLK 0 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_Count 4 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ResetValue 0x00000000 + +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA 31 : 24 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA_End 31 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA_Start 24 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA_Type U08 + +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED 23 : 16 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED_End 23 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED_Start 16 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED_Type U08 + +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN 15 : 8 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN_End 15 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN_Start 8 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN_Type U08 + +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE 7 : 0 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE_End 7 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE_Start 0 +#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock4GlobalDestColor +*/ + +/* Defines the global destination color and alpha values. */ + +#define gcregBlock4GlobalDestColorRegAddrs 0x4A44 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_MSB 15 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_LSB 2 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLK 0 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_Count 4 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ResetValue 0x00000000 + +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA 31 : 24 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA_End 31 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA_Start 24 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA_Type U08 + +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED 23 : 16 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED_End 23 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED_Start 16 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED_Type U08 + +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN 15 : 8 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN_End 15 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN_Start 8 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN_Type U08 + +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE 7 : 0 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE_End 7 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE_Start 0 +#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock4ColorMultiplyModes +*/ + +/* Color modes to multiply Source or Destination pixel color by alpha +** channel. Alpha can be from global color source or current pixel. +*/ + +#define gcregBlock4ColorMultiplyModesRegAddrs 0x4A48 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_MSB 15 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_LSB 2 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_BLK 0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_Count 4 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_FieldMask 0x00100311 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_ReadMask 0x00100311 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_WriteMask 0x00100311 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_ResetValue 0x00000000 + +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY 0 : 0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_End 0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Start 0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Type U01 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE 0x1 + +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY 4 : 4 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_End 4 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Start 4 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Type U01 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE 0x1 + +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY 9 : 8 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_End 9 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Start 8 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Type U02 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA 0x1 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR 0x2 + +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY 20 : 20 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_End 20 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Start 20 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Type U01 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE 0x1 + +/******************************************************************************* +** State gcregBlock4Transparency +*/ + +#define gcregBlock4TransparencyRegAddrs 0x4A4C +#define GCREG_BLOCK4_TRANSPARENCY_MSB 15 +#define GCREG_BLOCK4_TRANSPARENCY_LSB 2 +#define GCREG_BLOCK4_TRANSPARENCY_BLK 0 +#define GCREG_BLOCK4_TRANSPARENCY_Count 4 +#define GCREG_BLOCK4_TRANSPARENCY_FieldMask 0xB3331333 +#define GCREG_BLOCK4_TRANSPARENCY_ReadMask 0xB3331333 +#define GCREG_BLOCK4_TRANSPARENCY_WriteMask 0xB3331333 +#define GCREG_BLOCK4_TRANSPARENCY_ResetValue 0x00000000 + +/* Source transparency mode. */ +#define GCREG_BLOCK4_TRANSPARENCY_SOURCE 1 : 0 +#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_End 1 +#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_Start 0 +#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_Type U02 +#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_OPAQUE 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_MASK 0x1 +#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_KEY 0x2 + +/* Pattern transparency mode. KEY transparency mode is reserved. */ +#define GCREG_BLOCK4_TRANSPARENCY_PATTERN 5 : 4 +#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_End 5 +#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_Start 4 +#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_Type U02 +#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_OPAQUE 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_MASK 0x1 +#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_KEY 0x2 + +/* Destination transparency mode. MASK transparency mode is reserved. */ +#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION 9 : 8 +#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_End 9 +#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_Start 8 +#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_Type U02 +#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_OPAQUE 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_MASK 0x1 +#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_KEY 0x2 + +/* Mask field for Source/Pattern/Destination fields. */ +#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY 12 : 12 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_End 12 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_Start 12 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_Type U01 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_ENABLED 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_MASKED 0x1 + +/* Source usage override. */ +#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE 17 : 16 +#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_End 17 +#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_Start 16 +#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_Type U02 +#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE 0x2 + +/* Pattern usage override. */ +#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE 21 : 20 +#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_End 21 +#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_Start 20 +#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_Type U02 +#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE 0x2 + +/* Destination usage override. */ +#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE 25 : 24 +#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_End 25 +#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_Start 24 +#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_Type U02 +#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE 0x2 + +/* 2D resource usage override mask field. */ +#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE 28 : 28 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_End 28 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Start 28 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Type U01 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_ENABLED 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_MASKED 0x1 + +/* DFB Color Key. */ +#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY 29 : 29 +#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_End 29 +#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_Start 29 +#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_Type U01 +#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_DISABLED 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_ENABLED 0x1 + +#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY 31 : 31 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_End 31 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_Start 31 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_Type U01 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_ENABLED 0x0 +#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_MASKED 0x1 + +/******************************************************************************* +** State gcregBlock4Control +*/ + +/* General purpose control register. */ + +#define gcregBlock4ControlRegAddrs 0x4A50 +#define GCREG_BLOCK4_CONTROL_MSB 15 +#define GCREG_BLOCK4_CONTROL_LSB 2 +#define GCREG_BLOCK4_CONTROL_BLK 0 +#define GCREG_BLOCK4_CONTROL_Count 4 +#define GCREG_BLOCK4_CONTROL_FieldMask 0x00000999 +#define GCREG_BLOCK4_CONTROL_ReadMask 0x00000999 +#define GCREG_BLOCK4_CONTROL_WriteMask 0x00000999 +#define GCREG_BLOCK4_CONTROL_ResetValue 0x00000000 + +#define GCREG_BLOCK4_CONTROL_YUV 0 : 0 +#define GCREG_BLOCK4_CONTROL_YUV_End 0 +#define GCREG_BLOCK4_CONTROL_YUV_Start 0 +#define GCREG_BLOCK4_CONTROL_YUV_Type U01 +#define GCREG_BLOCK4_CONTROL_YUV_601 0x0 +#define GCREG_BLOCK4_CONTROL_YUV_709 0x1 + +#define GCREG_BLOCK4_CONTROL_MASK_YUV 3 : 3 +#define GCREG_BLOCK4_CONTROL_MASK_YUV_End 3 +#define GCREG_BLOCK4_CONTROL_MASK_YUV_Start 3 +#define GCREG_BLOCK4_CONTROL_MASK_YUV_Type U01 +#define GCREG_BLOCK4_CONTROL_MASK_YUV_ENABLED 0x0 +#define GCREG_BLOCK4_CONTROL_MASK_YUV_MASKED 0x1 + +#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE 4 : 4 +#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_End 4 +#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_Start 4 +#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_Type U01 +#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_UV 0x0 +#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_VU 0x1 + +#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE 7 : 7 +#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_End 7 +#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_Start 7 +#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_Type U01 +#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_ENABLED 0x0 +#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_MASKED 0x1 + +/* YUV to RGB convert enable */ +#define GCREG_BLOCK4_CONTROL_YUVRGB 8 : 8 +#define GCREG_BLOCK4_CONTROL_YUVRGB_End 8 +#define GCREG_BLOCK4_CONTROL_YUVRGB_Start 8 +#define GCREG_BLOCK4_CONTROL_YUVRGB_Type U01 +#define GCREG_BLOCK4_CONTROL_YUVRGB_DISABLED 0x0 +#define GCREG_BLOCK4_CONTROL_YUVRGB_ENABLED 0x1 + +#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB 11 : 11 +#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_End 11 +#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_Start 11 +#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_Type U01 +#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_ENABLED 0x0 +#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_MASKED 0x1 + +/******************************************************************************* +** State gcregBlock4SrcColorKeyHigh +*/ + +/* Defines the source transparency color in source format. */ + +#define gcregBlock4SrcColorKeyHighRegAddrs 0x4A54 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_MSB 15 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_LSB 2 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLK 0 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_Count 4 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA 31 : 24 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA_End 31 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA_Start 24 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA_Type U08 + +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED 23 : 16 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED_End 23 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED_Start 16 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED_Type U08 + +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN 15 : 8 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN_End 15 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN_Start 8 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN_Type U08 + +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE 7 : 0 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE_End 7 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE_Start 0 +#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock4SrcExConfig +*/ + +#define gcregBlock4SrcExConfigRegAddrs 0x4A58 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MSB 15 +#define GCREG_BLOCK4_SRC_EX_CONFIG_LSB 2 +#define GCREG_BLOCK4_SRC_EX_CONFIG_BLK 0 +#define GCREG_BLOCK4_SRC_EX_CONFIG_Count 4 +#define GCREG_BLOCK4_SRC_EX_CONFIG_FieldMask 0x00000109 +#define GCREG_BLOCK4_SRC_EX_CONFIG_ReadMask 0x00000109 +#define GCREG_BLOCK4_SRC_EX_CONFIG_WriteMask 0x00000109 +#define GCREG_BLOCK4_SRC_EX_CONFIG_ResetValue 0x00000000 + +/* Source multi tiled address computation control. */ +#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED 0 : 0 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_End 0 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_Start 0 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_Type U01 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_DISABLED 0x0 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_ENABLED 0x1 + +/* Source super tiled address computation control. */ +#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED 3 : 3 +#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_End 3 +#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_Start 3 +#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_Type U01 +#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_DISABLED 0x0 +#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_ENABLED 0x1 + +/* Source super tiled address computation control. */ +#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED 8 : 8 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_End 8 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_Start 8 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_Type U01 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_DISABLED 0x0 +#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_ENABLED 0x1 + +/******************************************************************************* +** State gcregBlock4SrcExAddress +*/ + +/* 32-bit aligned base address of the source extra surface. */ + +#define gcregBlock4SrcExAddressRegAddrs 0x4A5C +#define GCREG_BLOCK4_SRC_EX_ADDRESS_MSB 15 +#define GCREG_BLOCK4_SRC_EX_ADDRESS_LSB 2 +#define GCREG_BLOCK4_SRC_EX_ADDRESS_BLK 0 +#define GCREG_BLOCK4_SRC_EX_ADDRESS_Count 4 +#define GCREG_BLOCK4_SRC_EX_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK4_SRC_EX_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK4_SRC_EX_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK4_SRC_EX_ADDRESS_ResetValue 0x00000000 + +#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS 31 : 0 +#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS_End 30 +#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS_Start 0 +#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregBlock8SrcAddressEx +*/ + +/* 32-bit aligned base address of the source surface. */ + +#define gcregBlock8SrcAddressRegAddrs 0x4A80 +#define GCREG_BLOCK8_SRC_ADDRESS_MSB 15 +#define GCREG_BLOCK8_SRC_ADDRESS_LSB 3 +#define GCREG_BLOCK8_SRC_ADDRESS_BLK 0 +#define GCREG_BLOCK8_SRC_ADDRESS_Count 8 +#define GCREG_BLOCK8_SRC_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK8_SRC_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK8_SRC_ADDRESS_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS 31 : 0 +#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS_End 30 +#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS_Start 0 +#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregBlock8SrcStride +*/ + +/* Stride of the source surface in bytes. To calculate the stride multiply +** the surface width in pixels by the number of bytes per pixel. +*/ + +#define gcregBlock8SrcStrideRegAddrs 0x4A88 +#define GCREG_BLOCK8_SRC_STRIDE_MSB 15 +#define GCREG_BLOCK8_SRC_STRIDE_LSB 3 +#define GCREG_BLOCK8_SRC_STRIDE_BLK 0 +#define GCREG_BLOCK8_SRC_STRIDE_Count 8 +#define GCREG_BLOCK8_SRC_STRIDE_FieldMask 0x0003FFFF +#define GCREG_BLOCK8_SRC_STRIDE_ReadMask 0x0003FFFC +#define GCREG_BLOCK8_SRC_STRIDE_WriteMask 0x0003FFFC +#define GCREG_BLOCK8_SRC_STRIDE_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_STRIDE_STRIDE 17 : 0 +#define GCREG_BLOCK8_SRC_STRIDE_STRIDE_End 17 +#define GCREG_BLOCK8_SRC_STRIDE_STRIDE_Start 0 +#define GCREG_BLOCK8_SRC_STRIDE_STRIDE_Type U18 + +/******************************************************************************* +** State gcregBlock8SrcRotationConfig +*/ + +/* 90 degree rotation configuration for the source surface. Width field +** specifies the width of the surface in pixels. +*/ + +#define gcregBlock8SrcRotationConfigRegAddrs 0x4A90 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_MSB 15 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_LSB 3 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_BLK 0 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_Count 8 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_FieldMask 0x0001FFFF +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ReadMask 0x0001FFFF +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WriteMask 0x0001FFFF +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH 15 : 0 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH_End 15 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH_Start 0 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH_Type U16 + +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION 16 : 16 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_End 16 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_Start 16 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_Type U01 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_NORMAL 0x0 +#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_ROTATED 0x1 + +/******************************************************************************* +** State gcregBlock8SrcConfig +*/ + +/* Source surface configuration register. */ + +#define gcregBlock8SrcConfigRegAddrs 0x4A98 +#define GCREG_BLOCK8_SRC_CONFIG_MSB 15 +#define GCREG_BLOCK8_SRC_CONFIG_LSB 3 +#define GCREG_BLOCK8_SRC_CONFIG_BLK 0 +#define GCREG_BLOCK8_SRC_CONFIG_Count 8 +#define GCREG_BLOCK8_SRC_CONFIG_FieldMask 0xDF30B1C0 +#define GCREG_BLOCK8_SRC_CONFIG_ReadMask 0xDF30B1C0 +#define GCREG_BLOCK8_SRC_CONFIG_WriteMask 0xDF30B1C0 +#define GCREG_BLOCK8_SRC_CONFIG_ResetValue 0x00000000 + +/* Control source endianess. */ +#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL 31 : 30 +#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_End 31 +#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_Start 30 +#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_Type U02 +#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_NO_SWAP 0x0 +#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_SWAP_WORD 0x1 +#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_SWAP_DWORD 0x2 + +/* Defines the pixel format of the source surface. */ +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT 28 : 24 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_End 28 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_Start 24 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_Type U05 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_X4R4G4B4 0x00 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A4R4G4B4 0x01 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_X1R5G5B5 0x02 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A1R5G5B5 0x03 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_R5G6B5 0x04 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_X8R8G8B8 0x05 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 0x06 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_YUY2 0x07 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_UYVY 0x08 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_INDEX8 0x09 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_MONOCHROME 0x0A +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_YV12 0x0F +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A8 0x10 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_NV12 0x11 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_NV16 0x12 +#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_RG16 0x13 + +/* Color channel swizzles. */ +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE 21 : 20 +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_End 21 +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_Start 20 +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_Type U02 +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_ARGB 0x0 +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_RGBA 0x1 +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_ABGR 0x2 +#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_BGRA 0x3 + +/* Mono expansion: if 0, transparency color will be 0, otherwise transparency ** +** color will be 1. */ +#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY 15 : 15 +#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_End 15 +#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_Start 15 +#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_Type U01 +#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND 0x0 +#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND 0x1 + +/* Mono expansion or masked blit: stream packing in pixels. Determines how ** +** many horizontal pixels are there per each 32-bit chunk. For example, if ** +** set to Packed8, each 32-bit chunk is 8-pixel wide, which also means that ** +** it defines 4 vertical lines of pixels. */ +#define GCREG_BLOCK8_SRC_CONFIG_PACK 13 : 12 +#define GCREG_BLOCK8_SRC_CONFIG_PACK_End 13 +#define GCREG_BLOCK8_SRC_CONFIG_PACK_Start 12 +#define GCREG_BLOCK8_SRC_CONFIG_PACK_Type U02 +#define GCREG_BLOCK8_SRC_CONFIG_PACK_PACKED8 0x0 +#define GCREG_BLOCK8_SRC_CONFIG_PACK_PACKED16 0x1 +#define GCREG_BLOCK8_SRC_CONFIG_PACK_PACKED32 0x2 +#define GCREG_BLOCK8_SRC_CONFIG_PACK_UNPACKED 0x3 + +/* Source data location: set to STREAM for mono expansion blits or masked ** +** blits. For mono expansion blits the complete bitmap comes from the command ** +** stream. For masked blits the source data comes from the memory and the ** +** mask from the command stream. */ +#define GCREG_BLOCK8_SRC_CONFIG_LOCATION 8 : 8 +#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_End 8 +#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_Start 8 +#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_Type U01 +#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_MEMORY 0x0 +#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_STREAM 0x1 + +/* Source linear/tiled address computation control. */ +#define GCREG_BLOCK8_SRC_CONFIG_TILED 7 : 7 +#define GCREG_BLOCK8_SRC_CONFIG_TILED_End 7 +#define GCREG_BLOCK8_SRC_CONFIG_TILED_Start 7 +#define GCREG_BLOCK8_SRC_CONFIG_TILED_Type U01 +#define GCREG_BLOCK8_SRC_CONFIG_TILED_DISABLED 0x0 +#define GCREG_BLOCK8_SRC_CONFIG_TILED_ENABLED 0x1 + +/* If set to ABSOLUTE, the source coordinates are treated as absolute ** +** coordinates inside the source surface. If set to RELATIVE, the source ** +** coordinates are treated as the offsets from the destination coordinates ** +** with the source size equal to the size of the destination. */ +#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE 6 : 6 +#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_End 6 +#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_Start 6 +#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_Type U01 +#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE 0x0 +#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_RELATIVE 0x1 + +/******************************************************************************* +** State gcregBlock8SrcOrigin +*/ + +/* Absolute or relative (see SRC_RELATIVE field of gcregBlock8SrcConfig +** register) X and Y coordinates in pixels of the top left corner of the +** source rectangle within the source surface. +*/ + +#define gcregBlock8SrcOriginRegAddrs 0x4AA0 +#define GCREG_BLOCK8_SRC_ORIGIN_MSB 15 +#define GCREG_BLOCK8_SRC_ORIGIN_LSB 3 +#define GCREG_BLOCK8_SRC_ORIGIN_BLK 0 +#define GCREG_BLOCK8_SRC_ORIGIN_Count 8 +#define GCREG_BLOCK8_SRC_ORIGIN_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_ORIGIN_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_ORIGIN_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_ORIGIN_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_ORIGIN_Y 31 : 16 +#define GCREG_BLOCK8_SRC_ORIGIN_Y_End 31 +#define GCREG_BLOCK8_SRC_ORIGIN_Y_Start 16 +#define GCREG_BLOCK8_SRC_ORIGIN_Y_Type U16 + +#define GCREG_BLOCK8_SRC_ORIGIN_X 15 : 0 +#define GCREG_BLOCK8_SRC_ORIGIN_X_End 15 +#define GCREG_BLOCK8_SRC_ORIGIN_X_Start 0 +#define GCREG_BLOCK8_SRC_ORIGIN_X_Type U16 + +/******************************************************************************* +** State gcregBlock8SrcSize +*/ + +/* Width and height of the source rectangle in pixels. If the source is +** relative (see SRC_RELATIVE field of gcregBlock8SrcConfig register) or a +** regular bitblt is being performed without stretching, this register is +** ignored and the source size is assumed to be the same as the destination. +*/ + +#define gcregBlock8SrcSizeRegAddrs 0x4AA8 +#define GCREG_BLOCK8_SRC_SIZE_MSB 15 +#define GCREG_BLOCK8_SRC_SIZE_LSB 3 +#define GCREG_BLOCK8_SRC_SIZE_BLK 0 +#define GCREG_BLOCK8_SRC_SIZE_Count 8 +#define GCREG_BLOCK8_SRC_SIZE_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_SIZE_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_SIZE_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_SIZE_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_SIZE_Y 31 : 16 +#define GCREG_BLOCK8_SRC_SIZE_Y_End 31 +#define GCREG_BLOCK8_SRC_SIZE_Y_Start 16 +#define GCREG_BLOCK8_SRC_SIZE_Y_Type U16 + +#define GCREG_BLOCK8_SRC_SIZE_X 15 : 0 +#define GCREG_BLOCK8_SRC_SIZE_X_End 15 +#define GCREG_BLOCK8_SRC_SIZE_X_Start 0 +#define GCREG_BLOCK8_SRC_SIZE_X_Type U16 + +/******************************************************************************* +** State gcregBlock8SrcColorBg +*/ + +/* Select the color where source becomes transparent. It must be programmed +** in A8R8G8B8 format. +*/ + +#define gcregBlock8SrcColorBgRegAddrs 0x4AB0 +#define GCREG_BLOCK8_SRC_COLOR_BG_MSB 15 +#define GCREG_BLOCK8_SRC_COLOR_BG_LSB 3 +#define GCREG_BLOCK8_SRC_COLOR_BG_BLK 0 +#define GCREG_BLOCK8_SRC_COLOR_BG_Count 8 +#define GCREG_BLOCK8_SRC_COLOR_BG_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_COLOR_BG_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_COLOR_BG_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_COLOR_BG_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA 31 : 24 +#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA_End 31 +#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA_Start 24 +#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA_Type U08 + +#define GCREG_BLOCK8_SRC_COLOR_BG_RED 23 : 16 +#define GCREG_BLOCK8_SRC_COLOR_BG_RED_End 23 +#define GCREG_BLOCK8_SRC_COLOR_BG_RED_Start 16 +#define GCREG_BLOCK8_SRC_COLOR_BG_RED_Type U08 + +#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN 15 : 8 +#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN_End 15 +#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN_Start 8 +#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN_Type U08 + +#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE 7 : 0 +#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE_End 7 +#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE_Start 0 +#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock8Rop +*/ + +/* Raster operation foreground and background codes. Even though ROP is not +** used in CLEAR, HOR_FILTER_BLT, VER_FILTER_BLT and alpha-eanbled BIT_BLTs, +** ROP code still has to be programmed, because the engine makes the decision +** whether source, destination and pattern are involved in the current +** operation and the correct decision is essential for the engine to complete +** the operation as expected. +*/ + +#define gcregBlock8RopRegAddrs 0x4AB8 +#define GCREG_BLOCK8_ROP_MSB 15 +#define GCREG_BLOCK8_ROP_LSB 3 +#define GCREG_BLOCK8_ROP_BLK 0 +#define GCREG_BLOCK8_ROP_Count 8 +#define GCREG_BLOCK8_ROP_FieldMask 0x0030FFFF +#define GCREG_BLOCK8_ROP_ReadMask 0x0030FFFF +#define GCREG_BLOCK8_ROP_WriteMask 0x0030FFFF +#define GCREG_BLOCK8_ROP_ResetValue 0x00000000 + +/* ROP type: ROP2, ROP3 or ROP4 */ +#define GCREG_BLOCK8_ROP_TYPE 21 : 20 +#define GCREG_BLOCK8_ROP_TYPE_End 21 +#define GCREG_BLOCK8_ROP_TYPE_Start 20 +#define GCREG_BLOCK8_ROP_TYPE_Type U02 +#define GCREG_BLOCK8_ROP_TYPE_ROP2_PATTERN 0x0 +#define GCREG_BLOCK8_ROP_TYPE_ROP2_SOURCE 0x1 +#define GCREG_BLOCK8_ROP_TYPE_ROP3 0x2 +#define GCREG_BLOCK8_ROP_TYPE_ROP4 0x3 + +/* Background ROP code is used for transparent pixels. */ +#define GCREG_BLOCK8_ROP_ROP_BG 15 : 8 +#define GCREG_BLOCK8_ROP_ROP_BG_End 15 +#define GCREG_BLOCK8_ROP_ROP_BG_Start 8 +#define GCREG_BLOCK8_ROP_ROP_BG_Type U08 + +/* Background ROP code is used for opaque pixels. */ +#define GCREG_BLOCK8_ROP_ROP_FG 7 : 0 +#define GCREG_BLOCK8_ROP_ROP_FG_End 7 +#define GCREG_BLOCK8_ROP_ROP_FG_Start 0 +#define GCREG_BLOCK8_ROP_ROP_FG_Type U08 + +/******************************************************************************* +** State gcregBlock8AlphaControl +*/ + +#define gcregBlock8AlphaControlRegAddrs 0x4AC0 +#define GCREG_BLOCK8_ALPHA_CONTROL_MSB 15 +#define GCREG_BLOCK8_ALPHA_CONTROL_LSB 3 +#define GCREG_BLOCK8_ALPHA_CONTROL_BLK 0 +#define GCREG_BLOCK8_ALPHA_CONTROL_Count 8 +#define GCREG_BLOCK8_ALPHA_CONTROL_FieldMask 0x00000001 +#define GCREG_BLOCK8_ALPHA_CONTROL_ReadMask 0x00000001 +#define GCREG_BLOCK8_ALPHA_CONTROL_WriteMask 0x00000001 +#define GCREG_BLOCK8_ALPHA_CONTROL_ResetValue 0x00000000 + +#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE 0 : 0 +#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_End 0 +#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_Start 0 +#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_Type U01 +#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_OFF 0x0 +#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_ON 0x1 + +/******************************************************************************* +** State gcregBlock8AlphaModes +*/ + +#define gcregBlock8AlphaModesRegAddrs 0x4AC8 +#define GCREG_BLOCK8_ALPHA_MODES_MSB 15 +#define GCREG_BLOCK8_ALPHA_MODES_LSB 3 +#define GCREG_BLOCK8_ALPHA_MODES_BLK 0 +#define GCREG_BLOCK8_ALPHA_MODES_Count 8 +#define GCREG_BLOCK8_ALPHA_MODES_FieldMask 0xFF003311 +#define GCREG_BLOCK8_ALPHA_MODES_ReadMask 0xFF003311 +#define GCREG_BLOCK8_ALPHA_MODES_WriteMask 0xFF003311 +#define GCREG_BLOCK8_ALPHA_MODES_ResetValue 0x00000000 + +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE 0 : 0 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_End 0 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_Start 0 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_Type U01 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED 0x1 + +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE 4 : 4 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_End 4 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_Start 4 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_Type U01 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_INVERSED 0x1 + +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE 9 : 8 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_End 9 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Start 8 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Type U02 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL 0x1 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED 0x2 + +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE 13 : 12 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_End 13 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Start 12 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Type U02 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL 0x1 +#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED 0x2 + +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE 26 : 24 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_End 26 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_Start 24 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_Type U03 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_ZERO 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_ONE 0x1 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_NORMAL 0x2 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_INVERSED 0x3 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_COLOR 0x4 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_COLOR_INVERSED 0x5 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_ALPHA 0x6 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_DEST_ALPHA 0x7 + +/* Src Blending factor is calculate from Src alpha. */ +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR 27 : 27 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_End 27 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_Start 27 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_Type U01 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLED 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLED 0x1 + +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE 30 : 28 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_End 30 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_Start 28 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_Type U03 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_ZERO 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_ONE 0x1 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_NORMAL 0x2 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_INVERSED 0x3 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_COLOR 0x4 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_COLOR_INVERSED 0x5 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_ALPHA 0x6 +#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_DEST_ALPHA 0x7 + +/* Dst Blending factor is calculate from Dst alpha. */ +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR 31 : 31 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_End 31 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_Start 31 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_Type U01 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLED 0x0 +#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLED 0x1 + +/******************************************************************************* +** State gcregBlock8AddressU +*/ + +/* 32-bit aligned base address of the source U plane. */ + +#define gcregBlock8AddressURegAddrs 0x4AD0 +#define GCREG_BLOCK8_ADDRESS_U_MSB 15 +#define GCREG_BLOCK8_ADDRESS_U_LSB 3 +#define GCREG_BLOCK8_ADDRESS_U_BLK 0 +#define GCREG_BLOCK8_ADDRESS_U_Count 8 +#define GCREG_BLOCK8_ADDRESS_U_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_ADDRESS_U_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK8_ADDRESS_U_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK8_ADDRESS_U_ResetValue 0x00000000 + +#define GCREG_BLOCK8_ADDRESS_U_ADDRESS 31 : 0 +#define GCREG_BLOCK8_ADDRESS_U_ADDRESS_End 30 +#define GCREG_BLOCK8_ADDRESS_U_ADDRESS_Start 0 +#define GCREG_BLOCK8_ADDRESS_U_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregBlock8StrideU +*/ + +/* Stride of the source U plane in bytes. */ + +#define gcregBlock8StrideURegAddrs 0x4AD8 +#define GCREG_BLOCK8_STRIDE_U_MSB 15 +#define GCREG_BLOCK8_STRIDE_U_LSB 3 +#define GCREG_BLOCK8_STRIDE_U_BLK 0 +#define GCREG_BLOCK8_STRIDE_U_Count 8 +#define GCREG_BLOCK8_STRIDE_U_FieldMask 0x0003FFFF +#define GCREG_BLOCK8_STRIDE_U_ReadMask 0x0003FFFC +#define GCREG_BLOCK8_STRIDE_U_WriteMask 0x0003FFFC +#define GCREG_BLOCK8_STRIDE_U_ResetValue 0x00000000 + +#define GCREG_BLOCK8_STRIDE_U_STRIDE 17 : 0 +#define GCREG_BLOCK8_STRIDE_U_STRIDE_End 17 +#define GCREG_BLOCK8_STRIDE_U_STRIDE_Start 0 +#define GCREG_BLOCK8_STRIDE_U_STRIDE_Type U18 + +/******************************************************************************* +** State gcregBlock8AddressV +*/ + +/* 32-bit aligned base address of the source V plane. */ + +#define gcregBlock8AddressVRegAddrs 0x4AE0 +#define GCREG_BLOCK8_ADDRESS_V_MSB 15 +#define GCREG_BLOCK8_ADDRESS_V_LSB 3 +#define GCREG_BLOCK8_ADDRESS_V_BLK 0 +#define GCREG_BLOCK8_ADDRESS_V_Count 8 +#define GCREG_BLOCK8_ADDRESS_V_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_ADDRESS_V_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK8_ADDRESS_V_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK8_ADDRESS_V_ResetValue 0x00000000 + +#define GCREG_BLOCK8_ADDRESS_V_ADDRESS 31 : 0 +#define GCREG_BLOCK8_ADDRESS_V_ADDRESS_End 30 +#define GCREG_BLOCK8_ADDRESS_V_ADDRESS_Start 0 +#define GCREG_BLOCK8_ADDRESS_V_ADDRESS_Type U31 + +/******************************************************************************* +** State gcregBlock8StrideV +*/ + +/* Stride of the source V plane in bytes. */ + +#define gcregBlock8StrideVRegAddrs 0x4AE8 +#define GCREG_BLOCK8_STRIDE_V_MSB 15 +#define GCREG_BLOCK8_STRIDE_V_LSB 3 +#define GCREG_BLOCK8_STRIDE_V_BLK 0 +#define GCREG_BLOCK8_STRIDE_V_Count 8 +#define GCREG_BLOCK8_STRIDE_V_FieldMask 0x0003FFFF +#define GCREG_BLOCK8_STRIDE_V_ReadMask 0x0003FFFC +#define GCREG_BLOCK8_STRIDE_V_WriteMask 0x0003FFFC +#define GCREG_BLOCK8_STRIDE_V_ResetValue 0x00000000 + +#define GCREG_BLOCK8_STRIDE_V_STRIDE 17 : 0 +#define GCREG_BLOCK8_STRIDE_V_STRIDE_End 17 +#define GCREG_BLOCK8_STRIDE_V_STRIDE_Start 0 +#define GCREG_BLOCK8_STRIDE_V_STRIDE_Type U18 + +/******************************************************************************* +** State gcregBlock8SrcRotationHeight +*/ + +/* 180/270 degree rotation configuration for the Source surface. Height field +** specifies the height of the surface in pixels. +*/ + +#define gcregBlock8SrcRotationHeightRegAddrs 0x4AF0 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_MSB 15 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_LSB 3 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_BLK 0 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_Count 8 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_FieldMask 0x0000FFFF +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_ReadMask 0x0000FFFF +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_WriteMask 0x0000FFFF +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT 15 : 0 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT_End 15 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT_Start 0 +#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT_Type U16 + +/******************************************************************************* +** State gcregBlock8RotAngle +*/ + +/* 0/90/180/270 degree rotation configuration for the Source surface. Height +** field specifies the height of the surface in pixels. +*/ + +#define gcregBlock8RotAngleRegAddrs 0x4AF8 +#define GCREG_BLOCK8_ROT_ANGLE_MSB 15 +#define GCREG_BLOCK8_ROT_ANGLE_LSB 3 +#define GCREG_BLOCK8_ROT_ANGLE_BLK 0 +#define GCREG_BLOCK8_ROT_ANGLE_Count 8 +#define GCREG_BLOCK8_ROT_ANGLE_FieldMask 0x000BB33F +#define GCREG_BLOCK8_ROT_ANGLE_ReadMask 0x000BB33F +#define GCREG_BLOCK8_ROT_ANGLE_WriteMask 0x000BB33F +#define GCREG_BLOCK8_ROT_ANGLE_ResetValue 0x00000000 + +#define GCREG_BLOCK8_ROT_ANGLE_SRC 2 : 0 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_End 2 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_Start 0 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_Type U03 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_ROT0 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_FLIP_X 0x1 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_FLIP_Y 0x2 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_ROT90 0x4 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_ROT180 0x5 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_ROT270 0x6 + +#define GCREG_BLOCK8_ROT_ANGLE_DST 5 : 3 +#define GCREG_BLOCK8_ROT_ANGLE_DST_End 5 +#define GCREG_BLOCK8_ROT_ANGLE_DST_Start 3 +#define GCREG_BLOCK8_ROT_ANGLE_DST_Type U03 +#define GCREG_BLOCK8_ROT_ANGLE_DST_ROT0 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_DST_FLIP_X 0x1 +#define GCREG_BLOCK8_ROT_ANGLE_DST_FLIP_Y 0x2 +#define GCREG_BLOCK8_ROT_ANGLE_DST_ROT90 0x4 +#define GCREG_BLOCK8_ROT_ANGLE_DST_ROT180 0x5 +#define GCREG_BLOCK8_ROT_ANGLE_DST_ROT270 0x6 + +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC 8 : 8 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_End 8 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_Start 8 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_Type U01 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_ENABLED 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MASKED 0x1 + +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST 9 : 9 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_End 9 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_Start 9 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_Type U01 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_ENABLED 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MASKED 0x1 + +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR 13 : 12 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_End 13 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_Start 12 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_Type U02 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_NONE 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_MIRROR_X 0x1 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_MIRROR_Y 0x2 +#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_MIRROR_XY 0x3 + +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR 15 : 15 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_End 15 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_Start 15 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_Type U01 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_ENABLED 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_MASKED 0x1 + +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR 17 : 16 +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_End 17 +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_Start 16 +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_Type U02 +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_NONE 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_MIRROR_X 0x1 +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_MIRROR_Y 0x2 +#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_MIRROR_XY 0x3 + +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR 19 : 19 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_End 19 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_Start 19 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_Type U01 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_ENABLED 0x0 +#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_MASKED 0x1 + +/******************************************************************************* +** State gcregBlock8GlobalSrcColor +*/ + +/* Defines the global source color and alpha values. */ + +#define gcregBlock8GlobalSrcColorRegAddrs 0x4B00 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_MSB 15 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_LSB 3 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLK 0 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_Count 8 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ResetValue 0x00000000 + +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA 31 : 24 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA_End 31 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA_Start 24 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA_Type U08 + +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED 23 : 16 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED_End 23 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED_Start 16 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED_Type U08 + +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN 15 : 8 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN_End 15 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN_Start 8 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN_Type U08 + +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE 7 : 0 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE_End 7 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE_Start 0 +#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock8GlobalDestColor +*/ + +/* Defines the global destination color and alpha values. */ + +#define gcregBlock8GlobalDestColorRegAddrs 0x4B08 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_MSB 15 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_LSB 3 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLK 0 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_Count 8 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ResetValue 0x00000000 + +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA 31 : 24 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA_End 31 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA_Start 24 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA_Type U08 + +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED 23 : 16 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED_End 23 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED_Start 16 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED_Type U08 + +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN 15 : 8 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN_End 15 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN_Start 8 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN_Type U08 + +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE 7 : 0 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE_End 7 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE_Start 0 +#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock8ColorMultiplyModes +*/ + +/* Color modes to multiply Source or Destination pixel color by alpha +** channel. Alpha can be from global color source or current pixel. +*/ + +#define gcregBlock8ColorMultiplyModesRegAddrs 0x4B10 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_MSB 15 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_LSB 3 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_BLK 0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_Count 8 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_FieldMask 0x00100311 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_ReadMask 0x00100311 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_WriteMask 0x00100311 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_ResetValue 0x00000000 + +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY 0 : 0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_End 0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Start 0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Type U01 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE 0x1 + +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY 4 : 4 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_End 4 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Start 4 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Type U01 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE 0x1 + +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY 9 : 8 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_End 9 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Start 8 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Type U02 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA 0x1 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR 0x2 + +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY 20 : 20 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_End 20 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Start 20 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Type U01 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE 0x0 +#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE 0x1 + +/******************************************************************************* +** State gcregBlock8Transparency +*/ + +#define gcregBlock8TransparencyRegAddrs 0x4B18 +#define GCREG_BLOCK8_TRANSPARENCY_MSB 15 +#define GCREG_BLOCK8_TRANSPARENCY_LSB 3 +#define GCREG_BLOCK8_TRANSPARENCY_BLK 0 +#define GCREG_BLOCK8_TRANSPARENCY_Count 8 +#define GCREG_BLOCK8_TRANSPARENCY_FieldMask 0xB3331333 +#define GCREG_BLOCK8_TRANSPARENCY_ReadMask 0xB3331333 +#define GCREG_BLOCK8_TRANSPARENCY_WriteMask 0xB3331333 +#define GCREG_BLOCK8_TRANSPARENCY_ResetValue 0x00000000 + +/* Source transparency mode. */ +#define GCREG_BLOCK8_TRANSPARENCY_SOURCE 1 : 0 +#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_End 1 +#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_Start 0 +#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_Type U02 +#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_OPAQUE 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_MASK 0x1 +#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_KEY 0x2 + +/* Pattern transparency mode. KEY transparency mode is reserved. */ +#define GCREG_BLOCK8_TRANSPARENCY_PATTERN 5 : 4 +#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_End 5 +#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_Start 4 +#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_Type U02 +#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_OPAQUE 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_MASK 0x1 +#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_KEY 0x2 + +/* Destination transparency mode. MASK transparency mode is reserved. */ +#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION 9 : 8 +#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_End 9 +#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_Start 8 +#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_Type U02 +#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_OPAQUE 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_MASK 0x1 +#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_KEY 0x2 + +/* Mask field for Source/Pattern/Destination fields. */ +#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY 12 : 12 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_End 12 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_Start 12 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_Type U01 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_ENABLED 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_MASKED 0x1 + +/* Source usage override. */ +#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE 17 : 16 +#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_End 17 +#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_Start 16 +#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_Type U02 +#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE 0x2 + +/* Pattern usage override. */ +#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE 21 : 20 +#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_End 21 +#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_Start 20 +#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_Type U02 +#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE 0x2 + +/* Destination usage override. */ +#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE 25 : 24 +#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_End 25 +#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_Start 24 +#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_Type U02 +#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE 0x2 + +/* 2D resource usage override mask field. */ +#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE 28 : 28 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_End 28 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Start 28 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Type U01 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_ENABLED 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_MASKED 0x1 + +/* DFB Color Key. */ +#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY 29 : 29 +#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_End 29 +#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_Start 29 +#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_Type U01 +#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_DISABLED 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_ENABLED 0x1 + +#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY 31 : 31 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_End 31 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_Start 31 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_Type U01 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_ENABLED 0x0 +#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_MASKED 0x1 + +/******************************************************************************* +** State gcregBlock8Control +*/ + +/* General purpose control register. */ + +#define gcregBlock8ControlRegAddrs 0x4B20 +#define GCREG_BLOCK8_CONTROL_MSB 15 +#define GCREG_BLOCK8_CONTROL_LSB 3 +#define GCREG_BLOCK8_CONTROL_BLK 0 +#define GCREG_BLOCK8_CONTROL_Count 8 +#define GCREG_BLOCK8_CONTROL_FieldMask 0x00000999 +#define GCREG_BLOCK8_CONTROL_ReadMask 0x00000999 +#define GCREG_BLOCK8_CONTROL_WriteMask 0x00000999 +#define GCREG_BLOCK8_CONTROL_ResetValue 0x00000000 + +#define GCREG_BLOCK8_CONTROL_YUV 0 : 0 +#define GCREG_BLOCK8_CONTROL_YUV_End 0 +#define GCREG_BLOCK8_CONTROL_YUV_Start 0 +#define GCREG_BLOCK8_CONTROL_YUV_Type U01 +#define GCREG_BLOCK8_CONTROL_YUV_601 0x0 +#define GCREG_BLOCK8_CONTROL_YUV_709 0x1 + +#define GCREG_BLOCK8_CONTROL_MASK_YUV 3 : 3 +#define GCREG_BLOCK8_CONTROL_MASK_YUV_End 3 +#define GCREG_BLOCK8_CONTROL_MASK_YUV_Start 3 +#define GCREG_BLOCK8_CONTROL_MASK_YUV_Type U01 +#define GCREG_BLOCK8_CONTROL_MASK_YUV_ENABLED 0x0 +#define GCREG_BLOCK8_CONTROL_MASK_YUV_MASKED 0x1 + +#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE 4 : 4 +#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_End 4 +#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_Start 4 +#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_Type U01 +#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_UV 0x0 +#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_VU 0x1 + +#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE 7 : 7 +#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_End 7 +#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_Start 7 +#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_Type U01 +#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_ENABLED 0x0 +#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_MASKED 0x1 + +/* YUV to RGB convert enable */ +#define GCREG_BLOCK8_CONTROL_YUVRGB 8 : 8 +#define GCREG_BLOCK8_CONTROL_YUVRGB_End 8 +#define GCREG_BLOCK8_CONTROL_YUVRGB_Start 8 +#define GCREG_BLOCK8_CONTROL_YUVRGB_Type U01 +#define GCREG_BLOCK8_CONTROL_YUVRGB_DISABLED 0x0 +#define GCREG_BLOCK8_CONTROL_YUVRGB_ENABLED 0x1 + +#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB 11 : 11 +#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_End 11 +#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_Start 11 +#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_Type U01 +#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_ENABLED 0x0 +#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_MASKED 0x1 + +/******************************************************************************* +** State gcregBlock8SrcColorKeyHigh +*/ + +/* Defines the source transparency color in source format. */ + +#define gcregBlock8SrcColorKeyHighRegAddrs 0x4B28 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_MSB 15 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_LSB 3 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLK 0 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_Count 8 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ReadMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_WriteMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA 31 : 24 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA_End 31 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA_Start 24 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA_Type U08 + +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED 23 : 16 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED_End 23 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED_Start 16 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED_Type U08 + +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN 15 : 8 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN_End 15 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN_Start 8 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN_Type U08 + +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE 7 : 0 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE_End 7 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE_Start 0 +#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE_Type U08 + +/******************************************************************************* +** State gcregBlock8SrcExConfig +*/ + +#define gcregBlock8SrcExConfigRegAddrs 0x4B30 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MSB 15 +#define GCREG_BLOCK8_SRC_EX_CONFIG_LSB 3 +#define GCREG_BLOCK8_SRC_EX_CONFIG_BLK 0 +#define GCREG_BLOCK8_SRC_EX_CONFIG_Count 8 +#define GCREG_BLOCK8_SRC_EX_CONFIG_FieldMask 0x00000109 +#define GCREG_BLOCK8_SRC_EX_CONFIG_ReadMask 0x00000109 +#define GCREG_BLOCK8_SRC_EX_CONFIG_WriteMask 0x00000109 +#define GCREG_BLOCK8_SRC_EX_CONFIG_ResetValue 0x00000000 + +/* Source multi tiled address computation control. */ +#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED 0 : 0 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_End 0 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_Start 0 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_Type U01 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_DISABLED 0x0 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_ENABLED 0x1 + +/* Source super tiled address computation control. */ +#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED 3 : 3 +#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_End 3 +#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_Start 3 +#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_Type U01 +#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_DISABLED 0x0 +#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_ENABLED 0x1 + +/* Source super tiled address computation control. */ +#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED 8 : 8 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_End 8 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_Start 8 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_Type U01 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_DISABLED 0x0 +#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_ENABLED 0x1 + +/******************************************************************************* +** State gcregBlock8SrcExAddress +*/ + +/* 32-bit aligned base address of the source extra surface. */ + +#define gcregBlock8SrcExAddressRegAddrs 0x4B38 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_MSB 15 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_LSB 3 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_BLK 0 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_Count 8 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_FieldMask 0xFFFFFFFF +#define GCREG_BLOCK8_SRC_EX_ADDRESS_ReadMask 0xFFFFFFFC +#define GCREG_BLOCK8_SRC_EX_ADDRESS_WriteMask 0xFFFFFFFC +#define GCREG_BLOCK8_SRC_EX_ADDRESS_ResetValue 0x00000000 + +#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS 31 : 0 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS_End 30 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS_Start 0 +#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS_Type U31 + +/******************************************************************************* +** Generic defines +*/ + +#define GCREG_FORMAT_SUB_SAMPLE_MODE_YUV_MODE422 0x0 +#define GCREG_FORMAT_SUB_SAMPLE_MODE_YUV_MODE420 0x1 + +#define GCREG_DE_SWIZZLE_ARGB 0x0 +#define GCREG_DE_SWIZZLE_RGBA 0x1 +#define GCREG_DE_SWIZZLE_ABGR 0x2 +#define GCREG_DE_SWIZZLE_BGRA 0x3 + +#define GCREG_DE_FORMAT_X4R4G4B4 0x00 +#define GCREG_DE_FORMAT_A4R4G4B4 0x01 +#define GCREG_DE_FORMAT_X1R5G5B5 0x02 +#define GCREG_DE_FORMAT_A1R5G5B5 0x03 +#define GCREG_DE_FORMAT_R5G6B5 0x04 +#define GCREG_DE_FORMAT_X8R8G8B8 0x05 +#define GCREG_DE_FORMAT_A8R8G8B8 0x06 +#define GCREG_DE_FORMAT_YUY2 0x07 +#define GCREG_DE_FORMAT_UYVY 0x08 +#define GCREG_DE_FORMAT_INDEX8 0x09 +#define GCREG_DE_FORMAT_MONOCHROME 0x0A +#define GCREG_DE_FORMAT_YV12 0x0F +#define GCREG_DE_FORMAT_A8 0x10 +#define GCREG_DE_FORMAT_NV12 0x11 +#define GCREG_DE_FORMAT_NV16 0x12 +#define GCREG_DE_FORMAT_RG16 0x13 + +/* ~~~~~~~~~~~~~ */ + +#define GCREG_ALPHA_MODE_NORMAL 0x0 +#define GCREG_ALPHA_MODE_INVERSED 0x1 + +#define GCREG_GLOBAL_ALPHA_MODE_NORMAL 0x0 +#define GCREG_GLOBAL_ALPHA_MODE_GLOBAL 0x1 +#define GCREG_GLOBAL_ALPHA_MODE_SCALED 0x2 + +#define GCREG_COLOR_MODE_NORMAL 0x0 +#define GCREG_COLOR_MODE_MULTIPLY 0x1 + +#define GCREG_BLENDING_MODE_ZERO 0x0 +#define GCREG_BLENDING_MODE_ONE 0x1 +#define GCREG_BLENDING_MODE_NORMAL 0x2 +#define GCREG_BLENDING_MODE_INVERSED 0x3 +#define GCREG_BLENDING_MODE_COLOR 0x4 +#define GCREG_BLENDING_MODE_COLOR_INVERSED 0x5 +#define GCREG_BLENDING_MODE_SATURATED_ALPHA 0x6 +#define GCREG_BLENDING_MODE_SATURATED_DEST_ALPHA 0x7 + +/* ~~~~~~~~~~~~~ */ + +#define GCREG_FACTOR_INVERSE_DISABLE 0x0 +#define GCREG_FACTOR_INVERSE_ENABLE 0x1 + +/* ~~~~~~~~~~~~~ */ + +#define GCREG_RESOURCE_USAGE_OVERRIDE_DEFAULT 0x0 +#define GCREG_RESOURCE_USAGE_OVERRIDE_USE_ENABLE 0x1 +#define GCREG_RESOURCE_USAGE_OVERRIDE_USE_DISABLE 0x2 + +/******************************************************************************* +** Modular operations: pipesel +*/ + +static const struct gccmdldstate gcmopipesel_pipesel_ldst = + GCLDSTATE(gcregPipeSelectRegAddrs, 1); + +struct gcmopipesel { + /* gcregPipeSelectRegAddrs */ + struct gccmdldstate pipesel_ldst; + + /* gcregPipeSelectRegAddrs */ + union { + struct gcregpipeselect reg; + unsigned int raw; + } pipesel; +}; + +/******************************************************************************* +** Modular operations: signal +*/ + +static const struct gccmdldstate gcmosignal_signal_ldst = + GCLDSTATE(gcregEventRegAddrs, 1); + +struct gcmosignal { + /* gcregEventRegAddrs */ + struct gccmdldstate signal_ldst; + + /* gcregEventRegAddrs */ + union { + struct gcregevent reg; + unsigned int raw; + } signal; +}; + +/******************************************************************************* +** Modular operations: flush +*/ + +static const struct gccmdldstate gcmoflush_flush_ldst = + GCLDSTATE(gcregFlushRegAddrs, 1); + +struct gcmoflush { + /* gcregFlushRegAddrs */ + struct gccmdldstate flush_ldst; + + /* gcregFlushRegAddrs */ + union { + struct gcregflush reg; + unsigned int raw; + } flush; +}; + +/******************************************************************************* +** Modular operations: semaphore +*/ + +static const struct gccmdldstate gcmosema_sema_ldst = + GCLDSTATE(gcregSemaphoreRegAddrs, 1); + +struct gcmosema { + /* gcregSemaphoreRegAddrs */ + struct gccmdldstate sema_ldst; + + /* gcregSemaphoreRegAddrs */ + union { + struct gcregsemaphore reg; + unsigned int raw; + } sema; +}; + +/******************************************************************************* +** Modular operations: mmuinit +*/ + +struct gcmoterminator { + union { + struct gcmosignal done; + struct gccmdnop nop; + } u1; + + union { + struct gccmdwait wait; + struct gccmdlink linknext; + struct gccmdend end; + } u2; + + union { + struct gccmdlink linkwait; + struct gccmdnop nop; + } u3; +}; + +/******************************************************************************* +** Modular operations: mmuinit +*/ + +static const struct gccmdldstate gcmommuinit_safe_ldst = + GCLDSTATE(gcregMMUSafeAddressRegAddrs, 2); + +struct gcmommuinit { + /* gcregMMUSafeAddressRegAddrs */ + struct gccmdldstate safe_ldst; + + /* gcregMMUSafeAddressRegAddrs */ + unsigned int safe; + + /* gcregMMUConfigurationRegAddrs */ + unsigned int mtlb; + + /* Alignment filler. */ + unsigned int _filler; +}; + +/******************************************************************************* +** Modular operations: mmumaster +*/ + +static const struct gccmdldstate gcmommumaster_master_ldst = + GCLDSTATE(gcregMMUConfigurationRegAddrs, 1); + +struct gcmommumaster { + /* gcregMMUConfigurationRegAddrs */ + struct gccmdldstate master_ldst; + + /* gcregMMUConfigurationRegAddrs */ + unsigned int master; +}; + +/******************************************************************************* +** Modular operations: mmuflush +*/ + +static const struct gccmdldstate gcmommuflush_mmuflush_ldst = + GCLDSTATE(gcregMMUConfigurationRegAddrs, 1); + +struct gcmommuflush { + /* PE cache flush. */ + struct gcmoflush peflush; + + /* Semaphore/stall after PE flush. */ + struct gcmosema peflushsema; + struct gccmdstall peflushstall; + + /* Link to flush FE FIFO. */ + struct gccmdlink feflush; + + /* MMU flush. */ + struct gccmdldstate mmuflush_ldst; + + /* gcregMMUConfigurationRegAddrs */ + union { + struct gcregmmuconfiguration reg; + unsigned int raw; + } mmuflush; + + /* Semaphore/stall after MMU flush. */ + struct gcmosema mmuflushsema; + struct gccmdstall mmuflushstall; + + /* Link to the user buffer. */ + struct gccmdlink link; +}; + +/******************************************************************************* +** Modular operations: clip +*/ + +static const struct gccmdldstate gcmoclip_lt_ldst = + GCLDSTATE(gcregClipTopLeftRegAddrs, 2); + +struct gcmoclip { + /* gcregClipTopLeftRegAddrs */ + struct gccmdldstate lt_ldst; + + /* gcregClipTopLeftRegAddrs */ + union { + struct gcregcliplt reg; + unsigned int raw; + } lt; + + /* gcregClipBottomRight */ + union { + struct gcregcliprb reg; + unsigned int raw; + } rb; + + /* Alignment filler. */ + unsigned int _filler; +}; + +/******************************************************************************* +** Modular operations: dst +*/ + +static const struct gccmdldstate gcmodst_address_ldst = + GCLDSTATE(gcregDestAddressRegAddrs, 3); + +static const struct gccmdldstate gcmodst_rotationheight_ldst = + GCLDSTATE(gcregDstRotationHeightRegAddrs, 1); + +struct gcmodst { + /* gcregDestAddressRegAddrs */ + struct gccmdldstate address_ldst; + + /* gcregDestAddressRegAddrs */ + unsigned int address; + + /* gcregDestStrideRegAddrs */ + unsigned int stride; + + /* gcregDestRotationConfigRegAddrs */ + union { + struct gcregdstrotationconfig reg; + unsigned int raw; + } rotation; + + /* gcregDstRotationHeightRegAddrs */ + struct gccmdldstate rotationheight_ldst; + + /* gcregDstRotationHeightRegAddrs */ + union { + struct gcregdstrotationheight reg; + unsigned int raw; + } rotationheight; +}; + +/******************************************************************************* +** Modular operations: src +*/ + +static const struct gccmdldstate gcmosrc_address_ldst[4] = { + GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_stride_ldst[4] = { + GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_uplaneaddress_ldst[4] = { + GCLDSTATE(gcregUPlaneAddressRegAddrs + 0, 1), + GCLDSTATE(gcregUPlaneAddressRegAddrs + 1, 1), + GCLDSTATE(gcregUPlaneAddressRegAddrs + 2, 1), + GCLDSTATE(gcregUPlaneAddressRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_uplanestride_ldst[4] = { + GCLDSTATE(gcregUPlaneStrideRegAddrs + 0, 1), + GCLDSTATE(gcregUPlaneStrideRegAddrs + 1, 1), + GCLDSTATE(gcregUPlaneStrideRegAddrs + 2, 1), + GCLDSTATE(gcregUPlaneStrideRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_vplaneaddress_ldst[4] = { + GCLDSTATE(gcregVPlaneAddressRegAddrs + 0, 1), + GCLDSTATE(gcregVPlaneAddressRegAddrs + 1, 1), + GCLDSTATE(gcregVPlaneAddressRegAddrs + 2, 1), + GCLDSTATE(gcregVPlaneAddressRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_vplanestride_ldst[4] = { + GCLDSTATE(gcregVPlaneStrideRegAddrs + 0, 1), + GCLDSTATE(gcregVPlaneStrideRegAddrs + 1, 1), + GCLDSTATE(gcregVPlaneStrideRegAddrs + 2, 1), + GCLDSTATE(gcregVPlaneStrideRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_rotation_ldst[4] = { + GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_config_ldst[4] = { + GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_origin_ldst[4] = { + GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_size_ldst[4] = { + GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_rotationheight_ldst[4] = { + GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_rop_ldst[4] = { + GCLDSTATE(gcregBlock4RopRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4RopRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4RopRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4RopRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_mult_ldst[4] = { + GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrc_alphacontrol_ldst[4] = { + GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrcalpha_alphamodes_ldst[4] = { + GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrcalpha_srcglobal_ldst[4] = { + GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 3, 1), +}; + +static const struct gccmdldstate gcmosrcalpha_dstglobal_ldst[4] = { + GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 0, 1), + GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 1, 1), + GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 2, 1), + GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 3, 1), +}; + +struct gcmosrc { + /* gcregBlock4SrcAddressRegAddrs */ + struct gccmdldstate address_ldst; + + /* gcregBlock4SrcAddressRegAddrs */ + unsigned int address; + + /* gcregBlock4SrcStrideRegAddrs */ + struct gccmdldstate stride_ldst; + + /* gcregBlock4SrcStrideRegAddrs */ + unsigned int stride; + + /* gcregBlock4SrcRotationConfigRegAddrs */ + struct gccmdldstate rotation_ldst; + + /* gcregBlock4SrcRotationConfigRegAddrs */ + union { + struct gcregsrcrotationconfig reg; + unsigned int raw; + } rotation; + + /* gcregBlock4SrcConfigRegAddrs */ + struct gccmdldstate config_ldst; + + /* gcregBlock4SrcConfigRegAddrs */ + union { + struct gcregsrcconfig reg; + unsigned int raw; + } config; + + /* gcregBlock4SrcOriginRegAddrs */ + struct gccmdldstate origin_ldst; + + /* gcregBlock4SrcOriginRegAddrs */ + union { + struct gcregsrcorigin reg; + unsigned int raw; + } origin; + + /* gcregBlock4SrcSizeRegAddrs */ + struct gccmdldstate size_ldst; + + /* gcregBlock4SrcSizeRegAddrs */ + union { + struct gcregsrcsize reg; + unsigned int raw; + } size; + + /* gcregBlock4SrcRotationHeightRegAddrs */ + struct gccmdldstate rotationheight_ldst; + + /* gcregBlock4SrcRotationHeightRegAddrs */ + union { + struct gcregsrcrotationheight reg; + unsigned int raw; + } rotationheight; + + /* gcregBlock4RopRegAddrs */ + struct gccmdldstate rop_ldst; + + /* gcregBlock4RopRegAddrs */ + union { + struct gcregrop reg; + unsigned int raw; + } rop; + + /* gcregBlock4ColorMultiplyModesRegAddrs */ + struct gccmdldstate mult_ldst; + + /* gcregBlock4ColorMultiplyModesRegAddrs */ + union { + struct gcregcolormultiplymodes reg; + unsigned int raw; + } mult; + + /* gcregBlock4AlphaControlRegAddrs */ + struct gccmdldstate alphacontrol_ldst; + + /* gcregBlock4AlphaControlRegAddrs */ + union { + struct gcregalphacontrol reg; + unsigned int raw; + } alphacontrol; +}; + +struct gcmosrcplanaryuv { + /* gcregUPlaneAddressRegAddrs */ + struct gccmdldstate uplaneaddress_ldst; + unsigned int uplaneaddress; + + /* gcregUPlaneStrideRegAddrs */ + struct gccmdldstate uplanestride_ldst; + unsigned int uplanestride; + + /* gcregVPlaneAddressRegAddrs */ + struct gccmdldstate vplaneaddress_ldst; + unsigned int vplaneaddress; + + /* gcregVPlaneStrideRegAddrs */ + struct gccmdldstate vplanestride_ldst; + unsigned int vplanestride; +}; + +struct gcmosrcalpha { + /* gcregBlock4AlphaModesRegAddrs */ + struct gccmdldstate alphamodes_ldst; + + /* gcregBlock4AlphaModesRegAddrs */ + union { + struct gcregalphamodes reg; + unsigned int raw; + } alphamodes; + + /* gcregBlock4GlobalSrcColorRegAddrs */ + struct gccmdldstate srcglobal_ldst; + + /* gcregBlock4GlobalSrcColorRegAddrs */ + union { + struct gcregglobalsrccolor reg; + unsigned int raw; + } srcglobal; + + /* gcregBlock4GlobalDestColorRegAddrs */ + struct gccmdldstate dstglobal_ldst; + + /* gcregBlock4GlobalDestColorRegAddrs */ + union { + struct gcregglobaldstcolor reg; + unsigned int raw; + } dstglobal; +}; + +/******************************************************************************* +** Modular operations: multisrc +*/ + +static const struct gccmdldstate gcmomultisrc_control_ldst = + GCLDSTATE(gcregDEMultiSourceRegAddrs, 1); + +struct gcmomultisrc { + /* gcregDEMultiSourceRegAddrs */ + struct gccmdldstate control_ldst; + + /* gcregDEMultiSourceRegAddrs */ + union { + struct gcregmultisource reg; + unsigned int raw; + } control; +}; + +/******************************************************************************* +** Modular operations: startde +*/ + +static const struct gccmdldstate gcmostart_config_ldst = + GCLDSTATE(gcregDestConfigRegAddrs, 1); + +static const struct gccmdldstate gcmostart_rop_ldst = + GCLDSTATE(gcregRopRegAddrs, 1); + +struct gcmostart { + /* gcregDestConfigRegAddrs */ + struct gccmdldstate config_ldst; + + /* gcregDestConfigRegAddrs */ + union { + struct gcregdstconfig reg; + unsigned int raw; + } config; + + /* gcregRopRegAddrs */ + struct gccmdldstate rop_ldst; + + /* gcregRopRegAddrs */ + union { + struct gcregrop reg; + unsigned int raw; + } rop; + + /* Start DE command. */ + struct gccmdstartde startde; + struct gccmdstartderect rect; +}; + +/******************************************************************************* +** Modular operations: fillsrc +*/ + +static const struct gccmdldstate gcmofillsrc_rotation_ldst = + GCLDSTATE(gcregSrcRotationConfigRegAddrs, 2); + +static const struct gccmdldstate gcmofillsrc_rotationheight_ldst = + GCLDSTATE(gcregSrcRotationHeightRegAddrs, 1); + +static const struct gccmdldstate gcmofillsrc_alphacontrol_ldst = + GCLDSTATE(gcregAlphaControlRegAddrs, 1); + +struct gcmofillsrc { + /* gcregSrcRotationConfigRegAddrs */ + struct gccmdldstate rotation_ldst; + + /* gcregSrcRotationConfigRegAddrs */ + union { + struct gcregsrcrotationconfig reg; + unsigned int raw; + } rotation; + + /* gcregSrcConfigRegAddrs */ + union { + struct gcregsrcconfig reg; + unsigned int raw; + } config; + + /* Alignment filler. */ + unsigned int _filler; + + /* gcregSrcRotationHeightRegAddrs */ + struct gccmdldstate rotationheight_ldst; + + /* gcregSrcRotationHeightRegAddrs */ + union { + struct gcregsrcrotationheight reg; + unsigned int raw; + } rotationheight; + + /* gcregAlphaControlRegAddrs */ + struct gccmdldstate alphacontrol_ldst; + + /* gcregAlphaControlRegAddrs */ + union { + struct gcregalphacontrol reg; + unsigned int raw; + } alphacontrol; +}; + +/******************************************************************************* +** Modular operations: fill +*/ + +static const struct gccmdldstate gcmofill_clearcolor_ldst = + GCLDSTATE(gcregClearPixelValue32RegAddrs, 1); + +struct gcmofill { + struct gcmofillsrc src; + + /* gcregClearPixelValue32RegAddrs */ + struct gccmdldstate clearcolor_ldst; + + /* gcregClearPixelValue32RegAddrs */ + union { + struct gcregclearcolor reg; + unsigned int raw; + } clearcolor; + + struct gcmostart start; +}; + +#endif diff --git a/gcbv/mirror/include/gcx.h b/gcbv/mirror/include/gcx.h new file mode 100644 index 0000000..431c3c5 --- /dev/null +++ b/gcbv/mirror/include/gcx.h @@ -0,0 +1,100 @@ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + * + * BSD LICENSE + * + * Copyright(c) 2012, + * Texas Instruments, Inc. and Vivante Corporation. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Vivante Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GCX_H +#define GCX_H + +#include <pthread.h> +#include "gcerror.h" +#include "gcreg.h" +#include "gcdbglog.h" + +#ifndef countof +#define countof(a) \ + (sizeof(a) / sizeof(a[0])) +#endif + +#define GCLOCK_TYPE \ + pthread_mutex_t + +#define GCDEFINE_LOCK(name) \ + pthread_mutex_t name = PTHREAD_MUTEX_INITIALIZER + +#define GCLOCK_INIT(lock) \ + if (pthread_mutex_init(lock, NULL)) { \ + GCERR("failed to init mutex.\n"); \ + } + +#define GCLOCK_DESTROY(lock) \ + if (pthread_mutex_destroy(lock)) { \ + GCERR("failed to destroy mutex.\n"); \ + } + +#define GCLOCK(lock) \ + if (pthread_mutex_lock(lock)) { \ + GCERR("failed to lock mutex.\n"); \ + } + +#define GCUNLOCK(lock) \ + if (pthread_mutex_unlock(lock)) { \ + GCERR("failed to unlock mutex.\n"); \ + } + +#endif |