From 9374529441688bd5e22ac60b7725c1485a33307c Mon Sep 17 00:00:00 2001 From: Gustavo Diaz Prado Date: Fri, 31 Aug 2012 15:11:37 -0500 Subject: hwc: Fix incorrect tiler memory available check When the buffers composed with DSS pipes use exactly the tiler1d memory available (like 4 fullscreen layers on Tablet 2), the prepare operation fails to assign a DSS pipe to the last buffer (even if it was possible) making it to be rendered by the GPU but without a pipe to show it. This patch fixes the incorrect memory check that caused this problem. Change-Id: Ibb147a468aa2e1622600a56f581013dc1e517777 Signed-off-by: Gustavo Diaz Prado Signed-off-by: Jonas Larsson --- hwc/hwc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hwc') diff --git a/hwc/hwc.c b/hwc/hwc.c index ceff987..c98cacc 100644 --- a/hwc/hwc.c +++ b/hwc/hwc.c @@ -1758,7 +1758,7 @@ static int omap4_hwc_prepare(struct hwc_composer_device *dev, hwc_layer_list_t* is_protected(layer) || is_upscaled_NV12(hwc_dev, layer) || (hwc_dev->ext.current.docking && hwc_dev->ext.current.enabled && dockable(layer))) && - mem_used + mem1d(handle) < limits.tiler1d_slot_size && + mem_used + mem1d(handle) <= limits.tiler1d_slot_size && /* can't have a transparent overlay in the middle of the framebuffer stack */ !(is_BLENDED(layer) && fb_z >= 0)) { -- cgit v1.1