diff options
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/drivers/dma/Kconfig | 17 | ||||
| -rw-r--r-- | arch/sh/drivers/dma/dma-sysfs.c | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/dma-sh.h | 16 | ||||
| -rw-r--r-- | arch/sh/include/asm/dma.h | 8 | ||||
| -rw-r--r-- | arch/sh/include/mach-dreamcast/mach/dma.h | 2 |
5 files changed, 9 insertions, 36 deletions
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig index 4d58eb0..cfd5b90 100644 --- a/arch/sh/drivers/dma/Kconfig +++ b/arch/sh/drivers/dma/Kconfig @@ -40,23 +40,6 @@ config NR_ONCHIP_DMA_CHANNELS DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. -config NR_DMA_CHANNELS_BOOL - depends on SH_DMA - bool "Override default number of maximum DMA channels" - help - This allows you to forcibly update the maximum number of supported - DMA channels for a given board. If this is unset, this will default - to the number of channels that the on-chip DMAC has. - -config NR_DMA_CHANNELS - int "Maximum number of DMA channels" - depends on SH_DMA && NR_DMA_CHANNELS_BOOL - default NR_ONCHIP_DMA_CHANNELS - help - This allows you to specify the maximum number of DMA channels to - support. Setting this to a higher value allows for cascading DMACs - with additional channels. - config SH_DMABRG bool "SH7760 DMABRG support" depends on CPU_SUBTYPE_SH7760 diff --git a/arch/sh/drivers/dma/dma-sysfs.c b/arch/sh/drivers/dma/dma-sysfs.c index 67ee956..4b15fed 100644 --- a/arch/sh/drivers/dma/dma-sysfs.c +++ b/arch/sh/drivers/dma/dma-sysfs.c @@ -29,7 +29,7 @@ static ssize_t dma_show_devices(struct device *dev, ssize_t len = 0; int i; - for (i = 0; i < MAX_DMA_CHANNELS; i++) { + for (i = 0; i < 16; i++) { struct dma_info *info = get_dma_info(i); struct dma_channel *channel = get_dma_channel(i); diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h index f3acb8e..9a4875a 100644 --- a/arch/sh/include/asm/dma-sh.h +++ b/arch/sh/include/asm/dma-sh.h @@ -32,21 +32,21 @@ #endif static int dmte_irq_map[] __maybe_unused = { -#if (MAX_DMA_CHANNELS >= 4) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) DMTE0_IRQ, DMTE0_IRQ + 1, DMTE0_IRQ + 2, DMTE0_IRQ + 3, #endif -#if (MAX_DMA_CHANNELS >= 6) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) DMTE4_IRQ, DMTE4_IRQ + 1, #endif -#if (MAX_DMA_CHANNELS >= 8) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) DMTE6_IRQ, DMTE6_IRQ + 1, #endif -#if (MAX_DMA_CHANNELS >= 12) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) DMTE8_IRQ, DMTE9_IRQ, DMTE10_IRQ, @@ -62,21 +62,21 @@ static int dmte_irq_map[] __maybe_unused = { /* DMA base address */ static u32 dma_base_addr[] __maybe_unused = { -#if (MAX_DMA_CHANNELS >= 4) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4) SH_DMAC_BASE0 + 0x00, /* channel 0 */ SH_DMAC_BASE0 + 0x10, SH_DMAC_BASE0 + 0x20, SH_DMAC_BASE0 + 0x30, #endif -#if (MAX_DMA_CHANNELS >= 6) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6) SH_DMAC_BASE0 + 0x50, SH_DMAC_BASE0 + 0x60, #endif -#if (MAX_DMA_CHANNELS >= 8) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8) SH_DMAC_BASE1 + 0x00, SH_DMAC_BASE1 + 0x10, #endif -#if (MAX_DMA_CHANNELS >= 12) +#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12) SH_DMAC_BASE1 + 0x20, SH_DMAC_BASE1 + 0x30, SH_DMAC_BASE1 + 0x50, diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h index e6c2871..fb6e4f7 100644 --- a/arch/sh/include/asm/dma.h +++ b/arch/sh/include/asm/dma.h @@ -17,14 +17,6 @@ #include <linux/device.h> #include <asm-generic/dma.h> -#ifdef CONFIG_NR_DMA_CHANNELS -# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) -#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS) -# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) -#else -# define MAX_DMA_CHANNELS 0 -#endif - /* * Read and write modes can mean drastically different things depending on the * channel configuration. Consult your DMAC documentation and module diff --git a/arch/sh/include/mach-dreamcast/mach/dma.h b/arch/sh/include/mach-dreamcast/mach/dma.h index ddd68e7..1dbfdf7 100644 --- a/arch/sh/include/mach-dreamcast/mach/dma.h +++ b/arch/sh/include/mach-dreamcast/mach/dma.h @@ -11,9 +11,7 @@ #define __ASM_SH_DREAMCAST_DMA_H /* Number of DMA channels */ -#define ONCHIP_NR_DMA_CHANNELS 4 #define G2_NR_DMA_CHANNELS 4 -#define PVR2_NR_DMA_CHANNELS 1 /* Channels for cascading */ #define PVR2_CASCADE_CHAN 2 |