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path: root/drivers/clk/clk-vt8500.c
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* clk: vt8500: Fix "fix device clock divisor calculations"Arnd Bergmann2013-03-141-1/+1
| | | | | | | | | | | | Patch 72480014b8 "Fix device clock divisor calculations" was apparently rebased incorrectly before it got upstream, causing a build error. Replacing the "prate" pointer with the local parent_rate is most likely the correct solution. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Mike Turquette <mturquette@linaro.org>
* clk: vt8500: Use common of_clk_init() functionPrashant Gaikwad2013-01-241-12/+5
| | | | | | | | | | | Use common of_clk_init() function for clock initialization. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added entry for wm8750-pll-clock] Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: vt8500: Add support for WM8750/WM8850 PLL clocksTony Prisk2013-01-151-2/+100
| | | | | | | | This patch adds support for the new PLL module found in WM8750 and WM8850 SoCs. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: vt8500: Fix division-by-0 when requested rate=0Tony Prisk2013-01-151-2/+12
| | | | | | | | A request to vt8500_dclk_(round_rate/set_rate) with rate=0 results in a division-by-0 in the kernel. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: vt8500: Fix device clock divisor calculationsTony Prisk2013-01-151-0/+8
| | | | | | | | | | | | | When calculating device clock divisor values in set_rate and round_rate, we do a simple integer divide. If parent_rate / rate has a fraction, this is dropped which results in the device clock being set too high. This patch corrects the problem by adding 1 to the calculated divisor if the division would have had a decimal result. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: vt8500: Fix error in PLL calculations on non-exact match.Tony Prisk2013-01-151-3/+3
| | | | | | | | When a PLL frequency calculation is performed and a non-exact match is found the wrong multiplier and divisors are returned. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* CLK: vt8500: Fix SDMMC clk special casesTony Prisk2012-11-091-0/+18
| | | | | | | | | This patch adds some additional handling for the SDMMC special case in round_rate and set_rate which results in invalid divisor messages at boot time. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* arm: vt8500: clk: Add Common Clock Framework supportTony Prisk2012-09-211-0/+510
This patch adds common clock framework support for arch-vt8500. Support for PLL and device clocks on VT8500, WM8505 and WM8650 are included. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
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