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* Merge tag 'for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pciLinus Torvalds2012-12-131-12/+36
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull PCI update from Bjorn Helgaas: "Host bridge hotplug: - Untangle _PRT from struct pci_bus (Bjorn Helgaas) - Request _OSC control before scanning root bus (Taku Izumi) - Assign resources when adding host bridge (Yinghai Lu) - Remove root bus when removing host bridge (Yinghai Lu) - Remove _PRT during hot remove (Yinghai Lu) SRIOV - Add sysfs knobs to control numVFs (Don Dutile) Power management - Notify devices when power resource turned on (Huang Ying) Bug fixes - Work around broken _SEG on HP xw9300 (Bjorn Helgaas) - Keep runtime PM enabled for unbound PCI devices (Huang Ying) - Fix Optimus dual-GPU runtime D3 suspend issue (Dave Airlie) - Fix xen frontend shutdown issue (David Vrabel) - Work around PLX PCI 9050 BAR alignment erratum (Ian Abbott) Miscellaneous - Add GPL license for drivers/pci/ioapic (Andrew Cooks) - Add standard PCI-X, PCIe ASPM register #defines (Bjorn Helgaas) - NumaChip remote PCI support (Daniel Blueman) - Fix PCIe Link Capabilities Supported Link Speed definition (Jingoo Han) - Convert dev_printk() to dev_info(), etc (Joe Perches) - Add support for non PCI BAR ROM data (Matthew Garrett) - Add x86 support for host bridge translation offset (Mike Yoknis) - Report success only when every driver supports AER (Vijay Pandarathil)" Fix up trivial conflicts. * tag 'for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (48 commits) PCI: Use phys_addr_t for physical ROM address x86/PCI: Add NumaChip remote PCI support ath9k: Use standard #defines for PCIe Capability ASPM fields iwlwifi: Use standard #defines for PCIe Capability ASPM fields iwlwifi: collapse wrapper for pcie_capability_read_word() iwlegacy: Use standard #defines for PCIe Capability ASPM fields iwlegacy: collapse wrapper for pcie_capability_read_word() cxgb3: Use standard #defines for PCIe Capability ASPM fields PCI: Add standard PCIe Capability Link ASPM field names PCI/portdrv: Use PCI Express Capability accessors PCI: Use standard PCIe Capability Link register field names x86: Use PCI setup data PCI: Add support for non-BAR ROMs PCI: Add pcibios_add_device EFI: Stash ROMs if they're not in the PCI BAR PCI: Add and use standard PCI-X Capability register names PCI/PM: Keep runtime PM enabled for unbound PCI devices xen-pcifront: Handle backend CLOSED without CLOSING PCI: SRIOV control and status via sysfs (documentation) PCI/AER: Report success only when every device has AER-aware driver ...
| * Merge branch 'pci/mjg-pci-roms-from-efi' into nextBjorn Helgaas2012-12-061-0/+13
| |\ | | | | | | | | | | | | | | | | | | | | | * pci/mjg-pci-roms-from-efi: x86: Use PCI setup data PCI: Add support for non-BAR ROMs PCI: Add pcibios_add_device EFI: Stash ROMs if they're not in the PCI BAR
| | * PCI: Add pcibios_add_deviceMatthew Garrett2012-12-051-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms may want to provide architecture-specific functionality during PCI enumeration. Add a pcibios_add_device() call that architectures can override to do so. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Seth Forshee <seth.forshee@canonical.com>
| * | Merge branch 'pci/huang-d3cold-fixes' into nextBjorn Helgaas2012-12-041-0/+2
| |\ \ | | | | | | | | | | | | | | | | * pci/huang-d3cold-fixes: PCI/PM: Keep runtime PM enabled for unbound PCI devices
| | * | PCI/PM: Keep runtime PM enabled for unbound PCI devicesHuang Ying2012-12-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For unbound PCI devices, what we need is: - Always in D0 state, because some devices do not work again after being put into D3 by the PCI bus. - In SUSPENDED state if allowed, so that the parent devices can still be put into low power state. To satisfy these requirements, the runtime PM for the unbound PCI devices are disabled and set to SUSPENDED state. One issue of this solution is that the PCI devices will be put into SUSPENDED state even if the SUSPENDED state is forbidden via the sysfs interface (.../power/control) of the device. This is not an issue for most devices, because most PCI devices are not used at all if unbound. But there are exceptions. For example, unbound VGA card can be used for display, but suspending its parents makes it stop working. To fix the issue, we keep the runtime PM enabled when the PCI devices are unbound. But the runtime PM callbacks will do nothing if the PCI devices are unbound. This way, we can put the PCI devices into SUSPENDED state without putting the PCI devices into D3 state. Reference: https://bugzilla.kernel.org/show_bug.cgi?id=48201 Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> CC: stable@vger.kernel.org # v3.6+
| * | | Merge branch 'for-linus' into nextBjorn Helgaas2012-11-261-0/+32
| |\ \ \ | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | * for-linus: PCI/portdrv: Don't create hotplug slots unless port supports hotplug PCI/PM: Fix proc config reg access for D3cold and bridge suspending PCI/PM: Resume device before shutdown PCI/PM: Fix deadlock when unbinding device if parent in D3cold
| * | | Merge branch 'pci/taku-prt-cleanup' into nextBjorn Helgaas2012-11-091-3/+2
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/taku-prt-cleanup: PCI/ACPI: Request _OSC control before scanning PCI root bus PCI: Don't pass pci_dev to pci_ext_cfg_avail() PCI/ACPI: Add _PRT interrupt routing info before enumerating devices ACPI: Pass segment/bus to _PRT add/del so they don't depend on pci_bus
| | * | | PCI: Don't pass pci_dev to pci_ext_cfg_avail()Taku Izumi2012-11-071-3/+2
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_ext_cfg_avail() doesn't use the "struct pci_dev *" passed to it, and there's no requirement that a host bridge even be represented by a pci_dev. This drops the pci_ext_cfg_avail() parameter. [bhelgaas: changelog] Signed-off-by: Taku Izumi <izumi.taku@jp.fujitsu.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | PCI/PM: Add comments for PME poll support for PCIeHuang Ying2012-11-071-9/+19
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are comments on why PME poll support is necessary for PCI devices, but not for PCIe devices. That may lead to misunderstanding that PME poll is only necessary for PCI devices. So add comments related to PCIe PME poll to make it more clear. The content of comments comes from the changelog of commit: 379021d5c0899fcf9410cae4ca7a59a5a94ca769 Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | | PCI: Remove __dev* markingsBill Pemberton2012-11-281-2/+2
| |/ |/| | | | | | | | | | | | | | | CONFIG_HOTPLUG is going away as an option so __devexit_p, __devint, __devinitdata, __devinitconst, and _devexit are no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | PCI/PM: Fix proc config reg access for D3cold and bridge suspendingHuang Ying2012-11-051-0/+32
|/ | | | | | | | | | | | | | | | | | | | | | | | | | In https://bugzilla.kernel.org/show_bug.cgi?id=48981 Peter reported that /proc/bus/pci/??/??.? does not work for 3.6. This is because the device configuration space registers are not accessible if the corresponding parent bridge is suspended or the device is put into D3cold state. This is the same as /sys/bus/pci/devices/0000:??:??.?/config access issue. So the function used to solve sysfs issue is used to solve this issue. This patch moves pci_config_pm_runtime_get()/_put() from pci/pci-sysfs.c to pci/pci.c and makes them extern so they can be used by both the sysfs and proc paths. [bhelgaas: changelog, references, reporters] Reference: https://bugzilla.kernel.org/show_bug.cgi?id=48981 Reference: https://bugzilla.kernel.org/show_bug.cgi?id=49031 Reported-by: Forrest Loomis <cybercyst@gmail.com> Reported-by: Peter <lekensteyn@gmail.com> Reported-by: Micael Dias <kam1kaz3@gmail.com> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> CC: stable@vger.kernel.org # v3.6+
* Merge branch 'pci/trivial' into nextBjorn Helgaas2012-09-131-1/+1
|\ | | | | | | | | | | | | | | | | | | * pci/trivial: PCI: Drop duplicate const in DECLARE_PCI_FIXUP_SECTION PCI: Drop bogus default from ARCH_SUPPORTS_MSI PCI: cpqphp: Remove unreachable path PCI: Remove bus number resource debug messages PCI/AER: Print completion message at KERN_INFO to match starting message PCI: Fix drivers/pci/pci.c kernel-doc warnings
| * PCI: Fix drivers/pci/pci.c kernel-doc warningsRandy Dunlap2012-08-221-1/+1
| | | | | | | | | | | | | | | | | | Fix kernel-doc warnings in drivers/pci/pci.c: Warning(drivers/pci/pci.c:1550): No description found for parameter 'pci_dev' Warning(drivers/pci/pci.c:1550): Excess function parameter 'dev' description in 'pci_wakeup' Signed-off-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge commit 'v3.6-rc5' into nextBjorn Helgaas2012-09-131-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * commit 'v3.6-rc5': (1098 commits) Linux 3.6-rc5 HID: tpkbd: work even if the new Lenovo Keyboard driver is not configured Remove user-triggerable BUG from mpol_to_str xen/pciback: Fix proper FLR steps. uml: fix compile error in deliver_alarm() dj: memory scribble in logi_dj Fix order of arguments to compat_put_time[spec|val] xen: Use correct masking in xen_swiotlb_alloc_coherent. xen: fix logical error in tlb flushing xen/p2m: Fix one-off error in checking the P2M tree directory. powerpc: Don't use __put_user() in patch_instruction powerpc: Make sure IPI handlers see data written by IPI senders powerpc: Restore correct DSCR in context switch powerpc: Fix DSCR inheritance in copy_thread() powerpc: Keep thread.dscr and thread.dscr_inherit in sync powerpc: Update DSCR on all CPUs when writing sysfs dscr_default powerpc/powernv: Always go into nap mode when CPU is offline powerpc: Give hypervisor decrementer interrupts their own handler powerpc/vphn: Fix arch_update_cpu_topology() return value ARM: gemini: fix the gemini build ... Conflicts: drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c drivers/rapidio/devices/tsi721.c
| * | PCI/PM: Enable D3/D3cold by default for most devicesHuang Ying2012-08-211-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following bug: http://marc.info/?l=linux-usb&m=134318961120825&w=2 Originally, device lower power states include D1, D2, D3. After that, D3 is further divided into D3hot and D3cold. To support both scenario safely, original D3 is mapped to D3cold. When adding D3cold support, because worry about some device may have broken D3cold support, D3cold is disabled by default. This disable D3 on original platform too. But some original platform may only have working D3, but no working D1, D2. The root cause of the above bug is it too. To deal with this, this patch enables D3/D3cold by default for most devices. This restores the original behavior. For some devices that suspected to have broken D3cold support, such as PCIe port, D3cold is disabled by default. Reported-by: Bjorn Mork <bjorn@mork.no> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
* | Merge branch 'pci/bjorn-find-next-ext-cap' into nextBjorn Helgaas2012-08-231-10/+30
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * pci/bjorn-find-next-ext-cap: PCI: Add Vendor-Specific Extended Capability header info PCI: Add pci_find_next_ext_capability() Conflicts: drivers/pci/pci.c
| * | PCI: Add pci_find_next_ext_capability()Bjorn Helgaas2012-08-221-10/+30
| |/ | | | | | | | | | | | | | | Some extended capabilities, e.g., the vendor-specific capability, can occur several times. The existing pci_find_ext_capability() only finds the first occurrence. This adds pci_find_next_ext_capability(), which can iterate through all of them. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI/core: Use PCI Express Capability accessorsJiang Liu2012-08-231-253/+61
| | | | | | | | | | | | | | Use PCI Express Capability access functions to simplify core. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: Introduce pci_pcie_type(dev) to replace pci_dev->pcie_typeYijing Wang2012-08-231-12/+14
|/ | | | | | | | | Introduce an inline function pci_pcie_type(dev) to extract PCIe device type from pci_dev->pcie_flags_reg field, and prepare for removing pci_dev->pcie_type. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Merge branch 'pci/rafael-pci_set_power_state-rebase' into nextBjorn Helgaas2012-07-051-1/+18
|\ | | | | | | | | * pci/rafael-pci_set_power_state-rebase: PCI / PM: restore the original behavior of pci_set_power_state()
| * PCI / PM: restore the original behavior of pci_set_power_state()Rafael J. Wysocki2012-07-051-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cc2893b6 (PCI: Ensure we re-enable devices on resume) addressed the problem with USB not being powered after resume on recent Lenovo machines, but it did that in a suboptimal way. Namely, it should have changed the relevant code paths only, which are pci_pm_resume_noirq() and pci_pm_restore_noirq() supposed to restore the device's power and standard configuration registers after system resume from suspend or hibernation. Instead, however, it modified pci_set_power_state() which is executed in several other situations too. That resulted in some undesirable effects, like attempting to change a device's power state in the same way multiple times in a row (up to as many as 4 times in a row in the snd_hda_intel driver). Fix the bug addressed by commit cc2893b6 in an alternative way, by forcibly powering up all devices in pci_pm_default_resume_early(), which is called by pci_pm_resume_noirq() and pci_pm_restore_noirq() to restore the device's power and standard configuration registers, and modifying pci_pm_runtime_resume() to avoid the forcible power-up if not necessary. Then, revert the changes made by commit cc2893b6 to make the confusion introduced by it go away. Acked-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/myron-pcibios_setup' into nextBjorn Helgaas2012-07-051-0/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/myron-pcibios_setup: xtensa/PCI: factor out pcibios_setup() x86/PCI: adjust section annotations for pcibios_setup() unicore32/PCI: adjust section annotations for pcibios_setup() tile/PCI: factor out pcibios_setup() sparc/PCI: factor out pcibios_setup() sh/PCI: adjust section annotations for pcibios_setup() sh/PCI: factor out pcibios_setup() powerpc/PCI: factor out pcibios_setup() parisc/PCI: factor out pcibios_setup() MIPS/PCI: adjust section annotations for pcibios_setup() MIPS/PCI: factor out pcibios_setup() microblaze/PCI: factor out pcibios_setup() ia64/PCI: factor out pcibios_setup() cris/PCI: factor out pcibios_setup() alpha/PCI: factor out pcibios_setup() PCI: pull pcibios_setup() up into core
| * | PCI: pull pcibios_setup() up into coreMyron Stowe2012-06-261-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, all of the architectures implement their own pcibios_setup() routine. Most of the implementations do nothing so this patch introduces a generic (__weak) routine in the core that can be used by all architectures as a default. If necessary, it can be overridden by architecture-specific code. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | | Merge branch 'topic/huang-d3cold-v7' into nextBjorn Helgaas2012-06-231-9/+115
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | * topic/huang-d3cold-v7: PCI/PM: add PCIe runtime D3cold support PCI: do not call pci_set_power_state with PCI_D3cold PCI/PM: add runtime PM support to PCIe port ACPI/PM: specify lowest allowed state for device sleep state
| * | PCI/PM: add PCIe runtime D3cold supportHuang Ying2012-06-231-9/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime D3cold support and corresponding ACPI platform support. This patch only enables runtime D3cold support; it does not enable D3cold support during system suspend/hibernate. D3cold is the deepest power saving state for a PCIe device, where its main power is removed. While it is in D3cold, you can't access the device at all, not even its configuration space (which is still accessible in D3hot). Therefore the PCI PM registers can not be used to transition into/out of the D3cold state; that must be done by platform logic such as ACPI _PR3. To support wakeup from D3cold, a system may provide auxiliary power, which allows a device to request wakeup using a Beacon or the sideband WAKE# signal. WAKE# is usually connected to platform logic such as ACPI GPE. This is quite different from other power saving states, where devices request wakeup via a PME message on the PCIe link. Some devices, such as those in plug-in slots, have no direct platform logic. For example, there is usually no ACPI _PR3 for them. D3cold support for these devices can be done via the PCIe Downstream Port leading to the device. When the PCIe port is powered on/off, the device is powered on/off too. Wakeup events from the device will be notified to the corresponding PCIe port. For more information about PCIe D3cold and corresponding ACPI support, please refer to: - PCI Express Base Specification Revision 2.0 - Advanced Configuration and Power Interface Specification Revision 5.0 [bhelgaas: changelog] Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Originally-by: Zheng Yan <zheng.z.yan@intel.com> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI/PM: add runtime PM support to PCIe portZheng Yan2012-06-231-0/+10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime PM support to PCIe port. This is needed by PCIe D3cold support, where PCIe device without ACPI node may be powered on/off by PCIe port. Because runtime suspend is broken for some chipsets, a black list is used to disable runtime PM support for these chipsets. Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Zheng Yan <zheng.z.yan@intel.com> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'topic/bjorn-trivial' into nextBjorn Helgaas2012-06-221-8/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * topic/bjorn-trivial: PCI: remove useless pcix_set_mmrbc() dev->bus check PCI: acpiphp: check whether _ADR evaluation succeeded PCI: shpchp: remove dead code PCI: fix P2P bridge I/O port window sign extension PCI: fix upstream P2P bridge checks when enabling OBFF and LTR PCI: use __weak consistently PCI: cleanup assign_requested_resources_sorted() kernel-doc warning sparc/PCI: remove unused pcibios_assign_resource() definition
| * | PCI: remove useless pcix_set_mmrbc() dev->bus checkBjorn Helgaas2012-06-201-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | For a valid pci_dev, dev->bus != NULL always, so remove this unnecessary test. Found by Coverity (CID 101680). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: fix upstream P2P bridge checks when enabling OBFF and LTRBjorn Helgaas2012-06-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_enable_obff() and pci_enable_ltr() incorrectly check "dev->bus" instead of "dev->bus->self" to determine whether the upstream device is a P2P bridge or a host bridge. For devices on the root bus, the upstream device is a host bridge, "dev->bus != NULL" and "dev->bus->self == NULL", and we panic with a null pointer dereference. These functions should previously have panicked when called on devices supporting OBFF or LTR, so they should be regarded as untested. Found by Coverity (CID 143038 and CID 143039). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: use __weak consistentlyBjorn Helgaas2012-06-201-4/+4
| |/ | | | | | | | | Use "__weak" instead of the gcc-specific "__attribute__ ((weak))" Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'topic/jan-intx-masking' into nextBjorn Helgaas2012-06-181-0/+3
|\ \ | | | | | | | | | | | | | | | | | | * topic/jan-intx-masking: PCI: add Ralink RT2800 broken INTx masking quirk PCI: add Chelsio T310 10GbE NIC broken INTx masking quirk PCI: add infrastructure for devices with broken INTx masking
| * | PCI: add infrastructure for devices with broken INTx maskingBjorn Helgaas2012-06-161-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | pci_intx_mask_supported() assumes INTx masking is supported if the PCI_COMMAND_INTX_DISABLE bit is writable. But when that bit is set, some devices don't actually mask INTx or update PCI_STATUS_INTERRUPT as we expect. This patch adds a way for quirks to identify these broken devices. [bhelgaas: split out from Chelsio quirk addition] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'topic/stowe-cap-cleanup' into nextBjorn Helgaas2012-06-181-48/+67
|\ \ | | | | | | | | | | | | | | | | | | | | | * topic/stowe-cap-cleanup: PCI: remove redundant capabilities checking in pci_{save, restore}_pcie_state PCI: add pci_pcie_cap2() check for PCIe feature capabilities >= v2 PCI: remove redundant checking in PCI Express capability routines PCI: make pci_ltr_supported() static
| * | PCI: remove redundant capabilities checking in pci_{save, restore}_pcie_stateMyron Stowe2012-06-111-18/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike PCI Express v1's Capabilities Structure, v2's requires the entire structure to be implemented. In v2 structures, register fields that are not implemented are present but hardwired to 0x0. These may include: Link Capabilities, Status, and Control; Slot Capabilities, Status, and Control; Root Capabilities, Status, and Control; and all of the '2' (Device, Link, and Slot) Capabilities, Status, and Control registers. This patch removes the redundant capability checks corresponding to the Link 2's and Slot 2's, Capabilities, Status, and Control registers as they will be present if Device Capabilities 2's registers are (which explains why the macros for each of the three are identical). Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: add pci_pcie_cap2() check for PCIe feature capabilities >= v2Myron Stowe2012-06-111-15/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch resolves potential issues when accessing PCI Express Capability structures. The makeup of the capability varies substantially between v1 and v2: Version 1 of the PCI Express Capability (defined by PCI Express 1.0 and 1.1 base) neither requires the endpoint to implement the entire PCIe capability structure nor specifies default values of registers that are not implemented by the device. Version 2 of the PCI Express Capability (defined by PCIe 1.1 Capability Structure Expansion ECN, PCIe 2.0, 2.1, and 3.0) added additional registers to the structure and requires all registers to be either implemented or hardwired to 0. Due to the differences in the capability structures, code dealing with capability features must be careful not to access the additional registers introduced with v2 unless the device is specifically known to be a v2 capable device. Otherwise, attempts to access non-existant registers will occur. This is a subtle issue that is hard to track down when it occurs (and it has - see commit 864d296cf94). To try and help mitigate such occurrences, this patch introduces pci_pcie_cap2() which is similar to pci_pcie_cap() but also checks that the PCIe capability version is >= 2. pci_pcie_cap2() should be used for qualifying PCIe capability features introduced after v1. Suggested by Don Dutile. Acked-by: Donald Dutile <ddutile@redhat.com> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: remove redundant checking in PCI Express capability routinesMyron Stowe2012-06-111-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a number of redundant pci_is_pcie() checks in various PCI Express capabilities related routines like the following: if (!pci_is_pcie(dev)) return false; pos = pci_pcie_cap(dev); if (!pos) return false; The current pci_is_pcie() implementation is merely: static inline bool pci_is_pcie(struct pci_dev *dev) { return !!pci_pcie_cap(dev); } so we can just drop the pci_is_pcie() test in such cases. Acked-by: Donald Dutile <ddutile@redhat.com> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: make pci_ltr_supported() staticMyron Stowe2012-06-111-2/+1
| |/ | | | | | | | | | | | | | | | | The PCI Express Latency Tolerance Reporting (LTR) feature's pci_ltr_supported() routine is currently only used within drivers/pci/pci.c so make it static. Acked-by: Donald Dutile <ddutile@redhat.com> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'topic/alex-vfio-prep' into nextBjorn Helgaas2012-06-131-0/+69
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * topic/alex-vfio-prep: PCI: misc pci_reg additions PCI: create common pcibios_err_to_errno PCI: export pci_user functions for use by other drivers PCI: add ACS validation utility PCI: add PCI DMA source ID quirk
| * | PCI: add ACS validation utilityAlex Williamson2012-06-121-0/+69
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a PCI environment, transactions aren't always required to reach the root bus before being re-routed. Intermediate switches between an endpoint and the root bus can redirect DMA back downstream before things like IOMMUs have a chance to intervene. Legacy PCI is always susceptible to this as it operates on a shared bus. PCIe added a new capability to describe and control this behavior, Access Control Services, or ACS. The utility function pci_acs_enabled() allows us to test the ACS capabilities of an individual devices against a set of flags while pci_acs_path_enabled() tests a complete path from a given downstream device up to the specified upstream device. We also include the ability to add device specific tests as it's likely we'll see devices that do not implement ACS, but want to indicate support for various capabilities in this space. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'topic/bjorn-remove-unused' into nextBjorn Helgaas2012-06-131-67/+0
|\ \ | | | | | | | | | | | | | | | | | | * topic/bjorn-remove-unused: PCI/AER: use pci_is_pcie() instead of obsolete pci_dev.is_pcie PCI: remove pci_max_busnr() (was already commented out) PCI: remove pci_bus_find_ext_capability() (unused)
| * | PCI: remove pci_max_busnr() (was already commented out)Bjorn Helgaas2012-06-111-24/+0
| | | | | | | | | | | | | | | | | | | | | pci_max_busnr() has been commented out for years (since 54c762fe62), and this patch removes it completely. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: remove pci_bus_find_ext_capability() (unused)Bjorn Helgaas2012-06-111-43/+0
| |/ | | | | | | | | | | pci_bus_find_ext_capability() is unused, and this patch removes it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: replace struct pci_bus secondary/subordinate with busn_resYinghai Lu2012-06-131-1/+1
|/ | | | | | | | | Replace the struct pci_bus secondary/subordinate members with the struct resource busn_res. Later we'll build a resource tree of these bus numbers. [bhelgaas: changelog] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-05-291-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "The whole series has been sitting in -next for quite a while with no complaints. The last change to the series was before the weekend the removal of an SPI patch which Grant - even though previously acked by himself - appeared to raise objections. So I removed it until the situation is clarified. Other than that all the patches have the acks from their respective maintainers, all MIPS and x86 defconfigs are building fine and I'm not aware of any problems introduced by this series. Among the key features for this patch series is a sizable patchset for Lantiq which among other things introduces support for Lantiq's flagship product, the FALCON SOC. It also means that the opensource developers behind this patchset have overtaken Lantiq's competing inhouse development team that was working behind closed doors. Less noteworthy the ath79 patchset which adds support for a few more chip variants, cleanups and fixes. Finally the usual dose of tweaking of generic code." Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where printk spelling fixes clashed with file move and eventual removal of the printk. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits) MIPS: lantiq: remove orphaned code MIPS: Remove all -Wall and almost all -Werror usage from arch/mips. MIPS: lantiq: implement support for FALCON soc MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc MTD: MIPS: lantiq: implement OF support watchdog: MIPS: lantiq: implement OF support and minor fixes SERIAL: MIPS: lantiq: implement OF support GPIO: MIPS: lantiq: convert gpio-stp-xway to OF GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder MIPS: pci: convert lantiq driver to OF MIPS: lantiq: convert dma to platform driver MIPS: lantiq: implement support for clkdev api MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq() OF: MIPS: lantiq: implement irq_domain support OF: MIPS: lantiq: implement OF support MIPS: lantiq: drop mips_machine support OF: PCI: const usage needed by MIPS MIPS: Cavium: Remove smp_reserve_lock. MIPS: Move cache setup to setup_arch(). ...
| * OF: PCI: const usage needed by MIPSJohn Crispin2012-05-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On MIPS we want to call of_irq_map_pci from inside arch/mips/include/asm/pci.h:extern int pcibios_map_irq( const struct pci_dev *dev, u8 slot, u8 pin); For this to work we need to change several functions to const usage. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-pci@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-mips@linux-mips.org Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: https://patchwork.linux-mips.org/patch/3710/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'topic/stratus' into nextBjorn Helgaas2012-05-071-0/+3
|\ \
| * | PCI: work around Stratus ftServer broken PCIe hierarchyBjorn Helgaas2012-04-301-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A PCIe downstream port is a P2P bridge. Its secondary interface is a link that should lead only to device 0 (unless ARI is enabled)[1], so we don't probe for non-zero device numbers. Some Stratus ftServer systems have a PCIe downstream port (02:00.0) that leads to both an upstream port (03:00.0) and a downstream port (03:01.0), and 03:01.0 has important devices below it: [0000:02]-+-00.0-[03-3c]--+-00.0-[04-09]--... \-01.0-[0a-0d]--+-[USB] +-[NIC] +-... Previously, we didn't enumerate device 03:01.0, so USB and the network didn't work. This patch adds a DMI quirk to scan all device numbers, not just 0, below a downstream port. Based on a patch by Prarit Bhargava. [1] PCIe spec r3.0, sec 7.3.1 CC: Myron Stowe <mstowe@redhat.com> CC: Don Dutile <ddutile@redhat.com> CC: James Paradis <james.paradis@stratus.com> CC: Matthew Wilcox <matthew.r.wilcox@intel.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> CC: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: move mutex locking out of pci_dev_reset functionKonrad Rzeszutek Wilk2012-04-301-10/+17
|/ | | | | | | | | | | | | | | | | | | The intent of git commit 6fbf9e7a90862988c278462d85ce9684605a52b2 "PCI: Introduce __pci_reset_function_locked to be used when holding device_lock." was to have a non-locking function that would call pci_dev_reset function. But it fell short of that by just probing and not actually reseting the device. To make that work we need a way to move the lock around device_lock to not be in pci_dev_reset (as the caller of __pci_reset_function_locked already holds said lock). We do this by renaming pci_dev_reset to __pci_dev_reset and bubbling said mutex out of __pci_dev_reset to pci_dev_reset (a wrapper around __pci_dev_reset). The __pci_reset_function_locked can now call __pci_dev_reset without having to worry about the dead-lock. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: Retry BARs restoration for Type 0 headers onlyRafael J. Wysocki2012-04-161-9/+15
| | | | | | | | | | | | | | | | | | | | | | | Some shortcomings introduced into pci_restore_state() by commit 26f41062f28d ("PCI: check for pci bar restore completion and retry") have been fixed by recent commit ebfc5b802fa76 ("PCI: Fix regression in pci_restore_state(), v3"), but that commit treats all PCI devices as those with Type 0 configuration headers. That is not entirely correct, because Type 1 and Type 2 headers have different layouts. In particular, the area occupied by BARs in Type 0 config headers contains the secondary status register in Type 1 ones and it doesn't make sense to retry the restoration of that register even if the value read back from it after a write is not the same as the written one (it very well may be different). For this reason, make pci_restore_state() only retry the restoration of BARs for Type 0 config headers. This effectively makes it behave as before commit 26f41062f28d for all header types except for Type 0. Tested-by: Mikko Vinni <mmvinni@yahoo.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* PCI: Fix regression in pci_restore_state(), v3Rafael J. Wysocki2012-04-151-18/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 26f41062f28d ("PCI: check for pci bar restore completion and retry") attempted to address problems with PCI BAR restoration on systems where FLR had not been completed before pci_restore_state() was called, but it did that in an utterly wrong way. First off, instead of retrying the writes for the BAR registers only, it did that for all of the PCI config space of the device, including the status register (whose value after the write quite obviously need not be the same as the written one). Second, it added arbitrary delay to pci_restore_state() even for systems where the PCI config space restoration was successful at first attempt. Finally, the mdelay(10) it added to every iteration of the writing loop was way too much of a delay for any reasonable device. All of this actually caused resume failures for some devices on Mikko's system. To fix the regression, make pci_restore_state() only retry the writes for BAR registers and only wait if the first read from the register doesn't return the written value. Additionaly, make it wait for 1 ms, instead of 10 ms, after every failing attempt to write into config space. Reported-by: Mikko Vinni <mmvinni@yahoo.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
generated by cgit v1.1 at 2024-12-26 12:53:58 +0000