From 7f1225bd6e62c54edfa0a2464648ad9e4efb1313 Mon Sep 17 00:00:00 2001 From: Satish Date: Wed, 9 Jun 2010 13:21:27 +0300 Subject: omap iommu: Fix Memory leak The memory allocated for sgt structure is not freed on error when sg_alloc_table is called in sgtable_alloc(). Signed-off-by: Satish Kumar Signed-off-by: Manjunatha GK Cc: Vimal Singh Signed-off-by: Hiroshi DOYU Signed-off-by: Tony Lindgen --- arch/arm/plat-omap/iovmm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c index e43983b..8ce0de2 100644 --- a/arch/arm/plat-omap/iovmm.c +++ b/arch/arm/plat-omap/iovmm.c @@ -140,8 +140,10 @@ static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags) return ERR_PTR(-ENOMEM); err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL); - if (err) + if (err) { + kfree(sgt); return ERR_PTR(err); + } pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries); -- cgit v1.1 From bfb01197589965663772e6388f2bdf452e25adf2 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 9 Jun 2010 13:53:05 +0300 Subject: omap: fix build failure due to missing include dma-mapping.h Fixes following error, CC arch/arm/mach-omap2/usb-ehci.o arch/arm/mach-omap2/usb-ehci.c:263: error: implicit declaration of function 'DMA_BIT_MASK' arch/arm/mach-omap2/usb-ehci.c:263: error: initializer element is not constant make[1]: *** [arch/arm/mach-omap2/usb-ehci.o] Error 1 Signed-off-by: Amit Kucheria Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/usb-ehci.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index c68f799..d72d1ac 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c @@ -20,6 +20,8 @@ #include #include #include +#include + #include #include -- cgit v1.1 From 99716b662ba527ea66172ba215da8a9d0e567c3e Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 9 Jun 2010 13:53:05 +0300 Subject: omap: Stalker board: switch over to gpio_set_debounce Commit 48feb337475a arm: omap: switch over to gpio_set_debounce caused "undefined reference to omap_set_gpio_debounce" build error. The fix is to use the generic gpiolib function. Cc: Felipe Balbi Cc: Kevin Hilman Signed-off-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3stalker.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index f848ba8..a04cffd 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -538,9 +538,7 @@ static void ads7846_dev_init(void) printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); gpio_direction_input(OMAP3_STALKER_TS_GPIO); - - omap_set_gpio_debounce(OMAP3_STALKER_TS_GPIO, 1); - omap_set_gpio_debounce_time(OMAP3_STALKER_TS_GPIO, 0xa); + gpio_set_debounce(OMAP3_STALKER_TS_GPIO, 310); } static int ads7846_get_pendown_state(void) -- cgit v1.1 From 856f19145104dcab5b1415c1936c9aa81d83ba04 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 9 Jun 2010 13:53:05 +0300 Subject: omap: DMTIMER: Ack pending interrupt always when stopping a timer The kernel timer queue is being run currently from a GP timer running in a one shot mode, which works in a way that when it expires, it will also stop. Usually during this situation, the interrupt handler will ack the interrupt, load a new value to the timer and start it again. During suspend, the situation is slightly different, as we disable interrupts just before timekeeping is suspended, which leaves a small window where the timer can expire before it is stopped, and will leave the interrupt flag pending. This pending interrupt will prevent ARM sleep entry, thus now we ack it always when we are attempting to stop a timer. Signed-off-by: Tero Kristo Acked-by: Kevin Hilman [tony@atomide.com: removed the ifdef to make the patch cover omap1 also] Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dmtimer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index c64875f..44bafda 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -541,11 +541,11 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer) * timer is stopped */ udelay(3500000 / clk_get_rate(timer->fclk) + 1); - /* Ack possibly pending interrupt */ - omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, - OMAP_TIMER_INT_OVERFLOW); #endif } + /* Ack possibly pending interrupt */ + omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, + OMAP_TIMER_INT_OVERFLOW); } EXPORT_SYMBOL_GPL(omap_dm_timer_stop); -- cgit v1.1 From f7ec0b0b16c97a75a1b6aa8bc8b32548003f3339 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 9 Jun 2010 13:53:07 +0300 Subject: omap: GPIO: fix auto-disable of debounce clock The addition of the new debounce code (commit 168ef3d9a56bd8bffe0ef4189c450888b4aefefe) broke the auto-disable of debounce clocks on idle by forgetting to update the debounce clock enable mask. Add back the updating of bank->dbck_enable_mask so debounce clocks are auto-disabled. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 393e921..9b7e354 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -673,6 +673,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, if (cpu_is_omap34xx() || cpu_is_omap44xx()) clk_disable(bank->dbck); } + bank->dbck_enable_mask = val; __raw_writel(val, reg); } -- cgit v1.1 From 0b96a3a3c5c5e6e1b79a05c23d110d59518f4fc8 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 9 Jun 2010 13:53:09 +0300 Subject: OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg Checking to se if the IO daisy chain is enabled should be checking the PM_WKEN register, not the PM_WKST register. Reading PM_WKST tells us if an event occurred, not whether or not it is enabled. Apparently, we've been lucky until now in that a pending event has not been there during enable. However, on 3630/Zoom3, I noticed because of the WARN that this timeout was always happening. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 2e96771..b88737f 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -99,7 +99,7 @@ static void omap3_enable_io_chain(void) /* Do a readback to assure write has been done */ prm_read_mod_reg(WKUP_MOD, PM_WKEN); - while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & + while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & OMAP3430_ST_IO_CHAIN_MASK)) { timeout++; if (timeout > 1000) { @@ -108,7 +108,7 @@ static void omap3_enable_io_chain(void) return; } prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, - WKUP_MOD, PM_WKST); + WKUP_MOD, PM_WKEN); } } } -- cgit v1.1 From 390daa0d8f391378865221cd8446028884a3baa9 Mon Sep 17 00:00:00 2001 From: Steve Bennett Date: Wed, 21 Apr 2010 16:30:33 +1000 Subject: [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.h gpio must be int, not u16, otherwise -1 isn't recognised by gpio_is_valid(). Signed-off-by: Steve Bennett Signed-off-by: Eric Miao --- arch/arm/include/asm/mach/udc_pxa2xx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h index f3eabf1..833306e 100644 --- a/arch/arm/include/asm/mach/udc_pxa2xx.h +++ b/arch/arm/include/asm/mach/udc_pxa2xx.h @@ -21,8 +21,8 @@ struct pxa2xx_udc_mach_info { * here. Note that sometimes the signals go through inverters... */ bool gpio_vbus_inverted; - u16 gpio_vbus; /* high == vbus present */ + int gpio_vbus; /* high == vbus present */ bool gpio_pullup_inverted; - u16 gpio_pullup; /* high == pullup activated */ + int gpio_pullup; /* high == pullup activated */ }; -- cgit v1.1 From 60adc112bbd430b90cbafecc19e6e9be2e2000e3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 3 Jun 2010 03:50:10 +0200 Subject: [ARM] pxa/z2: fix flash layout to final version This patch fixes flash layout to it's final version. Also, I fixed the authorship information of this file as it's been totally reworked since Ken released his last version. Signed-off-by: Marek Vasut Signed-off-by: Eric Miao --- arch/arm/mach-pxa/z2.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index f5d1ae3..d303c69 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -3,8 +3,9 @@ * * Support for the Zipit Z2 Handheld device. * - * Author: Ken McGuire - * Created: Jan 25, 2009 + * Copyright (C) 2009-2010 Marek Vasut + * + * Based on research and code by: Ken McGuire * Based on mainstone.c as modified for the Zipit Z2. * * This program is free software; you can redistribute it and/or modify @@ -157,21 +158,14 @@ static struct mtd_partition z2_flash_parts[] = { { .name = "U-Boot Bootloader", .offset = 0x0, - .size = 0x20000, - }, - { - .name = "Linux Kernel", - .offset = 0x20000, - .size = 0x220000, - }, - { - .name = "Filesystem", - .offset = 0x240000, - .size = 0x5b0000, - }, - { + .size = 0x40000, + }, { .name = "U-Boot Environment", - .offset = 0x7f0000, + .offset = 0x40000, + .size = 0x60000, + }, { + .name = "Flash", + .offset = 0x60000, .size = MTDPART_SIZ_FULL, }, }; -- cgit v1.1 From 8dbed71ad1ab0636745af958934f1ca670702ca0 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 2 Jun 2010 23:29:50 +0200 Subject: [ARM] pxa/mioa701: fix camera regression Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the camera is not working anymore. After the v4l2 migration, the mt9m111 camera board information was not passed to the i2c layer anymore, but stored for future use of v4l2 (through soc_camera). Because mioa701_i2c_devices[] was tagged as "__initdata", and because after the v4l2 migration, the new structure "iclink" references it, the mt9m111 driver is not probed anymore, as part of "iclink" is not valid (discarded after kernel init). Although there is not compilation error, nor runtime oops, this patch restores a working camera on the mioa701 board. Signed-off-by: Robert Jarzmik Acked-by: Guennadi Liakhovetski Signed-off-by: Eric Miao --- arch/arm/mach-pxa/mioa701.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index d60db87..fa6a708 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -697,7 +697,7 @@ static struct i2c_board_info __initdata mioa701_pi2c_devices[] = { }; /* Board I2C devices. */ -static struct i2c_board_info __initdata mioa701_i2c_devices[] = { +static struct i2c_board_info mioa701_i2c_devices[] = { { I2C_BOARD_INFO("mt9m111", 0x5d), }, -- cgit v1.1 From cdb4acc0568f4f6e10e778f0c2cd04fcd4786c09 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Mon, 7 Jun 2010 18:49:19 +0100 Subject: [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXA PMU is not tested and enabled on MMP architecture at this moment, the device IRQ number, IRQ_PMU depends on ARCH_PXA. Build PMU only for ARCH_PXA. Signed-off-by: Jonathan Cameron Signed-off-by: Eric Miao --- arch/arm/plat-pxa/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index 6187edf..a17cc0c 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile @@ -2,8 +2,9 @@ # Makefile for code common across different PXA processor families # -obj-y := dma.o pmu.o +obj-y := dma.o +obj-$(CONFIG_ARCH_PXA) += pmu.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.o -- cgit v1.1 From 090830b4c79cd5ac85430822a9b87c90848bedcf Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 16 Jun 2010 19:01:33 +0300 Subject: OMAP4: clock: Fix multi-omap boot with reset un-used clocks This patch uses "ENABLE_ON_INIT" flag on the emif clock nodes to avoid the emif clk getting cut as part of reset un-used clock routine which prevents boot. Since "omap4xxx_clk_init()" calls "clk_enable_init_clocks()" which increases the usecount on all ENABLE_ON_INIT clocks, it prevents "omap2_clk_disable_unused()" from disabling the clock. The real fix is to have driver for EMIF and do clock get/enable as part of it. The EMIF driver is planned to be done HWMOD way so till that available to keep omap3_defconfig booting on OMAP4430, this patch is necessary. (Will updated the auto-gen script for 44xx accordingly) The fix was suggested by Paul Walmsley Signed-off-by: Santosh Shilimkar Tested-by: Nishanth Menon Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock44xx_data.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 0280422..e10db7a 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1369,6 +1369,7 @@ static struct clk emif1_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .flags = ENABLE_ON_INIT, .clkdm_name = "l3_emif_clkdm", .parent = &ddrphy_ck, .recalc = &followparent_recalc, @@ -1379,6 +1380,7 @@ static struct clk emif2_ick = { .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .flags = ENABLE_ON_INIT, .clkdm_name = "l3_emif_clkdm", .parent = &ddrphy_ck, .recalc = &followparent_recalc, -- cgit v1.1 From dc75925d67950889b79df1cc1518c21ec678df6c Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 23 Jun 2010 18:15:12 -0600 Subject: OMAP: hwmod: Fix the missing braces As reported by Sergei, a couple of braces were missing after the WARN removal patch. [07/22] OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed https://patchwork.kernel.org/patch/100756/ Signed-off-by: Benoit Cousson [paul@pwsan.com: fixed patch description per Anand's E-mail] Signed-off-by: Paul Walmsley Cc: Sergei Shtylyov Cc: Anand Gadiyar --- arch/arm/mach-omap2/omap_hwmod.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 95c9a5f..b7a4133 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -409,10 +409,11 @@ static int _init_main_clk(struct omap_hwmod *oh) return 0; oh->_clk = omap_clk_get_by_name(oh->main_clk); - if (!oh->_clk) + if (!oh->_clk) { pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", oh->name, oh->main_clk); return -EINVAL; + } if (!oh->_clk->clkdm) pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", @@ -444,10 +445,11 @@ static int _init_interface_clks(struct omap_hwmod *oh) continue; c = omap_clk_get_by_name(os->clk); - if (!c) + if (!c) { pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", oh->name, os->clk); ret = -EINVAL; + } os->_clk = c; } @@ -470,10 +472,11 @@ static int _init_opt_clks(struct omap_hwmod *oh) for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { c = omap_clk_get_by_name(oc->clk); - if (!c) + if (!c) { pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", oh->name, oc->clk); ret = -EINVAL; + } oc->_clk = c; } -- cgit v1.1 From fb967ecc584c20c74a007de749ca597068b0fcac Mon Sep 17 00:00:00 2001 From: Liu Aleaxander Date: Tue, 29 Jun 2010 15:05:40 -0700 Subject: um: os-linux/mem.c needs sys/stat.h The os-linux/mem.c file calls fchmod function, which is declared in sys/stat.h header file, so include it. Fixes build breakage under FC13. Signed-off-by: Liu Aleaxander Acked-by: Boaz Harrosh Cc: Jeff Dike Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/um/os-Linux/mem.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/um/os-Linux/mem.c b/arch/um/os-Linux/mem.c index 93a11d7..e696144 100644 --- a/arch/um/os-Linux/mem.c +++ b/arch/um/os-Linux/mem.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include "init.h" -- cgit v1.1 From a1e80fafc9f0742a1776a0490258cb64912411b0 Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Wed, 30 Jun 2010 15:09:06 +0200 Subject: x86: Send a SIGTRAP for user icebp traps Before we had a generic breakpoint layer, x86 used to send a sigtrap for any debug event that happened in userspace, except if it was caused by lazy dr7 switches. Currently we only send such signal for single step or breakpoint events. However, there are three other kind of debug exceptions: - debug register access detected: trigger an exception if the next instruction touches the debug registers. We don't use it. - task switch, but we don't use tss. - icebp/int01 trap. This instruction (0xf1) is undocumented and generates an int 1 exception. Unlike single step through TF flag, it doesn't set the single step origin of the exception in dr6. icebp then used to be reported in userspace using trap signals but this have been incidentally broken with the new breakpoint code. Reenable this. Since this is the only debug event that doesn't set anything in dr6, this is all we have to check. This fixes a regression in Wine where World Of Warcraft got broken as it uses this for software protection checks purposes. And probably other apps do. Reported-and-tested-by: Alexandre Julliard Signed-off-by: Frederic Weisbecker Cc: Ingo Molnar Cc: H. Peter Anvin Cc: Thomas Gleixner Cc: Prasad Cc: 2.6.33.x 2.6.34.x --- arch/x86/kernel/traps.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 142d70c..725ef4d 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -526,6 +526,7 @@ asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs) dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code) { struct task_struct *tsk = current; + int user_icebp = 0; unsigned long dr6; int si_code; @@ -534,6 +535,14 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code) /* Filter out all the reserved bits which are preset to 1 */ dr6 &= ~DR6_RESERVED; + /* + * If dr6 has no reason to give us about the origin of this trap, + * then it's very likely the result of an icebp/int01 trap. + * User wants a sigtrap for that. + */ + if (!dr6 && user_mode(regs)) + user_icebp = 1; + /* Catch kmemcheck conditions first of all! */ if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) return; @@ -575,7 +584,7 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code) regs->flags &= ~X86_EFLAGS_TF; } si_code = get_si_code(tsk->thread.debugreg6); - if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS)) + if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) send_sigtrap(tsk, regs, error_code, si_code); preempt_conditional_cli(regs); -- cgit v1.1 From b70f4e85bfc4d7000036355b714a92d5c574f1be Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Wed, 30 Jun 2010 10:46:16 -0700 Subject: [IA64] Fix spinaphore down_spin() Typo in down_spin() meant it only read the low 32 bits of the "serve" value, instead of the full 64 bits. This results in the system hanging when the values in ticket/serve get larger than 32-bits. A big enough system running the right test can hit this in a just a few hours. Broken since 883a3acf5b0d4782ac35981227a0d094e8b44850 [IA64] Re-implement spinaphores using ticket lock concepts Reported via IRC by Bjorn Helgaas Signed-off-by: Tony Luck --- arch/ia64/mm/tlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c index 5dfd916..7b3cdc6 100644 --- a/arch/ia64/mm/tlb.c +++ b/arch/ia64/mm/tlb.c @@ -121,7 +121,7 @@ static inline void down_spin(struct spinaphore *ss) ia64_invala(); for (;;) { - asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory"); + asm volatile ("ld8.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory"); if (time_before(t, serve)) return; cpu_relax(); -- cgit v1.1 From 4d5d85906ad109987504033fa04991f1b0a2e552 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 25 May 2010 16:46:55 +0200 Subject: ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init': mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mach-mx31lilly.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index d3d5877..b2c7f51 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -115,6 +115,8 @@ static struct platform_device physmap_flash_device = { /* USB */ +#if defined(CONFIG_USB_ULPI) + #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -244,10 +246,20 @@ static struct mxc_usbh_platform_data usbh2_pdata = { .flags = MXC_EHCI_POWER_PINS_ENABLED, }; -static struct platform_device *devices[] __initdata = { - &smsc91x_device, - &physmap_flash_device, -}; +static void lilly1131_usb_init(void) +{ + usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh1, &usbh1_pdata); + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +} + +#else +static inline void lilly1131_usb_init(void) {} +#endif /* CONFIG_USB_ULPI */ /* SPI */ @@ -279,6 +291,11 @@ static struct spi_board_info mc13783_dev __initdata = { .platform_data = &mc13783_pdata, }; +static struct platform_device *devices[] __initdata = { + &smsc91x_device, + &physmap_flash_device, +}; + static int mx31lilly_baseboard; core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); @@ -321,13 +338,7 @@ static void __init mx31lilly_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); /* USB */ - usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); - usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); - - mxc_register_device(&mxc_usbh1, &usbh1_pdata); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + lilly1131_usb_init(); } static void __init mx31lilly_timer_init(void) -- cgit v1.1 From a5e9d38b226686c89fd78413456535d5b66e8b1f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 21 Jun 2010 15:09:06 +0100 Subject: ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds This macro is not defined when !CONFIG_MMU so this patch moves the CONSISTENT_* definitions to the CONFIG_MMU section. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/dma-mapping.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 13fa536..9e7742f 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -24,15 +24,6 @@ #include #include -/* Sanity check size */ -#if (CONSISTENT_DMA_SIZE % SZ_2M) -#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" -#endif - -#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) -#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) -#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) - static u64 get_coherent_dma_mask(struct device *dev) { u64 mask = ISA_DMA_THRESHOLD; @@ -123,6 +114,15 @@ static void __dma_free_buffer(struct page *page, size_t size) } #ifdef CONFIG_MMU +/* Sanity check size */ +#if (CONSISTENT_DMA_SIZE % SZ_2M) +#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" +#endif + +#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) +#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) +#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) + /* * These are the page tables (2MB each) covering uncached, DMA consistent allocations */ -- cgit v1.1 From ca57926d53580f7c950496cb7ef6d7930610e1dd Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 21 Jun 2010 15:09:36 +0100 Subject: ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMP A recent patch for DMA cache maintenance on ARM11MPCore added a write for ownership trick to the v6_dma_inv_range() function. Such operation destroys data already present in the buffer. However, this function is used with with dma_sync_single_for_device() which is supposed to preserve the existing data transfered into the buffer. This patch adds a combination of read/write for ownership to preserve the original data. Reported-by: Ronen Shitrit Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/cache-v6.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index e46ecd8..332b48c 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -212,7 +212,8 @@ v6_dma_inv_range: #endif 1: #ifdef CONFIG_SMP - str r0, [r0] @ write for ownership + ldr r2, [r0] @ read for ownership + str r2, [r0] @ write for ownership #endif #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c6, 1 @ invalidate D line -- cgit v1.1 From ad642d9f58f1af6e96efccb5f84e52c6d01db5c4 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 21 Jun 2010 15:10:07 +0100 Subject: ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 19 +++++++++++++++++++ arch/arm/mm/cache-v6.S | 15 ++++++++++++--- 2 files changed, 31 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 346ae14..fc1b2fa 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -735,6 +735,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG Forget about fast user space cmpxchg support. It is just not possible. +config DMA_CACHE_RWFO + bool "Enable read/write for ownership DMA cache maintenance" + depends on CPU_V6 && SMP + default y + help + The Snoop Control Unit on ARM11MPCore does not detect the + cache maintenance operations and the dma_{map,unmap}_area() + functions may leave stale cache entries on other CPUs. By + enabling this option, Read or Write For Ownership in the ARMv6 + DMA cache maintenance functions is performed. These LDR/STR + instructions change the cache line state to shared or modified + so that the cache operation has the desired effect. + + Note that the workaround is only valid on processors that do + not perform speculative loads into the D-cache. For such + processors, if cache maintenance operations are not broadcast + in hardware, other workarounds are needed (e.g. cache + maintenance broadcasting in software via FIQ). + config OUTER_CACHE bool diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 332b48c..86aa689 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -211,7 +211,7 @@ v6_dma_inv_range: mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line #endif 1: -#ifdef CONFIG_SMP +#ifdef CONFIG_DMA_CACHE_RWFO ldr r2, [r0] @ read for ownership str r2, [r0] @ write for ownership #endif @@ -235,7 +235,7 @@ v6_dma_inv_range: v6_dma_clean_range: bic r0, r0, #D_CACHE_LINE_SIZE - 1 1: -#ifdef CONFIG_SMP +#ifdef CONFIG_DMA_CACHE_RWFO ldr r2, [r0] @ read for ownership #endif #ifdef HARVARD_CACHE @@ -258,7 +258,7 @@ v6_dma_clean_range: ENTRY(v6_dma_flush_range) bic r0, r0, #D_CACHE_LINE_SIZE - 1 1: -#ifdef CONFIG_SMP +#ifdef CONFIG_DMA_CACHE_RWFO ldr r2, [r0] @ read for ownership str r2, [r0] @ write for ownership #endif @@ -284,9 +284,13 @@ ENTRY(v6_dma_map_area) add r1, r1, r0 teq r2, #DMA_FROM_DEVICE beq v6_dma_inv_range +#ifndef CONFIG_DMA_CACHE_RWFO + b v6_dma_clean_range +#else teq r2, #DMA_TO_DEVICE beq v6_dma_clean_range b v6_dma_flush_range +#endif ENDPROC(v6_dma_map_area) /* @@ -296,6 +300,11 @@ ENDPROC(v6_dma_map_area) * - dir - DMA direction */ ENTRY(v6_dma_unmap_area) +#ifndef CONFIG_DMA_CACHE_RWFO + add r1, r1, r0 + teq r2, #DMA_TO_DEVICE + bne v6_dma_inv_range +#endif mov pc, lr ENDPROC(v6_dma_unmap_area) -- cgit v1.1 From cf0bb91b3ce7e42142ccea46232da19a9bbf28d5 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 21 Jun 2010 15:12:09 +0100 Subject: ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB section When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-vexpress/ct-ca9x4.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index 9b11eed..6353459 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -236,7 +237,7 @@ static void ct_ca9x4_init(void) } MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") - .phys_io = V2M_UART0, + .phys_io = V2M_UART0 & SECTION_MASK, .io_pg_offst = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .map_io = ct_ca9x4_map_io, -- cgit v1.1 From cc9897df72ddea33762f9d24ecaa2b23ef0ad1b4 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 21 Jun 2010 15:12:40 +0100 Subject: ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB section When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/realview_eb.c | 3 ++- arch/arm/mach-realview/realview_pb1176.c | 3 ++- arch/arm/mach-realview/realview_pb11mp.c | 3 ++- arch/arm/mach-realview/realview_pba8.c | 3 ++- arch/arm/mach-realview/realview_pbx.c | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 422ccd7..4425018 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -457,7 +458,7 @@ static void __init realview_eb_init(void) MACHINE_START(REALVIEW_EB, "ARM-RealView EB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .phys_io = REALVIEW_EB_UART0_BASE, + .phys_io = REALVIEW_EB_UART0_BASE & SECTION_MASK, .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 96568eb..099a1f1 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -351,7 +352,7 @@ static void __init realview_pb1176_init(void) MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .phys_io = REALVIEW_PB1176_UART0_BASE, + .phys_io = REALVIEW_PB1176_UART0_BASE & SECTION_MASK, .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .fixup = realview_pb1176_fixup, diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 7fbefbb..0e07a5c 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -373,7 +374,7 @@ static void __init realview_pb11mp_init(void) MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .phys_io = REALVIEW_PB11MP_UART0_BASE, + .phys_io = REALVIEW_PB11MP_UART0_BASE & SECTION_MASK, .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index d3c113b..ac2f06f 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -323,7 +324,7 @@ static void __init realview_pba8_init(void) MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .phys_io = REALVIEW_PBA8_UART0_BASE, + .phys_io = REALVIEW_PBA8_UART0_BASE & SECTION_MASK, .io_pg_offst = (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index a235ba3..08fd683 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -409,7 +410,7 @@ static void __init realview_pbx_init(void) MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .phys_io = REALVIEW_PBX_UART0_BASE, + .phys_io = REALVIEW_PBX_UART0_BASE & SECTION_MASK, .io_pg_offst = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x00000100, .fixup = realview_pbx_fixup, -- cgit v1.1 From 534be1d5a2da940ecc5e528992ea4ace8658157a Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 21 Jun 2010 15:29:03 +0100 Subject: ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. On an ARM11MPCore processor, loads are prioritised over stores so it is possible for a store operation to be postponed if a polling loop immediately follows it. If the variable being polled indirectly depends on the outstanding store [for example, another CPU may be polling the variable that is pending modification] then there is the potential for deadlock if interrupts are disabled. This deadlock occurs in the KGDB testsuire when executing on an SMP ARM11MPCore configuration. This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 cores, forcing a flushing of the write buffer on SMP systems before the next load takes place. If the Kernel is not compiled for SMP support, this will expand to a barrier() as before. Acked-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/processor.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 6a89567..7bed3da 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -91,7 +91,11 @@ extern void release_thread(struct task_struct *); unsigned long get_wchan(struct task_struct *p); +#if __LINUX_ARM_ARCH__ == 6 +#define cpu_relax() smp_mb() +#else #define cpu_relax() barrier() +#endif /* * Create a new kernel thread -- cgit v1.1 From 8954bb0da99b76c7ce5edf2f314807cff68b6ea8 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 21 Jun 2010 15:32:54 +0100 Subject: ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU CPU performance event counters on v7 cores will only operate if either the NIDEN or DBGEN signals are driven high. For the OMAP3 platform, these signals are driven low by default but DBGEN can be asserted by selecting the OMAP3_EMU Kconfig option, which enables the virtual clock for hardware debugging peripherals. Acked-by: Jean Pihet Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1f254bd..98922f7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -955,7 +955,8 @@ config XSCALE_PMU default y config CPU_HAS_PMU - depends on CPU_V6 || CPU_V7 || XSCALE_PMU + depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \ + (!ARCH_OMAP3 || OMAP3_EMU) default y bool -- cgit v1.1 From 2503a5ecd86c002506001eba432c524ea009fe7f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 1 Jul 2010 13:21:47 +0100 Subject: ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220 RealView boards with certain revisions of the L220 cache controller (ARM11* processors only) may have issues (hardware deadlock) with the recent changes to the mb() barrier implementation (DSB followed by an L2 cache sync). The patch redefines the RealView ARM11MPCore mandatory barriers without the outer_sync() call. Cc: Tested-by: Linus Walleij Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/Kconfig | 2 ++ arch/arm/mach-realview/include/mach/barriers.h | 8 ++++++++ 2 files changed, 10 insertions(+) create mode 100644 arch/arm/mach-realview/include/mach/barriers.h (limited to 'arch') diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index ee5e392..b4575ae 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -18,6 +18,7 @@ config REALVIEW_EB_ARM11MP bool "Support ARM11MPCore tile" depends on MACH_REALVIEW_EB select CPU_V6 + select ARCH_HAS_BARRIERS if SMP help Enable support for the ARM11MPCore tile on the Realview platform. @@ -35,6 +36,7 @@ config MACH_REALVIEW_PB11MP select CPU_V6 select ARM_GIC select HAVE_PATA_PLATFORM + select ARCH_HAS_BARRIERS if SMP help Include support for the ARM(R) RealView MPCore Platform Baseboard. PB11MPCore is a platform with an on-board ARM11MPCore and has diff --git a/arch/arm/mach-realview/include/mach/barriers.h b/arch/arm/mach-realview/include/mach/barriers.h new file mode 100644 index 0000000..0c5d749 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/barriers.h @@ -0,0 +1,8 @@ +/* + * Barriers redefined for RealView ARM11MPCore platforms with L220 cache + * controller to work around hardware errata causing the outer_sync() + * operation to deadlock the system. + */ +#define mb() dsb() +#define rmb() dmb() +#define wmb() mb() -- cgit v1.1 From 42c4dafe803dcad82980fd8b0831a89032156f93 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 1 Jul 2010 13:22:48 +0100 Subject: ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220 RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index fc1b2fa..101105e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -813,6 +813,8 @@ config ARM_L1_CACHE_SHIFT config ARM_DMA_MEM_BUFFERABLE bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7 + depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ + MACH_REALVIEW_PB11MP) default y if CPU_V6 || CPU_V7 help Historically, the kernel has used strongly ordered mappings to -- cgit v1.1 From f287d332ce835f77a4f5077d2c0ef1e3f9ea42d2 Mon Sep 17 00:00:00 2001 From: Vince Weaver Date: Thu, 1 Jul 2010 15:30:16 -0400 Subject: perf, x86: Fix incorrect branches event on AMD CPUs While doing some performance counter validation tests on some assembly language programs I noticed that the "branches:u" count was very wrong on AMD machines. It looks like the wrong event was selected. Signed-off-by: Vince Weaver Acked-by: Peter Zijlstra Cc: Paul Mackerras Cc: Arnaldo Carvalho de Melo Cc: Robert Richter Cc: Borislav Petkov Cc: Frederic Weisbecker Cc: LKML-Reference: Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c index 611df11..c2897b7 100644 --- a/arch/x86/kernel/cpu/perf_event_amd.c +++ b/arch/x86/kernel/cpu/perf_event_amd.c @@ -102,8 +102,8 @@ static const u64 amd_perfmon_event_map[] = [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, - [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, }; static u64 amd_pmu_event_map(int hw_event) -- cgit v1.1 From 446a5a8b1eb91a6990e5c8fe29f14e7a95b69132 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 2 Jul 2010 16:41:52 +0100 Subject: ARM: 6205/1: perf: ensure counter delta is treated as unsigned Hardware performance counters on ARM are 32-bits wide but atomic64_t variables are used to represent counter data in the hw_perf_event structure. The armpmu_event_update function right-shifts a signed 64-bit delta variable and adds the result to the event count. This can lead to shifting in sign-bits if the MSB of the 32-bit counter value is set. This results in perf output such as: Performance counter stats for 'sleep 20': 18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000 7783773 instructions # 0.000 IPC 465 context-switches 161 page-faults 1172393 branches 20.154242147 seconds time elapsed This patch ensures that the delta value is treated as unsigned so that the right shift sets the upper bits to zero. Cc: Acked-by: Jamie Iles Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/kernel/perf_event.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index c457686..de12536 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -201,7 +201,7 @@ armpmu_event_update(struct perf_event *event, { int shift = 64 - 32; s64 prev_raw_count, new_raw_count; - s64 delta; + u64 delta; again: prev_raw_count = atomic64_read(&hwc->prev_count); -- cgit v1.1