From ba492e900704ba00d43c7af9d94b00da4df52587 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 8 Jun 2013 22:47:17 +0800 Subject: clk: mux: add CLK_MUX_HIWORD_MASK In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner Signed-off-by: Haojian Zhuang Signed-off-by: Mike Turquette --- drivers/clk/clk-mux.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 25b1734..614444c 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -86,8 +86,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->lock) spin_lock_irqsave(mux->lock, flags); - val = readl(mux->reg); - val &= ~(mux->mask << mux->shift); + if (mux->flags & CLK_MUX_HIWORD_MASK) { + val = mux->mask << (mux->shift + 16); + } else { + val = readl(mux->reg); + val &= ~(mux->mask << mux->shift); + } val |= index << mux->shift; writel(val, mux->reg); @@ -111,6 +115,15 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, struct clk_mux *mux; struct clk *clk; struct clk_init_data init; + u8 width = 0; + + if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { + width = fls(mask) - ffs(mask) + 1; + if (width + shift > 16) { + pr_err("mux value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } /* allocate the mux */ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); -- cgit v1.1