diff options
Diffstat (limited to 'arch/arm/mach-s5pv210/include/mach')
25 files changed, 4085 insertions, 11 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/adc.h b/arch/arm/mach-s5pv210/include/mach/adc.h new file mode 100644 index 0000000..a0f703a --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/adc.h @@ -0,0 +1,36 @@ +/* arch/arm/plat-s3c/include/plat/adc.h + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simnte.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_ADC_H +#define __ASM_PLAT_ADC_H __FILE__ + +struct s3c_adc_request { + /* for linked list */ + struct list_head *list; + /* after finish ADC sampling, s3c_adc_request function call this function with three parameter */ + void (*callback)(int channel, unsigned long int param, unsigned short sample); + /* for private data */ + unsigned long int param; + /* selected channel for ADC sampling */ + int channel; +}; + +struct s3c_adc_mach_info { + /* if you need to use some platform data, add in here*/ + int delay; + int presc; + int resolution; +}; + +extern int s3c_adc_get_adc_data(int channel); +void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd); + +#endif /* __ASM_PLAT_ADC_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/battery.h b/arch/arm/mach-s5pv210/include/mach/battery.h new file mode 100644 index 0000000..b5f7339 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/battery.h @@ -0,0 +1,13 @@ +#ifndef __BATTERY_H_ +#define __BATTERY_H_ + +typedef enum +{ + PM_CHARGER_NULL, + PM_CHARGER_TA, + PM_CHARGER_USB_CABLE, //after enumeration + PM_CHARGER_USB_INSERT,// when usb is connected. + PM_CHARGER_DEFAULT +} charging_device_type; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h new file mode 100644 index 0000000..4d4469a --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h @@ -0,0 +1,54 @@ +/* arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * S5PV210/S5PC110 CPU frequency scaling support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_CPU_FREQ_H +#define __ASM_ARCH_CPU_FREQ_H + +#include <linux/cpufreq.h> + +enum perf_level { + OC0, L0, L1, L2, L3, L4, MAX_PERF_LEVEL = L4, +}; + +/* For cpu-freq driver */ +struct s5pv210_cpufreq_voltage { + unsigned int freq; /* kHz */ + unsigned long varm; /* uV */ + unsigned long vint; /* uV */ +}; + +struct s5pv210_cpufreq_data { + struct s5pv210_cpufreq_voltage *volt; + unsigned int size; +}; + +#ifdef CONFIG_DVFS_LIMIT +enum { + DVFS_LOCK_TOKEN_1 = 0, // MFC + DVFS_LOCK_TOKEN_2, // (FIMC) + DVFS_LOCK_TOKEN_3, // SND_RP + DVFS_LOCK_TOKEN_4, // (TV) + DVFS_LOCK_TOKEN_5, // (early suspend) + DVFS_LOCK_TOKEN_6, // APPS by sysfs + DVFS_LOCK_TOKEN_7, // (TOUCH) + DVFS_LOCK_TOKEN_8, // USB + DVFS_LOCK_TOKEN_9, // BT + DVFS_LOCK_TOKEN_PVR, + DVFS_LOCK_TOKEN_NUM +}; + +extern void s5pv210_lock_dvfs_high_level(uint nToken, uint perf_level); +extern void s5pv210_unlock_dvfs_high_level(unsigned int nToken); +#endif + +extern void s5pv210_cpufreq_set_platdata(struct s5pv210_cpufreq_data *pdata); + +#endif /* __ASM_ARCH_CPU_FREQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/cpuidle.h b/arch/arm/mach-s5pv210/include/mach/cpuidle.h new file mode 100644 index 0000000..7454ae4 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/cpuidle.h @@ -0,0 +1,16 @@ +/* arch/arm/mach-s5pv210/include/mach/cpuidle.h + * + * Copyright 2010 Samsung Electronics + * Jaecheol Lee <jc.lee@samsung> + * + * S5PV210 - CPUIDLE support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern int s5pv210_didle_save(unsigned long *saveblk); +extern void s5pv210_didle_resume(void); +extern void i2sdma_getpos(dma_addr_t *src); +extern unsigned int get_rtc_cnt(void); diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-aries.h b/arch/arm/mach-s5pv210/include/mach/gpio-aries.h new file mode 100644 index 0000000..c9ed133 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-aries.h @@ -0,0 +1,696 @@ +#ifndef __GPIO_HERRING_H_ +#define __GPIO_HERRING_H_ + +//#include <mach/gpio.h> + +#define S5PV210_GPE1_3_CAM_A_CLKOUT (0x2 << 12) + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 + +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 + +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 + +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 + +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 + +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 + +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 + +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 + +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 + +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 + +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) + +#define GPIO_MSENSE_nRST S5PV210_GPB(1) + +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_BT_nRST S5PV210_GPB(6) +#else +#define GPIO_BT_nRST S5PV210_GPB(3) +#endif + +#define GPIO_BOOT_MODE S5PV210_GPB(4) + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) + +#define GPIO_GPB6 S5PV210_GPB(6) + +#define GPIO_GPB7 S5PV210_GPB(7) + +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 + +#define GPIO_GPC01 S5PV210_GPC0(1) + +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 + +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 + +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 + +#define BLOW_PCM_CLK S5PV210_GPC1(0) + +#define GPIO_GPC11 S5PV210_GPC1(1) + +#define GPIO_GPC12 S5PV210_GPC1(2) + +#define GPIO_GPC13 S5PV210_GPC1(3) + +#define GPIO_GPC14 S5PV210_GPC1(4) + +#define GPIO_GPD00 S5PV210_GPD0(0) + +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) + +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) + +#define GPIO_GPD03 S5PV210_GPD0(3) + +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 + +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 + +#define GPIO_FM_SDA_28V S5PV210_GPD1(2) +#define GPIO_FM_SDA_28V_AF 2 + +#define GPIO_FM_SCL_28V S5PV210_GPD1(3) +#define GPIO_FM_SCL_28V_AF 2 + +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 + +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 + +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 + +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 + +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 + +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 + +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 + +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 + +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 + +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 + +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 + +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 + +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 + +#define GPIO_GPE14 S5PV210_GPE1(4) + +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF S3C_GPIO_SFN(2) + +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF S3C_GPIO_SFN(2) + +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF S3C_GPIO_SFN(2) + +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF S3C_GPIO_SFN(2) + +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) + +#define GPIO_GPF35 S5PV210_GPF3(5) + +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 + +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#define GPIO_ALS_SCL_28V S5PV210_GPG0(2) + +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 + +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 + +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 + +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 + +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG1(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG1(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_nRST S5PV210_GPG1(2) +#define GPIO_WLAN_nRST_AF 1 + +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG1(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG1(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG1(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG1(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_T_FLASH_CLK S5PV210_GPG2(0) +#define GPIO_T_FLASH_CLK_AF 2 + +#define GPIO_T_FLASH_CMD S5PV210_GPG2(1) +#define GPIO_T_FLASH_CMD_AF 2 + +#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) + +#define GPIO_T_FLASH_D0 S5PV210_GPG2(3) +#define GPIO_T_FLASH_D0_AF 2 + +#define GPIO_T_FLASH_D1 S5PV210_GPG2(4) +#define GPIO_T_FLASH_D1_AF 2 + +#define GPIO_T_FLASH_D2 S5PV210_GPG2(5) +#define GPIO_T_FLASH_D2_AF 2 + +#define GPIO_T_FLASH_D3 S5PV210_GPG2(6) +#define GPIO_T_FLASH_D3_AF 2 + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_GPS_nRST S5PV210_GPG3(2) +#else +#define GPIO_GPS_nRST S5PV210_GPG3(0) +#endif + +#define GPIO_GPS_PWR_EN S5PV210_GPG3(1) + +#define GPIO_GPS_CLK_INT S5PV210_GPG3(2) + +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPG3(3) + +#define GPIO_BT_WAKE S5PV210_GPG3(4) + +#define GPIO_WLAN_WAKE S5PV210_GPG3(5) +#define GPIO_WLAN_WAKE_AF 1 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) + +#define GPIO_ACC_INT S5PV210_GPH0(1) + +#define GPIO_PS_VOUT S5PV210_GPH0(2) +#define GPIO_PS_VOUT_AF 0xFF + +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) + +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) + +#define GPIO_BUCK_2_EN S5PV210_GPH0(5) + +#define GPIO_DET_35 S5PV210_GPH0(6) +#define GPIO_DET_35_AF 0xFF + +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +#if defined(CONFIG_SAMSUNG_FASCINATE) +#define GPIO_PDA_ACTIVE S5PV210_GPH1(0) +#define GPIO_PDA_ACTIVE_AF 0x1 +#else +#define GPIO_GPH10 S5PV210_GPH1(0) +#endif + +#define GPIO_GPH11 S5PV210_GPH1(1) + +#define GPIO_GPH12 S5PV210_GPH1(2) + +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF + +#define GPIO_GPH14 S5PV210_GPH1(4) + +#define GPIO_GPH15 S5PV210_GPH1(5) + +#define GPIO_GPH16 S5PV210_GPH1(6) + +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) + +#if defined(CONFIG_SAMSUNG_FASCINATE) +#define GPIO_PHONE_ACTIVE_AF 0xFF +#else +#define GPIO_PHONE_ACTIVE_AF 2 +#endif + +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 + +#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_KBC1_AF 3 + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) +#define GPIO_EAR_SEND_END35 S5PV210_GPH2(2) +#define GPIO_EAR_SEND_END35_AF 0xFF +#else +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 +#endif + +#define GPIO_GPH23 S5PV210_GPH2(3) + +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF + +#define GPIO_nPOWER S5PV210_GPH2(6) + +#define GPIO_JACK_nINT S5PV210_GPH2(7) +#define GPIO_JACK_nINT_AF 0xF + +#define GPIO_KBR0 S5PV210_GPH3(0) +#define GPIO_KBR0_AF 3 + +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 + +#define GPIO_KBR2 S5PV210_GPH3(2) +#define GPIO_KBR2_AF 3 + +#define GPIO_KBR3 S5PV210_GPH3(3) +#define GPIO_KBR3_AF 3 +#if defined (CONFIG_SAMSUNG_CAPTIVATE) +#define S5PV210_GPH3_3_EXT_INT33_3 (0xf << 12) +#endif + +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) + +#define GPIO_MSENSE_IRQ S5PV210_GPH3(5) + +#define GPIO_EAR_SEND_END S5PV210_GPH3(6) +#define GPIO_EAR_SEND_END_AF 0xFF +#define GPIO_CP_RST S5PV210_GPH3(7) + +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 + +#define GPIO_GPI1 S5PV210_GPI(1) + +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 + +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 + +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 + +#define GPIO_GPI5 S5PV210_GPI(5) + +#define GPIO_GPI6 S5PV210_GPI(6) + +#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) +#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE0 S5PV210_GPG3(6) +#else +#define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE1 S5PV210_GPJ2(0) +#else +#define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE2 S5PV210_GPJ2(1) +#else +#define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_TOUCH_INT S5PV210_GPB(3) +#else +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(7) +#else +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE3 S5PV210_GPJ2(3) +#else +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) +#endif + +#define GPIO_PHONE_ON S5PV210_GPJ1(0) + +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) + +#define GPIO_GPJ30 S5PV210_GPJ1(2) + +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#define GPIO_PS_ON S5PV210_GPJ1(4) + +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) + +#define GPIO_CAM_FLASH_EN S5PV210_GPJ2(0) + +#define GPIO_CAM_FLASH_SET S5PV210_GPJ2(1) + +#define GPIO_OLED_DET S5PV210_GPJ2(2) + +#define GPIO_CODEC_XTAL_EN S5PV210_GPJ2(3) + +#define GPIO_FM_INT S5PV210_GPJ2(4) + +#if !defined(CONFIG_SAMSUNG_VIBRANT) +#define GPIO_FM_RST S5PV210_GPJ2(5) +#else +#define GPIO_MICBIAS_EN2 S5PV210_GPJ2(5) //SGH-T959 REV0.5(HWREV = 0x0e) or 0.6 (HWREV = 0x0f) +#endif + +#define GPIO_EARPATH_SEL S5PV210_GPJ2(6) + +#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) + +#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) +#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#define _3_GPIO_TOUCH_ST_AF 1 + +#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) + +#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) + +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) + +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) + +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) + +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF S3C_GPIO_SFN(0xf) + +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) + +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) +#define GPIO_EAR_MICBIAS_EN S5PV210_GPJ4(4) +#else +#define GPIO_TV_EN S5PV210_GPJ4(4) +#endif + +#define GPIO_MP010 S5PV210_MP01(0) + +#define GPIO_DISPLAY_CS S5PV210_MP01(1) +#define GPIO_DISPLAY_CS_AF S3C_GPIO_SFN(1) + +#define GPIO_SUB_DISPLAY_CS S5PV210_MP01(2) + +#define GPIO_OLED_ID S5PV210_MP01(3) + +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 + +#define GPIO_DIC_ID S5PV210_MP01(5) + +#define GPIO_MP016 S5PV210_MP01(6) + +#define GPIO_MP017 S5PV210_MP01(7) + +#define GPIO_MP020 S5PV210_MP02(0) + +#define GPIO_MP021 S5PV210_MP02(1) + +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) + +#define GPIO_MP023 S5PV210_MP02(3) + +#define GPIO_MP030 S5PV210_MP03(0) + +#define GPIO_MP031 S5PV210_MP03(1) + +#define GPIO_MP032 S5PV210_MP03(2) + +#if !defined(CONFIG_SAMSUNG_FASCINATE) +#define GPIO_PDA_ACTIVE S5PV210_MP03(3) +#endif + +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) + +#define GPIO_CP_nRST S5PV210_MP03(5) + +#define GPIO_MP036 S5PV210_MP03(6) + +#define GPIO_PCM_SEL S5PV210_MP03(7) + +#define GPIO_USB_SEL S5PV210_MP04(0) + +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) +#define GPIO_DISPLAY_CLK_AF S3C_GPIO_SFN(1) + +#define GPIO_MP042 S5PV210_MP04(2) + +#define GPIO_DISPLAY_SI S5PV210_MP04(3) +#define GPIO_DISPLAY_SI_AF S3C_GPIO_SFN(1) + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) +#define GPIO_A1026_SCL S5PV210_MP04(4) +#define GPIO_A1026_SCL_AF 2 +#else +#define GPIO_MP044 S5PV210_MP04(4) +#endif + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) +#define GPIO_A1026_SDA S5PV210_MP04(5) +#define GPIO_A1026_SDA_AF 2 +#else +#define GPIO_LVDS_RST S5PV210_MP04(5) +#endif + +#define GPIO_GPS_CLK_EN S5PV210_MP04(6) + +#define GPIO_MHL_RST S5PV210_MP04(7) + +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) + +#define GPIO_AP_SCL_18V S5PV210_MP05(2) + +#define GPIO_AP_SDA_18V S5PV210_MP05(3) + +#define GPIO_MP054 S5PV210_MP05(4) + +#define GPIO_MLCD_RST S5PV210_MP05(5) +#define GPIO_MLCD_RST_AF S3C_GPIO_SFN(1) + +#define GPIO_MP056 S5PV210_MP05(6) + +#define GPIO_UART_SEL S5PV210_MP05(7) + +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_TOUCH_INT S5PV210_GPB(3) +#else +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#endif +#define GPIO_TOUCH_INT_AF 0xFF + +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 + +/* uart 0~3 */ +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 + +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_BT_RST S5PV210_GPB(6) +#else +#define GPIO_BT_RST S5PV210_GPB(3) +#endif + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) +#define GPIO_WLAN_RST S5PV210_GPG1(2) + +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#endif +/* end of __GPIO_HERRING_H_ */ diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-herring.h b/arch/arm/mach-s5pv210/include/mach/gpio-herring.h new file mode 100644 index 0000000..b55d0f0 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-herring.h @@ -0,0 +1,603 @@ +#ifndef __GPIO_HERRING_H_ +#define __GPIO_HERRING_H_ + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 + +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 + +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 + +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 + +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 + +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 + +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 + +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 + +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 + +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 + +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) + +#define GPIO_MSENSE_nRST S5PV210_GPB(1) + +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) + +#define GPIO_BT_nRST S5PV210_GPB(3) + +#define GPIO_BOOT_MODE S5PV210_GPB(4) + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) + +#define GPIO_GPB6 S5PV210_GPB(6) + +#define GPIO_GPB7 S5PV210_GPB(7) + +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 + +#define GPIO_GPC01 S5PV210_GPC0(1) + +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 + +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 + +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 + +#define GPIO_WIMAX_PM_SDA S5PV210_GPC1(0) + +#define GPIO_WIMAX_I2C_CON S5PV210_GPC1(1) + +#define GPIO_WIMAX_PM_SCL S5PV210_GPC1(2) + +#define GPIO_GPC13 S5PV210_GPC1(3) + +#define GPIO_GPC14 S5PV210_GPC1(4) + +#define GPIO_WIMAX_DBGEN_28V S5PV210_GPD0(0) + +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) + +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) + +#define GPIO_WIMAX_RESET_N S5PV210_GPD0(3) + +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 + +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 + +#define GYRO_SDA_28V S5PV210_GPD1(2) +#define GYRO_SCL_28V S5PV210_GPD1(3) + +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 + +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 + +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 + +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 + +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 + +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 + +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 + +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 + +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 + +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 + +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 + +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 + +#define GPIO_GPE14 S5PV210_GPE1(4) + +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF 2 + +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF 2 + +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF 2 + +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF 2 + +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF 2 + +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF 2 + +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF 2 + +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF 2 + +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF 2 + +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF 2 + +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF 2 + +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF 2 + +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF 2 + +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF 2 + +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF 2 + +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF 2 + +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF 2 + +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF 2 + +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF 2 + +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF 2 + +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF 2 + +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF 2 + +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF 2 + +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF 2 + +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF 2 + +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF 2 + +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF 2 + +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF 2 + +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) + +#define GPIO_GPF35 S5PV210_GPF3(5) + +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 + +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#define GPIO_ALS_SCL_28V S5PV210_GPG0(2) + +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 + +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 + +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 + +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 + +#define GPIO_GPS_nRST S5PV210_GPG1(0) + +#define GPIO_GPS_PWR_EN S5PV210_GPG1(1) + +#define GPIO_WLAN_RST S5PV210_GPG1(2) + +#define GPIO_NAND_D4 S5PV210_GPG1(3) +#define GPIO_NAND_D4_AF 3 + +#define GPIO_NAND_D5 S5PV210_GPG1(4) +#define GPIO_NAND_D5_AF 3 + +#define GPIO_NAND_D6 S5PV210_GPG1(5) +#define GPIO_NAND_D6_AF 3 + +#define GPIO_NAND_D7 S5PV210_GPG1(6) +#define GPIO_NAND_D7_AF 3 + +#define GPIO_WIMAX_SDIO_CLK S5PV210_GPG2(0) + +#define GPIO_WIMAX_SDIO_CMD S5PV210_GPG2(1) + +#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) + +#define GPIO_WIMAX_SDIO_D0 S5PV210_GPG2(3) + +#define GPIO_WIMAX_SDIO_D1 S5PV210_GPG2(4) + +#define GPIO_WIMAX_SDIO_D2 S5PV210_GPG2(5) + +#define GPIO_WIMAX_SDIO_D3 S5PV210_GPG2(6) + +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_nRST S5PV210_GPG3(2) +#define GPIO_WLAN_nRST_AF 1 + +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) + +#define GPIO_ACC_INT S5PV210_GPH0(1) + +#define GPIO_PS_VOUT S5PV210_GPH0(2) +#define GPIO_PS_VOUT_AF 0xFF + +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) + +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) + +#define GPIO_BUCK_2_EN S5PV210_GPH0(5) +#define GPIO_DET_35 S5PV210_GPH0(6) +#define GPIO_DET_35_AF 0xFF + +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +#define GPIO_WIMAX_EN S5PV210_GPH1(0) + +#define GPIO_PDA_ACTIVE S5PV210_GPH1(1) + +#define GPIO_WIMAX_WAKEUP S5PV210_GPH1(2) + +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF + +#define GPIO_GPH14 S5PV210_GPH1(4) + +#define GPIO_GPH15 S5PV210_GPH1(5) + +#define GPIO_GPH16 S5PV210_GPH1(6) + +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) +#define GPIO_PHONE_ACTIVE_AF 2 + +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 +#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_KBC1_AF 3 +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 + +#define GPIO_BT_WAKE S5PV210_GPH2(2) +#define GPIO_WLAN_WAKE S5PV210_GPH2(3) +#define GPIO_WLAN_WAKE_AF 1 + +#define GPIO_KBC_DATA (GPIO_KBC2 + 0x04) + +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF + +#define GPIO_nPOWER S5PV210_GPH2(6) + +#define GPIO_JACK_nINT S5PV210_GPH2(7) + +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPH3(0) + +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 + +#define GPIO_KBR2 S5PV210_GPH3(2) +#define GPIO_KBR2_AF 3 + +#define GPIO_MSENSE_IRQ S5PV210_GPH3(3) + +#define GPIO_KBR_DATA (GPIO_KBR1 + 0x04) + +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) + +/* EAR_SEN_END_OPEN */ +#define GPIO_OK_KEY S5PV210_GPH3(5) + +#define GPIO_EAR_SEND_END S5PV210_GPH3(6) +#define GPIO_EAR_SEND_END_AF 0xFF +#define GPIO_CP_RST S5PV210_GPH3(7) + +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 + +#define GPIO_GPI1 S5PV210_GPI(1) + +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 + +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 + +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 + +#define GPIO_GPI5 S5PV210_GPI(5) + +#define GPIO_GPI6 S5PV210_GPI(6) + +#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) +#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) + +#define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) +#define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) +#define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) + +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) + +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) + +#define GPIO_CAM_FLASH_EN_SET S5PV210_GPJ1(0) + +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) + +#define GPIO_USB_HS_SEL S5PV210_GPJ2(0) +#define GPIO_PHONE_ON S5PV210_GPJ2(1) + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_UART_SEL1 S5PV210_GPJ2(4) + +#define GPIO_FLASH_EN S5PV210_GPJ1(2) +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#define GPIO_PS_ON S5PV210_GPJ1(4) + +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) + +#define GPIO_OLED_DET S5PV210_GPJ2(2) + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_FM_INT S5PV210_GPJ2(4) +#define GPIO_FM_RST S5PV210_GPJ2(5) +#define GPIO_TV_OUT_SEL S5PV210_GPJ2(6) + +#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) + +#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) +#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 +#define GPIO_EAR_ADC_SEL S5PV210_GPJ3(3) +#define GPIO_EAR_ADC_SEL_AF 1 + +#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) + +#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) + +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) + +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) + +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF 0xFF +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) + +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) + +#define GPIO_EAR_MICBIAS_EN S5PV210_GPJ4(4) + +#define GPIO_MP010 S5PV210_MP01(0) + +#define GPIO_DISPLAY_CS S5PV210_MP01(1) + +#define GPIO_WIMAX_CON0 S5PV210_MP01(2) + +#define GPIO_OLED_ID S5PV210_MP01(3) + +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 + +#define GPIO_DIC_ID S5PV210_MP01(5) + +#define GPIO_MP016 S5PV210_MP01(6) + +#define GPIO_MP017 S5PV210_MP01(7) + +#define GPIO_MP020 S5PV210_MP02(0) + +#define GPIO_MP021 S5PV210_MP02(1) + +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) + +#define GPIO_MP023 S5PV210_MP02(3) + +#define GPIO_MP030 S5PV210_MP03(0) + +#define GPIO_MP031 S5PV210_MP03(1) + +#define GPIO_MP032 S5PV210_MP03(2) + +#define GPIO_MP033 S5PV210_MP03(3) + +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) + +#define GPIO_CP_nRST S5PV210_MP03(5) + +#define GPIO_MP036 S5PV210_MP03(6) + +#define GPIO_PCM_SEL S5PV210_MP03(7) + +#define GPIO_USB_SEL S5PV210_MP04(0) + +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) + +#define GPIO_WIMAX_IF_MODE0 S5PV210_MP04(2) + +#define GPIO_DISPLAY_SI S5PV210_MP04(3) + +#define GPIO_MP044 S5PV210_MP04(4) + +#define GPIO_LVDS_RST S5PV210_MP04(5) + +#define GPIO_GPS_CLK_EN S5PV210_MP04(6) + +#define GPIO_WIMAX_CON1 S5PV210_MP04(7) + +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) + +#define GPIO_AP_SCL_18V S5PV210_MP05(2) + +#define GPIO_AP_SDA_18V S5PV210_MP05(3) + +#define GPIO_WIMAX_IF_MODE1 S5PV210_MP05(4) + +#define GPIO_MLCD_RST S5PV210_MP05(5) + +#define GPIO_WIMAX_CON2 S5PV210_MP05(6) + +#define GPIO_UART_SEL S5PV210_MP05(7) + +#define GPOI_WIMAX_WAKEUP S5PV210_MP06(5) + +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +#define NFC_SCL_18V S5PV210_MP04(4) +#define NFC_SDA_18V S5PV210_MP04(5) +#define NFC_IRQ S5PV210_GPH1(4) +#define NFC_EN S5PV210_GPH1(5) +#define NFC_FIRM S5PV210_GPH1(6) + +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#define GPIO_TOUCH_INT_AF 0xFF + +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 + +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 + +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 + +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#endif +/* end of __GPIO_HERRING_H_ */ + diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-p1.h b/arch/arm/mach-s5pv210/include/mach/gpio-p1.h new file mode 100644 index 0000000..f36cfc7 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-p1.h @@ -0,0 +1,633 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/gpio-p1.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef __GPIO_P1_H_ +#define __GPIO_P1_H_ + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 + +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 + +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 + +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 + +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 + +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 + +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 + +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 + +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 + +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 + +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) + +#define GPIO_MSENSE_nRST S5PV210_GPB(1) + +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) + +#define GPIO_BT_nRST S5PV210_GPB(3) + +#define GPIO_BOOT_MODE S5PV210_GPB(4) + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) + +#define GPIO_GPB6 S5PV210_GPB(6) + +#define GPIO_GPB7 S5PV210_GPB(7) + +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 + +#define GPIO_GPC01 S5PV210_GPC0(1) + +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 + +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 + +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 + +#define BLOW_PCM_CLK S5PV210_GPC1(0) + +#define GPIO_GPC11 S5PV210_GPC1(1) + +#define GPIO_GPC12 S5PV210_GPC1(2) + +#define GPIO_GPC13 S5PV210_GPC1(3) + +#define GPIO_GPC14 S5PV210_GPC1(4) + +// CMC623 +#define GPIO_CMC_SLEEP S5PV210_GPC1(0) +#define GPIO_CMC_SLEEP_AF 2 +#define GPIO_CMC_EN S5PV210_GPC1(1) +#define GPIO_CMC_EN_AF 2 +#define GPIO_CMC_RST S5PV210_GPC1(2) +#define GPIO_CMC_RST_AF 2 +#define GPIO_CMC_SHDN S5PV210_GPC1(3) +#define GPIO_CMC_SHDN_AF 2 +#define GPIO_CMC_BYPASS S5PV210_GPC1(4) +#define GPIO_CMC_BYPASS_AF 2 + +#define GPIO_GPD00 S5PV210_GPD0(0) + +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) + +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) + +#define GPIO_GPD03 S5PV210_GPD0(3) + +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 + +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 + +#define GYRO_SDA_28V S5PV210_GPD1(2) +#define GYRO_SCL_28V S5PV210_GPD1(3) + +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 + +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 + +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 + +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 + +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 + +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 + +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 + +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 + +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 + +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 + +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 + +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 + +#define GPIO_GPE14 S5PV210_GPE1(4) + +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF 2 + +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF 2 + +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF 2 + +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF 2 + +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF 2 + +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF 2 + +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF 2 + +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF 2 + +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF 2 + +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF 2 + +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF 2 + +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF 2 + +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF 2 + +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF 2 + +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF 2 + +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF 2 + +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF 2 + +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF 2 + +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF 2 + +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF 2 + +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF 2 + +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF 2 + +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF 2 + +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF 2 + +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF 2 + +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF 2 + +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF 2 + +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF 2 + +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) + +#define GPIO_GPF35 S5PV210_GPF3(5) + +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 + +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#define GPIO_ALS_SCL_28V S5PV210_GPG0(2) + +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 + +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 + +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 + +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 + +#define GPIO_GPS_nRST S5PV210_GPG1(0) + +#define GPIO_GPS_PWR_EN S5PV210_GPG1(1) + +#define GPIO_WLAN_RST S5PV210_GPG1(2) + +#define GPIO_NAND_D4 S5PV210_GPG1(3) +#define GPIO_NAND_D4_AF 3 + +#define GPIO_NAND_D5 S5PV210_GPG1(4) +#define GPIO_NAND_D5_AF 3 + +#define GPIO_NAND_D6 S5PV210_GPG1(5) +#define GPIO_NAND_D6_AF 3 + +#define GPIO_NAND_D7 S5PV210_GPG1(6) +#define GPIO_NAND_D7_AF 3 + +#define GPIO_T_FLASH_CLK S5PV210_GPG2(0) +#define GPIO_T_FLASH_CLK_AF 2 + +#define GPIO_T_FLASH_CMD S5PV210_GPG2(1) +#define GPIO_T_FLASH_CMD_AF 2 + +#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) + +#define GPIO_T_FLASH_D0 S5PV210_GPG2(3) +#define GPIO_T_FLASH_D0_AF 2 + +#define GPIO_T_FLASH_D1 S5PV210_GPG2(4) +#define GPIO_T_FLASH_D1_AF 2 + +#define GPIO_T_FLASH_D2 S5PV210_GPG2(5) +#define GPIO_T_FLASH_D2_AF 2 + +#define GPIO_T_FLASH_D3 S5PV210_GPG2(6) +#define GPIO_T_FLASH_D3_AF 2 + +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_nRST S5PV210_GPG3(2) +#define GPIO_WLAN_nRST_AF 1 + +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) + +#define GPIO_ACC_INT S5PV210_GPH0(1) + +#define GPIO_PS_VOUT S5PV210_GPH0(2) +#define GPIO_PS_VOUT_AF 0xFF + +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) + +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) + +#define GPIO_BUCK_2_EN S5PV210_GPH0(5) + +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +#define GPIO_GPH10 S5PV210_GPH1(0) +#define GPIO_DET_35 S5PV210_GPH1(0) +#define GPIO_DET_35_AF 0xF + +#define GPIO_PDA_ACTIVE S5PV210_GPH1(1) + +#define GPIO_GPH12 S5PV210_GPH1(2) +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF + +#define GPIO_GPH14 S5PV210_GPH1(4) +#define GPIO_EAR_SEND_END S5PV210_GPH1(4) +#define GPIO_EAR_SEND_END_AF 0xF + +#define GPIO_GPH15 S5PV210_GPH1(5) + +#define GPIO_GPH16 S5PV210_GPH1(6) + +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) +#define GPIO_PHONE_ACTIVE_AF 2 + +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 +#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_KBC1_AF 3 +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 + +#define GPIO_BT_WAKE S5PV210_GPH2(2) +#define GPIO_WLAN_WAKE S5PV210_GPH2(3) +#define GPIO_WLAN_WAKE_AF 1 + +#define GPIO_KBC_DATA (GPIO_KBC2 + 0x04) + +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF + +#define GPIO_nPOWER S5PV210_GPH2(6) + +#define GPIO_JACK_nINT S5PV210_GPH2(7) + +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPH3(0) + +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 + +#define GPIO_MSENSE_IRQ S5PV210_GPH3(2) + +#define GPIO_SIM_nDETECT S5PV210_GPH3(3) + +#define GPIO_KBR_DATA (GPIO_KBR1 + 0x04) + +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) +#define GPIO_T_FLASH_DETECT_AF 0xF + +/* EAR_SEN_END_OPEN */ +#define GPIO_OK_KEY S5PV210_GPH3(5) + +#define GPIO_CP_RST S5PV210_GPH3(7) + +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 + +#define GPIO_GPI1 S5PV210_GPI(1) + +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 + +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 + +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 + +#define GPIO_GPI5 S5PV210_GPI(5) + +#define GPIO_GPI6 S5PV210_GPI(6) + +#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) +#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) + +#define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) +#define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) +#define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) + +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) + +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) + +#define GPIO_CAM_FLASH_EN_SET S5PV210_GPJ1(0) + +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) +#define GPIO_MASSMEMORY_EN S5PV210_GPJ1(1) // Rev0.6 + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) + +#define GPIO_FLASH_EN S5PV210_GPJ1(2) +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#define GPIO_PS_ON S5PV210_GPJ1(4) + +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) + +#define GPIO_OLED_DET S5PV210_GPJ2(2) +#define GPIO_USB_SW_SCL S5PV210_GPJ2(3) + +//#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_FM_INT S5PV210_GPJ2(4) +#define GPIO_FM_RST S5PV210_GPJ2(5) +#define GPIO_LCD_LDO_EN S5PV210_GPJ2(6) + +//#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) +#define GPIO_USB_SW_SDA S5PV210_GPJ2(7) + +#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) +#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 +#define GPIO_EAR_ADC_SEL S5PV210_GPJ3(3) +#define GPIO_EAR_ADC_SEL_AF 1 + +#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) + +#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) + +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) + +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) + +#define GPIO_MASSMEMORY_EN2_REV06 S5PV210_GPJ4(1) // Rev0.6 + +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF 0xFF +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) + +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) + +#define GPIO_MP010 S5PV210_MP01(0) + +#define GPIO_DISPLAY_CS S5PV210_MP01(1) + +#define GPIO_RESET_REQ_N S5PV210_MP01(2) + +#define GPIO_OLED_ID S5PV210_MP01(3) + +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 + +#define GPIO_DIC_ID S5PV210_MP01(5) + +#define GPIO_EAR_MICBIAS_EN S5PV210_MP01(5) + +#define GPIO_MP016 S5PV210_MP01(6) + +#define GPIO_MP017 S5PV210_MP01(7) + +#define GPIO_MP020 S5PV210_MP02(0) + +#define GPIO_MP021 S5PV210_MP02(1) + +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) + +#define GPIO_MP023 S5PV210_MP02(3) + +#define GPIO_MP030 S5PV210_MP03(0) + +#define GPIO_MP031 S5PV210_MP03(1) + +#define GPIO_MP032 S5PV210_MP03(2) + +#define GPIO_MP033 S5PV210_MP03(3) + +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) + +#define GPIO_CP_nRST S5PV210_MP03(5) + +#define GPIO_MP036 S5PV210_MP03(6) + +#define GPIO_PCM_SEL S5PV210_MP03(7) + +#define GPIO_USB_SEL S5PV210_MP04(0) + +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) + +#define GPIO_MP042 S5PV210_MP04(2) + +#define GPIO_DISPLAY_SI S5PV210_MP04(3) + +#define GPIO_MP044 S5PV210_MP04(4) + +#define GPIO_CMC_SDA_18V S5PV210_MP04(5) // Rev0.9 +#define GPIO_LVDS_RST S5PV210_MP04(5) + +#define GPIO_GPS_CLK_EN S5PV210_MP04(6) +#define GPIO_CMC_SCL_18V S5PV210_MP04(6) // Rev1.2 + +#define GPIO_MHL_RST S5PV210_MP04(7) + +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) + +#define GPIO_EAR_MICBIAS0_EN S5PV210_MP05(1) + +#define GPIO_AP_SCL_18V S5PV210_MP05(2) + +#define GPIO_AP_SDA_18V S5PV210_MP05(3) + +#define GPIO_MP054 S5PV210_MP05(4) +#define GPIO_LVDS_SHDN S5PV210_MP05(4) + +#define GPIO_MLCD_RST S5PV210_MP05(5) + +#define GPIO_MP056 S5PV210_MP05(6) + +#define GPIO_UART_SEL S5PV210_MP05(7) + +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +#define NFC_SCL_18V S5PV210_MP04(4) +#define NFC_SDA_18V S5PV210_MP04(5) +#define NFC_IRQ S5PV210_GPH1(4) +#define NFC_EN S5PV210_GPH1(5) +#define NFC_FIRM S5PV210_GPH1(6) + +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#define GPIO_TOUCH_INT_AF 0xFF + +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 + +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 + +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 + +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#endif +/* end of __GPIO_P1_H_ */ + diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-settings.h b/arch/arm/mach-s5pv210/include/mach/gpio-settings.h new file mode 100644 index 0000000..e8f8fee --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-settings.h @@ -0,0 +1,898 @@ +#ifndef __GPIO_SETTINGS_H_ +#define __GPIO_SETTINGS_H_ + +#define S3C_GPIO_SETPIN_ZERO 0 +#define S3C_GPIO_SETPIN_ONE 1 +#define S3C_GPIO_SETPIN_NONE 2 + +#define S3C_GPIO_EINT S3C_GPIO_SPECIAL(0xF) + +// GPIO Initialization table +// {pin number, pin conf, pin value, pullup/down config} +static unsigned int initial_gpio_table[][4] = +{ + // GPA0 -------------------------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) // Modify NTT S1 + {S5PV210_GPA0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + // GPA1 -------------------------------------------------------------------- + + // GPA1 -------------------------------------------------------------------- + + // GPB --------------------------------------------------------------------- + {S5PV210_GPB(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPB(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPB(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPB(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPB(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPB(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPB(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPC0 -------------------------------------------------------------------- + {S5PV210_GPC0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPC1 -------------------------------------------------------------------- + {S5PV210_GPC1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPD0 -------------------------------------------------------------------- + {S5PV210_GPD0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD0(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPD1 -------------------------------------------------------------------- + {S5PV210_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + // GPE0 -------------------------------------------------------------------- + {S5PV210_GPE0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPE1 -------------------------------------------------------------------- + {S5PV210_GPE1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPE1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPE1(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPE1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPF0 -------------------------------------------------------------------- + + // GPF1 -------------------------------------------------------------------- + + // GPF2 -------------------------------------------------------------------- + + // GPF3 -------------------------------------------------------------------- + {S5PV210_GPF3(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG0 -------------------------------------------------------------------- + {S5PV210_GPG0(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG1 -------------------------------------------------------------------- + {S5PV210_GPG1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG2 -------------------------------------------------------------------- + {S5PV210_GPG2(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG3 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPG3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPG3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPH0 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH0(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(7), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + + // GPH1 -------------------------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPH1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(7), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + + // GPH2 -------------------------------------------------------------------- + {S5PV210_GPH2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH2(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, +#else + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH2(5), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH2(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + + // GPH3 -------------------------------------------------------------------- + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH3(1), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH3(2), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(3), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH3(5), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH3(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + + // GPI --------------------------------------------------------------------- + {S5PV210_GPI(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPJ0 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(5), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#else + {S5PV210_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPJ0(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + // GPJ1 -------------------------------------------------------------------- + {S5PV210_GPJ1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ1(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPJ2 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPJ2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, +#endif +#if defined(CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPJ2(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ2(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPJ3 -------------------------------------------------------------------- + {S5PV210_GPJ3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ3(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + // GPJ4 -------------------------------------------------------------------- + {S5PV210_GPJ4(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(1), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ4(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#else + {S5PV210_GPJ4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + + // MP01 -------------------------------------------------------------------- + {S5PV210_MP01(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP01(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP02 -------------------------------------------------------------------- + {S5PV210_MP02(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP02(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP02(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP03 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_MP03(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_MP03(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_ARIES_NTT) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_MP03(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_MP03(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP03(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP04 -------------------------------------------------------------------- + {S5PV210_MP04(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_MP04(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_MP04(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP04(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP05 -------------------------------------------------------------------- + {S5PV210_MP05(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP05(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +}; + +// off part GPIO Sleep Control table +// {pin number, sleep mode conf, sleep pullup/down config} +static unsigned int sleep_gpio_table[][3] = +{ + // GPA0 ------------------------------------------------- + {S5PV210_GPA0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_RXD + {S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_TXD + {S5PV210_GPA0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_CTS + {S5PV210_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_RTS +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA04 + {S5PV210_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA05 + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA06 + {S5PV210_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA07 +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPA0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + {S5PV210_GPA0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + + // GPA1 ------------------------------------------------- + {S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_AP_RXD + {S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_AP_TXD +#if defined(CONFIG_ARIES_NTT) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_AP_FLM_RXD +#else + {S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_FLM_RXD +#endif + {S5PV210_GPA1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_AP_FLM_TXD + + // GPB ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) || defined (CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VGA_nSTBY + {S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MSENSE_nRST + {S5PV210_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VGA_nRST +#else + {S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_nRST + {S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_BOOT_MODE + {S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_BT_EN + {S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPB6 + {S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPB7 (CAM_IO_EN) + + // GPC0 ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC00 + {S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC01 + {S5PV210_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC02 + {S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC03 + {S5PV210_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC04 +#else + {S5PV210_GPC0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPC1 ------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPC1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPC10 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC10 +#endif + {S5PV210_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC11 +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPC1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPC12 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC12 +#endif + {S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC13 + {S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC14 + + // GPD0 ------------------------------------------------- + {S5PV210_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD00 + {S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_VIBTONE_PWM + {S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD02 + {S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD03 + + // GPD1 ------------------------------------------------- + {S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_SDA_29V + {S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_SCL_29V +#if defined(CONFIG_ARIES_NTT) || defined (CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD12 + {S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD13 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_TSP_SDA_28V + {S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_TSP_SCL_28V + + // GPE0 ------------------------------------------------- + {S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_PCLK + {S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VSYNC + {S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_HSYNC + {S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D0 + {S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D1 + {S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D2 + {S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D3 + {S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D4 + + // GPE1 ------------------------------------------------- + {S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D5 + {S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D6 + {S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D7 + {S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_CAM_MCLK + {S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPE14 + + // GPF0 ------------------------------------------------- + {S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_HSYNC + {S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_VSYNC + {S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_DE + {S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_PCLK + {S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D0 + {S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D1 + {S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D2 + {S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D3 + + // GPF1 ------------------------------------------------- + {S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D4 + {S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D5 + {S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D6 + {S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D7 + {S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D8 + {S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D9 + {S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D10 + {S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D11 + + // GPF2 ------------------------------------------------- + {S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D12 + {S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D13 + {S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D14 + {S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D15 + {S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D16 + {S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D17 + {S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D18 + {S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D19 + + // GPF3 ------------------------------------------------- + {S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D20 + {S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D21 + {S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D22 + {S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D23 + {S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_LDO_EN + {S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPF35 + + // GPG0 ------------------------------------------------- + {S5PV210_GPG0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_CLK +#if defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_CMD +#else + {S5PV210_GPG0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_CMD +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // GPIO_ALS_SCL_28V +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, // GPIO_ALS_SCL_28V +#endif +#if defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D0 + {S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D1 + {S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D2 + {S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D3 +#else + {S5PV210_GPG0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D0 + {S5PV210_GPG0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D1 + {S5PV210_GPG0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D2 + {S5PV210_GPG0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D3 +#endif + + // GPG1 ------------------------------------------------- + {S5PV210_GPG1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_CLK + {S5PV210_GPG1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_CMD + {S5PV210_GPG1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_nRST + {S5PV210_GPG1(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D0 + {S5PV210_GPG1(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D1 + {S5PV210_GPG1(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D2 + {S5PV210_GPG1(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D3 + + // GPG2 ------------------------------------------------- + {S5PV210_GPG2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CLK +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG2(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CMD +#else + {S5PV210_GPG2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CMD +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_ALS_SDA_28V +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_ALS_SDA_28V +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D0 + {S5PV210_GPG2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D1 + {S5PV210_GPG2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D2 + {S5PV210_GPG2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D3 +#else + {S5PV210_GPG2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D0 + {S5PV210_GPG2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D1 + {S5PV210_GPG2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D2 + {S5PV210_GPG2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D3 +#endif + + // GPG3 ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPG3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPG30 + {S5PV210_GPG3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPG31 +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPG3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + {S5PV210_GPG3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, +#else //CONFIG_SAMSUNG_CAPTIVATE CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPG3(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPG3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_TA_CURRENT_SEL_AP +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, //GPIO_TA_CURRENT_SEL_AP +#endif + {S5PV210_GPG3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_BT_WAKE + {S5PV210_GPG3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_WAKE +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPG3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPG36 +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPG36 +#else //CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPG36 +#endif + + // GPI -------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPI(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I2S_CLK +#else + {S5PV210_GPI(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I2S_CLK +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI1 +#else //CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI1 +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPI(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I2S_WS + {S5PV210_GPI(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I3S_DI + {S5PV210_GPI(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I3S_DO +#else + {S5PV210_GPI(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I2S_WS + {S5PV210_GPI(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I3S_DI + {S5PV210_GPI(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I3S_DO +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI5 + {S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI6 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI5 + {S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI6 +#endif + + // GPJ0 ------------------------------------------------- + {S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MSENSE_SCL_28V + {S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MSENSE_SDA_28V + {S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE0 + {S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE1 + {S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE2 + {S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_TOUCH_INT + {S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_CAM_MEGA_EN + {S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE3 + + // GPJ1 ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) || defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_PHONE_ON +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_VIBTONE_EN1 + {S5PV210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ12 + {S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_TOUCH_EN +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPJ1(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_PS_ON +#else + {S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_CAM_MEGA_nRST + + // GPJ2 ------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ20 + {S5PV210_GPJ2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ21 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ20 + {S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ21 +#endif + {S5PV210_GPJ2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_OLED_DET +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_USIM_BOOT + {S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, //NC + {S5PV210_GPJ2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //NC + {S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //NC + {S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_SUB_MICBIAS_EN +#else //CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_EARPATH_SEL + {S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MASSMEMORY_EN +#else + {S5PV210_GPJ2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_EARPATH_SEL + {S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_MASSMEMORY_EN +#endif + + // GPJ3 ------------------------------------------------- + {S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_TOUCH_SDA_28V + {S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_TOUCH_SCL_28V + {S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //_3_GPIO_TOUCH_EN +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ33 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPJ3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ33 +#endif + {S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_USB_SDA_28V + {S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_USB_SCL_28V + {S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SDA_28V + {S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SCL_28V + + // GPJ4 ------------------------------------------------- + {S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_PMIC_SDA + {S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_GPIO_TOUCH_INT + {S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_MICBIAS_EN + {S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_PMIC_SCL +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_EARMICBIAS_EN +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPJ4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ44 +#endif + + // MP01 ------------------------------------------------- + {S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP010 + {S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_CS + {S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP012 + {S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_OLED_ID + {S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_AP_NANDCS + {S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_DIC_ID + {S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP016 + {S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP017 + + // MP02 ------------------------------------------------- + {S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP020 + {S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP021 + {S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP022 + {S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP023 + + // MP03 ------------------------------------------------- + {S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP030 + {S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP031 +#if defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_MP03(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //NC +#else //CONFIG_SAMSUNG_CAPTIVATE CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MP032 +#endif + {S5PV210_MP03(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_PDA_ACTIVE + {S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP04 +#if defined(CONFIG_ARIES_NTT) + {S5PV210_MP03(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP035 +#else + {S5PV210_MP03(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP036 + {S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP037 + + // MP04 ------------------------------------------------- + {S5PV210_MP04(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP040 + {S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_CLK + {S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP042 + {S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_SI +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP044 + {S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP045 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP044 + {S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP045 +#endif +#if defined(CONFIG_ARIES_NTT) + {S5PV210_MP04(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP046 +#else + {S5PV210_MP04(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP04(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP047 + + // MP05 ------------------------------------------------- + {S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //FUEL_SCL_18V + {S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //FUEL_SDA_18V + {S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SCL_18V + {S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SDA_18V + {S5PV210_MP05(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP054 + {S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_MLCD_RST + {S5PV210_MP05(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP056 + {S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_UART_SEL + + // MP06 ------------------------------------------------- + {S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // MP07 ------------------------------------------------- + {S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +}; + + + +// alive part GPIO Sleep Control table +// {pin number, sleep mode conf, sleep pin value, sleep pullup/down config} +static unsigned int sleep_alive_gpio_table[][4] = +{ +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN},//GPIO_ACC_INT +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //pwr hold + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH0(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_BUCK_1_EN_A + {S5PV210_GPH0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_BUCK_1_EN_B + {S5PV210_GPH0(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_BUCK_2_EN + +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_AP_PMIC_IRQ + {S5PV210_GPH1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_AP_PMIC_IRQ //cross check + {S5PV210_GPH1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH11 + {S5PV210_GPH1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH11 + +#if defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH1(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_GPH14 +#else + {S5PV210_GPH1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH14 +#endif + {S5PV210_GPH1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH15 + {S5PV210_GPH1(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH16 +#if defined(CONFIG_ARIES_NTT) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH17 +#else + {S5PV210_GPH1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + {S5PV210_GPH2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH20 + {S5PV210_GPH2(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_KBC1 + {S5PV210_GPH2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_KBC2 +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, //GPIO_PHONE_ACTIVE +#else + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_nPOWER + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR0 + {S5PV210_GPH3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR1 + {S5PV210_GPH3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR2 +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH2(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR0 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_KBR0 +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR3 +#else + {S5PV210_GPH3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_KBR3 +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(4), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR4 +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_OK_KEY + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_UP}, //GPIO_CP_RST +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_OK_KEY + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_NONE}, //GPIO_CP_RST +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_NONE}, //GPIO_CP_RST +#endif +}; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index a5a1e33..16b38f1 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -54,6 +54,34 @@ #define S5PV210_GPIO_MP03_NR (8) #define S5PV210_GPIO_MP04_NR (8) #define S5PV210_GPIO_MP05_NR (8) +#define S5PV210_GPIO_MP06_NR (8) +#define S5PV210_GPIO_MP07_NR (8) + +#define S5PV210_GPIO_MP10_NR (8) +#define S5PV210_GPIO_MP11_NR (8) +#define S5PV210_GPIO_MP12_NR (8) +#define S5PV210_GPIO_MP13_NR (8) +#define S5PV210_GPIO_MP14_NR (8) +#define S5PV210_GPIO_MP15_NR (8) +#define S5PV210_GPIO_MP16_NR (8) +#define S5PV210_GPIO_MP17_NR (8) +#define S5PV210_GPIO_MP18_NR (7) + +#define S5PV210_GPIO_MP20_NR (8) +#define S5PV210_GPIO_MP21_NR (8) +#define S5PV210_GPIO_MP22_NR (8) +#define S5PV210_GPIO_MP23_NR (8) +#define S5PV210_GPIO_MP24_NR (8) +#define S5PV210_GPIO_MP25_NR (8) +#define S5PV210_GPIO_MP26_NR (8) +#define S5PV210_GPIO_MP27_NR (8) +#define S5PV210_GPIO_MP28_NR (7) + +#define S5PV210_GPIO_ETC0_NR (6) +#define S5PV210_GPIO_ETC1_NR (8) +#define S5PV210_GPIO_ETC2_NR (8) +#define S5PV210_GPIO_ETC4_NR (6) + /* GPIO bank numbers */ @@ -98,6 +126,30 @@ enum s5p_gpio_number { S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03), S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04), + S5PV210_GPIO_MP06_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP05), + S5PV210_GPIO_MP07_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP06), + S5PV210_GPIO_MP10_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP07), + S5PV210_GPIO_MP11_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP10), + S5PV210_GPIO_MP12_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP11), + S5PV210_GPIO_MP13_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP12), + S5PV210_GPIO_MP14_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP13), + S5PV210_GPIO_MP15_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP14), + S5PV210_GPIO_MP16_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP15), + S5PV210_GPIO_MP17_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP16), + S5PV210_GPIO_MP18_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP17), + S5PV210_GPIO_MP20_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP18), + S5PV210_GPIO_MP21_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP20), + S5PV210_GPIO_MP22_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP21), + S5PV210_GPIO_MP23_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP22), + S5PV210_GPIO_MP24_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP23), + S5PV210_GPIO_MP25_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP24), + S5PV210_GPIO_MP26_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP25), + S5PV210_GPIO_MP27_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP26), + S5PV210_GPIO_MP28_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP27), + S5PV210_GPIO_ETC0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP28), + S5PV210_GPIO_ETC1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC0), + S5PV210_GPIO_ETC2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC1), + S5PV210_GPIO_ETC4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC2), }; /* S5PV210 GPIO number definitions */ @@ -133,15 +185,69 @@ enum s5p_gpio_number { #define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) #define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr)) #define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr)) +#define S5PV210_MP06(_nr) (S5PV210_GPIO_MP06_START + (_nr)) +#define S5PV210_MP07(_nr) (S5PV210_GPIO_MP07_START + (_nr)) +#define S5PV210_MP10(_nr) (S5PV210_GPIO_MP10_START + (_nr)) +#define S5PV210_MP11(_nr) (S5PV210_GPIO_MP11_START + (_nr)) +#define S5PV210_MP12(_nr) (S5PV210_GPIO_MP12_START + (_nr)) +#define S5PV210_MP13(_nr) (S5PV210_GPIO_MP13_START + (_nr)) +#define S5PV210_MP14(_nr) (S5PV210_GPIO_MP14_START + (_nr)) +#define S5PV210_MP15(_nr) (S5PV210_GPIO_MP15_START + (_nr)) +#define S5PV210_MP16(_nr) (S5PV210_GPIO_MP16_START + (_nr)) +#define S5PV210_MP17(_nr) (S5PV210_GPIO_MP17_START + (_nr)) +#define S5PV210_MP18(_nr) (S5PV210_GPIO_MP18_START + (_nr)) +#define S5PV210_MP20(_nr) (S5PV210_GPIO_MP20_START + (_nr)) +#define S5PV210_MP21(_nr) (S5PV210_GPIO_MP21_START + (_nr)) +#define S5PV210_MP22(_nr) (S5PV210_GPIO_MP22_START + (_nr)) +#define S5PV210_MP23(_nr) (S5PV210_GPIO_MP23_START + (_nr)) +#define S5PV210_MP24(_nr) (S5PV210_GPIO_MP24_START + (_nr)) +#define S5PV210_MP25(_nr) (S5PV210_GPIO_MP25_START + (_nr)) +#define S5PV210_MP26(_nr) (S5PV210_GPIO_MP26_START + (_nr)) +#define S5PV210_MP27(_nr) (S5PV210_GPIO_MP27_START + (_nr)) +#define S5PV210_MP28(_nr) (S5PV210_GPIO_MP28_START + (_nr)) +#define S5PV210_ETC0(_nr) (S5PV210_GPIO_ETC0_START + (_nr)) +#define S5PV210_ETC1(_nr) (S5PV210_GPIO_ETC1_START + (_nr)) +#define S5PV210_ETC2(_nr) (S5PV210_GPIO_ETC2_START + (_nr)) +#define S5PV210_ETC4(_nr) (S5PV210_GPIO_ETC4_START + (_nr)) + +/* Define EXT INT GPIO */ +#define S5P_EXT_INT0(x) S5PV210_GPH0(x) +#define S5P_EXT_INT1(x) S5PV210_GPH1(x) +#define S5P_EXT_INT2(x) S5PV210_GPH2(x) +#define S5P_EXT_INT3(x) S5PV210_GPH3(x) /* the end of the S5PV210 specific gpios */ -#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1) +#define S5PV210_GPIO_END (S5PV210_ETC4(S5PV210_GPIO_ETC4_NR) + 1) #define S3C_GPIO_END S5PV210_GPIO_END -/* define the number of gpios we need to the one after the MP05() range */ -#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \ +/* define the number of gpios we need to the one after the GPJ4() range */ +#define ARCH_NR_GPIOS (S5PV210_ETC4(S5PV210_GPIO_ETC4_NR) + \ CONFIG_SAMSUNG_GPIO_EXTRA + 1) #include <asm-generic/gpio.h> +#include <plat/gpio-cfg.h> + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int to); +extern s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin); + +#define S3C_GPIO_SLP_OUT0 ((__force s3c_gpio_pull_t)0x00) +#define S3C_GPIO_SLP_OUT1 ((__force s3c_gpio_pull_t)0x01) +#define S3C_GPIO_SLP_INPUT ((__force s3c_gpio_pull_t)0x02) +#define S3C_GPIO_SLP_PREV ((__force s3c_gpio_pull_t)0x03) + +extern int s3c_gpio_set_drvstrength(unsigned int pin, unsigned int config); +extern int s3c_gpio_set_slewrate(unsigned int pin, unsigned int config); + +#define S3C_GPIO_DRVSTR_1X (0) +#define S3C_GPIO_DRVSTR_2X (1) +#define S3C_GPIO_DRVSTR_3X (2) +#define S3C_GPIO_DRVSTR_4X (3) + +#define S3C_GPIO_SLEWRATE_FAST (0) +#define S3C_GPIO_SLEWRATE_SLOW (1) + +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, s3c_gpio_pull_t pull); +extern int s5pv210_gpiolib_init(void); + #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index b9f9ec3..b747128 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -17,6 +17,22 @@ /* VIC0: System, DMA, Timer */ +#define IRQ_EINT0 S5P_IRQ_VIC0(0) +#define IRQ_EINT1 S5P_IRQ_VIC0(1) +#define IRQ_EINT2 S5P_IRQ_VIC0(2) +#define IRQ_EINT3 S5P_IRQ_VIC0(3) +#define IRQ_EINT4 S5P_IRQ_VIC0(4) +#define IRQ_EINT5 S5P_IRQ_VIC0(5) +#define IRQ_EINT6 S5P_IRQ_VIC0(6) +#define IRQ_EINT7 S5P_IRQ_VIC0(7) +#define IRQ_EINT8 S5P_IRQ_VIC0(8) +#define IRQ_EINT9 S5P_IRQ_VIC0(9) +#define IRQ_EINT10 S5P_IRQ_VIC0(10) +#define IRQ_EINT11 S5P_IRQ_VIC0(11) +#define IRQ_EINT12 S5P_IRQ_VIC0(12) +#define IRQ_EINT13 S5P_IRQ_VIC0(13) +#define IRQ_EINT14 S5P_IRQ_VIC0(14) +#define IRQ_EINT15 S5P_IRQ_VIC0(15) #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) #define IRQ_BATF S5P_IRQ_VIC0(17) #define IRQ_MDMA S5P_IRQ_VIC0(18) @@ -116,17 +132,19 @@ #define IRQ_MDNIE1 S5P_IRQ_VIC3(6) #define IRQ_MDNIE2 S5P_IRQ_VIC3(7) #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) +#define IRQ_ADC1 S5P_IRQ_VIC3(9) +#define IRQ_PENDN1 S5P_IRQ_VIC3(10) #define IRQ_VIC_END S5P_IRQ_VIC3(31) #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) +#define S5P_IRQ_EINT_BASE S5P_EINT_BASE2 /* GPIO interrupt */ #define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) #define S5P_GPIOINT_GROUP_MAXNR 22 -/* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) +#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) /* Compatibility */ #define IRQ_LCD_FIFO IRQ_LCD0 @@ -134,4 +152,73 @@ #define IRQ_LCD_SYSTEM IRQ_LCD2 #define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (8) /* A0 */ +#define IRQ_EINT_GROUP2_NR (4) /* A1 */ +#define IRQ_EINT_GROUP3_NR (8) /* B */ +#define IRQ_EINT_GROUP4_NR (5) /* C0 */ +#define IRQ_EINT_GROUP5_NR (5) /* C1 */ +#define IRQ_EINT_GROUP6_NR (4) /* D0 */ +#define IRQ_EINT_GROUP7_NR (6) /* D1 */ +#define IRQ_EINT_GROUP8_NR (8) /* E0 */ +#define IRQ_EINT_GROUP9_NR (5) /* E1 */ +#define IRQ_EINT_GROUP10_NR (8) /* F0 */ +#define IRQ_EINT_GROUP11_NR (8) /* F1 */ +#define IRQ_EINT_GROUP12_NR (8) /* F2 */ +#define IRQ_EINT_GROUP13_NR (6) /* F3 */ +#define IRQ_EINT_GROUP14_NR (7) /* G0 */ +#define IRQ_EINT_GROUP15_NR (7) /* G1 */ +#define IRQ_EINT_GROUP16_NR (7) /* G2 */ +#define IRQ_EINT_GROUP17_NR (7) /* G3 */ +#define IRQ_EINT_GROUP18_NR (8) /* J0 */ +#define IRQ_EINT_GROUP19_NR (6) /* J1 */ +#define IRQ_EINT_GROUP20_NR (8) /* J2 */ +#define IRQ_EINT_GROUP21_NR (8) /* J3 */ +#define IRQ_EINT_GROUP22_NR (5) /* J4 */ + +#define IRQ_EINT_GROUP_BASE S5P_EINT(31 + 1) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) +#define IRQ_EINT_GROUP10_BASE (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR) +#define IRQ_EINT_GROUP11_BASE (IRQ_EINT_GROUP10_BASE + IRQ_EINT_GROUP10_NR) +#define IRQ_EINT_GROUP12_BASE (IRQ_EINT_GROUP11_BASE + IRQ_EINT_GROUP11_NR) +#define IRQ_EINT_GROUP13_BASE (IRQ_EINT_GROUP12_BASE + IRQ_EINT_GROUP12_NR) +#define IRQ_EINT_GROUP14_BASE (IRQ_EINT_GROUP13_BASE + IRQ_EINT_GROUP13_NR) +#define IRQ_EINT_GROUP15_BASE (IRQ_EINT_GROUP14_BASE + IRQ_EINT_GROUP14_NR) +#define IRQ_EINT_GROUP16_BASE (IRQ_EINT_GROUP15_BASE + IRQ_EINT_GROUP15_NR) +#define IRQ_EINT_GROUP17_BASE (IRQ_EINT_GROUP16_BASE + IRQ_EINT_GROUP16_NR) +#define IRQ_EINT_GROUP18_BASE (IRQ_EINT_GROUP17_BASE + IRQ_EINT_GROUP17_NR) +#define IRQ_EINT_GROUP19_BASE (IRQ_EINT_GROUP18_BASE + IRQ_EINT_GROUP18_NR) +#define IRQ_EINT_GROUP20_BASE (IRQ_EINT_GROUP19_BASE + IRQ_EINT_GROUP19_NR) +#define IRQ_EINT_GROUP21_BASE (IRQ_EINT_GROUP20_BASE + IRQ_EINT_GROUP20_NR) +#define IRQ_EINT_GROUP22_BASE (IRQ_EINT_GROUP21_BASE + IRQ_EINT_GROUP21_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) + +/* Set the default NR_IRQS */ +//#define NR_IRQS (IRQ_EINT(31) + 1) +#define NR_IRQS (IRQ_EINT_GROUP22_BASE + IRQ_EINT_GROUP22_NR + 1) + +#define HALL_SENSOR_IRQ IRQ_EINT3 + +#define FIQ_START 0 + #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 1dd5883..704e192 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -16,7 +16,11 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> -#define S5PV210_PA_SDRAM 0x20000000 +#if defined(CONFIG_MACH_SMDKV210) +#define S5PV210_PA_SDRAM (0x20000000) +#else +#define S5PV210_PA_SDRAM (0x30000000) +#endif #define S5PV210_PA_SROM_BANK5 0xA8000000 @@ -53,6 +57,9 @@ #define S5PV210_PA_WATCHDOG 0xE2700000 #define S5PV210_PA_RTC 0xE2800000 +#define S5PV210_VA_RTC S3C_ADDR(0x00c00000) +#define S5P_VA_RTC S5PV210_VA_RTC + #define S5PV210_PA_UART 0xE2900000 #define S5PV210_PA_SROMC 0xE8000000 @@ -61,9 +68,27 @@ #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) +/* usb */ +#define S5PV210_PA_OTG (0xEC000000) +#define S5PV210_SZ_OTG SZ_1M + +#define S5PV210_PA_OTGSFR (0xEC100000) +#define S5PV210_SZ_OTGSFR SZ_1M + +#define S5PV210_PA_USB_EHCI (0xEC200000) +#define S5P_PA_USB_EHCI S5PV210_PA_USB_EHCI +#define S5P_SZ_USB_EHCI SZ_1M + +#define S5PV210_PA_USB_OHCI (0xEC300000) +#define S5P_PA_USB_OHCI S5PV210_PA_USB_OHCI +#define S5P_SZ_USB_OHCI SZ_1M +/* end usb */ + #define S5PV210_PA_HSOTG 0xEC000000 #define S5PV210_PA_HSPHY 0xEC100000 +#define S5PV210_PA_AUDSS (0xEEE10000) + #define S5PV210_PA_IIS0 0xEEE30000 #define S5PV210_PA_IIS1 0xE2100000 #define S5PV210_PA_IIS2 0xE2A00000 @@ -71,6 +96,31 @@ #define S5PV210_PA_DMC0 0xF0000000 #define S5PV210_PA_DMC1 0xF1400000 +#define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0) +#define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define S5P_VA_VIC2 (S3C_VA_IRQ + 0x20000) +#define S5P_VA_VIC3 (S3C_VA_IRQ + 0x30000) + +#define S5PV210_PA_LCD (0xF8000000) +#define S5P_PA_LCD S5PV210_PA_LCD +#define S5PV210_SZ_LCD SZ_1M +#define S5P_SZ_LCD S5PV210_SZ_LCD + +#define S5PV210_PA_JPEG (0xFB600000) +#define S5PV210_SZ_JPEG SZ_1M + +#define S5PV210_SZ_FIMC0 SZ_1M +#define S5P_SZ_FIMC0 S5PV210_SZ_FIMC0 +#define S5PV210_SZ_FIMC1 SZ_1M +#define S5P_SZ_FIMC1 S5PV210_SZ_FIMC1 +#define S5PV210_SZ_FIMC2 SZ_1M +#define S5P_SZ_FIMC2 S5PV210_SZ_FIMC2 + +#define S5PV210_PA_IPC (0xFB700000) +#define S5P_PA_IPC S5PV210_PA_IPC +#define S5PV210_SZ_IPC SZ_1M +#define S5P_SZ_IPC S5PV210_SZ_IPC + #define S5PV210_PA_VIC0 0xF2000000 #define S5PV210_PA_VIC1 0xF2100000 #define S5PV210_PA_VIC2 0xF2200000 @@ -88,6 +138,28 @@ #define S5PV210_PA_FIMC1 0xFB300000 #define S5PV210_PA_FIMC2 0xFB400000 +/* mfc */ +#define S5PV210_PA_MFC (0xF1700000) +#define S5PV210_SZ_MFC SZ_1M +#define S5P_PA_MFC S5PV210_PA_MFC +#define S5P_SZ_MFC S5PV210_SZ_MFC + + +/* jpeg */ +#define S5PV210_PA_JPEG (0xFB600000) +#define S5P_PA_JPEG S5PV210_PA_JPEG +#define S5P_SZ_JPEG SZ_1M + +/* rotator */ +#define S5PV210_PA_ROTATOR (0xFA300000) +#define S5P_PA_ROTATOR S5PV210_PA_ROTATOR +#define S5P_SZ_ROTATOR SZ_1M + +/* fimg2d */ +#define S5PV210_PA_FIMG2D (0xFA000000) +#define S5P_PA_FIMG2D S5PV210_PA_FIMG2D +#define S5P_SZ_FIMG2D SZ_1M + /* Compatibiltiy Defines */ #define S3C_PA_FB S5PV210_PA_FB @@ -132,4 +204,38 @@ #define S5P_SZ_UART SZ_256 +/* CEC */ +#define S5PV210_PA_CEC (0xE1B00000) +#define S5P_PA_CEC S5PV210_PA_CEC +#define S5P_SZ_CEC SZ_4K + +/* TVOUT */ +#define S5PV210_PA_TVENC (0xF9000000) +#define S5P_PA_TVENC S5PV210_PA_TVENC +#define S5P_SZ_TVENC SZ_1M + +#define S5PV210_PA_VP (0xF9100000) +#define S5P_PA_VP S5PV210_PA_VP +#define S5P_SZ_VP SZ_1M + +#define S5PV210_PA_MIXER (0xF9200000) +#define S5P_PA_MIXER S5PV210_PA_MIXER +#define S5P_SZ_MIXER SZ_1M + +#define S5PV210_PA_HDMI (0xFA100000) +#define S5P_PA_HDMI S5PV210_PA_HDMI +#define S5P_SZ_HDMI SZ_1M + +#define S5PV210_I2C_HDMI_PHY (0xFA900000) +#define S5P_I2C_HDMI_PHY S5PV210_I2C_HDMI_PHY +#define S5P_I2C_HDMI_SZ_PHY SZ_1K + +/* usb */ +#define S3C_PA_OTG S5PV210_PA_OTG +#define S3C_SZ_OTG S5PV210_SZ_OTG + +#define S3C_PA_OTGSFR S5PV210_PA_OTGSFR +#define S3C_SZ_OTGSFR S5PV210_SZ_OTGSFR + +/* end usb */ #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/media.h b/arch/arm/mach-s5pv210/include/mach/media.h new file mode 100755 index 0000000..ad9eb82 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/media.h @@ -0,0 +1,32 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/media.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung Media device descriptions for smdkv210 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _S5PV210_MEDIA_H +#define _S5PV210_MEDIA_H + +/* 3 fimc indexes should be fixed as n, n+1 and n+2 */ +#define S5P_MDEV_FIMC0 0 +#define S5P_MDEV_FIMC1 1 +#define S5P_MDEV_FIMC2 2 +#define S5P_MDEV_TV 3 +#define S5P_MDEV_MFC 4 +#define S5P_MDEV_JPEG 5 +#define S5P_MDEV_PMEM 6 +#define S5P_MDEV_PMEM_GPU1 7 +#define S5P_MDEV_PMEM_ADSP 8 +#define S5P_MDEV_TEXSTREAM 9 +#define S5P_MDEV_FIMD 10 +#define S5P_MDEV_MAX 11 + +#define S5P_RANGE_MFC SZ_256M +#endif + diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h index 7b5fcf0..003d287 100644 --- a/arch/arm/mach-s5pv210/include/mach/memory.h +++ b/arch/arm/mach-s5pv210/include/mach/memory.h @@ -13,7 +13,12 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H +#if defined(CONFIG_MACH_SMDKV210) #define PLAT_PHYS_OFFSET UL(0x20000000) +#else +#define PLAT_PHYS_OFFSET UL(0x30000000) +#endif + #define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) /* @@ -24,5 +29,6 @@ #define MAX_PHYSMEM_BITS 31 #define SECTION_SIZE_BITS 28 +#define NODE_MEM_SIZE_BITS 28 #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/param.h b/arch/arm/mach-s5pv210/include/mach/param.h new file mode 100644 index 0000000..dbba308 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/param.h @@ -0,0 +1,89 @@ +
+/*
+ * Parameter Infomation
+ */
+
+#ifndef ASM_MACH_PARAM_H
+#define ASM_MACH_PARAM_H
+
+#define PARAM_MAGIC 0x72726624
+#define PARAM_VERSION 0x13 /* Rev 1.3 */
+#define PARAM_STRING_SIZE 1024 /* 1024 Characters */
+
+#define MAX_PARAM 20
+#define MAX_STRING_PARAM 5
+
+/* Default Parameter Values */
+
+#define SERIAL_SPEED 7 /* Baudrate */
+#define LCD_LEVEL 0x061 /* Backlight Level */
+#define BOOT_DELAY 0 /* Boot Wait Time */
+#define LOAD_RAMDISK 0 /* Enable Ramdisk Loading */
+#define SWITCH_SEL 1 /* Switch Setting (UART[1], USB[0]) */
+#define PHONE_DEBUG_ON 0 /* Enable Phone Debug Mode */
+#define LCD_DIM_LEVEL 0x011 /* Backlight Dimming Level */
+#define LCD_DIM_TIME 0
+#define MELODY_MODE 0 /* Melody Mode */
+#define REBOOT_MODE 0 /* Reboot Mode */
+#define NATION_SEL 0 /* Language Configuration */
+#define LANGUAGE_SEL 0
+#define SET_DEFAULT_PARAM 0 /* Set Param to Default */
+#define VERSION_LINE "I8315XXIE00" /* Set Image Info */
+#define COMMAND_LINE "console=ttySAC2,115200"
+#define BOOT_VERSION " version=Sbl(1.0.0) "
+
+typedef enum {
+ __SERIAL_SPEED,
+ __LOAD_RAMDISK,
+ __BOOT_DELAY,
+ __LCD_LEVEL,
+ __SWITCH_SEL,
+ __PHONE_DEBUG_ON,
+ __LCD_DIM_LEVEL,
+ __LCD_DIM_TIME,
+ __MELODY_MODE,
+ __REBOOT_MODE,
+ __NATION_SEL,
+ __LANGUAGE_SEL,
+ __SET_DEFAULT_PARAM,
+ __PARAM_INT_13, /* Reserved. */
+ __PARAM_INT_14, /* Reserved. */
+ __VERSION,
+ __CMDLINE,
+ __PARAM_STR_2,
+ __PARAM_STR_3, /* Reserved. */
+ __PARAM_STR_4 /* Reserved. */
+} param_idx;
+
+typedef struct _param_int_t {
+ param_idx ident;
+ int value;
+} param_int_t;
+
+typedef struct _param_str_t {
+ param_idx ident;
+ char value[PARAM_STRING_SIZE];
+} param_str_t;
+
+typedef struct {
+ int param_magic;
+ int param_version;
+ param_int_t param_list[MAX_PARAM - MAX_STRING_PARAM];
+ param_str_t param_str_list[MAX_STRING_PARAM];
+} status_t;
+
+/* REBOOT_MODE */
+#define REBOOT_MODE_NONE 0
+#define REBOOT_MODE_DOWNLOAD 1
+#define REBOOT_MODE_CHARGING 3
+#define REBOOT_MODE_RECOVERY 4
+#define REBOOT_MODE_ARM11_FOTA 5
+#define REBOOT_MODE_ARM9_FOTA 6
+
+extern void (*sec_set_param_value)(int idx, void *value);
+extern void (*sec_get_param_value)(int idx, void *value);
+
+#define USB_SEL_MASK (1 << 0)
+#define UART_SEL_MASK (1 << 1)
+
+#endif /* ASM_MACH_PARAM_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index e8d394f..e0db671 100644..100755 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h @@ -14,6 +14,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <mach/regs-gpio.h> static inline void s3c_pm_debug_init_uart(void) { @@ -33,7 +34,10 @@ static inline void s3c_pm_arch_stop_clocks(void) static inline void s3c_pm_arch_show_resume_irqs(void) { - /* nothing here yet */ + printk(KERN_DEBUG "S5P_WAKEUP_STAT 0x%X\n", __raw_readl(S5P_WAKEUP_STAT)); + printk(KERN_DEBUG "EINT_PEND 0x%X, 0x%X, 0x%X, 0x%X\n", + __raw_readl(S5P_EINT_PEND(0)), __raw_readl(S5P_EINT_PEND(1)), + __raw_readl(S5P_EINT_PEND(2)), __raw_readl(S5P_EINT_PEND(3))); } static inline void s3c_pm_arch_update_uart(void __iomem *regs, @@ -41,3 +45,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, { /* nothing here yet */ } + diff --git a/arch/arm/mach-s5pv210/include/mach/power-domain.h b/arch/arm/mach-s5pv210/include/mach/power-domain.h new file mode 100644 index 0000000..8456c10 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/power-domain.h @@ -0,0 +1,57 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/power-domain.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Power domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_POWER_DOMAIN_H +#define __ASM_ARCH_POWER_DOMAIN_H __FILE__ + +#define S5PV210_PD_IROM (1 << 20) +#define S5PV210_PD_AUDIO (1 << 7) +#define S5PV210_PD_CAM (1 << 5) +#define S5PV210_PD_TV (1 << 4) +#define S5PV210_PD_LCD (1 << 3) +#define S5PV210_PD_G3D (1 << 2) +#define S5PV210_PD_MFC (1 << 1) + +struct regulator_init_data; + +/** + * struct s5pv210_pd_config - s5pv210_pd_config structure + * @supply_name: Name of the regulator supply + * @microvolts: Output voltage of regulator + * @startup_delay: Start-up time in microseconds + * @init_data: regulator_init_data + * @clk_should_be_running: the clocks for the IPs in the power domain + * should be running when the power domain + * is turned on + * @ctrlbit: register control bit + * + * This structure contains samsung power domain regulator configuration + * information that must be passed by platform code to the samsung + * power domain regulator driver. + */ +struct s5pv210_pd_config { + const char *supply_name; + int microvolts; + unsigned startup_delay; + struct regulator_init_data *init_data; + struct clk_should_be_running *clk_run; + int ctrlbit; +}; + +extern struct platform_device s5pv210_pd_audio; +extern struct platform_device s5pv210_pd_cam; +extern struct platform_device s5pv210_pd_tv; +extern struct platform_device s5pv210_pd_lcd; +extern struct platform_device s5pv210_pd_g3d; +extern struct platform_device s5pv210_pd_mfc; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/regs-adc.h b/arch/arm/mach-s5pv210/include/mach/regs-adc.h new file mode 100644 index 0000000..200fed9 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-adc.h @@ -0,0 +1,119 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-adc.h + * + * Copyright (c) 2004 Shannon Holland <holland@loser.net> + * + * This program is free software; yosu can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 ADC registers +*/ + +#ifndef __ASM_ARCH_REGS_ADC_H +#define __ASM_ARCH_REGS_ADC_H "regs-adc.h" + +#define S3C2410_ADCREG(x) (x) + +#define S3C2410_ADCCON S3C2410_ADCREG(0x00) +#define S3C2410_ADCTSC S3C2410_ADCREG(0x04) +#define S3C2410_ADCDLY S3C2410_ADCREG(0x08) +#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) +#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) + + +/* ADCCON Register Bits */ +#define S3C2410_ADCCON_ECFLG (1<<15) +#define S3C2410_ADCCON_PRSCEN (1<<14) +#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C2410_ADCCON_MUXMASK (0x7<<3) +#define S3C2410_ADCCON_STDBM (1<<2) +#define S3C2410_ADCCON_READ_START (1<<1) +#define S3C2410_ADCCON_ENABLE_START (1<<0) +#define S3C2410_ADCCON_STARTMASK (0x3<<0) + + +/* ADCTSC Register Bits */ +#define S3C2410_ADCTSC_YM_SEN (1<<7) +#define S3C2410_ADCTSC_YP_SEN (1<<6) +#define S3C2410_ADCTSC_XM_SEN (1<<5) +#define S3C2410_ADCTSC_XP_SEN (1<<4) +#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C2410_ADCTSC_AUTO_PST (1<<2) +#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) + +/* ADCDAT0 Bits */ +#define S3C2410_ADCDAT0_UPDOWN (1<<15) +#define S3C2410_ADCDAT0_AUTO_PST (1<<14) +#define S3C2410_ADCDAT0_XY_PST (0x3<<12) +#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) + +/* ADCDAT1 Bits */ +#define S3C2410_ADCDAT1_UPDOWN (1<<15) +#define S3C2410_ADCDAT1_AUTO_PST (1<<14) +#define S3C2410_ADCDAT1_XY_PST (0x3<<12) +#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) + +/*--------------------------- Common definitions for S3C ---------------------------*/ +/* The following definitions will be applied to S3C24XX, S3C64XX, S5PC1XX. */ +/*-----------------------------------------------------------------------------------*/ + +#define S3C_ADCREG(x) (x) + +#define S3C_ADCCON S3C_ADCREG(0x00) +#define S3C_ADCTSC S3C_ADCREG(0x04) +#define S3C_ADCDLY S3C_ADCREG(0x08) +#define S3C_ADCDAT0 S3C_ADCREG(0x0C) +#define S3C_ADCDAT1 S3C_ADCREG(0x10) +#define S3C_ADCUPDN S3C_ADCREG(0x14) +#define S3C_ADCCLRINT S3C_ADCREG(0x18) +#define S3C_ADCMUX S3C_ADCREG(0x1C) +#define S3C_ADCCLRWK S3C_ADCREG(0x20) + + +/* ADCCON Register Bits */ +#define S3C_ADCCON_RESSEL_10BIT (0x0<<16) +#define S3C_ADCCON_RESSEL_12BIT (0x1<<16) +#define S3C_ADCCON_ECFLG (1<<15) +#define S3C_ADCCON_PRSCEN (1<<14) +#define S3C_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C_ADCCON_SELMUX_1(x) (((x)&0xF)<<0) +#define S3C_ADCCON_MUXMASK (0x7<<3) +#define S3C_ADCCON_RESSEL_10BIT_1 (0x0<<3) +#define S3C_ADCCON_RESSEL_12BIT_1 (0x1<<3) +#define S3C_ADCCON_STDBM (1<<2) +#define S3C_ADCCON_READ_START (1<<1) +#define S3C_ADCCON_ENABLE_START (1<<0) +#define S3C_ADCCON_STARTMASK (0x3<<0) + + +/* ADCTSC Register Bits */ +#define S3C_ADCTSC_UD_SEN (1<<8) +#define S3C_ADCTSC_YM_SEN (1<<7) +#define S3C_ADCTSC_YP_SEN (1<<6) +#define S3C_ADCTSC_XM_SEN (1<<5) +#define S3C_ADCTSC_XP_SEN (1<<4) +#define S3C_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C_ADCTSC_AUTO_PST (1<<2) +#define S3C_ADCTSC_XY_PST(x) (((x)&0x3)<<0) + +/* ADCDAT0 Bits */ +#define S3C_ADCDAT0_UPDOWN (1<<15) +#define S3C_ADCDAT0_AUTO_PST (1<<14) +#define S3C_ADCDAT0_XY_PST (0x3<<12) +#define S3C_ADCDAT0_XPDATA_MASK (0x03FF) +#define S3C_ADCDAT0_XPDATA_MASK_12BIT (0x0FFF) + +/* ADCDAT1 Bits */ +#define S3C_ADCDAT1_UPDOWN (1<<15) +#define S3C_ADCDAT1_AUTO_PST (1<<14) +#define S3C_ADCDAT1_XY_PST (0x3<<12) +#define S3C_ADCDAT1_YPDATA_MASK (0x03FF) +#define S3C_ADCDAT1_YPDATA_MASK_12BIT (0x0FFF) + +#endif /* __ASM_ARCH_REGS_ADC_H */ + + diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h new file mode 100644 index 0000000..b2cc2fd --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h @@ -0,0 +1,44 @@ +/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h + * + * Copyright 2008 Samsung Electronics + * + * S5PV2XX Audio SubSystem clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_AUDSS_H +#define __PLAT_REGS_AUDSS_H __FILE__ + +#define S5P_AUDSSREG(x) (S5P_VA_AUDSS + (x)) + +#define S5P_CLKSRC_AUDSS S5P_AUDSSREG(0x0) +#define S5P_CLKDIV_AUDSS S5P_AUDSSREG(0x4) +#define S5P_CLKGATE_AUDSS S5P_AUDSSREG(0x8) + +/* CLKSRC0 */ +#define S5P_AUDSS_CLKSRC_MAIN_MASK (0x1<<0) +#define S5P_AUDSS_CLKSRC_MAIN_SHIFT (0) +#define S5P_AUDSS_CLKSRC_BUSCLK_MASK (0x1<<1) +#define S5P_AUDSS_CLKSRC_BUSCLK_SHIFT (1) +#define S5P_AUDSS_CLKSRC_I2SCLK_MASK (0x3<<2) +#define S5P_AUDSS_CLKSRC_I2SCLK_SHIFT (2) + +/* CLKDIV0 */ +#define S5P_AUDSS_CLKDIV_BUSCLK_MASK (0xf<<0) +#define S5P_AUDSS_CLKDIV_BUSCLK_SHIFT (0) +#define S5P_AUDSS_CLKDIV_I2SCLK_MASK (0xf<<4) +#define S5P_AUDSS_CLKDIV_I2SCLK_SHIFT (4) + +/* IP Clock Gate 0 Registers */ +#define S5P_AUDSS_CLKGATE_HCLKRP (1<<0) +#define S5P_AUDSS_CLKGATE_HCLKBUF (1<<1) +#define S5P_AUDSS_CLKGATE_HCLKDMA (1<<2) +#define S5P_AUDSS_CLKGATE_HCLKHWA (1<<3) +#define S5P_AUDSS_CLKGATE_HCLKUART (1<<4) +#define S5P_AUDSS_CLKGATE_HCLKI2S (1<<5) +#define S5P_AUDSS_CLKGATE_CLKI2S (1<<6) + +#endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 78925c5..d5d51cd 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -17,6 +17,9 @@ #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) +#define S5P_IECREG(x) (S5PC11X_VA_IEC + (x)) +#define S5P_APCREG(x) (S5PC11X_VA_APC + (x)) + #define S5P_APLL_LOCK S5P_CLKREG(0x00) #define S5P_MPLL_LOCK S5P_CLKREG(0x08) #define S5P_EPLL_LOCK S5P_CLKREG(0x10) @@ -64,8 +67,7 @@ #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) -#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) -#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) +#define S5P_CLKGATE_IP5 S5P_CLKREG(0x484) #define S5P_CLK_OUT S5P_CLKREG(0x500) /* DIV/MUX STATUS */ @@ -77,6 +79,17 @@ /* CLKSRC0 */ #define S5P_CLKSRC0_MUX200_SHIFT (16) #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) + +#define S5P_MIXER_OUT_SEL S5P_CLKREG(0x7004) + +#define S5P_EPLL_EN (1<<31) +#define S5P_EPLL_MASK 0xffffffff +#define S5P_EPLLVAL(_v,_m,_p,_s) ((_v) << 27 | (_m) << 16 | ((_p) << 8) | ((_s))) + +#define S5P_EPLL_MASK_VSEL (0x1<<27) +#define S5P_EPLL_MASK_M (0x1FF<<16) +#define S5P_EPLL_MASK_P (0x3F<<8) +#define S5P_EPLL_MASK_S (0x3<<0) #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) @@ -122,6 +135,161 @@ #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) +/* IP Clock Gate 0 Registers */ +#define S5P_CLKGATE_IP0_CSIS (1<<31) +#define S5P_CLKGATE_IP0_IPC (1<<30) +#define S5P_CLKGATE_IP0_ROTATOR (1<<29) +#define S5P_CLKGATE_IP0_JPEG (1<<28) +#define S5P_CLKGATE_IP0_FIMC2 (1<<26) +#define S5P_CLKGATE_IP0_FIMC1 (1<<25) +#define S5P_CLKGATE_IP0_FIMC0 (1<<24) +#define S5P_CLKGATE_IP0_MFC (1<<16) +#define S5P_CLKGATE_IP0_G2D (1<<12) +#define S5P_CLKGATE_IP0_G3D (1<<8) +#define S5P_CLKGATE_IP0_IMEM (1<<5) +#define S5P_CLKGATE_IP0_PDMA1 (1<<4) +#define S5P_CLKGATE_IP0_PDMA0 (1<<3) +#define S5P_CLKGATE_IP0_MDMA (1<<2) +#define S5P_CLKGATE_IP0_DMC1 (1<<1) +#define S5P_CLKGATE_IP0_DMC0 (1<<0) + +/* IP Clock Gate 1 Registers */ +#define S5P_CLKGATE_IP1_NFCON (1<<28) +#define S5P_CLKGATE_IP1_SROMC (1<<26) +#define S5P_CLKGATE_IP1_CFCON (1<<25) +#define S5P_CLKGATE_IP1_NANDXL (1<<24) +#define S5P_CLKGATE_IP1_USBHOST (1<<17) +#define S5P_CLKGATE_IP1_USBOTG (1<<16) +#define S5P_CLKGATE_IP1_HDMI (1<<11) +#define S5P_CLKGATE_IP1_TVENC (1<<10) +#define S5P_CLKGATE_IP1_MIXER (1<<9) +#define S5P_CLKGATE_IP1_VP (1<<8) +#define S5P_CLKGATE_IP1_DSIM (1<<2) +#define S5P_CLKGATE_IP1_MIE (1<<1) +#define S5P_CLKGATE_IP1_FIMD (1<<0) + +/* IP Clock Gate 2 Registers */ +#define S5P_CLKGATE_IP2_TZIC3 (1<<31) +#define S5P_CLKGATE_IP2_TZIC2 (1<<30) +#define S5P_CLKGATE_IP2_TZIC1 (1<<29) +#define S5P_CLKGATE_IP2_TZIC0 (1<<28) +#define S5P_CLKGATE_IP2_VIC3 (1<<27) +#define S5P_CLKGATE_IP2_VIC2 (1<<26) +#define S5P_CLKGATE_IP2_VIC1 (1<<25) +#define S5P_CLKGATE_IP2_VIC0 (1<<24) +#define S5P_CLKGATE_IP2_TSI (1<<20) +#define S5P_CLKGATE_IP2_HSMMC3 (1<<19) +#define S5P_CLKGATE_IP2_HSMMC2 (1<<18) +#define S5P_CLKGATE_IP2_HSMMC1 (1<<17) +#define S5P_CLKGATE_IP2_HSMMC0 (1<<16) +#define S5P_CLKGATE_IP2_SECJTAG (1<<11) +#define S5P_CLKGATE_IP2_HOSTIF (1<<10) +#define S5P_CLKGATE_IP2_MODEM (1<<9) +#define S5P_CLKGATE_IP2_CORESIGHT (1<<8) +#define S5P_CLKGATE_IP2_SDM (1<<1) +#define S5P_CLKGATE_IP2_SECSS (1<<0) + +/* IP Clock Gate 3 Registers */ +#define S5P_CLKGATE_IP3_PCM2 (1<<30) +#define S5P_CLKGATE_IP3_PCM1 (1<<29) +#define S5P_CLKGATE_IP3_PCM0 (1<<28) +#define S5P_CLKGATE_IP3_SYSCON (1<<27) +#define S5P_CLKGATE_IP3_GPIO (1<<26) +#define S5P_CLKGATE_IP3_TSADC (1<<24) +#define S5P_CLKGATE_IP3_PWM (1<<23) +#define S5P_CLKGATE_IP3_WDT (1<<22) +#define S5P_CLKGATE_IP3_KEYIF (1<<21) +#define S5P_CLKGATE_IP3_UART3 (1<<20) +#define S5P_CLKGATE_IP3_UART2 (1<<19) +#define S5P_CLKGATE_IP3_UART1 (1<<18) +#define S5P_CLKGATE_IP3_UART0 (1<<17) +#define S5P_CLKGATE_IP3_SYSTIMER (1<<16) +#define S5P_CLKGATE_IP3_RTC (1<<15) +#define S5P_CLKGATE_IP3_SPI2 (1<<14) +#define S5P_CLKGATE_IP3_SPI1 (1<<13) +#define S5P_CLKGATE_IP3_SPI0 (1<<12) +#define S5P_CLKGATE_IP3_I2C_HDMI_PHY (1<<11) +#define S5P_CLKGATE_IP3_I2C_HDMI_DDC (1<<10) +#define S5P_CLKGATE_IP3_I2C2 (1<<9) +#define S5P_CLKGATE_IP3_I2C1 (1<<8) +#define S5P_CLKGATE_IP3_I2C0 (1<<7) +#define S5P_CLKGATE_IP3_I2S2 (1<<6) +#define S5P_CLKGATE_IP3_I2S1 (1<<5) +#define S5P_CLKGATE_IP3_I2S0 (1<<4) +#define S5P_CLKGATE_IP3_AC97 (1<<1) +#define S5P_CLKGATE_IP3_SPDIF (1<<0) + +/* IP Clock Gate 4 Registers */ +#define S5P_CLKGATE_IP4_TZPC3 (1<<8) +#define S5P_CLKGATE_IP4_TZPC2 (1<<7) +#define S5P_CLKGATE_IP4_TZPC1 (1<<6) +#define S5P_CLKGATE_IP4_TZPC0 (1<<5) +#define S5P_CLKGATE_IP4_SECKEY (1<<3) +#define S5P_CLKGATE_IP4_IEM_APC (1<<2) +#define S5P_CLKGATE_IP4_IEM_IEC (1<<1) +#define S5P_CLKGATE_IP4_CHIP_ID (1<<0) + +/* Block Clock Gate Registers */ +#define S5P_CLKGATE_BLOCK_INTC (1<<10) +#define S5P_CLKGATE_BLOCK_HSMMC (1<<9) +#define S5P_CLKGATE_BLOCK_DEBUG (1<<8) +#define S5P_CLKGATE_BLOCK_SECURITY (1<<7) +#define S5P_CLKGATE_BLOCK_MEMORY (1<<6) +#define S5P_CLKGATE_BLOCK_USB (1<<5) +#define S5P_CLKGATE_BLOCK_TV (1<<4) +#define S5P_CLKGATE_BLOCK_LCD (1<<3) +#define S5P_CLKGATE_BLOCK_IMG (1<<2) +#define S5P_CLKGATE_BLOCK_MFC (1<<1) +#define S5P_CLKGATE_BLOCK_G3D (1<<0) + +/* IP Clock Gate 5 Registers */ +#define S5P_CLKGATE_IP5_JPEG (1<<29) + + +/* Bus Clock Gate Registers (hidden) */ + +/* register for EINT on PM Driver */ +#define S5P_APM_REG(x) ((x) + 0xE0200C00) + +#define S5P_APM_BASE S5P_APM_REG(0x000) + +#define S5P_APM_GPH0CON (0x000) +#define S5P_APM_GPH0DAT (0x004) +#define S5P_APM_GPH0PUD (0x008) +#define S5P_APM_GPH0DRV (0x00C) +#define S5P_APM_GPH1CON (0x020) +#define S5P_APM_GPH1DAT (0x024) +#define S5P_APM_GPH1PUD (0x028) +#define S5P_APM_GPH1DRV (0x02C) +#define S5P_APM_GPH2CON (0x040) +#define S5P_APM_GPH2DAT (0x044) +#define S5P_APM_GPH2PUD (0x048) +#define S5P_APM_GPH2DRV (0x04C) +#define S5P_APM_GPH3CON (0x060) +#define S5P_APM_GPH3DAT (0x064) +#define S5P_APM_GPH3PUD (0x068) +#define S5P_APM_GPH3DRV (0x06C) +#define S5P_APM_WEINT0_CON (0x200) +#define S5P_APM_WEINT1_CON (0x204) +#define S5P_APM_WEINT2_CON (0x208) +#define S5P_APM_WEINT3_CON (0x20C) +#define S5P_APM_WEINT0_FLTCON0 (0x280) +#define S5P_APM_WEINT0_FLTCON1 (0x284) +#define S5P_APM_WEINT1_FLTCON0 (0x288) +#define S5P_APM_WEINT1_FLTCON1 (0x28C) +#define S5P_APM_WEINT2_FLTCON0 (0x290) +#define S5P_APM_WEINT2_FLTCON1 (0x294) +#define S5P_APM_WEINT3_FLTCON0 (0x298) +#define S5P_APM_WEINT3_FLTCON1 (0x29C) +#define S5P_APM_WEINT0_MASK (0x300) +#define S5P_APM_WEINT1_MASK (0x304) +#define S5P_APM_WEINT2_MASK (0x308) +#define S5P_APM_WEINT3_MASK (0x30C) +#define S5P_APM_WEINT0_PEND (0x340) +#define S5P_APM_WEINT1_PEND (0x344) +#define S5P_APM_WEINT2_PEND (0x348) +#define S5P_APM_WEINT3_PEND (0x34C) + /* Registers related to power management */ #define S5P_PWR_CFG S5P_CLKREG(0xC000) #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) @@ -141,15 +309,21 @@ #define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) #define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) +#define S5P_ABB_VALUE S5P_CLKREG(0xC300) #define S5P_OTHERS S5P_CLKREG(0xE000) #define S5P_OM_STAT S5P_CLKREG(0xE100) +#define S5P_MIE_CONTROL S5P_CLKREG(0xE800) +#define S5P_HDMI_CONTROL S5P_CLKREG(0xE804) #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) #define S5P_DAC_CONTROL S5P_CLKREG(0xE810) #define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814) #define S5P_MIPI_DPHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_SRESETN (1 << 1) #define S5P_MIPI_DPHY_MRESETN (1 << 2) +#define S5P_ADC_CONTROL S5P_CLKREG(0xE818) +#define S5P_PSHOLD_CONTROL S5P_CLKREG(0xE81C) #define S5P_INFORM0 S5P_CLKREG(0xF000) #define S5P_INFORM1 S5P_CLKREG(0xF004) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h index de0c899..b2c69e8 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h @@ -15,11 +15,230 @@ #include <mach/map.h> +/* Base addresses for each of the banks */ + +#define S5PV210_GPA0_BASE (S5P_VA_GPIO + 0x000) +#define S5PV210_GPA1_BASE (S5P_VA_GPIO + 0x020) +#define S5PV210_GPB_BASE (S5P_VA_GPIO + 0x040) +#define S5PV210_GPC0_BASE (S5P_VA_GPIO + 0x060) +#define S5PV210_GPC1_BASE (S5P_VA_GPIO + 0x080) +#define S5PV210_GPD0_BASE (S5P_VA_GPIO + 0x0A0) +#define S5PV210_GPD1_BASE (S5P_VA_GPIO + 0x0C0) +#define S5PV210_GPE0_BASE (S5P_VA_GPIO + 0x0E0) +#define S5PV210_GPE1_BASE (S5P_VA_GPIO + 0x100) +#define S5PV210_GPF0_BASE (S5P_VA_GPIO + 0x120) +#define S5PV210_GPF1_BASE (S5P_VA_GPIO + 0x140) +#define S5PV210_GPF2_BASE (S5P_VA_GPIO + 0x160) +#define S5PV210_GPF3_BASE (S5P_VA_GPIO + 0x180) +#define S5PV210_GPG0_BASE (S5P_VA_GPIO + 0x1A0) +#define S5PV210_GPG1_BASE (S5P_VA_GPIO + 0x1C0) +#define S5PV210_GPG2_BASE (S5P_VA_GPIO + 0x1E0) +#define S5PV210_GPG3_BASE (S5P_VA_GPIO + 0x200) +#define S5PV210_GPH0_BASE (S5P_VA_GPIO + 0xC00) +#define S5PV210_GPH1_BASE (S5P_VA_GPIO + 0xC20) +#define S5PV210_GPH2_BASE (S5P_VA_GPIO + 0xC40) +#define S5PV210_GPH3_BASE (S5P_VA_GPIO + 0xC60) +#define S5PV210_GPI_BASE (S5P_VA_GPIO + 0x220) +#define S5PV210_GPJ0_BASE (S5P_VA_GPIO + 0x240) +#define S5PV210_GPJ1_BASE (S5P_VA_GPIO + 0x260) +#define S5PV210_GPJ2_BASE (S5P_VA_GPIO + 0x280) +#define S5PV210_GPJ3_BASE (S5P_VA_GPIO + 0x2A0) +#define S5PV210_GPJ4_BASE (S5P_VA_GPIO + 0x2C0) +#define S5PV210_MP01_BASE (S5P_VA_GPIO + 0x2E0) +#define S5PV210_MP02_BASE (S5P_VA_GPIO + 0x300) +#define S5PV210_MP03_BASE (S5P_VA_GPIO + 0x320) +#define S5PV210_MP04_BASE (S5P_VA_GPIO + 0x340) +#define S5PV210_MP05_BASE (S5P_VA_GPIO + 0x360) +#define S5PV210_MP06_BASE (S5P_VA_GPIO + 0x380) +#define S5PV210_MP07_BASE (S5P_VA_GPIO + 0x3A0) +#define S5PV210_MP10_BASE (S5P_VA_GPIO + 0x3C0) +#define S5PV210_MP11_BASE (S5P_VA_GPIO + 0x3E0) +#define S5PV210_MP12_BASE (S5P_VA_GPIO + 0x400) +#define S5PV210_MP13_BASE (S5P_VA_GPIO + 0x420) +#define S5PV210_MP14_BASE (S5P_VA_GPIO + 0x440) +#define S5PV210_MP15_BASE (S5P_VA_GPIO + 0x460) +#define S5PV210_MP16_BASE (S5P_VA_GPIO + 0x480) +#define S5PV210_MP17_BASE (S5P_VA_GPIO + 0x4A0) +#define S5PV210_MP18_BASE (S5P_VA_GPIO + 0x4C0) +#define S5PV210_MP20_BASE (S5P_VA_GPIO + 0x4E0) +#define S5PV210_MP21_BASE (S5P_VA_GPIO + 0x500) +#define S5PV210_MP22_BASE (S5P_VA_GPIO + 0x520) +#define S5PV210_MP23_BASE (S5P_VA_GPIO + 0x540) +#define S5PV210_MP24_BASE (S5P_VA_GPIO + 0x560) +#define S5PV210_MP25_BASE (S5P_VA_GPIO + 0x580) +#define S5PV210_MP26_BASE (S5P_VA_GPIO + 0x5A0) +#define S5PV210_MP27_BASE (S5P_VA_GPIO + 0x5C0) +#define S5PV210_MP28_BASE (S5P_VA_GPIO + 0x5E0) +#define S5PV210_ETC0_BASE (S5P_VA_GPIO + 0x600) +#define S5PV210_ETC1_BASE (S5P_VA_GPIO + 0x620) +#define S5PV210_ETC2_BASE (S5P_VA_GPIO + 0x640) +#define S5PV210_ETC4_BASE (S5P_VA_GPIO + 0x660) + +#define S5PV210_GPA0_INT_CON (S5P_VA_GPIO + 0x700) +#define S5PV210_GPA0_INT_FLTCON0 (S5P_VA_GPIO + 0x800) +#define S5PV210_GPA0_INT_FLTCON1 (S5P_VA_GPIO + 0x804) +#define S5PV210_GPA0_INT_MASK (S5P_VA_GPIO + 0x900) +#define S5PV210_GPA0_INT_PEND (S5P_VA_GPIO + 0xA00) +#define S5PV210_GPA0_INT_FIXPRI (S5P_VA_GPIO + 0xB14) + +#define S5PV210_GPA1_INT_CON (S5P_VA_GPIO + 0x704) +#define S5PV210_GPA1_INT_FLTCON0 (S5P_VA_GPIO + 0x808) +#define S5PV210_GPA1_INT_FLTCON1 (S5P_VA_GPIO + 0x80C) +#define S5PV210_GPA1_INT_MASK (S5P_VA_GPIO + 0x904) +#define S5PV210_GPA1_INT_PEND (S5P_VA_GPIO + 0xA04) +#define S5PV210_GPA1_INT_FIXPRI (S5P_VA_GPIO + 0xB18) + +#define S5PV210_GPB_INT_CON (S5P_VA_GPIO + 0x708) +#define S5PV210_GPB_INT_FLTCON0 (S5P_VA_GPIO + 0x810) +#define S5PV210_GPB_INT_FLTCON1 (S5P_VA_GPIO + 0x814) +#define S5PV210_GPB_INT_MASK (S5P_VA_GPIO + 0x908) +#define S5PV210_GPB_INT_PEND (S5P_VA_GPIO + 0xA08) +#define S5PV210_GPB_INT_FIXPRI (S5P_VA_GPIO + 0xB1C) + +#define S5PV210_GPC0_INT_CON (S5P_VA_GPIO + 0x70C) +#define S5PV210_GPC0_INT_FLTCON0 (S5P_VA_GPIO + 0x818) +#define S5PV210_GPC0_INT_FLTCON1 (S5P_VA_GPIO + 0x81C) +#define S5PV210_GPC0_INT_MASK (S5P_VA_GPIO + 0x90C) +#define S5PV210_GPC0_INT_PEND (S5P_VA_GPIO + 0xA0C) +#define S5PV210_GPC0_INT_FIXPRI (S5P_VA_GPIO + 0xB20) + +#define S5PV210_GPC1_INT_CON (S5P_VA_GPIO + 0x710) +#define S5PV210_GPC1_INT_FLTCON0 (S5P_VA_GPIO + 0x820) +#define S5PV210_GPC1_INT_FLTCON1 (S5P_VA_GPIO + 0x824) +#define S5PV210_GPC1_INT_MASK (S5P_VA_GPIO + 0x910) +#define S5PV210_GPC1_INT_PEND (S5P_VA_GPIO + 0xA10) +#define S5PV210_GPC1_INT_FIXPRI (S5P_VA_GPIO + 0xB24) + +#define S5PV210_GPD0_INT_CON (S5P_VA_GPIO + 0x714) +#define S5PV210_GPD0_INT_FLTCON0 (S5P_VA_GPIO + 0x828) +#define S5PV210_GPD0_INT_FLTCON1 (S5P_VA_GPIO + 0x82C) +#define S5PV210_GPD0_INT_MASK (S5P_VA_GPIO + 0x914) +#define S5PV210_GPD0_INT_PEND (S5P_VA_GPIO + 0xA14) +#define S5PV210_GPD0_INT_FIXPRI (S5P_VA_GPIO + 0xB28) + +#define S5PV210_GPD1_INT_CON (S5P_VA_GPIO + 0x718) +#define S5PV210_GPD1_INT_FLTCON0 (S5P_VA_GPIO + 0x830) +#define S5PV210_GPD1_INT_FLTCON1 (S5P_VA_GPIO + 0x834) +#define S5PV210_GPD1_INT_MASK (S5P_VA_GPIO + 0x918) +#define S5PV210_GPD1_INT_PEND (S5P_VA_GPIO + 0xA18) +#define S5PV210_GPD1_INT_FIXPRI (S5P_VA_GPIO + 0xB2C) + +#define S5PV210_GPE0_INT_CON (S5P_VA_GPIO + 0x71C) +#define S5PV210_GPE0_INT_FLTCON0 (S5P_VA_GPIO + 0x838) +#define S5PV210_GPE0_INT_FLTCON1 (S5P_VA_GPIO + 0x83C) +#define S5PV210_GPE0_INT_MASK (S5P_VA_GPIO + 0x91C) +#define S5PV210_GPE0_INT_PEND (S5P_VA_GPIO + 0xA1C) +#define S5PV210_GPE0_INT_FIXPRI (S5P_VA_GPIO + 0xB30) + +#define S5PV210_GPE1_INT_CON (S5P_VA_GPIO + 0x720) +#define S5PV210_GPE1_INT_FLTCON0 (S5P_VA_GPIO + 0x840) +#define S5PV210_GPE1_INT_FLTCON1 (S5P_VA_GPIO + 0x844) +#define S5PV210_GPE1_INT_MASK (S5P_VA_GPIO + 0x920) +#define S5PV210_GPE1_INT_PEND (S5P_VA_GPIO + 0xA20) +#define S5PV210_GPE1_INT_FIXPRI (S5P_VA_GPIO + 0xB34) + +#define S5PV210_GPF0_INT_CON (S5P_VA_GPIO + 0x724) +#define S5PV210_GPF0_INT_FLTCON0 (S5P_VA_GPIO + 0x848) +#define S5PV210_GPF0_INT_FLTCON1 (S5P_VA_GPIO + 0x84C) +#define S5PV210_GPF0_INT_MASK (S5P_VA_GPIO + 0x924) +#define S5PV210_GPF0_INT_PEND (S5P_VA_GPIO + 0xA24) +#define S5PV210_GPF0_INT_FIXPRI (S5P_VA_GPIO + 0xB38) + +#define S5PV210_GPF1_INT_CON (S5P_VA_GPIO + 0x728) +#define S5PV210_GPF1_INT_FLTCON0 (S5P_VA_GPIO + 0x850) +#define S5PV210_GPF1_INT_FLTCON1 (S5P_VA_GPIO + 0x854) +#define S5PV210_GPF1_INT_MASK (S5P_VA_GPIO + 0x928) +#define S5PV210_GPF1_INT_PEND (S5P_VA_GPIO + 0xA28) +#define S5PV210_GPF1_INT_FIXPRI (S5P_VA_GPIO + 0xB3C) + +#define S5PV210_GPF2_INT_CON (S5P_VA_GPIO + 0x72C) +#define S5PV210_GPF2_INT_FLTCON0 (S5P_VA_GPIO + 0x858) +#define S5PV210_GPF2_INT_FLTCON1 (S5P_VA_GPIO + 0x85C) +#define S5PV210_GPF2_INT_MASK (S5P_VA_GPIO + 0x92C) +#define S5PV210_GPF2_INT_PEND (S5P_VA_GPIO + 0xA2C) +#define S5PV210_GPF2_INT_FIXPRI (S5P_VA_GPIO + 0xB40) + +#define S5PV210_GPF3_INT_CON (S5P_VA_GPIO + 0x730) +#define S5PV210_GPF3_INT_FLTCON0 (S5P_VA_GPIO + 0x860) +#define S5PV210_GPF3_INT_FLTCON1 (S5P_VA_GPIO + 0x864) +#define S5PV210_GPF3_INT_MASK (S5P_VA_GPIO + 0x930) +#define S5PV210_GPF3_INT_PEND (S5P_VA_GPIO + 0xA30) +#define S5PV210_GPF3_INT_FIXPRI (S5P_VA_GPIO + 0xB44) + +#define S5PV210_GPG0_INT_CON (S5P_VA_GPIO + 0x734) +#define S5PV210_GPG0_INT_FLTCON0 (S5P_VA_GPIO + 0x868) +#define S5PV210_GPG0_INT_FLTCON1 (S5P_VA_GPIO + 0x86C) +#define S5PV210_GPG0_INT_MASK (S5P_VA_GPIO + 0x934) +#define S5PV210_GPG0_INT_PEND (S5P_VA_GPIO + 0xA34) +#define S5PV210_GPG0_INT_FIXPRI (S5P_VA_GPIO + 0xB48) + +#define S5PV210_GPG1_INT_CON (S5P_VA_GPIO + 0x738) +#define S5PV210_GPG1_INT_FLTCON0 (S5P_VA_GPIO + 0x870) +#define S5PV210_GPG1_INT_FLTCON1 (S5P_VA_GPIO + 0x874) +#define S5PV210_GPG1_INT_MASK (S5P_VA_GPIO + 0x938) +#define S5PV210_GPG1_INT_PEND (S5P_VA_GPIO + 0xA38) +#define S5PV210_GPG1_INT_FIXPRI (S5P_VA_GPIO + 0xB4C) + +#define S5PV210_GPG2_INT_CON (S5P_VA_GPIO + 0x73C) +#define S5PV210_GPG2_INT_FLTCON0 (S5P_VA_GPIO + 0x878) +#define S5PV210_GPG2_INT_FLTCON1 (S5P_VA_GPIO + 0x87C) +#define S5PV210_GPG2_INT_MASK (S5P_VA_GPIO + 0x93C) +#define S5PV210_GPG2_INT_PEND (S5P_VA_GPIO + 0xA3C) +#define S5PV210_GPG2_INT_FIXPRI (S5P_VA_GPIO + 0xB50) + +#define S5PV210_GPG3_INT_CON (S5P_VA_GPIO + 0x740) +#define S5PV210_GPG3_INT_FLTCON0 (S5P_VA_GPIO + 0x880) +#define S5PV210_GPG3_INT_FLTCON1 (S5P_VA_GPIO + 0x884) +#define S5PV210_GPG3_INT_MASK (S5P_VA_GPIO + 0x940) +#define S5PV210_GPG3_INT_PEND (S5P_VA_GPIO + 0xA40) +#define S5PV210_GPG3_INT_FIXPRI (S5P_VA_GPIO + 0xB54) + +#define S5PV210_GPJ0_INT_CON (S5P_VA_GPIO + 0x744) +#define S5PV210_GPJ0_INT_FLTCON0 (S5P_VA_GPIO + 0x888) +#define S5PV210_GPJ0_INT_FLTCON1 (S5P_VA_GPIO + 0x88C) +#define S5PV210_GPJ0_INT_MASK (S5P_VA_GPIO + 0x944) +#define S5PV210_GPJ0_INT_PEND (S5P_VA_GPIO + 0xA44) +#define S5PV210_GPJ0_INT_FIXPRI (S5P_VA_GPIO + 0xB58) + +#define S5PV210_GPJ1_INT_CON (S5P_VA_GPIO + 0x748) +#define S5PV210_GPJ1_INT_FLTCON0 (S5P_VA_GPIO + 0x890) +#define S5PV210_GPJ1_INT_FLTCON1 (S5P_VA_GPIO + 0x894) +#define S5PV210_GPJ1_INT_MASK (S5P_VA_GPIO + 0x948) +#define S5PV210_GPJ1_INT_PEND (S5P_VA_GPIO + 0xA48) +#define S5PV210_GPJ1_INT_FIXPRI (S5P_VA_GPIO + 0xB5C) + +#define S5PV210_GPJ2_INT_CON (S5P_VA_GPIO + 0x74C) +#define S5PV210_GPJ2_INT_FLTCON0 (S5P_VA_GPIO + 0x898) +#define S5PV210_GPJ2_INT_FLTCON1 (S5P_VA_GPIO + 0x89C) +#define S5PV210_GPJ2_INT_MASK (S5P_VA_GPIO + 0x94C) +#define S5PV210_GPJ2_INT_PEND (S5P_VA_GPIO + 0xA4C) +#define S5PV210_GPJ2_INT_FIXPRI (S5P_VA_GPIO + 0xB60) + +#define S5PV210_GPJ3_INT_CON (S5P_VA_GPIO + 0x750) +#define S5PV210_GPJ3_INT_FLTCON0 (S5P_VA_GPIO + 0x8A0) +#define S5PV210_GPJ3_INT_FLTCON1 (S5P_VA_GPIO + 0x8A4) +#define S5PV210_GPJ3_INT_MASK (S5P_VA_GPIO + 0x950) +#define S5PV210_GPJ3_INT_PEND (S5P_VA_GPIO + 0xA50) +#define S5PV210_GPJ3_INT_FIXPRI (S5P_VA_GPIO + 0xB64) + +#define S5PV210_GPJ4_INT_CON (S5P_VA_GPIO + 0x754) +#define S5PV210_GPJ4_INT_FLTCON0 (S5P_VA_GPIO + 0x8A8) +#define S5PV210_GPJ4_INT_FLTCON1 (S5P_VA_GPIO + 0x8AC) +#define S5PV210_GPJ4_INT_MASK (S5P_VA_GPIO + 0x954) +#define S5PV210_GPJ4_INT_PEND (S5P_VA_GPIO + 0xA54) +#define S5PV210_GPJ4_INT_FIXPRI (S5P_VA_GPIO + 0xB68) + +#define S5PV210_EXT_INT_GRPPRI (S5P_VA_GPIO + 0xB00) +#define S5PV210_EXT_INT_PRIO (S5P_VA_GPIO + 0xB04) +#define S5PV210_EXT_INT_SVC (S5P_VA_GPIO + 0xB08) +#define S5PV210_EXT_INT_SVC_PND (S5P_VA_GPIO + 0xB0C) +#define S5PV210_EXT_INT_GRPFIXPRI (S5P_VA_GPIO + 0xB10) + #define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00) #define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4)) #define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) -#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4)) +#define S5P_EINT_FLTCON(x,y) (S5PV210_EINT30FLTCON0 + ((x) * 0x8) + ((y) * 0x4)) #define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00) #define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4)) @@ -29,8 +248,16 @@ #define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) +#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq)-IRQ_EINT0)\ + : (irq-S5P_IRQ_EINT_BASE)) + #define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) +#define eint_conf_reg(irq) ((eint_offset(irq)) >> 3) +#define eint_filt_reg(irq) ((eint_offset(irq)) >> 2) +#define eint_mask_reg(irq) ((eint_offset(irq)) >> 3) +#define eint_pend_reg(irq) ((eint_offset(irq)) >> 3) + #define EINT_MODE S3C_GPIO_SFN(0xf) #define EINT_GPIO_0(x) S5PV210_GPH0(x) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h index 5c3b104..e3b86f1 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h @@ -16,4 +16,10 @@ #include <asm/hardware/vic.h> #include <mach/map.h> +/* interrupt controller */ +#define S5P_VIC0REG(x) ((x) + S5P_VA_VIC0) +#define S5P_VIC1REG(x) ((x) + S5P_VA_VIC1) +#define S5P_VIC2REG(x) ((x) + S5P_VA_VIC2) +#define S5P_VIC3REG(x) ((x) + S5P_VA_VIC3) + #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-mem.h b/arch/arm/mach-s5pv210/include/mach/regs-mem.h new file mode 100644 index 0000000..1c79d54 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-mem.h @@ -0,0 +1,28 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/regs-mem.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Memory Control register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MEM_H +#define __ASM_ARCH_REGS_MEM_H __FILE__ + +#include <mach/map.h> + +#define S5P_MEMREG(x) (S5P_VA_SROMC + (x)) + +#define S5P_SROM_BW S5P_MEMREG(0x00) +#define S5P_SROM_BC0 S5P_MEMREG(0x04) +#define S5P_SROM_BC1 S5P_MEMREG(0x08) +#define S5P_SROM_BC2 S5P_MEMREG(0x0C) +#define S5P_SROM_BC3 S5P_MEMREG(0x10) +#define S5P_SROM_BC4 S5P_MEMREG(0x14) +#define S5P_SROM_BC5 S5P_MEMREG(0x18) + +#endif /* __ASM_ARCH_REGS_MEM_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/sec_switch.h b/arch/arm/mach-s5pv210/include/mach/sec_switch.h new file mode 100644 index 0000000..c1e8f69 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/sec_switch.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2010 Samsung Electronics, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_SEC_SWITCH_H +#define __ASM_ARCH_SEC_SWITCH_H + +struct sec_switch_platform_data { + void (*set_vbus_status) (u8 mode); + void (*set_usb_gadget_vbus) (bool en); + int (*get_cable_status) (void); + int (*get_phy_init_status) (void); +}; + +#define SWITCH_MODEM 0 +#define SWITCH_PDA 1 + +#define USB_VBUS_ALL_OFF 0 +#define USB_VBUS_CP_ON 1 +#define USB_VBUS_AP_ON 2 +#define USB_VBUS_ALL_ON 3 + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/tick.h b/arch/arm/mach-s5pv210/include/mach/tick.h index 7993b36..9fc5a8d 100644 --- a/arch/arm/mach-s5pv210/include/mach/tick.h +++ b/arch/arm/mach-s5pv210/include/mach/tick.h @@ -21,6 +21,12 @@ static inline u32 s3c24xx_ostimer_pending(void) return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); } +static inline u32 s5p_ostimer_pending(void) +{ + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_SYSTIMER - S5P_IRQ_VIC0(0))); +} + #define TICK_MAX (0xffffffff) #endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h index a6c659d..223e21a 100644 --- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h +++ b/arch/arm/mach-s5pv210/include/mach/vmalloc.h @@ -17,6 +17,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H __FILE__ -#define VMALLOC_END 0xF6000000UL +#define VMALLOC_END (0xFC000000) #endif /* __ASM_ARCH_VMALLOC_H */ |