diff options
Diffstat (limited to 'arch/arm/mach-s5pv210')
73 files changed, 22980 insertions, 154 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 37b5a97..0ecf8ee 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -20,11 +20,15 @@ config CPU_S5PV210 config S5PV210_SETUP_I2C1 bool + default y + select HAVE_S3C2410_I2C help Common setup code for i2c bus 1. config S5PV210_SETUP_I2C2 bool + default y + select HAVE_S3C2410_I2C help Common setup code for i2c bus 2. @@ -59,6 +63,39 @@ config S5PV210_SETUP_FIMC help Common setup code for the camera interfaces. +config S5PV210_POWER_DOMAIN + bool + depends on REGULATOR + default y + help + Enable S5PV210 power domain support. + +config S5PV210_CORESIGHT + bool "Coresight" + select OC_ETM + default y + help + Support embedded trace cell + +comment "MMC/SD slot setup" +depends on PLAT_S5P + +menu "Use 8-bit bus width" +config S5PV210_SD_CH0_8BIT +bool "Channel 0" +depends on PLAT_S5P +default n +help +IF channel 0 uses 8-bit bus, channel 1 is disabled. + +config S5PV210_SD_CH2_8BIT +bool "Channel 2" +depends on PLAT_S5P +default n +help +IF channel 2 uses 8-bit bus, channel 3 is disabled. +endmenu + menu "S5PC110 Machines" config MACH_AQUILA @@ -108,6 +145,7 @@ config MACH_SMDKC110 select S3C_DEV_I2C1 select S3C_DEV_I2C2 select S3C_DEV_RTC + select HAVE_S3C_RTC select S3C_DEV_WDT select SAMSUNG_DEV_IDE select S5PV210_SETUP_I2C1 @@ -172,4 +210,157 @@ config S5PV210_PM help Power Management code common to S5PV210 +config MACH_HERRING + bool "Herring" + select CPU_S5PV210 + select S3C_DEV_WDT + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S5P_DEV_ONENAND + select HAVE_PWM + select SAMSUNG_DEV_PWM + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 if !S5PV210_SD_CH0_8BIT + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 if !S5PV210_SD_CH2_8BIT + select S5PV210_SETUP_SDHCI + select S5PV210_POWER_DOMAIN + select S5P_DEV_CSIS0 + select S5P_SETUP_MIPIPHY + help + Machine support for Herring + +config MACH_ARIES + bool "Aries" + select CPU_S5PV210 + select S3C_DEV_WDT + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S5P_DEV_ONENAND + select HAVE_PWM + select SAMSUNG_DEV_PWM + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 if !S5PV210_SD_CH0_8BIT + select S3C_DEV_HSMMC2 + select S5PV210_SETUP_SDHCI + select S5PV210_POWER_DOMAIN + select S5P_DEV_CSIS0 + select S5P_SETUP_MIPIPHY + help + Machine support for Aries + +if MACH_ARIES +choice + prompt "Select phone Type" + +config PHONE_ARIES + bool "select aries" + depends on MACH_ARIES + help + Select Aries Phone + +config PHONE_ARIES_CDMA + bool "select aries cdma" + depends on MACH_ARIES + help + Select Aries Cdma Phone + +config PHONE_CRESPO + bool "select crespo" + depends on MACH_ARIES + help + Select Crespo Phone + +endchoice + +choice + prompt "Select Device Type" + +config SAMSUNG_GALAXYS + bool "select GTI9000" + depends on MACH_ARIES + help + Select Samsung Galaxy S GT-I9000 + +config SAMSUNG_GALAXYSB + bool "select GTI9000B" + depends on MACH_ARIES + help + Select Samsung Galaxy S GT-I9000B + +config SAMSUNG_CAPTIVATE + bool "select SGHI897" + depends on MACH_ARIES + help + Select Samsung Captivate + +config SAMSUNG_VIBRANT + bool "select SGHT959" + depends on MACH_ARIES + help + Select Samsung Vibrant + +config SAMSUNG_FASCINATE + bool "select SCHI500" + depends on MACH_ARIES + help + Select Samsung Fascinate + +config SAMSUNG_EPIC + bool "select SPHD700" + depends on MACH_ARIES + help + Select Samsung Epic 4G +endchoice +endif + +config S5PV210_SETUP_FB + bool + depends on FB_S3C + default y + help + Common setup code for FIMD controller. + +config S5P_ADC + bool "S5PXXXX ADC driver" + depends on PLAT_S5P + default y + help + ADC ( A/D Conversion ) driver for Samsung S5PXXXX + +config S5PV210_SETUP_FIMC0 + bool + depends on VIDEO_FIMC || CPU_FREQ + default y + help + Common setup code for FIMC controller 0. + +config S5PV210_SETUP_FIMC1 + bool + depends on VIDEO_FIMC || CPU_FREQ + default y + help + Common setup code for FIMC controller 1. + +config S5PV210_SETUP_FIMC2 + bool + depends on VIDEO_FIMC || CPU_FREQ + default y + help + Common setup code for FIMC controller 2. + +config DVFS_LIMIT + bool "DVFS limit" + depends on CPU_FREQ + default n + +config CPU_DIDLE + bool "DEEP Idle" + depends on CPU_IDLE + default n + +config WIFI_CONTROL_FUNC + bool "Enable WiFi control function abstraction" + help + Enables Power/Reset/Carddetect function abstraction endif diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 50907ac..f146970 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -1,7 +1,7 @@ # arch/arm/mach-s5pv210/Makefile # # Copyright (c) 2010 Samsung Electronics Co., Ltd. -# http://www.samsung.com/ +# http://www.samsung.com/ # # Licensed under GPLv2 @@ -17,6 +17,9 @@ obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o +obj-$(CONFIG_S5PV210_POWER_DOMAIN) += power-domain.o +obj-$(CONFIG_S5PV210_CORESIGHT) += coresight.o + # machine support obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o @@ -24,13 +27,36 @@ obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o obj-$(CONFIG_MACH_GONI) += mach-goni.o obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o +obj-$(CONFIG_MACH_HERRING) += mach-herring.o herring-rfkill.o +obj-$(CONFIG_MACH_HERRING) += herring-vibrator.o +obj-$(CONFIG_MACH_HERRING) += herring-btlpm.o +obj-$(CONFIG_MACH_HERRING) += herring-watchdog.o +obj-$(CONFIG_MACH_HERRING) += herring-panel.o +obj-$(CONFIG_MACH_HERRING) += herring-touchkey-led.o + +obj-$(CONFIG_MACH_HERRING) += dev-herring-phone.o + +obj-$(CONFIG_MACH_ARIES) += mach-aries.o aries-rfkill.o +obj-$(CONFIG_MACH_ARIES) += aries-vibrator.o +obj-$(CONFIG_MACH_ARIES) += aries-btlpm.o +obj-$(CONFIG_MACH_ARIES) += aries-watchdog.o +obj-$(CONFIG_MACH_ARIES) += aries-panel.o +obj-$(CONFIG_PHONE_ARIES) += dev-s1-phone.o +obj-$(CONFIG_PHONE_ARIES) += level.o +obj-$(CONFIG_PHONE_ARIES_CDMA) += dev-s1-phone.o +obj-$(CONFIG_PHONE_ARIES_CDMA) += level.o +obj-$(CONFIG_PHONE_CRESPO) += dev-aries-phone.o # device support obj-y += dev-audio.o +obj-y += dev-fiqdbg.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o -obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o + +obj-$(CONFIG_S5P_ADC) += adc.o + +obj-$(CONFIG_S5PV210_SETUP_FB) += setup-fb.o obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o @@ -38,3 +64,9 @@ obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o +obj-$(CONFIG_S5PV210_SETUP_FIMC0) += setup-fimc0.o +obj-$(CONFIG_S5PV210_SETUP_FIMC1) += setup-fimc1.o +obj-$(CONFIG_S5PV210_SETUP_FIMC2) += setup-fimc2.o + +obj-$(CONFIG_CPU_IDLE) += cpuidle.o +obj-$(CONFIG_CPU_FREQ) += dev-cpufreq.o diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot index ff90aa1..667f731 100644 --- a/arch/arm/mach-s5pv210/Makefile.boot +++ b/arch/arm/mach-s5pv210/Makefile.boot @@ -1,2 +1,10 @@ - zreladdr-y := 0x20008000 +zreladdr-y := 0x20008000 params_phys-y := 0x20000100 + +# override for Herring +zreladdr-$(CONFIG_MACH_HERRING) := 0x30008000 +params_phys-$(CONFIG_MACH_HERRING) := 0x30000100 + +# override for Aries +zreladdr-$(CONFIG_MACH_ARIES) := 0x30008000 +params_phys-$(CONFIG_MACH_ARIES) := 0x30000100
\ No newline at end of file diff --git a/arch/arm/mach-s5pv210/adc.c b/arch/arm/mach-s5pv210/adc.c new file mode 100644 index 0000000..d7945fb --- /dev/null +++ b/arch/arm/mach-s5pv210/adc.c @@ -0,0 +1,401 @@ +/* linux/arch/arm/mach-s5pv210/adc.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> + * iPAQ H1940 touchscreen support + * + * ChangeLog + * + * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at> + * - added clock (de-)allocation code + * + * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org> + * - h1940_ -> s3c24xx (this driver is now also used on the n30 + * machines :P) + * - Debug messages are now enabled with the config option + * TOUCHSCREEN_S3C_DEBUG + * - Changed the way the value are read + * - Input subsystem should now work + * - Use ioremap and readl/writel + * + * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org> + * - Make use of some undocumented features of the touchscreen + * controller + * + */ + + +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/input.h> +#include <linux/init.h> +#include <linux/serio.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/miscdevice.h> +#include <linux/clk.h> +#include <linux/mutex.h> +#include <linux/io.h> +#include <linux/uaccess.h> + +#include <asm/irq.h> +#include <mach/hardware.h> +#include <linux/uaccess.h> + +#include <mach/regs-adc.h> +#include <mach/adc.h> +#include <mach/irqs.h> + +#define ADC_MINOR 131 +#define ADC_INPUT_PIN _IOW('S', 0x0c, unsigned long) + +#define ADC_WITH_TOUCHSCREEN + +static struct clk *adc_clock; + +static void __iomem *base_addr; +static int adc_port; +struct s3c_adc_mach_info *plat_data; + +#ifdef ADC_WITH_TOUCHSCREEN +static DEFINE_MUTEX(adc_mutex); + +static unsigned long data_for_ADCCON; +static unsigned long data_for_ADCTSC; + +static void s3c_adc_save_SFR_on_ADC(void) +{ + data_for_ADCCON = readl(base_addr + S3C_ADCCON); + data_for_ADCTSC = readl(base_addr + S3C_ADCTSC); +} + +static void s3c_adc_restore_SFR_on_ADC(void) +{ + writel(data_for_ADCCON, base_addr + S3C_ADCCON); + writel(data_for_ADCTSC, base_addr + S3C_ADCTSC); +} +#else +static struct resource *adc_mem; +#endif + +static int s3c_adc_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static unsigned int s3c_adc_convert(void) +{ + unsigned int adc_return = 0; + unsigned long data0; + unsigned long data1; + + writel((readl(base_addr + S3C_ADCCON) | S3C_ADCCON_PRSCEN) & ~S3C_ADCCON_STDBM, + base_addr + S3C_ADCCON); + + writel((adc_port & 0xF), base_addr + S3C_ADCMUX); + + udelay(10); + + writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_ENABLE_START, + base_addr + S3C_ADCCON); + + do { + data0 = readl(base_addr + S3C_ADCCON); + } while (!(data0 & S3C_ADCCON_ECFLG)); + + data1 = readl(base_addr + S3C_ADCDAT0); + + writel((readl(base_addr + S3C_ADCCON) | S3C_ADCCON_STDBM) & ~S3C_ADCCON_PRSCEN, + base_addr + S3C_ADCCON); + + if (plat_data->resolution == 12) + adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT; + else + adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK; + + return adc_return; +} + + +int s3c_adc_get_adc_data(int channel) +{ + int adc_value = 0; + int cur_adc_port = 0; + +#ifdef ADC_WITH_TOUCHSCREEN + mutex_lock(&adc_mutex); + s3c_adc_save_SFR_on_ADC(); +#else + mutex_lock(&adc_mutex); +#endif + + cur_adc_port = adc_port; + adc_port = channel; + + adc_value = s3c_adc_convert(); + + adc_port = cur_adc_port; + +#ifdef ADC_WITH_TOUCHSCREEN + s3c_adc_restore_SFR_on_ADC(); + mutex_unlock(&adc_mutex); +#else + mutex_unlock(&adc_mutex); +#endif + + pr_debug("%s : Converted Value: %03d\n", __func__, adc_value); + + return adc_value; +} +EXPORT_SYMBOL(s3c_adc_get_adc_data); + +int s3c_adc_get(struct s3c_adc_request *req) +{ + unsigned adc_channel = req->channel; + int adc_value_ret = 0; + + adc_value_ret = s3c_adc_convert(); + + req->callback(adc_channel, req->param, adc_value_ret); + + return 0; +} +EXPORT_SYMBOL(s3c_adc_get); + +static ssize_t +s3c_adc_read(struct file *file, char __user *buffer, + size_t size, loff_t *pos) +{ + int adc_value = 0; + +#ifdef ADC_WITH_TOUCHSCREEN + mutex_lock(&adc_mutex); + s3c_adc_save_SFR_on_ADC(); +#endif + printk(KERN_INFO "## delay: %d\n", readl(base_addr + S3C_ADCDLY)); + adc_value = s3c_adc_convert(); + +#ifdef ADC_WITH_TOUCHSCREEN + s3c_adc_restore_SFR_on_ADC(); + mutex_unlock(&adc_mutex); +#endif + + if (copy_to_user(buffer, &adc_value, sizeof(unsigned int))) + return -EFAULT; + + return sizeof(unsigned int); +} + + +static long s3c_adc_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + + switch (cmd) { + case ADC_INPUT_PIN: + adc_port = (unsigned int) arg; + + if (adc_port >= 4) + printk(KERN_WARNING + " %d is already reserved for TouchScreen\n", + adc_port); + return 0; + + default: + return -ENOIOCTLCMD; + } +} + +static const struct file_operations s3c_adc_fops = { + .owner = THIS_MODULE, + .read = s3c_adc_read, + .open = s3c_adc_open, + .unlocked_ioctl = s3c_adc_ioctl, +}; + +static struct miscdevice s3c_adc_miscdev = { + .minor = ADC_MINOR, + .name = "adc", + .fops = &s3c_adc_fops, +}; + +static struct s3c_adc_mach_info *s3c_adc_get_platdata(struct device *dev) +{ + if (dev->platform_data != NULL) + return (struct s3c_adc_mach_info *) dev->platform_data; + else + return 0; +} + +/* + * The functions for inserting/removing us as a module. + */ + +static int __devinit s3c_adc_probe(struct platform_device *pdev) +{ + struct resource *res; + struct device *dev; + int ret; + int size; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dev = &pdev->dev; + + if (res == NULL) { + dev_err(dev, "no memory resource specified\n"); + return -ENOENT; + } + + size = (res->end - res->start) + 1; + +#if !defined(ADC_WITH_TOUCHSCREEN) + adc_mem = request_mem_region(res->start, size, pdev->name); + if (adc_mem == NULL) { + dev_err(dev, "failed to get memory region\n"); + ret = -ENOENT; + goto err_req; + } +#endif + + base_addr = ioremap(res->start, size); + if (base_addr == NULL) { + dev_err(dev, "fail to ioremap() region\n"); + ret = -ENOENT; + goto err_map; + } + + adc_clock = clk_get(&pdev->dev, "adc"); + + if (IS_ERR(adc_clock)) { + dev_err(dev, "failed to fine ADC clock source\n"); + ret = PTR_ERR(adc_clock); + goto err_clk; + } + + clk_enable(adc_clock); + + /* read platform data from device struct */ + plat_data = s3c_adc_get_platdata(&pdev->dev); + + if ((plat_data->presc & 0xff) > 0) + writel(S3C_ADCCON_PRSCEN | + S3C_ADCCON_PRSCVL(plat_data->presc & 0xff), + base_addr + S3C_ADCCON); + else + writel(0, base_addr + S3C_ADCCON); + + /* Initialise registers */ + if ((plat_data->delay & 0xffff) > 0) + writel(plat_data->delay & 0xffff, base_addr + S3C_ADCDLY); + + if (plat_data->resolution == 12) + writel(readl(base_addr + S3C_ADCCON) | + S3C_ADCCON_RESSEL_12BIT, base_addr + S3C_ADCCON); + + writel((readl(base_addr + S3C_ADCCON) | S3C_ADCCON_STDBM) & ~S3C_ADCCON_PRSCEN, + base_addr + S3C_ADCCON); + + ret = misc_register(&s3c_adc_miscdev); + if (ret) { + printk(KERN_ERR "cannot register miscdev on minor=%d (%d)\n", + ADC_MINOR, ret); + goto err_clk; + } + + return 0; + +err_clk: + clk_disable(adc_clock); + clk_put(adc_clock); + +err_map: + iounmap(base_addr); + +#if !defined(ADC_WITH_TOUCHSCREEN) +err_req: + release_resource(adc_mem); + kfree(adc_mem); +#endif + + return ret; +} + + +static int s3c_adc_remove(struct platform_device *dev) +{ + clk_disable(adc_clock); + clk_put(adc_clock); + return 0; +} + +#ifdef CONFIG_PM +static unsigned int adccon, adctsc, adcdly; + +static int s3c_adc_suspend(struct platform_device *dev, pm_message_t state) +{ + adccon = readl(base_addr + S3C_ADCCON); + adctsc = readl(base_addr + S3C_ADCTSC); + adcdly = readl(base_addr + S3C_ADCDLY); + + return 0; +} + +static int s3c_adc_resume(struct platform_device *pdev) +{ + writel(adccon, base_addr + S3C_ADCCON); + writel(adctsc, base_addr + S3C_ADCTSC); + writel(adcdly, base_addr + S3C_ADCDLY); + + return 0; +} +#else +#define s3c_adc_suspend NULL +#define s3c_adc_resume NULL +#endif + +static struct platform_driver s3c_adc_driver = { + .probe = s3c_adc_probe, + .remove = s3c_adc_remove, + .suspend = s3c_adc_suspend, + .resume = s3c_adc_resume, + .driver = { + .owner = THIS_MODULE, + .name = "s3c-adc", + }, +}; + +static char banner[] __initdata = KERN_INFO \ + "S5PV210 ADC driver, (c) 2010 Samsung Electronics\n"; + +int __init s3c_adc_init(void) +{ + printk(banner); + return platform_driver_register(&s3c_adc_driver); +} + +void __exit s3c_adc_exit(void) +{ + platform_driver_unregister(&s3c_adc_driver); +} + +module_init(s3c_adc_init); +module_exit(s3c_adc_exit); + +MODULE_AUTHOR("dsfine.ha@samsung.com"); +MODULE_DESCRIPTION("S5PV210 ADC driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/aries-btlpm.c b/arch/arm/mach-s5pv210/aries-btlpm.c new file mode 100644 index 0000000..6ff9f67 --- /dev/null +++ b/arch/arm/mach-s5pv210/aries-btlpm.c @@ -0,0 +1,66 @@ +/* linux/arch/arm/mach-s5pv210/aries-btlpm.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/hrtimer.h> + +#include <asm/mach-types.h> + +#include <mach/gpio-aries.h> + +#include "aries.h" + +static struct aries_bt_lpm { + struct hrtimer bt_lpm_timer; + ktime_t bt_lpm_delay; +} bt_lpm; + +static enum hrtimer_restart bt_enter_lpm(struct hrtimer *timer) +{ + gpio_set_value(GPIO_BT_WAKE, 0); + + return HRTIMER_NORESTART; +} + +void aries_bt_uart_wake_peer(struct uart_port *port) +{ + if (!bt_lpm.bt_lpm_timer.function) + return; + + hrtimer_try_to_cancel(&bt_lpm.bt_lpm_timer); + gpio_set_value(GPIO_BT_WAKE, 1); + hrtimer_start(&bt_lpm.bt_lpm_timer, bt_lpm.bt_lpm_delay, HRTIMER_MODE_REL); +} + +static int __init bt_lpm_init(void) +{ + int ret; + + if (!machine_is_aries()) + return 0; + + ret = gpio_request(GPIO_BT_WAKE, "gpio_bt_wake"); + if (ret) { + printk(KERN_ERR "Failed to request gpio_bt_wake control\n"); + return 0; + } + + gpio_direction_output(GPIO_BT_WAKE, GPIO_LEVEL_LOW); + + hrtimer_init(&bt_lpm.bt_lpm_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + bt_lpm.bt_lpm_delay = ktime_set(1, 0); /* 1 sec */ + bt_lpm.bt_lpm_timer.function = bt_enter_lpm; + return 0; +} +device_initcall(bt_lpm_init); diff --git a/arch/arm/mach-s5pv210/aries-panel.c b/arch/arm/mach-s5pv210/aries-panel.c new file mode 100644 index 0000000..933f272 --- /dev/null +++ b/arch/arm/mach-s5pv210/aries-panel.c @@ -0,0 +1,360 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/tl2796.h> +#include <linux/nt35580.h> +#include <mach/gpio.h> +#include <linux/delay.h> + +static const u16 s6e63m0_SEQ_STANDBY_ON[] = { + 0x010, /* Stand-by On Command */ + SLEEPMSEC, 160, + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_STANDBY_OFF[] = { + 0x011, /* Stand-by Off Command */ + SLEEPMSEC, 120, + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_DISPLAY_SETTING[] = { + SLEEPMSEC, 10, + 0x0F8, /* Panel Condition Set Command*/ + 0x101, /* DOCT */ + 0x127, /* CLWEA */ + 0x127, /* CLWEB*/ + 0x107, /* CLTE */ + 0x107, /* SHE */ + 0x154, /* FLTE */ + 0x19F, /* FLWE */ + 0x163, /* SCTE */ + 0x186, /* SCWE */ + 0x11A, /* INTE */ + 0x133, /* INWE */ + 0x10D, /* EMPS */ + 0x100, /* E_INTE */ + 0x100, /* E_INWE */ + 0x0F2, /* Display Condition Set Command*/ + 0x102, /* Number of Line */ + 0x103, /* VBP */ + 0x11C, /* VFP */ + 0x110, /* HBP */ + 0x110, /* HFP */ + 0x0F7, /* Command */ + 0x103, /* GTCON */ + 0x100, /* Display Mode */ + 0x100, /* Vsync/Hsync, DOCCLK, RGB mode */ + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_ETC_SETTING[] = { + /* ETC Condition Set Command */ + 0x0F6, + 0x100, 0x18E, + 0x107, + 0x0B3, + 0x16C, + 0x0B5, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0B6, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x0B7, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0B8, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x0B9, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0BA, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x011, + SLEEPMSEC, 120, + 0x029, + ENDDEF, 0x0000 +}; + +static const struct tl2796_gamma_adj_points gamma_adj_points = { + .v0 = 0, + .v1 = BV_1, + .v19 = BV_19, + .v43 = BV_43, + .v87 = BV_87, + .v171 = BV_171, + .v255 = BV_255, +}; + +static const struct gamma_entry gamma_table[] = { + { BV_0, { 4200000, 4200000, 4200000, }, }, + { 1, { 3994200, 4107600, 3910200, }, }, + { 0x00000400, { 3669486, 3738030, 3655093, }, }, + { 0x000004C2, { 3664456, 3732059, 3649872, }, }, + { 0x000005A8, { 3659356, 3726019, 3644574, }, }, + { 0x000006BA, { 3654160, 3719879, 3639171, }, }, + { 0x00000800, { 3648872, 3713646, 3633668, }, }, + { 0x00000983, { 3643502, 3707331, 3628075, }, }, + { 0x00000B50, { 3638029, 3700909, 3622368, }, }, + { 0x00000D74, { 3632461, 3694392, 3616558, }, }, + { 0x00001000, { 3626792, 3687772, 3610636, }, }, + { 0x00001307, { 3621022, 3681052, 3604605, }, }, + { 0x000016A1, { 3615146, 3674224, 3598455, }, }, + { 0x00001AE9, { 3609163, 3667289, 3592189, }, }, + { 0x00002000, { 3603070, 3660245, 3585801, }, }, + { 0x0000260E, { 3596860, 3653083, 3579284, }, }, + { 0x00002D41, { 3590532, 3645805, 3572637, }, }, + { 0x000035D1, { 3584081, 3638403, 3565854, }, }, + { 0x00004000, { 3577504, 3630876, 3558930, }, }, + { 0x00004C1C, { 3570797, 3623221, 3551863, }, }, + { 0x00005A82, { 3563956, 3615434, 3544649, }, }, + { 0x00006BA2, { 3556976, 3607510, 3537279, }, }, + { 0x00008000, { 3549853, 3599444, 3529750, }, }, + { 0x00009838, { 3542582, 3591234, 3522056, }, }, + { 0x0000B505, { 3535159, 3582874, 3514193, }, }, + { 0x0000D745, { 3527577, 3574360, 3506153, }, }, + { 0x00010000, { 3519832, 3565687, 3497931, }, }, + { 0x00013070, { 3511918, 3556849, 3489519, }, }, + { 0x00016A0A, { 3503829, 3547842, 3480912, }, }, + { 0x0001AE8A, { 3495559, 3538659, 3472102, }, }, + { 0x00020000, { 3487101, 3529295, 3463080, }, }, + { 0x000260E0, { 3478447, 3519742, 3453839, }, }, + { 0x0002D414, { 3469592, 3509996, 3444372, }, }, + { 0x00035D14, { 3460527, 3500049, 3434667, }, }, + { 0x00040000, { 3451244, 3489893, 3424717, }, }, + { 0x0004C1C0, { 3441734, 3479522, 3414512, }, }, + { 0x0005A828, { 3431990, 3468927, 3404040, }, }, + { 0x0006BA28, { 3422000, 3458099, 3393292, }, }, + { 0x00080000, { 3411756, 3447030, 3382254, }, }, + { 0x0009837F, { 3401247, 3435711, 3370915, }, }, + { 0x000B504F, { 3390462, 3424131, 3359262, }, }, + { 0x000D7450, { 3379388, 3412280, 3347281, }, }, + { 0x00100000, { 3368014, 3400147, 3334957, }, }, + { 0x001306FE, { 3356325, 3387721, 3322274, }, }, + { 0x0016A09E, { 3344309, 3374988, 3309216, }, }, + { 0x001AE8A0, { 3331950, 3361936, 3295765, }, }, + { 0x00200000, { 3319231, 3348550, 3281902, }, }, + { 0x00260DFC, { 3306137, 3334817, 3267607, }, }, + { 0x002D413D, { 3292649, 3320719, 3252859, }, }, + { 0x0035D13F, { 3278748, 3306240, 3237634, }, }, + { 0x00400000, { 3264413, 3291361, 3221908, }, }, + { 0x004C1BF8, { 3249622, 3276065, 3205654, }, }, + { 0x005A827A, { 3234351, 3260329, 3188845, }, }, + { 0x006BA27E, { 3218576, 3244131, 3171449, }, }, + { 0x00800000, { 3202268, 3227448, 3153434, }, }, + { 0x009837F0, { 3185399, 3210255, 3134765, }, }, + { 0x00B504F3, { 3167936, 3192523, 3115404, }, }, + { 0x00D744FD, { 3149847, 3174223, 3095308, }, }, + { 0x01000000, { 3131093, 3155322, 3074435, }, }, + { 0x01306FE1, { 3111635, 3135786, 3052735, }, }, + { 0x016A09E6, { 3091431, 3115578, 3030156, }, }, + { 0x01AE89FA, { 3070432, 3094655, 3006641, }, }, + { 0x02000000, { 3048587, 3072974, 2982127, }, }, + { 0x0260DFC1, { 3025842, 3050485, 2956547, }, }, + { 0x02D413CD, { 3002134, 3027135, 2929824, }, }, + { 0x035D13F3, { 2977397, 3002865, 2901879, }, }, + { 0x04000000, { 2951558, 2977611, 2872620, }, }, + { 0x04C1BF83, { 2924535, 2951302, 2841948, }, }, + { 0x05A8279A, { 2896240, 2923858, 2809753, }, }, + { 0x06BA27E6, { 2866574, 2895192, 2775914, }, }, + { 0x08000000, { 2835426, 2865207, 2740295, }, }, + { 0x09837F05, { 2802676, 2833793, 2702744, }, }, + { 0x0B504F33, { 2768187, 2800829, 2663094, }, }, + { 0x0D744FCD, { 2731806, 2766175, 2621155, }, }, + { 0x10000000, { 2693361, 2729675, 2576712, }, }, + { 0x1306FE0A, { 2652659, 2691153, 2529527, }, }, + { 0x16A09E66, { 2609480, 2650402, 2479324, }, }, + { 0x1AE89F99, { 2563575, 2607191, 2425793, }, }, + { 0x20000000, { 2514655, 2561246, 2368579, }, }, + { 0x260DFC14, { 2462394, 2512251, 2307272, }, }, + { 0x2D413CCD, { 2406412, 2459834, 2241403, }, }, + { 0x35D13F32, { 2346266, 2403554, 2170425, }, }, + { 0x40000000, { 2281441, 2342883, 2093706, }, }, + { 0x4C1BF828, { 2211332, 2277183, 2010504, }, }, + { 0x5A82799A, { 2135220, 2205675, 1919951, }, }, + { 0x6BA27E65, { 2052250, 2127391, 1821028, }, }, + { 0x80000000, { 1961395, 2041114, 1712536, }, }, + { 0x9837F051, { 1861415, 1945288, 1593066, }, }, + { 0xB504F333, { 1750800, 1837874, 1460986, }, }, + { 0xD744FCCA, { 1627706, 1716150, 1314437, }, }, + { 0xFFFFFFFF, { 1489879, 1576363, 1151415, }, }, +}; + +static void reset_lcd(struct s5p_panel_data *pdata) +{ + gpio_direction_output(pdata->gpio_rst, 1); + msleep(10); + + gpio_set_value(pdata->gpio_rst, 0); + msleep(10); + + gpio_set_value(pdata->gpio_rst, 1); + msleep(10); +} + +static int configure_mtp_gpios(struct s5p_panel_data *pdata, bool enable) +{ + int i; + int ret = 0; + if (enable) { + /* wrx and csx are already requested by the spi driver */ + ret = gpio_request(pdata->gpio_rdx, "tl2796_rdx"); + if (ret) + goto err_rdx; + ret = gpio_request(pdata->gpio_dcx, "tl2796_dcx"); + if (ret) + goto err_dcx; + ret = gpio_request(pdata->gpio_rst, "tl2796_rst"); + if (ret) + goto err_rst; + for (i = 0; i < 8; i++) { + ret = gpio_request(pdata->gpio_db[i], "tl2796_dbx"); + if (ret) + goto err_dbx; + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF0(i), 0); + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_UP); + gpio_set_value(S5PV210_GPF1(i), 0); + } + return 0; + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + reset_lcd(pdata); + + for (i = 7; i >= 0; i--) { + gpio_free(pdata->gpio_db[i]); +err_dbx: + ; + } + gpio_free(pdata->gpio_rst); +err_rst: + gpio_free(pdata->gpio_dcx); +err_dcx: + gpio_free(pdata->gpio_rdx); +err_rdx: + return ret; +} + +struct s5p_panel_data aries_panel_data = { + .seq_display_set = s6e63m0_SEQ_DISPLAY_SETTING, + .seq_etc_set = s6e63m0_SEQ_ETC_SETTING, + .standby_on = s6e63m0_SEQ_STANDBY_ON, + .standby_off = s6e63m0_SEQ_STANDBY_OFF, + .gpio_dcx = S5PV210_GPF0(0), /* H_SYNC pad */ + .gpio_rdx = S5PV210_GPF0(2), /* Enable */ + .gpio_csx = S5PV210_MP01(1), + .gpio_wrx = S5PV210_MP04(1), /* SCL pad */ + .gpio_rst = S5PV210_MP05(5), + .gpio_db = { + S5PV210_GPF0(4), + S5PV210_GPF0(5), + S5PV210_GPF0(6), + S5PV210_GPF0(7), + S5PV210_GPF1(0), + S5PV210_GPF1(1), + S5PV210_GPF1(2), + S5PV210_GPF1(3), + }, + .configure_mtp_gpios = configure_mtp_gpios, + .factory_v255_regs = { + 0x0b9, + 0x0b8, + 0x0fc, + }, + .gamma_adj_points = &gamma_adj_points, + .gamma_table = gamma_table, + .gamma_table_size = ARRAY_SIZE(gamma_table), +}; + diff --git a/arch/arm/mach-s5pv210/aries-rfkill.c b/arch/arm/mach-s5pv210/aries-rfkill.c new file mode 100644 index 0000000..6cbc52e --- /dev/null +++ b/arch/arm/mach-s5pv210/aries-rfkill.c @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co., Ltd. + * + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Modified for Crespo on August, 2010 By Samsung Electronics Co. + * This is modified operate according to each status. + * + */ + +/* Control bluetooth power for Crespo platform */ + +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/rfkill.h> +#include <linux/delay.h> +#include <linux/types.h> +#include <linux/wakelock.h> +#include <linux/irq.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <mach/gpio.h> +#include <mach/gpio-aries.h> +#include <mach/hardware.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> +#include "aries.h" + +#define IRQ_BT_HOST_WAKE IRQ_EINT(21) + +static struct wake_lock rfkill_wake_lock; + +#ifndef GPIO_LEVEL_LOW +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#endif + +static struct rfkill *bt_rfk; +static const char bt_name[] = "bcm4329"; + +static int bluetooth_set_power(void *data, enum rfkill_user_states state) +{ + int ret = 0; + int irq; + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + switch (state) { + + case RFKILL_USER_STATE_UNBLOCKED: + pr_debug("[BT] Device Powering ON\n"); + + s3c_setup_uart_cfg_gpio(0); + + if (gpio_is_valid(GPIO_WLAN_BT_EN)) + gpio_direction_output(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + if (gpio_is_valid(GPIO_BT_nRST)) + gpio_direction_output(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* Set GPIO_BT_WLAN_REG_ON high */ + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + /* + * FIXME sleep should be enabled disabled since the device is + * not booting if its enabled + */ + /* + * 100msec, delay between reg_on & rst. + * (bcm4329 powerup sequence) + */ + msleep(100); + + /* Set GPIO_BT_nRST high */ + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* + * 50msec, delay after bt rst + * (bcm4329 powerup sequence) + */ + msleep(50); + + ret = enable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] set wakeup src failed\n"); + + enable_irq(irq); + break; + + case RFKILL_USER_STATE_SOFT_BLOCKED: + pr_debug("[BT] Device Powering OFF\n"); + + ret = disable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] unset wakeup src failed\n"); + + disable_irq(irq); + wake_unlock(&rfkill_wake_lock); + + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + if (gpio_get_value(GPIO_WLAN_nRST) == 0) { + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + } + + break; + + default: + pr_err("[BT] Bad bluetooth rfkill state %d\n", state); + } + + return 0; +} + +irqreturn_t bt_host_wake_irq_handler(int irq, void *dev_id) +{ + pr_debug("[BT] bt_host_wake_irq_handler start\n"); + + if (gpio_get_value(GPIO_BT_HOST_WAKE)) + wake_lock(&rfkill_wake_lock); + else + wake_lock_timeout(&rfkill_wake_lock, HZ); + + return IRQ_HANDLED; +} + +static int bt_rfkill_set_block(void *data, bool blocked) +{ + unsigned int ret = 0; + + ret = bluetooth_set_power(data, blocked ? + RFKILL_USER_STATE_SOFT_BLOCKED : + RFKILL_USER_STATE_UNBLOCKED); + + return ret; +} + +static const struct rfkill_ops bt_rfkill_ops = { + .set_block = bt_rfkill_set_block, +}; + +static int __init aries_rfkill_probe(struct platform_device *pdev) +{ + int irq; + int ret; + + /* Initialize wake locks */ + wake_lock_init(&rfkill_wake_lock, WAKE_LOCK_SUSPEND, "bt_host_wake"); + + ret = gpio_request(GPIO_WLAN_BT_EN, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_WLAN_BT_EN!\n"); + goto err_req_gpio_wlan_bt_en; + } + + ret = gpio_request(GPIO_BT_nRST, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_BT_nRST!\n"); + goto err_req_gpio_bt_nrst; + } + + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + ret = request_irq(irq, bt_host_wake_irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "bt_host_wake_irq_handler", NULL); + + if (ret < 0) { + pr_err("[BT] Request_irq failed\n"); + goto err_req_irq; + } + + disable_irq(irq); + + bt_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &bt_rfkill_ops, NULL); + + if (!bt_rfk) { + pr_err("[BT] bt_rfk : rfkill_alloc is failed\n"); + ret = -ENOMEM; + goto err_alloc; + } + + rfkill_init_sw_state(bt_rfk, 0); + + pr_debug("[BT] rfkill_register(bt_rfk)\n"); + + ret = rfkill_register(bt_rfk); + if (ret) { + pr_debug("********ERROR IN REGISTERING THE RFKILL********\n"); + goto err_register; + } + + rfkill_set_sw_state(bt_rfk, 1); + bluetooth_set_power(NULL, RFKILL_USER_STATE_SOFT_BLOCKED); + + return ret; + + err_register: + rfkill_destroy(bt_rfk); + + err_alloc: + free_irq(irq, NULL); + + err_req_irq: + gpio_free(GPIO_BT_nRST); + + err_req_gpio_bt_nrst: + gpio_free(GPIO_WLAN_BT_EN); + + err_req_gpio_wlan_bt_en: + return ret; +} + +static struct platform_driver aries_device_rfkill = { + .probe = aries_rfkill_probe, + .driver = { + .name = "bt_rfkill", + .owner = THIS_MODULE, + }, +}; + +static int __init aries_rfkill_init(void) +{ + int rc = 0; + rc = platform_driver_register(&aries_device_rfkill); + + return rc; +} + +module_init(aries_rfkill_init); +MODULE_DESCRIPTION("aries rfkill"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/aries-touchkey-led.c b/arch/arm/mach-s5pv210/aries-touchkey-led.c new file mode 100644 index 0000000..843516c --- /dev/null +++ b/arch/arm/mach-s5pv210/aries-touchkey-led.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. All Rights Reserved. + * Author: Rom Lemarchand <rlemarchand@sta.samsung.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/earlysuspend.h> +#include <asm/mach-types.h> + +static int led_gpios[] = { 2, 3, 6, 7 }; + +static void aries_touchkey_led_onoff(int onoff) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) + gpio_direction_output(S5PV210_GPJ3(led_gpios[i]), !!onoff); +} + +static void aries_touchkey_led_early_suspend(struct early_suspend *h) +{ + aries_touchkey_led_onoff(0); +} + +static void aries_touchkey_led_late_resume(struct early_suspend *h) +{ + aries_touchkey_led_onoff(1); +} + +static struct early_suspend early_suspend = { + .level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1, + .suspend = aries_touchkey_led_early_suspend, + .resume = aries_touchkey_led_late_resume, +}; + +static int __init aries_init_touchkey_led(void) +{ + int i; + int ret = 0; + + if (!machine_is_aries() || system_rev < 0x10) + return 0; + + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) { + ret = gpio_request(S5PV210_GPJ3(led_gpios[i]), "touchkey led"); + if (ret) { + pr_err("Failed to request touchkey led gpio %d\n", i); + goto err_req; + } + s3c_gpio_setpull(S5PV210_GPJ3(led_gpios[i]), + S3C_GPIO_PULL_NONE); + } + + aries_touchkey_led_onoff(1); + + register_early_suspend(&early_suspend); + + return 0; + +err_req: + while (--i >= 0) + gpio_free(S5PV210_GPJ3(led_gpios[i])); + return ret; +} + +device_initcall(aries_init_touchkey_led); diff --git a/arch/arm/mach-s5pv210/aries-vibrator.c b/arch/arm/mach-s5pv210/aries-vibrator.c new file mode 100644 index 0000000..0397a81 --- /dev/null +++ b/arch/arm/mach-s5pv210/aries-vibrator.c @@ -0,0 +1,197 @@ +/* arch/arm/mach-s5pv210/aries-vibrator.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. All Rights Reserved. + * Author: Rom Lemarchand <rlemarchand@sta.samsung.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/hrtimer.h> +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/pwm.h> +#include <linux/wakelock.h> +#include <linux/mutex.h> +#include <linux/clk.h> +#include <linux/workqueue.h> + +#include <asm/mach-types.h> + +#include <../../../drivers/staging/android/timed_output.h> + +#include <mach/gpio-aries.h> + +#include <linux/device.h> +#include <linux/miscdevice.h> + +#define GPD0_TOUT_1 2 << 4 + +#ifdef CONFIG_SAMSUNG_VIBRANT +#define PWM_PERIOD (87084 / 2) +#define PWM_DUTY_MAX (87000 / 2) +#else +#define PWM_PERIOD (89284 / 2) +#define PWM_DUTY_MAX (87280 / 2) +#endif + +#define MAX_TIMEOUT 10000 /* 10s */ + +#define PWM_DUTY_MIN 22340 +static unsigned int multiplier = (PWM_DUTY_MAX - PWM_DUTY_MIN) / 100; +static unsigned int pwm_duty = 100; +static unsigned int pwm_duty_value = PWM_DUTY_MAX; + +static struct vibrator { + struct wake_lock wklock; + struct pwm_device *pwm_dev; + struct hrtimer timer; + struct mutex lock; + struct work_struct work; +} vibdata; + +static void aries_vibrator_off(void) +{ + pwm_disable(vibdata.pwm_dev); + gpio_direction_output(GPIO_VIBTONE_EN1, GPIO_LEVEL_LOW); + wake_unlock(&vibdata.wklock); +} + +static int aries_vibrator_get_time(struct timed_output_dev *dev) +{ + if (hrtimer_active(&vibdata.timer)) { + ktime_t r = hrtimer_get_remaining(&vibdata.timer); + return ktime_to_ms(r); + } + + return 0; +} + +static void aries_vibrator_enable(struct timed_output_dev *dev, int value) +{ + mutex_lock(&vibdata.lock); + + /* cancel previous timer and set GPIO according to value */ + hrtimer_cancel(&vibdata.timer); + cancel_work_sync(&vibdata.work); + if (value) { + wake_lock(&vibdata.wklock); + pwm_config(vibdata.pwm_dev, pwm_duty_value, PWM_PERIOD); + pwm_enable(vibdata.pwm_dev); + gpio_direction_output(GPIO_VIBTONE_EN1, GPIO_LEVEL_HIGH); + + if (value > 0) { + if (value > MAX_TIMEOUT) + value = MAX_TIMEOUT; + + hrtimer_start(&vibdata.timer, + ns_to_ktime((u64)value * NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + } else + aries_vibrator_off(); + + mutex_unlock(&vibdata.lock); +} + +static ssize_t aries_vibrator_set_duty(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + sscanf(buf, "%d\n", &pwm_duty); + if (pwm_duty >= 0 && pwm_duty <= 100) pwm_duty_value = (pwm_duty * multiplier) + PWM_DUTY_MIN; + return size; +} +static ssize_t aries_vibrator_show_duty(struct device *dev, + struct device_attribute *attr, + const char *buf) +{ + return sprintf(buf, "%d", pwm_duty); +} +static DEVICE_ATTR(pwm_duty, S_IRUGO | S_IWUGO, aries_vibrator_show_duty, aries_vibrator_set_duty); +static struct attribute *pwm_duty_attributes[] = { + &dev_attr_pwm_duty, + NULL +}; +static struct attribute_group pwm_duty_group = { + .attrs = pwm_duty_attributes, +}; +static struct miscdevice pwm_duty_device = { + .minor = MISC_DYNAMIC_MINOR, + .name = "pwm_duty", +}; + +static struct timed_output_dev to_dev = { + .name = "vibrator", + .get_time = aries_vibrator_get_time, + .enable = aries_vibrator_enable, +}; + +static enum hrtimer_restart aries_vibrator_timer_func(struct hrtimer *timer) +{ + schedule_work(&vibdata.work); + return HRTIMER_NORESTART; +} + +static void aries_vibrator_work(struct work_struct *work) +{ + aries_vibrator_off(); +} + +static int __init aries_init_vibrator(void) +{ + int ret = 0; + +#ifdef CONFIG_MACH_ARIES + if (!machine_is_aries()) + return 0; +#endif + hrtimer_init(&vibdata.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + vibdata.timer.function = aries_vibrator_timer_func; + INIT_WORK(&vibdata.work, aries_vibrator_work); + + ret = gpio_request(GPIO_VIBTONE_EN1, "vibrator-en"); + if (ret < 0) + return ret; + + s3c_gpio_cfgpin(GPIO_VIBTONE_PWM, GPD0_TOUT_1); + + vibdata.pwm_dev = pwm_request(1, "vibrator-pwm"); + if (IS_ERR(vibdata.pwm_dev)) { + ret = PTR_ERR(vibdata.pwm_dev); + goto err_pwm_req; + } + + wake_lock_init(&vibdata.wklock, WAKE_LOCK_SUSPEND, "vibrator"); + mutex_init(&vibdata.lock); + + ret = timed_output_dev_register(&to_dev); + if (ret < 0) + goto err_to_dev_reg; + + if (misc_register(&pwm_duty_device)) + printk("%s misc_register(%s) failed\n", __FUNCTION__, pwm_duty_device.name); + else { + if (sysfs_create_group(&pwm_duty_device.this_device->kobj, &pwm_duty_group)) + dev_err("failed to create sysfs group for device %s\n", pwm_duty_device.name); + } + + return 0; + +err_to_dev_reg: + mutex_destroy(&vibdata.lock); + wake_lock_destroy(&vibdata.wklock); + pwm_free(vibdata.pwm_dev); +err_pwm_req: + gpio_free(GPIO_VIBTONE_EN1); + return ret; +} + +device_initcall(aries_init_vibrator); diff --git a/arch/arm/mach-s5pv210/aries-watchdog.c b/arch/arm/mach-s5pv210/aries-watchdog.c new file mode 100644 index 0000000..2d6509af --- /dev/null +++ b/arch/arm/mach-s5pv210/aries-watchdog.c @@ -0,0 +1,111 @@ +/* aries-watchdog.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <plat/regs-watchdog.h> +#include <mach/map.h> + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/cpufreq.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/workqueue.h> +#include <linux/io.h> + +/* reset timeout in PCLK/256/128 (~2048:1s) */ +static unsigned watchdog_reset = (30 * 2048); + +/* pet timeout in jiffies */ +static unsigned watchdog_pet = (10 * HZ); + +static struct workqueue_struct *watchdog_wq; +static void watchdog_workfunc(struct work_struct *work); +static DECLARE_DELAYED_WORK(watchdog_work, watchdog_workfunc); + +static void watchdog_workfunc(struct work_struct *work) +{ + writel(watchdog_reset, S3C2410_WTCNT); + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_start(void) +{ + unsigned int val; + + /* set to PCLK / 256 / 128 */ + val = S3C2410_WTCON_DIV128; + val |= S3C2410_WTCON_PRESCALE(255); + writel(val, S3C2410_WTCON); + + /* program initial count */ + writel(watchdog_reset, S3C2410_WTCNT); + writel(watchdog_reset, S3C2410_WTDAT); + + /* start timer */ + val |= S3C2410_WTCON_RSTEN | S3C2410_WTCON_ENABLE; + writel(val, S3C2410_WTCON); + + /* make sure we're ready to pet the dog */ + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_stop(void) +{ + writel(0, S3C2410_WTCON); +} + +static int watchdog_probe(struct platform_device *pdev) +{ + watchdog_wq = alloc_workqueue("pet_watchdog", + WQ_UNBOUND | WQ_HIGHPRI, 1); + watchdog_start(); + return 0; +} + +static int watchdog_suspend(struct device *dev) +{ + watchdog_stop(); + return 0; +} + +static int watchdog_resume(struct device *dev) +{ + watchdog_start(); + return 0; +} + +static struct dev_pm_ops watchdog_pm_ops = { + .suspend_noirq = watchdog_suspend, + .resume_noirq = watchdog_resume, +}; + +static struct platform_driver watchdog_driver = { + .probe = watchdog_probe, + .driver = { + .owner = THIS_MODULE, + .name = "watchdog", + .pm = &watchdog_pm_ops, + }, +}; + +static int __init watchdog_init(void) +{ + return platform_driver_register(&watchdog_driver); +} + +module_init(watchdog_init); diff --git a/arch/arm/mach-s5pv210/aries.h b/arch/arm/mach-s5pv210/aries.h new file mode 100644 index 0000000..7e31307 --- /dev/null +++ b/arch/arm/mach-s5pv210/aries.h @@ -0,0 +1,18 @@ +/* + * arch/arm/mach-s5pv210/aries.h + */ + +#ifndef __ARIES_H__ +#define __ARIES_H__ + +struct uart_port; + +void aries_bt_uart_wake_peer(struct uart_port *port); +extern void s3c_setup_uart_cfg_gpio(unsigned char port); + +extern struct s5p_panel_data aries_panel_data; +extern struct s5p_tft_panel_data aries_sony_panel_data; +extern struct s5p_tft_panel_data aries_hydis_panel_data; +extern struct s5p_tft_panel_data aries_hitachi_panel_data; + +#endif diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 2d59949..6d3e609 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -19,6 +19,8 @@ #include <linux/clk.h> #include <linux/sysdev.h> #include <linux/io.h> +#include <linux/device.h> +#include <linux/platform_device.h> #include <mach/map.h> @@ -30,9 +32,13 @@ #include <plat/s5p-clock.h> #include <plat/clock-clksrc.h> #include <plat/s5pv210.h> +#include <plat/devs.h> +#include <mach/regs-audss.h> static unsigned long xtal; +static int s5pv210_usbosc_enable(struct clk *clk, int enable); + static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", @@ -175,6 +181,16 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); } +static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable); +} + +static int s5pv210_clk_ip5_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP5, clk, enable); +} + static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); @@ -185,6 +201,11 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); } +static int s5pv210_clk_audss_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable); +} + static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .id = -1, @@ -206,6 +227,21 @@ static struct clk clk_sclk_usbphy1 = { .id = -1, }; +static struct clk clk_i2scdclk0 = { + .name = "i2scdclk", + .id = 0, +}; + +static struct clk clk_i2scdclk1 = { + .name = "i2scdclk", + .id = 1, +}; + +static struct clk clk_i2scdclk2 = { + .name = "i2scdclk", + .id = 2, +}; + static struct clk clk_pcmcdclk0 = { .name = "pcmcdclk", .id = -1, @@ -311,18 +347,6 @@ static struct clk_ops clk_fout_apll_ops = { static struct clk init_clocks_off[] = { { - .name = "pdma", - .id = 0, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "pdma", - .id = 1, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 4), - }, { .name = "rot", .id = -1, .parent = &clk_hclk_dsys.clk, @@ -359,11 +383,30 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<17), }, { - .name = "lcd", + .name = "jpeg", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip5_ctrl, + .ctrlbit = S5P_CLKGATE_IP5_JPEG, + }, { + .name = "mfc", + .id = -1, + .parent = &clk_hclk_msys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<16), + }, { + .name = "dsim", .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip1_ctrl, - .ctrlbit = (1<<0), + .ctrlbit = (1<<2), + }, { + .name = "onenand", + .id = -1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 24), + .dev = &s5p_device_onenand.dev, }, { .name = "cfcon", .id = 0, @@ -401,12 +444,6 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<16), }, { - .name = "watchdog", - .id = -1, - .parent = &clk_pclk_psys.clk, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<22), - }, { .name = "rtc", .id = -1, .parent = &clk_pclk_psys.clk, @@ -490,11 +527,117 @@ static struct clk init_clocks_off[] = { .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 0), + }, { + .name = "pcm", + .id = 2, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_PCM2, + }, { +#if 0 + .name = "pcm", + .id = 1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_PCM1 | S5P_CLKGATE_IP3_I2S1 , + }, { + .name = "pcm", + .id = 0, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_PCM0, + }, { +#endif + .name = "i2c-hdmiphy", + .id = -1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "hdmi", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "tvenc", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "mixer", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "vp", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "usb_osc", + .id = -1, + .enable = s5pv210_usbosc_enable, + .ctrlbit = (1 << 1), + }, { + .name = "secss", + .id = -1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "seckey", + .id = -1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip4_ctrl, + .ctrlbit = (1 << 3), }, }; +static struct clk init_dmaclocks[] = { + { + .name = "pdma", + .id = 0, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<2), + .dev = &s5pv210_device_mdma.dev, + }, { + .name = "pdma", + .id = 1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<3), + .dev = &s5pv210_device_pdma0.dev, + }, { + .name = "pdma", + .id = 2, + .parent = &init_dmaclocks[1], + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<4), + .dev = &s5pv210_device_pdma1.dev, + }, +}; + +static int s5pc11x_clk_out_set_rate(struct clk *clk, unsigned long rate); +static int s5pc11x_clk_out_set_parent(struct clk *clk, struct clk *parent); + +static struct clk_ops s5pc11x_clkout_ops = { + .set_parent = s5pc11x_clk_out_set_parent, + .set_rate = s5pc11x_clk_out_set_rate, +}; + static struct clk init_clocks[] = { { + .name = "watchdog", + .id = -1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1<<22), + }, { .name = "hclk_imem", .id = -1, .parent = &clk_hclk_msys.clk, @@ -502,6 +645,12 @@ static struct clk init_clocks[] = { .enable = s5pv210_clk_ip0_ctrl, .ops = &clk_hclk_imem_ops, }, { + .name = "lcd", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1<<0), + }, { .name = "uart", .id = 0, .parent = &clk_pclk_psys.clk, @@ -531,6 +680,21 @@ static struct clk init_clocks[] = { .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1 << 26), + }, { +#if 1 + .name = "i2s_v50", + .id = 0, + .parent = &clk_p, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_I2S0 | S5P_CLKGATE_IP3_PCM0, + }, { +#endif + .name = "clk_out", + .id = -1, + .ops = &s5pc11x_clkout_ops, + }, { + .name = "apb_pclk", + .id = -1, }, }; @@ -627,6 +791,54 @@ static struct clksrc_sources clkset_sclk_mixer = { .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), }; +static int s5pc11x_clk_out_set_rate(struct clk *clk, unsigned long rate) +{ + u32 val = 0, div = 0, rate_div = 1; + int err = -EINVAL; + + if (rate && clk->parent) { + if (clk->parent == &clk_fout_apll) + rate_div = 4; + if (clk->parent == &clk_fout_mpll) + rate_div = 2; + + div = clk_get_rate(clk->parent) / rate / rate_div; + val = __raw_readl(S5P_CLK_OUT); + val &= (~(0xF << 20)); + val |= (div - 1) << 20; + __raw_writel(val, S5P_CLK_OUT); + err = 0; + } + return err; +} + +static int s5pc11x_clk_out_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val = 0; + int err = 0; + clk->parent = parent; + val = __raw_readl(S5P_CLK_OUT); + + if (parent == &clk_fout_apll) { + val = val & (~(0x1F << 12)); + val |= (0x0 << 12); + } else if (parent == &clk_fout_mpll) { + val = val & (~(0x1F << 12)); + val |= (0x1 << 12); + } else if (parent == &clk_fout_epll) { + val = val & (~(0x1F << 12)); + val |= (0x2 << 12); + } else if (parent == &clk_sclk_vpll.clk) { + val = val & (~(0x1F << 12)); + val |= (0x3 << 12); + } else { + err = -EINVAL; + } + + __raw_writel(val, S5P_CLK_OUT); + return err; +} + static struct clk *clkset_sclk_audio0_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_pcmcdclk0, @@ -656,6 +868,59 @@ static struct clksrc_clk clk_sclk_audio0 = { .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, }; +static struct clk *clkset_mout_audss_list[] = { + &clk_ext_xtal_mux, + &clk_fout_epll, +}; + +static struct clksrc_sources clkset_mout_audss = { + .sources = clkset_mout_audss_list, + .nr_sources = ARRAY_SIZE(clkset_mout_audss_list), +}; + +static struct clksrc_clk clk_mout_audss = { + .clk = { + .name = "mout_audss", + .id = -1, + }, + .sources = &clkset_mout_audss, + .reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 0, .size = 1 }, +}; + +static struct clk *clkset_mout_i2s_a_list[] = { + &clk_mout_audss.clk, + &clk_pcmcdclk0, + &clk_sclk_audio0.clk, +}; + +static struct clksrc_sources clkset_mout_i2s_a = { + .sources = clkset_mout_i2s_a_list, + .nr_sources = ARRAY_SIZE(clkset_mout_i2s_a_list), +}; + +static struct clksrc_clk clk_mout_i2s_a = { + .clk = { + .name = "audio-bus", + .id = 0, + .enable = s5pv210_clk_audss_ctrl, + .ctrlbit = (1 << 6), + }, + .sources = &clkset_mout_i2s_a, + .reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 2, .size = 2 }, + .reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_dout_audio_bus_clk_i2s = { + .clk = { + .name = "dout_audio_bus_clk_i2s", + .id = -1, + .parent = &clk_mout_audss.clk, + .enable = s5pv210_clk_audss_ctrl, + .ctrlbit = (1 << 5), + }, + .reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 0, .size = 4 }, +}; + static struct clk *clkset_sclk_audio1_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_pcmcdclk1, @@ -808,40 +1073,44 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 0, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 12), + .dev = &s3c24xx_uart_device0.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 13), + .dev = &s3c24xx_uart_device1.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 2, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 14), + .dev = &s3c24xx_uart_device2.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 3, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 15), + .dev = &s3c24xx_uart_device3.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, @@ -909,8 +1178,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimd", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 5), + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 0), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, @@ -967,7 +1236,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, }, { .clk = { - .name = "sclk_g2d", + .name = "sclk_fimg2d", .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 12), @@ -977,10 +1246,11 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, }, { .clk = { - .name = "sclk_g3d", + .name = "sclk", .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 8), + .dev = &s3c_device_g3d.dev, }, .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, @@ -1035,7 +1305,41 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_mdnie", + .id = -1, + .enable = s5pv210_clk_mask1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, + .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_mdnie_pwm", + .id = -1, + .enable = s5pv210_clk_mask1_ctrl, + .ctrlbit = (1 << 1), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 4, + .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, + }, +}; + +/* MOUT CSIS */ +static struct clksrc_clk clk_mout_csis = { + .clk = { + .name = "mout_csis", + .id = -1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 6), }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, }; /* Clock initialisation code */ @@ -1058,12 +1362,29 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_hdmi, &clk_mout_dmc0, &clk_sclk_dmc0, + &clk_mout_csis, &clk_sclk_audio0, &clk_sclk_audio1, &clk_sclk_audio2, &clk_sclk_spdif, + &clk_mout_audss, + &clk_mout_i2s_a, + &clk_dout_audio_bus_clk_i2s, }; +static int s5pv210_usbosc_enable(struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + unsigned int usbosc_con = __raw_readl(S5P_SLEEP_CFG) & ~ctrlbit; + + if (enable) + usbosc_con |= ctrlbit; + + writel(usbosc_con, S5P_SLEEP_CFG); + + return 0; +} + static u32 epll_div[][6] = { { 48000000, 0, 48, 3, 3, 0 }, { 96000000, 0, 48, 3, 2, 0 }, @@ -1157,6 +1478,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) unsigned long vpll; unsigned int ptr; u32 clkdiv0, clkdiv1; + struct clksrc_clk *pclkSrc; /* Set functions for clk_fout_epll */ clk_fout_epll.enable = s5p_epll_enable; @@ -1210,8 +1532,38 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) clk_h.rate = hclk_psys; clk_p.rate = pclk_psys; - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_set_clksrc(&clksrcs[ptr], true); + /*Assign clock source and rates for IP's*/ + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) { + pclkSrc = &clksrcs[ptr]; + if (!strcmp(pclkSrc->clk.name, "sclk_mdnie")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + clk_set_rate(&pclkSrc->clk, 167*MHZ); + } else if (!strcmp(pclkSrc->clk.name, "sclk_mmc")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + + if (pclkSrc->clk.id == 0) + clk_set_rate(&pclkSrc->clk, 52*MHZ); + else + clk_set_rate(&pclkSrc->clk, 50*MHZ); + } else if (!strcmp(pclkSrc->clk.name, "sclk_spi")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_epll.clk); + } else if (!strcmp(pclkSrc->clk.name, "sclk_cam") && + (pclkSrc->clk.id == 0)) { + clk_set_parent(&pclkSrc->clk, &clk_xusbxti); + } else if (!strcmp(pclkSrc->clk.name, "sclk_g2d")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + clk_set_rate(&pclkSrc->clk, 250*MHZ); + } else if (!strcmp(pclkSrc->clk.name, "sclk")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + + if (pclkSrc->clk.id == 0) + clk_set_rate(&pclkSrc->clk, 133400000); + else + clk_set_rate(&pclkSrc->clk, 66700000); + } + /* Display the clock source */ + s3c_set_clksrc(pclkSrc, true); + } } static struct clk *clks[] __initdata = { @@ -1219,6 +1571,9 @@ static struct clk *clks[] __initdata = { &clk_sclk_hdmiphy, &clk_sclk_usbphy0, &clk_sclk_usbphy1, + &clk_i2scdclk0, + &clk_i2scdclk1, + &clk_i2scdclk2, &clk_pcmcdclk0, &clk_pcmcdclk1, &clk_pcmcdclk2, @@ -1239,5 +1594,9 @@ void __init s5pv210_register_clocks(void) s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + /* Register DMA Clock */ + s3c_register_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks)); + s3c_disable_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks)); + s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pv210/coresight.c b/arch/arm/mach-s5pv210/coresight.c new file mode 100755 index 0000000..b8c29c7 --- /dev/null +++ b/arch/arm/mach-s5pv210/coresight.c @@ -0,0 +1,163 @@ +/* coresight.c + * + * Copyright (C) 2011 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm/hardware/coresight.h> +#include <linux/amba/bus.h> +#include <linux/io.h> +#include <plat/pm.h> + +#define CS_ETB_BASE (0xE0D00000 + 0x1000) +#define CS_FUNNEL_BASE (0xE0D00000 + 0x4000) +#define CS_ETM_BASE (0xE0D00000 + 0x6000) +#define TZPC3_BASE (0xE1C00000) + +static void __iomem *cs_etb_regs; +static void __iomem *cs_funnel_regs; +static void __iomem *cs_etm_regs; +static void __iomem *tzpc3_regs; + +static void cs_unlock(void *regs) +{ + writel(UNLOCK_MAGIC, regs + CSMR_LOCKACCESS); + readl(regs + CSMR_LOCKSTATUS); +} + +static void cs_relock(void *regs) +{ + writel(0, regs + CSMR_LOCKACCESS); +} + +static void cs_init_static_regs(void) +{ + /* Enable NIDEN and SPNIDEN */ + writel(0x5, tzpc3_regs + 0x828); + + /* Set funnel control: Enable ATB port0 */ + cs_unlock(cs_funnel_regs); + writel(0x301, cs_funnel_regs); + cs_relock(cs_funnel_regs); +} + +#ifdef CONFIG_PM +static void (*orig_pm_cpu_prep)(void); +static void (*orig_pm_cpu_restore)(void); + +static u32 etm_state[64]; +static int etm_state_count; +static u32 etb_ffcr; +static u32 etb_ctl; + +static void cs_pm_prep(void) +{ + int save_count; + + if (orig_pm_cpu_prep) + orig_pm_cpu_prep(); + + cs_unlock(cs_etb_regs); + etb_ctl = readl(cs_etb_regs + ETBR_CTRL); + etb_ffcr = readl(cs_etb_regs + ETBR_FORMATTERCTRL); + cs_relock(cs_etb_regs); + + cs_unlock(cs_etm_regs); + writel(UNLOCK_MAGIC, cs_etm_regs + ETMMR_OSLAR); + save_count = readl(cs_etm_regs + ETMMR_OSSRR); + pr_debug("%s: trace_pm_prep reg count %d\n", __func__, save_count); + if (save_count > ARRAY_SIZE(etm_state)) + save_count = 0; + etm_state_count = 0; + while (save_count--) + etm_state[etm_state_count++] = readl(cs_etm_regs + ETMMR_OSSRR); + writel(0, cs_etm_regs + ETMMR_OSLAR); + cs_relock(cs_etm_regs); +} + +static void cs_pm_resume(void) +{ + int i; + + cs_init_static_regs(); + + cs_unlock(cs_etb_regs); + writel(etb_ffcr, cs_etb_regs + ETBR_FORMATTERCTRL); + writel(etb_ctl, cs_etb_regs + ETBR_CTRL); + cs_relock(cs_etb_regs); + + cs_unlock(cs_etm_regs); + readl(cs_etm_regs + ETMMR_PDSR); + writel(UNLOCK_MAGIC, cs_etm_regs + ETMMR_OSLAR); + readl(cs_etm_regs + ETMMR_OSSRR); + for (i = 0; i < etm_state_count; i++) { + writel(etm_state[i], cs_etm_regs + ETMMR_OSSRR); + pr_debug("%s: restore %d %08x\n", __func__, i, etm_state[i]); + } + writel(0, cs_etm_regs + ETMMR_OSLAR); + cs_relock(cs_etm_regs); + + if (orig_pm_cpu_restore) + orig_pm_cpu_restore(); +} + +static void cs_pm_init(void) +{ + orig_pm_cpu_restore = pm_cpu_restore; + orig_pm_cpu_prep = pm_cpu_prep; + pm_cpu_restore = cs_pm_resume; + pm_cpu_prep = cs_pm_prep; +} +#else +static inline void cs_pm_init(void) {} +#endif + +static struct amba_device s5pv210_etb_device = { + .dev = { + .init_name = "etb", + }, + .res = { + .start = CS_ETB_BASE, + .end = CS_ETB_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = 0x000bb907, +}; + +static struct amba_device s5pv210_etm_device = { + .dev = { + .init_name = "etm", + }, + .res = { + .start = CS_ETM_BASE, + .end = CS_ETM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = 0x005bb921, +}; + +static int trace_init(void) +{ + cs_etb_regs = ioremap(CS_ETB_BASE, SZ_4K); + cs_funnel_regs = ioremap(CS_FUNNEL_BASE, SZ_4K); + cs_etm_regs = ioremap(CS_ETM_BASE, SZ_4K); + tzpc3_regs = ioremap(TZPC3_BASE, SZ_4K); + + cs_init_static_regs(); + + cs_pm_init(); + + amba_device_register(&s5pv210_etb_device, &iomem_resource); + amba_device_register(&s5pv210_etm_device, &iomem_resource); + return 0; +} +device_initcall(trace_init); diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 61e6c24..cd40d7c 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -25,6 +25,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <asm/mach-types.h> #include <asm/proc-fns.h> #include <mach/map.h> #include <mach/regs-clock.h> @@ -95,7 +96,31 @@ static struct map_desc s5pv210_iodesc[] __initdata = { .pfn =__phys_to_pfn(S5PV210_PA_HSPHY), .length = SZ_4K, .type = MT_DEVICE, - } + }, { + .virtual = (unsigned long)S3C_VA_OTG, + .pfn = __phys_to_pfn(S5PV210_PA_OTG), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_OTGSFR, + .pfn = __phys_to_pfn(S5PV210_PA_OTGSFR), + .length = SZ_1M, + .type = MT_DEVICE, + }, +#if defined(CONFIG_HRT_RTC) + { + .virtual = (unsigned long)S5P_VA_RTC, + .pfn = __phys_to_pfn(S5PV210_PA_RTC), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif + { + .virtual = (unsigned long)S5P_VA_AUDSS, + .pfn = __phys_to_pfn(S5PV210_PA_AUDSS), + .length = SZ_1M, + .type = MT_DEVICE, + }, }; static void s5pv210_idle(void) @@ -191,7 +216,8 @@ int __init s5pv210_init(void) pm_idle = s5pv210_idle; /* set sw_reset function */ - s5p_reset_hook = s5pv210_sw_reset; + if (!(machine_is_herring() || machine_is_aries())) + s5p_reset_hook = s5pv210_sw_reset; return sysdev_register(&s5pv210_sysdev); } diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c index 153af8b..e712847 100644..100755 --- a/arch/arm/mach-s5pv210/cpufreq.c +++ b/arch/arm/mach-s5pv210/cpufreq.c @@ -16,20 +16,40 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/suspend.h> +#include <linux/reboot.h> +#include <linux/regulator/consumer.h> #include <linux/cpufreq.h> +#include <linux/platform_device.h> #include <mach/map.h> #include <mach/regs-clock.h> +#include <mach/cpu-freq-v210.h> static struct clk *cpu_clk; static struct clk *dmc0_clk; static struct clk *dmc1_clk; static struct cpufreq_freqs freqs; +static DEFINE_MUTEX(set_freq_lock); -/* APLL M,P,S values for 1G/800Mhz */ +/* APLL M,P,S values for 1.2G/1G/800Mhz */ +#define APLL_VAL_1200 ((1 << 31) | (150 << 16) | (3 << 8) | 1) #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1) #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1) +#define SLEEP_FREQ (800 * 1000) /* Use 800MHz when entering sleep */ + +/* + * relation has an additional symantics other than the standard of cpufreq + * DISALBE_FURTHER_CPUFREQ: disable further access to target until being re-enabled. + * ENABLE_FURTUER_CPUFREQ: re-enable access to target +*/ +enum cpufreq_access { + DISABLE_FURTHER_CPUFREQ = 0x10, + ENABLE_FURTHER_CPUFREQ = 0x20, +}; +static bool no_cpufreq_access; + /* * DRAM configurations to calculate refresh counter for changing * frequency of memory. @@ -42,10 +62,6 @@ struct dram_conf { /* DRAM configuration (DMC0 and DMC1) */ static struct dram_conf s5pv210_dram_conf[2]; -enum perf_level { - L0, L1, L2, L3, L4, -}; - enum s5pv210_mem_type { LPDDR = 0x1, LPDDR2 = 0x2, @@ -58,6 +74,7 @@ enum s5pv210_dmc_port { }; static struct cpufreq_frequency_table s5pv210_freq_table[] = { + {OC0, 1200*1000}, {L0, 1000*1000}, {L1, 800*1000}, {L2, 400*1000}, @@ -66,7 +83,52 @@ static struct cpufreq_frequency_table s5pv210_freq_table[] = { {0, CPUFREQ_TABLE_END}, }; -static u32 clkdiv_val[5][11] = { +static struct regulator *arm_regulator; +static struct regulator *internal_regulator; + +struct s5pv210_dvs_conf { + unsigned long arm_volt; /* uV */ + unsigned long int_volt; /* uV */ +}; + +#ifdef CONFIG_DVFS_LIMIT +static unsigned int g_dvfs_high_lock_token = 0; +static unsigned int g_dvfs_high_lock_limit = 6; +static unsigned int g_dvfslockval[DVFS_LOCK_TOKEN_NUM]; +//static DEFINE_MUTEX(dvfs_high_lock); +#endif + +const unsigned long arm_volt_max = 1350000; +const unsigned long int_volt_max = 1250000; + +static struct s5pv210_dvs_conf dvs_conf[] = { + [OC0] = { + .arm_volt = 1275000, + .int_volt = 1100000, + }, + [L0] = { + .arm_volt = 1275000, + .int_volt = 1100000, + }, + [L1] = { + .arm_volt = 1200000, + .int_volt = 1100000, + }, + [L2] = { + .arm_volt = 1050000, + .int_volt = 1100000, + }, + [L3] = { + .arm_volt = 950000, + .int_volt = 1100000, + }, + [L4] = { + .arm_volt = 950000, + .int_volt = 1000000, + }, +}; + +static u32 clkdiv_val[6][11] = { /* * Clock divider value for following * { APLL, A2M, HCLK_MSYS, PCLK_MSYS, @@ -74,6 +136,9 @@ static u32 clkdiv_val[5][11] = { * ONEDRAM, MFC, G3D } */ + /* OC0 : [1200/200/100][166/83][133/66][200/200] */ + {0, 5, 5, 1, 3, 1, 4, 1, 3, 0, 0}, + /* L0 : [1000/200/100][166/83][133/66][200/200] */ {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0}, @@ -84,7 +149,7 @@ static u32 clkdiv_val[5][11] = { {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, /* L3 : [200/200/100][166/83][133/66][200/200] */ - {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, + {3, 3, 0, 1, 3, 1, 4, 1, 3, 0, 0}, /* L4 : [100/100/100][83/83][66/66][100/100] */ {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0}, @@ -138,44 +203,144 @@ unsigned int s5pv210_getspeed(unsigned int cpu) return clk_get_rate(cpu_clk) / 1000; } +#ifdef CONFIG_DVFS_LIMIT +void s5pv210_lock_dvfs_high_level(uint nToken, uint perf_level) +{ + //printk(KERN_DEBUG "%s : lock with token(%d) level(%d) current(%X)\n", + // __func__, nToken, perf_level, g_dvfs_high_lock_token); + + if (g_dvfs_high_lock_token & (1 << nToken)) + return; + + if (perf_level > (MAX_PERF_LEVEL - 1)) + return; + + //mutex_lock(&dvfs_high_lock); + + g_dvfs_high_lock_token |= (1 << nToken); + g_dvfslockval[nToken] = perf_level; + + if (perf_level < g_dvfs_high_lock_limit) + g_dvfs_high_lock_limit = perf_level; + + //mutex_unlock(&dvfs_high_lock); + + /* Reevaluate cpufreq policy with the effect of calling the governor with a + * CPUFREQ_GOV_LIMITS event, so that the governor sets its preferred + * frequency. The governor MUST call __cpufreq_driver_target, even if it + * decides not to change frequencies, as the DVFS limit takes effect in + * doing so. */ + cpufreq_update_policy(0); +} +EXPORT_SYMBOL(s5pv210_lock_dvfs_high_level); + +void s5pv210_unlock_dvfs_high_level(unsigned int nToken) +{ + unsigned int i; + + //mutex_lock(&dvfs_high_lock); + + g_dvfs_high_lock_token &= ~(1 << nToken); + g_dvfslockval[nToken] = MAX_PERF_LEVEL; + g_dvfs_high_lock_limit = MAX_PERF_LEVEL; + + if (g_dvfs_high_lock_token) { + for (i = 0; i < DVFS_LOCK_TOKEN_NUM; i++) { + if (g_dvfslockval[i] < g_dvfs_high_lock_limit) + g_dvfs_high_lock_limit = g_dvfslockval[i]; + } + } + + //mutex_unlock(&dvfs_high_lock); + + //printk(KERN_DEBUG "%s : unlock with token(%d) current(%X) level(%d)\n", + // __func__, nToken, g_dvfs_high_lock_token, g_dvfs_high_lock_limit); + + /* Reevaluate cpufreq policy with the effect of calling the governor with a + * CPUFREQ_GOV_LIMITS event, so that the governor sets its preferred + * frequency with the new (or no) DVFS limit. */ + cpufreq_update_policy(0); +} +EXPORT_SYMBOL(s5pv210_unlock_dvfs_high_level); +#endif + static int s5pv210_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) { unsigned long reg; - unsigned int index, priv_index; + unsigned int index; unsigned int pll_changing = 0; unsigned int bus_speed_changing = 0; + unsigned int arm_volt, int_volt; + int ret = 0; + + mutex_lock(&set_freq_lock); + + if (relation & ENABLE_FURTHER_CPUFREQ) + no_cpufreq_access = false; + if (no_cpufreq_access) { +#ifdef CONFIG_PM_VERBOSE + pr_err("%s:%d denied access to %s as it is disabled" + "temporarily\n", __FILE__, __LINE__, __func__); +#endif + ret = -EINVAL; + goto out; + } + if (relation & DISABLE_FURTHER_CPUFREQ) + no_cpufreq_access = true; + relation &= ~(ENABLE_FURTHER_CPUFREQ | DISABLE_FURTHER_CPUFREQ); freqs.old = s5pv210_getspeed(0); if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, - target_freq, relation, &index)) - return -EINVAL; + target_freq, relation, &index)) { + ret = -EINVAL; + goto out; + } + +#ifdef CONFIG_DVFS_LIMIT + if (g_dvfs_high_lock_token) { + if (index > g_dvfs_high_lock_limit) + index = g_dvfs_high_lock_limit; + } +#endif freqs.new = s5pv210_freq_table[index].frequency; freqs.cpu = 0; if (freqs.new == freqs.old) - return 0; - - /* Finding current running level index */ - if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, - freqs.old, relation, &priv_index)) - return -EINVAL; + goto out; - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + arm_volt = dvs_conf[index].arm_volt; + int_volt = dvs_conf[index].int_volt; if (freqs.new > freqs.old) { - /* Voltage up: will be implemented */ + /* Voltage up code: increase ARM first */ + if (!IS_ERR_OR_NULL(arm_regulator) && + !IS_ERR_OR_NULL(internal_regulator)) { + ret = regulator_set_voltage(arm_regulator, + arm_volt, arm_volt_max); + if (ret) + goto out; + ret = regulator_set_voltage(internal_regulator, + int_volt, int_volt_max); + if (ret) + goto out; + } } + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + /* Don't use cpufreq_frequency_table_target() any more as it */ + /* may not be accurate. Compare against freqs.old instead */ + /* Check if there need to change PLL */ - if ((index == L0) || (priv_index == L0)) + if ((index <= L0) || (freqs.old >= s5pv210_freq_table[L0].frequency)) pll_changing = 1; /* Check if there need to change System bus clock */ - if ((index == L4) || (priv_index == L4)) + if ((index == L4) || (freqs.old == s5pv210_freq_table[L4].frequency)) bus_speed_changing = 1; if (bus_speed_changing) { @@ -290,10 +455,17 @@ static int s5pv210_target(struct cpufreq_policy *policy, * 6-1. Set PMS values * 6-2. Wait untile the PLL is locked */ - if (index == L0) + switch (index) { + case OC0: + __raw_writel(APLL_VAL_1200, S5P_APLL_CON); + break; + case L0: __raw_writel(APLL_VAL_1000, S5P_APLL_CON); - else + break; + default: __raw_writel(APLL_VAL_800, S5P_APLL_CON); + break; + } do { reg = __raw_readl(S5P_APLL_CON); @@ -380,15 +552,23 @@ static int s5pv210_target(struct cpufreq_policy *policy, } } - if (freqs.new < freqs.old) { - /* Voltage down: will be implemented */ - } - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - printk(KERN_DEBUG "Perf changed[L%d]\n", index); + if (freqs.new < freqs.old) { + /* Voltage down: decrease INT first */ + if (!IS_ERR_OR_NULL(arm_regulator) && + !IS_ERR_OR_NULL(internal_regulator)) { + regulator_set_voltage(internal_regulator, + int_volt, int_volt_max); + regulator_set_voltage(arm_regulator, + arm_volt, arm_volt_max); + } + } - return 0; + pr_debug("Perf changed[L%d]\n", index); +out: + mutex_unlock(&set_freq_lock); + return ret; } #ifdef CONFIG_PM @@ -416,6 +596,7 @@ static int check_mem_type(void __iomem *dmc_reg) static int __init s5pv210_cpu_init(struct cpufreq_policy *policy) { unsigned long mem_type; + int ret; cpu_clk = clk_get(NULL, "armclk"); if (IS_ERR(cpu_clk)) @@ -461,9 +642,59 @@ static int __init s5pv210_cpu_init(struct cpufreq_policy *policy) policy->cpuinfo.transition_latency = 40000; - return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table); +#ifdef CONFIG_DVFS_LIMIT + int i; + for (i = 0; i < DVFS_LOCK_TOKEN_NUM; i++) + g_dvfslockval[i] = MAX_PERF_LEVEL; +#endif + + /* Set max freq to 1GHz on startup */ + ret = cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table); + policy->min = 100000; + policy->max = 1000000; + + return ret; +} + +static int s5pv210_cpufreq_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int ret; + + switch (event) { + case PM_SUSPEND_PREPARE: + ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, + DISABLE_FURTHER_CPUFREQ); + if (ret < 0) + return NOTIFY_BAD; + return NOTIFY_OK; + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, + ENABLE_FURTHER_CPUFREQ); + return NOTIFY_OK; + } + return NOTIFY_DONE; +} + +static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int ret = 0; + + ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, + DISABLE_FURTHER_CPUFREQ); + if (ret < 0) + return NOTIFY_BAD; + + return NOTIFY_DONE; } +static struct freq_attr *s5pv210_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + static struct cpufreq_driver s5pv210_driver = { .flags = CPUFREQ_STICKY, .verify = s5pv210_verify_speed, @@ -475,11 +706,113 @@ static struct cpufreq_driver s5pv210_driver = { .suspend = s5pv210_cpufreq_suspend, .resume = s5pv210_cpufreq_resume, #endif + .attr = s5pv210_cpufreq_attr, }; -static int __init s5pv210_cpufreq_init(void) +static struct notifier_block s5pv210_cpufreq_notifier = { + .notifier_call = s5pv210_cpufreq_notifier_event, +}; + +static struct notifier_block s5pv210_cpufreq_reboot_notifier = { + .notifier_call = s5pv210_cpufreq_reboot_notifier_event, +}; + +static int __init s5pv210_cpufreq_probe(struct platform_device *pdev) { + struct s5pv210_cpufreq_data *pdata = dev_get_platdata(&pdev->dev); + int i, j; + + if (pdata && pdata->size) { + for (i = 0; i < pdata->size; i++) { + j = 0; + while (s5pv210_freq_table[j].frequency != CPUFREQ_TABLE_END) { + if (s5pv210_freq_table[j].frequency == pdata->volt[i].freq) { + dvs_conf[j].arm_volt = pdata->volt[i].varm; + dvs_conf[j].int_volt = pdata->volt[i].vint; + break; + } + j++; + } + } + } + + arm_regulator = regulator_get(NULL, "vddarm"); + if (IS_ERR(arm_regulator)) { + pr_err("failed to get regulater resource vddarm\n"); + goto error; + } + internal_regulator = regulator_get(NULL, "vddint"); + if (IS_ERR(internal_regulator)) { + pr_err("failed to get regulater resource vddint\n"); + goto error; + } + goto finish; +error: + pr_warn("Cannot get vddarm or vddint. CPUFREQ Will not" + " change the voltage.\n"); +finish: + register_pm_notifier(&s5pv210_cpufreq_notifier); + register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier); + return cpufreq_register_driver(&s5pv210_driver); } +static struct platform_driver s5pv210_cpufreq_drv = { + .probe = s5pv210_cpufreq_probe, + .driver = { + .owner = THIS_MODULE, + .name = "s5pv210-cpufreq", + }, +}; + +static int __init s5pv210_cpufreq_init(void) +{ + int ret; + + ret = platform_driver_register(&s5pv210_cpufreq_drv); + if (!ret) + pr_info("%s: S5PV210 cpu-freq driver\n", __func__); + + return ret; +} + late_initcall(s5pv210_cpufreq_init); + +ssize_t show_UV_mV_table(struct cpufreq_policy *policy, char *buf) +{ + int i, len = 0; + for (i = 0; i <= MAX_PERF_LEVEL; i++) { + len += sprintf(buf + len, "%dmhz: %d mV\n", s5pv210_freq_table[i].frequency / 1000, dvs_conf[i].arm_volt / 1000); + } + return len; +} + +ssize_t store_UV_mV_table(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + int ret = -EINVAL; + int i = 0; + int j = 0; + int u[MAX_PERF_LEVEL + 1]; + while (j < MAX_PERF_LEVEL + 1) { + int consumed; + int val; + ret = sscanf(buf, "%d%n", &val, &consumed); + if (ret > 0) { + buf += consumed; + u[j++] = val; + } + else { + break; + } + } + + for (i = 0; i < j; i++) { + if (u[i] > arm_volt_max / 1000) { + u[i] = arm_volt_max / 1000; + } + dvs_conf[i].arm_volt = u[i] * 1000; + } + + return count; +} diff --git a/arch/arm/mach-s5pv210/cpuidle.c b/arch/arm/mach-s5pv210/cpuidle.c new file mode 100644 index 0000000..d7d532a --- /dev/null +++ b/arch/arm/mach-s5pv210/cpuidle.c @@ -0,0 +1,100 @@ +/* + * arch/arm/mach-s5pv210/cpuidle.c + * + * Copyright (c) Samsung Electronics Co. Ltd + * + * CPU idle driver for S5PV210 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/cpuidle.h> +#include <linux/io.h> +#include <asm/proc-fns.h> +#include <asm/cacheflush.h> + +#include <mach/map.h> +#include <mach/regs-irq.h> +#include <mach/regs-clock.h> +#include <plat/pm.h> +#include <plat/devs.h> + +#include <mach/dma.h> +#include <mach/regs-gpio.h> + +#define S5PC110_MAX_STATES 1 + +static void s5p_enter_idle(void) +{ + unsigned long tmp; + + tmp = __raw_readl(S5P_IDLE_CFG); + tmp &= ~((3<<30)|(3<<28)|(1<<0)); + tmp |= ((2<<30)|(2<<28)); + __raw_writel(tmp, S5P_IDLE_CFG); + + tmp = __raw_readl(S5P_PWR_CFG); + tmp &= S5P_CFG_WFI_CLEAN; + __raw_writel(tmp, S5P_PWR_CFG); + + cpu_do_idle(); +} + +/* Actual code that puts the SoC in different idle states */ +static int s5p_enter_idle_normal(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + struct timeval before, after; + int idle_time; + + local_irq_disable(); + do_gettimeofday(&before); + + s5p_enter_idle(); + + do_gettimeofday(&after); + local_irq_enable(); + idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + + (after.tv_usec - before.tv_usec); + return idle_time; +} + +static DEFINE_PER_CPU(struct cpuidle_device, s5p_cpuidle_device); + +static struct cpuidle_driver s5p_idle_driver = { + .name = "s5p_idle", + .owner = THIS_MODULE, +}; + +/* Initialize CPU idle by registering the idle states */ +static int s5p_init_cpuidle(void) +{ + struct cpuidle_device *device; + + cpuidle_register_driver(&s5p_idle_driver); + + device = &per_cpu(s5p_cpuidle_device, smp_processor_id()); + device->state_count = 1; + + /* Wait for interrupt state */ + device->states[0].enter = s5p_enter_idle_normal; + device->states[0].exit_latency = 1; /* uS */ + device->states[0].target_residency = 10000; + device->states[0].flags = CPUIDLE_FLAG_TIME_VALID; + strcpy(device->states[0].name, "IDLE"); + strcpy(device->states[0].desc, "ARM clock gating - WFI"); + + if (cpuidle_register_device(device)) { + printk(KERN_ERR "s5p_init_cpuidle: Failed registering\n"); + return -EIO; + } + + return 0; +} + +device_initcall(s5p_init_cpuidle); diff --git a/arch/arm/mach-s5pv210/dev-aries-phone.c b/arch/arm/mach-s5pv210/dev-aries-phone.c new file mode 100644 index 0000000..8657009 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-aries-phone.c @@ -0,0 +1,69 @@ +/* linux/arch/arm/mach-s5pv210/dev-aries-phone.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/gpio-aries.h> + +#include "../../../drivers/misc/samsung_modemctl/modem_ctl.h" + +/* Modem control */ +static struct modemctl_data mdmctl_data = { + .name = "xmm", + .gpio_phone_active = GPIO_PHONE_ACTIVE, + .gpio_pda_active = GPIO_PDA_ACTIVE, + .gpio_cp_reset = GPIO_CP_RST, +}; + +static struct resource mdmctl_res[] = { + [0] = { + .name = "active", + .start = IRQ_EINT15, + .end = IRQ_EINT15, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "onedram", + .start = IRQ_EINT11, + .end = IRQ_EINT11, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "onedram", + .start = (S5PV210_PA_SDRAM + 0x05000000), + .end = (S5PV210_PA_SDRAM + 0x05000000 + SZ_16M - 1), + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device modemctl = { + .name = "modemctl", + .id = -1, + .num_resources = ARRAY_SIZE(mdmctl_res), + .resource = mdmctl_res, + .dev = { + .platform_data = &mdmctl_data, + }, +}; + +static int __init aries_init_phone_interface(void) +{ + platform_device_register(&modemctl); + return 0; +} +device_initcall(aries_init_phone_interface); diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 8d58f19..c6109b1 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -80,8 +80,8 @@ static struct resource s5pv210_iis0_resource[] = { }; struct platform_device s5pv210_device_iis0 = { - .name = "samsung-i2s", - .id = 0, + .name = "samsung-i2s", + .id = 0, .num_resources = ARRAY_SIZE(s5pv210_iis0_resource), .resource = s5pv210_iis0_resource, .dev = { diff --git a/arch/arm/mach-s5pv210/dev-cpufreq.c b/arch/arm/mach-s5pv210/dev-cpufreq.c new file mode 100644 index 0000000..ff0e0f1 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-cpufreq.c @@ -0,0 +1,28 @@ +/* + * linux/arch/arm/mach-s5pv210/dev-cpufreq.c + * + * Copyright (c) 2008-2010 Samsung Electronics + * Taekki Kim <taekki.kim@samsung.com> + * + * S5PV210 series device definition for cpufreq devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/cpu-freq-v210.h> + +struct platform_device s5pv210_device_cpufreq = { + .name = "s5pv210-cpufreq", + .id = -1, +}; + +void s5pv210_cpufreq_set_platdata(struct s5pv210_cpufreq_data *pdata) +{ + s5pv210_device_cpufreq.dev.platform_data = pdata; +} + diff --git a/arch/arm/mach-s5pv210/dev-fiqdbg.c b/arch/arm/mach-s5pv210/dev-fiqdbg.c new file mode 100644 index 0000000..16ef49b --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-fiqdbg.c @@ -0,0 +1,161 @@ +/* linux/arch/arm/mach-s5pv210/dev-fiqdbg.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/irq.h> +#include <linux/sysdev.h> + +#include <asm/hardware/vic.h> +#include <asm/fiq_debugger.h> + +#include <mach/irqs.h> +#include <mach/map.h> +#include <plat/regs-serial.h> + +static void *s5pv210_fiqdbg_get_base(struct platform_device *pdev) +{ + return S5P_VA_UART0 + S3C_UART_OFFSET * pdev->id; +} + +static unsigned int s5pv210_fiqdbg_tx_empty(void *base) +{ + unsigned long ufstat = readl(base + S3C2410_UFSTAT); + + return !(ufstat & (S5PV210_UFSTAT_TXMASK | S5PV210_UFSTAT_TXFULL)); +} + +static void s5pv210_fiqdbg_wait_for_tx_empty(void *base) +{ + unsigned int tmout = 10000; + + while (true) { + if (s5pv210_fiqdbg_tx_empty(base)) + return; + if (--tmout == 0) + break; + udelay(1); + } +} + +static int s5pv210_fiqdbg_uart_getc(struct platform_device *pdev) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + unsigned int ufstat; + + if (readl(base + S3C2410_UERSTAT) & S3C2410_UERSTAT_BREAK) + return FIQ_DEBUGGER_BREAK; + + ufstat = readl(base + S3C2410_UFSTAT); + if (!(ufstat & (S5PV210_UFSTAT_RXMASK | S5PV210_UFSTAT_RXFULL))) + return FIQ_DEBUGGER_NO_CHAR; + return readb(base + S3C2410_URXH); +} + +static void s5pv210_fiqdbg_uart_putc(struct platform_device *pdev, + unsigned int c) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + s5pv210_fiqdbg_wait_for_tx_empty(base); + writeb(c, base + S3C2410_UTXH); + if (c == 10) { + s5pv210_fiqdbg_wait_for_tx_empty(base); + writeb(13, base + S3C2410_UTXH); + } + s5pv210_fiqdbg_wait_for_tx_empty(base); +} + +static void fiq_enable(struct platform_device *pdev, + unsigned int fiq, bool enabled) +{ + struct irq_chip *chip = irq_get_chip(fiq); + struct irq_data *d = irq_get_irq_data(fiq); + + vic_set_fiq(fiq, enabled); + if (enabled) + chip->irq_unmask(d); + else + chip->irq_mask(d); +} + +static void fiq_ack(struct platform_device *pdev, unsigned int fiq) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + writel(0x3, base + S5P_UINTP); +} + +static int s5pv210_fiqdbg_uart_init(struct platform_device *pdev) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + + writel(S3C2410_UCON_TXILEVEL | + S3C2410_UCON_RXILEVEL | + S3C2410_UCON_TXIRQMODE | + S3C2410_UCON_RXIRQMODE | + S3C2410_UCON_RXFIFO_TOI | + S3C2443_UCON_RXERR_IRQEN, base + S3C2410_UCON); + writel(S3C2410_LCON_CS8, base + S3C2410_ULCON); + writel(S3C2410_UFCON_FIFOMODE | + S5PV210_UFCON_TXTRIG4 | + S5PV210_UFCON_RXTRIG4 | + S3C2410_UFCON_RESETRX, base + S3C2410_UFCON); + writel(0, base + S3C2410_UMCON); + /* 115200 */ + writel(35, base + S3C2410_UBRDIV); + writel(0x808, base + S3C2443_DIVSLOT); + writel(0xc, base + S5P_UINTM); + writel(0xf, base + S5P_UINTP); + + return 0; +} + +static struct fiq_debugger_pdata s5pv210_fiqdbg_pdata = { + .uart_init = s5pv210_fiqdbg_uart_init, + .uart_resume = s5pv210_fiqdbg_uart_init, + .uart_getc = s5pv210_fiqdbg_uart_getc, + .uart_putc = s5pv210_fiqdbg_uart_putc, + .fiq_enable = fiq_enable, + .fiq_ack = fiq_ack, +}; + +#define DEFINE_FIQDBG_UART(uart) \ +static struct resource s5pv210_fiqdbg_uart##uart##_resource[] = { \ + { \ + .start = IRQ_UART##uart, \ + .end = IRQ_UART##uart, \ + .name = "fiq", \ + .flags = IORESOURCE_IRQ, \ + }, \ + { \ + .start = IRQ_VIC_END-uart, \ + .end = IRQ_VIC_END-uart, \ + .name = "signal", \ + .flags = IORESOURCE_IRQ, \ + }, \ +}; \ +struct platform_device s5pv210_device_fiqdbg_uart##uart = { \ + .name = "fiq_debugger", \ + .id = uart, \ + .num_resources = ARRAY_SIZE(s5pv210_fiqdbg_uart##uart##_resource), \ + .resource = s5pv210_fiqdbg_uart##uart##_resource, \ + .dev = { \ + .platform_data = &s5pv210_fiqdbg_pdata, \ + }, \ +} + +DEFINE_FIQDBG_UART(0); +DEFINE_FIQDBG_UART(1); +DEFINE_FIQDBG_UART(2); +DEFINE_FIQDBG_UART(3); diff --git a/arch/arm/mach-s5pv210/dev-herring-phone.c b/arch/arm/mach-s5pv210/dev-herring-phone.c new file mode 100755 index 0000000..b605e02 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-herring-phone.c @@ -0,0 +1,79 @@ +/* linux/arch/arm/mach-s5pv210/dev-herring-phone.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/gpio-herring.h> + +#include "../../../drivers/misc/samsung_modemctl/modem_ctl.h" +#include "herring.h" + +/* Modem control */ +static struct modemctl_data mdmctl_data = { + .name = "xmm", + .gpio_phone_active = GPIO_PHONE_ACTIVE, + .gpio_pda_active = GPIO_PDA_ACTIVE, + .gpio_cp_reset = GPIO_CP_RST, + .gpio_phone_on = GPIO_PHONE_ON, + .is_cdma_modem = 0, + .num_pdp_contexts = 3, +}; + +static struct resource mdmctl_res[] = { + [0] = { + .name = "active", + .start = IRQ_EINT15, + .end = IRQ_EINT15, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "onedram", + .start = IRQ_EINT11, + .end = IRQ_EINT11, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "onedram", + .start = (S5PV210_PA_SDRAM + 0x05000000), + .end = (S5PV210_PA_SDRAM + 0x05000000 + SZ_16M - 1), + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device modemctl = { + .name = "modemctl", + .id = -1, + .num_resources = ARRAY_SIZE(mdmctl_res), + .resource = mdmctl_res, + .dev = { + .platform_data = &mdmctl_data, + }, +}; + +static int __init herring_init_phone_interface(void) +{ + /* CDMA device */ + if (herring_is_cdma_wimax_dev()) { + mdmctl_data.is_cdma_modem = 1; + mdmctl_data.num_pdp_contexts = 1; + } + + platform_device_register(&modemctl); + return 0; +} +device_initcall(herring_init_phone_interface); diff --git a/arch/arm/mach-s5pv210/dev-s1-phone.c b/arch/arm/mach-s5pv210/dev-s1-phone.c new file mode 100644 index 0000000..cac93ac --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-s1-phone.c @@ -0,0 +1,161 @@ +/* linux/arch/arm/mach-s5pv210/dev-s1-phone.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/gpio-aries.h> + +#if defined(CONFIG_PHONE_ARIES_CDMA) +#include "../../../drivers/misc/samsung_modemctl/dpram/onedram.h" +#include "../../../drivers/misc/samsung_modemctl/dpram/modemctl.h" +#else +#include "../../../drivers/misc/samsung_modemctl/onedram/onedram.h" +#include "../../../drivers/misc/samsung_modemctl/modemctl/modemctl.h" +#endif + + +/* onedram */ +static void onedram_cfg_gpio(void) +{ + s3c_gpio_cfgpin(GPIO_nINT_ONEDRAM_AP, S3C_GPIO_SFN(GPIO_nINT_ONEDRAM_AP_AF)); + s3c_gpio_setpull(GPIO_nINT_ONEDRAM_AP, S3C_GPIO_PULL_UP); + irq_set_irq_type(GPIO_nINT_ONEDRAM_AP, IRQ_TYPE_LEVEL_LOW); +} + +static struct onedram_platform_data onedram_data = { + .cfg_gpio = onedram_cfg_gpio, + }; + +static struct resource onedram_res[] = { + [0] = { + .start = (S5PV210_PA_SDRAM + 0x05000000), + .end = (S5PV210_PA_SDRAM + 0x05000000 + SZ_16M - 1), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EINT11, + .end = IRQ_EINT11, + .flags = IORESOURCE_IRQ, + }, + }; + +static struct platform_device onedram = { + .name = "onedram", + .id = -1, + .num_resources = ARRAY_SIZE(onedram_res), + .resource = onedram_res, + .dev = { + .platform_data = &onedram_data, + }, + }; + +/* Modem control */ + +static void modemctl_cfg_gpio(void); +static struct modemctl_platform_data mdmctl_data = { + .name = "xmm", +#if defined(CONFIG_PHONE_ARIES_CDMA) + .gpio_phone_on = GPIO_PHONE_ON, +#else + .gpio_phone_on = NULL, +#endif + .gpio_phone_active = GPIO_PHONE_ACTIVE, + .gpio_pda_active = GPIO_PDA_ACTIVE, + .gpio_cp_reset = GPIO_CP_RST, + .cfg_gpio = modemctl_cfg_gpio, + }; + +static struct resource mdmctl_res[] = { + [0] = { + .start = IRQ_EINT15, + .end = IRQ_EINT15, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_EINT(27), + .end = IRQ_EINT(27), + .flags = IORESOURCE_IRQ, + }, + }; + +static struct platform_device modemctl = { + .name = "modemctl", + .id = -1, + .num_resources = ARRAY_SIZE(mdmctl_res), + .resource = mdmctl_res, + .dev = { + .platform_data = &mdmctl_data, + }, + }; + +static void modemctl_cfg_gpio(void) +{ + int err = 0; + + unsigned gpio_phone_on = mdmctl_data.gpio_phone_on; + unsigned gpio_phone_active = mdmctl_data.gpio_phone_active; + unsigned gpio_cp_rst = mdmctl_data.gpio_cp_reset; + unsigned gpio_pda_active = mdmctl_data.gpio_pda_active; + unsigned gpio_sim_ndetect = mdmctl_data.gpio_sim_ndetect; +#if defined(CONFIG_PHONE_ARIES_CDMA) + err = gpio_request(gpio_phone_on, "PHONE_ON"); + if (err) { + printk("fail to request gpio %s\n","PHONE_ON"); + } else { + gpio_direction_output(gpio_phone_on, GPIO_LEVEL_LOW); + s3c_gpio_setpull(gpio_phone_on, S3C_GPIO_PULL_NONE); + } +#endif + err = gpio_request(gpio_cp_rst, "CP_RST"); + if (err) { + printk("fail to request gpio %s\n","CP_RST"); + } else { + gpio_direction_output(gpio_cp_rst, GPIO_LEVEL_LOW); + s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); + } + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) { + printk("fail to request gpio %s\n","PDA_ACTIVE"); + } else { + gpio_direction_output(gpio_pda_active, GPIO_LEVEL_HIGH); + s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); + } +#if !defined(CONFIG_PHONE_ARIES_CDMA) + if (mdmctl_data.gpio_reset_req_n) { + err = gpio_request(mdmctl_data.gpio_reset_req_n, "RST_REQN"); + if (err) { + printk("fail to request gpio %s\n","RST_REQN"); + } + } +#endif + s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH); + + s3c_gpio_cfgpin(gpio_sim_ndetect, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_sim_ndetect, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_sim_ndetect, IRQ_TYPE_EDGE_BOTH); +} + +static int __init p1_init_phone_interface(void) +{ + platform_device_register(&modemctl); + platform_device_register(&onedram); + return 0; +} +device_initcall(p1_init_phone_interface); diff --git a/arch/arm/mach-s5pv210/didle.S b/arch/arm/mach-s5pv210/didle.S new file mode 100644 index 0000000..a68615e --- /dev/null +++ b/arch/arm/mach-s5pv210/didle.S @@ -0,0 +1,218 @@ +/* linux/arch/arm/mach-s5pv210/didle.S + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/hardware.h> +#include <mach/map.h> +#include <asm/asm-offsets.h> +#include <asm/memory.h> +#include <asm/system.h> + +/* + * v7_flush_l1_dcache() + * + * Flush the L1 D-cache. + */ +ENTRY(v7_flush_l1_dcache) + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt finished @ finish if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb + isb + mov pc, lr +ENDPROC(v7_flush_l1_dcache) + +ENTRY(v7_flush_cache_for_didle) + stmfd sp!, {r4-r5, r7, r9-r11, lr} + bl v7_flush_l1_dcache + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + ldmfd sp!, {r4-r5, r7, r9-r11, lr} + mov pc, lr +ENDPROC(v7_flush_cache_for_didle) + +ENTRY(s5pv210_didle) + stmfd sp!, {r4-r5, r7, r9-r11, lr} + + bl v7_flush_cache_for_didle + + ldmfd sp!, {r4-r5, r7, r9-r11, lr} + dmb + dsb + wfi + + b . + + .text + + /* s5pv210_didle_save + * + * entry: + * r0 = save address (virtual addr of s3c_sleep_save_phys) + */ + +ENTRY(s5pv210_didle_save) + + stmfd sp!, { r3 - r12, lr } + + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control + mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mrc p15, 0, r12, c10, c2, 0 @ Read PRRR + mrc p15, 0, r3, c10, c2, 1 @ READ NMRR + + /* Save CP15 registers */ + stmia r0, { r3 - r13 } + + bl s5pv210_didle + + @@ return to the caller, after having the MMU + @@ turned on, this restores the last bits from the + @@ stack +resume_with_mmu: + mrc p15, 0, r0, c1, c0, 1 @enable L2 cache + orr r0, r0, #(1<<1) + mcr p15, 0, r0, c1, c0, 1 + + mov r0, #1 + /* delete added mmu table list */ + ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET) + add r4, r4, r9 + str r12, [r4] + + ldmfd sp!, { r3 - r12, pc } + + .ltorg + + /* s5pv210_didle_resume + * + * resume code entry for bootloader to call + * + * we must put this code here in the data segment as we have no + * other way of restoring the stack pointer after sleep, and we + * must not write to the code segment (code is read-only) + */ + +ENTRY(s5pv210_didle_resume) + mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE + msr cpsr_c, r0 + + @@ load UART to allow us to print the two characters for + @@ resume debug + + mov r1, #0 + mcr p15, 0, r1, c8, c7, 0 @@ invalidate TLBs + mcr p15, 0, r1, c7, c5, 0 @@ invalidate I Cache + + ldr r1, =0xe010f008 @ Read INFORM2 register + ldr r0, [r1] @ Load phy_regs_save value + ldmia r0, { r3 - r13 } + + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + + mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control + mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + + bic r10, r10, #(1<<1) @ disable L2cache + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB + + mov r0, #0 @ restore copro access controls + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mcr p15, 0, r0, c7, c5, 4 + + mcr p15, 0, r12, c10, c2, 0 @ write PRRR + mcr p15, 0, r3, c10, c2, 1 @ write NMRR + + /* calculate first section address into r8 */ + mov r4, r6 + ldr r5, =0x3fff + bic r4, r4, r5 + ldr r11, =0xe010f000 + ldr r10, [r11, #0] + mov r10, r10 ,LSR #18 + bic r10, r10, #0x3 + orr r4, r4, r10 + + /* calculate mmu list value into r9 */ + mov r10, r10, LSL #18 + ldr r5, =0x40e + orr r10, r10, r5 + + /* back up originally data */ + ldr r12, [r4] + + /* Added list about mmu */ + str r10, [r4] + + ldr r2, =resume_with_mmu + mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc + + nop + nop + nop + nop + nop @ second-to-last before mmu + + mov pc, r2 @ go back to virtual address + + .ltorg diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index 497d343..34cfacc 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -30,6 +30,71 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); +static struct resource s5pv210_mdma_resource[] = { + [0] = { + .start = S5PV210_PA_MDMA, + .end = S5PV210_PA_MDMA + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MDMA, + .end = IRQ_MDMA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pv210_mdma_pdata = { + .peri = { + /* The DMAC can have max 8 channel so there + * can be 8 M<->M requests served at any time. + */ + [0] = DMACH_MTOM_0, + [1] = DMACH_MTOM_1, + [2] = DMACH_MTOM_2, + [3] = DMACH_MTOM_3, + [4] = DMACH_MTOM_4, + [5] = DMACH_MTOM_5, + [6] = DMACH_MTOM_6, + [7] = DMACH_MTOM_7, + [8] = DMACH_MAX, + [9] = DMACH_MAX, + [10] = DMACH_MAX, + [11] = DMACH_MAX, + [12] = DMACH_MAX, + [13] = DMACH_MAX, + [14] = DMACH_MAX, + [15] = DMACH_MAX, + [16] = DMACH_MAX, + [17] = DMACH_MAX, + [18] = DMACH_MAX, + [19] = DMACH_MAX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_MAX, + [23] = DMACH_MAX, + [24] = DMACH_MAX, + [25] = DMACH_MAX, + [26] = DMACH_MAX, + [27] = DMACH_MAX, + [28] = DMACH_MAX, + [29] = DMACH_MAX, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +struct platform_device s5pv210_device_mdma = { + .name = "s3c-pl330", + .id = 0, + .num_resources = ARRAY_SIZE(s5pv210_mdma_resource), + .resource = s5pv210_mdma_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_mdma_pdata, + }, +}; + static struct resource s5pv210_pdma0_resource[] = { [0] = { .start = S5PV210_PA_PDMA0, @@ -80,9 +145,9 @@ static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { }, }; -static struct platform_device s5pv210_device_pdma0 = { +struct platform_device s5pv210_device_pdma0 = { .name = "s3c-pl330", - .id = 0, + .id = 1, .num_resources = ARRAY_SIZE(s5pv210_pdma0_resource), .resource = s5pv210_pdma0_resource, .dev = { @@ -142,9 +207,9 @@ static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { }, }; -static struct platform_device s5pv210_device_pdma1 = { +struct platform_device s5pv210_device_pdma1 = { .name = "s3c-pl330", - .id = 1, + .id = 2, .num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), .resource = s5pv210_pdma1_resource, .dev = { @@ -155,6 +220,7 @@ static struct platform_device s5pv210_device_pdma1 = { }; static struct platform_device *s5pv210_dmacs[] __initdata = { + &s5pv210_device_mdma, &s5pv210_device_pdma0, &s5pv210_device_pdma1, }; diff --git a/arch/arm/mach-s5pv210/herring-btlpm.c b/arch/arm/mach-s5pv210/herring-btlpm.c new file mode 100644 index 0000000..362f35a --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-btlpm.c @@ -0,0 +1,66 @@ +/* linux/arch/arm/mach-s5pv210/herring-btlpm.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/hrtimer.h> + +#include <asm/mach-types.h> + +#include <mach/gpio-herring.h> + +#include "herring.h" + +static struct herring_bt_lpm { + struct hrtimer bt_lpm_timer; + ktime_t bt_lpm_delay; +} bt_lpm; + +static enum hrtimer_restart bt_enter_lpm(struct hrtimer *timer) +{ + gpio_set_value(GPIO_BT_WAKE, 0); + + return HRTIMER_NORESTART; +} + +void herring_bt_uart_wake_peer(struct uart_port *port) +{ + if (!bt_lpm.bt_lpm_timer.function) + return; + + hrtimer_try_to_cancel(&bt_lpm.bt_lpm_timer); + gpio_set_value(GPIO_BT_WAKE, 1); + hrtimer_start(&bt_lpm.bt_lpm_timer, bt_lpm.bt_lpm_delay, HRTIMER_MODE_REL); +} + +static int __init bt_lpm_init(void) +{ + int ret; + + if (!machine_is_herring()) + return 0; + + ret = gpio_request(GPIO_BT_WAKE, "gpio_bt_wake"); + if (ret) { + printk(KERN_ERR "Failed to request gpio_bt_wake control\n"); + return 0; + } + + gpio_direction_output(GPIO_BT_WAKE, GPIO_LEVEL_LOW); + + hrtimer_init(&bt_lpm.bt_lpm_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + bt_lpm.bt_lpm_delay = ktime_set(1, 0); /* 1 sec */ + bt_lpm.bt_lpm_timer.function = bt_enter_lpm; + return 0; +} +device_initcall(bt_lpm_init); diff --git a/arch/arm/mach-s5pv210/herring-panel.c b/arch/arm/mach-s5pv210/herring-panel.c new file mode 100755 index 0000000..8f69681 --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-panel.c @@ -0,0 +1,1012 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/tl2796.h> +#include <linux/nt35580.h> +#include <mach/gpio.h> +#include <linux/delay.h> + +static const u16 s6e63m0_SEQ_STANDBY_ON[] = { + 0x010, /* Stand-by On Command */ + SLEEPMSEC, 160, + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_STANDBY_OFF[] = { + 0x011, /* Stand-by Off Command */ + SLEEPMSEC, 120, + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_DISPLAY_SETTING[] = { + SLEEPMSEC, 10, + 0x0F8, /* Panel Condition Set Command*/ + 0x101, /* DOCT */ + 0x127, /* CLWEA */ + 0x127, /* CLWEB*/ + 0x107, /* CLTE */ + 0x107, /* SHE */ + 0x154, /* FLTE */ + 0x19F, /* FLWE */ + 0x163, /* SCTE */ + 0x186, /* SCWE */ + 0x11A, /* INTE */ + 0x133, /* INWE */ + 0x10D, /* EMPS */ + 0x100, /* E_INTE */ + 0x100, /* E_INWE */ + 0x0F2, /* Display Condition Set Command*/ + 0x102, /* Number of Line */ + 0x103, /* VBP */ + 0x11C, /* VFP */ + 0x110, /* HBP */ + 0x110, /* HFP */ + 0x0F7, /* Command */ + 0x103, /* GTCON */ + 0x100, /* Display Mode */ + 0x100, /* Vsync/Hsync, DOCCLK, RGB mode */ + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_ETC_SETTING[] = { + /* ETC Condition Set Command */ + 0x0F6, + 0x100, 0x18E, + 0x107, + 0x0B3, + 0x16C, + 0x0B5, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0B6, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x0B7, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0B8, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x0B9, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0BA, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x011, + SLEEPMSEC, 120, + 0x029, + ENDDEF, 0x0000 +}; + +static const struct tl2796_gamma_adj_points gamma_adj_points = { + .v0 = 0, + .v1 = BV_1, + .v19 = BV_19, + .v43 = BV_43, + .v87 = BV_87, + .v171 = BV_171, + .v255 = BV_255, +}; + +static const struct gamma_entry gamma_table[] = { + { BV_0, { 4200000, 4200000, 4200000, }, }, + { 1, { 3994200, 4107600, 3910200, }, }, + { 0x00000400, { 3669486, 3738030, 3655093, }, }, + { 0x000004C2, { 3664456, 3732059, 3649872, }, }, + { 0x000005A8, { 3659356, 3726019, 3644574, }, }, + { 0x000006BA, { 3654160, 3719879, 3639171, }, }, + { 0x00000800, { 3648872, 3713646, 3633668, }, }, + { 0x00000983, { 3643502, 3707331, 3628075, }, }, + { 0x00000B50, { 3638029, 3700909, 3622368, }, }, + { 0x00000D74, { 3632461, 3694392, 3616558, }, }, + { 0x00001000, { 3626792, 3687772, 3610636, }, }, + { 0x00001307, { 3621022, 3681052, 3604605, }, }, + { 0x000016A1, { 3615146, 3674224, 3598455, }, }, + { 0x00001AE9, { 3609163, 3667289, 3592189, }, }, + { 0x00002000, { 3603070, 3660245, 3585801, }, }, + { 0x0000260E, { 3596860, 3653083, 3579284, }, }, + { 0x00002D41, { 3590532, 3645805, 3572637, }, }, + { 0x000035D1, { 3584081, 3638403, 3565854, }, }, + { 0x00004000, { 3577504, 3630876, 3558930, }, }, + { 0x00004C1C, { 3570797, 3623221, 3551863, }, }, + { 0x00005A82, { 3563956, 3615434, 3544649, }, }, + { 0x00006BA2, { 3556976, 3607510, 3537279, }, }, + { 0x00008000, { 3549853, 3599444, 3529750, }, }, + { 0x00009838, { 3542582, 3591234, 3522056, }, }, + { 0x0000B505, { 3535159, 3582874, 3514193, }, }, + { 0x0000D745, { 3527577, 3574360, 3506153, }, }, + { 0x00010000, { 3519832, 3565687, 3497931, }, }, + { 0x00013070, { 3511918, 3556849, 3489519, }, }, + { 0x00016A0A, { 3503829, 3547842, 3480912, }, }, + { 0x0001AE8A, { 3495559, 3538659, 3472102, }, }, + { 0x00020000, { 3487101, 3529295, 3463080, }, }, + { 0x000260E0, { 3478447, 3519742, 3453839, }, }, + { 0x0002D414, { 3469592, 3509996, 3444372, }, }, + { 0x00035D14, { 3460527, 3500049, 3434667, }, }, + { 0x00040000, { 3451244, 3489893, 3424717, }, }, + { 0x0004C1C0, { 3441734, 3479522, 3414512, }, }, + { 0x0005A828, { 3431990, 3468927, 3404040, }, }, + { 0x0006BA28, { 3422000, 3458099, 3393292, }, }, + { 0x00080000, { 3411756, 3447030, 3382254, }, }, + { 0x0009837F, { 3401247, 3435711, 3370915, }, }, + { 0x000B504F, { 3390462, 3424131, 3359262, }, }, + { 0x000D7450, { 3379388, 3412280, 3347281, }, }, + { 0x00100000, { 3368014, 3400147, 3334957, }, }, + { 0x001306FE, { 3356325, 3387721, 3322274, }, }, + { 0x0016A09E, { 3344309, 3374988, 3309216, }, }, + { 0x001AE8A0, { 3331950, 3361936, 3295765, }, }, + { 0x00200000, { 3319231, 3348550, 3281902, }, }, + { 0x00260DFC, { 3306137, 3334817, 3267607, }, }, + { 0x002D413D, { 3292649, 3320719, 3252859, }, }, + { 0x0035D13F, { 3278748, 3306240, 3237634, }, }, + { 0x00400000, { 3264413, 3291361, 3221908, }, }, + { 0x004C1BF8, { 3249622, 3276065, 3205654, }, }, + { 0x005A827A, { 3234351, 3260329, 3188845, }, }, + { 0x006BA27E, { 3218576, 3244131, 3171449, }, }, + { 0x00800000, { 3202268, 3227448, 3153434, }, }, + { 0x009837F0, { 3185399, 3210255, 3134765, }, }, + { 0x00B504F3, { 3167936, 3192523, 3115404, }, }, + { 0x00D744FD, { 3149847, 3174223, 3095308, }, }, + { 0x01000000, { 3131093, 3155322, 3074435, }, }, + { 0x01306FE1, { 3111635, 3135786, 3052735, }, }, + { 0x016A09E6, { 3091431, 3115578, 3030156, }, }, + { 0x01AE89FA, { 3070432, 3094655, 3006641, }, }, + { 0x02000000, { 3048587, 3072974, 2982127, }, }, + { 0x0260DFC1, { 3025842, 3050485, 2956547, }, }, + { 0x02D413CD, { 3002134, 3027135, 2929824, }, }, + { 0x035D13F3, { 2977397, 3002865, 2901879, }, }, + { 0x04000000, { 2951558, 2977611, 2872620, }, }, + { 0x04C1BF83, { 2924535, 2951302, 2841948, }, }, + { 0x05A8279A, { 2896240, 2923858, 2809753, }, }, + { 0x06BA27E6, { 2866574, 2895192, 2775914, }, }, + { 0x08000000, { 2835426, 2865207, 2740295, }, }, + { 0x09837F05, { 2802676, 2833793, 2702744, }, }, + { 0x0B504F33, { 2768187, 2800829, 2663094, }, }, + { 0x0D744FCD, { 2731806, 2766175, 2621155, }, }, + { 0x10000000, { 2693361, 2729675, 2576712, }, }, + { 0x1306FE0A, { 2652659, 2691153, 2529527, }, }, + { 0x16A09E66, { 2609480, 2650402, 2479324, }, }, + { 0x1AE89F99, { 2563575, 2607191, 2425793, }, }, + { 0x20000000, { 2514655, 2561246, 2368579, }, }, + { 0x260DFC14, { 2462394, 2512251, 2307272, }, }, + { 0x2D413CCD, { 2406412, 2459834, 2241403, }, }, + { 0x35D13F32, { 2346266, 2403554, 2170425, }, }, + { 0x40000000, { 2281441, 2342883, 2093706, }, }, + { 0x4C1BF828, { 2211332, 2277183, 2010504, }, }, + { 0x5A82799A, { 2135220, 2205675, 1919951, }, }, + { 0x6BA27E65, { 2052250, 2127391, 1821028, }, }, + { 0x80000000, { 1961395, 2041114, 1712536, }, }, + { 0x9837F051, { 1861415, 1945288, 1593066, }, }, + { 0xB504F333, { 1750800, 1837874, 1460986, }, }, + { 0xD744FCCA, { 1627706, 1716150, 1314437, }, }, + { 0xFFFFFFFF, { 1489879, 1576363, 1151415, }, }, +}; + +static void reset_lcd(struct s5p_panel_data *pdata) +{ + gpio_direction_output(pdata->gpio_rst, 1); + msleep(10); + + gpio_set_value(pdata->gpio_rst, 0); + msleep(10); + + gpio_set_value(pdata->gpio_rst, 1); + msleep(10); +} + +static int configure_mtp_gpios(struct s5p_panel_data *pdata, bool enable) +{ + int i; + int ret = 0; + if (enable) { + /* wrx and csx are already requested by the spi driver */ + ret = gpio_request(pdata->gpio_rdx, "tl2796_rdx"); + if (ret) + goto err_rdx; + ret = gpio_request(pdata->gpio_dcx, "tl2796_dcx"); + if (ret) + goto err_dcx; + ret = gpio_request(pdata->gpio_rst, "tl2796_rst"); + if (ret) + goto err_rst; + for (i = 0; i < 8; i++) { + ret = gpio_request(pdata->gpio_db[i], "tl2796_dbx"); + if (ret) + goto err_dbx; + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF0(i), 0); + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_UP); + gpio_set_value(S5PV210_GPF1(i), 0); + } + return 0; + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + reset_lcd(pdata); + + for (i = 7; i >= 0; i--) { + gpio_free(pdata->gpio_db[i]); +err_dbx: + ; + } + gpio_free(pdata->gpio_rst); +err_rst: + gpio_free(pdata->gpio_dcx); +err_dcx: + gpio_free(pdata->gpio_rdx); +err_rdx: + return ret; +} + +struct s5p_panel_data herring_panel_data = { + .seq_display_set = s6e63m0_SEQ_DISPLAY_SETTING, + .seq_etc_set = s6e63m0_SEQ_ETC_SETTING, + .standby_on = s6e63m0_SEQ_STANDBY_ON, + .standby_off = s6e63m0_SEQ_STANDBY_OFF, + .gpio_dcx = S5PV210_GPF0(0), /* H_SYNC pad */ + .gpio_rdx = S5PV210_GPF0(2), /* Enable */ + .gpio_csx = S5PV210_MP01(1), + .gpio_wrx = S5PV210_MP04(1), /* SCL pad */ + .gpio_rst = S5PV210_MP05(5), + .gpio_db = { + S5PV210_GPF0(4), + S5PV210_GPF0(5), + S5PV210_GPF0(6), + S5PV210_GPF0(7), + S5PV210_GPF1(0), + S5PV210_GPF1(1), + S5PV210_GPF1(2), + S5PV210_GPF1(3), + }, + .configure_mtp_gpios = configure_mtp_gpios, + .factory_v255_regs = { + 0x0b9, + 0x0b8, + 0x0fc, + }, + .color_adj = { + /* Convert from 8500K to D65, assuming: + * Rx 0.66950, Ry 0.33100 + * Gx 0.18800, Gy 0.74350 + * Bx 0.14142, By 0.04258 + */ + .mult = { + 2318372099U, + 2117262806U, + 1729744557U, + }, + .rshift = 31, + }, + + .gamma_adj_points = &gamma_adj_points, + .gamma_table = gamma_table, + .gamma_table_size = ARRAY_SIZE(gamma_table), +}; + +static const u16 brightness_setting_table[] = { + 0x051, 0x17f, + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_DISPLAY_ON[] = { + 0x029, + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_DISPLAY_OFF[] = { + 0x028, + SLEEPMSEC, 27, /* more than 25ms */ + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_SETTING[] = { + /* SET_PIXEL_FORMAT */ + 0x3A, + 0x177, /* 24 bpp */ + /* RGBCTRL */ + 0x3B, + /* RGB Mode1, DE is sampled at the rising edge of PCLK, + * P-rising edge, EP- low active, HSP-low active, VSP-low active */ + 0x107, + 0x10A, + 0x10E, + 0x10A, + 0x10A, + /* SET_HORIZONTAL_ADDRESS (Frame Memory Area define) */ + 0x2A, + 0x100, + 0x100, + 0x101, /* 480x800 */ + 0x1DF, /* 480x800 */ + /* SET_VERTICAL_ADDRESS (Frame Memory Area define) */ + 0x2B, + 0x100, + 0x100, + 0x103, /* 480x800 */ + 0x11F, /* 480x800 */ + /* SET_ADDRESS_MODE */ + 0x36, + 0x1D4, + SLEEPMSEC, 30, /* recommend by Sony-LCD, */ + /* SLPOUT */ + 0x11, + SLEEPMSEC, 155, /* recommend by Sony */ + /* WRCTRLD-1 */ + 0x55, + 0x100, /* CABC Off 1: UI-Mode, 2:Still-Mode, 3:Moving-Mode */ + /* WRCABCMB */ + 0x5E, + /* Minimum Brightness Value Setting 0:the lowest, 0xFF:the highest */ + 0x100, + /* WRCTRLD-2 */ + 0x53, + /* BCTRL(1)-PWM Output Enable, A(0)-LABC Off, + * DD(1)-Enable Dimming Function Only for CABC, + * BL(1)-turn on Backlight Control without dimming effect */ + 0x12C, + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_SLEEP_IN[] = { + 0x010, + SLEEPMSEC, 155, /* more than 150ms */ + ENDDEF, 0x0000 +}; + +struct s5p_tft_panel_data herring_sony_panel_data = { + .seq_set = nt35580_SEQ_SETTING, + .sleep_in = nt35580_SEQ_SLEEP_IN, + .display_on = nt35580_SEQ_DISPLAY_ON, + .display_off = nt35580_SEQ_DISPLAY_OFF, + .brightness_set = brightness_setting_table, + .pwm_reg_offset = 1, +}; + +/* Hydis Panel (nt35510) */ +static const u16 nt35510_SEQ_SETTING[] = { + 0xFF, + 0x1AA, + 0x155, + 0x125, + 0x101, + + 0xF3, + 0x100, + 0x132, + 0x100, + 0x138, + 0x131, + 0x108, + 0x111, + 0x100, + + /* Enable CMD2_Page1 */ + 0xF0, + 0x155, + 0x1AA, + 0x152, + 0x108, + 0x100, + + 0xB0, + 0x104, + 0x10A, + 0x10E, + 0x109, + 0x104, + + 0xB1, + 0x1CC, + 0x104, + + 0x36, 0x102, + 0xB3, 0x100, + + /* AVDD */ + 0xB6, + 0x103, + + 0xB7, + 0x170, + 0x170, + + 0xB8, + 0x100, + 0x106, + 0x106, + 0x106, + + 0xBC, + 0x100, + 0x100, + 0x100, + + 0xBD, + 0x101, + 0x184, + 0x106, + 0x150, + 0x100, + + 0xCC, + 0x101, + 0x101, + 0x106, + + 0xF0, + 0x155, + 0x1AA, + 0x152, + 0x108, + 0x1101, + + 0xB0, + 0x104, + 0x10A, + 0x10E, + 0x109, + 0x104, + + 0xB1, + 0x105, + 0x105, + 0x105, + + 0xB2, + 0x103, + 0x103, + 0x103, + + 0xB8, + 0x125, + 0x125, + 0x125, + + 0xB3, + 0x100, + + 0xB9, + 0x134, + 0x134, + 0x134, + + /* VGH */ + 0xBF, + 0x101, + + 0xB5, + 0x109, + 0x109, + 0x109, + + /* VGL */ + 0xBA, + 0x124, + 0x124, + 0x124, + + 0xB4, + 0x124, + 0x124, + 0x124, + + 0xBC, + 0x100, + 0x168, + 0x100, + + 0xBD, + 0x100, + 0x17c, + 0x100, + + 0xBE, + 0x100, + 0x145, + + 0xD0, + 0x10A, + 0x114, + 0x10A, + 0x10E, + + 0xD1, + 0x100, + 0x137, + 0x100, + 0x161, + 0x100, + 0x192, + 0x100, + 0x1B4, + 0x100, + 0x1CF, + 0x100, + 0x1F6, + 0x101, + 0x12F, + 0x101, + 0x17F, + 0x101, + 0x197, + 0x101, + 0x1C0, + 0x101, + 0x1E5, + 0x102, + 0x125, + 0x102, + 0x15E, + 0x102, + 0x160, + 0x102, + 0x187, + 0x102, + 0x1BE, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD2, + 0x100, + 0x137, + 0x100, + 0x161, + 0x100, + 0x192, + 0x100, + 0x1B4, + 0x100, + 0x1CF, + 0x100, + 0x1F6, + 0x101, + 0x12F, + 0x101, + 0x17F, + 0x101, + 0x197, + 0x101, + 0x1C0, + 0x101, + 0x1E5, + 0x102, + 0x125, + 0x102, + 0x15E, + 0x102, + 0x160, + 0x102, + 0x187, + 0x102, + 0x1BE, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD3, + 0x100, + 0x137, + 0x100, + 0x161, + 0x100, + 0x192, + 0x100, + 0x1B4, + 0x100, + 0x1CF, + 0x100, + 0x1F6, + 0x101, + 0x12F, + 0x101, + 0x17F, + 0x101, + 0x197, + 0x101, + 0x1C0, + 0x101, + 0x1E5, + 0x102, + 0x125, + 0x102, + 0x15E, + 0x102, + 0x160, + 0x102, + 0x187, + 0x102, + 0x1BE, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD4, + 0x100, + 0x137, + 0x100, + 0x150, + 0x100, + 0x189, + 0x100, + 0x1A9, + 0x100, + 0x1C0, + 0x100, + 0x1F6, + 0x101, + 0x114, + 0x101, + 0x148, + 0x101, + 0x16B, + 0x101, + 0x1A7, + 0x101, + 0x1D3, + 0x102, + 0x117, + 0x102, + 0x14F, + 0x102, + 0x151, + 0x102, + 0x186, + 0x102, + 0x1BD, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD5, + 0x100, + 0x137, + 0x100, + 0x150, + 0x100, + 0x189, + 0x100, + 0x1A9, + 0x100, + 0x1C0, + 0x100, + 0x1F6, + 0x101, + 0x114, + 0x101, + 0x148, + 0x101, + 0x16B, + 0x101, + 0x1A7, + 0x101, + 0x1D3, + 0x102, + 0x117, + 0x102, + 0x14F, + 0x102, + 0x151, + 0x102, + 0x186, + 0x102, + 0x1BD, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD6, + 0x100, + 0x137, + 0x100, + 0x150, + 0x100, + 0x189, + 0x100, + 0x1A9, + 0x100, + 0x1C0, + 0x100, + 0x1F6, + 0x101, + 0x114, + 0x101, + 0x148, + 0x101, + 0x16B, + 0x101, + 0x1A7, + 0x101, + 0x1D3, + 0x102, + 0x117, + 0x102, + 0x14F, + 0x102, + 0x151, + 0x102, + 0x186, + 0x102, + 0x1BD, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xF0, + 0x155, + 0x1AA, + 0x152, + 0x108, + 0x101, + + ENDDEF, 0x0000 +}; + +static const u16 nt35510_SEQ_DISPLAY_ON[] = { + 0x53, 0x12C, + 0x11, + SLEEPMSEC, 120, + 0x29, + ENDDEF, 0x0000 +}; + +static const u16 nt35510_SEQ_DISPLAY_OFF[] = { + 0x28, + SLEEPMSEC, 27, + ENDDEF, 0x0000 +}; +static const u16 nt35510_SEQ_SLEEP_IN[] = { + 0x10, + SLEEPMSEC, 155, /* more than 150ms */ + ENDDEF, 0x0000 +}; + +struct s5p_tft_panel_data herring_hydis_panel_data = { + .seq_set = nt35510_SEQ_SETTING, + .display_on = nt35510_SEQ_DISPLAY_ON, + .sleep_in = nt35510_SEQ_SLEEP_IN, + .display_off = nt35510_SEQ_DISPLAY_OFF, + .brightness_set = brightness_setting_table, + .pwm_reg_offset = 1, +}; + +/* hitachi panel (R61408) */ +static const u16 R61408_SEQ_SETTING[] = { + 0x36, 0x100, + 0x3A, 0x177, + + 0x11, + SLEEPMSEC, 150, + + 0xB0, 0x104, + 0xC1, 0x142, + 0x131, 0x104, + 0xB0, 0x103, + ENDDEF, 0x0000 +}; + +static const u16 R61408_SEQ_DISPLAY_ON[] = { + 0x29, + ENDDEF, 0x0000 +}; + +static const u16 R61408_SEQ_DISPLAY_OFF[] = { + 0xB0, 0x104, + 0xB1, 0x101, + SLEEPMSEC, 2, + ENDDEF, 0x0000 +}; +static const u16 R61408_SEQ_SLEEP_IN[] = { + 0x10, + SLEEPMSEC, 150, /* more than 150ms */ + ENDDEF, 0x0000 +}; + +static const u16 R61408_brightness_setting_table[] = { + 0xB0, 0x102, + 0xB9, 0x100, + 0x1F7, 0x102, + 0x108, + 0xB0, 0x103, + ENDDEF, 0x0000 +}; +struct s5p_tft_panel_data herring_hitachi_panel_data = { + .seq_set = R61408_SEQ_SETTING, + .display_on = R61408_SEQ_DISPLAY_ON, + .sleep_in = R61408_SEQ_SLEEP_IN, + .display_off = R61408_SEQ_DISPLAY_OFF, + .brightness_set = R61408_brightness_setting_table, + .pwm_reg_offset = 4, +}; + diff --git a/arch/arm/mach-s5pv210/herring-rfkill.c b/arch/arm/mach-s5pv210/herring-rfkill.c new file mode 100644 index 0000000..2115d9f --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-rfkill.c @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co., Ltd. + * + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Modified for Crespo on August, 2010 By Samsung Electronics Co. + * This is modified operate according to each status. + * + */ + +/* Control bluetooth power for Crespo platform */ + +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/rfkill.h> +#include <linux/delay.h> +#include <linux/types.h> +#include <linux/wakelock.h> +#include <linux/irq.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <mach/gpio.h> +#include <mach/gpio-herring.h> +#include <mach/hardware.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> +#include "herring.h" + +#define IRQ_BT_HOST_WAKE IRQ_EINT(21) + +static struct wake_lock rfkill_wake_lock; + +#ifndef GPIO_LEVEL_LOW +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#endif + +static struct rfkill *bt_rfk; +static const char bt_name[] = "bcm4329"; + +static int bluetooth_set_power(void *data, enum rfkill_user_states state) +{ + int ret = 0; + int irq; + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + switch (state) { + + case RFKILL_USER_STATE_UNBLOCKED: + pr_debug("[BT] Device Powering ON\n"); + + s3c_setup_uart_cfg_gpio(0); + + if (gpio_is_valid(GPIO_WLAN_BT_EN)) + gpio_direction_output(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + if (gpio_is_valid(GPIO_BT_nRST)) + gpio_direction_output(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* Set GPIO_BT_WLAN_REG_ON high */ + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + /* + * FIXME sleep should be enabled disabled since the device is + * not booting if its enabled + */ + /* + * 100msec, delay between reg_on & rst. + * (bcm4329 powerup sequence) + */ + msleep(100); + + /* Set GPIO_BT_nRST high */ + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* + * 50msec, delay after bt rst + * (bcm4329 powerup sequence) + */ + msleep(50); + + ret = enable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] set wakeup src failed\n"); + + enable_irq(irq); + break; + + case RFKILL_USER_STATE_SOFT_BLOCKED: + pr_debug("[BT] Device Powering OFF\n"); + + ret = disable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] unset wakeup src failed\n"); + + disable_irq(irq); + wake_unlock(&rfkill_wake_lock); + + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + if (gpio_get_value(GPIO_WLAN_nRST) == 0) { + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + } + + break; + + default: + pr_err("[BT] Bad bluetooth rfkill state %d\n", state); + } + + return 0; +} + +irqreturn_t bt_host_wake_irq_handler(int irq, void *dev_id) +{ + pr_debug("[BT] bt_host_wake_irq_handler start\n"); + + if (gpio_get_value(GPIO_BT_HOST_WAKE)) + wake_lock(&rfkill_wake_lock); + else + wake_lock_timeout(&rfkill_wake_lock, HZ); + + return IRQ_HANDLED; +} + +static int bt_rfkill_set_block(void *data, bool blocked) +{ + unsigned int ret = 0; + + ret = bluetooth_set_power(data, blocked ? + RFKILL_USER_STATE_SOFT_BLOCKED : + RFKILL_USER_STATE_UNBLOCKED); + + return ret; +} + +static const struct rfkill_ops bt_rfkill_ops = { + .set_block = bt_rfkill_set_block, +}; + +static int __init herring_rfkill_probe(struct platform_device *pdev) +{ + int irq; + int ret; + + /* Initialize wake locks */ + wake_lock_init(&rfkill_wake_lock, WAKE_LOCK_SUSPEND, "bt_host_wake"); + + ret = gpio_request(GPIO_WLAN_BT_EN, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_WLAN_BT_EN!\n"); + goto err_req_gpio_wlan_bt_en; + } + + ret = gpio_request(GPIO_BT_nRST, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_BT_nRST!\n"); + goto err_req_gpio_bt_nrst; + } + + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + ret = request_irq(irq, bt_host_wake_irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "bt_host_wake_irq_handler", NULL); + + if (ret < 0) { + pr_err("[BT] Request_irq failed\n"); + goto err_req_irq; + } + + disable_irq(irq); + + bt_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &bt_rfkill_ops, NULL); + + if (!bt_rfk) { + pr_err("[BT] bt_rfk : rfkill_alloc is failed\n"); + ret = -ENOMEM; + goto err_alloc; + } + + rfkill_init_sw_state(bt_rfk, 0); + + pr_debug("[BT] rfkill_register(bt_rfk)\n"); + + ret = rfkill_register(bt_rfk); + if (ret) { + pr_debug("********ERROR IN REGISTERING THE RFKILL********\n"); + goto err_register; + } + + rfkill_set_sw_state(bt_rfk, 1); + bluetooth_set_power(NULL, RFKILL_USER_STATE_SOFT_BLOCKED); + + return ret; + + err_register: + rfkill_destroy(bt_rfk); + + err_alloc: + free_irq(irq, NULL); + + err_req_irq: + gpio_free(GPIO_BT_nRST); + + err_req_gpio_bt_nrst: + gpio_free(GPIO_WLAN_BT_EN); + + err_req_gpio_wlan_bt_en: + return ret; +} + +static struct platform_driver herring_device_rfkill = { + .probe = herring_rfkill_probe, + .driver = { + .name = "bt_rfkill", + .owner = THIS_MODULE, + }, +}; + +static int __init herring_rfkill_init(void) +{ + int rc = 0; + rc = platform_driver_register(&herring_device_rfkill); + + return rc; +} + +module_init(herring_rfkill_init); +MODULE_DESCRIPTION("herring rfkill"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/herring-touchkey-led.c b/arch/arm/mach-s5pv210/herring-touchkey-led.c new file mode 100644 index 0000000..b36e0f0 --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-touchkey-led.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. All Rights Reserved. + * Author: Rom Lemarchand <rlemarchand@sta.samsung.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/earlysuspend.h> +#include <asm/mach-types.h> + +#include "herring.h" + +static int led_gpios[] = { 2, 3, 6, 7 }; + +static void herring_touchkey_led_onoff(int onoff) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) + gpio_direction_output(S5PV210_GPJ3(led_gpios[i]), !!onoff); +} + +static void herring_touchkey_led_early_suspend(struct early_suspend *h) +{ + herring_touchkey_led_onoff(0); +} + +static void herring_touchkey_led_late_resume(struct early_suspend *h) +{ + herring_touchkey_led_onoff(1); +} + +static struct early_suspend early_suspend = { + .level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1, + .suspend = herring_touchkey_led_early_suspend, + .resume = herring_touchkey_led_late_resume, +}; + +static int __init herring_init_touchkey_led(void) +{ + int i; + int ret = 0; + + if (!machine_is_herring() || !herring_is_tft_dev()) + return 0; + + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) { + ret = gpio_request(S5PV210_GPJ3(led_gpios[i]), "touchkey led"); + if (ret) { + pr_err("Failed to request touchkey led gpio %d\n", i); + goto err_req; + } + s3c_gpio_setpull(S5PV210_GPJ3(led_gpios[i]), + S3C_GPIO_PULL_NONE); + } + + herring_touchkey_led_onoff(1); + + register_early_suspend(&early_suspend); + + return 0; + +err_req: + while (--i >= 0) + gpio_free(S5PV210_GPJ3(led_gpios[i])); + return ret; +} + +device_initcall(herring_init_touchkey_led); diff --git a/arch/arm/mach-s5pv210/herring-vibrator.c b/arch/arm/mach-s5pv210/herring-vibrator.c new file mode 100644 index 0000000..323520f --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-vibrator.c @@ -0,0 +1,149 @@ +/* arch/arm/mach-s5pv210/herring-vibrator.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. All Rights Reserved. + * Author: Rom Lemarchand <rlemarchand@sta.samsung.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/hrtimer.h> +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/pwm.h> +#include <linux/wakelock.h> +#include <linux/mutex.h> +#include <linux/clk.h> +#include <linux/workqueue.h> + +#include <asm/mach-types.h> + +#include <../../../drivers/staging/android/timed_output.h> + +#include <mach/gpio-herring.h> + +#define GPD0_TOUT_1 2 << 4 + +#define PWM_PERIOD (89284 / 2) +#define PWM_DUTY (87280 / 2) +#define MAX_TIMEOUT 10000 /* 10s */ + +static struct vibrator { + struct wake_lock wklock; + struct pwm_device *pwm_dev; + struct hrtimer timer; + struct mutex lock; + struct work_struct work; +} vibdata; + +static void herring_vibrator_off(void) +{ + pwm_disable(vibdata.pwm_dev); + gpio_direction_output(GPIO_VIBTONE_EN1, GPIO_LEVEL_LOW); + wake_unlock(&vibdata.wklock); +} + +static int herring_vibrator_get_time(struct timed_output_dev *dev) +{ + if (hrtimer_active(&vibdata.timer)) { + ktime_t r = hrtimer_get_remaining(&vibdata.timer); + return ktime_to_ms(r); + } + + return 0; +} + +static void herring_vibrator_enable(struct timed_output_dev *dev, int value) +{ + mutex_lock(&vibdata.lock); + + /* cancel previous timer and set GPIO according to value */ + hrtimer_cancel(&vibdata.timer); + cancel_work_sync(&vibdata.work); + if (value) { + wake_lock(&vibdata.wklock); + pwm_config(vibdata.pwm_dev, PWM_DUTY, PWM_PERIOD); + pwm_enable(vibdata.pwm_dev); + gpio_direction_output(GPIO_VIBTONE_EN1, GPIO_LEVEL_HIGH); + + if (value > 0) { + if (value > MAX_TIMEOUT) + value = MAX_TIMEOUT; + + hrtimer_start(&vibdata.timer, + ns_to_ktime((u64)value * NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + } else + herring_vibrator_off(); + + mutex_unlock(&vibdata.lock); +} + +static struct timed_output_dev to_dev = { + .name = "vibrator", + .get_time = herring_vibrator_get_time, + .enable = herring_vibrator_enable, +}; + +static enum hrtimer_restart herring_vibrator_timer_func(struct hrtimer *timer) +{ + schedule_work(&vibdata.work); + return HRTIMER_NORESTART; +} + +static void herring_vibrator_work(struct work_struct *work) +{ + herring_vibrator_off(); +} + +static int __init herring_init_vibrator(void) +{ + int ret = 0; + +#ifdef CONFIG_MACH_HERRING + if (!machine_is_herring()) + return 0; +#endif + hrtimer_init(&vibdata.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + vibdata.timer.function = herring_vibrator_timer_func; + INIT_WORK(&vibdata.work, herring_vibrator_work); + + ret = gpio_request(GPIO_VIBTONE_EN1, "vibrator-en"); + if (ret < 0) + return ret; + + s3c_gpio_cfgpin(GPIO_VIBTONE_PWM, GPD0_TOUT_1); + + vibdata.pwm_dev = pwm_request(1, "vibrator-pwm"); + if (IS_ERR(vibdata.pwm_dev)) { + ret = PTR_ERR(vibdata.pwm_dev); + goto err_pwm_req; + } + + wake_lock_init(&vibdata.wklock, WAKE_LOCK_SUSPEND, "vibrator"); + mutex_init(&vibdata.lock); + + ret = timed_output_dev_register(&to_dev); + if (ret < 0) + goto err_to_dev_reg; + + return 0; + +err_to_dev_reg: + mutex_destroy(&vibdata.lock); + wake_lock_destroy(&vibdata.wklock); + pwm_free(vibdata.pwm_dev); +err_pwm_req: + gpio_free(GPIO_VIBTONE_EN1); + return ret; +} + +device_initcall(herring_init_vibrator); diff --git a/arch/arm/mach-s5pv210/herring-watchdog.c b/arch/arm/mach-s5pv210/herring-watchdog.c new file mode 100644 index 0000000..7ff9fee --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-watchdog.c @@ -0,0 +1,111 @@ +/* herring-watchdog.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <plat/regs-watchdog.h> +#include <mach/map.h> + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/cpufreq.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/workqueue.h> +#include <linux/io.h> + +/* reset timeout in PCLK/256/128 (~2048:1s) */ +static unsigned watchdog_reset = (30 * 2048); + +/* pet timeout in jiffies */ +static unsigned watchdog_pet = (10 * HZ); + +static struct workqueue_struct *watchdog_wq; +static void watchdog_workfunc(struct work_struct *work); +static DECLARE_DELAYED_WORK(watchdog_work, watchdog_workfunc); + +static void watchdog_workfunc(struct work_struct *work) +{ + writel(watchdog_reset, S3C2410_WTCNT); + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_start(void) +{ + unsigned int val; + + /* set to PCLK / 256 / 128 */ + val = S3C2410_WTCON_DIV128; + val |= S3C2410_WTCON_PRESCALE(255); + writel(val, S3C2410_WTCON); + + /* program initial count */ + writel(watchdog_reset, S3C2410_WTCNT); + writel(watchdog_reset, S3C2410_WTDAT); + + /* start timer */ + val |= S3C2410_WTCON_RSTEN | S3C2410_WTCON_ENABLE; + writel(val, S3C2410_WTCON); + + /* make sure we're ready to pet the dog */ + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_stop(void) +{ + writel(0, S3C2410_WTCON); +} + +static int watchdog_probe(struct platform_device *pdev) +{ + watchdog_wq = alloc_workqueue("pet_watchdog", + WQ_UNBOUND | WQ_HIGHPRI, 1); + watchdog_start(); + return 0; +} + +static int watchdog_suspend(struct device *dev) +{ + watchdog_stop(); + return 0; +} + +static int watchdog_resume(struct device *dev) +{ + watchdog_start(); + return 0; +} + +static struct dev_pm_ops watchdog_pm_ops = { + .suspend_noirq = watchdog_suspend, + .resume_noirq = watchdog_resume, +}; + +static struct platform_driver watchdog_driver = { + .probe = watchdog_probe, + .driver = { + .owner = THIS_MODULE, + .name = "watchdog", + .pm = &watchdog_pm_ops, + }, +}; + +static int __init watchdog_init(void) +{ + return platform_driver_register(&watchdog_driver); +} + +module_init(watchdog_init); diff --git a/arch/arm/mach-s5pv210/herring.h b/arch/arm/mach-s5pv210/herring.h new file mode 100755 index 0000000..51fb43f --- /dev/null +++ b/arch/arm/mach-s5pv210/herring.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-s5pv210/herring.h + */ + +#include <asm/system.h> +#include <asm/mach-types.h> + +#ifndef __HERRING_H__ +#define __HERRING_H__ + +struct uart_port; + +void herring_bt_uart_wake_peer(struct uart_port *port); +extern void s3c_setup_uart_cfg_gpio(unsigned char port); + +#ifdef CONFIG_MACH_HERRING +# define herring_is_cdma_wimax_dev() (machine_is_herring() && \ + ((system_rev & 0xFFF0) == 0x20)) +# define herring_is_cdma_wimax_rev(n) (herring_is_cdma_wimax_dev() && \ + (system_rev & 0xF) == ((n) & 0xF)) +# define herring_is_cdma_wimax_rev0() herring_is_cdma_wimax_rev(0) +# define herring_is_tft_dev() (machine_is_herring() && (system_rev >= 0x30)) +#else +# define herring_is_cdma_wimax_dev() (0) +# define herring_is_cdma_wimax_rev0() (0) +# define herring_is_cdma_wimax_rev(n) (0) +# define herring_is_tft_dev() (0) +#endif + +#ifdef CONFIG_PHONE_ARIES_CDMA +# define phone_is_aries_cdma() (1) +#else +# define phone_is_aries_cdma() (0) +#endif + +extern struct s5p_panel_data herring_panel_data; +extern struct s5p_tft_panel_data herring_sony_panel_data; +extern struct s5p_tft_panel_data herring_hydis_panel_data; +extern struct s5p_tft_panel_data herring_hitachi_panel_data; +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/adc.h b/arch/arm/mach-s5pv210/include/mach/adc.h new file mode 100644 index 0000000..a0f703a --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/adc.h @@ -0,0 +1,36 @@ +/* arch/arm/plat-s3c/include/plat/adc.h + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simnte.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_ADC_H +#define __ASM_PLAT_ADC_H __FILE__ + +struct s3c_adc_request { + /* for linked list */ + struct list_head *list; + /* after finish ADC sampling, s3c_adc_request function call this function with three parameter */ + void (*callback)(int channel, unsigned long int param, unsigned short sample); + /* for private data */ + unsigned long int param; + /* selected channel for ADC sampling */ + int channel; +}; + +struct s3c_adc_mach_info { + /* if you need to use some platform data, add in here*/ + int delay; + int presc; + int resolution; +}; + +extern int s3c_adc_get_adc_data(int channel); +void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd); + +#endif /* __ASM_PLAT_ADC_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/battery.h b/arch/arm/mach-s5pv210/include/mach/battery.h new file mode 100644 index 0000000..b5f7339 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/battery.h @@ -0,0 +1,13 @@ +#ifndef __BATTERY_H_ +#define __BATTERY_H_ + +typedef enum +{ + PM_CHARGER_NULL, + PM_CHARGER_TA, + PM_CHARGER_USB_CABLE, //after enumeration + PM_CHARGER_USB_INSERT,// when usb is connected. + PM_CHARGER_DEFAULT +} charging_device_type; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h new file mode 100644 index 0000000..4d4469a --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h @@ -0,0 +1,54 @@ +/* arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * S5PV210/S5PC110 CPU frequency scaling support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_CPU_FREQ_H +#define __ASM_ARCH_CPU_FREQ_H + +#include <linux/cpufreq.h> + +enum perf_level { + OC0, L0, L1, L2, L3, L4, MAX_PERF_LEVEL = L4, +}; + +/* For cpu-freq driver */ +struct s5pv210_cpufreq_voltage { + unsigned int freq; /* kHz */ + unsigned long varm; /* uV */ + unsigned long vint; /* uV */ +}; + +struct s5pv210_cpufreq_data { + struct s5pv210_cpufreq_voltage *volt; + unsigned int size; +}; + +#ifdef CONFIG_DVFS_LIMIT +enum { + DVFS_LOCK_TOKEN_1 = 0, // MFC + DVFS_LOCK_TOKEN_2, // (FIMC) + DVFS_LOCK_TOKEN_3, // SND_RP + DVFS_LOCK_TOKEN_4, // (TV) + DVFS_LOCK_TOKEN_5, // (early suspend) + DVFS_LOCK_TOKEN_6, // APPS by sysfs + DVFS_LOCK_TOKEN_7, // (TOUCH) + DVFS_LOCK_TOKEN_8, // USB + DVFS_LOCK_TOKEN_9, // BT + DVFS_LOCK_TOKEN_PVR, + DVFS_LOCK_TOKEN_NUM +}; + +extern void s5pv210_lock_dvfs_high_level(uint nToken, uint perf_level); +extern void s5pv210_unlock_dvfs_high_level(unsigned int nToken); +#endif + +extern void s5pv210_cpufreq_set_platdata(struct s5pv210_cpufreq_data *pdata); + +#endif /* __ASM_ARCH_CPU_FREQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/cpuidle.h b/arch/arm/mach-s5pv210/include/mach/cpuidle.h new file mode 100644 index 0000000..7454ae4 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/cpuidle.h @@ -0,0 +1,16 @@ +/* arch/arm/mach-s5pv210/include/mach/cpuidle.h + * + * Copyright 2010 Samsung Electronics + * Jaecheol Lee <jc.lee@samsung> + * + * S5PV210 - CPUIDLE support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern int s5pv210_didle_save(unsigned long *saveblk); +extern void s5pv210_didle_resume(void); +extern void i2sdma_getpos(dma_addr_t *src); +extern unsigned int get_rtc_cnt(void); diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-aries.h b/arch/arm/mach-s5pv210/include/mach/gpio-aries.h new file mode 100644 index 0000000..c9ed133 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-aries.h @@ -0,0 +1,696 @@ +#ifndef __GPIO_HERRING_H_ +#define __GPIO_HERRING_H_ + +//#include <mach/gpio.h> + +#define S5PV210_GPE1_3_CAM_A_CLKOUT (0x2 << 12) + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 + +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 + +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 + +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 + +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 + +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 + +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 + +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 + +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 + +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 + +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) + +#define GPIO_MSENSE_nRST S5PV210_GPB(1) + +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_BT_nRST S5PV210_GPB(6) +#else +#define GPIO_BT_nRST S5PV210_GPB(3) +#endif + +#define GPIO_BOOT_MODE S5PV210_GPB(4) + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) + +#define GPIO_GPB6 S5PV210_GPB(6) + +#define GPIO_GPB7 S5PV210_GPB(7) + +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 + +#define GPIO_GPC01 S5PV210_GPC0(1) + +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 + +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 + +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 + +#define BLOW_PCM_CLK S5PV210_GPC1(0) + +#define GPIO_GPC11 S5PV210_GPC1(1) + +#define GPIO_GPC12 S5PV210_GPC1(2) + +#define GPIO_GPC13 S5PV210_GPC1(3) + +#define GPIO_GPC14 S5PV210_GPC1(4) + +#define GPIO_GPD00 S5PV210_GPD0(0) + +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) + +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) + +#define GPIO_GPD03 S5PV210_GPD0(3) + +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 + +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 + +#define GPIO_FM_SDA_28V S5PV210_GPD1(2) +#define GPIO_FM_SDA_28V_AF 2 + +#define GPIO_FM_SCL_28V S5PV210_GPD1(3) +#define GPIO_FM_SCL_28V_AF 2 + +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 + +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 + +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 + +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 + +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 + +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 + +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 + +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 + +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 + +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 + +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 + +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 + +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 + +#define GPIO_GPE14 S5PV210_GPE1(4) + +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF S3C_GPIO_SFN(2) + +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF S3C_GPIO_SFN(2) + +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF S3C_GPIO_SFN(2) + +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF S3C_GPIO_SFN(2) + +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF S3C_GPIO_SFN(2) + +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) + +#define GPIO_GPF35 S5PV210_GPF3(5) + +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 + +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#define GPIO_ALS_SCL_28V S5PV210_GPG0(2) + +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 + +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 + +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 + +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 + +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG1(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG1(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_nRST S5PV210_GPG1(2) +#define GPIO_WLAN_nRST_AF 1 + +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG1(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG1(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG1(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG1(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_T_FLASH_CLK S5PV210_GPG2(0) +#define GPIO_T_FLASH_CLK_AF 2 + +#define GPIO_T_FLASH_CMD S5PV210_GPG2(1) +#define GPIO_T_FLASH_CMD_AF 2 + +#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) + +#define GPIO_T_FLASH_D0 S5PV210_GPG2(3) +#define GPIO_T_FLASH_D0_AF 2 + +#define GPIO_T_FLASH_D1 S5PV210_GPG2(4) +#define GPIO_T_FLASH_D1_AF 2 + +#define GPIO_T_FLASH_D2 S5PV210_GPG2(5) +#define GPIO_T_FLASH_D2_AF 2 + +#define GPIO_T_FLASH_D3 S5PV210_GPG2(6) +#define GPIO_T_FLASH_D3_AF 2 + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_GPS_nRST S5PV210_GPG3(2) +#else +#define GPIO_GPS_nRST S5PV210_GPG3(0) +#endif + +#define GPIO_GPS_PWR_EN S5PV210_GPG3(1) + +#define GPIO_GPS_CLK_INT S5PV210_GPG3(2) + +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPG3(3) + +#define GPIO_BT_WAKE S5PV210_GPG3(4) + +#define GPIO_WLAN_WAKE S5PV210_GPG3(5) +#define GPIO_WLAN_WAKE_AF 1 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) + +#define GPIO_ACC_INT S5PV210_GPH0(1) + +#define GPIO_PS_VOUT S5PV210_GPH0(2) +#define GPIO_PS_VOUT_AF 0xFF + +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) + +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) + +#define GPIO_BUCK_2_EN S5PV210_GPH0(5) + +#define GPIO_DET_35 S5PV210_GPH0(6) +#define GPIO_DET_35_AF 0xFF + +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +#if defined(CONFIG_SAMSUNG_FASCINATE) +#define GPIO_PDA_ACTIVE S5PV210_GPH1(0) +#define GPIO_PDA_ACTIVE_AF 0x1 +#else +#define GPIO_GPH10 S5PV210_GPH1(0) +#endif + +#define GPIO_GPH11 S5PV210_GPH1(1) + +#define GPIO_GPH12 S5PV210_GPH1(2) + +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF + +#define GPIO_GPH14 S5PV210_GPH1(4) + +#define GPIO_GPH15 S5PV210_GPH1(5) + +#define GPIO_GPH16 S5PV210_GPH1(6) + +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) + +#if defined(CONFIG_SAMSUNG_FASCINATE) +#define GPIO_PHONE_ACTIVE_AF 0xFF +#else +#define GPIO_PHONE_ACTIVE_AF 2 +#endif + +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 + +#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_KBC1_AF 3 + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) +#define GPIO_EAR_SEND_END35 S5PV210_GPH2(2) +#define GPIO_EAR_SEND_END35_AF 0xFF +#else +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 +#endif + +#define GPIO_GPH23 S5PV210_GPH2(3) + +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF + +#define GPIO_nPOWER S5PV210_GPH2(6) + +#define GPIO_JACK_nINT S5PV210_GPH2(7) +#define GPIO_JACK_nINT_AF 0xF + +#define GPIO_KBR0 S5PV210_GPH3(0) +#define GPIO_KBR0_AF 3 + +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 + +#define GPIO_KBR2 S5PV210_GPH3(2) +#define GPIO_KBR2_AF 3 + +#define GPIO_KBR3 S5PV210_GPH3(3) +#define GPIO_KBR3_AF 3 +#if defined (CONFIG_SAMSUNG_CAPTIVATE) +#define S5PV210_GPH3_3_EXT_INT33_3 (0xf << 12) +#endif + +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) + +#define GPIO_MSENSE_IRQ S5PV210_GPH3(5) + +#define GPIO_EAR_SEND_END S5PV210_GPH3(6) +#define GPIO_EAR_SEND_END_AF 0xFF +#define GPIO_CP_RST S5PV210_GPH3(7) + +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 + +#define GPIO_GPI1 S5PV210_GPI(1) + +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 + +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 + +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 + +#define GPIO_GPI5 S5PV210_GPI(5) + +#define GPIO_GPI6 S5PV210_GPI(6) + +#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) +#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE0 S5PV210_GPG3(6) +#else +#define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE1 S5PV210_GPJ2(0) +#else +#define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE2 S5PV210_GPJ2(1) +#else +#define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_TOUCH_INT S5PV210_GPB(3) +#else +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(7) +#else +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_HWREV_MODE3 S5PV210_GPJ2(3) +#else +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) +#endif + +#define GPIO_PHONE_ON S5PV210_GPJ1(0) + +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) + +#define GPIO_GPJ30 S5PV210_GPJ1(2) + +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#define GPIO_PS_ON S5PV210_GPJ1(4) + +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) + +#define GPIO_CAM_FLASH_EN S5PV210_GPJ2(0) + +#define GPIO_CAM_FLASH_SET S5PV210_GPJ2(1) + +#define GPIO_OLED_DET S5PV210_GPJ2(2) + +#define GPIO_CODEC_XTAL_EN S5PV210_GPJ2(3) + +#define GPIO_FM_INT S5PV210_GPJ2(4) + +#if !defined(CONFIG_SAMSUNG_VIBRANT) +#define GPIO_FM_RST S5PV210_GPJ2(5) +#else +#define GPIO_MICBIAS_EN2 S5PV210_GPJ2(5) //SGH-T959 REV0.5(HWREV = 0x0e) or 0.6 (HWREV = 0x0f) +#endif + +#define GPIO_EARPATH_SEL S5PV210_GPJ2(6) + +#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) + +#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) +#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#define _3_GPIO_TOUCH_ST_AF 1 + +#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) + +#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) + +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) + +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) + +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) + +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF S3C_GPIO_SFN(0xf) + +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) + +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) +#define GPIO_EAR_MICBIAS_EN S5PV210_GPJ4(4) +#else +#define GPIO_TV_EN S5PV210_GPJ4(4) +#endif + +#define GPIO_MP010 S5PV210_MP01(0) + +#define GPIO_DISPLAY_CS S5PV210_MP01(1) +#define GPIO_DISPLAY_CS_AF S3C_GPIO_SFN(1) + +#define GPIO_SUB_DISPLAY_CS S5PV210_MP01(2) + +#define GPIO_OLED_ID S5PV210_MP01(3) + +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 + +#define GPIO_DIC_ID S5PV210_MP01(5) + +#define GPIO_MP016 S5PV210_MP01(6) + +#define GPIO_MP017 S5PV210_MP01(7) + +#define GPIO_MP020 S5PV210_MP02(0) + +#define GPIO_MP021 S5PV210_MP02(1) + +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) + +#define GPIO_MP023 S5PV210_MP02(3) + +#define GPIO_MP030 S5PV210_MP03(0) + +#define GPIO_MP031 S5PV210_MP03(1) + +#define GPIO_MP032 S5PV210_MP03(2) + +#if !defined(CONFIG_SAMSUNG_FASCINATE) +#define GPIO_PDA_ACTIVE S5PV210_MP03(3) +#endif + +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) + +#define GPIO_CP_nRST S5PV210_MP03(5) + +#define GPIO_MP036 S5PV210_MP03(6) + +#define GPIO_PCM_SEL S5PV210_MP03(7) + +#define GPIO_USB_SEL S5PV210_MP04(0) + +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) +#define GPIO_DISPLAY_CLK_AF S3C_GPIO_SFN(1) + +#define GPIO_MP042 S5PV210_MP04(2) + +#define GPIO_DISPLAY_SI S5PV210_MP04(3) +#define GPIO_DISPLAY_SI_AF S3C_GPIO_SFN(1) + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) +#define GPIO_A1026_SCL S5PV210_MP04(4) +#define GPIO_A1026_SCL_AF 2 +#else +#define GPIO_MP044 S5PV210_MP04(4) +#endif + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) +#define GPIO_A1026_SDA S5PV210_MP04(5) +#define GPIO_A1026_SDA_AF 2 +#else +#define GPIO_LVDS_RST S5PV210_MP04(5) +#endif + +#define GPIO_GPS_CLK_EN S5PV210_MP04(6) + +#define GPIO_MHL_RST S5PV210_MP04(7) + +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) + +#define GPIO_AP_SCL_18V S5PV210_MP05(2) + +#define GPIO_AP_SDA_18V S5PV210_MP05(3) + +#define GPIO_MP054 S5PV210_MP05(4) + +#define GPIO_MLCD_RST S5PV210_MP05(5) +#define GPIO_MLCD_RST_AF S3C_GPIO_SFN(1) + +#define GPIO_MP056 S5PV210_MP05(6) + +#define GPIO_UART_SEL S5PV210_MP05(7) + +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_TOUCH_INT S5PV210_GPB(3) +#else +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#endif +#define GPIO_TOUCH_INT_AF 0xFF + +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 + +/* uart 0~3 */ +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 + +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 + +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK +#define GPIO_BT_RST S5PV210_GPB(6) +#else +#define GPIO_BT_RST S5PV210_GPB(3) +#endif + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) +#define GPIO_WLAN_RST S5PV210_GPG1(2) + +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#endif +/* end of __GPIO_HERRING_H_ */ diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-herring.h b/arch/arm/mach-s5pv210/include/mach/gpio-herring.h new file mode 100644 index 0000000..b55d0f0 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-herring.h @@ -0,0 +1,603 @@ +#ifndef __GPIO_HERRING_H_ +#define __GPIO_HERRING_H_ + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 + +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 + +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 + +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 + +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 + +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 + +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 + +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 + +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 + +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 + +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) + +#define GPIO_MSENSE_nRST S5PV210_GPB(1) + +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) + +#define GPIO_BT_nRST S5PV210_GPB(3) + +#define GPIO_BOOT_MODE S5PV210_GPB(4) + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) + +#define GPIO_GPB6 S5PV210_GPB(6) + +#define GPIO_GPB7 S5PV210_GPB(7) + +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 + +#define GPIO_GPC01 S5PV210_GPC0(1) + +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 + +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 + +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 + +#define GPIO_WIMAX_PM_SDA S5PV210_GPC1(0) + +#define GPIO_WIMAX_I2C_CON S5PV210_GPC1(1) + +#define GPIO_WIMAX_PM_SCL S5PV210_GPC1(2) + +#define GPIO_GPC13 S5PV210_GPC1(3) + +#define GPIO_GPC14 S5PV210_GPC1(4) + +#define GPIO_WIMAX_DBGEN_28V S5PV210_GPD0(0) + +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) + +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) + +#define GPIO_WIMAX_RESET_N S5PV210_GPD0(3) + +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 + +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 + +#define GYRO_SDA_28V S5PV210_GPD1(2) +#define GYRO_SCL_28V S5PV210_GPD1(3) + +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 + +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 + +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 + +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 + +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 + +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 + +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 + +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 + +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 + +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 + +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 + +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 + +#define GPIO_GPE14 S5PV210_GPE1(4) + +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF 2 + +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF 2 + +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF 2 + +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF 2 + +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF 2 + +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF 2 + +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF 2 + +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF 2 + +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF 2 + +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF 2 + +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF 2 + +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF 2 + +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF 2 + +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF 2 + +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF 2 + +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF 2 + +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF 2 + +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF 2 + +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF 2 + +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF 2 + +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF 2 + +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF 2 + +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF 2 + +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF 2 + +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF 2 + +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF 2 + +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF 2 + +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF 2 + +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) + +#define GPIO_GPF35 S5PV210_GPF3(5) + +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 + +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#define GPIO_ALS_SCL_28V S5PV210_GPG0(2) + +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 + +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 + +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 + +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 + +#define GPIO_GPS_nRST S5PV210_GPG1(0) + +#define GPIO_GPS_PWR_EN S5PV210_GPG1(1) + +#define GPIO_WLAN_RST S5PV210_GPG1(2) + +#define GPIO_NAND_D4 S5PV210_GPG1(3) +#define GPIO_NAND_D4_AF 3 + +#define GPIO_NAND_D5 S5PV210_GPG1(4) +#define GPIO_NAND_D5_AF 3 + +#define GPIO_NAND_D6 S5PV210_GPG1(5) +#define GPIO_NAND_D6_AF 3 + +#define GPIO_NAND_D7 S5PV210_GPG1(6) +#define GPIO_NAND_D7_AF 3 + +#define GPIO_WIMAX_SDIO_CLK S5PV210_GPG2(0) + +#define GPIO_WIMAX_SDIO_CMD S5PV210_GPG2(1) + +#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) + +#define GPIO_WIMAX_SDIO_D0 S5PV210_GPG2(3) + +#define GPIO_WIMAX_SDIO_D1 S5PV210_GPG2(4) + +#define GPIO_WIMAX_SDIO_D2 S5PV210_GPG2(5) + +#define GPIO_WIMAX_SDIO_D3 S5PV210_GPG2(6) + +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_nRST S5PV210_GPG3(2) +#define GPIO_WLAN_nRST_AF 1 + +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) + +#define GPIO_ACC_INT S5PV210_GPH0(1) + +#define GPIO_PS_VOUT S5PV210_GPH0(2) +#define GPIO_PS_VOUT_AF 0xFF + +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) + +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) + +#define GPIO_BUCK_2_EN S5PV210_GPH0(5) +#define GPIO_DET_35 S5PV210_GPH0(6) +#define GPIO_DET_35_AF 0xFF + +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +#define GPIO_WIMAX_EN S5PV210_GPH1(0) + +#define GPIO_PDA_ACTIVE S5PV210_GPH1(1) + +#define GPIO_WIMAX_WAKEUP S5PV210_GPH1(2) + +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF + +#define GPIO_GPH14 S5PV210_GPH1(4) + +#define GPIO_GPH15 S5PV210_GPH1(5) + +#define GPIO_GPH16 S5PV210_GPH1(6) + +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) +#define GPIO_PHONE_ACTIVE_AF 2 + +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 +#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_KBC1_AF 3 +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 + +#define GPIO_BT_WAKE S5PV210_GPH2(2) +#define GPIO_WLAN_WAKE S5PV210_GPH2(3) +#define GPIO_WLAN_WAKE_AF 1 + +#define GPIO_KBC_DATA (GPIO_KBC2 + 0x04) + +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF + +#define GPIO_nPOWER S5PV210_GPH2(6) + +#define GPIO_JACK_nINT S5PV210_GPH2(7) + +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPH3(0) + +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 + +#define GPIO_KBR2 S5PV210_GPH3(2) +#define GPIO_KBR2_AF 3 + +#define GPIO_MSENSE_IRQ S5PV210_GPH3(3) + +#define GPIO_KBR_DATA (GPIO_KBR1 + 0x04) + +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) + +/* EAR_SEN_END_OPEN */ +#define GPIO_OK_KEY S5PV210_GPH3(5) + +#define GPIO_EAR_SEND_END S5PV210_GPH3(6) +#define GPIO_EAR_SEND_END_AF 0xFF +#define GPIO_CP_RST S5PV210_GPH3(7) + +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 + +#define GPIO_GPI1 S5PV210_GPI(1) + +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 + +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 + +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 + +#define GPIO_GPI5 S5PV210_GPI(5) + +#define GPIO_GPI6 S5PV210_GPI(6) + +#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) +#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) + +#define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) +#define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) +#define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) + +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) + +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) + +#define GPIO_CAM_FLASH_EN_SET S5PV210_GPJ1(0) + +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) + +#define GPIO_USB_HS_SEL S5PV210_GPJ2(0) +#define GPIO_PHONE_ON S5PV210_GPJ2(1) + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_UART_SEL1 S5PV210_GPJ2(4) + +#define GPIO_FLASH_EN S5PV210_GPJ1(2) +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#define GPIO_PS_ON S5PV210_GPJ1(4) + +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) + +#define GPIO_OLED_DET S5PV210_GPJ2(2) + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_FM_INT S5PV210_GPJ2(4) +#define GPIO_FM_RST S5PV210_GPJ2(5) +#define GPIO_TV_OUT_SEL S5PV210_GPJ2(6) + +#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) + +#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) +#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 +#define GPIO_EAR_ADC_SEL S5PV210_GPJ3(3) +#define GPIO_EAR_ADC_SEL_AF 1 + +#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) + +#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) + +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) + +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) + +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF 0xFF +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) + +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) + +#define GPIO_EAR_MICBIAS_EN S5PV210_GPJ4(4) + +#define GPIO_MP010 S5PV210_MP01(0) + +#define GPIO_DISPLAY_CS S5PV210_MP01(1) + +#define GPIO_WIMAX_CON0 S5PV210_MP01(2) + +#define GPIO_OLED_ID S5PV210_MP01(3) + +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 + +#define GPIO_DIC_ID S5PV210_MP01(5) + +#define GPIO_MP016 S5PV210_MP01(6) + +#define GPIO_MP017 S5PV210_MP01(7) + +#define GPIO_MP020 S5PV210_MP02(0) + +#define GPIO_MP021 S5PV210_MP02(1) + +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) + +#define GPIO_MP023 S5PV210_MP02(3) + +#define GPIO_MP030 S5PV210_MP03(0) + +#define GPIO_MP031 S5PV210_MP03(1) + +#define GPIO_MP032 S5PV210_MP03(2) + +#define GPIO_MP033 S5PV210_MP03(3) + +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) + +#define GPIO_CP_nRST S5PV210_MP03(5) + +#define GPIO_MP036 S5PV210_MP03(6) + +#define GPIO_PCM_SEL S5PV210_MP03(7) + +#define GPIO_USB_SEL S5PV210_MP04(0) + +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) + +#define GPIO_WIMAX_IF_MODE0 S5PV210_MP04(2) + +#define GPIO_DISPLAY_SI S5PV210_MP04(3) + +#define GPIO_MP044 S5PV210_MP04(4) + +#define GPIO_LVDS_RST S5PV210_MP04(5) + +#define GPIO_GPS_CLK_EN S5PV210_MP04(6) + +#define GPIO_WIMAX_CON1 S5PV210_MP04(7) + +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) + +#define GPIO_AP_SCL_18V S5PV210_MP05(2) + +#define GPIO_AP_SDA_18V S5PV210_MP05(3) + +#define GPIO_WIMAX_IF_MODE1 S5PV210_MP05(4) + +#define GPIO_MLCD_RST S5PV210_MP05(5) + +#define GPIO_WIMAX_CON2 S5PV210_MP05(6) + +#define GPIO_UART_SEL S5PV210_MP05(7) + +#define GPOI_WIMAX_WAKEUP S5PV210_MP06(5) + +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +#define NFC_SCL_18V S5PV210_MP04(4) +#define NFC_SDA_18V S5PV210_MP04(5) +#define NFC_IRQ S5PV210_GPH1(4) +#define NFC_EN S5PV210_GPH1(5) +#define NFC_FIRM S5PV210_GPH1(6) + +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#define GPIO_TOUCH_INT_AF 0xFF + +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 + +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 + +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 + +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#endif +/* end of __GPIO_HERRING_H_ */ + diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-p1.h b/arch/arm/mach-s5pv210/include/mach/gpio-p1.h new file mode 100644 index 0000000..f36cfc7 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-p1.h @@ -0,0 +1,633 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/gpio-p1.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef __GPIO_P1_H_ +#define __GPIO_P1_H_ + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 + +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 + +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 + +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 + +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 + +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 + +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 + +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 + +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 + +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 + +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) + +#define GPIO_MSENSE_nRST S5PV210_GPB(1) + +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) + +#define GPIO_BT_nRST S5PV210_GPB(3) + +#define GPIO_BOOT_MODE S5PV210_GPB(4) + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) + +#define GPIO_GPB6 S5PV210_GPB(6) + +#define GPIO_GPB7 S5PV210_GPB(7) + +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 + +#define GPIO_GPC01 S5PV210_GPC0(1) + +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 + +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 + +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 + +#define BLOW_PCM_CLK S5PV210_GPC1(0) + +#define GPIO_GPC11 S5PV210_GPC1(1) + +#define GPIO_GPC12 S5PV210_GPC1(2) + +#define GPIO_GPC13 S5PV210_GPC1(3) + +#define GPIO_GPC14 S5PV210_GPC1(4) + +// CMC623 +#define GPIO_CMC_SLEEP S5PV210_GPC1(0) +#define GPIO_CMC_SLEEP_AF 2 +#define GPIO_CMC_EN S5PV210_GPC1(1) +#define GPIO_CMC_EN_AF 2 +#define GPIO_CMC_RST S5PV210_GPC1(2) +#define GPIO_CMC_RST_AF 2 +#define GPIO_CMC_SHDN S5PV210_GPC1(3) +#define GPIO_CMC_SHDN_AF 2 +#define GPIO_CMC_BYPASS S5PV210_GPC1(4) +#define GPIO_CMC_BYPASS_AF 2 + +#define GPIO_GPD00 S5PV210_GPD0(0) + +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) + +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) + +#define GPIO_GPD03 S5PV210_GPD0(3) + +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 + +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 + +#define GYRO_SDA_28V S5PV210_GPD1(2) +#define GYRO_SCL_28V S5PV210_GPD1(3) + +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 + +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 + +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 + +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 + +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 + +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 + +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 + +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 + +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 + +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 + +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 + +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 + +#define GPIO_GPE14 S5PV210_GPE1(4) + +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF 2 + +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF 2 + +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF 2 + +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF 2 + +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF 2 + +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF 2 + +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF 2 + +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF 2 + +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF 2 + +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF 2 + +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF 2 + +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF 2 + +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF 2 + +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF 2 + +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF 2 + +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF 2 + +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF 2 + +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF 2 + +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF 2 + +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF 2 + +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF 2 + +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF 2 + +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF 2 + +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF 2 + +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF 2 + +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF 2 + +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF 2 + +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF 2 + +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) + +#define GPIO_GPF35 S5PV210_GPF3(5) + +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 + +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#define GPIO_ALS_SCL_28V S5PV210_GPG0(2) + +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 + +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 + +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 + +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 + +#define GPIO_GPS_nRST S5PV210_GPG1(0) + +#define GPIO_GPS_PWR_EN S5PV210_GPG1(1) + +#define GPIO_WLAN_RST S5PV210_GPG1(2) + +#define GPIO_NAND_D4 S5PV210_GPG1(3) +#define GPIO_NAND_D4_AF 3 + +#define GPIO_NAND_D5 S5PV210_GPG1(4) +#define GPIO_NAND_D5_AF 3 + +#define GPIO_NAND_D6 S5PV210_GPG1(5) +#define GPIO_NAND_D6_AF 3 + +#define GPIO_NAND_D7 S5PV210_GPG1(6) +#define GPIO_NAND_D7_AF 3 + +#define GPIO_T_FLASH_CLK S5PV210_GPG2(0) +#define GPIO_T_FLASH_CLK_AF 2 + +#define GPIO_T_FLASH_CMD S5PV210_GPG2(1) +#define GPIO_T_FLASH_CMD_AF 2 + +#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) + +#define GPIO_T_FLASH_D0 S5PV210_GPG2(3) +#define GPIO_T_FLASH_D0_AF 2 + +#define GPIO_T_FLASH_D1 S5PV210_GPG2(4) +#define GPIO_T_FLASH_D1_AF 2 + +#define GPIO_T_FLASH_D2 S5PV210_GPG2(5) +#define GPIO_T_FLASH_D2_AF 2 + +#define GPIO_T_FLASH_D3 S5PV210_GPG2(6) +#define GPIO_T_FLASH_D3_AF 2 + +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_nRST S5PV210_GPG3(2) +#define GPIO_WLAN_nRST_AF 1 + +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) + +#define GPIO_ACC_INT S5PV210_GPH0(1) + +#define GPIO_PS_VOUT S5PV210_GPH0(2) +#define GPIO_PS_VOUT_AF 0xFF + +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) + +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) + +#define GPIO_BUCK_2_EN S5PV210_GPH0(5) + +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +#define GPIO_GPH10 S5PV210_GPH1(0) +#define GPIO_DET_35 S5PV210_GPH1(0) +#define GPIO_DET_35_AF 0xF + +#define GPIO_PDA_ACTIVE S5PV210_GPH1(1) + +#define GPIO_GPH12 S5PV210_GPH1(2) +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF + +#define GPIO_GPH14 S5PV210_GPH1(4) +#define GPIO_EAR_SEND_END S5PV210_GPH1(4) +#define GPIO_EAR_SEND_END_AF 0xF + +#define GPIO_GPH15 S5PV210_GPH1(5) + +#define GPIO_GPH16 S5PV210_GPH1(6) + +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) +#define GPIO_PHONE_ACTIVE_AF 2 + +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 +#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_KBC1_AF 3 +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 + +#define GPIO_BT_WAKE S5PV210_GPH2(2) +#define GPIO_WLAN_WAKE S5PV210_GPH2(3) +#define GPIO_WLAN_WAKE_AF 1 + +#define GPIO_KBC_DATA (GPIO_KBC2 + 0x04) + +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF + +#define GPIO_nPOWER S5PV210_GPH2(6) + +#define GPIO_JACK_nINT S5PV210_GPH2(7) + +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPH3(0) + +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 + +#define GPIO_MSENSE_IRQ S5PV210_GPH3(2) + +#define GPIO_SIM_nDETECT S5PV210_GPH3(3) + +#define GPIO_KBR_DATA (GPIO_KBR1 + 0x04) + +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) +#define GPIO_T_FLASH_DETECT_AF 0xF + +/* EAR_SEN_END_OPEN */ +#define GPIO_OK_KEY S5PV210_GPH3(5) + +#define GPIO_CP_RST S5PV210_GPH3(7) + +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 + +#define GPIO_GPI1 S5PV210_GPI(1) + +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 + +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 + +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 + +#define GPIO_GPI5 S5PV210_GPI(5) + +#define GPIO_GPI6 S5PV210_GPI(6) + +#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) +#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) + +#define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) +#define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) +#define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) + +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) + +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) + +#define GPIO_CAM_FLASH_EN_SET S5PV210_GPJ1(0) + +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) +#define GPIO_MASSMEMORY_EN S5PV210_GPJ1(1) // Rev0.6 + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) + +#define GPIO_FLASH_EN S5PV210_GPJ1(2) +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#define GPIO_PS_ON S5PV210_GPJ1(4) + +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) + +#define GPIO_OLED_DET S5PV210_GPJ2(2) +#define GPIO_USB_SW_SCL S5PV210_GPJ2(3) + +//#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_FM_INT S5PV210_GPJ2(4) +#define GPIO_FM_RST S5PV210_GPJ2(5) +#define GPIO_LCD_LDO_EN S5PV210_GPJ2(6) + +//#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) +#define GPIO_USB_SW_SDA S5PV210_GPJ2(7) + +#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) +#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 +#define GPIO_EAR_ADC_SEL S5PV210_GPJ3(3) +#define GPIO_EAR_ADC_SEL_AF 1 + +#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) + +#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) + +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) + +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) + +#define GPIO_MASSMEMORY_EN2_REV06 S5PV210_GPJ4(1) // Rev0.6 + +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF 0xFF +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) + +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) + +#define GPIO_MP010 S5PV210_MP01(0) + +#define GPIO_DISPLAY_CS S5PV210_MP01(1) + +#define GPIO_RESET_REQ_N S5PV210_MP01(2) + +#define GPIO_OLED_ID S5PV210_MP01(3) + +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 + +#define GPIO_DIC_ID S5PV210_MP01(5) + +#define GPIO_EAR_MICBIAS_EN S5PV210_MP01(5) + +#define GPIO_MP016 S5PV210_MP01(6) + +#define GPIO_MP017 S5PV210_MP01(7) + +#define GPIO_MP020 S5PV210_MP02(0) + +#define GPIO_MP021 S5PV210_MP02(1) + +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) + +#define GPIO_MP023 S5PV210_MP02(3) + +#define GPIO_MP030 S5PV210_MP03(0) + +#define GPIO_MP031 S5PV210_MP03(1) + +#define GPIO_MP032 S5PV210_MP03(2) + +#define GPIO_MP033 S5PV210_MP03(3) + +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) + +#define GPIO_CP_nRST S5PV210_MP03(5) + +#define GPIO_MP036 S5PV210_MP03(6) + +#define GPIO_PCM_SEL S5PV210_MP03(7) + +#define GPIO_USB_SEL S5PV210_MP04(0) + +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) + +#define GPIO_MP042 S5PV210_MP04(2) + +#define GPIO_DISPLAY_SI S5PV210_MP04(3) + +#define GPIO_MP044 S5PV210_MP04(4) + +#define GPIO_CMC_SDA_18V S5PV210_MP04(5) // Rev0.9 +#define GPIO_LVDS_RST S5PV210_MP04(5) + +#define GPIO_GPS_CLK_EN S5PV210_MP04(6) +#define GPIO_CMC_SCL_18V S5PV210_MP04(6) // Rev1.2 + +#define GPIO_MHL_RST S5PV210_MP04(7) + +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) + +#define GPIO_EAR_MICBIAS0_EN S5PV210_MP05(1) + +#define GPIO_AP_SCL_18V S5PV210_MP05(2) + +#define GPIO_AP_SDA_18V S5PV210_MP05(3) + +#define GPIO_MP054 S5PV210_MP05(4) +#define GPIO_LVDS_SHDN S5PV210_MP05(4) + +#define GPIO_MLCD_RST S5PV210_MP05(5) + +#define GPIO_MP056 S5PV210_MP05(6) + +#define GPIO_UART_SEL S5PV210_MP05(7) + +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +#define NFC_SCL_18V S5PV210_MP04(4) +#define NFC_SDA_18V S5PV210_MP04(5) +#define NFC_IRQ S5PV210_GPH1(4) +#define NFC_EN S5PV210_GPH1(5) +#define NFC_FIRM S5PV210_GPH1(6) + +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#define GPIO_TOUCH_INT_AF 0xFF + +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 + +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 + +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 + +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#endif +/* end of __GPIO_P1_H_ */ + diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-settings.h b/arch/arm/mach-s5pv210/include/mach/gpio-settings.h new file mode 100644 index 0000000..e8f8fee --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-settings.h @@ -0,0 +1,898 @@ +#ifndef __GPIO_SETTINGS_H_ +#define __GPIO_SETTINGS_H_ + +#define S3C_GPIO_SETPIN_ZERO 0 +#define S3C_GPIO_SETPIN_ONE 1 +#define S3C_GPIO_SETPIN_NONE 2 + +#define S3C_GPIO_EINT S3C_GPIO_SPECIAL(0xF) + +// GPIO Initialization table +// {pin number, pin conf, pin value, pullup/down config} +static unsigned int initial_gpio_table[][4] = +{ + // GPA0 -------------------------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) // Modify NTT S1 + {S5PV210_GPA0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + // GPA1 -------------------------------------------------------------------- + + // GPA1 -------------------------------------------------------------------- + + // GPB --------------------------------------------------------------------- + {S5PV210_GPB(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPB(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPB(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPB(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPB(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPB(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPB(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPC0 -------------------------------------------------------------------- + {S5PV210_GPC0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPC1 -------------------------------------------------------------------- + {S5PV210_GPC1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPD0 -------------------------------------------------------------------- + {S5PV210_GPD0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD0(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPD1 -------------------------------------------------------------------- + {S5PV210_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + // GPE0 -------------------------------------------------------------------- + {S5PV210_GPE0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPE1 -------------------------------------------------------------------- + {S5PV210_GPE1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPE1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPE1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPE1(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPE1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPF0 -------------------------------------------------------------------- + + // GPF1 -------------------------------------------------------------------- + + // GPF2 -------------------------------------------------------------------- + + // GPF3 -------------------------------------------------------------------- + {S5PV210_GPF3(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG0 -------------------------------------------------------------------- + {S5PV210_GPG0(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG1 -------------------------------------------------------------------- + {S5PV210_GPG1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG2 -------------------------------------------------------------------- + {S5PV210_GPG2(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPG3 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPG3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPG3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPH0 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH0(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH0(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH0(7), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + + // GPH1 -------------------------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPH1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH1(7), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + + // GPH2 -------------------------------------------------------------------- + {S5PV210_GPH2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH2(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, +#else + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH2(5), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH2(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + + // GPH3 -------------------------------------------------------------------- + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPH3(1), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPH3(2), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(3), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH3(5), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH3(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + + // GPI --------------------------------------------------------------------- + {S5PV210_GPI(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // GPJ0 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(5), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#else + {S5PV210_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPJ0(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + // GPJ1 -------------------------------------------------------------------- + {S5PV210_GPJ1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ1(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPJ2 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPJ2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, +#endif +#if defined(CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPJ2(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ2(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ2(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + + // GPJ3 -------------------------------------------------------------------- + {S5PV210_GPJ3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPJ3(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + // GPJ4 -------------------------------------------------------------------- + {S5PV210_GPJ4(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(1), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ4(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#else + {S5PV210_GPJ4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + + // MP01 -------------------------------------------------------------------- + {S5PV210_MP01(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP01(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP02 -------------------------------------------------------------------- + {S5PV210_MP02(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP02(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP02(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP03 -------------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_MP03(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_MP03(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_ARIES_NTT) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_MP03(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_MP03(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP03(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP04 -------------------------------------------------------------------- + {S5PV210_MP04(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_MP04(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_MP04(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP04(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + + // MP05 -------------------------------------------------------------------- + {S5PV210_MP05(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP05(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +}; + +// off part GPIO Sleep Control table +// {pin number, sleep mode conf, sleep pullup/down config} +static unsigned int sleep_gpio_table[][3] = +{ + // GPA0 ------------------------------------------------- + {S5PV210_GPA0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_RXD + {S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_TXD + {S5PV210_GPA0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_CTS + {S5PV210_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_RTS +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA04 + {S5PV210_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA05 + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA06 + {S5PV210_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPA07 +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPA0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + {S5PV210_GPA0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + + // GPA1 ------------------------------------------------- + {S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_AP_RXD + {S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_AP_TXD +#if defined(CONFIG_ARIES_NTT) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_AP_FLM_RXD +#else + {S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_FLM_RXD +#endif + {S5PV210_GPA1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_AP_FLM_TXD + + // GPB ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) || defined (CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VGA_nSTBY + {S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MSENSE_nRST + {S5PV210_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VGA_nRST +#else + {S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_nRST + {S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_BOOT_MODE + {S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_BT_EN + {S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPB6 + {S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPB7 (CAM_IO_EN) + + // GPC0 ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC00 + {S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC01 + {S5PV210_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC02 + {S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC03 + {S5PV210_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC04 +#else + {S5PV210_GPC0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else + {S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPC1 ------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPC1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPC10 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC10 +#endif + {S5PV210_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC11 +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPC1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPC12 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC12 +#endif + {S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC13 + {S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC14 + + // GPD0 ------------------------------------------------- + {S5PV210_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD00 + {S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_VIBTONE_PWM + {S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD02 + {S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD03 + + // GPD1 ------------------------------------------------- + {S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_SDA_29V + {S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_SCL_29V +#if defined(CONFIG_ARIES_NTT) || defined (CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD12 + {S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD13 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_TSP_SDA_28V + {S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_TSP_SCL_28V + + // GPE0 ------------------------------------------------- + {S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_PCLK + {S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VSYNC + {S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_HSYNC + {S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D0 + {S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D1 + {S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D2 + {S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D3 + {S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D4 + + // GPE1 ------------------------------------------------- + {S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D5 + {S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D6 + {S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_D7 + {S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_CAM_MCLK + {S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPE14 + + // GPF0 ------------------------------------------------- + {S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_HSYNC + {S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_VSYNC + {S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_DE + {S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_PCLK + {S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D0 + {S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D1 + {S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D2 + {S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D3 + + // GPF1 ------------------------------------------------- + {S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D4 + {S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D5 + {S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D6 + {S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D7 + {S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D8 + {S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D9 + {S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D10 + {S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D11 + + // GPF2 ------------------------------------------------- + {S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D12 + {S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D13 + {S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D14 + {S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D15 + {S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D16 + {S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D17 + {S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D18 + {S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D19 + + // GPF3 ------------------------------------------------- + {S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D20 + {S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D21 + {S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D22 + {S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_LCD_D23 + {S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_LDO_EN + {S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPF35 + + // GPG0 ------------------------------------------------- + {S5PV210_GPG0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_CLK +#if defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_CMD +#else + {S5PV210_GPG0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_CMD +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // GPIO_ALS_SCL_28V +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, // GPIO_ALS_SCL_28V +#endif +#if defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D0 + {S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D1 + {S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D2 + {S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D3 +#else + {S5PV210_GPG0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D0 + {S5PV210_GPG0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D1 + {S5PV210_GPG0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D2 + {S5PV210_GPG0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_NAND_D3 +#endif + + // GPG1 ------------------------------------------------- + {S5PV210_GPG1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_CLK + {S5PV210_GPG1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_CMD + {S5PV210_GPG1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_nRST + {S5PV210_GPG1(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D0 + {S5PV210_GPG1(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D1 + {S5PV210_GPG1(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D2 + {S5PV210_GPG1(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D3 + + // GPG2 ------------------------------------------------- + {S5PV210_GPG2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CLK +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG2(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CMD +#else + {S5PV210_GPG2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CMD +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_ALS_SDA_28V +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_ALS_SDA_28V +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPG2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D0 + {S5PV210_GPG2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D1 + {S5PV210_GPG2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D2 + {S5PV210_GPG2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D3 +#else + {S5PV210_GPG2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D0 + {S5PV210_GPG2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D1 + {S5PV210_GPG2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D2 + {S5PV210_GPG2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D3 +#endif + + // GPG3 ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPG3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPG30 + {S5PV210_GPG3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPG31 +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPG3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + {S5PV210_GPG3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, +#else //CONFIG_SAMSUNG_CAPTIVATE CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPG3(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPG3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_TA_CURRENT_SEL_AP +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, //GPIO_TA_CURRENT_SEL_AP +#endif + {S5PV210_GPG3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_BT_WAKE + {S5PV210_GPG3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_WAKE +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPG3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPG36 +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPG36 +#else //CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPG36 +#endif + + // GPI -------------------------------------------------- +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPI(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I2S_CLK +#else + {S5PV210_GPI(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I2S_CLK +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI1 +#else //CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI1 +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPI(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I2S_WS + {S5PV210_GPI(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I3S_DI + {S5PV210_GPI(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, //GPIO_CODEC_I3S_DO +#else + {S5PV210_GPI(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I2S_WS + {S5PV210_GPI(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I3S_DI + {S5PV210_GPI(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I3S_DO +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI5 + {S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI6 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI5 + {S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI6 +#endif + + // GPJ0 ------------------------------------------------- + {S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MSENSE_SCL_28V + {S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MSENSE_SDA_28V + {S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE0 + {S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE1 + {S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE2 + {S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_TOUCH_INT + {S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_CAM_MEGA_EN + {S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_HWREV_MODE3 + + // GPJ1 ------------------------------------------------- +#if defined(CONFIG_ARIES_NTT) || defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_PHONE_ON +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_VIBTONE_EN1 + {S5PV210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ12 + {S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_TOUCH_EN +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPJ1(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_PS_ON +#else + {S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_CAM_MEGA_nRST + + // GPJ2 ------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ20 + {S5PV210_GPJ2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ21 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ20 + {S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ21 +#endif + {S5PV210_GPJ2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_OLED_DET +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_USIM_BOOT + {S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, //NC + {S5PV210_GPJ2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //NC + {S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //NC + {S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_SUB_MICBIAS_EN +#else //CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + {S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPJ2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_EARPATH_SEL + {S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MASSMEMORY_EN +#else + {S5PV210_GPJ2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_EARPATH_SEL + {S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_MASSMEMORY_EN +#endif + + // GPJ3 ------------------------------------------------- + {S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_TOUCH_SDA_28V + {S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_TOUCH_SCL_28V + {S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //_3_GPIO_TOUCH_EN +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ33 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPJ3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ33 +#endif + {S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_USB_SDA_28V + {S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_USB_SCL_28V + {S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SDA_28V + {S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SCL_28V + + // GPJ4 ------------------------------------------------- + {S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_PMIC_SDA + {S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_GPIO_TOUCH_INT + {S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_MICBIAS_EN + {S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_PMIC_SCL +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_EARMICBIAS_EN +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_GPJ4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ44 +#endif + + // MP01 ------------------------------------------------- + {S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP010 + {S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_CS + {S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP012 + {S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_OLED_ID + {S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_AP_NANDCS + {S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_DIC_ID + {S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP016 + {S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP017 + + // MP02 ------------------------------------------------- + {S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP020 + {S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP021 + {S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP022 + {S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP023 + + // MP03 ------------------------------------------------- + {S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP030 + {S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP031 +#if defined (CONFIG_SAMSUNG_VIBRANT) + {S5PV210_MP03(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //NC +#else //CONFIG_SAMSUNG_CAPTIVATE CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MP032 +#endif + {S5PV210_MP03(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_PDA_ACTIVE + {S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP04 +#if defined(CONFIG_ARIES_NTT) + {S5PV210_MP03(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP035 +#else + {S5PV210_MP03(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP036 + {S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP037 + + // MP04 ------------------------------------------------- + {S5PV210_MP04(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP040 + {S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_CLK + {S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP042 + {S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_DISPLAY_SI +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP044 + {S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP045 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS CONFIG_SAMSUNG_FASCINATE + {S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP044 + {S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP045 +#endif +#if defined(CONFIG_ARIES_NTT) + {S5PV210_MP04(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP046 +#else + {S5PV210_MP04(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP04(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP047 + + // MP05 ------------------------------------------------- + {S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //FUEL_SCL_18V + {S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //FUEL_SDA_18V + {S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SCL_18V + {S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SDA_18V + {S5PV210_MP05(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP054 + {S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_MLCD_RST + {S5PV210_MP05(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP056 + {S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_UART_SEL + + // MP06 ------------------------------------------------- + {S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // MP07 ------------------------------------------------- + {S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +}; + + + +// alive part GPIO Sleep Control table +// {pin number, sleep mode conf, sleep pin value, sleep pullup/down config} +static unsigned int sleep_alive_gpio_table[][4] = +{ +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN},//GPIO_ACC_INT +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //pwr hold + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPH0(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_BUCK_1_EN_A + {S5PV210_GPH0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_BUCK_1_EN_B + {S5PV210_GPH0(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_BUCK_2_EN + +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_AP_PMIC_IRQ + {S5PV210_GPH1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_AP_PMIC_IRQ //cross check + {S5PV210_GPH1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_DOWN}, +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPH1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH11 + {S5PV210_GPH1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH11 + +#if defined (CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH1(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_GPH14 +#else + {S5PV210_GPH1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH14 +#endif + {S5PV210_GPH1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH15 + {S5PV210_GPH1(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH16 +#if defined(CONFIG_ARIES_NTT) || defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH17 +#else + {S5PV210_GPH1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, +#endif + + {S5PV210_GPH2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_GPH20 + {S5PV210_GPH2(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE}, //GPIO_KBC1 + {S5PV210_GPH2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_KBC2 +#if defined(CONFIG_ARIES_NTT) + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE}, //GPIO_PHONE_ACTIVE +#else + {S5PV210_GPH2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_nPOWER + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR0 + {S5PV210_GPH3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR1 + {S5PV210_GPH3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR2 +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH2(6), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR0 +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_KBR0 +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR3 +#else + {S5PV210_GPH3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_KBR3 +#endif +#if defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(4), S3C_GPIO_EINT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_UP}, //GPIO_KBR4 +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + {S5PV210_GPH3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_OK_KEY + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_UP}, //GPIO_CP_RST +#elif defined(CONFIG_SAMSUNG_FASCINATE) + {S5PV210_GPH3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN}, //GPIO_OK_KEY + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_NONE}, //GPIO_CP_RST +#else //CONFIG_SAMSUNG_VIBRANT CONFIG_SAMSUNG_GALAXYS + {S5PV210_GPH3(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, S3C_GPIO_PULL_NONE}, //GPIO_CP_RST +#endif +}; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index a5a1e33..16b38f1 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -54,6 +54,34 @@ #define S5PV210_GPIO_MP03_NR (8) #define S5PV210_GPIO_MP04_NR (8) #define S5PV210_GPIO_MP05_NR (8) +#define S5PV210_GPIO_MP06_NR (8) +#define S5PV210_GPIO_MP07_NR (8) + +#define S5PV210_GPIO_MP10_NR (8) +#define S5PV210_GPIO_MP11_NR (8) +#define S5PV210_GPIO_MP12_NR (8) +#define S5PV210_GPIO_MP13_NR (8) +#define S5PV210_GPIO_MP14_NR (8) +#define S5PV210_GPIO_MP15_NR (8) +#define S5PV210_GPIO_MP16_NR (8) +#define S5PV210_GPIO_MP17_NR (8) +#define S5PV210_GPIO_MP18_NR (7) + +#define S5PV210_GPIO_MP20_NR (8) +#define S5PV210_GPIO_MP21_NR (8) +#define S5PV210_GPIO_MP22_NR (8) +#define S5PV210_GPIO_MP23_NR (8) +#define S5PV210_GPIO_MP24_NR (8) +#define S5PV210_GPIO_MP25_NR (8) +#define S5PV210_GPIO_MP26_NR (8) +#define S5PV210_GPIO_MP27_NR (8) +#define S5PV210_GPIO_MP28_NR (7) + +#define S5PV210_GPIO_ETC0_NR (6) +#define S5PV210_GPIO_ETC1_NR (8) +#define S5PV210_GPIO_ETC2_NR (8) +#define S5PV210_GPIO_ETC4_NR (6) + /* GPIO bank numbers */ @@ -98,6 +126,30 @@ enum s5p_gpio_number { S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03), S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04), + S5PV210_GPIO_MP06_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP05), + S5PV210_GPIO_MP07_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP06), + S5PV210_GPIO_MP10_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP07), + S5PV210_GPIO_MP11_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP10), + S5PV210_GPIO_MP12_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP11), + S5PV210_GPIO_MP13_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP12), + S5PV210_GPIO_MP14_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP13), + S5PV210_GPIO_MP15_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP14), + S5PV210_GPIO_MP16_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP15), + S5PV210_GPIO_MP17_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP16), + S5PV210_GPIO_MP18_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP17), + S5PV210_GPIO_MP20_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP18), + S5PV210_GPIO_MP21_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP20), + S5PV210_GPIO_MP22_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP21), + S5PV210_GPIO_MP23_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP22), + S5PV210_GPIO_MP24_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP23), + S5PV210_GPIO_MP25_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP24), + S5PV210_GPIO_MP26_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP25), + S5PV210_GPIO_MP27_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP26), + S5PV210_GPIO_MP28_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP27), + S5PV210_GPIO_ETC0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP28), + S5PV210_GPIO_ETC1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC0), + S5PV210_GPIO_ETC2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC1), + S5PV210_GPIO_ETC4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC2), }; /* S5PV210 GPIO number definitions */ @@ -133,15 +185,69 @@ enum s5p_gpio_number { #define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) #define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr)) #define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr)) +#define S5PV210_MP06(_nr) (S5PV210_GPIO_MP06_START + (_nr)) +#define S5PV210_MP07(_nr) (S5PV210_GPIO_MP07_START + (_nr)) +#define S5PV210_MP10(_nr) (S5PV210_GPIO_MP10_START + (_nr)) +#define S5PV210_MP11(_nr) (S5PV210_GPIO_MP11_START + (_nr)) +#define S5PV210_MP12(_nr) (S5PV210_GPIO_MP12_START + (_nr)) +#define S5PV210_MP13(_nr) (S5PV210_GPIO_MP13_START + (_nr)) +#define S5PV210_MP14(_nr) (S5PV210_GPIO_MP14_START + (_nr)) +#define S5PV210_MP15(_nr) (S5PV210_GPIO_MP15_START + (_nr)) +#define S5PV210_MP16(_nr) (S5PV210_GPIO_MP16_START + (_nr)) +#define S5PV210_MP17(_nr) (S5PV210_GPIO_MP17_START + (_nr)) +#define S5PV210_MP18(_nr) (S5PV210_GPIO_MP18_START + (_nr)) +#define S5PV210_MP20(_nr) (S5PV210_GPIO_MP20_START + (_nr)) +#define S5PV210_MP21(_nr) (S5PV210_GPIO_MP21_START + (_nr)) +#define S5PV210_MP22(_nr) (S5PV210_GPIO_MP22_START + (_nr)) +#define S5PV210_MP23(_nr) (S5PV210_GPIO_MP23_START + (_nr)) +#define S5PV210_MP24(_nr) (S5PV210_GPIO_MP24_START + (_nr)) +#define S5PV210_MP25(_nr) (S5PV210_GPIO_MP25_START + (_nr)) +#define S5PV210_MP26(_nr) (S5PV210_GPIO_MP26_START + (_nr)) +#define S5PV210_MP27(_nr) (S5PV210_GPIO_MP27_START + (_nr)) +#define S5PV210_MP28(_nr) (S5PV210_GPIO_MP28_START + (_nr)) +#define S5PV210_ETC0(_nr) (S5PV210_GPIO_ETC0_START + (_nr)) +#define S5PV210_ETC1(_nr) (S5PV210_GPIO_ETC1_START + (_nr)) +#define S5PV210_ETC2(_nr) (S5PV210_GPIO_ETC2_START + (_nr)) +#define S5PV210_ETC4(_nr) (S5PV210_GPIO_ETC4_START + (_nr)) + +/* Define EXT INT GPIO */ +#define S5P_EXT_INT0(x) S5PV210_GPH0(x) +#define S5P_EXT_INT1(x) S5PV210_GPH1(x) +#define S5P_EXT_INT2(x) S5PV210_GPH2(x) +#define S5P_EXT_INT3(x) S5PV210_GPH3(x) /* the end of the S5PV210 specific gpios */ -#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1) +#define S5PV210_GPIO_END (S5PV210_ETC4(S5PV210_GPIO_ETC4_NR) + 1) #define S3C_GPIO_END S5PV210_GPIO_END -/* define the number of gpios we need to the one after the MP05() range */ -#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \ +/* define the number of gpios we need to the one after the GPJ4() range */ +#define ARCH_NR_GPIOS (S5PV210_ETC4(S5PV210_GPIO_ETC4_NR) + \ CONFIG_SAMSUNG_GPIO_EXTRA + 1) #include <asm-generic/gpio.h> +#include <plat/gpio-cfg.h> + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int to); +extern s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin); + +#define S3C_GPIO_SLP_OUT0 ((__force s3c_gpio_pull_t)0x00) +#define S3C_GPIO_SLP_OUT1 ((__force s3c_gpio_pull_t)0x01) +#define S3C_GPIO_SLP_INPUT ((__force s3c_gpio_pull_t)0x02) +#define S3C_GPIO_SLP_PREV ((__force s3c_gpio_pull_t)0x03) + +extern int s3c_gpio_set_drvstrength(unsigned int pin, unsigned int config); +extern int s3c_gpio_set_slewrate(unsigned int pin, unsigned int config); + +#define S3C_GPIO_DRVSTR_1X (0) +#define S3C_GPIO_DRVSTR_2X (1) +#define S3C_GPIO_DRVSTR_3X (2) +#define S3C_GPIO_DRVSTR_4X (3) + +#define S3C_GPIO_SLEWRATE_FAST (0) +#define S3C_GPIO_SLEWRATE_SLOW (1) + +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, s3c_gpio_pull_t pull); +extern int s5pv210_gpiolib_init(void); + #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index b9f9ec3..b747128 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -17,6 +17,22 @@ /* VIC0: System, DMA, Timer */ +#define IRQ_EINT0 S5P_IRQ_VIC0(0) +#define IRQ_EINT1 S5P_IRQ_VIC0(1) +#define IRQ_EINT2 S5P_IRQ_VIC0(2) +#define IRQ_EINT3 S5P_IRQ_VIC0(3) +#define IRQ_EINT4 S5P_IRQ_VIC0(4) +#define IRQ_EINT5 S5P_IRQ_VIC0(5) +#define IRQ_EINT6 S5P_IRQ_VIC0(6) +#define IRQ_EINT7 S5P_IRQ_VIC0(7) +#define IRQ_EINT8 S5P_IRQ_VIC0(8) +#define IRQ_EINT9 S5P_IRQ_VIC0(9) +#define IRQ_EINT10 S5P_IRQ_VIC0(10) +#define IRQ_EINT11 S5P_IRQ_VIC0(11) +#define IRQ_EINT12 S5P_IRQ_VIC0(12) +#define IRQ_EINT13 S5P_IRQ_VIC0(13) +#define IRQ_EINT14 S5P_IRQ_VIC0(14) +#define IRQ_EINT15 S5P_IRQ_VIC0(15) #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) #define IRQ_BATF S5P_IRQ_VIC0(17) #define IRQ_MDMA S5P_IRQ_VIC0(18) @@ -116,17 +132,19 @@ #define IRQ_MDNIE1 S5P_IRQ_VIC3(6) #define IRQ_MDNIE2 S5P_IRQ_VIC3(7) #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) +#define IRQ_ADC1 S5P_IRQ_VIC3(9) +#define IRQ_PENDN1 S5P_IRQ_VIC3(10) #define IRQ_VIC_END S5P_IRQ_VIC3(31) #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) +#define S5P_IRQ_EINT_BASE S5P_EINT_BASE2 /* GPIO interrupt */ #define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) #define S5P_GPIOINT_GROUP_MAXNR 22 -/* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) +#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) /* Compatibility */ #define IRQ_LCD_FIFO IRQ_LCD0 @@ -134,4 +152,73 @@ #define IRQ_LCD_SYSTEM IRQ_LCD2 #define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (8) /* A0 */ +#define IRQ_EINT_GROUP2_NR (4) /* A1 */ +#define IRQ_EINT_GROUP3_NR (8) /* B */ +#define IRQ_EINT_GROUP4_NR (5) /* C0 */ +#define IRQ_EINT_GROUP5_NR (5) /* C1 */ +#define IRQ_EINT_GROUP6_NR (4) /* D0 */ +#define IRQ_EINT_GROUP7_NR (6) /* D1 */ +#define IRQ_EINT_GROUP8_NR (8) /* E0 */ +#define IRQ_EINT_GROUP9_NR (5) /* E1 */ +#define IRQ_EINT_GROUP10_NR (8) /* F0 */ +#define IRQ_EINT_GROUP11_NR (8) /* F1 */ +#define IRQ_EINT_GROUP12_NR (8) /* F2 */ +#define IRQ_EINT_GROUP13_NR (6) /* F3 */ +#define IRQ_EINT_GROUP14_NR (7) /* G0 */ +#define IRQ_EINT_GROUP15_NR (7) /* G1 */ +#define IRQ_EINT_GROUP16_NR (7) /* G2 */ +#define IRQ_EINT_GROUP17_NR (7) /* G3 */ +#define IRQ_EINT_GROUP18_NR (8) /* J0 */ +#define IRQ_EINT_GROUP19_NR (6) /* J1 */ +#define IRQ_EINT_GROUP20_NR (8) /* J2 */ +#define IRQ_EINT_GROUP21_NR (8) /* J3 */ +#define IRQ_EINT_GROUP22_NR (5) /* J4 */ + +#define IRQ_EINT_GROUP_BASE S5P_EINT(31 + 1) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) +#define IRQ_EINT_GROUP10_BASE (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR) +#define IRQ_EINT_GROUP11_BASE (IRQ_EINT_GROUP10_BASE + IRQ_EINT_GROUP10_NR) +#define IRQ_EINT_GROUP12_BASE (IRQ_EINT_GROUP11_BASE + IRQ_EINT_GROUP11_NR) +#define IRQ_EINT_GROUP13_BASE (IRQ_EINT_GROUP12_BASE + IRQ_EINT_GROUP12_NR) +#define IRQ_EINT_GROUP14_BASE (IRQ_EINT_GROUP13_BASE + IRQ_EINT_GROUP13_NR) +#define IRQ_EINT_GROUP15_BASE (IRQ_EINT_GROUP14_BASE + IRQ_EINT_GROUP14_NR) +#define IRQ_EINT_GROUP16_BASE (IRQ_EINT_GROUP15_BASE + IRQ_EINT_GROUP15_NR) +#define IRQ_EINT_GROUP17_BASE (IRQ_EINT_GROUP16_BASE + IRQ_EINT_GROUP16_NR) +#define IRQ_EINT_GROUP18_BASE (IRQ_EINT_GROUP17_BASE + IRQ_EINT_GROUP17_NR) +#define IRQ_EINT_GROUP19_BASE (IRQ_EINT_GROUP18_BASE + IRQ_EINT_GROUP18_NR) +#define IRQ_EINT_GROUP20_BASE (IRQ_EINT_GROUP19_BASE + IRQ_EINT_GROUP19_NR) +#define IRQ_EINT_GROUP21_BASE (IRQ_EINT_GROUP20_BASE + IRQ_EINT_GROUP20_NR) +#define IRQ_EINT_GROUP22_BASE (IRQ_EINT_GROUP21_BASE + IRQ_EINT_GROUP21_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) + +/* Set the default NR_IRQS */ +//#define NR_IRQS (IRQ_EINT(31) + 1) +#define NR_IRQS (IRQ_EINT_GROUP22_BASE + IRQ_EINT_GROUP22_NR + 1) + +#define HALL_SENSOR_IRQ IRQ_EINT3 + +#define FIQ_START 0 + #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 1dd5883..704e192 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -16,7 +16,11 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> -#define S5PV210_PA_SDRAM 0x20000000 +#if defined(CONFIG_MACH_SMDKV210) +#define S5PV210_PA_SDRAM (0x20000000) +#else +#define S5PV210_PA_SDRAM (0x30000000) +#endif #define S5PV210_PA_SROM_BANK5 0xA8000000 @@ -53,6 +57,9 @@ #define S5PV210_PA_WATCHDOG 0xE2700000 #define S5PV210_PA_RTC 0xE2800000 +#define S5PV210_VA_RTC S3C_ADDR(0x00c00000) +#define S5P_VA_RTC S5PV210_VA_RTC + #define S5PV210_PA_UART 0xE2900000 #define S5PV210_PA_SROMC 0xE8000000 @@ -61,9 +68,27 @@ #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) +/* usb */ +#define S5PV210_PA_OTG (0xEC000000) +#define S5PV210_SZ_OTG SZ_1M + +#define S5PV210_PA_OTGSFR (0xEC100000) +#define S5PV210_SZ_OTGSFR SZ_1M + +#define S5PV210_PA_USB_EHCI (0xEC200000) +#define S5P_PA_USB_EHCI S5PV210_PA_USB_EHCI +#define S5P_SZ_USB_EHCI SZ_1M + +#define S5PV210_PA_USB_OHCI (0xEC300000) +#define S5P_PA_USB_OHCI S5PV210_PA_USB_OHCI +#define S5P_SZ_USB_OHCI SZ_1M +/* end usb */ + #define S5PV210_PA_HSOTG 0xEC000000 #define S5PV210_PA_HSPHY 0xEC100000 +#define S5PV210_PA_AUDSS (0xEEE10000) + #define S5PV210_PA_IIS0 0xEEE30000 #define S5PV210_PA_IIS1 0xE2100000 #define S5PV210_PA_IIS2 0xE2A00000 @@ -71,6 +96,31 @@ #define S5PV210_PA_DMC0 0xF0000000 #define S5PV210_PA_DMC1 0xF1400000 +#define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0) +#define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define S5P_VA_VIC2 (S3C_VA_IRQ + 0x20000) +#define S5P_VA_VIC3 (S3C_VA_IRQ + 0x30000) + +#define S5PV210_PA_LCD (0xF8000000) +#define S5P_PA_LCD S5PV210_PA_LCD +#define S5PV210_SZ_LCD SZ_1M +#define S5P_SZ_LCD S5PV210_SZ_LCD + +#define S5PV210_PA_JPEG (0xFB600000) +#define S5PV210_SZ_JPEG SZ_1M + +#define S5PV210_SZ_FIMC0 SZ_1M +#define S5P_SZ_FIMC0 S5PV210_SZ_FIMC0 +#define S5PV210_SZ_FIMC1 SZ_1M +#define S5P_SZ_FIMC1 S5PV210_SZ_FIMC1 +#define S5PV210_SZ_FIMC2 SZ_1M +#define S5P_SZ_FIMC2 S5PV210_SZ_FIMC2 + +#define S5PV210_PA_IPC (0xFB700000) +#define S5P_PA_IPC S5PV210_PA_IPC +#define S5PV210_SZ_IPC SZ_1M +#define S5P_SZ_IPC S5PV210_SZ_IPC + #define S5PV210_PA_VIC0 0xF2000000 #define S5PV210_PA_VIC1 0xF2100000 #define S5PV210_PA_VIC2 0xF2200000 @@ -88,6 +138,28 @@ #define S5PV210_PA_FIMC1 0xFB300000 #define S5PV210_PA_FIMC2 0xFB400000 +/* mfc */ +#define S5PV210_PA_MFC (0xF1700000) +#define S5PV210_SZ_MFC SZ_1M +#define S5P_PA_MFC S5PV210_PA_MFC +#define S5P_SZ_MFC S5PV210_SZ_MFC + + +/* jpeg */ +#define S5PV210_PA_JPEG (0xFB600000) +#define S5P_PA_JPEG S5PV210_PA_JPEG +#define S5P_SZ_JPEG SZ_1M + +/* rotator */ +#define S5PV210_PA_ROTATOR (0xFA300000) +#define S5P_PA_ROTATOR S5PV210_PA_ROTATOR +#define S5P_SZ_ROTATOR SZ_1M + +/* fimg2d */ +#define S5PV210_PA_FIMG2D (0xFA000000) +#define S5P_PA_FIMG2D S5PV210_PA_FIMG2D +#define S5P_SZ_FIMG2D SZ_1M + /* Compatibiltiy Defines */ #define S3C_PA_FB S5PV210_PA_FB @@ -132,4 +204,38 @@ #define S5P_SZ_UART SZ_256 +/* CEC */ +#define S5PV210_PA_CEC (0xE1B00000) +#define S5P_PA_CEC S5PV210_PA_CEC +#define S5P_SZ_CEC SZ_4K + +/* TVOUT */ +#define S5PV210_PA_TVENC (0xF9000000) +#define S5P_PA_TVENC S5PV210_PA_TVENC +#define S5P_SZ_TVENC SZ_1M + +#define S5PV210_PA_VP (0xF9100000) +#define S5P_PA_VP S5PV210_PA_VP +#define S5P_SZ_VP SZ_1M + +#define S5PV210_PA_MIXER (0xF9200000) +#define S5P_PA_MIXER S5PV210_PA_MIXER +#define S5P_SZ_MIXER SZ_1M + +#define S5PV210_PA_HDMI (0xFA100000) +#define S5P_PA_HDMI S5PV210_PA_HDMI +#define S5P_SZ_HDMI SZ_1M + +#define S5PV210_I2C_HDMI_PHY (0xFA900000) +#define S5P_I2C_HDMI_PHY S5PV210_I2C_HDMI_PHY +#define S5P_I2C_HDMI_SZ_PHY SZ_1K + +/* usb */ +#define S3C_PA_OTG S5PV210_PA_OTG +#define S3C_SZ_OTG S5PV210_SZ_OTG + +#define S3C_PA_OTGSFR S5PV210_PA_OTGSFR +#define S3C_SZ_OTGSFR S5PV210_SZ_OTGSFR + +/* end usb */ #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/media.h b/arch/arm/mach-s5pv210/include/mach/media.h new file mode 100755 index 0000000..ad9eb82 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/media.h @@ -0,0 +1,32 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/media.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung Media device descriptions for smdkv210 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _S5PV210_MEDIA_H +#define _S5PV210_MEDIA_H + +/* 3 fimc indexes should be fixed as n, n+1 and n+2 */ +#define S5P_MDEV_FIMC0 0 +#define S5P_MDEV_FIMC1 1 +#define S5P_MDEV_FIMC2 2 +#define S5P_MDEV_TV 3 +#define S5P_MDEV_MFC 4 +#define S5P_MDEV_JPEG 5 +#define S5P_MDEV_PMEM 6 +#define S5P_MDEV_PMEM_GPU1 7 +#define S5P_MDEV_PMEM_ADSP 8 +#define S5P_MDEV_TEXSTREAM 9 +#define S5P_MDEV_FIMD 10 +#define S5P_MDEV_MAX 11 + +#define S5P_RANGE_MFC SZ_256M +#endif + diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h index 7b5fcf0..003d287 100644 --- a/arch/arm/mach-s5pv210/include/mach/memory.h +++ b/arch/arm/mach-s5pv210/include/mach/memory.h @@ -13,7 +13,12 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H +#if defined(CONFIG_MACH_SMDKV210) #define PLAT_PHYS_OFFSET UL(0x20000000) +#else +#define PLAT_PHYS_OFFSET UL(0x30000000) +#endif + #define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) /* @@ -24,5 +29,6 @@ #define MAX_PHYSMEM_BITS 31 #define SECTION_SIZE_BITS 28 +#define NODE_MEM_SIZE_BITS 28 #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/param.h b/arch/arm/mach-s5pv210/include/mach/param.h new file mode 100644 index 0000000..dbba308 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/param.h @@ -0,0 +1,89 @@ +
+/*
+ * Parameter Infomation
+ */
+
+#ifndef ASM_MACH_PARAM_H
+#define ASM_MACH_PARAM_H
+
+#define PARAM_MAGIC 0x72726624
+#define PARAM_VERSION 0x13 /* Rev 1.3 */
+#define PARAM_STRING_SIZE 1024 /* 1024 Characters */
+
+#define MAX_PARAM 20
+#define MAX_STRING_PARAM 5
+
+/* Default Parameter Values */
+
+#define SERIAL_SPEED 7 /* Baudrate */
+#define LCD_LEVEL 0x061 /* Backlight Level */
+#define BOOT_DELAY 0 /* Boot Wait Time */
+#define LOAD_RAMDISK 0 /* Enable Ramdisk Loading */
+#define SWITCH_SEL 1 /* Switch Setting (UART[1], USB[0]) */
+#define PHONE_DEBUG_ON 0 /* Enable Phone Debug Mode */
+#define LCD_DIM_LEVEL 0x011 /* Backlight Dimming Level */
+#define LCD_DIM_TIME 0
+#define MELODY_MODE 0 /* Melody Mode */
+#define REBOOT_MODE 0 /* Reboot Mode */
+#define NATION_SEL 0 /* Language Configuration */
+#define LANGUAGE_SEL 0
+#define SET_DEFAULT_PARAM 0 /* Set Param to Default */
+#define VERSION_LINE "I8315XXIE00" /* Set Image Info */
+#define COMMAND_LINE "console=ttySAC2,115200"
+#define BOOT_VERSION " version=Sbl(1.0.0) "
+
+typedef enum {
+ __SERIAL_SPEED,
+ __LOAD_RAMDISK,
+ __BOOT_DELAY,
+ __LCD_LEVEL,
+ __SWITCH_SEL,
+ __PHONE_DEBUG_ON,
+ __LCD_DIM_LEVEL,
+ __LCD_DIM_TIME,
+ __MELODY_MODE,
+ __REBOOT_MODE,
+ __NATION_SEL,
+ __LANGUAGE_SEL,
+ __SET_DEFAULT_PARAM,
+ __PARAM_INT_13, /* Reserved. */
+ __PARAM_INT_14, /* Reserved. */
+ __VERSION,
+ __CMDLINE,
+ __PARAM_STR_2,
+ __PARAM_STR_3, /* Reserved. */
+ __PARAM_STR_4 /* Reserved. */
+} param_idx;
+
+typedef struct _param_int_t {
+ param_idx ident;
+ int value;
+} param_int_t;
+
+typedef struct _param_str_t {
+ param_idx ident;
+ char value[PARAM_STRING_SIZE];
+} param_str_t;
+
+typedef struct {
+ int param_magic;
+ int param_version;
+ param_int_t param_list[MAX_PARAM - MAX_STRING_PARAM];
+ param_str_t param_str_list[MAX_STRING_PARAM];
+} status_t;
+
+/* REBOOT_MODE */
+#define REBOOT_MODE_NONE 0
+#define REBOOT_MODE_DOWNLOAD 1
+#define REBOOT_MODE_CHARGING 3
+#define REBOOT_MODE_RECOVERY 4
+#define REBOOT_MODE_ARM11_FOTA 5
+#define REBOOT_MODE_ARM9_FOTA 6
+
+extern void (*sec_set_param_value)(int idx, void *value);
+extern void (*sec_get_param_value)(int idx, void *value);
+
+#define USB_SEL_MASK (1 << 0)
+#define UART_SEL_MASK (1 << 1)
+
+#endif /* ASM_MACH_PARAM_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index e8d394f..e0db671 100644..100755 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h @@ -14,6 +14,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <mach/regs-gpio.h> static inline void s3c_pm_debug_init_uart(void) { @@ -33,7 +34,10 @@ static inline void s3c_pm_arch_stop_clocks(void) static inline void s3c_pm_arch_show_resume_irqs(void) { - /* nothing here yet */ + printk(KERN_DEBUG "S5P_WAKEUP_STAT 0x%X\n", __raw_readl(S5P_WAKEUP_STAT)); + printk(KERN_DEBUG "EINT_PEND 0x%X, 0x%X, 0x%X, 0x%X\n", + __raw_readl(S5P_EINT_PEND(0)), __raw_readl(S5P_EINT_PEND(1)), + __raw_readl(S5P_EINT_PEND(2)), __raw_readl(S5P_EINT_PEND(3))); } static inline void s3c_pm_arch_update_uart(void __iomem *regs, @@ -41,3 +45,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, { /* nothing here yet */ } + diff --git a/arch/arm/mach-s5pv210/include/mach/power-domain.h b/arch/arm/mach-s5pv210/include/mach/power-domain.h new file mode 100644 index 0000000..8456c10 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/power-domain.h @@ -0,0 +1,57 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/power-domain.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Power domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_POWER_DOMAIN_H +#define __ASM_ARCH_POWER_DOMAIN_H __FILE__ + +#define S5PV210_PD_IROM (1 << 20) +#define S5PV210_PD_AUDIO (1 << 7) +#define S5PV210_PD_CAM (1 << 5) +#define S5PV210_PD_TV (1 << 4) +#define S5PV210_PD_LCD (1 << 3) +#define S5PV210_PD_G3D (1 << 2) +#define S5PV210_PD_MFC (1 << 1) + +struct regulator_init_data; + +/** + * struct s5pv210_pd_config - s5pv210_pd_config structure + * @supply_name: Name of the regulator supply + * @microvolts: Output voltage of regulator + * @startup_delay: Start-up time in microseconds + * @init_data: regulator_init_data + * @clk_should_be_running: the clocks for the IPs in the power domain + * should be running when the power domain + * is turned on + * @ctrlbit: register control bit + * + * This structure contains samsung power domain regulator configuration + * information that must be passed by platform code to the samsung + * power domain regulator driver. + */ +struct s5pv210_pd_config { + const char *supply_name; + int microvolts; + unsigned startup_delay; + struct regulator_init_data *init_data; + struct clk_should_be_running *clk_run; + int ctrlbit; +}; + +extern struct platform_device s5pv210_pd_audio; +extern struct platform_device s5pv210_pd_cam; +extern struct platform_device s5pv210_pd_tv; +extern struct platform_device s5pv210_pd_lcd; +extern struct platform_device s5pv210_pd_g3d; +extern struct platform_device s5pv210_pd_mfc; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/regs-adc.h b/arch/arm/mach-s5pv210/include/mach/regs-adc.h new file mode 100644 index 0000000..200fed9 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-adc.h @@ -0,0 +1,119 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-adc.h + * + * Copyright (c) 2004 Shannon Holland <holland@loser.net> + * + * This program is free software; yosu can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 ADC registers +*/ + +#ifndef __ASM_ARCH_REGS_ADC_H +#define __ASM_ARCH_REGS_ADC_H "regs-adc.h" + +#define S3C2410_ADCREG(x) (x) + +#define S3C2410_ADCCON S3C2410_ADCREG(0x00) +#define S3C2410_ADCTSC S3C2410_ADCREG(0x04) +#define S3C2410_ADCDLY S3C2410_ADCREG(0x08) +#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) +#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) + + +/* ADCCON Register Bits */ +#define S3C2410_ADCCON_ECFLG (1<<15) +#define S3C2410_ADCCON_PRSCEN (1<<14) +#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C2410_ADCCON_MUXMASK (0x7<<3) +#define S3C2410_ADCCON_STDBM (1<<2) +#define S3C2410_ADCCON_READ_START (1<<1) +#define S3C2410_ADCCON_ENABLE_START (1<<0) +#define S3C2410_ADCCON_STARTMASK (0x3<<0) + + +/* ADCTSC Register Bits */ +#define S3C2410_ADCTSC_YM_SEN (1<<7) +#define S3C2410_ADCTSC_YP_SEN (1<<6) +#define S3C2410_ADCTSC_XM_SEN (1<<5) +#define S3C2410_ADCTSC_XP_SEN (1<<4) +#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C2410_ADCTSC_AUTO_PST (1<<2) +#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) + +/* ADCDAT0 Bits */ +#define S3C2410_ADCDAT0_UPDOWN (1<<15) +#define S3C2410_ADCDAT0_AUTO_PST (1<<14) +#define S3C2410_ADCDAT0_XY_PST (0x3<<12) +#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) + +/* ADCDAT1 Bits */ +#define S3C2410_ADCDAT1_UPDOWN (1<<15) +#define S3C2410_ADCDAT1_AUTO_PST (1<<14) +#define S3C2410_ADCDAT1_XY_PST (0x3<<12) +#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) + +/*--------------------------- Common definitions for S3C ---------------------------*/ +/* The following definitions will be applied to S3C24XX, S3C64XX, S5PC1XX. */ +/*-----------------------------------------------------------------------------------*/ + +#define S3C_ADCREG(x) (x) + +#define S3C_ADCCON S3C_ADCREG(0x00) +#define S3C_ADCTSC S3C_ADCREG(0x04) +#define S3C_ADCDLY S3C_ADCREG(0x08) +#define S3C_ADCDAT0 S3C_ADCREG(0x0C) +#define S3C_ADCDAT1 S3C_ADCREG(0x10) +#define S3C_ADCUPDN S3C_ADCREG(0x14) +#define S3C_ADCCLRINT S3C_ADCREG(0x18) +#define S3C_ADCMUX S3C_ADCREG(0x1C) +#define S3C_ADCCLRWK S3C_ADCREG(0x20) + + +/* ADCCON Register Bits */ +#define S3C_ADCCON_RESSEL_10BIT (0x0<<16) +#define S3C_ADCCON_RESSEL_12BIT (0x1<<16) +#define S3C_ADCCON_ECFLG (1<<15) +#define S3C_ADCCON_PRSCEN (1<<14) +#define S3C_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C_ADCCON_SELMUX_1(x) (((x)&0xF)<<0) +#define S3C_ADCCON_MUXMASK (0x7<<3) +#define S3C_ADCCON_RESSEL_10BIT_1 (0x0<<3) +#define S3C_ADCCON_RESSEL_12BIT_1 (0x1<<3) +#define S3C_ADCCON_STDBM (1<<2) +#define S3C_ADCCON_READ_START (1<<1) +#define S3C_ADCCON_ENABLE_START (1<<0) +#define S3C_ADCCON_STARTMASK (0x3<<0) + + +/* ADCTSC Register Bits */ +#define S3C_ADCTSC_UD_SEN (1<<8) +#define S3C_ADCTSC_YM_SEN (1<<7) +#define S3C_ADCTSC_YP_SEN (1<<6) +#define S3C_ADCTSC_XM_SEN (1<<5) +#define S3C_ADCTSC_XP_SEN (1<<4) +#define S3C_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C_ADCTSC_AUTO_PST (1<<2) +#define S3C_ADCTSC_XY_PST(x) (((x)&0x3)<<0) + +/* ADCDAT0 Bits */ +#define S3C_ADCDAT0_UPDOWN (1<<15) +#define S3C_ADCDAT0_AUTO_PST (1<<14) +#define S3C_ADCDAT0_XY_PST (0x3<<12) +#define S3C_ADCDAT0_XPDATA_MASK (0x03FF) +#define S3C_ADCDAT0_XPDATA_MASK_12BIT (0x0FFF) + +/* ADCDAT1 Bits */ +#define S3C_ADCDAT1_UPDOWN (1<<15) +#define S3C_ADCDAT1_AUTO_PST (1<<14) +#define S3C_ADCDAT1_XY_PST (0x3<<12) +#define S3C_ADCDAT1_YPDATA_MASK (0x03FF) +#define S3C_ADCDAT1_YPDATA_MASK_12BIT (0x0FFF) + +#endif /* __ASM_ARCH_REGS_ADC_H */ + + diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h new file mode 100644 index 0000000..b2cc2fd --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h @@ -0,0 +1,44 @@ +/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h + * + * Copyright 2008 Samsung Electronics + * + * S5PV2XX Audio SubSystem clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_AUDSS_H +#define __PLAT_REGS_AUDSS_H __FILE__ + +#define S5P_AUDSSREG(x) (S5P_VA_AUDSS + (x)) + +#define S5P_CLKSRC_AUDSS S5P_AUDSSREG(0x0) +#define S5P_CLKDIV_AUDSS S5P_AUDSSREG(0x4) +#define S5P_CLKGATE_AUDSS S5P_AUDSSREG(0x8) + +/* CLKSRC0 */ +#define S5P_AUDSS_CLKSRC_MAIN_MASK (0x1<<0) +#define S5P_AUDSS_CLKSRC_MAIN_SHIFT (0) +#define S5P_AUDSS_CLKSRC_BUSCLK_MASK (0x1<<1) +#define S5P_AUDSS_CLKSRC_BUSCLK_SHIFT (1) +#define S5P_AUDSS_CLKSRC_I2SCLK_MASK (0x3<<2) +#define S5P_AUDSS_CLKSRC_I2SCLK_SHIFT (2) + +/* CLKDIV0 */ +#define S5P_AUDSS_CLKDIV_BUSCLK_MASK (0xf<<0) +#define S5P_AUDSS_CLKDIV_BUSCLK_SHIFT (0) +#define S5P_AUDSS_CLKDIV_I2SCLK_MASK (0xf<<4) +#define S5P_AUDSS_CLKDIV_I2SCLK_SHIFT (4) + +/* IP Clock Gate 0 Registers */ +#define S5P_AUDSS_CLKGATE_HCLKRP (1<<0) +#define S5P_AUDSS_CLKGATE_HCLKBUF (1<<1) +#define S5P_AUDSS_CLKGATE_HCLKDMA (1<<2) +#define S5P_AUDSS_CLKGATE_HCLKHWA (1<<3) +#define S5P_AUDSS_CLKGATE_HCLKUART (1<<4) +#define S5P_AUDSS_CLKGATE_HCLKI2S (1<<5) +#define S5P_AUDSS_CLKGATE_CLKI2S (1<<6) + +#endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 78925c5..d5d51cd 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -17,6 +17,9 @@ #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) +#define S5P_IECREG(x) (S5PC11X_VA_IEC + (x)) +#define S5P_APCREG(x) (S5PC11X_VA_APC + (x)) + #define S5P_APLL_LOCK S5P_CLKREG(0x00) #define S5P_MPLL_LOCK S5P_CLKREG(0x08) #define S5P_EPLL_LOCK S5P_CLKREG(0x10) @@ -64,8 +67,7 @@ #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) -#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) -#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) +#define S5P_CLKGATE_IP5 S5P_CLKREG(0x484) #define S5P_CLK_OUT S5P_CLKREG(0x500) /* DIV/MUX STATUS */ @@ -77,6 +79,17 @@ /* CLKSRC0 */ #define S5P_CLKSRC0_MUX200_SHIFT (16) #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) + +#define S5P_MIXER_OUT_SEL S5P_CLKREG(0x7004) + +#define S5P_EPLL_EN (1<<31) +#define S5P_EPLL_MASK 0xffffffff +#define S5P_EPLLVAL(_v,_m,_p,_s) ((_v) << 27 | (_m) << 16 | ((_p) << 8) | ((_s))) + +#define S5P_EPLL_MASK_VSEL (0x1<<27) +#define S5P_EPLL_MASK_M (0x1FF<<16) +#define S5P_EPLL_MASK_P (0x3F<<8) +#define S5P_EPLL_MASK_S (0x3<<0) #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) @@ -122,6 +135,161 @@ #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) +/* IP Clock Gate 0 Registers */ +#define S5P_CLKGATE_IP0_CSIS (1<<31) +#define S5P_CLKGATE_IP0_IPC (1<<30) +#define S5P_CLKGATE_IP0_ROTATOR (1<<29) +#define S5P_CLKGATE_IP0_JPEG (1<<28) +#define S5P_CLKGATE_IP0_FIMC2 (1<<26) +#define S5P_CLKGATE_IP0_FIMC1 (1<<25) +#define S5P_CLKGATE_IP0_FIMC0 (1<<24) +#define S5P_CLKGATE_IP0_MFC (1<<16) +#define S5P_CLKGATE_IP0_G2D (1<<12) +#define S5P_CLKGATE_IP0_G3D (1<<8) +#define S5P_CLKGATE_IP0_IMEM (1<<5) +#define S5P_CLKGATE_IP0_PDMA1 (1<<4) +#define S5P_CLKGATE_IP0_PDMA0 (1<<3) +#define S5P_CLKGATE_IP0_MDMA (1<<2) +#define S5P_CLKGATE_IP0_DMC1 (1<<1) +#define S5P_CLKGATE_IP0_DMC0 (1<<0) + +/* IP Clock Gate 1 Registers */ +#define S5P_CLKGATE_IP1_NFCON (1<<28) +#define S5P_CLKGATE_IP1_SROMC (1<<26) +#define S5P_CLKGATE_IP1_CFCON (1<<25) +#define S5P_CLKGATE_IP1_NANDXL (1<<24) +#define S5P_CLKGATE_IP1_USBHOST (1<<17) +#define S5P_CLKGATE_IP1_USBOTG (1<<16) +#define S5P_CLKGATE_IP1_HDMI (1<<11) +#define S5P_CLKGATE_IP1_TVENC (1<<10) +#define S5P_CLKGATE_IP1_MIXER (1<<9) +#define S5P_CLKGATE_IP1_VP (1<<8) +#define S5P_CLKGATE_IP1_DSIM (1<<2) +#define S5P_CLKGATE_IP1_MIE (1<<1) +#define S5P_CLKGATE_IP1_FIMD (1<<0) + +/* IP Clock Gate 2 Registers */ +#define S5P_CLKGATE_IP2_TZIC3 (1<<31) +#define S5P_CLKGATE_IP2_TZIC2 (1<<30) +#define S5P_CLKGATE_IP2_TZIC1 (1<<29) +#define S5P_CLKGATE_IP2_TZIC0 (1<<28) +#define S5P_CLKGATE_IP2_VIC3 (1<<27) +#define S5P_CLKGATE_IP2_VIC2 (1<<26) +#define S5P_CLKGATE_IP2_VIC1 (1<<25) +#define S5P_CLKGATE_IP2_VIC0 (1<<24) +#define S5P_CLKGATE_IP2_TSI (1<<20) +#define S5P_CLKGATE_IP2_HSMMC3 (1<<19) +#define S5P_CLKGATE_IP2_HSMMC2 (1<<18) +#define S5P_CLKGATE_IP2_HSMMC1 (1<<17) +#define S5P_CLKGATE_IP2_HSMMC0 (1<<16) +#define S5P_CLKGATE_IP2_SECJTAG (1<<11) +#define S5P_CLKGATE_IP2_HOSTIF (1<<10) +#define S5P_CLKGATE_IP2_MODEM (1<<9) +#define S5P_CLKGATE_IP2_CORESIGHT (1<<8) +#define S5P_CLKGATE_IP2_SDM (1<<1) +#define S5P_CLKGATE_IP2_SECSS (1<<0) + +/* IP Clock Gate 3 Registers */ +#define S5P_CLKGATE_IP3_PCM2 (1<<30) +#define S5P_CLKGATE_IP3_PCM1 (1<<29) +#define S5P_CLKGATE_IP3_PCM0 (1<<28) +#define S5P_CLKGATE_IP3_SYSCON (1<<27) +#define S5P_CLKGATE_IP3_GPIO (1<<26) +#define S5P_CLKGATE_IP3_TSADC (1<<24) +#define S5P_CLKGATE_IP3_PWM (1<<23) +#define S5P_CLKGATE_IP3_WDT (1<<22) +#define S5P_CLKGATE_IP3_KEYIF (1<<21) +#define S5P_CLKGATE_IP3_UART3 (1<<20) +#define S5P_CLKGATE_IP3_UART2 (1<<19) +#define S5P_CLKGATE_IP3_UART1 (1<<18) +#define S5P_CLKGATE_IP3_UART0 (1<<17) +#define S5P_CLKGATE_IP3_SYSTIMER (1<<16) +#define S5P_CLKGATE_IP3_RTC (1<<15) +#define S5P_CLKGATE_IP3_SPI2 (1<<14) +#define S5P_CLKGATE_IP3_SPI1 (1<<13) +#define S5P_CLKGATE_IP3_SPI0 (1<<12) +#define S5P_CLKGATE_IP3_I2C_HDMI_PHY (1<<11) +#define S5P_CLKGATE_IP3_I2C_HDMI_DDC (1<<10) +#define S5P_CLKGATE_IP3_I2C2 (1<<9) +#define S5P_CLKGATE_IP3_I2C1 (1<<8) +#define S5P_CLKGATE_IP3_I2C0 (1<<7) +#define S5P_CLKGATE_IP3_I2S2 (1<<6) +#define S5P_CLKGATE_IP3_I2S1 (1<<5) +#define S5P_CLKGATE_IP3_I2S0 (1<<4) +#define S5P_CLKGATE_IP3_AC97 (1<<1) +#define S5P_CLKGATE_IP3_SPDIF (1<<0) + +/* IP Clock Gate 4 Registers */ +#define S5P_CLKGATE_IP4_TZPC3 (1<<8) +#define S5P_CLKGATE_IP4_TZPC2 (1<<7) +#define S5P_CLKGATE_IP4_TZPC1 (1<<6) +#define S5P_CLKGATE_IP4_TZPC0 (1<<5) +#define S5P_CLKGATE_IP4_SECKEY (1<<3) +#define S5P_CLKGATE_IP4_IEM_APC (1<<2) +#define S5P_CLKGATE_IP4_IEM_IEC (1<<1) +#define S5P_CLKGATE_IP4_CHIP_ID (1<<0) + +/* Block Clock Gate Registers */ +#define S5P_CLKGATE_BLOCK_INTC (1<<10) +#define S5P_CLKGATE_BLOCK_HSMMC (1<<9) +#define S5P_CLKGATE_BLOCK_DEBUG (1<<8) +#define S5P_CLKGATE_BLOCK_SECURITY (1<<7) +#define S5P_CLKGATE_BLOCK_MEMORY (1<<6) +#define S5P_CLKGATE_BLOCK_USB (1<<5) +#define S5P_CLKGATE_BLOCK_TV (1<<4) +#define S5P_CLKGATE_BLOCK_LCD (1<<3) +#define S5P_CLKGATE_BLOCK_IMG (1<<2) +#define S5P_CLKGATE_BLOCK_MFC (1<<1) +#define S5P_CLKGATE_BLOCK_G3D (1<<0) + +/* IP Clock Gate 5 Registers */ +#define S5P_CLKGATE_IP5_JPEG (1<<29) + + +/* Bus Clock Gate Registers (hidden) */ + +/* register for EINT on PM Driver */ +#define S5P_APM_REG(x) ((x) + 0xE0200C00) + +#define S5P_APM_BASE S5P_APM_REG(0x000) + +#define S5P_APM_GPH0CON (0x000) +#define S5P_APM_GPH0DAT (0x004) +#define S5P_APM_GPH0PUD (0x008) +#define S5P_APM_GPH0DRV (0x00C) +#define S5P_APM_GPH1CON (0x020) +#define S5P_APM_GPH1DAT (0x024) +#define S5P_APM_GPH1PUD (0x028) +#define S5P_APM_GPH1DRV (0x02C) +#define S5P_APM_GPH2CON (0x040) +#define S5P_APM_GPH2DAT (0x044) +#define S5P_APM_GPH2PUD (0x048) +#define S5P_APM_GPH2DRV (0x04C) +#define S5P_APM_GPH3CON (0x060) +#define S5P_APM_GPH3DAT (0x064) +#define S5P_APM_GPH3PUD (0x068) +#define S5P_APM_GPH3DRV (0x06C) +#define S5P_APM_WEINT0_CON (0x200) +#define S5P_APM_WEINT1_CON (0x204) +#define S5P_APM_WEINT2_CON (0x208) +#define S5P_APM_WEINT3_CON (0x20C) +#define S5P_APM_WEINT0_FLTCON0 (0x280) +#define S5P_APM_WEINT0_FLTCON1 (0x284) +#define S5P_APM_WEINT1_FLTCON0 (0x288) +#define S5P_APM_WEINT1_FLTCON1 (0x28C) +#define S5P_APM_WEINT2_FLTCON0 (0x290) +#define S5P_APM_WEINT2_FLTCON1 (0x294) +#define S5P_APM_WEINT3_FLTCON0 (0x298) +#define S5P_APM_WEINT3_FLTCON1 (0x29C) +#define S5P_APM_WEINT0_MASK (0x300) +#define S5P_APM_WEINT1_MASK (0x304) +#define S5P_APM_WEINT2_MASK (0x308) +#define S5P_APM_WEINT3_MASK (0x30C) +#define S5P_APM_WEINT0_PEND (0x340) +#define S5P_APM_WEINT1_PEND (0x344) +#define S5P_APM_WEINT2_PEND (0x348) +#define S5P_APM_WEINT3_PEND (0x34C) + /* Registers related to power management */ #define S5P_PWR_CFG S5P_CLKREG(0xC000) #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) @@ -141,15 +309,21 @@ #define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) #define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) +#define S5P_ABB_VALUE S5P_CLKREG(0xC300) #define S5P_OTHERS S5P_CLKREG(0xE000) #define S5P_OM_STAT S5P_CLKREG(0xE100) +#define S5P_MIE_CONTROL S5P_CLKREG(0xE800) +#define S5P_HDMI_CONTROL S5P_CLKREG(0xE804) #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) #define S5P_DAC_CONTROL S5P_CLKREG(0xE810) #define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814) #define S5P_MIPI_DPHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_SRESETN (1 << 1) #define S5P_MIPI_DPHY_MRESETN (1 << 2) +#define S5P_ADC_CONTROL S5P_CLKREG(0xE818) +#define S5P_PSHOLD_CONTROL S5P_CLKREG(0xE81C) #define S5P_INFORM0 S5P_CLKREG(0xF000) #define S5P_INFORM1 S5P_CLKREG(0xF004) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h index de0c899..b2c69e8 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h @@ -15,11 +15,230 @@ #include <mach/map.h> +/* Base addresses for each of the banks */ + +#define S5PV210_GPA0_BASE (S5P_VA_GPIO + 0x000) +#define S5PV210_GPA1_BASE (S5P_VA_GPIO + 0x020) +#define S5PV210_GPB_BASE (S5P_VA_GPIO + 0x040) +#define S5PV210_GPC0_BASE (S5P_VA_GPIO + 0x060) +#define S5PV210_GPC1_BASE (S5P_VA_GPIO + 0x080) +#define S5PV210_GPD0_BASE (S5P_VA_GPIO + 0x0A0) +#define S5PV210_GPD1_BASE (S5P_VA_GPIO + 0x0C0) +#define S5PV210_GPE0_BASE (S5P_VA_GPIO + 0x0E0) +#define S5PV210_GPE1_BASE (S5P_VA_GPIO + 0x100) +#define S5PV210_GPF0_BASE (S5P_VA_GPIO + 0x120) +#define S5PV210_GPF1_BASE (S5P_VA_GPIO + 0x140) +#define S5PV210_GPF2_BASE (S5P_VA_GPIO + 0x160) +#define S5PV210_GPF3_BASE (S5P_VA_GPIO + 0x180) +#define S5PV210_GPG0_BASE (S5P_VA_GPIO + 0x1A0) +#define S5PV210_GPG1_BASE (S5P_VA_GPIO + 0x1C0) +#define S5PV210_GPG2_BASE (S5P_VA_GPIO + 0x1E0) +#define S5PV210_GPG3_BASE (S5P_VA_GPIO + 0x200) +#define S5PV210_GPH0_BASE (S5P_VA_GPIO + 0xC00) +#define S5PV210_GPH1_BASE (S5P_VA_GPIO + 0xC20) +#define S5PV210_GPH2_BASE (S5P_VA_GPIO + 0xC40) +#define S5PV210_GPH3_BASE (S5P_VA_GPIO + 0xC60) +#define S5PV210_GPI_BASE (S5P_VA_GPIO + 0x220) +#define S5PV210_GPJ0_BASE (S5P_VA_GPIO + 0x240) +#define S5PV210_GPJ1_BASE (S5P_VA_GPIO + 0x260) +#define S5PV210_GPJ2_BASE (S5P_VA_GPIO + 0x280) +#define S5PV210_GPJ3_BASE (S5P_VA_GPIO + 0x2A0) +#define S5PV210_GPJ4_BASE (S5P_VA_GPIO + 0x2C0) +#define S5PV210_MP01_BASE (S5P_VA_GPIO + 0x2E0) +#define S5PV210_MP02_BASE (S5P_VA_GPIO + 0x300) +#define S5PV210_MP03_BASE (S5P_VA_GPIO + 0x320) +#define S5PV210_MP04_BASE (S5P_VA_GPIO + 0x340) +#define S5PV210_MP05_BASE (S5P_VA_GPIO + 0x360) +#define S5PV210_MP06_BASE (S5P_VA_GPIO + 0x380) +#define S5PV210_MP07_BASE (S5P_VA_GPIO + 0x3A0) +#define S5PV210_MP10_BASE (S5P_VA_GPIO + 0x3C0) +#define S5PV210_MP11_BASE (S5P_VA_GPIO + 0x3E0) +#define S5PV210_MP12_BASE (S5P_VA_GPIO + 0x400) +#define S5PV210_MP13_BASE (S5P_VA_GPIO + 0x420) +#define S5PV210_MP14_BASE (S5P_VA_GPIO + 0x440) +#define S5PV210_MP15_BASE (S5P_VA_GPIO + 0x460) +#define S5PV210_MP16_BASE (S5P_VA_GPIO + 0x480) +#define S5PV210_MP17_BASE (S5P_VA_GPIO + 0x4A0) +#define S5PV210_MP18_BASE (S5P_VA_GPIO + 0x4C0) +#define S5PV210_MP20_BASE (S5P_VA_GPIO + 0x4E0) +#define S5PV210_MP21_BASE (S5P_VA_GPIO + 0x500) +#define S5PV210_MP22_BASE (S5P_VA_GPIO + 0x520) +#define S5PV210_MP23_BASE (S5P_VA_GPIO + 0x540) +#define S5PV210_MP24_BASE (S5P_VA_GPIO + 0x560) +#define S5PV210_MP25_BASE (S5P_VA_GPIO + 0x580) +#define S5PV210_MP26_BASE (S5P_VA_GPIO + 0x5A0) +#define S5PV210_MP27_BASE (S5P_VA_GPIO + 0x5C0) +#define S5PV210_MP28_BASE (S5P_VA_GPIO + 0x5E0) +#define S5PV210_ETC0_BASE (S5P_VA_GPIO + 0x600) +#define S5PV210_ETC1_BASE (S5P_VA_GPIO + 0x620) +#define S5PV210_ETC2_BASE (S5P_VA_GPIO + 0x640) +#define S5PV210_ETC4_BASE (S5P_VA_GPIO + 0x660) + +#define S5PV210_GPA0_INT_CON (S5P_VA_GPIO + 0x700) +#define S5PV210_GPA0_INT_FLTCON0 (S5P_VA_GPIO + 0x800) +#define S5PV210_GPA0_INT_FLTCON1 (S5P_VA_GPIO + 0x804) +#define S5PV210_GPA0_INT_MASK (S5P_VA_GPIO + 0x900) +#define S5PV210_GPA0_INT_PEND (S5P_VA_GPIO + 0xA00) +#define S5PV210_GPA0_INT_FIXPRI (S5P_VA_GPIO + 0xB14) + +#define S5PV210_GPA1_INT_CON (S5P_VA_GPIO + 0x704) +#define S5PV210_GPA1_INT_FLTCON0 (S5P_VA_GPIO + 0x808) +#define S5PV210_GPA1_INT_FLTCON1 (S5P_VA_GPIO + 0x80C) +#define S5PV210_GPA1_INT_MASK (S5P_VA_GPIO + 0x904) +#define S5PV210_GPA1_INT_PEND (S5P_VA_GPIO + 0xA04) +#define S5PV210_GPA1_INT_FIXPRI (S5P_VA_GPIO + 0xB18) + +#define S5PV210_GPB_INT_CON (S5P_VA_GPIO + 0x708) +#define S5PV210_GPB_INT_FLTCON0 (S5P_VA_GPIO + 0x810) +#define S5PV210_GPB_INT_FLTCON1 (S5P_VA_GPIO + 0x814) +#define S5PV210_GPB_INT_MASK (S5P_VA_GPIO + 0x908) +#define S5PV210_GPB_INT_PEND (S5P_VA_GPIO + 0xA08) +#define S5PV210_GPB_INT_FIXPRI (S5P_VA_GPIO + 0xB1C) + +#define S5PV210_GPC0_INT_CON (S5P_VA_GPIO + 0x70C) +#define S5PV210_GPC0_INT_FLTCON0 (S5P_VA_GPIO + 0x818) +#define S5PV210_GPC0_INT_FLTCON1 (S5P_VA_GPIO + 0x81C) +#define S5PV210_GPC0_INT_MASK (S5P_VA_GPIO + 0x90C) +#define S5PV210_GPC0_INT_PEND (S5P_VA_GPIO + 0xA0C) +#define S5PV210_GPC0_INT_FIXPRI (S5P_VA_GPIO + 0xB20) + +#define S5PV210_GPC1_INT_CON (S5P_VA_GPIO + 0x710) +#define S5PV210_GPC1_INT_FLTCON0 (S5P_VA_GPIO + 0x820) +#define S5PV210_GPC1_INT_FLTCON1 (S5P_VA_GPIO + 0x824) +#define S5PV210_GPC1_INT_MASK (S5P_VA_GPIO + 0x910) +#define S5PV210_GPC1_INT_PEND (S5P_VA_GPIO + 0xA10) +#define S5PV210_GPC1_INT_FIXPRI (S5P_VA_GPIO + 0xB24) + +#define S5PV210_GPD0_INT_CON (S5P_VA_GPIO + 0x714) +#define S5PV210_GPD0_INT_FLTCON0 (S5P_VA_GPIO + 0x828) +#define S5PV210_GPD0_INT_FLTCON1 (S5P_VA_GPIO + 0x82C) +#define S5PV210_GPD0_INT_MASK (S5P_VA_GPIO + 0x914) +#define S5PV210_GPD0_INT_PEND (S5P_VA_GPIO + 0xA14) +#define S5PV210_GPD0_INT_FIXPRI (S5P_VA_GPIO + 0xB28) + +#define S5PV210_GPD1_INT_CON (S5P_VA_GPIO + 0x718) +#define S5PV210_GPD1_INT_FLTCON0 (S5P_VA_GPIO + 0x830) +#define S5PV210_GPD1_INT_FLTCON1 (S5P_VA_GPIO + 0x834) +#define S5PV210_GPD1_INT_MASK (S5P_VA_GPIO + 0x918) +#define S5PV210_GPD1_INT_PEND (S5P_VA_GPIO + 0xA18) +#define S5PV210_GPD1_INT_FIXPRI (S5P_VA_GPIO + 0xB2C) + +#define S5PV210_GPE0_INT_CON (S5P_VA_GPIO + 0x71C) +#define S5PV210_GPE0_INT_FLTCON0 (S5P_VA_GPIO + 0x838) +#define S5PV210_GPE0_INT_FLTCON1 (S5P_VA_GPIO + 0x83C) +#define S5PV210_GPE0_INT_MASK (S5P_VA_GPIO + 0x91C) +#define S5PV210_GPE0_INT_PEND (S5P_VA_GPIO + 0xA1C) +#define S5PV210_GPE0_INT_FIXPRI (S5P_VA_GPIO + 0xB30) + +#define S5PV210_GPE1_INT_CON (S5P_VA_GPIO + 0x720) +#define S5PV210_GPE1_INT_FLTCON0 (S5P_VA_GPIO + 0x840) +#define S5PV210_GPE1_INT_FLTCON1 (S5P_VA_GPIO + 0x844) +#define S5PV210_GPE1_INT_MASK (S5P_VA_GPIO + 0x920) +#define S5PV210_GPE1_INT_PEND (S5P_VA_GPIO + 0xA20) +#define S5PV210_GPE1_INT_FIXPRI (S5P_VA_GPIO + 0xB34) + +#define S5PV210_GPF0_INT_CON (S5P_VA_GPIO + 0x724) +#define S5PV210_GPF0_INT_FLTCON0 (S5P_VA_GPIO + 0x848) +#define S5PV210_GPF0_INT_FLTCON1 (S5P_VA_GPIO + 0x84C) +#define S5PV210_GPF0_INT_MASK (S5P_VA_GPIO + 0x924) +#define S5PV210_GPF0_INT_PEND (S5P_VA_GPIO + 0xA24) +#define S5PV210_GPF0_INT_FIXPRI (S5P_VA_GPIO + 0xB38) + +#define S5PV210_GPF1_INT_CON (S5P_VA_GPIO + 0x728) +#define S5PV210_GPF1_INT_FLTCON0 (S5P_VA_GPIO + 0x850) +#define S5PV210_GPF1_INT_FLTCON1 (S5P_VA_GPIO + 0x854) +#define S5PV210_GPF1_INT_MASK (S5P_VA_GPIO + 0x928) +#define S5PV210_GPF1_INT_PEND (S5P_VA_GPIO + 0xA28) +#define S5PV210_GPF1_INT_FIXPRI (S5P_VA_GPIO + 0xB3C) + +#define S5PV210_GPF2_INT_CON (S5P_VA_GPIO + 0x72C) +#define S5PV210_GPF2_INT_FLTCON0 (S5P_VA_GPIO + 0x858) +#define S5PV210_GPF2_INT_FLTCON1 (S5P_VA_GPIO + 0x85C) +#define S5PV210_GPF2_INT_MASK (S5P_VA_GPIO + 0x92C) +#define S5PV210_GPF2_INT_PEND (S5P_VA_GPIO + 0xA2C) +#define S5PV210_GPF2_INT_FIXPRI (S5P_VA_GPIO + 0xB40) + +#define S5PV210_GPF3_INT_CON (S5P_VA_GPIO + 0x730) +#define S5PV210_GPF3_INT_FLTCON0 (S5P_VA_GPIO + 0x860) +#define S5PV210_GPF3_INT_FLTCON1 (S5P_VA_GPIO + 0x864) +#define S5PV210_GPF3_INT_MASK (S5P_VA_GPIO + 0x930) +#define S5PV210_GPF3_INT_PEND (S5P_VA_GPIO + 0xA30) +#define S5PV210_GPF3_INT_FIXPRI (S5P_VA_GPIO + 0xB44) + +#define S5PV210_GPG0_INT_CON (S5P_VA_GPIO + 0x734) +#define S5PV210_GPG0_INT_FLTCON0 (S5P_VA_GPIO + 0x868) +#define S5PV210_GPG0_INT_FLTCON1 (S5P_VA_GPIO + 0x86C) +#define S5PV210_GPG0_INT_MASK (S5P_VA_GPIO + 0x934) +#define S5PV210_GPG0_INT_PEND (S5P_VA_GPIO + 0xA34) +#define S5PV210_GPG0_INT_FIXPRI (S5P_VA_GPIO + 0xB48) + +#define S5PV210_GPG1_INT_CON (S5P_VA_GPIO + 0x738) +#define S5PV210_GPG1_INT_FLTCON0 (S5P_VA_GPIO + 0x870) +#define S5PV210_GPG1_INT_FLTCON1 (S5P_VA_GPIO + 0x874) +#define S5PV210_GPG1_INT_MASK (S5P_VA_GPIO + 0x938) +#define S5PV210_GPG1_INT_PEND (S5P_VA_GPIO + 0xA38) +#define S5PV210_GPG1_INT_FIXPRI (S5P_VA_GPIO + 0xB4C) + +#define S5PV210_GPG2_INT_CON (S5P_VA_GPIO + 0x73C) +#define S5PV210_GPG2_INT_FLTCON0 (S5P_VA_GPIO + 0x878) +#define S5PV210_GPG2_INT_FLTCON1 (S5P_VA_GPIO + 0x87C) +#define S5PV210_GPG2_INT_MASK (S5P_VA_GPIO + 0x93C) +#define S5PV210_GPG2_INT_PEND (S5P_VA_GPIO + 0xA3C) +#define S5PV210_GPG2_INT_FIXPRI (S5P_VA_GPIO + 0xB50) + +#define S5PV210_GPG3_INT_CON (S5P_VA_GPIO + 0x740) +#define S5PV210_GPG3_INT_FLTCON0 (S5P_VA_GPIO + 0x880) +#define S5PV210_GPG3_INT_FLTCON1 (S5P_VA_GPIO + 0x884) +#define S5PV210_GPG3_INT_MASK (S5P_VA_GPIO + 0x940) +#define S5PV210_GPG3_INT_PEND (S5P_VA_GPIO + 0xA40) +#define S5PV210_GPG3_INT_FIXPRI (S5P_VA_GPIO + 0xB54) + +#define S5PV210_GPJ0_INT_CON (S5P_VA_GPIO + 0x744) +#define S5PV210_GPJ0_INT_FLTCON0 (S5P_VA_GPIO + 0x888) +#define S5PV210_GPJ0_INT_FLTCON1 (S5P_VA_GPIO + 0x88C) +#define S5PV210_GPJ0_INT_MASK (S5P_VA_GPIO + 0x944) +#define S5PV210_GPJ0_INT_PEND (S5P_VA_GPIO + 0xA44) +#define S5PV210_GPJ0_INT_FIXPRI (S5P_VA_GPIO + 0xB58) + +#define S5PV210_GPJ1_INT_CON (S5P_VA_GPIO + 0x748) +#define S5PV210_GPJ1_INT_FLTCON0 (S5P_VA_GPIO + 0x890) +#define S5PV210_GPJ1_INT_FLTCON1 (S5P_VA_GPIO + 0x894) +#define S5PV210_GPJ1_INT_MASK (S5P_VA_GPIO + 0x948) +#define S5PV210_GPJ1_INT_PEND (S5P_VA_GPIO + 0xA48) +#define S5PV210_GPJ1_INT_FIXPRI (S5P_VA_GPIO + 0xB5C) + +#define S5PV210_GPJ2_INT_CON (S5P_VA_GPIO + 0x74C) +#define S5PV210_GPJ2_INT_FLTCON0 (S5P_VA_GPIO + 0x898) +#define S5PV210_GPJ2_INT_FLTCON1 (S5P_VA_GPIO + 0x89C) +#define S5PV210_GPJ2_INT_MASK (S5P_VA_GPIO + 0x94C) +#define S5PV210_GPJ2_INT_PEND (S5P_VA_GPIO + 0xA4C) +#define S5PV210_GPJ2_INT_FIXPRI (S5P_VA_GPIO + 0xB60) + +#define S5PV210_GPJ3_INT_CON (S5P_VA_GPIO + 0x750) +#define S5PV210_GPJ3_INT_FLTCON0 (S5P_VA_GPIO + 0x8A0) +#define S5PV210_GPJ3_INT_FLTCON1 (S5P_VA_GPIO + 0x8A4) +#define S5PV210_GPJ3_INT_MASK (S5P_VA_GPIO + 0x950) +#define S5PV210_GPJ3_INT_PEND (S5P_VA_GPIO + 0xA50) +#define S5PV210_GPJ3_INT_FIXPRI (S5P_VA_GPIO + 0xB64) + +#define S5PV210_GPJ4_INT_CON (S5P_VA_GPIO + 0x754) +#define S5PV210_GPJ4_INT_FLTCON0 (S5P_VA_GPIO + 0x8A8) +#define S5PV210_GPJ4_INT_FLTCON1 (S5P_VA_GPIO + 0x8AC) +#define S5PV210_GPJ4_INT_MASK (S5P_VA_GPIO + 0x954) +#define S5PV210_GPJ4_INT_PEND (S5P_VA_GPIO + 0xA54) +#define S5PV210_GPJ4_INT_FIXPRI (S5P_VA_GPIO + 0xB68) + +#define S5PV210_EXT_INT_GRPPRI (S5P_VA_GPIO + 0xB00) +#define S5PV210_EXT_INT_PRIO (S5P_VA_GPIO + 0xB04) +#define S5PV210_EXT_INT_SVC (S5P_VA_GPIO + 0xB08) +#define S5PV210_EXT_INT_SVC_PND (S5P_VA_GPIO + 0xB0C) +#define S5PV210_EXT_INT_GRPFIXPRI (S5P_VA_GPIO + 0xB10) + #define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00) #define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4)) #define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) -#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4)) +#define S5P_EINT_FLTCON(x,y) (S5PV210_EINT30FLTCON0 + ((x) * 0x8) + ((y) * 0x4)) #define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00) #define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4)) @@ -29,8 +248,16 @@ #define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) +#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq)-IRQ_EINT0)\ + : (irq-S5P_IRQ_EINT_BASE)) + #define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) +#define eint_conf_reg(irq) ((eint_offset(irq)) >> 3) +#define eint_filt_reg(irq) ((eint_offset(irq)) >> 2) +#define eint_mask_reg(irq) ((eint_offset(irq)) >> 3) +#define eint_pend_reg(irq) ((eint_offset(irq)) >> 3) + #define EINT_MODE S3C_GPIO_SFN(0xf) #define EINT_GPIO_0(x) S5PV210_GPH0(x) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h index 5c3b104..e3b86f1 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h @@ -16,4 +16,10 @@ #include <asm/hardware/vic.h> #include <mach/map.h> +/* interrupt controller */ +#define S5P_VIC0REG(x) ((x) + S5P_VA_VIC0) +#define S5P_VIC1REG(x) ((x) + S5P_VA_VIC1) +#define S5P_VIC2REG(x) ((x) + S5P_VA_VIC2) +#define S5P_VIC3REG(x) ((x) + S5P_VA_VIC3) + #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-mem.h b/arch/arm/mach-s5pv210/include/mach/regs-mem.h new file mode 100644 index 0000000..1c79d54 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-mem.h @@ -0,0 +1,28 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/regs-mem.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Memory Control register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MEM_H +#define __ASM_ARCH_REGS_MEM_H __FILE__ + +#include <mach/map.h> + +#define S5P_MEMREG(x) (S5P_VA_SROMC + (x)) + +#define S5P_SROM_BW S5P_MEMREG(0x00) +#define S5P_SROM_BC0 S5P_MEMREG(0x04) +#define S5P_SROM_BC1 S5P_MEMREG(0x08) +#define S5P_SROM_BC2 S5P_MEMREG(0x0C) +#define S5P_SROM_BC3 S5P_MEMREG(0x10) +#define S5P_SROM_BC4 S5P_MEMREG(0x14) +#define S5P_SROM_BC5 S5P_MEMREG(0x18) + +#endif /* __ASM_ARCH_REGS_MEM_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/sec_switch.h b/arch/arm/mach-s5pv210/include/mach/sec_switch.h new file mode 100644 index 0000000..c1e8f69 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/sec_switch.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2010 Samsung Electronics, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_SEC_SWITCH_H +#define __ASM_ARCH_SEC_SWITCH_H + +struct sec_switch_platform_data { + void (*set_vbus_status) (u8 mode); + void (*set_usb_gadget_vbus) (bool en); + int (*get_cable_status) (void); + int (*get_phy_init_status) (void); +}; + +#define SWITCH_MODEM 0 +#define SWITCH_PDA 1 + +#define USB_VBUS_ALL_OFF 0 +#define USB_VBUS_CP_ON 1 +#define USB_VBUS_AP_ON 2 +#define USB_VBUS_ALL_ON 3 + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/tick.h b/arch/arm/mach-s5pv210/include/mach/tick.h index 7993b36..9fc5a8d 100644 --- a/arch/arm/mach-s5pv210/include/mach/tick.h +++ b/arch/arm/mach-s5pv210/include/mach/tick.h @@ -21,6 +21,12 @@ static inline u32 s3c24xx_ostimer_pending(void) return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); } +static inline u32 s5p_ostimer_pending(void) +{ + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_SYSTIMER - S5P_IRQ_VIC0(0))); +} + #define TICK_MAX (0xffffffff) #endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h index a6c659d..223e21a 100644 --- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h +++ b/arch/arm/mach-s5pv210/include/mach/vmalloc.h @@ -17,6 +17,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H __FILE__ -#define VMALLOC_END 0xF6000000UL +#define VMALLOC_END (0xFC000000) #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5pv210/init.c b/arch/arm/mach-s5pv210/init.c index 4865ae2..aca3789 100644 --- a/arch/arm/mach-s5pv210/init.c +++ b/arch/arm/mach-s5pv210/init.c @@ -20,7 +20,7 @@ static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = { [0] = { - .name = "pclk", + .name = "sclk", .divisor = 1, .min_baud = 0, .max_baud = 0, diff --git a/arch/arm/mach-s5pv210/level.c b/arch/arm/mach-s5pv210/level.c new file mode 100644 index 0000000..12cf8bb --- /dev/null +++ b/arch/arm/mach-s5pv210/level.c @@ -0,0 +1,171 @@ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/miscdevice.h> +#include <linux/kernel.h> +#include <linux/fs.h> +#include <linux/errno.h> +#include <linux/types.h> +#include <linux/fcntl.h> + +#include <asm/uaccess.h> + +#define LEVEL_DEV_NAME "level" + +#define LEVEL_DEV_IOCTL_CMD 0xee + +#define LEVEL_DEV_UNSET_UPLOAD _IO(LEVEL_DEV_IOCTL_CMD, 0x1) +#define LEVEL_DEV_SET_AUTOTEST _IO(LEVEL_DEV_IOCTL_CMD, 0x2) +#define LEVEL_DEV_SET_DEBUGLEVEL _IO(LEVEL_DEV_IOCTL_CMD, 0x3) +#define LEVEL_DEV_GET_DEBUGLEVEL _IO(LEVEL_DEV_IOCTL_CMD, 0x4) + +#define KERNEL_SEC_DEBUG_LEVEL_LOW 0xA0A0 +#define KERNEL_SEC_DEBUG_LEVEL_MID 0xB0B0 +#define KERNEL_SEC_DEBUG_LEVEL_HIGH 0xC0C0 +#define FAKED_DEBUG_LEVEL KERNEL_SEC_DEBUG_LEVEL_HIGH + + +static unsigned int get_debug_level(void); + +static ssize_t show_control(struct device *d, + struct device_attribute *attr, char *buf); +static ssize_t store_control(struct device *d, + struct device_attribute *attr, const char *buf, size_t count); + +static DEVICE_ATTR(control, S_IRUGO | S_IWUGO, show_control, store_control); + +static struct attribute *levelctl_attributes[] = { + &dev_attr_control.attr, + NULL +}; + +static const struct attribute_group levelctl_group = { + .attrs = levelctl_attributes, +}; + +static ssize_t show_control(struct device *d, + struct device_attribute *attr, char *buf) +{ + char *p = buf; + unsigned int val; + + val = get_debug_level(); + + p += sprintf(p, "0x%4x\n",val); + + return p - buf; +} + +static ssize_t store_control(struct device *d, + struct device_attribute *attr, const char *buf, size_t count) +{ + + if(!strncmp(buf, "clear", 5)) { + // clear upload magic number + printk("fake_level: %s clear", __func__); + //kernel_sec_clear_upload_magic_number(); + return count; + } + + if(!strncmp(buf, "autotest", 8)) { + // set auto test + printk("fake_level: %s autotest", __func__); + //kernel_sec_set_autotest(); + return count; + } + + if(!strncmp(buf, "set", 3)) { + // set debug level + printk("fake_level: %s set", __func__); + //set_debug_level(); + return count; + } + +return count; +} + +static int level_open(struct inode *inode, struct file *filp) +{ + printk("level Device open\n"); + + return 0; +} + +static int level_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + unsigned int val; + + switch (cmd) { + case LEVEL_DEV_UNSET_UPLOAD: + printk("fake_level: %s LEVEL_DEV_UNSET_UPLOAD", __func__); + //kernel_sec_clear_upload_magic_number(); + return 0; + + case LEVEL_DEV_SET_AUTOTEST: + printk("fake_level: %s LEVEL_DEV_SET_AUTOTEST", __func__); + //kernel_sec_set_autotest(); + return 0; + + case LEVEL_DEV_SET_DEBUGLEVEL: + printk("fake_level: %s LEVEL_DEV_SET_DEBUGLEVEL", __func__); + //set_debug_level(); + return 0; + + case LEVEL_DEV_GET_DEBUGLEVEL: + { + val = get_debug_level(); + return copy_to_user((unsigned int *)arg, &val, sizeof(val)); + } + default: + printk("Unknown Cmd: %x\n", cmd); + break; + } + return -ENOTSUPP; +} + +static unsigned int get_debug_level() +{ + return FAKED_DEBUG_LEVEL; +} + +static struct file_operations level_fops = +{ + .owner = THIS_MODULE, + .open = level_open, + .unlocked_ioctl = level_ioctl, +}; + +static struct miscdevice level_device = { + .minor = MISC_DYNAMIC_MINOR, + .name = LEVEL_DEV_NAME, + .fops = &level_fops, +}; + +/* init & cleanup. */ +static int __init level_init(void) +{ + int result; + + printk("level device init\n"); + + result = misc_register(&level_device); + if (result <0) + return result; + + result = sysfs_create_group(&level_device.this_device->kobj, &levelctl_group); + if (result < 0) { + printk("failed to create sysfs files\n"); + } + + return 0; +} + +static void __exit level_exit(void) +{ + printk("level device exit\n"); + misc_deregister(&level_device); +} + +module_init(level_init); +module_exit(level_exit); + diff --git a/arch/arm/mach-s5pv210/mach-aries.c b/arch/arm/mach-s5pv210/mach-aries.c new file mode 100644 index 0000000..b4c1c11 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-aries.c @@ -0,0 +1,5699 @@ +/* linux/arch/arm/mach-s5pv210/mach-aries.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/gpio.h> +#include <linux/gpio_event.h> +#include <linux/videodev2.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/mfd/max8998.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/usb/ch9.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/clk.h> +#include <linux/usb/ch9.h> +#include <linux/input/cypress-touchkey.h> +#include <linux/input.h> +#include <linux/irq.h> +#include <linux/skbuff.h> +#include <linux/console.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/system.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/gpio.h> +#include <mach/gpio-aries.h> +#include <mach/adc.h> +#include <mach/param.h> +#include <mach/system.h> +#include <mach/sec_switch.h> +#ifdef CONFIG_SAMSUNG_FASCINATE +#include <mach/regs-gpio.h> +#endif + +#include <linux/usb/gadget.h> +#include <linux/fsa9480.h> +#include <linux/pn544.h> +#include <linux/notifier.h> +#include <linux/reboot.h> +#include <linux/wlan_plat.h> +#include <linux/mfd/wm8994/wm8994_pdata.h> + +#ifdef CONFIG_ANDROID_PMEM +#include <linux/android_pmem.h> +#endif + +#include <plat/media.h> +#include <mach/media.h> + +#ifdef CONFIG_S5PV210_POWER_DOMAIN +#include <mach/power-domain.h> +#endif +#include <mach/cpu-freq-v210.h> + +#include <media/ce147_platform.h> +#ifdef CONFIG_VIDEO_S5KA3DFX +#include <media/s5ka3dfx_platform.h> +#endif + +#include <plat/regs-serial.h> +#include <plat/s5pv210.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/fb.h> +#include <plat/mfc.h> +#include <plat/iic.h> +#include <plat/pm.h> +#include <plat/s5p-time.h> + +#include <plat/sdhci.h> +#include <plat/fimc.h> +#include <plat/jpeg.h> +#include <plat/clock.h> +#include <plat/regs-otg.h> + +#include <linux/gp2a.h> + +#include <linux/yas529.h> +#include <../../../drivers/video/samsung/s3cfb.h> +#include <linux/sec_jack.h> +#include <linux/input/mxt224.h> +#include <linux/max17040_battery.h> +#include <linux/mfd/max8998.h> +#include <linux/switch.h> + +#ifdef CONFIG_KERNEL_DEBUG_SEC +#include <linux/kernel_sec_common.h> +#endif + +#include "aries.h" + +#undef pr_debug +#define pr_debug pr_info + +struct class *sec_class; +EXPORT_SYMBOL(sec_class); + +struct device *switch_dev; +EXPORT_SYMBOL(switch_dev); + +void (*sec_set_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_set_param_value); + +void (*sec_get_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_get_param_value); + +#define KERNEL_REBOOT_MASK 0xFFFFFFFF +#define REBOOT_MODE_FAST_BOOT 7 + +#define PREALLOC_WLAN_SEC_NUM 4 +#define PREALLOC_WLAN_BUF_NUM 160 +#define PREALLOC_WLAN_SECTION_HEADER 24 + +#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512) +#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024) + +#define WLAN_SKB_BUF_NUM 16 + +static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM]; + +struct wifi_mem_prealloc { + void *mem_ptr; + unsigned long size; +}; + +static int aries_notifier_call(struct notifier_block *this, + unsigned long code, void *_cmd) +{ + int mode = REBOOT_MODE_NONE; + + if ((code == SYS_RESTART) && _cmd) { + if (!strcmp((char *)_cmd, "recovery")) + mode = 2; // It's not REBOOT_MODE_RECOVERY, blame Samsung + else + mode = REBOOT_MODE_NONE; + } + __raw_writel(mode, S5P_INFORM6); + + return NOTIFY_DONE; +} + +static struct notifier_block aries_reboot_notifier = { + .notifier_call = aries_notifier_call, +}; + +static void gps_gpio_init(void) +{ + struct device *gps_dev; + + gps_dev = device_create(sec_class, NULL, 0, NULL, "gps"); + if (IS_ERR(gps_dev)) { + pr_err("Failed to create device(gps)!\n"); + goto err; + } + + gpio_request(GPIO_GPS_nRST, "GPS_nRST"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_nRST, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_nRST, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_nRST, 1); + + gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_PWR_EN, 0); + + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + gpio_export(GPIO_GPS_nRST, 1); + gpio_export(GPIO_GPS_PWR_EN, 1); + + gpio_export_link(gps_dev, "GPS_nRST", GPIO_GPS_nRST); + gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN); + + err: + return; +} + +static void uart_switch_init(void) +{ + int ret; + struct device *uartswitch_dev; + + uartswitch_dev = device_create(sec_class, NULL, 0, NULL, "uart_switch"); + if (IS_ERR(uartswitch_dev)) { + pr_err("Failed to create device(uart_switch)!\n"); + return; + } + + ret = gpio_request(GPIO_UART_SEL, "UART_SEL"); + if (ret < 0) { + pr_err("Failed to request GPIO_UART_SEL!\n"); + return; + } + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_UART_SEL, 1); + + gpio_export(GPIO_UART_SEL, 1); + + gpio_export_link(uartswitch_dev, "UART_SEL", GPIO_UART_SEL); +} + +static void aries_switch_init(void) +{ + sec_class = class_create(THIS_MODULE, "sec"); + + if (IS_ERR(sec_class)) + pr_err("Failed to create class(sec)!\n"); + + switch_dev = device_create(sec_class, NULL, 0, NULL, "switch"); + + if (IS_ERR(switch_dev)) + pr_err("Failed to create device(switch)!\n"); +}; + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg aries_uartcfgs[] __initdata = { + { + .hwport = 0, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + .wake_peer = aries_bt_uart_wake_peer, + }, + { + .hwport = 1, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#ifndef CONFIG_FIQ_DEBUGGER + { + .hwport = 2, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#endif + { + .hwport = 3, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +}; + +#define S5PV210_LCD_WIDTH 480 +#define S5PV210_LCD_HEIGHT 800 + +static struct s3cfb_lcd s6e63m0 = { + .width = S5PV210_LCD_WIDTH, + .height = S5PV210_LCD_HEIGHT, + .p_width = 52, + .p_height = 86, + .bpp = 24, + .freq = 60, + + .timing = { + .h_fp = 16, + .h_bp = 16, + .h_sw = 2, + .v_fp = 28, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 1, + }, +}; + +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0 (12288 * SZ_1K) +// Disabled to save memory (we can't find where it's used) +//#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1 (9900 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2 (12288 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0 (14336 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (21504 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD (S5PV210_LCD_WIDTH * \ + S5PV210_LCD_HEIGHT * 4 * \ + (CONFIG_FB_S3C_NR_BUFFERS + \ + (CONFIG_FB_S3C_NUM_OVLY_WIN * \ + CONFIG_FB_S3C_NUM_BUF_OVLY_WIN))) +// Was 8M, but we're only using it to encode VGA jpegs +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG (4096 * SZ_1K) +#define S5PV210_ANDROID_PMEM_MEMSIZE_PMEM (5550 * SZ_1K) +#define S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 (3000 * SZ_1K) +#define S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_ADSP (1500 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_TEXTSTREAM (3000 * SZ_1K) + + +static struct s5p_media_device aries_media_devs[] = { + [0] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0, + .paddr = 0, + }, + [1] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1, + .paddr = 0, + }, + [2] = { + .id = S5P_MDEV_FIMC0, + .name = "fimc0", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0, + .paddr = 0, + }, +/* [3] = { + .id = S5P_MDEV_FIMC1, + .name = "fimc1", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1, + .paddr = 0, + },*/ + [4] = { + .id = S5P_MDEV_FIMC2, + .name = "fimc2", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2, + .paddr = 0, + }, + [5] = { + .id = S5P_MDEV_JPEG, + .name = "jpeg", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG, + .paddr = 0, + }, + [6] = { + .id = S5P_MDEV_FIMD, + .name = "fimd", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD, + .paddr = 0, + }, +#ifdef CONFIG_ANDROID_PMEM + [7] = { + .id = S5P_MDEV_PMEM, + .name = "pmem", + .bank = 0, + .memsize = S5PV210_ANDROID_PMEM_MEMSIZE_PMEM, + .paddr = 0, + }, + [8] = { + .id = S5P_MDEV_PMEM_GPU1, + .name = "pmem_gpu1", + .bank = 0, + .memsize = S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_GPU1, + .paddr = 0, + }, + [9] = { + .id = S5P_MDEV_PMEM_ADSP, + .name = "pmem_adsp", + .bank = 0, + .memsize = S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_ADSP, + .paddr = 0, + }, + [10] = { + .id = S5P_MDEV_TEXSTREAM, + .name = "s3c_bc", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_TEXTSTREAM, + .paddr = 0, + }, +#endif +}; + +#ifdef CONFIG_CPU_FREQ +static struct s5pv210_cpufreq_voltage smdkc110_cpufreq_volt[] = { + { + .freq = 1200000, + .varm = 1275000, + .vint = 1100000, + }, { + .freq = 1000000, + .varm = 1275000, + .vint = 1100000, + }, { + .freq = 800000, + .varm = 1200000, + .vint = 1100000, + }, { + .freq = 400000, + .varm = 1050000, + .vint = 1100000, + }, { + .freq = 200000, + .varm = 950000, + .vint = 1100000, + }, { + .freq = 100000, + .varm = 950000, + .vint = 1000000, + }, +}; + +static struct s5pv210_cpufreq_data smdkc110_cpufreq_plat = { + .volt = smdkc110_cpufreq_volt, + .size = ARRAY_SIZE(smdkc110_cpufreq_volt), +}; +#endif + +static struct regulator_consumer_supply ldo3_consumer[] = { + REGULATOR_SUPPLY("pd_io", "s3c-usbgadget") +}; + +#ifndef CONFIG_SAMSUNG_FASCINATE +static struct regulator_consumer_supply ldo5_consumer[] = { + REGULATOR_SUPPLY("vmmc", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo7_consumer[] = { + { .supply = "vlcd", }, +}; + +static struct regulator_consumer_supply ldo8_consumer[] = { + REGULATOR_SUPPLY("pd_core", "s3c-usbgadget"), + REGULATOR_SUPPLY("tvout", NULL), +}; + +static struct regulator_consumer_supply ldo11_consumer[] = { + { .supply = "cam_af", }, +}; + +static struct regulator_consumer_supply ldo12_consumer[] = { + { .supply = "cam_sensor", }, +}; + +static struct regulator_consumer_supply ldo13_consumer[] = { + { .supply = "vga_vddio", }, +}; + +static struct regulator_consumer_supply ldo14_consumer[] = { + { .supply = "vga_dvdd", }, +}; + +static struct regulator_consumer_supply ldo15_consumer[] = { + { .supply = "cam_isp_host", }, +}; + +static struct regulator_consumer_supply ldo16_consumer[] = { + { .supply = "vga_avdd", }, +}; + +static struct regulator_consumer_supply ldo17_consumer[] = { + { .supply = "vcc_lcd", }, +}; + +static struct regulator_consumer_supply buck1_consumer[] = { + { .supply = "vddarm", }, +}; + +static struct regulator_consumer_supply buck2_consumer[] = { + { .supply = "vddint", }, +}; + +static struct regulator_consumer_supply buck4_consumer[] = { + { .supply = "cam_isp_core", }, +}; + +static struct regulator_init_data aries_ldo2_data = { + .constraints = { + .name = "VALIVE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data aries_ldo3_data = { + .constraints = { + .name = "VUSB_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), + .consumer_supplies = ldo3_consumer, +}; + +static struct regulator_init_data aries_ldo4_data = { + .constraints = { + .name = "VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, +}; + +#ifndef CONFIG_SAMSUNG_FASCINATE +static struct regulator_init_data aries_ldo5_data = { + .constraints = { + .name = "VTF_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo5_consumer), + .consumer_supplies = ldo5_consumer, +}; +#endif + +static struct regulator_init_data aries_ldo7_data = { + .constraints = { + .name = "VLCD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 0, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), + .consumer_supplies = ldo7_consumer, +}; + +static struct regulator_init_data aries_ldo8_data = { + .constraints = { + .name = "VUSB_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), + .consumer_supplies = ldo8_consumer, +}; + +static struct regulator_init_data aries_ldo9_data = { + .constraints = { + .name = "VCC_2.8V_PDA", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aries_ldo11_data = { + .constraints = { + .name = "CAM_AF_3.0V", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), + .consumer_supplies = ldo11_consumer, +}; + +static struct regulator_init_data aries_ldo12_data = { + .constraints = { + .name = "CAM_SENSOR_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo12_consumer), + .consumer_supplies = ldo12_consumer, +}; + +static struct regulator_init_data aries_ldo13_data = { + .constraints = { + .name = "VGA_VDDIO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo13_consumer), + .consumer_supplies = ldo13_consumer, +}; + +static struct regulator_init_data aries_ldo14_data = { + .constraints = { + .name = "VGA_DVDD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), + .consumer_supplies = ldo14_consumer, +}; + +static struct regulator_init_data aries_ldo15_data = { + .constraints = { + .name = "CAM_ISP_HOST_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo15_consumer), + .consumer_supplies = ldo15_consumer, +}; + +static struct regulator_init_data aries_ldo16_data = { + .constraints = { + .name = "VGA_AVDD_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo16_consumer), + .consumer_supplies = ldo16_consumer, +}; + +static struct regulator_init_data aries_ldo17_data = { + .constraints = { + .name = "VCC_3.0V_LCD", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .always_on = 0, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), + .consumer_supplies = ldo17_consumer, +}; + +static struct regulator_init_data aries_buck1_data = { + .constraints = { + .name = "VDD_ARM", + .min_uV = 750000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1250000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), + .consumer_supplies = buck1_consumer, +}; + +static struct regulator_init_data aries_buck2_data = { + .constraints = { + .name = "VDD_INT", + .min_uV = 750000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1100000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), + .consumer_supplies = buck2_consumer, +}; + +static struct regulator_init_data aries_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aries_buck4_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck4_consumer), + .consumer_supplies = buck4_consumer, +}; + +static struct max8998_regulator_data aries_regulators[] = { + { MAX8998_LDO2, &aries_ldo2_data }, + { MAX8998_LDO3, &aries_ldo3_data }, + { MAX8998_LDO4, &aries_ldo4_data }, +#ifndef CONFIG_SAMSUNG_FASCINATE + { MAX8998_LDO5, &aries_ldo5_data }, +#endif + { MAX8998_LDO7, &aries_ldo7_data }, + { MAX8998_LDO8, &aries_ldo8_data }, + { MAX8998_LDO9, &aries_ldo9_data }, + { MAX8998_LDO11, &aries_ldo11_data }, + { MAX8998_LDO12, &aries_ldo12_data }, + { MAX8998_LDO13, &aries_ldo13_data }, + { MAX8998_LDO14, &aries_ldo14_data }, + { MAX8998_LDO15, &aries_ldo15_data }, + { MAX8998_LDO16, &aries_ldo16_data }, + { MAX8998_LDO17, &aries_ldo17_data }, + { MAX8998_BUCK1, &aries_buck1_data }, + { MAX8998_BUCK2, &aries_buck2_data }, + { MAX8998_BUCK3, &aries_buck3_data }, + { MAX8998_BUCK4, &aries_buck4_data }, +}; + +static struct max8998_adc_table_data temper_table[] = { +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { 206, 700 }, + { 220, 690 }, + { 234, 680 }, + { 248, 670 }, + { 262, 660 }, + { 276, 650 }, + { 290, 640 }, + { 304, 630 }, + { 314, 620 }, + { 323, 610 }, + { 337, 600 }, + { 351, 590 }, + { 364, 580 }, + { 379, 570 }, + { 395, 560 }, + { 408, 550 }, + { 423, 540 }, + { 438, 530 }, + { 453, 520 }, + { 465, 510 }, + { 478, 500 }, + { 495, 490 }, + { 513, 480 }, + { 528, 470 }, + { 544, 460 }, + { 564, 450 }, + { 584, 440 }, + { 602, 430 }, + { 621, 420 }, + { 643, 410 }, + { 665, 400 }, + { 682, 390 }, + { 702, 380 }, + { 729, 370 }, + { 752, 360 }, + { 775, 350 }, + { 798, 340 }, + { 821, 330 }, + { 844, 320 }, + { 867, 310 }, + { 890, 300 }, + { 913, 290 }, + { 936, 280 }, + { 959, 270 }, + { 982, 260 }, + { 1005, 250 }, + { 1028, 240 }, + { 1051, 230 }, + { 1074, 220 }, + { 1097, 210 }, + { 1120, 200 }, + { 1143, 190 }, + { 1166, 180 }, + { 1189, 170 }, + { 1212, 160 }, + { 1235, 150 }, + { 1258, 140 }, + { 1281, 130 }, + { 1304, 120 }, + { 1327, 110 }, + { 1350, 100 }, + { 1373, 90 }, + { 1396, 80 }, + { 1419, 70 }, + { 1442, 60 }, + { 1465, 50 }, + { 1484, 40 }, + { 1504, 30 }, + { 1526, 20 }, + { 1543, 10 }, // +10 + { 1567, 0 }, // 10 + { 1569, -10 }, + { 1592, -20 }, + { 1613, -30 }, + { 1633, -40 }, + { 1653, -50 }, + { 1654, -60 }, + { 1671, -70 }, + { 1691, -80 }, + { 1711, -90 }, + { 1731, -100}, // 0 +#else + { 264, 650 }, + { 275, 640 }, + { 286, 630 }, + { 293, 620 }, + { 299, 610 }, + { 306, 600 }, + { 324, 590 }, + { 341, 580 }, + { 354, 570 }, + { 368, 560 }, + { 381, 550 }, + { 396, 540 }, + { 411, 530 }, + { 427, 520 }, + { 442, 510 }, + { 457, 500 }, + { 472, 490 }, + { 487, 480 }, + { 503, 470 }, + { 518, 460 }, + { 533, 450 }, + { 554, 440 }, + { 574, 430 }, + { 595, 420 }, + { 615, 410 }, + { 636, 400 }, + { 656, 390 }, + { 677, 380 }, + { 697, 370 }, + { 718, 360 }, + { 738, 350 }, + { 761, 340 }, + { 784, 330 }, + { 806, 320 }, + { 829, 310 }, + { 852, 300 }, + { 875, 290 }, + { 898, 280 }, + { 920, 270 }, + { 943, 260 }, + { 966, 250 }, + { 990, 240 }, + { 1013, 230 }, + { 1037, 220 }, + { 1060, 210 }, + { 1084, 200 }, + { 1108, 190 }, + { 1131, 180 }, + { 1155, 170 }, + { 1178, 160 }, + { 1202, 150 }, + { 1226, 140 }, + { 1251, 130 }, + { 1275, 120 }, + { 1299, 110 }, + { 1324, 100 }, + { 1348, 90 }, + { 1372, 80 }, + { 1396, 70 }, + { 1421, 60 }, + { 1445, 50 }, + { 1468, 40 }, + { 1491, 30 }, + { 1513, 20 }, + { 1536, 10 }, + { 1559, 0 }, + { 1577, -10 }, + { 1596, -20 }, + { 1614, -30 }, + { 1619, -40 }, + { 1632, -50 }, + { 1658, -60 }, + { 1667, -70 }, +#endif +}; +struct max8998_charger_callbacks *charger_callbacks; +static enum cable_type_t set_cable_status; + +static void max8998_charger_register_callbacks( + struct max8998_charger_callbacks *ptr) +{ + charger_callbacks = ptr; + /* if there was a cable status change before the charger was + ready, send this now */ + if ((set_cable_status != 0) && charger_callbacks && charger_callbacks->set_cable) + charger_callbacks->set_cable(charger_callbacks, set_cable_status); +} + +static struct max8998_charger_data aries_charger = { + .register_callbacks = &max8998_charger_register_callbacks, + .adc_table = temper_table, + .adc_array_size = ARRAY_SIZE(temper_table), +}; + +static struct max8998_platform_data max8998_pdata = { + .num_regulators = ARRAY_SIZE(aries_regulators), + .regulators = aries_regulators, + .charger = &aries_charger, + /* Preloads must be in increasing order of voltage value */ + .buck1_voltage4 = 950000, + .buck1_voltage3 = 1050000, + .buck1_voltage2 = 1200000, + .buck1_voltage1 = 1275000, + .buck2_voltage2 = 1000000, + .buck2_voltage1 = 1100000, + .buck1_set1 = GPIO_BUCK_1_EN_A, + .buck1_set2 = GPIO_BUCK_1_EN_B, + .buck2_set3 = GPIO_BUCK_2_EN, + .buck1_default_idx = 1, + .buck2_default_idx = 0, +}; + +struct platform_device sec_device_dpram = { + .name = "dpram-device", + .id = -1, +}; + +static void tl2796_cfg_gpio(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < 8; i++) + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + + for (i = 0; i < 8; i++) + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + + for (i = 0; i < 8; i++) + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_SFN(2)); + + for (i = 0; i < 4; i++) + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_SFN(2)); + + /* mDNIe SEL: why we shall write 0x2 ? */ +#ifdef CONFIG_FB_S3C_MDNIE + writel(0x1, S5P_MDNIE_SEL); +#else + writel(0x2, S5P_MDNIE_SEL); +#endif + + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_NONE); +} + +void lcd_cfg_gpio_early_suspend(void) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_OUTPUT); + gpio_set_value(S5PV210_GPF0(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_OUTPUT); + gpio_set_value(S5PV210_GPF1(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_OUTPUT); + gpio_set_value(S5PV210_GPF2(i), 0); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_OUTPUT); + gpio_set_value(S5PV210_GPF3(i), 0); + } + + gpio_set_value(GPIO_MLCD_RST, 0); + + gpio_set_value(GPIO_DISPLAY_CS, 0); + gpio_set_value(GPIO_DISPLAY_CLK, 0); + gpio_set_value(GPIO_DISPLAY_SI, 0); + + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_DOWN); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_DOWN); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_DOWN); +} +EXPORT_SYMBOL(lcd_cfg_gpio_early_suspend); + +void lcd_cfg_gpio_late_resume(void) +{ + +} +EXPORT_SYMBOL(lcd_cfg_gpio_late_resume); + +static int tl2796_reset_lcd(struct platform_device *pdev) +{ + int err; + + err = gpio_request(GPIO_MLCD_RST, "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request MP0(5) for " + "lcd reset control\n"); + return err; + } + + gpio_direction_output(GPIO_MLCD_RST, 1); + msleep(10); + + gpio_set_value(GPIO_MLCD_RST, 0); + msleep(10); + + gpio_set_value(GPIO_MLCD_RST, 1); + msleep(10); + + gpio_free(GPIO_MLCD_RST); + + return 0; +} + +static int tl2796_backlight_on(struct platform_device *pdev) +{ + return 0; +} + +static struct s3c_platform_fb tl2796_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &s6e63m0, + .cfg_gpio = tl2796_cfg_gpio, + .backlight_on = tl2796_backlight_on, + .reset_lcd = tl2796_reset_lcd, +}; + +#define LCD_BUS_NUM 3 +#define DISPLAY_CS S5PV210_MP01(1) +#define SUB_DISPLAY_CS S5PV210_MP01(2) +#define DISPLAY_CLK S5PV210_MP04(1) +#define DISPLAY_SI S5PV210_MP04(3) + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "tl2796", + .platform_data = &aries_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +static struct spi_gpio_platform_data tl2796_spi_gpio_data = { + .sck = DISPLAY_CLK, + .mosi = DISPLAY_SI, + .miso = -1, + .num_chipselect = 2, +}; + +static struct platform_device s3c_device_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s3c_device_fb.dev, + .platform_data = &tl2796_spi_gpio_data, + }, +}; + +static struct i2c_gpio_platform_data i2c4_platdata = { + .sda_pin = GPIO_AP_SDA_18V, + .scl_pin = GPIO_AP_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device aries_s3c_device_i2c4 = { + .name = "i2c-gpio", + .id = 4, + .dev.platform_data = &i2c4_platdata, +}; + +static struct i2c_gpio_platform_data i2c5_platdata = { + .sda_pin = GPIO_AP_SDA_28V, + .scl_pin = GPIO_AP_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device aries_s3c_device_i2c5 = { + .name = "i2c-gpio", + .id = 5, + .dev.platform_data = &i2c5_platdata, +}; + +static struct i2c_gpio_platform_data i2c6_platdata = { + .sda_pin = GPIO_AP_PMIC_SDA, + .scl_pin = GPIO_AP_PMIC_SCL, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device aries_s3c_device_i2c6 = { + .name = "i2c-gpio", + .id = 6, + .dev.platform_data = &i2c6_platdata, +}; + +static struct i2c_gpio_platform_data i2c7_platdata = { + .sda_pin = GPIO_USB_SDA_28V, + .scl_pin = GPIO_USB_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device aries_s3c_device_i2c7 = { + .name = "i2c-gpio", + .id = 7, + .dev.platform_data = &i2c7_platdata, +}; +// For FM radio +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) +static struct i2c_gpio_platform_data i2c8_platdata = { + .sda_pin = GPIO_FM_SDA_28V, + .scl_pin = GPIO_FM_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c8 = { + .name = "i2c-gpio", + .id = 8, + .dev.platform_data = &i2c8_platdata, +}; +#endif + +static struct i2c_gpio_platform_data i2c9_platdata = { + .sda_pin = FUEL_SDA_18V, + .scl_pin = FUEL_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c9 = { + .name = "i2c-gpio", + .id = 9, + .dev.platform_data = &i2c9_platdata, +}; + +static struct i2c_gpio_platform_data i2c10_platdata = { + .sda_pin = _3_TOUCH_SDA_28V, + .scl_pin = _3_TOUCH_SCL_28V, + .udelay = 0, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c10 = { + .name = "i2c-gpio", + .id = 10, + .dev.platform_data = &i2c10_platdata, +}; + +static struct i2c_gpio_platform_data i2c11_platdata = { + .sda_pin = GPIO_ALS_SDA_28V, + .scl_pin = GPIO_ALS_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c11 = { + .name = "i2c-gpio", + .id = 11, + .dev.platform_data = &i2c11_platdata, +}; + +static struct i2c_gpio_platform_data i2c12_platdata = { + .sda_pin = GPIO_MSENSE_SDA_28V, + .scl_pin = GPIO_MSENSE_SCL_28V, + .udelay = 0, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c12 = { + .name = "i2c-gpio", + .id = 12, + .dev.platform_data = &i2c12_platdata, +}; + +#if defined (CONFIG_SAMSUNG_CAPTIVATE) +static struct i2c_gpio_platform_data i2c13_platdata = { + .sda_pin = GPIO_A1026_SDA, + .scl_pin = GPIO_A1026_SCL, + .udelay = 1, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, + }; +static struct platform_device s3c_device_i2c13 = { + .name = "i2c-gpio", + .id = 13, + .dev.platform_data = &i2c13_platdata, + }; +#endif + +#ifdef CONFIG_SAMSUNG_FASCINATE +void touch_key_set_int_flt(unsigned long width) +{ + writel(readl(S5PV210_GPJ4_INT_FLTCON0) | + (1 << 15) | // enable bit + (width << 8), // max width = 0x2f + S5PV210_GPJ4_INT_FLTCON0); +} + +const unsigned long touch_int_flt_width = 0x2f; // arbitrary value - max is 0x2f +#endif + +static void touch_keypad_gpio_init(void) +{ + int ret = 0; + + ret = gpio_request(_3_GPIO_TOUCH_EN, "TOUCH_EN"); + if (ret) + printk(KERN_ERR "Failed to request gpio touch_en.\n"); + +#ifdef CONFIG_SAMSUNG_FASCINATE + touch_key_set_int_flt(touch_int_flt_width); +#endif +} + +static void touch_keypad_onoff(int onoff) +{ + gpio_direction_output(_3_GPIO_TOUCH_EN, onoff); + + if (onoff == TOUCHKEY_OFF) + msleep(30); + else + msleep(25); +} + +static void touch_keypad_gpio_sleep(int onoff) { + if (onoff == TOUCHKEY_ON) + s3c_gpio_slp_cfgpin(_3_GPIO_TOUCH_EN, S3C_GPIO_SLP_OUT1); + else + s3c_gpio_slp_cfgpin(_3_GPIO_TOUCH_EN, S3C_GPIO_SLP_OUT0); +} + +static const int touch_keypad_code[] = { +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) + KEY_MENU, + KEY_BACK, + /* Unofficial support for the Telus Fascinate - same internals as I9000 */ + KEY_HOME, + KEY_SEARCH +#else + KEY_MENU, + KEY_HOME, + KEY_BACK, + KEY_SEARCH +#endif +}; + +static struct touchkey_platform_data touchkey_data = { + .keycode_cnt = ARRAY_SIZE(touch_keypad_code), + .keycode = touch_keypad_code, + .touchkey_onoff = touch_keypad_onoff, + .touchkey_sleep_onoff = touch_keypad_gpio_sleep, + .fw_name = "cypress-touchkey.bin", + .scl_pin = _3_TOUCH_SCL_28V, + .sda_pin = _3_TOUCH_SDA_28V, + .en_pin = _3_GPIO_TOUCH_EN, +}; + +static struct gpio_event_direct_entry aries_keypad_key_map[] = { + { + .gpio = S5PV210_GPH2(6), + .code = KEY_POWER, + }, +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) + { + .gpio = S5PV210_GPH3(5), + .code = KEY_HOME, + }, +#endif +#ifdef CONFIG_SAMSUNG_VIBRANT + { + .gpio = S5PV210_GPH3(2), + .code = KEY_VOLUMEDOWN, + }, + { + .gpio = S5PV210_GPH3(1), + .code = KEY_VOLUMEUP, + } +#elif defined(CONFIG_SAMSUNG_FASCINATE) + { + .gpio = S5PV210_GPH3(1), + .code = KEY_VOLUMEDOWN, + }, + { + .gpio = S5PV210_GPH3(3), + .code = KEY_VOLUMEUP, + } +#else + { + .gpio = S5PV210_GPH3(1), + .code = KEY_VOLUMEDOWN, + }, + { + .gpio = S5PV210_GPH3(2), + .code = KEY_VOLUMEUP, + } +#endif +}; + +static struct gpio_event_input_info aries_keypad_key_info = { + .info.func = gpio_event_input_func, + .info.no_suspend = true, + .debounce_time.tv64 = 5 * NSEC_PER_MSEC, + .type = EV_KEY, + .keymap = aries_keypad_key_map, + .keymap_size = ARRAY_SIZE(aries_keypad_key_map) +}; + +static struct gpio_event_info *aries_input_info[] = { + &aries_keypad_key_info.info, +}; + + +static struct gpio_event_platform_data aries_input_data = { + .names = { + "aries-keypad", + NULL, + }, + .info = aries_input_info, + .info_count = ARRAY_SIZE(aries_input_info), +}; + +static struct platform_device aries_input_device = { + .name = GPIO_EVENT_DEV_NAME, + .id = 0, + .dev = { + .platform_data = &aries_input_data, + }, +}; + +#ifdef CONFIG_S5P_ADC +static struct s3c_adc_mach_info s3c_adc_platform __initdata = { + /* s5pc110 support 12-bit resolution */ + .delay = 10000, + .presc = 65, + .resolution = 12, +}; +#endif + +unsigned int HWREV; +EXPORT_SYMBOL(HWREV); + +/* in revisions before 0.9, there is a common mic bias gpio */ + +static DEFINE_SPINLOCK(mic_bias_lock); +static bool wm8994_mic_bias; +static bool jack_mic_bias; +static void set_shared_mic_bias(void) +{ +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + gpio_set_value(GPIO_MICBIAS_EN, wm8994_mic_bias); + gpio_set_value(GPIO_EARPATH_SEL, jack_mic_bias); + gpio_set_value(GPIO_EAR_MICBIAS_EN, jack_mic_bias); +#elif defined(CONFIG_SAMSUNG_VIBRANT) + if((HWREV == 0x0A) || (HWREV == 0x0C) || (HWREV == 0x0D) || (HWREV == 0x0E) ) //0x0A:00, 0x0C:00, 0x0D:01, 0x0E:05 + gpio_set_value(GPIO_MICBIAS_EN, wm8994_mic_bias || jack_mic_bias); + else { + gpio_set_value(GPIO_MICBIAS_EN2, jack_mic_bias); + gpio_set_value(GPIO_MICBIAS_EN, wm8994_mic_bias); + } + gpio_set_value(GPIO_EARPATH_SEL, jack_mic_bias); +#else + gpio_set_value(GPIO_MICBIAS_EN, wm8994_mic_bias || jack_mic_bias); + gpio_set_value(GPIO_EARPATH_SEL, wm8994_mic_bias || jack_mic_bias); +#endif +} + +static void wm8994_set_mic_bias(bool on) +{ + unsigned long flags; + pr_debug("%s: HWREV=%d, on=%d\n", __func__, HWREV, on ? 1 : 0); + spin_lock_irqsave(&mic_bias_lock, flags); + wm8994_mic_bias = on; + set_shared_mic_bias(); + spin_unlock_irqrestore(&mic_bias_lock, flags); +} + +static void sec_jack_set_micbias_state(bool on) +{ + unsigned long flags; + pr_debug("%s: HWREV=%d, on=%d\n", __func__, HWREV, on ? 1 : 0); + spin_lock_irqsave(&mic_bias_lock, flags); + jack_mic_bias = on; + set_shared_mic_bias(); + spin_unlock_irqrestore(&mic_bias_lock, flags); +} + +static struct wm8994_platform_data wm8994_pdata = { + .ldo = GPIO_CODEC_LDO_EN, + .ear_sel = -1, + .set_mic_bias = wm8994_set_mic_bias, +}; + +#ifdef CONFIG_VIDEO_CE147 +/* + * Guide for Camera Configuration for Jupiter board + * ITU CAM CH A: CE147 +*/ + +static struct regulator *cam_isp_core_regulator;/*buck4*/ +static struct regulator *cam_isp_host_regulator;/*15*/ +static struct regulator *cam_af_regulator;/*11*/ +static struct regulator *cam_sensor_core_regulator;/*12*/ +static struct regulator *cam_vga_vddio_regulator;/*13*/ +static struct regulator *cam_vga_dvdd_regulator;/*14*/ +static struct regulator *cam_vga_avdd_regulator;/*16*/ +static bool ce147_powered_on; + +static int ce147_regulator_init(void) +{ +/*BUCK 4*/ + if (IS_ERR_OR_NULL(cam_isp_core_regulator)) { + cam_isp_core_regulator = regulator_get(NULL, "cam_isp_core"); + if (IS_ERR_OR_NULL(cam_isp_core_regulator)) { + pr_err("failed to get cam_isp_core regulator"); + return -EINVAL; + } + } +/*ldo 11*/ + if (IS_ERR_OR_NULL(cam_af_regulator)) { + cam_af_regulator = regulator_get(NULL, "cam_af"); + if (IS_ERR_OR_NULL(cam_af_regulator)) { + pr_err("failed to get cam_af regulator"); + return -EINVAL; + } + } +/*ldo 12*/ + if (IS_ERR_OR_NULL(cam_sensor_core_regulator)) { + cam_sensor_core_regulator = regulator_get(NULL, "cam_sensor"); + if (IS_ERR_OR_NULL(cam_sensor_core_regulator)) { + pr_err("failed to get cam_sensor regulator"); + return -EINVAL; + } + } +/*ldo 13*/ + if (IS_ERR_OR_NULL(cam_vga_vddio_regulator)) { + cam_vga_vddio_regulator = regulator_get(NULL, "vga_vddio"); + if (IS_ERR_OR_NULL(cam_vga_vddio_regulator)) { + pr_err("failed to get vga_vddio regulator"); + return -EINVAL; + } + } +/*ldo 14*/ + if (IS_ERR_OR_NULL(cam_vga_dvdd_regulator)) { + cam_vga_dvdd_regulator = regulator_get(NULL, "vga_dvdd"); + if (IS_ERR_OR_NULL(cam_vga_dvdd_regulator)) { + pr_err("failed to get vga_dvdd regulator"); + return -EINVAL; + } + } +/*ldo 15*/ + if (IS_ERR_OR_NULL(cam_isp_host_regulator)) { + cam_isp_host_regulator = regulator_get(NULL, "cam_isp_host"); + if (IS_ERR_OR_NULL(cam_isp_host_regulator)) { + pr_err("failed to get cam_isp_host regulator"); + return -EINVAL; + } + } +/*ldo 16*/ + if (IS_ERR_OR_NULL(cam_vga_avdd_regulator)) { + cam_vga_avdd_regulator = regulator_get(NULL, "vga_avdd"); + if (IS_ERR_OR_NULL(cam_vga_avdd_regulator)) { + pr_err("failed to get vga_avdd regulator"); + return -EINVAL; + } + } + pr_debug("cam_isp_core_regulator = %p\n", cam_isp_core_regulator); + pr_debug("cam_isp_host_regulator = %p\n", cam_isp_host_regulator); + pr_debug("cam_af_regulator = %p\n", cam_af_regulator); + pr_debug("cam_sensor_core_regulator = %p\n", cam_sensor_core_regulator); + pr_debug("cam_vga_vddio_regulator = %p\n", cam_vga_vddio_regulator); + pr_debug("cam_vga_dvdd_regulator = %p\n", cam_vga_dvdd_regulator); + pr_debug("cam_vga_avdd_regulator = %p\n", cam_vga_avdd_regulator); + return 0; +} + +static void ce147_init(void) +{ + /* CAM_IO_EN - GPB(7) */ + if (gpio_request(GPIO_GPB7, "GPB7") < 0) + pr_err("failed gpio_request(GPB7) for camera control\n"); + /* CAM_MEGA_nRST - GPJ1(5) */ + if (gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1") < 0) + pr_err("failed gpio_request(GPJ1) for camera control\n"); + /* CAM_MEGA_EN - GPJ0(6) */ + if (gpio_request(GPIO_CAM_MEGA_EN, "GPJ0") < 0) + pr_err("failed gpio_request(GPJ0) for camera control\n"); +} + +static int ce147_ldo_en(bool en) +{ + int err = 0; + int result; + + if (IS_ERR_OR_NULL(cam_isp_core_regulator) || + IS_ERR_OR_NULL(cam_isp_host_regulator) || + IS_ERR_OR_NULL(cam_af_regulator) || //) {// || + IS_ERR_OR_NULL(cam_sensor_core_regulator) || + IS_ERR_OR_NULL(cam_vga_vddio_regulator) || + IS_ERR_OR_NULL(cam_vga_dvdd_regulator) || + IS_ERR_OR_NULL(cam_vga_avdd_regulator)) { + pr_err("Camera regulators not initialized\n"); + return -EINVAL; + } + + if (!en) + goto off; + + /* Turn CAM_ISP_CORE_1.2V(VDD_REG) on BUCK 4*/ + err = regulator_enable(cam_isp_core_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + mdelay(1); + + /* Turn CAM_AF_2.8V or 3.0V on ldo 11*/ + err = regulator_enable(cam_af_regulator); + if (err) { + pr_err("Failed to enable regulator cam_af\n"); + goto off; + } + udelay(50); + + /*ldo 12*/ + err = regulator_enable(cam_sensor_core_regulator); + if (err) { + pr_err("Failed to enable regulator cam_sensor\n"); + goto off; + } + udelay(50); + + /*ldo 13*/ + err = regulator_enable(cam_vga_vddio_regulator); + if (err) { + pr_err("Failed to enable regulator cam_vga_vddio\n"); + goto off; + } + udelay(50); + + /*ldo 14*/ + err = regulator_enable(cam_vga_dvdd_regulator); + if (err) { + pr_err("Failed to enable regulator cam_vga_dvdd\n"); + goto off; + } + udelay(50); + + /* Turn CAM_ISP_HOST_2.8V(VDDIO) on ldo 15*/ + err = regulator_enable(cam_isp_host_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + udelay(50); + + /*ldo 16*/ + err = regulator_enable(cam_vga_avdd_regulator); + if (err) { + pr_err("Failed to enable regulator cam_vga_avdd\n"); + goto off; + } + udelay(50); + + /* Turn CAM_SENSOR_A_2.8V(VDDA) on */ + gpio_set_value(GPIO_GPB7, 1); + mdelay(1); + + return 0; + +off: + result = err; + + gpio_direction_output(GPIO_GPB7, 1); + gpio_set_value(GPIO_GPB7, 0); + + /* ldo 11 */ + err = regulator_disable(cam_af_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + /* ldo 12 */ + err = regulator_disable(cam_sensor_core_regulator); + if (err) { + pr_err("Failed to disable regulator cam_sensor\n"); + result = err; + } + /* ldo 13 */ + err = regulator_disable(cam_vga_vddio_regulator); + if (err) { + pr_err("Failed to disable regulator cam_vga_vddio\n"); + result = err; + } + /* ldo 14 */ + err = regulator_disable(cam_vga_dvdd_regulator); + if (err) { + pr_err("Failed to disable regulator cam_vga_dvdd\n"); + result = err; + } + /* ldo 15 */ + err = regulator_disable(cam_isp_host_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + /* ldo 16 */ + err = regulator_disable(cam_vga_avdd_regulator); + if (err) { + pr_err("Failed to disable regulator cam_vga_avdd\n"); + result = err; + } + /* BUCK 4 */ + err = regulator_disable(cam_isp_core_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + return result; +} + +static int ce147_power_on(void) +{ + int err; + bool TRUE = true; + + if (ce147_regulator_init()) { + pr_err("Failed to initialize camera regulators\n"); + return -EINVAL; + } + + ce147_init(); + + /* CAM_VGA_nSTBY - GPB(0) */ + err = gpio_request(GPIO_CAM_VGA_nSTBY, "GPB0"); + + if (err) { + printk(KERN_ERR "failed to request GPB0 for camera control\n"); + + return err; + } + + /* CAM_VGA_nRST - GPB(2) */ + err = gpio_request(GPIO_CAM_VGA_nRST, "GPB2"); + + if (err) { + printk(KERN_ERR "failed to request GPB2 for camera control\n"); + + return err; + } + + ce147_ldo_en(TRUE); + + mdelay(1); + + // CAM_VGA_nSTBY HIGH + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + + gpio_set_value(GPIO_CAM_VGA_nSTBY, 1); + + mdelay(1); + + // Mclk enable + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(0x02)); + + mdelay(1); + + // CAM_VGA_nRST HIGH + gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + + gpio_set_value(GPIO_CAM_VGA_nRST, 1); + + mdelay(1); + + // CAM_VGA_nSTBY LOW + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + + mdelay(1); + + // CAM_MEGA_EN HIGH + gpio_direction_output(GPIO_CAM_MEGA_EN, 0); + + gpio_set_value(GPIO_CAM_MEGA_EN, 1); + + mdelay(1); + + // CAM_MEGA_nRST HIGH + gpio_direction_output(GPIO_CAM_MEGA_nRST, 0); + + gpio_set_value(GPIO_CAM_MEGA_nRST, 1); + + gpio_free(GPIO_CAM_MEGA_EN); + gpio_free(GPIO_CAM_MEGA_nRST); + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_CAM_VGA_nRST); + gpio_free(GPIO_GPB7); + + mdelay(5); + + return 0; +} + + +static int ce147_power_off(void) +{ + int err; + bool FALSE = false; + + /* CAM_IO_EN - GPB(7) */ + err = gpio_request(GPIO_GPB7, "GPB7"); + + if(err) { + printk(KERN_ERR "failed to request GPB7 for camera control\n"); + + return err; + } + + /* CAM_MEGA_EN - GPJ0(6) */ + err = gpio_request(GPIO_CAM_MEGA_EN, "GPJ0"); + + if(err) { + printk(KERN_ERR "failed to request GPJ0 for camera control\n"); + + return err; + } + + /* CAM_MEGA_nRST - GPJ1(5) */ + err = gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1"); + + if(err) { + printk(KERN_ERR "failed to request GPJ1 for camera control\n"); + + return err; + } + + /* CAM_VGA_nRST - GPB(2) */ + err = gpio_request(GPIO_CAM_VGA_nRST, "GPB2"); + + if (err) { + printk(KERN_ERR "failed to request GPB2 for camera control\n"); + + return err; + } + /* CAM_VGA_nSTBY - GPB(0) */ + err = gpio_request(GPIO_CAM_VGA_nSTBY, "GPB0"); + + if (err) { + printk(KERN_ERR "failed to request GPB0 for camera control\n"); + + return err; + } + + // CAM_VGA_nSTBY LOW + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + + mdelay(1); + + // CAM_VGA_nRST LOW + gpio_direction_output(GPIO_CAM_VGA_nRST, 1); + + gpio_set_value(GPIO_CAM_VGA_nRST, 0); + + mdelay(1); + + // CAM_MEGA_nRST - GPJ1(5) LOW + gpio_direction_output(GPIO_CAM_MEGA_nRST, 1); + + gpio_set_value(GPIO_CAM_MEGA_nRST, 0); + + mdelay(1); + + // Mclk disable + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + + mdelay(1); + + // CAM_MEGA_EN - GPJ0(6) LOW + gpio_direction_output(GPIO_CAM_MEGA_EN, 1); + + gpio_set_value(GPIO_CAM_MEGA_EN, 0); + + mdelay(1); + + ce147_ldo_en(FALSE); + + mdelay(1); + + gpio_free(GPIO_CAM_MEGA_EN); + gpio_free(GPIO_CAM_MEGA_nRST); + gpio_free(GPIO_CAM_VGA_nRST); + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_GPB7); + + return 0; +} + + +static int ce147_power_en(int onoff) +{ +/* int bd_level; // unused variable */ + int err = 0; +#if 0 + if(onoff){ + ce147_ldo_en(true); + s3c_gpio_cfgpin(S5PV210_GPE1(3), S5PV210_GPE1_3_CAM_A_CLKOUT); + ce147_cam_en(true); + ce147_cam_nrst(true); + } else { + ce147_cam_en(false); + ce147_cam_nrst(false); + s3c_gpio_cfgpin(S5PV210_GPE1(3), 0); + ce147_ldo_en(false); + } + + return 0; +#endif + + if (onoff != ce147_powered_on) { + if (onoff) + err = ce147_power_on(); + else { + err = ce147_power_off(); + s3c_i2c0_force_stop(); + } + if (!err) + ce147_powered_on = onoff; + } + + return 0; +} + +static int smdkc110_cam1_power(int onoff) +{ + int err; + /* Implement on/off operations */ + + /* CAM_VGA_nSTBY - GPB(0) */ + err = gpio_request(S5PV210_GPB(0), "GPB"); + + if (err) { + printk(KERN_ERR "failed to request GPB for camera control\n"); + return err; + } + + gpio_direction_output(S5PV210_GPB(0), 0); + + mdelay(1); + + gpio_direction_output(S5PV210_GPB(0), 1); + + mdelay(1); + + gpio_set_value(S5PV210_GPB(0), 1); + + mdelay(1); + + gpio_free(S5PV210_GPB(0)); + + mdelay(1); + + /* CAM_VGA_nRST - GPB(2) */ + err = gpio_request(S5PV210_GPB(2), "GPB"); + + if (err) { + printk(KERN_ERR "failed to request GPB for camera control\n"); + return err; + } + + gpio_direction_output(S5PV210_GPB(2), 0); + + mdelay(1); + + gpio_direction_output(S5PV210_GPB(2), 1); + + mdelay(1); + + gpio_set_value(S5PV210_GPB(2), 1); + + mdelay(1); + + gpio_free(S5PV210_GPB(2)); + + return 0; +} + +/* + * Guide for Camera Configuration for Jupiter board + * ITU CAM CH A: CE147 +*/ + +/* External camera module setting */ +static struct ce147_platform_data ce147_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 0, + .power_en = ce147_power_en, +}; + +static struct i2c_board_info ce147_i2c_info = { + I2C_BOARD_INFO("CE147", 0x78>>1), + .platform_data = &ce147_plat, +}; + +static struct s3c_platform_camera ce147 = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &ce147_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam",//"sclk_cam0", + .clk_rate = 24000000, + .line_length = 1920, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + // Polarity + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, + .cam_power = ce147_power_en, +}; +#endif + +#ifdef CONFIG_VIDEO_S5KA3DFX +/* External camera module setting */ +static DEFINE_MUTEX(s5ka3dfx_lock); +static struct regulator *s5ka3dfx_vga_avdd; +static struct regulator *s5ka3dfx_vga_vddio; +static struct regulator *s5ka3dfx_cam_isp_host; +static struct regulator *s5ka3dfx_vga_dvdd; +static bool s5ka3dfx_powered_on; + +static int s5ka3dfx_request_gpio(void) +{ + int err; + + /* CAM_VGA_nSTBY - GPB(0) */ + err = gpio_request(GPIO_CAM_VGA_nSTBY, "GPB0"); + if (err) { + pr_err("Failed to request GPB0 for camera control\n"); + return -EINVAL; + } + + /* CAM_VGA_nRST - GPB(2) */ + err = gpio_request(GPIO_CAM_VGA_nRST, "GPB2"); + if (err) { + pr_err("Failed to request GPB2 for camera control\n"); + gpio_free(GPIO_CAM_VGA_nSTBY); + return -EINVAL; + } + /* CAM_IO_EN - GPB(7) */ + err = gpio_request(GPIO_GPB7, "GPB7"); + + if(err) { + pr_err("Failed to request GPB2 for camera control\n"); + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_CAM_VGA_nRST); + return -EINVAL; + } + + return 0; +} + +static int s5ka3dfx_power_init(void) +{ + /*if (IS_ERR_OR_NULL(s5ka3dfx_vga_avdd)) + s5ka3dfx_vga_avdd = regulator_get(NULL, "vga_avdd"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_avdd)) { + pr_err("Failed to get regulator vga_avdd\n"); + return -EINVAL; + }*/ + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_vddio)) + s5ka3dfx_vga_vddio = regulator_get(NULL, "vga_vddio"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_vddio)) { + pr_err("Failed to get regulator vga_vddio\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_cam_isp_host)) + s5ka3dfx_cam_isp_host = regulator_get(NULL, "cam_isp_host"); + + if (IS_ERR_OR_NULL(s5ka3dfx_cam_isp_host)) { + pr_err("Failed to get regulator cam_isp_host\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_dvdd)) + s5ka3dfx_vga_dvdd = regulator_get(NULL, "vga_dvdd"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_dvdd)) { + pr_err("Failed to get regulator vga_dvdd\n"); + return -EINVAL; + } + + return 0; +} + +static int s5ka3dfx_power_on(void) +{ + int err = 0; + int result; + + if (s5ka3dfx_power_init()) { + pr_err("Failed to get all regulator\n"); + return -EINVAL; + } + + s5ka3dfx_request_gpio(); + /* Turn VGA_AVDD_2.8V on */ + /*err = regulator_enable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to enable regulator vga_avdd\n"); + return -EINVAL; + } + msleep(3);*/ + // Turn CAM_ISP_SYS_2.8V on + gpio_direction_output(GPIO_GPB7, 0); + gpio_set_value(GPIO_GPB7, 1); + + mdelay(1); + + /* Turn VGA_VDDIO_2.8V on */ + err = regulator_enable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to enable regulator vga_vddio\n"); + return -EINVAL;//goto off_vga_vddio; + } + udelay(20); + + /* Turn VGA_DVDD_1.8V on */ + err = regulator_enable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to enable regulator vga_dvdd\n"); + goto off_vga_dvdd; + } + udelay(100); + + /* CAM_VGA_nSTBY HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 1); + + udelay(10); + + /* Mclk enable */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(0x02)); + udelay(430); + + /* Turn CAM_ISP_HOST_2.8V on */ + err = regulator_enable(s5ka3dfx_cam_isp_host); + if (err) { + pr_err("Failed to enable regulator cam_isp_host\n"); + goto off_cam_isp_host; + } + udelay(150); + + /* CAM_VGA_nRST HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + gpio_set_value(GPIO_CAM_VGA_nRST, 1); + mdelay(5); + + return 0; +off_cam_isp_host: + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + udelay(1); + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + udelay(1); + err = regulator_disable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to disable regulator vga_dvdd\n"); + result = err; + } +off_vga_dvdd: + err = regulator_disable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to disable regulator vga_vddio\n"); + result = err; + } +/*off_vga_vddio: + err = regulator_disable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to disable regulator vga_avdd\n"); + result = err; + }*/ + + return result; +} + +static int s5ka3dfx_power_off(void) +{ + int err; + + if (/*!s5ka3dfx_vga_avdd ||*/ !s5ka3dfx_vga_vddio || + !s5ka3dfx_cam_isp_host || !s5ka3dfx_vga_dvdd) { + pr_err("Faild to get all regulator\n"); + return -EINVAL; + } + + /* Turn CAM_ISP_HOST_2.8V off */ + err = regulator_disable(s5ka3dfx_cam_isp_host); + if (err) { + pr_err("Failed to disable regulator cam_isp_host\n"); + return -EINVAL; + } + + /* CAM_VGA_nRST LOW */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 1); + gpio_set_value(GPIO_CAM_VGA_nRST, 0); + udelay(430); + + /* Mclk disable */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + + udelay(1); + + /* Turn VGA_VDDIO_2.8V off */ + err = regulator_disable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to disable regulator vga_vddio\n"); + return -EINVAL; + } + + /* Turn VGA_DVDD_1.8V off */ + err = regulator_disable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to disable regulator vga_dvdd\n"); + return -EINVAL; + } + + /* CAM_VGA_nSTBY LOW */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + + udelay(1); + + /* Turn VGA_AVDD_2.8V off */ + /*err = regulator_disable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to disable regulator vga_avdd\n"); + return -EINVAL; + }*/ + + gpio_free(GPIO_GPB7); + gpio_free(GPIO_CAM_VGA_nRST); + gpio_free(GPIO_CAM_VGA_nSTBY); + + return err; +} + +static int s5ka3dfx_power_en(int onoff) +{ + int err = 0; + mutex_lock(&s5ka3dfx_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != s5ka3dfx_powered_on) { + if (onoff) + err = s5ka3dfx_power_on(); + else { + err = s5ka3dfx_power_off(); + s3c_i2c0_force_stop(); + } + if (!err) + s5ka3dfx_powered_on = onoff; + } + mutex_unlock(&s5ka3dfx_lock); + + return err; +} + +static struct s5ka3dfx_platform_data s5ka3dfx_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 0, + + .cam_power = s5ka3dfx_power_en, +}; + +static struct i2c_board_info s5ka3dfx_i2c_info = { + I2C_BOARD_INFO("S5KA3DFX", 0xc4>>1), + .platform_data = &s5ka3dfx_plat, +}; + +static struct s3c_platform_camera s5ka3dfx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &s5ka3dfx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 480, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, + .cam_power = s5ka3dfx_power_en, +}; +#endif + +/* Interface setting */ +static struct s3c_platform_fimc fimc_plat_lsi = { + .srclk_name = "mout_mpll", + .clk_name = "sclk_fimc", + .lclk_name = "fimc", + .clk_rate = 166750000, + .default_cam = CAMERA_PAR_A, + .camera = { + &ce147, +#ifdef CONFIG_VIDEO_S5KA3DFX + &s5ka3dfx, +#endif + }, + .hw_ver = 0x43, +}; + +#ifdef CONFIG_VIDEO_JPEG_V2 +static struct s3c_platform_jpeg jpeg_plat __initdata = { + .max_main_width = 800, + .max_main_height = 480, + .max_thumb_width = 320, + .max_thumb_height = 240, +}; +#endif + +/* I2C0 */ +static struct i2c_board_info i2c_devs0[] __initdata = { +}; + +static struct i2c_board_info i2c_devs4[] __initdata = { + { + I2C_BOARD_INFO("wm8994-samsung", (0x34>>1)), + .platform_data = &wm8994_pdata, + }, +}; + +/* I2C1 */ +static struct i2c_board_info i2c_devs1[] __initdata = { +}; + +static void mxt224_power_on(void) +{ + gpio_direction_output(GPIO_TOUCH_EN, 1); + + mdelay(40); +} + +static void mxt224_power_off(void) +{ + gpio_direction_output(GPIO_TOUCH_EN, 0); +} + +#define MXT224_MAX_MT_FINGERS 10 + +static u8 t7_config[] = {GEN_POWERCONFIG_T7, + 64, 255, 50}; +static u8 t8_config[] = {GEN_ACQUISITIONCONFIG_T8, + 7, 0, 5, 0, 0, 0, 9, 35}; +static u8 t9_config[] = {TOUCH_MULTITOUCHSCREEN_T9, + 139, 0, 0, 19, 11, 0, 33, 30, 2, 1, 0, 3, 1, + 46, MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 0, + 0, 0, 0, 0, 0, 0, 143, 40, 143, 80, 18}; +static u8 t18_config[] = {SPT_COMCONFIG_T18, + 0, 1}; +static u8 t20_config[] = {PROCI_GRIPFACESUPPRESSION_T20, + 7, 0, 0, 0, 0, 0, 0, 80, 40, 4, 35, 10}; +static u8 t22_config[] = {PROCG_NOISESUPPRESSION_T22, + 5, 0, 0, 0, 0, 0, 0, 3, 30, 0, 0, 29, 34, 39, + 49, 58, 3}; +static u8 t28_config[] = {SPT_CTECONFIG_T28, + 1, 0, 3, 16, 63, 60}; +static u8 end_config[] = {RESERVED_T255}; + +static const u8 *mxt224_config[] = { + t7_config, + t8_config, + t9_config, + t18_config, + t20_config, + t22_config, + t28_config, + end_config, +}; + +static struct mxt224_platform_data mxt224_data = { + .max_finger_touches = MXT224_MAX_MT_FINGERS, + .gpio_read_done = GPIO_TOUCH_INT, + .config = mxt224_config, + .min_x = 0, + .max_x = 1023, + .min_y = 0, + .max_y = 1023, + .min_z = 0, + .max_z = 255, + .min_w = 0, + .max_w = 30, + .power_on = mxt224_power_on, + .power_off = mxt224_power_off, +}; + +/* I2C2 */ +static struct i2c_board_info i2c_devs2[] __initdata = { + { +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK + I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a), + .platform_data = &mxt224_data, + .irq = IRQ_EINT_GROUP(3, 3), +#else + I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a), + .platform_data = &mxt224_data, + .irq = IRQ_EINT_GROUP(18, 5), +#endif + }, +}; + +static void mxt224_init(void) +{ + return; +} + +/* I2C2 */ +static struct i2c_board_info i2c_devs10[] __initdata = { + { + I2C_BOARD_INFO(CYPRESS_TOUCHKEY_DEV_NAME, 0x20), + .platform_data = &touchkey_data, + .irq = (IRQ_EINT_GROUP22_BASE + 1), + }, +}; + +static struct i2c_board_info i2c_devs5[] __initdata = { +#if defined(CONFIG_SAMSUNG_FASCINATE) + { + I2C_BOARD_INFO("kr3dh", 0x19), + }, +#else + { + I2C_BOARD_INFO("bma023", 0x38), + }, +#endif +}; + +static struct i2c_board_info i2c_devs8[] __initdata = { + { + I2C_BOARD_INFO("Si4709", (0x20 >> 1)), + }, +}; + +static void fsa9480_usb_cb(bool attached) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + if (gadget) { + if (attached) + usb_gadget_vbus_connect(gadget); + else + usb_gadget_vbus_disconnect(gadget); + } + + set_cable_status = attached ? CABLE_TYPE_USB : CABLE_TYPE_NONE; + if (charger_callbacks && charger_callbacks->set_cable) + charger_callbacks->set_cable(charger_callbacks, set_cable_status); +} + +static void fsa9480_charger_cb(bool attached) +{ + set_cable_status = attached ? CABLE_TYPE_AC : CABLE_TYPE_NONE; + if (charger_callbacks && charger_callbacks->set_cable) + charger_callbacks->set_cable(charger_callbacks, set_cable_status); +} + +static struct switch_dev switch_dock = { + .name = "dock", +}; + +static void fsa9480_deskdock_cb(bool attached) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + if (attached) + switch_set_state(&switch_dock, 1); + else + switch_set_state(&switch_dock, 0); + + if (gadget) { + if (attached) + usb_gadget_vbus_connect(gadget); + else + usb_gadget_vbus_disconnect(gadget); + } + + set_cable_status = attached ? CABLE_TYPE_USB : CABLE_TYPE_NONE; + if (charger_callbacks && charger_callbacks->set_cable) + charger_callbacks->set_cable(charger_callbacks, set_cable_status); +} + +static void fsa9480_cardock_cb(bool attached) +{ + if (attached) + switch_set_state(&switch_dock, 2); + else + switch_set_state(&switch_dock, 0); + + set_cable_status = attached ? CABLE_TYPE_AC : CABLE_TYPE_NONE; + if (charger_callbacks && charger_callbacks->set_cable) + charger_callbacks->set_cable(charger_callbacks, set_cable_status); +} + +static void fsa9480_reset_cb(void) +{ + int ret; + + /* for CarDock, DeskDock */ + ret = switch_dev_register(&switch_dock); + if (ret < 0) + pr_err("Failed to register dock switch. %d\n", ret); +} + +static struct fsa9480_platform_data fsa9480_pdata = { + .usb_cb = fsa9480_usb_cb, + .charger_cb = fsa9480_charger_cb, + .deskdock_cb = fsa9480_deskdock_cb, + .cardock_cb = fsa9480_cardock_cb, + .reset_cb = fsa9480_reset_cb, +}; + +static struct i2c_board_info i2c_devs7[] __initdata = { + { + I2C_BOARD_INFO("fsa9480", 0x4A >> 1), + .platform_data = &fsa9480_pdata, + .irq = IRQ_EINT(23), + }, +}; + +static struct i2c_board_info i2c_devs6[] __initdata = { +#ifdef CONFIG_REGULATOR_MAX8998 + { + /* The address is 0xCC used since SRAD = 0 */ + I2C_BOARD_INFO("max8998", (0xCC >> 1)), + .platform_data = &max8998_pdata, + .irq = IRQ_EINT7, + }, { + I2C_BOARD_INFO("rtc_max8998", (0x0D >> 1)), + }, +#endif +}; + +static int max17040_power_supply_register(struct device *parent, + struct power_supply *psy) +{ + aries_charger.psy_fuelgauge = psy; + return 0; +} + +static void max17040_power_supply_unregister(struct power_supply *psy) +{ + aries_charger.psy_fuelgauge = NULL; +} + +static struct max17040_platform_data max17040_pdata = { + .power_supply_register = max17040_power_supply_register, + .power_supply_unregister = max17040_power_supply_unregister, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + .rcomp_value = 0xD000, +#else + .rcomp_value = 0xB000, +#endif +}; + +static struct i2c_board_info i2c_devs9[] __initdata = { + { + I2C_BOARD_INFO("max17040", (0x6D >> 1)), + .platform_data = &max17040_pdata, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + .irq = IRQ_EINT(27), +#endif + }, +}; + +static int gp2a_power(bool on) +{ + /* this controls the power supply rail to the gp2a IC */ + gpio_direction_output(GPIO_PS_ON, on); + return 0; +} + +static int gp2a_light_adc_value(void) +{ + return s3c_adc_get_adc_data(9); +} + +static struct gp2a_platform_data gp2a_pdata = { + .power = gp2a_power, + .p_out = GPIO_PS_VOUT, + .light_adc_value = gp2a_light_adc_value +}; + +static void gp2a_gpio_init(void) +{ + int ret = gpio_request(GPIO_PS_ON, "gp2a_power_supply_on"); + if (ret) + printk(KERN_ERR "Failed to request gpio gp2a power supply.\n"); +} + +static struct i2c_board_info i2c_devs11[] __initdata = { + { + I2C_BOARD_INFO("gp2a", (0x88 >> 1)), + .platform_data = &gp2a_pdata, + }, +}; + +static struct yas529_platform_data yas529_pdata = { + .reset_line = GPIO_MSENSE_nRST, + .reset_asserted = GPIO_LEVEL_LOW, +}; + +static struct i2c_board_info i2c_devs12[] __initdata = { + { + I2C_BOARD_INFO("yas529", 0x2e), + .platform_data = &yas529_pdata, + }, +}; + +#if defined (CONFIG_SAMSUNG_CAPTIVATE) +static struct i2c_board_info i2c_devs13[] __initdata = { + { + I2C_BOARD_INFO("A1026_driver", (0x3E)), + }, +}; +#endif + +static struct resource ram_console_resource[] = { + { + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ram_console_device = { + .name = "ram_console", + .id = -1, + .num_resources = ARRAY_SIZE(ram_console_resource), + .resource = ram_console_resource, +}; + +#ifdef CONFIG_ANDROID_PMEM +static struct android_pmem_platform_data pmem_pdata = { + .name = "pmem", + .no_allocator = 1, + .cached = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_gpu1_pdata = { + .name = "pmem_gpu1", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_adsp_pdata = { + .name = "pmem_adsp", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct platform_device pmem_device = { + .name = "android_pmem", + .id = 0, + .dev = { .platform_data = &pmem_pdata }, +}; + +static struct platform_device pmem_gpu1_device = { + .name = "android_pmem", + .id = 1, + .dev = { .platform_data = &pmem_gpu1_pdata }, +}; + +static struct platform_device pmem_adsp_device = { + .name = "android_pmem", + .id = 2, + .dev = { .platform_data = &pmem_adsp_pdata }, +}; + +static void __init android_pmem_set_platdata(void) +{ + pmem_pdata.start = (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM, 0); + pmem_pdata.size = (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM, 0); + + pmem_gpu1_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_GPU1, 0); + pmem_gpu1_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_GPU1, 0); + + pmem_adsp_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_ADSP, 0); + pmem_adsp_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_ADSP, 0); +} +#endif + +struct platform_device sec_device_battery = { + .name = "sec-battery", + .id = -1, +}; + +static struct platform_device sec_device_rfkill = { + .name = "bt_rfkill", + .id = -1, +}; + +static struct platform_device sec_device_btsleep = { + .name = "bt_sleep", + .id = -1, +}; + +static struct sec_jack_zone sec_jack_zones[] = { + { + /* adc == 0, unstable zone, default to 3pole if it stays + * in this range for a half second (20ms delays, 25 samples) + */ + .adc_high = 0, + .delay_ms = 20, + .check_count = 25, + .jack_type = SEC_HEADSET_3POLE, + }, +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + { + /* 0 < adc <= 700, unstable zone, default to 3pole if it stays + * in this range for a second (10ms delays, 80 samples) + */ + .adc_high = 700, + .delay_ms = 10, + .check_count = 80, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 700 < adc <= 2500, default to 4pole if it + * stays in this range for 800ms second (10ms delays, 80 samples) + */ + .adc_high = 2500, + .delay_ms = 10, + .check_count = 80, + .jack_type = SEC_HEADSET_4POLE, + }, +#elif defined(CONFIG_SAMSUNG_VIBRANT) + { + /* 0 < adc <= 500, unstable zone, default to 3pole if it stays + * in this range for 800ms (10ms delays, 80 samples) + */ + .adc_high = 500, + .delay_ms = 10, + .check_count = 80, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 500 < adc <= 3300, default to 4pole if it + * stays in this range for 800ms (10ms delays, 80 samples) + */ + .adc_high = 3300, + .delay_ms = 10, + .check_count = 80, + .jack_type = SEC_HEADSET_4POLE, + }, +#else + { + /* 0 < adc <= 900, unstable zone, default to 3pole if it stays + * in this range for 800ms (10ms delays, 80 samples) + */ + .adc_high = 900, + .delay_ms = 10, + .check_count = 80, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 900 < adc <= 2000, unstable zone, default to 4pole if it + * stays in this range for 800ms (10ms delays, 80 samples) + */ + .adc_high = 2000, + .delay_ms = 10, + .check_count = 80, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* 2000 < adc <= 3400, 4 pole zone, default to 4pole if it + * stays in this range for 100ms (10ms delays, 10 samples) + */ + .adc_high = 3400, + .delay_ms = 10, + .check_count = 10, + .jack_type = SEC_HEADSET_4POLE, + }, +#endif + { + /* adc > max for device above, unstable zone, default to 3pole if it stays + * in this range for two seconds (10ms delays, 200 samples) + */ + .adc_high = 0x7fffffff, + .delay_ms = 10, + .check_count = 200, + .jack_type = SEC_HEADSET_3POLE, + }, +}; + +/* To support 3-buttons earjack */ +static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = { +#if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_VIBRANT) + { + /* 0 <= adc <=110, stable zone */ + .code = KEY_MEDIA, + .adc_low = 0, + .adc_high = 110, + }, + { + /* 130 <= adc <= 365, stable zone */ + .code = KEY_PREVIOUSSONG, + .adc_low = 130, + .adc_high = 365, + }, + { + /* 385 <= adc <= 870, stable zone */ + .code = KEY_NEXTSONG, + .adc_low = 385, + .adc_high = 870, + }, +#else + { + /* 0 <= adc <=1000, stable zone */ + .code = KEY_MEDIA, + .adc_low = 0, + .adc_high = 1000, + }, +#endif +}; + +static int sec_jack_get_adc_value(void) +{ + pr_info("%s: sec_jack adc value = %i \n", __func__, s3c_adc_get_adc_data(3)); + return s3c_adc_get_adc_data(3); +} + +struct sec_jack_platform_data sec_jack_pdata = { + .set_micbias_state = sec_jack_set_micbias_state, + .get_adc_value = sec_jack_get_adc_value, + .zones = sec_jack_zones, + .num_zones = ARRAY_SIZE(sec_jack_zones), + .buttons_zones = sec_jack_buttons_zones, + .num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones), + .det_gpio = GPIO_DET_35, +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + .send_end_gpio = GPIO_EAR_SEND_END35, +#else + .send_end_gpio = GPIO_EAR_SEND_END, +#endif +}; + +static struct platform_device sec_device_jack = { + .name = "sec_jack", + .id = 1, /* will be used also for gpio_event id */ + .dev.platform_data = &sec_jack_pdata, +}; + + +#define S3C_GPIO_SETPIN_ZERO 0 +#define S3C_GPIO_SETPIN_ONE 1 +#define S3C_GPIO_SETPIN_NONE 2 + +// just4info +// S3C_GPIO_SFN(0xF) = S3C_GPIO_EINT = S3C_GPIO_SPECIAL(0xF) + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +static struct gpio_init_data aries_init_gpios[] = { + + // GPB ----------------------------- + { + .num = S5PV210_GPB(0), // GPIO_CAM_VGA_nSTBY + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(1), // GPIO_MSENSE_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(2), // GPIO_CAM_VGA_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { +#if defined(CONFIG_SAMSUNG_GALAXYSB) + .num = S5PV210_GPB(3), // GPIO_BT_nRST + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPB(3), // GPIO_BT_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { + .num = S5PV210_GPB(4), // GPIO_BOOT_MODE + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(5), // GPIO_WLAN_BT_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { +#if defined(CONFIG_SAMSUNG_GALAXYSB) + .num = S5PV210_GPB(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPB(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { + .num = S5PV210_GPB(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPC0 ---------------------------- + { + .num = S5PV210_GPC0(0), // GPIO_REC_PCM_CLK + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(2), // GPIO_REC_PCM_SYNC + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(3), // GPIO_REC_PCM_IN + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(4), // GPIO_REC_PCM_OUT + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPC1 ---------------------------- + { + .num = S5PV210_GPC1(0), // BLOW_PCM_CLK + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPD0 ---------------------------- + { + .num = S5PV210_GPD0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(1), // GPIO_VIBTONE_PWM + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPD1 ---------------------------- + { + .num = S5PV210_GPD1(0), // GPIO_CAM_SDA_29V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(1), // GPIO_CAM_SCL_29V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(2), // GPIO_FM_SDA_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(3), // GPIO_FM_SCL_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(4), // GPIO_TSP_SDA_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(5), // GPIO_TSP_SCL_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPE0 ---------------------------- + { + .num = S5PV210_GPE0(0), // GPIO_CAM_PCLK + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(1), // GPIO_CAM_VSYNC + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(2), // GPIO_CAM_HSYNC + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(3), // GPIO_CAM_D0 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(4), // GPIO_CAM_D1 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(5), // GPIO_CAM_D2 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(6), // GPIO_CAM_D3 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(7), // GPIO_CAM_D4 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPE1 ---------------------------- + { + .num = S5PV210_GPE1(0), // GPIO_CAM_D5 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(1), // GPIO_CAM_D6 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(2), // GPIO_CAM_D7 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(3), // GPIO_CAM_MCLK + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPF3 ---------------------------- + { + .num = S5PV210_GPF3(4), // GPIO_CODEC_LDO_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPF3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPG0 ---------------------------- + { + .num = S5PV210_GPG0(0), // GPIO_NAND_CLK + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(1), // GPIO_NAND_CMD + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(2), // GPIO_ALS_SCL_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(3), // GPIO_NAND_D0 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(4), // GPIO_NAND_D1 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(5), // GPIO_NAND_D2 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(6), // GPIO_NAND_D3 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPG1 ---------------------------- + { + .num = S5PV210_GPG1(0), // GPIO_WLAN_SDIO_CLK + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(1), // GPIO_WLAN_SDIO_CMD + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(2), // GPIO_WLAN_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(3), // GPIO_WLAN_SDIO_D0 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(4), // GPIO_WLAN_SDIO_D1 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(5), // GPIO_WLAN_SDIO_D2 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(6), // GPIO_WLAN_SDIO_D3 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPG2 ---------------------------- + { + .num = S5PV210_GPG2(0), // GPIO_T_FLASH_CLK + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(1), // GPIO_T_FLASH_CMD + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(2), // GPIO_ALS_SDA_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(3), // GPIO_T_FLASH_D0 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(4), // GPIO_T_FLASH_D1 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(5), // GPIO_T_FLASH_D2 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(6), // GPIO_T_FLASH_D3 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPG3 ---------------------------- + { +#if defined(CONFIG_SAMSUNG_VIBRANT) + .num = S5PV210_GPG3(0), // GPIO_GPS_nRST + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPG3(0), // GPIO_GPS_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { +#if defined(CONFIG_SAMSUNG_VIBRANT) + .num = S5PV210_GPG3(1), // GPIO_GPS_PWR_EN + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPG3(1), // GPIO_GPS_PWR_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { +#if defined(CONFIG_SAMSUNG_GALAXYSB) + .num = S5PV210_GPG3(2), // GPIO_GPS_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPG3(2), // GPIO_GPS_CLK_INT + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { + .num = S5PV210_GPG3(3), // GPIO_TA_CURRENT_SEL_AP + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(4), // GPIO_BT_WAKE + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(5), // GPIO_WLAN_WAKE + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { +#if defined(CONFIG_SAMSUNG_GALAXYSB) + .num = S5PV210_GPG3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPG3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, + + // GPH0 ---------------------------- + { + .num = S5PV210_GPH0(0), // GPIO_AP_PS_HOLD + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(1), // GPIO_ACC_INT + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(2), // GPIO_PS_VOUT + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(3), // GPIO_BUCK_1_EN_A + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(4), // GPIO_BUCK_1_EN_B + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(5), // GPIO_BUCK_2_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_DET_35 - 3.5" ear jack */ + .num = S5PV210_GPH0(6), // GPIO_DET_35 + .cfg = S3C_GPIO_SFN(GPIO_DET_35_AF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(7), // GPIO_AP_PMIC_IRQ + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPH1 ---------------------------- + { +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + .num = S5PV210_GPH1(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPH1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + .num = S5PV210_GPH1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPH1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { + .num = S5PV210_GPH1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_IRQ */ + .num = S5PV210_GPH1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_EN */ + .num = S5PV210_GPH1(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_FIRM */ + .num = S5PV210_GPH1(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(7), // GPIO_PHONE_ACTIVE + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPH2 ---------------------------- + { + .num = S5PV210_GPH2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_EAR_SEND_END_35 */ + .num = S5PV210_GPH2(2), // GPIO_EAR_SEND_END35, GPIO_KBC2 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(4), // GPIO_WLAN_HOST_WAKE + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(5), // GPIO_BT_HOST_WAKE + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(6), // GPIO_nPOWER + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(7), // GPIO_JACK_nINT + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPH3 ---------------------------- + { + .num = S5PV210_GPH3(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(1), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(2), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(4), // GPIO_T_FLASH_DETECT + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) /* HOME Key */ + .num = S5PV210_GPH3(5), // GPIO_MSENSE_IRQ + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPH3(5), // GPIO_MSENSE_IRQ + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { /* GPIO_EAR_SEND_END */ +#if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) + .num = S5PV210_GPH3(6), // GPIO_EAR_SEND_END + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPH3(6), // GPIO_EAR_SEND_END + .cfg = S3C_GPIO_SFN(GPIO_EAR_SEND_END_AF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { +#if defined(CONFIG_SAMSUNG_FASCINATE) + .num = S5PV210_GPH3(7), // GPIO_CP_RST + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPH3(7), // GPIO_CP_RST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, + + // GPI ---------------------------- + { + .num = S5PV210_GPI(0), // GPIO_CODEC_I2S_CLK + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(2), // GPIO_CODEC_I2S_WS + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(3), // GPIO_CODEC_I3S_DI + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(4), // GPIO_CODEC_I3S_DO + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPJ0 ---------------------------- + { + .num = S5PV210_GPJ0(0), // GPIO_MSENSE_SCL_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(2), // GPIO_HWREV_MODE0 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(3), // GPIO_HWREV_MODE1 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(4), // GPIO_HWREV_MODE2 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(5), // GPIO_TOUCH_INT + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(6), // GPIO_CAM_MEGA_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { +#if defined(CONFIG_SAMSUNG_GALAXYSB) + .num = S5PV210_GPJ0(7), // GPIO_CAM_MEGA_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPJ0(7), // GPIO_HWREV_MODE3 + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, + + // GPJ1 ---------------------------- + { + .num = S5PV210_GPJ1(0), // GPIO_PHONE_ON + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(1), // GPIO_VIBTONE_EN1 + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(3), // GPIO_TOUCH_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(4), // GPIO_PS_ON + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(5), // GPIO_CAM_MEGA_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPJ2 ---------------------------- +#if defined(CONFIG_SAMSUNG_GALAXYSB) + { + .num = S5PV210_GPJ2(0), // GPIO_CAM_FLASH_EN + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(1), // GPIO_CAM_FLASH_SET + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#else + { + .num = S5PV210_GPJ2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#endif + { + .num = S5PV210_GPJ2(2), // GPIO_OLED_DET + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { +#if defined(CONFIG_SAMSUNG_GALAXYSB) + .num = S5PV210_GPJ2(3), // GPIO_CODEC_XTAL_EN + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPJ2(3), // GPIO_CODEC_XTAL_EN + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { + .num = S5PV210_GPJ2(4), // GPIO_FM_INT + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_UP, + .drv = S3C_GPIO_DRVSTR_1X, + }, { +#if defined(CONFIG_SAMSUNG_VIBRANT) + .num = S5PV210_GPJ2(5), // GPIO_MICBIAS_EN2 + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPJ2(5), // GPIO_FM_RST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { +#if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_VIBRANT) || defined(CONFIG_SAMSUNG_GALAXYS) + .num = S5PV210_GPJ2(6), // GPIO_EARPATH_SEL + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, +#else + .num = S5PV210_GPJ2(6), // GPIO_EARPATH_SEL + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +#endif + }, { + .num = S5PV210_GPJ2(7), // GPIO_MASSMEMORY_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPJ3 ---------------------------- + { + .num = S5PV210_GPJ3(0), // _3_TOUCH_SDA_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(1), // _3_TOUCH_SCL_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(2), // _3_GPIO_TOUCH_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_EAR_ADC_SEL */ + .num = S5PV210_GPJ3(3), // _3_GPIO_TOUCH_CE + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(4), // GPIO_USB_SDA_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(5), // GPIO_USB_SCL_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(6), // GPIO_AP_SDA_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(7), // GPIO_AP_SCL_28V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // GPJ4 ---------------------------- + { + .num = S5PV210_GPJ4(0), // GPIO_AP_PMIC_SDA + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(1), // _3_GPIO_TOUCH_INT + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(2), // GPIO_MICBIAS_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(3), // GPIO_AP_PMIC_SCL + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(4), // GPIO_TV_EN, GPIO_EAR_MICBIAS_EN +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, +#else + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, +#endif + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // MP01 ---------------------------- + { + .num = S5PV210_MP01(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(2), // GPIO_SUB_DISPLAY_CS + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(5), // GPIO_DIC_ID + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // MP02 ---------------------------- + { + .num = S5PV210_MP02(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // MP03 ---------------------------- + { + .num = S5PV210_MP03(3), // GPIO_PDA_ACTIVE + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(5), // GPIO_CP_nRST + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(7), // GPIO_PCM_SEL + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // MP04 ---------------------------- + { + .num = S5PV210_MP04(0), // GPIO_USB_SEL + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(4), // GPIO_A1026_SCL + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(5), // GPIO_A1026_SDA + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + // MP05 ---------------------------- + { + .num = S5PV210_MP05(0), // FUEL_SCL_18V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(1), // FUEL_SDA_18V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(2), // GPIO_AP_SCL_18V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(3), // GPIO_AP_SDA_18V + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +}; + +void s3c_config_gpio_table(void) +{ + u32 i, gpio; + + for (i = 0; i < ARRAY_SIZE(aries_init_gpios); i++) { + gpio = aries_init_gpios[i].num; + if (system_rev <= 0x07 && gpio == S5PV210_GPJ3(3)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ONE); + } else if (gpio <= S5PV210_MP05(7)) { + s3c_gpio_cfgpin(gpio, aries_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, aries_init_gpios[i].pud); + + if (aries_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, aries_init_gpios[i].val); + + s3c_gpio_set_drvstrength(gpio, aries_init_gpios[i].drv); + } + } +#ifdef CONFIG_SAMSUNG_FASCINATE + s3c_gpio_set_drvstrength(S5PV210_GPH3(7), S3C_GPIO_DRVSTR_4X); +#endif +} + +#define S5PV210_PS_HOLD_CONTROL_REG (S3C_VA_SYS+0xE81C) +static void aries_power_off(void) +{ + while (1) { + /* Check reboot charging */ + if (set_cable_status) { + /* watchdog reset */ + pr_info("%s: charger connected, rebooting\n", __func__); + writel(3, S5P_INFORM6); + arch_reset('r', NULL); + pr_crit("%s: waiting for reset!\n", __func__); + while (1); + } + + /* wait for power button release */ + if (gpio_get_value(GPIO_nPOWER)) { + pr_info("%s: set PS_HOLD low\n", __func__); + + /* PS_HOLD high PS_HOLD_CONTROL, R/W, 0xE010_E81C */ + writel(readl(S5PV210_PS_HOLD_CONTROL_REG) & 0xFFFFFEFF, + S5PV210_PS_HOLD_CONTROL_REG); + + pr_crit("%s: should not reach here!\n", __func__); + } + + /* if power button is not released, wait and check TA again */ + pr_info("%s: PowerButton is not released.\n", __func__); + mdelay(1000); + } +} + +/* this table only for B4 board */ +static unsigned int aries_sleep_gpio_table[][3] = { + + // GPA0 --------------------------------------------------- + { S5PV210_GPA0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_RXD + { S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_TXD + { S5PV210_GPA0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_CTS + { S5PV210_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_BT_UART_RTS +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_SAMSUNG_VIBRANT) + { S5PV210_GPA0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else + { S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + + // GPA1 --------------------------------------------------- + { S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_FASCINATE) + { S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else + { S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + { S5PV210_GPA1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPB ---------------------------------------------------- +#if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) + { S5PV210_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VGA_nSTBY + { S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MSENSE_nRST + { S5PV210_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_CAM_VGA_nRST +#else + { S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + +#if defined(CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, // S5PV210_GPJ0(5) +#else + { S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#endif + { S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPB(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // S5PV210_GPB(3) +#else + { S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + { S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPC0 --------------------------------------------------- + { S5PV210_GPC0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPC1 --------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPC1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPC10 +#else + { S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC10 +#endif + { S5PV210_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPC1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPC12 +#else + { S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPC12 +#endif + { S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // GPD0 --------------------------------------------------- + { S5PV210_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // GPD1 --------------------------------------------------- + { S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD12 + { S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPD13 +#else + { S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + { S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // GPE0 --------------------------------------------------- + { S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // GPE1 --------------------------------------------------- + { S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // GPF0 --------------------------------------------------- + { S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPF1 --------------------------------------------------- + { S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPF2 --------------------------------------------------- + { S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPF3 --------------------------------------------------- + { S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // GPG0 --------------------------------------------------- + { S5PV210_GPG0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#else + { S5PV210_GPG0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + { S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // GPIO_ALS_SCL_28V +#else + { S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, // GPIO_ALS_SCL_28V +#endif +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#else + { S5PV210_GPG0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + + // GPG1 --------------------------------------------------- + { S5PV210_GPG1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_CLK + { S5PV210_GPG1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_CMD + { S5PV210_GPG1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_nRST + { S5PV210_GPG1(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D0 + { S5PV210_GPG1(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D1 + { S5PV210_GPG1(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D2 + { S5PV210_GPG1(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_SDIO_D3 + + // GPG2 --------------------------------------------------- + { S5PV210_GPG2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CLK + { S5PV210_GPG2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_CMD +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_FASCINATE) + { S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_ALS_SDA_28V +#else + { S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_ALS_SDA_28V +#endif + { S5PV210_GPG2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D0 + { S5PV210_GPG2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D1 + { S5PV210_GPG2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D2 + { S5PV210_GPG2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_T_FLASH_D3 + + // GPG3 --------------------------------------------------- +#if defined (CONFIG_SAMSUNG_VIBRANT) + { S5PV210_GPG3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, + { S5PV210_GPG3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, +#else + { S5PV210_GPG3(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPG3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#else + { S5PV210_GPG3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_TA_CURRENT_SEL_AP +#else + { S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, //GPIO_TA_CURRENT_SEL_AP +#endif + { S5PV210_GPG3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_BT_WAKE + { S5PV210_GPG3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_WLAN_WAKE +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPG3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPG36 +#elif defined (CONFIG_SAMSUNG_VIBRANT) + { S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPG36 +#else + { S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPG36 +#endif + + /* Alive part ending and off part start*/ + // GPI ---------------------------------------------------- + { S5PV210_GPI(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I2S_CLK +#if defined (CONFIG_SAMSUNG_CAPTIVATE) || defined (CONFIG_SAMSUNG_VIBRANT) + { S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI1 +#else + { S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI1 +#endif + { S5PV210_GPI(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I2S_WS + { S5PV210_GPI(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I3S_DI + { S5PV210_GPI(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_CODEC_I3S_DO +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI5 + { S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_GPI6 +#else + { S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI5 + { S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPI6 +#endif + + // GPJ0 --------------------------------------------------- + { S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK + { S5PV210_GPJ0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, // S5PV210_GPJ0(6) +#else + { S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + + // GPJ1 --------------------------------------------------- +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPJ1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_PHONE_ON +#elif defined(CONFIG_SAMSUNG_FASCINATE) + { S5PV210_GPJ1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, +#else + { S5PV210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + { S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ12 + { S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + // GPJ2 --------------------------------------------------- +#if defined(CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // S5PV210_GPJ0(3) + { S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // S5PV210_GPJ0(4) +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPJ2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ20 + { S5PV210_GPJ2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ21 +#else + { S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ20 + { S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ21 +#endif + { S5PV210_GPJ2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_OLED_DET +#if defined (CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // S5PV210_GPJ0(7) + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPJ2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ23 + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, //NC + { S5PV210_GPJ2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_SAMSUNG_VIBRANT) + { S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //NC + { S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#else + { S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ23 + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + { S5PV210_GPJ2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_SUB_MICBIAS_EN +#endif + { S5PV210_GPJ2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_EARPATH_SEL +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MASSMEMORY_EN +#else + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_MASSMEMORY_EN +#endif + + // GPJ3 --------------------------------------------------- + { S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_TOUCH_SDA_28V + { S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //_3_TOUCH_SCL_28V + { S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //_3_GPIO_TOUCH_EN +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPJ3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_GPJ33 +#else + { S5PV210_GPJ3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ33 +#endif + { S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_USB_SDA_28V + { S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_USB_SCL_28V + { S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SDA_28V + { S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SCL_28V + + // GPJ4 --------------------------------------------------- + { S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_EARMICBIAS_EN +#else + { S5PV210_GPJ4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_GPJ44 +#endif + + /* memory part */ + // MP01 --------------------------------------------------- + { S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // MP02 --------------------------------------------------- + { S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // MP03 --------------------------------------------------- + { S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined (CONFIG_SAMSUNG_VIBRANT) + { S5PV210_MP03(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //NC +#else + { S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, //GPIO_MP032 +#endif + { S5PV210_MP03(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // MP04 --------------------------------------------------- + { S5PV210_MP04(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + { S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP044 + { S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_MP045 +#else + { S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP044 + { S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP045 +#endif + { S5PV210_MP04(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // MP05 --------------------------------------------------- + { S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //FUEL_SCL_18V + { S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //FUEL_SDA_18V + { S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SCL_18V + { S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, //GPIO_AP_SDA_18V + { S5PV210_MP05(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP054 + { S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, //GPIO_MLCD_RST + { S5PV210_MP05(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, //GPIO_MP056 + { S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //GPIO_UART_SEL + + // MP06 --------------------------------------------------- + { S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + // MP07 --------------------------------------------------- + { S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /* Memory part ending and off part ending */ +}; + +void s3c_config_sleep_gpio_table(int array_size, unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +void s3c_config_sleep_gpio(void) +{ +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + // Reported to cause battery drain and other things on captivate, so we'll + // disable this for now. + return; +#endif + + /* setting the alive mode registers */ +#if defined(CONFIG_SAMSUNG_FASCINATE) || defined(CONFIG_SAMSUNG_CAPTIVATE) + s3c_gpio_cfgpin(S5PV210_GPH0(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(0), S3C_GPIO_PULL_DOWN); +#endif + + s3c_gpio_cfgpin(S5PV210_GPH0(1), S3C_GPIO_INPUT); +#if defined(CONFIG_SAMSUNG_FASCINATE) || defined(CONFIG_SAMSUNG_CAPTIVATE) + s3c_gpio_setpull(S5PV210_GPH0(1), S3C_GPIO_PULL_DOWN); +#else + s3c_gpio_setpull(S5PV210_GPH0(1), S3C_GPIO_PULL_NONE); +#endif + + s3c_gpio_cfgpin(S5PV210_GPH0(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(4), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(4), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(4), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(5), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(5), 0); + +#if defined(CONFIG_SAMSUNG_FASCINATE) || defined(CONFIG_SAMSUNG_CAPTIVATE) + s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP); +#endif + +#if defined(CONFIG_SAMSUNG_FASCINATE) + s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_DOWN); + gpio_set_value(S5PV210_GPH1(0), 0); +#elif defined(CONFIG_SAMSUNG_CAPTIVATE) && defined (CONFIG_A1026) // Dummy config for Audience chip - which we aren't using at the moment + s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(0), 1); +#else + s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_DOWN); +#endif + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) && defined (CONFIG_A1026) + s3c_gpio_cfgpin(S5PV210_GPH1(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(1), S3C_GPIO_PULL_DOWN); + gpio_set_value(S5PV210_GPH1(1), 1); +#else + s3c_gpio_cfgpin(S5PV210_GPH1(1), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(1), S3C_GPIO_PULL_DOWN); +#endif + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) && defined (CONFIG_A1026) + s3c_gpio_cfgpin(S5PV210_GPH1(2), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(2), S3C_GPIO_PULL_DOWN); + gpio_set_value(S5PV210_GPH1(2), 1); +#else + s3c_gpio_cfgpin(S5PV210_GPH1(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(2), S3C_GPIO_PULL_DOWN); +#endif + +#if defined(CONFIG_SAMSUNG_FASCINATE) + s3c_gpio_cfgpin(S5PV210_GPH1(4), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(4), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(4), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(5), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(5), S3C_GPIO_PULL_DOWN); +#else + s3c_gpio_cfgpin(S5PV210_GPH1(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(4), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(5), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(5), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(6), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(6), S3C_GPIO_PULL_DOWN); + +#endif + +#if !defined(CONFIG_SAMSUNG_CAPTIVATE) + s3c_gpio_cfgpin(S5PV210_GPH1(7), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(7), S3C_GPIO_PULL_NONE); +#endif + + s3c_gpio_cfgpin(S5PV210_GPH2(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(0), S3C_GPIO_PULL_DOWN); + +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + s3c_gpio_cfgpin(S5PV210_GPH2(1), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(1), S3C_GPIO_PULL_DOWN); +#else + s3c_gpio_cfgpin(S5PV210_GPH2(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(1), S3C_GPIO_PULL_NONE); +#endif + gpio_set_value(S5PV210_GPH2(1), 0); + +#if !defined(CONFIG_SAMSUNG_FASCINATE) + s3c_gpio_cfgpin(S5PV210_GPH2(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(2), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH2(3), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(3), S3C_GPIO_PULL_DOWN); +#endif + +#if defined(CONFIG_SAMSUNG_FASCINATE) + s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_EINT); + s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP); +#endif + + s3c_gpio_cfgpin(S5PV210_GPH3(0), S3C_GPIO_INPUT); +#if defined(CONFIG_SAMSUNG_FASCINATE) + s3c_gpio_setpull(S5PV210_GPH3(3), S3C_GPIO_PULL_UP); +#else + s3c_gpio_setpull(S5PV210_GPH3(0), S3C_GPIO_PULL_DOWN); +#endif + +#if defined(CONFIG_SAMSUNG_FASCINATE) + s3c_gpio_cfgpin(S5PV210_GPH3(3), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(3), S3C_GPIO_PULL_UP); +#elif !defined(CONFIG_SAMSUNG_CAPTIVATE) + s3c_gpio_cfgpin(S5PV210_GPH3(3), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(3), S3C_GPIO_PULL_DOWN); +#endif + +#if defined(CONFIG_SAMSUNG_FASCINATE) + s3c_gpio_cfgpin(S5PV210_GPH3(4), S3C_GPIO_EINT); + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_UP); +#endif + +#if defined(CONFIG_SAMSUNG_FASCINATE) || defined(CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_VIBRANT) + s3c_gpio_cfgpin(S5PV210_GPH3(5), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(5), S3C_GPIO_PULL_DOWN); +#endif + + s3c_gpio_cfgpin(S5PV210_GPH3(7), S3C_GPIO_OUTPUT); +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + s3c_gpio_setpull(S5PV210_GPH3(7), S3C_GPIO_PULL_UP); +#else + s3c_gpio_setpull(S5PV210_GPH3(7), S3C_GPIO_PULL_NONE); +#endif + gpio_set_value(S5PV210_GPH2(3), 1); + +#if !defined(CONFIG_SAMSUNG_FASCINATE) + if (gpio_get_value(GPIO_PS_ON)) { + s3c_gpio_slp_setpull_updown(GPIO_ALS_SDA_28V, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_setpull_updown(GPIO_ALS_SCL_28V, S3C_GPIO_PULL_NONE); + } else { + s3c_gpio_setpull(GPIO_PS_VOUT, S3C_GPIO_PULL_DOWN); + } +#endif +} +EXPORT_SYMBOL(s3c_config_sleep_gpio); + +static unsigned int wlan_sdio_on_table[][4] = { + {GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, +}; + +static unsigned int wlan_sdio_off_table[][4] = { + {GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, +}; + +static int wlan_power_en(int onoff) +{ + if (onoff) { + s3c_gpio_cfgpin(GPIO_WLAN_HOST_WAKE, + S3C_GPIO_SFN(GPIO_WLAN_HOST_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_HOST_WAKE, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_WLAN_WAKE, + S3C_GPIO_SFN(GPIO_WLAN_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_WAKE, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_WAKE, GPIO_LEVEL_LOW); + + s3c_gpio_cfgpin(GPIO_WLAN_nRST, + S3C_GPIO_SFN(GPIO_WLAN_nRST_AF)); + s3c_gpio_setpull(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + msleep(80); + } else { + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + if (gpio_get_value(GPIO_BT_nRST) == 0) { + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + } + } + return 0; +} + +static int wlan_reset_en(int onoff) +{ + gpio_set_value(GPIO_WLAN_nRST, + onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); + return 0; +} + +static int wlan_carddetect_en(int onoff) +{ + u32 i; + u32 sdio; + + if (onoff) { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_on_table); i++) { + sdio = wlan_sdio_on_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wlan_sdio_on_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_on_table[i][3]); + if (wlan_sdio_on_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_on_table[i][2]); + } + } else { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_off_table); i++) { + sdio = wlan_sdio_off_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wlan_sdio_off_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_off_table[i][3]); + if (wlan_sdio_off_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_off_table[i][2]); + } + } + udelay(5); + + sdhci_s3c_force_presence_change(&s3c_device_hsmmc1); + return 0; +} + +static struct resource wifi_resources[] = { + [0] = { + .name = "bcm4329_wlan_irq", + .start = IRQ_EINT(20), + .end = IRQ_EINT(20), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = { + {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)} +}; + +static void *aries_mem_prealloc(int section, unsigned long size) +{ + if (section == PREALLOC_WLAN_SEC_NUM) + return wlan_static_skb; + + if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM)) + return NULL; + + if (wifi_mem_array[section].size < size) + return NULL; + + return wifi_mem_array[section].mem_ptr; +} + +int __init aries_init_wifi_mem(void) +{ + int i; + int j; + + for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) { + wlan_static_skb[i] = dev_alloc_skb( + ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192)); + + if (!wlan_static_skb[i]) + goto err_skb_alloc; + } + + for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) { + wifi_mem_array[i].mem_ptr = + kmalloc(wifi_mem_array[i].size, GFP_KERNEL); + + if (!wifi_mem_array[i].mem_ptr) + goto err_mem_alloc; + } + return 0; + + err_mem_alloc: + pr_err("Failed to mem_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + kfree(wifi_mem_array[j].mem_ptr); + + i = WLAN_SKB_BUF_NUM; + + err_skb_alloc: + pr_err("Failed to skb_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + dev_kfree_skb(wlan_static_skb[j]); + + return -ENOMEM; +} + +/* Customized Locale table : OPTIONAL feature */ +#define WLC_CNTRY_BUF_SZ 4 +typedef struct cntry_locales_custom { + char iso_abbrev[WLC_CNTRY_BUF_SZ]; + char custom_locale[WLC_CNTRY_BUF_SZ]; + int custom_locale_rev; +} cntry_locales_custom_t; + +static cntry_locales_custom_t aries_wifi_translate_custom_table[] = { +/* Table should be filled out based on custom platform regulatory requirement */ + {"", "XY", 4}, /* universal */ + {"US", "US", 69}, /* input ISO "US" to : US regrev 69 */ + {"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */ + {"EU", "EU", 5}, /* European union countries */ + {"AT", "EU", 5}, + {"BE", "EU", 5}, + {"BG", "EU", 5}, + {"CY", "EU", 5}, + {"CZ", "EU", 5}, + {"DK", "EU", 5}, + {"EE", "EU", 5}, + {"FI", "EU", 5}, + {"FR", "EU", 5}, + {"DE", "EU", 5}, + {"GR", "EU", 5}, + {"HU", "EU", 5}, + {"IE", "EU", 5}, + {"IT", "EU", 5}, + {"LV", "EU", 5}, + {"LI", "EU", 5}, + {"LT", "EU", 5}, + {"LU", "EU", 5}, + {"MT", "EU", 5}, + {"NL", "EU", 5}, + {"PL", "EU", 5}, + {"PT", "EU", 5}, + {"RO", "EU", 5}, + {"SK", "EU", 5}, + {"SI", "EU", 5}, + {"ES", "EU", 5}, + {"SE", "EU", 5}, + {"GB", "EU", 5}, /* input ISO "GB" to : EU regrev 05 */ + {"IL", "IL", 0}, + {"CH", "CH", 0}, + {"TR", "TR", 0}, + {"NO", "NO", 0}, + {"KR", "XY", 3}, + {"AU", "XY", 3}, + {"CN", "XY", 3}, /* input ISO "CN" to : XY regrev 03 */ + {"TW", "XY", 3}, + {"AR", "XY", 3}, + {"MX", "XY", 3} +}; + +static void *aries_wifi_get_country_code(char *ccode) +{ + int size = ARRAY_SIZE(aries_wifi_translate_custom_table); + int i; + + if (!ccode) + return NULL; + + for (i = 0; i < size; i++) + if (strcmp(ccode, aries_wifi_translate_custom_table[i].iso_abbrev) == 0) + return &aries_wifi_translate_custom_table[i]; + return &aries_wifi_translate_custom_table[0]; +} + +static struct wifi_platform_data wifi_pdata = { + .set_power = wlan_power_en, + .set_reset = wlan_reset_en, + .set_carddetect = wlan_carddetect_en, + .mem_prealloc = aries_mem_prealloc, + .get_country_code = aries_wifi_get_country_code, +}; + +static struct platform_device sec_device_wifi = { + .name = "bcm4329_wlan", + .id = 1, + .num_resources = ARRAY_SIZE(wifi_resources), + .resource = wifi_resources, + .dev = { + .platform_data = &wifi_pdata, + }, +}; + +static struct platform_device watchdog_device = { + .name = "watchdog", + .id = -1, +}; + +static struct platform_device *aries_devices[] __initdata = { + &watchdog_device, +#ifdef CONFIG_FIQ_DEBUGGER + &s5pv210_device_fiqdbg_uart2, +#endif + &s5p_device_onenand, +#ifdef CONFIG_RTC_DRV_S3C + &s5p_device_rtc, +#endif + &aries_input_device, + + &s5pv210_device_iis0, + &s3c_device_wdt, + +#ifdef CONFIG_FB_S3C + &s3c_device_fb, +#endif + +#ifdef CONFIG_VIDEO_MFC50 + &s3c_device_mfc, +#endif +#ifdef CONFIG_S5P_ADC + &s3c_device_adc, +#endif +#ifdef CONFIG_VIDEO_FIMC + &s3c_device_fimc0, + &s3c_device_fimc1, + &s3c_device_fimc2, +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + &s3c_device_jpeg, +#endif + + &s3c_device_g3d, + &s3c_device_lcd, + +#ifdef CONFIG_FB_S3C_TL2796 + &s3c_device_spi_gpio, +#endif + &sec_device_jack, + + &s3c_device_i2c0, +#if defined(CONFIG_S3C_DEV_I2C1) + &s3c_device_i2c1, +#endif + +#if defined(CONFIG_S3C_DEV_I2C2) + &s3c_device_i2c2, +#endif + &aries_s3c_device_i2c4, + &aries_s3c_device_i2c5, /* accel sensor */ + &aries_s3c_device_i2c6, + &aries_s3c_device_i2c7, +#if defined(CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) + &s3c_device_i2c8, /* si470x: fm radio */ +#endif + &s3c_device_i2c9, /* max1704x:fuel_guage */ + &s3c_device_i2c11, /* optical sensor */ + &s3c_device_i2c12, /* magnetic sensor */ +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + &s3c_device_i2c13, +#endif +#ifdef CONFIG_USB_GADGET + &s3c_device_usbgadget, +#endif +#ifdef CONFIG_USB_ANDROID + &s3c_device_android_usb, +#ifdef CONFIG_USB_ANDROID_MASS_STORAGE + &s3c_device_usb_mass_storage, +#endif +#ifdef CONFIG_USB_ANDROID_RNDIS + &s3c_device_rndis, +#endif +#endif + +#ifdef CONFIG_PHONE_ARIES_CDMA + &sec_device_dpram, +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + &s3c_device_hsmmc0, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + &s3c_device_hsmmc1, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + &s3c_device_hsmmc2, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + &s3c_device_hsmmc3, +#endif +#ifdef CONFIG_VIDEO_TV20 + &s5p_device_tvout, +#endif + &sec_device_battery, + &s3c_device_i2c10, + +#ifdef CONFIG_S5PV210_POWER_DOMAIN + &s5pv210_pd_audio, + &s5pv210_pd_cam, + &s5pv210_pd_tv, + &s5pv210_pd_lcd, + &s5pv210_pd_g3d, + &s5pv210_pd_mfc, +#endif + +#ifdef CONFIG_ANDROID_PMEM + &pmem_device, + &pmem_gpu1_device, + &pmem_adsp_device, +#endif + +#ifdef CONFIG_HAVE_PWM + &s3c_device_timer[0], + &s3c_device_timer[1], + &s3c_device_timer[2], + &s3c_device_timer[3], +#endif + +#ifdef CONFIG_CPU_FREQ + &s5pv210_device_cpufreq, +#endif + + &sec_device_rfkill, + &sec_device_btsleep, + &ram_console_device, + &sec_device_wifi, + &samsung_asoc_dma, +}; + +static void __init aries_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s5pv210_gpiolib_init(); + s3c24xx_init_uarts(aries_uartcfgs, ARRAY_SIZE(aries_uartcfgs)); + #ifndef CONFIG_S5P_HIGH_RES_TIMERS + s5p_set_timer_source(S5P_PWM3, S5P_PWM4); + #endif + s5p_reserve_bootmem(aries_media_devs, + ARRAY_SIZE(aries_media_devs), S5P_RANGE_MFC); +#ifdef CONFIG_MTD_ONENAND + s5p_device_onenand.name = "s5pc110-onenand"; +#endif +} + +unsigned int pm_debug_scratchpad; + +static unsigned int ram_console_start; +static unsigned int ram_console_size; + +static void __init aries_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, + struct meminfo *mi) +{ + mi->bank[0].start = 0x30000000; + mi->bank[0].size = 80 * SZ_1M; + + mi->bank[1].start = 0x40000000; + mi->bank[1].size = 256 * SZ_1M; + + mi->bank[2].start = 0x50000000; + /* 1M for ram_console buffer */ + mi->bank[2].size = 127 * SZ_1M; + mi->nr_banks = 3; + + ram_console_start = mi->bank[2].start + mi->bank[2].size; + ram_console_size = SZ_1M - SZ_4K; + + pm_debug_scratchpad = ram_console_start + ram_console_size; +} + +/* this function are used to detect s5pc110 chip version temporally */ +int s5pc110_version ; + +void _hw_version_check(void) +{ + void __iomem *phy_address ; + int temp; + + phy_address = ioremap(0x40, 1); + + temp = __raw_readl(phy_address); + + if (temp == 0xE59F010C) + s5pc110_version = 0; + else + s5pc110_version = 1; + + printk(KERN_INFO "S5PC110 Hardware version : EVT%d\n", + s5pc110_version); + + iounmap(phy_address); +} + +/* + * Temporally used + * return value 0 -> EVT 0 + * value 1 -> evt 1 + */ + +int hw_version_check(void) +{ + return s5pc110_version ; +} +EXPORT_SYMBOL(hw_version_check); + +static void aries_init_gpio(void) +{ + s3c_config_gpio_table(); + s3c_config_sleep_gpio_table(ARRAY_SIZE(aries_sleep_gpio_table), + aries_sleep_gpio_table); +} + +static void __init fsa9480_gpio_init(void) +{ + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_JACK_nINT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_JACK_nINT, S3C_GPIO_PULL_NONE); +} + +#if defined (CONFIG_SAMSUNG_CAPTIVATE) +static void __init fuelgauge_gpio_init(void) +{ + s3c_gpio_cfgpin(GPIO_KBR3, S5PV210_GPH3_3_EXT_INT33_3); + s3c_gpio_setpull(GPIO_KBR3, S3C_GPIO_PULL_NONE); +} +#endif + +static void __init setup_ram_console_mem(void) +{ + ram_console_resource[0].start = ram_console_start; + ram_console_resource[0].end = ram_console_start + ram_console_size - 1; +} + +static void __init sound_init(void) +{ + u32 reg; + + reg = __raw_readl(S5P_OTHERS); + reg &= ~(0x3 << 8); + reg |= 3 << 8; + __raw_writel(reg, S5P_OTHERS); + + reg = __raw_readl(S5P_CLK_OUT); + reg &= ~(0x1f << 12); + reg |= 19 << 12; + __raw_writel(reg, S5P_CLK_OUT); + + reg = __raw_readl(S5P_CLK_OUT); + reg &= ~0x1; + reg |= 0x1; + __raw_writel(reg, S5P_CLK_OUT); + +#if defined(CONFIG_SAMSUNG_VIBRANT) + if((HWREV == 0x0A) || (HWREV == 0x0C) || (HWREV == 0x0D) || (HWREV == 0x0E) ) //0x0A:00, 0x0C:00, 0x0D:01, 0x0E:05 + gpio_request(GPIO_MICBIAS_EN, "micbias_enable"); + else { + gpio_request(GPIO_MICBIAS_EN2, "micbias_enable2"); + gpio_request(GPIO_MICBIAS_EN, "micbias_enable"); + } +#else + gpio_request(GPIO_MICBIAS_EN, "micbias_enable"); +#endif +} + +static bool console_flushed; + +static void flush_console(void) +{ + if (console_flushed) + return; + + console_flushed = true; + + printk("\n"); + pr_emerg("Restarting %s\n", linux_banner); + if (!is_console_locked()) + return; + + mdelay(50); + + local_irq_disable(); + if (console_trylock()) + pr_emerg("flush_console: console was locked! busting!\n"); + else + pr_emerg("flush_console: console was locked!\n"); + console_unlock(); +} + +static void aries_pm_restart(char mode, const char *cmd) +{ + flush_console(); + + /* On a normal reboot, INFORM6 will contain a small integer + * reason code from the notifier hook. On a panic, it will + * contain the 0xee we set at boot. Write 0xbb to differentiate + * a watchdog-timeout-and-reboot (0xee) from a controlled reboot + * (0xbb) + */ + if (__raw_readl(S5P_INFORM6) == 0xee) + __raw_writel(0xbb, S5P_INFORM6); + + arm_machine_restart(mode, cmd); +} + +// Ugly hack to inject parameters (e.g. device serial, bootmode) into /proc/cmdline +static void __init aries_inject_cmdline(void) { + char *new_command_line; + int bootmode = __raw_readl(S5P_INFORM6); + int size; + + size = strlen(boot_command_line); + new_command_line = kmalloc(size + 40 + 11, GFP_KERNEL); + strcpy(new_command_line, saved_command_line); + size += sprintf(new_command_line + size, " androidboot.serialno=%08X%08X", + system_serial_high, system_serial_low); + + // Only write bootmode when less than 10 to prevent confusion with watchdog + // reboot (0xee = 238) + if (bootmode < 10) { + size += sprintf(new_command_line + size, " bootmode=%d", bootmode); + } + + saved_command_line = new_command_line; +} + +static void __init aries_machine_init(void) +{ + arm_pm_restart = aries_pm_restart; + + setup_ram_console_mem(); + aries_inject_cmdline(); + platform_add_devices(aries_devices, ARRAY_SIZE(aries_devices)); + + /* smb380 */ + /* platform_device_register(&aries_s3c_device_i2c5); */ + + /* Find out S5PC110 chip version */ + _hw_version_check(); + + pm_power_off = aries_power_off ; + + s3c_gpio_cfgpin(GPIO_HWREV_MODE0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE0, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE1, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE1, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE2, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE2, S3C_GPIO_PULL_NONE); + HWREV = gpio_get_value(GPIO_HWREV_MODE0); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE1) << 1); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE2) << 2); + s3c_gpio_cfgpin(GPIO_HWREV_MODE3, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE3, S3C_GPIO_PULL_NONE); +#if defined(CONFIG_SAMSUNG_GALAXYSB) // ffosilva : OK + HWREV = 0xE; +#else + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE3) << 3); +#endif + printk(KERN_INFO "HWREV is 0x%x\n", HWREV); + + /*initialise the gpio's*/ + aries_init_gpio(); + +#ifdef CONFIG_ANDROID_PMEM + android_pmem_set_platdata(); +#endif + + /* headset/earjack detection */ +#if defined(CONFIG_SAMSUNG_CAPTIVATE) + gpio_request(GPIO_EAR_MICBIAS_EN, "ear_micbias_enable"); +#endif + + gpio_request(GPIO_TOUCH_EN, "touch en"); + + /* i2c */ + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_i2c2_set_platdata(NULL); + + /* H/W I2C lines */ + + /* mxt224 */ + mxt224_init(); + i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2)); + + /* wm8994 codec */ + sound_init(); + i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4)); + + /* accel sensor */ + i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5)); + + /* max8998 */ + i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6)); + + /* cypress touchkey */ + touch_keypad_gpio_init(); + i2c_register_board_info(10, i2c_devs10, ARRAY_SIZE(i2c_devs10)); + + /* FSA9480 */ + fsa9480_gpio_init(); + i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7)); + +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined (CONFIG_SAMSUNG_GALAXYSB) + /* fm radio */ + i2c_register_board_info(8, i2c_devs8, ARRAY_SIZE(i2c_devs8)); +#endif + +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + fuelgauge_gpio_init(); +#endif + + /* max17040 */ + i2c_register_board_info(9, i2c_devs9, ARRAY_SIZE(i2c_devs9)); + + /* optical sensor */ + gp2a_gpio_init(); + i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11)); + + /* yamaha magnetic sensor */ + i2c_register_board_info(12, i2c_devs12, ARRAY_SIZE(i2c_devs12)); + +#if defined (CONFIG_SAMSUNG_CAPTIVATE) + i2c_register_board_info(13, i2c_devs13, ARRAY_SIZE(i2c_devs13)); /* audience A1026 */ +#endif + + /* panel */ + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + s3cfb_set_platdata(&tl2796_data); + +#if defined(CONFIG_S5P_ADC) + s3c_adc_set_platdata(&s3c_adc_platform); +#endif + +#if defined(CONFIG_PM) + s3c_pm_init(); +#endif + +#ifdef CONFIG_VIDEO_FIMC + /* fimc */ + s3c_fimc0_set_platdata(&fimc_plat_lsi); + s3c_fimc1_set_platdata(&fimc_plat_lsi); + s3c_fimc2_set_platdata(&fimc_plat_lsi); +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + s3c_jpeg_set_platdata(&jpeg_plat); +#endif + +#ifdef CONFIG_VIDEO_MFC50 + /* mfc */ + s3c_mfc_set_platdata(NULL); +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + s5pv210_default_sdhci0(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + s5pv210_default_sdhci1(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + s5pv210_default_sdhci2(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + s5pv210_default_sdhci3(); +#endif +#ifdef CONFIG_S5PV210_SETUP_SDHCI + s3c_sdhci_set_platdata(); +#endif + +#ifdef CONFIG_CPU_FREQ + s5pv210_cpufreq_set_platdata(&smdkc110_cpufreq_plat); +#endif + + regulator_has_full_constraints(); + + register_reboot_notifier(&aries_reboot_notifier); + + aries_switch_init(); + + gps_gpio_init(); + + uart_switch_init(); + + aries_init_wifi_mem(); + + /* write something into the INFORM6 register that we can use to + * differentiate an unclear reboot from a clean reboot (which + * writes a small integer code to INFORM6). + */ + __raw_writel(0xee, S5P_INFORM6); +} + +#ifdef CONFIG_USB_SUPPORT +/* Initializes OTG Phy. */ +void otg_phy_init(void) +{ + /* USB PHY0 Enable */ + writel(readl(S5P_USB_PHY_CONTROL) | (0x1<<0), + S5P_USB_PHY_CONTROL); + writel((readl(S3C_USBOTG_PHYPWR) & ~(0x3<<3) & ~(0x1<<0)) | (0x1<<5), + S3C_USBOTG_PHYPWR); + writel((readl(S3C_USBOTG_PHYCLK) & ~(0x5<<2)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + writel((readl(S3C_USBOTG_RSTCON) & ~(0x3<<1)) | (0x1<<0), + S3C_USBOTG_RSTCON); + msleep(1); + writel(readl(S3C_USBOTG_RSTCON) & ~(0x7<<0), + S3C_USBOTG_RSTCON); + msleep(1); + + /* rising/falling time */ + writel(readl(S3C_USBOTG_PHYTUNE) | (0x1<<20), + S3C_USBOTG_PHYTUNE); + + /* set DC level as 6 (6%) */ + writel((readl(S3C_USBOTG_PHYTUNE) & ~(0xf)) | (0x1<<2) | (0x1<<1), + S3C_USBOTG_PHYTUNE); +} +EXPORT_SYMBOL(otg_phy_init); + +/* USB Control request data struct must be located here for DMA transfer */ +struct usb_ctrlrequest usb_ctrl __attribute__((aligned(64))); + +/* OTG PHY Power Off */ +void otg_phy_off(void) +{ + writel(readl(S3C_USBOTG_PHYPWR) | (0x3<<3), + S3C_USBOTG_PHYPWR); + writel(readl(S5P_USB_PHY_CONTROL) & ~(1<<0), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(otg_phy_off); + +void usb_host_phy_init(void) +{ + struct clk *otg_clk; + + otg_clk = clk_get(NULL, "otg"); + clk_enable(otg_clk); + + if (readl(S5P_USB_PHY_CONTROL) & (0x1<<1)) + return; + + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) | (0x1<<1), + S5P_USB_PHY_CONTROL); + __raw_writel((__raw_readl(S3C_USBOTG_PHYPWR) + & ~(0x1<<7) & ~(0x1<<6)) | (0x1<<8) | (0x1<<5), + S3C_USBOTG_PHYPWR); + __raw_writel((__raw_readl(S3C_USBOTG_PHYCLK) & ~(0x1<<7)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + __raw_writel((__raw_readl(S3C_USBOTG_RSTCON)) | (0x1<<4) | (0x1<<3), + S3C_USBOTG_RSTCON); + __raw_writel(__raw_readl(S3C_USBOTG_RSTCON) & ~(0x1<<4) & ~(0x1<<3), + S3C_USBOTG_RSTCON); +} +EXPORT_SYMBOL(usb_host_phy_init); + +void usb_host_phy_off(void) +{ + __raw_writel(__raw_readl(S3C_USBOTG_PHYPWR) | (0x1<<7)|(0x1<<6), + S3C_USBOTG_PHYPWR); + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) & ~(1<<1), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(usb_host_phy_off); +#endif + +MACHINE_START(ARIES, "aries") + .boot_params = S5P_PA_SDRAM + 0x100, + .fixup = aries_fixup, + .init_irq = s5pv210_init_irq, + .map_io = aries_map_io, + .init_machine = aries_machine_init, +#if defined(CONFIG_S5P_HIGH_RES_TIMERS) + .timer = &s5p_systimer, +#else + .timer = &s3c24xx_timer, +#endif +MACHINE_END + +void s3c_setup_uart_cfg_gpio(unsigned char port) +{ + switch (port) { + case 0: + s3c_gpio_cfgpin(GPIO_BT_RXD, S3C_GPIO_SFN(GPIO_BT_RXD_AF)); + s3c_gpio_setpull(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_TXD, S3C_GPIO_SFN(GPIO_BT_TXD_AF)); + s3c_gpio_setpull(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_CTS, S3C_GPIO_SFN(GPIO_BT_CTS_AF)); + s3c_gpio_setpull(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_RTS, S3C_GPIO_SFN(GPIO_BT_RTS_AF)); + s3c_gpio_setpull(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_TXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_CTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + break; + case 1: + s3c_gpio_cfgpin(GPIO_GPS_RXD, S3C_GPIO_SFN(GPIO_GPS_RXD_AF)); + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_GPS_TXD, S3C_GPIO_SFN(GPIO_GPS_TXD_AF)); + s3c_gpio_setpull(GPIO_GPS_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_CTS, S3C_GPIO_SFN(GPIO_GPS_CTS_AF)); + s3c_gpio_setpull(GPIO_GPS_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_RTS, S3C_GPIO_SFN(GPIO_GPS_RTS_AF)); + s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_NONE); + break; + case 2: + s3c_gpio_cfgpin(GPIO_AP_RXD, S3C_GPIO_SFN(GPIO_AP_RXD_AF)); + s3c_gpio_setpull(GPIO_AP_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_AP_TXD, S3C_GPIO_SFN(GPIO_AP_TXD_AF)); + s3c_gpio_setpull(GPIO_AP_TXD, S3C_GPIO_PULL_NONE); + break; + case 3: + s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(GPIO_FLM_RXD_AF)); + s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(GPIO_FLM_TXD_AF)); + s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); + break; + default: + break; + } +} +EXPORT_SYMBOL(s3c_setup_uart_cfg_gpio); diff --git a/arch/arm/mach-s5pv210/mach-herring.c b/arch/arm/mach-s5pv210/mach-herring.c new file mode 100755 index 0000000..993cb66 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-herring.c @@ -0,0 +1,6092 @@ +/* linux/arch/arm/mach-s5pv210/mach-herring.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/gpio.h> +#include <linux/gpio_event.h> +#include <linux/videodev2.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/mfd/max8998.h> +#include <linux/i2c/ak8973.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/usb/ch9.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/clk.h> +#include <linux/usb/ch9.h> +#include <linux/input/cypress-touchkey.h> +#include <linux/input.h> +#include <linux/irq.h> +#include <linux/skbuff.h> +#include <linux/console.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/system.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/gpio.h> +#include <mach/gpio-herring.h> +#include <mach/adc.h> +#include <mach/param.h> +#include <mach/system.h> + +#include <linux/usb/gadget.h> +#include <linux/fsa9480.h> +#include <linux/pn544.h> +#include <linux/notifier.h> +#include <linux/reboot.h> +#include <linux/wlan_plat.h> +#include <linux/mfd/wm8994/wm8994_pdata.h> + +#ifdef CONFIG_ANDROID_PMEM +#include <linux/android_pmem.h> +#endif +#include <plat/media.h> +#include <mach/media.h> + +#ifdef CONFIG_S5PV210_POWER_DOMAIN +#include <mach/power-domain.h> +#endif +#include <mach/cpu-freq-v210.h> + +#include <media/s5ka3dfx_platform.h> +#include <media/s5k4ecgx.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv210.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/fb.h> +#include <plat/mfc.h> +#include <plat/iic.h> +#include <plat/pm.h> +#include <plat/s5p-time.h> + +#include <plat/sdhci.h> +#include <plat/fimc.h> +#include <plat/jpeg.h> +#include <plat/clock.h> +#include <plat/regs-otg.h> +#include <linux/gp2a.h> +#include <linux/kr3dm.h> +#include <linux/input/k3g.h> +#include <../../../drivers/video/samsung/s3cfb.h> +#include <linux/sec_jack.h> +#include <linux/input/mxt224.h> +#include <linux/max17040_battery.h> +#include <linux/mfd/max8998.h> +#include <linux/regulator/max8893.h> +#include <linux/wimax/samsung/wimax732.h> +#include <linux/switch.h> + +#include "herring.h" + +struct class *sec_class; +EXPORT_SYMBOL(sec_class); + +struct device *switch_dev; +EXPORT_SYMBOL(switch_dev); + +void (*sec_set_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_set_param_value); + +void (*sec_get_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_get_param_value); + +#define REBOOT_MODE_FAST_BOOT 7 + +#define PREALLOC_WLAN_SEC_NUM 4 +#define PREALLOC_WLAN_BUF_NUM 160 +#define PREALLOC_WLAN_SECTION_HEADER 24 + +#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512) +#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024) + +#define WLAN_SKB_BUF_NUM 16 + +static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM]; + +struct wifi_mem_prealloc { + void *mem_ptr; + unsigned long size; +}; + +static int herring_notifier_call(struct notifier_block *this, + unsigned long code, void *_cmd) +{ + int mode = REBOOT_MODE_NONE; + + if ((code == SYS_RESTART) && _cmd) { + if (!strcmp((char *)_cmd, "recovery")) + mode = REBOOT_MODE_RECOVERY; + else if (!strcmp((char *)_cmd, "bootloader")) + mode = REBOOT_MODE_FAST_BOOT; + else + mode = REBOOT_MODE_NONE; + } + __raw_writel(mode, S5P_INFORM6); + + return NOTIFY_DONE; +} + +static struct notifier_block herring_reboot_notifier = { + .notifier_call = herring_notifier_call, +}; + +static void gps_gpio_init(void) +{ + struct device *gps_dev; + + gps_dev = device_create(sec_class, NULL, 0, NULL, "gps"); + if (IS_ERR(gps_dev)) { + pr_err("Failed to create device(gps)!\n"); + goto err; + } + + gpio_request(GPIO_GPS_nRST, "GPS_nRST"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_nRST, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_nRST, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_nRST, 1); + + gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_PWR_EN, 0); + + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + gpio_export(GPIO_GPS_nRST, 1); + gpio_export(GPIO_GPS_PWR_EN, 1); + + gpio_export_link(gps_dev, "GPS_nRST", GPIO_GPS_nRST); + gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN); + + err: + return; +} + +static void uart_switch_init(void) +{ + int ret; + struct device *uartswitch_dev; + + uartswitch_dev = device_create(sec_class, NULL, 0, NULL, "uart_switch"); + if (IS_ERR(uartswitch_dev)) { + pr_err("Failed to create device(uart_switch)!\n"); + return; + } + + ret = gpio_request(GPIO_UART_SEL, "UART_SEL"); + if (ret < 0) { + pr_err("Failed to request GPIO_UART_SEL!\n"); + return; + } + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + + gpio_direction_output(GPIO_UART_SEL, 1); + + gpio_export(GPIO_UART_SEL, 1); + + gpio_export_link(uartswitch_dev, "UART_SEL", GPIO_UART_SEL); + + if (herring_is_cdma_wimax_dev()) { + ret = gpio_request(GPIO_UART_SEL1, "UART_SEL1"); + if (ret < 0) { + pr_err("Failed to request GPIO_UART_SEL1!\n"); + gpio_free(GPIO_UART_SEL); + return; + } + + s3c_gpio_cfgpin(GPIO_UART_SEL1, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL1, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_UART_SEL1, 0); + + gpio_export(GPIO_UART_SEL1, 1); + gpio_export_link(uartswitch_dev, "UART_SEL1", GPIO_UART_SEL1); + } +} + +static void herring_switch_init(void) +{ + sec_class = class_create(THIS_MODULE, "sec"); + + if (IS_ERR(sec_class)) + pr_err("Failed to create class(sec)!\n"); + + switch_dev = device_create(sec_class, NULL, 0, NULL, "switch"); + + if (IS_ERR(switch_dev)) + pr_err("Failed to create device(switch)!\n"); +}; + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg herring_uartcfgs[] __initdata = { + { + .hwport = 0, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + .wake_peer = herring_bt_uart_wake_peer, + }, + { + .hwport = 1, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#ifndef CONFIG_FIQ_DEBUGGER + { + .hwport = 2, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#endif + { + .hwport = 3, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +}; + +#define S5PV210_LCD_WIDTH 480 +#define S5PV210_LCD_HEIGHT 800 + +static struct s3cfb_lcd s6e63m0 = { + .width = S5PV210_LCD_WIDTH, + .height = S5PV210_LCD_HEIGHT, + .p_width = 52, + .p_height = 86, + .bpp = 24, + .freq = 60, + + .timing = { + .h_fp = 16, + .h_bp = 16, + .h_sw = 2, + .v_fp = 28, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 1, + }, +}; + +static struct s3cfb_lcd nt35580 = { + .width = 480, + .height = 800, + .p_width = 52, + .p_height = 86, + .bpp = 24, + .freq = 60, + .timing = { + .h_fp = 10, + .h_bp = 20, + .h_sw = 10, + .v_fp = 6, + .v_fpe = 1, + .v_bp = 8, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 1, + }, +}; + +static struct s3cfb_lcd r61408 = { + .width = 480, + .height = 800, + .p_width = 52, + .p_height = 86, + .bpp = 24, + .freq = 60, + .timing = { + .h_fp = 100, + .h_bp = 2, + .h_sw = 2, + .v_fp = 8, + .v_fpe = 1, + .v_bp = 10, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 0, + }, +}; + +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0 (6144 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1 (4 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2 (6144 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0 (36864 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (36864 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD (S5PV210_LCD_WIDTH * \ + S5PV210_LCD_HEIGHT * 4 * \ + (CONFIG_FB_S3C_NR_BUFFERS + \ + (CONFIG_FB_S3C_NUM_OVLY_WIN * \ + CONFIG_FB_S3C_NUM_BUF_OVLY_WIN))) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG (8192 * SZ_1K) + +static struct s5p_media_device herring_media_devs[] = { + [0] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0, + .paddr = 0, + }, + [1] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1, + .paddr = 0, + }, + [2] = { + .id = S5P_MDEV_FIMC0, + .name = "fimc0", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0, + .paddr = 0, + }, + [3] = { + .id = S5P_MDEV_FIMC1, + .name = "fimc1", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1, + .paddr = 0, + }, + [4] = { + .id = S5P_MDEV_FIMC2, + .name = "fimc2", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2, + .paddr = 0, + }, + [5] = { + .id = S5P_MDEV_JPEG, + .name = "jpeg", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG, + .paddr = 0, + }, + [6] = { + .id = S5P_MDEV_FIMD, + .name = "fimd", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD, + .paddr = 0, + }, +}; + +#ifdef CONFIG_CPU_FREQ +static struct s5pv210_cpufreq_voltage smdkc110_cpufreq_volt[] = { + { + .freq = 1000000, + .varm = 1275000, + .vint = 1100000, + }, { + .freq = 800000, + .varm = 1200000, + .vint = 1100000, + }, { + .freq = 400000, + .varm = 1050000, + .vint = 1100000, + }, { + .freq = 200000, + .varm = 950000, + .vint = 1100000, + }, { + .freq = 100000, + .varm = 950000, + .vint = 1000000, + }, +}; + +static struct s5pv210_cpufreq_data smdkc110_cpufreq_plat = { + .volt = smdkc110_cpufreq_volt, + .size = ARRAY_SIZE(smdkc110_cpufreq_volt), +}; +#endif + +static struct regulator_consumer_supply ldo3_consumer[] = { + REGULATOR_SUPPLY("pd_io", "s3c-usbgadget") +}; + +static struct regulator_consumer_supply ldo7_consumer[] = { + { .supply = "vlcd", }, +}; + +static struct regulator_consumer_supply ldo8_consumer[] = { + REGULATOR_SUPPLY("pd_core", "s3c-usbgadget") +}; + +static struct regulator_consumer_supply ldo11_consumer[] = { + { .supply = "cam_af", }, +}; + +static struct regulator_consumer_supply ldo12_consumer[] = { + { .supply = "cam_sensor", }, +}; + +static struct regulator_consumer_supply ldo13_consumer[] = { + { .supply = "vga_vddio", }, +}; + +static struct regulator_consumer_supply ldo14_consumer[] = { + { .supply = "vga_dvdd", }, +}; + +static struct regulator_consumer_supply ldo15_consumer[] = { + { .supply = "cam_isp_host", }, +}; + +static struct regulator_consumer_supply ldo16_consumer[] = { + { .supply = "vga_avdd", }, +}; + +static struct regulator_consumer_supply ldo17_consumer[] = { + { .supply = "vcc_lcd", }, +}; + +static struct regulator_consumer_supply buck1_consumer[] = { + { .supply = "vddarm", }, +}; + +static struct regulator_consumer_supply buck2_consumer[] = { + { .supply = "vddint", }, +}; + +static struct regulator_consumer_supply buck4_consumer[] = { + { .supply = "cam_isp_core", }, +}; + +static struct regulator_init_data herring_ldo2_data = { + .constraints = { + .name = "VALIVE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data herring_ldo3_data = { + .constraints = { + .name = "VUSB_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), + .consumer_supplies = ldo3_consumer, +}; + +static struct regulator_init_data herring_ldo4_data = { + .constraints = { + .name = "VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, +}; + +static struct regulator_init_data herring_ldo7_data = { + .constraints = { + .name = "VLCD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), + .consumer_supplies = ldo7_consumer, +}; + +static struct regulator_init_data herring_ldo8_data = { + .constraints = { + .name = "VUSB_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), + .consumer_supplies = ldo8_consumer, +}; + +static struct regulator_init_data herring_ldo9_data = { + .constraints = { + .name = "VCC_2.8V_PDA", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data herring_ldo11_data = { + .constraints = { + .name = "CAM_AF_3.0V", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), + .consumer_supplies = ldo11_consumer, +}; + +static struct regulator_init_data herring_ldo12_data = { + .constraints = { + .name = "CAM_SENSOR_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo12_consumer), + .consumer_supplies = ldo12_consumer, +}; + +static struct regulator_init_data herring_ldo13_data = { + .constraints = { + .name = "VGA_VDDIO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo13_consumer), + .consumer_supplies = ldo13_consumer, +}; + +static struct regulator_init_data herring_ldo14_data = { + .constraints = { + .name = "VGA_DVDD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), + .consumer_supplies = ldo14_consumer, +}; + +static struct regulator_init_data herring_ldo15_data = { + .constraints = { + .name = "CAM_ISP_HOST_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo15_consumer), + .consumer_supplies = ldo15_consumer, +}; + +static struct regulator_init_data herring_ldo16_data = { + .constraints = { + .name = "VGA_AVDD_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo16_consumer), + .consumer_supplies = ldo16_consumer, +}; + +static struct regulator_init_data herring_ldo17_data = { + .constraints = { + .name = "VCC_3.0V_LCD", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), + .consumer_supplies = ldo17_consumer, +}; + +static struct regulator_init_data herring_buck1_data = { + .constraints = { + .name = "VDD_ARM", + .min_uV = 750000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1250000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), + .consumer_supplies = buck1_consumer, +}; + +static struct regulator_init_data herring_buck2_data = { + .constraints = { + .name = "VDD_INT", + .min_uV = 750000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1100000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), + .consumer_supplies = buck2_consumer, +}; + +static struct regulator_init_data herring_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data herring_buck4_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck4_consumer), + .consumer_supplies = buck4_consumer, +}; + +static struct max8998_regulator_data herring_regulators[] = { + { MAX8998_LDO2, &herring_ldo2_data }, + { MAX8998_LDO3, &herring_ldo3_data }, + { MAX8998_LDO4, &herring_ldo4_data }, + { MAX8998_LDO7, &herring_ldo7_data }, + { MAX8998_LDO8, &herring_ldo8_data }, + { MAX8998_LDO9, &herring_ldo9_data }, + { MAX8998_LDO11, &herring_ldo11_data }, + { MAX8998_LDO12, &herring_ldo12_data }, + { MAX8998_LDO13, &herring_ldo13_data }, + { MAX8998_LDO14, &herring_ldo14_data }, + { MAX8998_LDO15, &herring_ldo15_data }, + { MAX8998_LDO16, &herring_ldo16_data }, + { MAX8998_LDO17, &herring_ldo17_data }, + { MAX8998_BUCK1, &herring_buck1_data }, + { MAX8998_BUCK2, &herring_buck2_data }, + { MAX8998_BUCK3, &herring_buck3_data }, + { MAX8998_BUCK4, &herring_buck4_data }, +}; + +static struct max8998_regulator_data herring_cdma_wimax_regulators[] = { + { MAX8998_LDO2, &herring_ldo2_data }, + { MAX8998_LDO3, &herring_ldo3_data }, + { MAX8998_LDO4, &herring_ldo4_data }, + { MAX8998_LDO7, &herring_ldo7_data }, + { MAX8998_LDO8, &herring_ldo8_data }, + { MAX8998_LDO9, &herring_ldo9_data }, + { MAX8998_LDO11, &herring_ldo11_data }, + { MAX8998_LDO13, &herring_ldo13_data }, + { MAX8998_LDO14, &herring_ldo14_data }, + { MAX8998_LDO15, &herring_ldo15_data }, + { MAX8998_LDO16, &herring_ldo16_data }, + { MAX8998_LDO17, &herring_ldo17_data }, + { MAX8998_BUCK1, &herring_buck1_data }, + { MAX8998_BUCK2, &herring_buck2_data }, + { MAX8998_BUCK3, &herring_buck3_data }, + { MAX8998_BUCK4, &herring_buck4_data }, +}; + +static struct max8998_adc_table_data temper_table_oled[] = { + /* ADC, Temperature (C/10) */ + { 222, 700 }, + { 230, 690 }, + { 238, 680 }, + { 245, 670 }, + { 253, 660 }, + { 261, 650 }, + { 274, 640 }, + { 287, 630 }, + { 300, 620 }, + { 314, 610 }, + { 327, 600 }, + { 339, 590 }, + { 350, 580 }, + { 362, 570 }, + { 374, 560 }, + { 386, 550 }, + { 401, 540 }, + { 415, 530 }, + { 430, 520 }, + { 444, 510 }, + { 459, 500 }, + { 477, 490 }, + { 495, 480 }, + { 513, 470 }, + { 526, 460 }, + { 539, 450 }, + { 559, 440 }, + { 580, 430 }, + { 600, 420 }, + { 618, 410 }, + { 642, 400 }, + { 649, 390 }, + { 674, 380 }, + { 695, 370 }, + { 717, 360 }, + { 739, 350 }, + { 760, 340 }, + { 782, 330 }, + { 803, 320 }, + { 825, 310 }, + { 847, 300 }, + { 870, 290 }, + { 894, 280 }, + { 918, 270 }, + { 942, 260 }, + { 966, 250 }, + { 990, 240 }, + { 1014, 230 }, + { 1038, 220 }, + { 1062, 210 }, + { 1086, 200 }, + { 1110, 190 }, + { 1134, 180 }, + { 1158, 170 }, + { 1182, 160 }, + { 1206, 150 }, + { 1228, 140 }, + { 1251, 130 }, + { 1274, 120 }, + { 1297, 110 }, + { 1320, 100 }, + { 1341, 90 }, + { 1362, 80 }, + { 1384, 70 }, + { 1405, 60 }, + { 1427, 50 }, + { 1450, 40 }, + { 1474, 30 }, + { 1498, 20 }, + { 1514, 10 }, + { 1533, 0 }, + { 1544, (-10) }, + { 1567, (-20) }, + { 1585, (-30) }, + { 1604, (-40) }, + { 1623, (-50) }, + { 1641, (-60) }, + { 1659, (-70) }, + { 1678, (-80) }, + { 1697, (-90) }, + { 1715, (-100) }, +}; +static struct max8998_adc_table_data temper_table_tft[] = { + /* ADC, Temperature (C/10) */ + { 242, 700 }, + { 253, 690 }, + { 264, 680 }, + { 275, 670 }, + { 286, 660 }, + { 297, 650 }, + { 310, 640 }, + { 323, 630 }, + { 336, 620 }, + { 349, 610 }, + { 362, 600 }, + { 375, 590 }, + { 388, 580 }, + { 401, 570 }, + { 414, 560 }, + { 430, 550 }, + { 444, 540 }, + { 458, 530 }, + { 472, 520 }, + { 486, 510 }, + { 500, 500 }, + { 515, 490 }, + { 530, 480 }, + { 545, 470 }, + { 560, 460 }, + { 575, 450 }, + { 590, 440 }, + { 605, 430 }, + { 625, 420 }, + { 645, 410 }, + { 665, 400 }, + { 683, 390 }, + { 702, 380 }, + { 735, 370 }, + { 768, 360 }, + { 768, 350 }, + { 790, 340 }, + { 812, 330 }, + { 834, 320 }, + { 856, 310 }, + { 881, 300 }, + { 905, 290 }, + { 929, 280 }, + { 955, 270 }, + { 979, 260 }, + { 1002, 250 }, + { 1027, 240 }, + { 1053, 230 }, + { 1078, 220 }, + { 1105, 210 }, + { 1130, 200 }, + { 1151, 190 }, + { 1174, 180 }, + { 1195, 170 }, + { 1219, 160 }, + { 1237, 150 }, + { 1261, 140 }, + { 1285, 130 }, + { 1309, 120 }, + { 1331, 110 }, + { 1359, 100 }, + { 1381, 90 }, + { 1404, 80 }, + { 1426, 70 }, + { 1438, 60 }, + { 1470, 50 }, + { 1488, 40 }, + { 1506, 30 }, + { 1524, 20 }, + { 1532, 10 }, + { 1560, 0 }, + { 1586, (-10) }, + { 1604, (-20) }, + { 1614, (-30) }, + { 1622, (-40) }, + { 1630, (-50) }, + { 1648, (-60) }, + { 1666, (-70) }, + { 1684, (-80) }, + { 1702, (-90) }, + { 1720, (-100) }, +}; + +static struct max8998_adc_table_data temper_table_cdma_wimax_oled[] = { + /* ADC, Temperature (C/10) */ + { 116, 700 }, + { 122, 690 }, + { 128, 680 }, + { 134, 670 }, + { 140, 660 }, + { 146, 650 }, + { 152, 640 }, + { 158, 630 }, + { 164, 620 }, + { 170, 610 }, + { 176, 600 }, + { 182, 590 }, + { 188, 580 }, + { 194, 570 }, + { 200, 560 }, + { 206, 550 }, + { 212, 540 }, + { 218, 530 }, + { 222, 520 }, + { 230, 510 }, + { 238, 500 }, + { 245, 490 }, + { 260, 480 }, + { 290, 470 }, + { 325, 460 }, + { 360, 450 }, + { 395, 440 }, + { 430, 430 }, + { 465, 420 }, + { 500, 410 }, + { 535, 400 }, + { 575, 390 }, + { 615, 380 }, + { 642, 370 }, + { 695, 360 }, + { 717, 350 }, + { 737, 340 }, + { 760, 330 }, + { 782, 320 }, + { 803, 310 }, + { 825, 300 }, + { 847, 290 }, + { 870, 280 }, + { 900, 270 }, + { 942, 260 }, + { 966, 250 }, + { 990, 240 }, + { 1014, 230 }, + { 1038, 220 }, + { 1062, 210 }, + { 1086, 200 }, + { 1110, 190 }, + { 1134, 180 }, + { 1158, 170 }, + { 1182, 160 }, + { 1206, 150 }, + { 1228, 140 }, + { 1251, 130 }, + { 1274, 120 }, + { 1297, 110 }, + { 1320, 100 }, + { 1341, 90 }, + { 1362, 80 }, + { 1384, 70 }, + { 1405, 60 }, + { 1427, 50 }, + { 1450, 40 }, + { 1474, 30 }, + { 1498, 20 }, + { 1514, 10 }, + { 1533, 0 }, + { 1544, (-10) }, + { 1567, (-20) }, + { 1585, (-30) }, + { 1604, (-40) }, + { 1623, (-50) }, + { 1641, (-60) }, + { 1659, (-70) }, + { 1678, (-80) }, + { 1697, (-90) }, + { 1715, (-100) }, +}; + +struct max8998_charger_callbacks *callbacks; +static enum cable_type_t set_cable_status; + +static void max8998_charger_register_callbacks( + struct max8998_charger_callbacks *ptr) +{ + callbacks = ptr; + /* if there was a cable status change before the charger was + ready, send this now */ + if ((set_cable_status != 0) && callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static struct max8998_charger_data herring_charger = { + .register_callbacks = &max8998_charger_register_callbacks, +}; + +static void set_adc_table(void) +{ + if (!herring_is_tft_dev()) { + if (herring_is_cdma_wimax_dev()) { + herring_charger.adc_table = + temper_table_cdma_wimax_oled; + herring_charger.adc_array_size = + ARRAY_SIZE(temper_table_cdma_wimax_oled); + } else { + herring_charger.adc_table = temper_table_oled; + herring_charger.adc_array_size = + ARRAY_SIZE(temper_table_oled); + } + } else { + herring_charger.adc_table = temper_table_tft; + herring_charger.adc_array_size = + ARRAY_SIZE(temper_table_tft); + } +} + +static struct max8998_platform_data max8998_pdata = { + .num_regulators = ARRAY_SIZE(herring_regulators), + .regulators = herring_regulators, + .charger = &herring_charger, + /* Preloads must be in increasing order of voltage value */ + .buck1_voltage4 = 950000, + .buck1_voltage3 = 1050000, + .buck1_voltage2 = 1200000, + .buck1_voltage1 = 1275000, + .buck2_voltage2 = 1000000, + .buck2_voltage1 = 1100000, + .buck1_set1 = GPIO_BUCK_1_EN_A, + .buck1_set2 = GPIO_BUCK_1_EN_B, + .buck2_set3 = GPIO_BUCK_2_EN, + .buck1_default_idx = 1, + .buck2_default_idx = 0, +}; + +struct platform_device sec_device_dpram = { + .name = "dpram-device", + .id = -1, +}; + +static unsigned int lcd_type; +module_param_named(lcd_type, lcd_type, uint, 0444); +MODULE_PARM_DESC(lcd_type, "LCD type: default= sony, 1= hydis, 2= hitachi"); + +static void panel_cfg_gpio(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + } + + /* mDNIe SEL: why we shall write 0x2 ? */ +#ifdef CONFIG_FB_S3C_MDNIE + writel(0x1, S5P_MDNIE_SEL); +#else + writel(0x2, S5P_MDNIE_SEL); +#endif + + /* DISPLAY_CS */ + s3c_gpio_cfgpin(S5PV210_MP01(1), S3C_GPIO_SFN(1)); + /* DISPLAY_CLK */ + s3c_gpio_cfgpin(S5PV210_MP04(1), S3C_GPIO_SFN(1)); + /* DISPLAY_SO */ + s3c_gpio_cfgpin(S5PV210_MP04(2), S3C_GPIO_SFN(1)); + /* DISPLAY_SI */ + s3c_gpio_cfgpin(S5PV210_MP04(3), S3C_GPIO_SFN(1)); + + /* DISPLAY_CS */ + s3c_gpio_setpull(S5PV210_MP01(1), S3C_GPIO_PULL_NONE); + /* DISPLAY_CLK */ + s3c_gpio_setpull(S5PV210_MP04(1), S3C_GPIO_PULL_NONE); + /* DISPLAY_SO */ + s3c_gpio_setpull(S5PV210_MP04(2), S3C_GPIO_PULL_NONE); + /* DISPLAY_SI */ + s3c_gpio_setpull(S5PV210_MP04(3), S3C_GPIO_PULL_NONE); + + /* OLED_ID */ + if (herring_is_tft_dev()) { + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_DOWN); + } +} + +void lcd_cfg_gpio_early_suspend(void) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF0(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF1(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF2(i), 0); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF3(i), 0); + } + /* drive strength to min */ + writel(0x00000000, S5P_VA_GPIO + 0x12c); /* GPF0DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x14c); /* GPF1DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x16c); /* GPF2DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x18c); /* GPF3DRV */ + + /* OLED_DET */ + s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_OLED_DET, 0); + + /* LCD_RST */ + s3c_gpio_cfgpin(GPIO_MLCD_RST, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_MLCD_RST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_MLCD_RST, 0); + + /* DISPLAY_CS */ + s3c_gpio_cfgpin(GPIO_DISPLAY_CS, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_CS, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_CS, 0); + + /* DISPLAY_CLK */ + s3c_gpio_cfgpin(GPIO_DISPLAY_CLK, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_CLK, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_CLK, 0); + + /* DISPLAY_SO */ + /* + s3c_gpio_cfgpin(S5PV210_MP04(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_MP04(2), S3C_GPIO_PULL_DOWN); + */ + + /* DISPLAY_SI */ + s3c_gpio_cfgpin(GPIO_DISPLAY_SI, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_SI, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_SI, 0); + + /* OLED_ID */ + if (!herring_is_tft_dev()) { + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_DOWN); + /* gpio_set_value(GPIO_OLED_ID, 0); */ + } + + /* DIC_ID */ + s3c_gpio_cfgpin(GPIO_DIC_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_DOWN); + /* gpio_set_value(GPIO_DIC_ID, 0); */ +} +EXPORT_SYMBOL(lcd_cfg_gpio_early_suspend); + +void lcd_cfg_gpio_late_resume(void) +{ + /* OLED_DET */ + s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); + /* OLED_ID */ + if (!herring_is_tft_dev()) { + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_NONE); + /* gpio_set_value(GPIO_OLED_ID, 0); */ + } + /* DIC_ID */ + s3c_gpio_cfgpin(GPIO_DIC_ID, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_NONE); + /* gpio_set_value(GPIO_DIC_ID, 0); */ +} +EXPORT_SYMBOL(lcd_cfg_gpio_late_resume); + +static int panel_reset_lcd(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_MP05(5), "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request MP0(5) for " + "lcd reset control\n"); + return err; + } + + gpio_direction_output(S5PV210_MP05(5), 1); + msleep(10); + + gpio_set_value(S5PV210_MP05(5), 0); + msleep(10); + + gpio_set_value(S5PV210_MP05(5), 1); + msleep(10); + + gpio_free(S5PV210_MP05(5)); + + return 0; +} + +static int panel_backlight_on(struct platform_device *pdev) +{ + return 0; +} + +static struct s3c_platform_fb tl2796_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &s6e63m0, + .cfg_gpio = panel_cfg_gpio, + .backlight_on = panel_backlight_on, + .reset_lcd = panel_reset_lcd, +}; + +static struct s3c_platform_fb nt35580_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &nt35580, + .cfg_gpio = panel_cfg_gpio, + .backlight_on = panel_backlight_on, + .reset_lcd = panel_reset_lcd, +}; + +static struct s3c_platform_fb r61408_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &r61408, + .cfg_gpio = panel_cfg_gpio, + .backlight_on = panel_backlight_on, + .reset_lcd = panel_reset_lcd, +}; + +#define LCD_BUS_NUM 3 +#define DISPLAY_CS S5PV210_MP01(1) +#define SUB_DISPLAY_CS S5PV210_MP01(2) +#define DISPLAY_CLK S5PV210_MP04(1) +#define DISPLAY_SI S5PV210_MP04(3) + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "tl2796", + .platform_data = &herring_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +static struct spi_board_info spi_board_info_sony[] __initdata = { + { + .modalias = "nt35580", + .platform_data = &herring_sony_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +static struct spi_board_info spi_board_info_hydis[] __initdata = { + { + .modalias = "nt35580", + .platform_data = &herring_hydis_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +static struct spi_board_info spi_board_info_hitachi[] __initdata = { + { + .modalias = "nt35580", + .platform_data = &herring_hitachi_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + + +static struct spi_gpio_platform_data tl2796_spi_gpio_data = { + .sck = DISPLAY_CLK, + .mosi = DISPLAY_SI, + .miso = -1, + .num_chipselect = 2, +}; + +static struct platform_device s3c_device_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s3c_device_fb.dev, + .platform_data = &tl2796_spi_gpio_data, + }, +}; + +static struct i2c_gpio_platform_data herring_i2c4_platdata = { + .sda_pin = GPIO_AP_SDA_18V, + .scl_pin = GPIO_AP_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c4_device = { + .name = "i2c-gpio", + .id = 4, + .dev.platform_data = &herring_i2c4_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c5_platdata = { + .sda_pin = GPIO_AP_SDA_28V, + .scl_pin = GPIO_AP_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c5_device = { + .name = "i2c-gpio", + .id = 5, + .dev.platform_data = &herring_i2c5_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c6_platdata = { + .sda_pin = GPIO_AP_PMIC_SDA, + .scl_pin = GPIO_AP_PMIC_SCL, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c6_device = { + .name = "i2c-gpio", + .id = 6, + .dev.platform_data = &herring_i2c6_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c7_platdata = { + .sda_pin = GPIO_USB_SDA_28V, + .scl_pin = GPIO_USB_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c7_device = { + .name = "i2c-gpio", + .id = 7, + .dev.platform_data = &herring_i2c7_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c8_platdata = { + .sda_pin = GYRO_SDA_28V, + .scl_pin = GYRO_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c8_device = { + .name = "i2c-gpio", + .id = 8, + .dev.platform_data = &herring_i2c8_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c9_platdata = { + .sda_pin = FUEL_SDA_18V, + .scl_pin = FUEL_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c9_device = { + .name = "i2c-gpio", + .id = 9, + .dev.platform_data = &herring_i2c9_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c10_platdata = { + .sda_pin = _3_TOUCH_SDA_28V, + .scl_pin = _3_TOUCH_SCL_28V, + .udelay = 0, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c10_device = { + .name = "i2c-gpio", + .id = 10, + .dev.platform_data = &herring_i2c10_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c11_platdata = { + .sda_pin = GPIO_ALS_SDA_28V, + .scl_pin = GPIO_ALS_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c11_device = { + .name = "i2c-gpio", + .id = 11, + .dev.platform_data = &herring_i2c11_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c12_platdata = { + .sda_pin = GPIO_MSENSE_SDA_28V, + .scl_pin = GPIO_MSENSE_SCL_28V, + .udelay = 0, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c12_device = { + .name = "i2c-gpio", + .id = 12, + .dev.platform_data = &herring_i2c12_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c14_platdata = { + .sda_pin = NFC_SDA_18V, + .scl_pin = NFC_SCL_18V, + .udelay = 2, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c14_device = { + .name = "i2c-gpio", + .id = 14, + .dev.platform_data = &herring_i2c14_platdata, +}; + +/* max8893 wimax PMIC */ +static struct i2c_gpio_platform_data herring_i2c15_platdata = { + .sda_pin = GPIO_WIMAX_PM_SDA, + .scl_pin = GPIO_WIMAX_PM_SCL, +}; + +static struct platform_device herring_i2c15_device = { + .name = "i2c-gpio", + .id = 15, + .dev.platform_data = &herring_i2c15_platdata, +}; + +static struct regulator_init_data herring_max8893_buck_data = { + .constraints = { + .name = "max8893_buck", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo1_data = { + .constraints = { + .name = "max8893_ldo1", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo2_data = { + .constraints = { + .name = "max8893_ldo2", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo3_data = { + .constraints = { + .name = "max8893_ldo3", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo4_data = { + .constraints = { + .name = "max8893_ldo4", + .min_uV = 2900000, + .max_uV = 2900000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo5_data = { + .constraints = { + .name = "max8893_ldo5", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct max8893_subdev_data herring_max8893_subdev_data[] = { + { + .id = MAX8893_BUCK, + .initdata = &herring_max8893_buck_data, + }, + { + .id = MAX8893_LDO1, + .initdata = &herring_max8893_ldo1_data, + }, + { + .id = MAX8893_LDO2, + .initdata = &herring_max8893_ldo2_data, + }, + { + .id = MAX8893_LDO3, + .initdata = &herring_max8893_ldo3_data, + }, + { + .id = MAX8893_LDO4, + .initdata = &herring_max8893_ldo4_data, + }, + { + .id = MAX8893_LDO5, + .initdata = &herring_max8893_ldo5_data, + }, +}; + +static struct max8893_platform_data herring_max8893_pdata = { + .num_subdevs = ARRAY_SIZE(herring_max8893_subdev_data), + .subdevs = herring_max8893_subdev_data, +}; + +static struct i2c_board_info i2c_devs15[] __initdata = { + { + I2C_BOARD_INFO("max8893", 0x3E), + .platform_data = &herring_max8893_pdata, + }, +}; + +static struct wimax_cfg wimax_config; + +static unsigned int wimax_sdio_on_table[][4] = { + {GPIO_WIMAX_SDIO_CLK, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_CMD, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D0, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D1, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D2, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D3, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, +}; + +static unsigned int wimax_sdio_off_table[][4] = { + {GPIO_WIMAX_SDIO_CLK, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, +}; + +static int wimax_sdio_en(int onoff) +{ + u32 i; + u32 sdio; + unsigned int (*wimax_gpio_table)[4]; + + wimax_gpio_table = onoff ? wimax_sdio_on_table : wimax_sdio_off_table; + + for (i = 0; i < ARRAY_SIZE(wimax_sdio_on_table); i++) { + sdio = wimax_gpio_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wimax_gpio_table[i][1])); + s3c_gpio_setpull(sdio, wimax_gpio_table[i][3]); + s3c_gpio_set_drvstrength(sdio, S3C_GPIO_DRVSTR_2X); + + if (wimax_gpio_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wimax_gpio_table[i][2]); + } + return 0; +} + +static void wimax_deinit_gpios(void); +/* signal wimax modem to wakeup if asleep */ +static void wimax_wakeup_assert(int enable) +{ + if (herring_is_cdma_wimax_rev(0) || herring_is_cdma_wimax_rev(1)) + gpio_set_value(GPIO_WIMAX_WAKEUP, !enable); + else + gpio_set_value(GPIO_USB_SEL, !enable); +} + +static int get_wimax_sleep_mode(void) +{ + return gpio_get_value(GPIO_WIMAX_IF_MODE1); +} + +static int is_wimax_active(void) +{ + return gpio_get_value(GPIO_WIMAX_CON0); +} + +/* signal AP is active*/ +static void signal_ap_active(int enable) +{ + gpio_set_value(GPIO_WIMAX_CON1, enable); +} + +/* switch USB path to AP */ +void switch_usb_ap(void) +{ + gpio_set_value(GPIO_USB_HS_SEL, 1); + msleep(10); +} + +/* switch USB path to WiMAX */ +void switch_usb_wimax(void) +{ + gpio_set_value(GPIO_USB_HS_SEL, 0); + msleep(10); +} + +void wimax_init_gpios(void) +{ + s3c_gpio_cfgpin(GPIO_WIMAX_RESET_N, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_RESET_N, 0); + + s3c_gpio_cfgpin(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_DBGEN_28V, 0); + + s3c_gpio_cfgpin(GPIO_WIMAX_I2C_CON, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_I2C_CON, 1); + msleep(10); + + if (herring_is_cdma_wimax_rev(0) || herring_is_cdma_wimax_rev(1)) { + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_WIMAX_WAKEUP, S3C_GPIO_OUTPUT); + } else { + /* g_pdata->wimax_int set Input and Pull up */ + s3c_gpio_setpull(GPIO_WIMAX_WAKEUP, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_OUTPUT); + } + wimax_wakeup_assert(0); + + /* + * IDLE, VI setting pin: high for suspend idle, + * low for suspend vi + */ + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE1, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_IF_MODE1, 1); + + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE0, S3C_GPIO_OUTPUT); + + /* IDLE, VI interrupt for WiMAX */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON2, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_CON2, 1);/* active low interrupt */ + + /* PDA Active */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON1, S3C_GPIO_OUTPUT); + s3c_gpio_set_drvstrength(GPIO_WIMAX_CON1, S3C_GPIO_DRVSTR_2X); + signal_ap_active(1); + +} + +static void hw_set_wimax_mode(void) +{ + bool legacy_rev; + + legacy_rev = herring_is_cdma_wimax_rev(0) || + herring_is_cdma_wimax_rev(1); + + switch (wimax_config.wimax_mode) { + case SDIO_MODE: + pr_debug("SDIO MODE"); + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 1); + else + gpio_set_value(GPIO_USB_SEL, 1); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 1); + break; + case WTM_MODE: + case AUTH_MODE: + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 0); + else + gpio_set_value(GPIO_USB_SEL, 0); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 0); + break; + case DM_MODE: + pr_debug("DM MODE"); + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 1); + else + gpio_set_value(GPIO_USB_SEL, 1); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 0); + break; + case USB_MODE: + case USIM_RELAY_MODE: + pr_debug("USB MODE"); + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 0); + else + gpio_set_value(GPIO_USB_SEL, 0); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 1); + break; + } +} + +void wimax_hsmmc_presence_check(void) +{ + sdhci_s3c_force_presence_change(&s3c_device_hsmmc2); +} + +int gpio_wimax_power(int enable) +{ + if (!enable) + goto wimax_power_off; + + if (gpio_get_value(GPIO_WIMAX_EN)) { + pr_debug("Already Wimax powered ON"); + return WIMAX_ALREADY_POWER_ON; + } + /* wait for sdio remove complete*/ + while (!wimax_config.card_removed) + msleep(100); + + pr_debug("Wimax power ON"); + + wimax_sdio_en(1); + wimax_init_gpios(); + + if (wimax_config.wimax_mode != SDIO_MODE) + switch_usb_wimax(); + + gpio_set_value(GPIO_WIMAX_I2C_CON, 1); + msleep(10); + + gpio_set_value(GPIO_WIMAX_EN, 1); + + msleep(10); + pr_debug("RESET"); + + gpio_set_value(GPIO_WIMAX_RESET_N, 1); + + /* Delay important for bootloader initialization */ + msleep(1800); + + /*Dont force detect if the card is already detected*/ + if (wimax_config.card_removed) + wimax_hsmmc_presence_check(); + + return WIMAX_POWER_SUCCESS; + +wimax_power_off: + /*Wait for modem to flush EEPROM data*/ + msleep(500); + wimax_deinit_gpios(); + + pr_debug("Wimax power OFF"); + + /*Dont force detect if the card is already detected as removed*/ + if (!wimax_config.card_removed) + wimax_hsmmc_presence_check(); + + /*Not critial, just some safty margin*/ + msleep(300); + wimax_sdio_en(0); + + return WIMAX_POWER_SUCCESS; +} + +static struct wimax732_platform_data wimax732_pdata = { + .power = gpio_wimax_power, + .set_mode = hw_set_wimax_mode, + .signal_ap_active = signal_ap_active, + .get_sleep_mode = get_wimax_sleep_mode, + .is_modem_awake = is_wimax_active, + .wakeup_assert = wimax_wakeup_assert, + .g_cfg = &wimax_config, + .wimax_int = GPIO_USB_SEL, /* GPIO_USB_SEL,*/ +}; + +static struct platform_device s3c_device_cmc732 = { + .name = "wimax732_driver", + .id = 1, + .dev.platform_data = &wimax732_pdata, +}; + +void wimax_deinit_gpios(void) +{ + /* Disable WiMAX JTAG for freerun */ + s3c_gpio_cfgpin(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_PULL_NONE); + + /* g_pdata->wimax_int set Output low */ + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_NONE); + + /* MODE pin */ + s3c_gpio_cfgpin(GPIO_WIMAX_WAKEUP, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_WAKEUP, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_IF_MODE0, S3C_GPIO_PULL_NONE); + + /* WiMAX active */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON0, S3C_GPIO_PULL_NONE); + + /* IDLE, VI setting pin: high for suspend idle, + low for suspend vi */ + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE1, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_IF_MODE1, S3C_GPIO_PULL_NONE); + + /* IDLE, VI interrupt for WiMAX */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON2, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON2, S3C_GPIO_PULL_NONE); + + /* PDA Active */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON1, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON1, S3C_GPIO_PULL_NONE); + + /* power related */ + s3c_gpio_cfgpin(GPIO_WIMAX_RESET_N, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_RESET_N, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WIMAX_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_EN, S3C_GPIO_PULL_NONE); + + /* EEPROM switch to WiMAX */ + s3c_gpio_cfgpin(GPIO_WIMAX_I2C_CON, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_I2C_CON, S3C_GPIO_PULL_NONE); + + gpio_set_value(GPIO_WIMAX_EN, 0); + s3c_gpio_cfgpin(GPIO_WIMAX_I2C_CON, S3C_GPIO_INPUT); + + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_UART_SEL1, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL1, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_USB_HS_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_USB_HS_SEL, S3C_GPIO_PULL_NONE); + switch_usb_ap(); + + if (herring_is_cdma_wimax_rev(0) || herring_is_cdma_wimax_rev(1)) + wimax732_pdata.wimax_int = GPIO_USB_SEL; + else + wimax732_pdata.wimax_int = GPIO_WIMAX_WAKEUP; +} + +static void touch_keypad_gpio_init(void) +{ + int ret = 0; + + ret = gpio_request(_3_GPIO_TOUCH_EN, "TOUCH_EN"); + if (ret) + printk(KERN_ERR "Failed to request gpio touch_en.\n"); +} + +static void touch_keypad_onoff(int onoff) +{ + gpio_direction_output(_3_GPIO_TOUCH_EN, onoff); + + if (onoff == TOUCHKEY_OFF) + msleep(30); + else + msleep(50); +} + +static const int touch_keypad_code[] = { + KEY_MENU, + KEY_HOME, + KEY_BACK, + KEY_SEARCH +}; + +static struct touchkey_platform_data touchkey_data = { + .keycode_cnt = ARRAY_SIZE(touch_keypad_code), + .keycode = touch_keypad_code, + .touchkey_onoff = touch_keypad_onoff, + .fw_name = "cypress-touchkey.bin", + .scl_pin = _3_TOUCH_SCL_28V, + .sda_pin = _3_TOUCH_SDA_28V, + .en_pin = _3_GPIO_TOUCH_EN, +}; + +static struct gpio_event_direct_entry herring_keypad_key_map[] = { + { + .gpio = S5PV210_GPH2(6), + .code = KEY_POWER, + }, + { + .gpio = S5PV210_GPH3(1), + .code = KEY_VOLUMEDOWN, + }, + { + .gpio = S5PV210_GPH3(2), + .code = KEY_VOLUMEUP, + } +}; + +static struct gpio_event_input_info herring_keypad_key_info = { + .info.func = gpio_event_input_func, + .info.no_suspend = true, + .debounce_time.tv64 = 5 * NSEC_PER_MSEC, + .type = EV_KEY, + .keymap = herring_keypad_key_map, + .keymap_size = ARRAY_SIZE(herring_keypad_key_map) +}; + +static struct gpio_event_info *herring_input_info[] = { + &herring_keypad_key_info.info, +}; + + +static struct gpio_event_platform_data herring_input_data = { + .names = { + "herring-keypad", + NULL, + }, + .info = herring_input_info, + .info_count = ARRAY_SIZE(herring_input_info), +}; + +static struct platform_device herring_input_device = { + .name = GPIO_EVENT_DEV_NAME, + .id = 0, + .dev = { + .platform_data = &herring_input_data, + }, +}; + +#ifdef CONFIG_S5P_ADC +static struct s3c_adc_mach_info s3c_adc_platform __initdata = { + /* s5pc110 support 12-bit resolution */ + .delay = 10000, + .presc = 65, + .resolution = 12, +}; +#endif + +/* in revisions before 0.9, there is a common mic bias gpio */ + +static DEFINE_SPINLOCK(mic_bias_lock); +static bool wm8994_mic_bias; +static bool jack_mic_bias; +static void set_shared_mic_bias(void) +{ + gpio_set_value(GPIO_MICBIAS_EN, wm8994_mic_bias || jack_mic_bias); +} + +static void wm8994_set_mic_bias(bool on) +{ + if (system_rev < 0x09) { + unsigned long flags; + spin_lock_irqsave(&mic_bias_lock, flags); + wm8994_mic_bias = on; + set_shared_mic_bias(); + spin_unlock_irqrestore(&mic_bias_lock, flags); + } else + gpio_set_value(GPIO_MICBIAS_EN, on); +} + +static void sec_jack_set_micbias_state(bool on) +{ + if (system_rev < 0x09) { + unsigned long flags; + spin_lock_irqsave(&mic_bias_lock, flags); + jack_mic_bias = on; + set_shared_mic_bias(); + spin_unlock_irqrestore(&mic_bias_lock, flags); + } else + gpio_set_value(GPIO_EAR_MICBIAS_EN, on); +} + +static struct wm8994_platform_data wm8994_pdata = { + .ldo = GPIO_CODEC_LDO_EN, + .ear_sel = GPIO_EAR_SEL, + .set_mic_bias = wm8994_set_mic_bias, +}; + +/* + * Guide for Camera Configuration for Crespo board + * ITU CAM CH A: LSI s5k4ecgx + */ +static DEFINE_MUTEX(s5k4ecgx_lock); +static struct regulator *cam_isp_core_regulator; +static struct regulator *cam_isp_host_regulator; +static struct regulator *cam_af_regulator; +static bool s5k4ecgx_powered_on; +static int s5k4ecgx_regulator_init(void) +{ + if (IS_ERR_OR_NULL(cam_isp_core_regulator)) { + cam_isp_core_regulator = regulator_get(NULL, "cam_isp_core"); + if (IS_ERR_OR_NULL(cam_isp_core_regulator)) { + pr_err("failed to get cam_isp_core regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_isp_host_regulator)) { + cam_isp_host_regulator = regulator_get(NULL, "cam_isp_host"); + if (IS_ERR_OR_NULL(cam_isp_host_regulator)) { + pr_err("failed to get cam_isp_host regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_af_regulator)) { + cam_af_regulator = regulator_get(NULL, "cam_af"); + if (IS_ERR_OR_NULL(cam_af_regulator)) { + pr_err("failed to get cam_af regulator"); + return -EINVAL; + } + } + pr_debug("cam_isp_core_regulator = %p\n", cam_isp_core_regulator); + pr_debug("cam_isp_host_regulator = %p\n", cam_isp_host_regulator); + pr_debug("cam_af_regulator = %p\n", cam_af_regulator); + return 0; +} + +static void s5k4ecgx_init(void) +{ + /* CAM_IO_EN - GPB(7) */ + if (gpio_request(GPIO_GPB7, "GPB7") < 0) + pr_err("failed gpio_request(GPB7) for camera control\n"); + /* CAM_MEGA_nRST - GPJ1(5) */ + if (gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1") < 0) + pr_err("failed gpio_request(GPJ1) for camera control\n"); + /* CAM_MEGA_EN - GPJ0(6) */ + if (gpio_request(GPIO_CAM_MEGA_EN, "GPJ0") < 0) + pr_err("failed gpio_request(GPJ0) for camera control\n"); + /* FLASH_EN - GPJ1(2) */ + if (gpio_request(GPIO_FLASH_EN, "GPIO_FLASH_EN") < 0) + pr_err("failed gpio_request(GPIO_FLASH_EN)\n"); + /* FLASH_EN_SET - GPJ1(0) */ + if (gpio_request(GPIO_CAM_FLASH_EN_SET, "GPIO_CAM_FLASH_EN_SET") < 0) + pr_err("failed gpio_request(GPIO_CAM_FLASH_EN_SET)\n"); +} + +static int s5k4ecgx_ldo_en(bool en) +{ + int err = 0; + int result; + + if (IS_ERR_OR_NULL(cam_isp_core_regulator) || + IS_ERR_OR_NULL(cam_isp_host_regulator) || + IS_ERR_OR_NULL(cam_af_regulator)) { + pr_err("Camera regulators not initialized\n"); + return -EINVAL; + } + + if (!en) + goto off; + + /* Turn CAM_ISP_CORE_1.2V(VDD_REG) on */ + err = regulator_enable(cam_isp_core_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + mdelay(1); + + /* Turn CAM_SENSOR_A_2.8V(VDDA) on */ + gpio_set_value(GPIO_GPB7, 1); + mdelay(1); + + /* Turn CAM_ISP_HOST_2.8V(VDDIO) on */ + err = regulator_enable(cam_isp_host_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + udelay(50); + + /* Turn CAM_AF_2.8V or 3.0V on */ + err = regulator_enable(cam_af_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + udelay(50); + return 0; + +off: + result = err; + err = regulator_disable(cam_af_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + err = regulator_disable(cam_isp_host_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + gpio_set_value(GPIO_GPB7, 0); + err = regulator_disable(cam_isp_core_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + return result; +} + +static int s5k4ecgx_power_on(void) +{ + /* LDO on */ + int err; + + /* can't do this earlier because regulators aren't available in + * early boot + */ + if (s5k4ecgx_regulator_init()) { + pr_err("Failed to initialize camera regulators\n"); + return -EINVAL; + } + + err = s5k4ecgx_ldo_en(true); + if (err) + return err; + mdelay(66); + + /* MCLK on - default is input, to save power when camera not on */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(GPIO_CAM_MCLK_AF)); + mdelay(1); + + /* CAM_MEGA_EN - GPJ1(2) LOW */ + gpio_set_value(GPIO_CAM_MEGA_EN, 1); + mdelay(1); + + /* CAM_MEGA_nRST - GPJ1(5) LOW */ + gpio_set_value(GPIO_CAM_MEGA_nRST, 1); + mdelay(1); + + return 0; +} + +static int s5k4ecgx_power_off(void) +{ + /* CAM_MEGA_nRST - GPJ1(5) LOW */ + gpio_set_value(GPIO_CAM_MEGA_nRST, 0); + udelay(60); + + /* Mclk disable - set to input function to save power */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + udelay(10); + + /* CAM_MEGA_EN - GPJ1(2) LOW */ + gpio_set_value(GPIO_CAM_MEGA_EN, 0); + udelay(10); + + s5k4ecgx_ldo_en(false); + mdelay(1); + + return 0; +} + +static int s5k4ecgx_power_en(int onoff) +{ + int err = 0; + mutex_lock(&s5k4ecgx_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != s5k4ecgx_powered_on) { + if (onoff) + err = s5k4ecgx_power_on(); + else + err = s5k4ecgx_power_off(); + if (!err) + s5k4ecgx_powered_on = onoff; + } + mutex_unlock(&s5k4ecgx_lock); + return err; +} + +#define FLASH_MOVIE_MODE_CURRENT_50_PERCENT 7 + +#define FLASH_TIME_LATCH_US 500 +#define FLASH_TIME_EN_SET_US 1 + +/* The AAT1274 uses a single wire interface to write data to its + * control registers. An incoming value is written by sending a number + * of rising edges to EN_SET. Data is 4 bits, or 1-16 pulses, and + * addresses are 17 pulses or more. Data written without an address + * controls the current to the LED via the default address 17. */ +static void aat1274_write(int value) +{ + while (value--) { + gpio_set_value(GPIO_CAM_FLASH_EN_SET, 0); + udelay(FLASH_TIME_EN_SET_US); + gpio_set_value(GPIO_CAM_FLASH_EN_SET, 1); + udelay(FLASH_TIME_EN_SET_US); + } + udelay(FLASH_TIME_LATCH_US); + /* At this point, the LED will be on */ +} + +static int aat1274_flash(int enable) +{ + /* Turn main flash on or off by asserting a value on the EN line. */ + gpio_set_value(GPIO_FLASH_EN, !!enable); + + return 0; +} + +static int aat1274_af_assist(int enable) +{ + /* Turn assist light on or off by asserting a value on the EN_SET + * line. The default illumination level of 1/7.3 at 100% is used */ + gpio_set_value(GPIO_CAM_FLASH_EN_SET, !!enable); + if (!enable) + gpio_set_value(GPIO_FLASH_EN, 0); + + return 0; +} + +static int aat1274_torch(int enable) +{ + /* Turn torch mode on or off by writing to the EN_SET line. A level + * of 1/7.3 and 50% is used (half AF assist brightness). */ + if (enable) { + aat1274_write(FLASH_MOVIE_MODE_CURRENT_50_PERCENT); + } else { + gpio_set_value(GPIO_CAM_FLASH_EN_SET, 0); + gpio_set_value(GPIO_FLASH_EN, 0); + } + + return 0; +} + +static struct s5k4ecgx_platform_data s5k4ecgx_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .flash_onoff = &aat1274_flash, + .af_assist_onoff = &aat1274_af_assist, + .torch_onoff = &aat1274_torch, +}; + +static struct i2c_board_info s5k4ecgx_i2c_info = { + I2C_BOARD_INFO("S5K4ECGX", 0x5A>>1), + .platform_data = &s5k4ecgx_plat, +}; + +static struct s3c_platform_camera s5k4ecgx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &s5k4ecgx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 1920, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, + .cam_power = s5k4ecgx_power_en, +}; + + +/* External camera module setting */ +static DEFINE_MUTEX(s5ka3dfx_lock); +static struct regulator *s5ka3dfx_vga_avdd; +static struct regulator *s5ka3dfx_vga_vddio; +static struct regulator *s5ka3dfx_cam_isp_host; +static struct regulator *s5ka3dfx_vga_dvdd; +static bool s5ka3dfx_powered_on; + +static int s5ka3dfx_request_gpio(void) +{ + int err; + + /* CAM_VGA_nSTBY - GPB(0) */ + err = gpio_request(GPIO_CAM_VGA_nSTBY, "GPB0"); + if (err) { + pr_err("Failed to request GPB0 for camera control\n"); + return -EINVAL; + } + + /* CAM_VGA_nRST - GPB(2) */ + err = gpio_request(GPIO_CAM_VGA_nRST, "GPB2"); + if (err) { + pr_err("Failed to request GPB2 for camera control\n"); + gpio_free(GPIO_CAM_VGA_nSTBY); + return -EINVAL; + } + + return 0; +} + +static int s5ka3dfx_power_init(void) +{ + if (IS_ERR_OR_NULL(s5ka3dfx_vga_avdd)) + s5ka3dfx_vga_avdd = regulator_get(NULL, "vga_avdd"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_avdd)) { + pr_err("Failed to get regulator vga_avdd\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_vddio)) + s5ka3dfx_vga_vddio = regulator_get(NULL, "vga_vddio"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_vddio)) { + pr_err("Failed to get regulator vga_vddio\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_cam_isp_host)) + s5ka3dfx_cam_isp_host = regulator_get(NULL, "cam_isp_host"); + + if (IS_ERR_OR_NULL(s5ka3dfx_cam_isp_host)) { + pr_err("Failed to get regulator cam_isp_host\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_dvdd)) + s5ka3dfx_vga_dvdd = regulator_get(NULL, "vga_dvdd"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_dvdd)) { + pr_err("Failed to get regulator vga_dvdd\n"); + return -EINVAL; + } + + return 0; +} + +static int s5ka3dfx_power_on(void) +{ + int err = 0; + int result; + + if (s5ka3dfx_power_init()) { + pr_err("Failed to get all regulator\n"); + return -EINVAL; + } + + /* Turn VGA_AVDD_2.8V on */ + err = regulator_enable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to enable regulator vga_avdd\n"); + return -EINVAL; + } + msleep(3); + + /* Turn VGA_VDDIO_2.8V on */ + err = regulator_enable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to enable regulator vga_vddio\n"); + goto off_vga_vddio; + } + udelay(20); + + /* Turn VGA_DVDD_1.8V on */ + err = regulator_enable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to enable regulator vga_dvdd\n"); + goto off_vga_dvdd; + } + udelay(100); + + /* CAM_VGA_nSTBY HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 1); + + udelay(10); + + /* Mclk enable */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(0x02)); + udelay(430); + + /* Turn CAM_ISP_HOST_2.8V on */ + err = regulator_enable(s5ka3dfx_cam_isp_host); + if (err) { + pr_err("Failed to enable regulator cam_isp_host\n"); + goto off_cam_isp_host; + } + udelay(150); + + /* CAM_VGA_nRST HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + gpio_set_value(GPIO_CAM_VGA_nRST, 1); + mdelay(5); + + return 0; +off_cam_isp_host: + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + udelay(1); + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + udelay(1); + err = regulator_disable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to disable regulator vga_dvdd\n"); + result = err; + } +off_vga_dvdd: + err = regulator_disable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to disable regulator vga_vddio\n"); + result = err; + } +off_vga_vddio: + err = regulator_disable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to disable regulator vga_avdd\n"); + result = err; + } + + return result; +} + +static int s5ka3dfx_power_off(void) +{ + int err; + + if (!s5ka3dfx_vga_avdd || !s5ka3dfx_vga_vddio || + !s5ka3dfx_cam_isp_host || !s5ka3dfx_vga_dvdd) { + pr_err("Faild to get all regulator\n"); + return -EINVAL; + } + + /* Turn CAM_ISP_HOST_2.8V off */ + err = regulator_disable(s5ka3dfx_cam_isp_host); + if (err) { + pr_err("Failed to disable regulator cam_isp_host\n"); + return -EINVAL; + } + + /* CAM_VGA_nRST LOW */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 1); + gpio_set_value(GPIO_CAM_VGA_nRST, 0); + udelay(430); + + /* Mclk disable */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + + udelay(1); + + /* Turn VGA_VDDIO_2.8V off */ + err = regulator_disable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to disable regulator vga_vddio\n"); + return -EINVAL; + } + + /* Turn VGA_DVDD_1.8V off */ + err = regulator_disable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to disable regulator vga_dvdd\n"); + return -EINVAL; + } + + /* CAM_VGA_nSTBY LOW */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + + udelay(1); + + /* Turn VGA_AVDD_2.8V off */ + err = regulator_disable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to disable regulator vga_avdd\n"); + return -EINVAL; + } + + return err; +} + +static int s5ka3dfx_power_en(int onoff) +{ + int err = 0; + mutex_lock(&s5ka3dfx_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != s5ka3dfx_powered_on) { + if (onoff) + err = s5ka3dfx_power_on(); + else { + err = s5ka3dfx_power_off(); + s3c_i2c0_force_stop(); + } + if (!err) + s5ka3dfx_powered_on = onoff; + } + mutex_unlock(&s5ka3dfx_lock); + + return err; +} + +static struct s5ka3dfx_platform_data s5ka3dfx_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 0, + + .cam_power = s5ka3dfx_power_en, +}; + +static struct i2c_board_info s5ka3dfx_i2c_info = { + I2C_BOARD_INFO("S5KA3DFX", 0xc4>>1), + .platform_data = &s5ka3dfx_plat, +}; + +static struct s3c_platform_camera s5ka3dfx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &s5ka3dfx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 480, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, + .cam_power = s5ka3dfx_power_en, +}; + +/* Interface setting */ +static struct s3c_platform_fimc fimc_plat_lsi = { + .srclk_name = "mout_mpll", + .clk_name = "sclk_fimc", + .lclk_name = "fimc", + .clk_rate = 166750000, + .default_cam = CAMERA_PAR_A, + .camera = { + &s5k4ecgx, + &s5ka3dfx, + }, + .hw_ver = 0x43, +}; + +#ifdef CONFIG_VIDEO_JPEG_V2 +static struct s3c_platform_jpeg jpeg_plat __initdata = { + .max_main_width = 800, + .max_main_height = 480, + .max_thumb_width = 320, + .max_thumb_height = 240, +}; +#endif + +static struct k3g_platform_data k3g_pdata = { + .axis_map_x = 1, + .axis_map_y = 1, + .axis_map_z = 1, + .negate_x = 0, + .negate_y = 0, + .negate_z = 0, +}; + +/* I2C0 */ +static struct i2c_board_info i2c_devs0[] __initdata = { + { + I2C_BOARD_INFO("k3g", 0x69), + .platform_data = &k3g_pdata, + }, +}; + +static struct i2c_board_info i2c_devs4[] __initdata = { + { + I2C_BOARD_INFO("wm8994-samsung", (0x34>>1)), + .platform_data = &wm8994_pdata, + }, +}; + +static struct akm8973_platform_data akm8973_pdata = { + .reset_line = GPIO_MSENSE_nRST, + .reset_asserted = GPIO_LEVEL_LOW, + .gpio_data_ready_int = GPIO_MSENSE_IRQ, +}; + +static struct kr3dm_platform_data kr3dm_data = { + .gpio_acc_int = GPIO_ACC_INT, +}; + +/* I2C1 */ +static struct i2c_board_info i2c_devs1[] __initdata = { + { + I2C_BOARD_INFO("ak8973", 0x1c), + .platform_data = &akm8973_pdata, + }, + { + I2C_BOARD_INFO("kr3dm", 0x09), + .platform_data = &kr3dm_data, + }, +}; + +static void mxt224_power_on(void) +{ + gpio_direction_output(GPIO_TOUCH_EN, 1); + + mdelay(40); +} + +static void mxt224_power_off(void) +{ + gpio_direction_output(GPIO_TOUCH_EN, 0); +} + +#define MXT224_MAX_MT_FINGERS 5 + +static u8 t7_config[] = {GEN_POWERCONFIG_T7, + 64, 255, 50}; +static u8 t8_config[] = {GEN_ACQUISITIONCONFIG_T8, + 7, 0, 5, 0, 0, 0, 9, 35}; +static u8 t9_config[] = {TOUCH_MULTITOUCHSCREEN_T9, + 139, 0, 0, 19, 11, 0, 32, 25, 2, 1, 25, 3, 1, + 46, MXT224_MAX_MT_FINGERS, 5, 14, 10, 255, 3, + 255, 3, 18, 18, 10, 10, 141, 65, 143, 110, 18}; +static u8 t18_config[] = {SPT_COMCONFIG_T18, + 0, 1}; +static u8 t20_config[] = {PROCI_GRIPFACESUPPRESSION_T20, + 7, 0, 0, 0, 0, 0, 0, 80, 40, 4, 35, 10}; +static u8 t22_config[] = {PROCG_NOISESUPPRESSION_T22, + 5, 0, 0, 0, 0, 0, 0, 3, 30, 0, 0, 29, 34, 39, + 49, 58, 3}; +static u8 t28_config[] = {SPT_CTECONFIG_T28, + 1, 0, 3, 16, 63, 60}; +static u8 end_config[] = {RESERVED_T255}; + +static const u8 *mxt224_config[] = { + t7_config, + t8_config, + t9_config, + t18_config, + t20_config, + t22_config, + t28_config, + end_config, +}; + +static struct mxt224_platform_data mxt224_data = { + .max_finger_touches = MXT224_MAX_MT_FINGERS, + .gpio_read_done = GPIO_TOUCH_INT, + .config = mxt224_config, + .min_x = 0, + .max_x = 1023, + .min_y = 0, + .max_y = 1023, + .min_z = 0, + .max_z = 255, + .min_w = 0, + .max_w = 30, + .power_on = mxt224_power_on, + .power_off = mxt224_power_off, +}; + +/* I2C2 */ +static struct i2c_board_info i2c_devs2[] __initdata = { + { + I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a), + .platform_data = &mxt224_data, + .irq = IRQ_EINT_GROUP(18, 5), + }, +}; + +static void mxt224_init(void) +{ + if (!herring_is_tft_dev()) + return; + mxt224_data.max_y = 950; + t9_config[8] = 45; + t9_config[9] = 3; + t9_config[23] = 0; + t9_config[24] = 0; + t9_config[27] = 0; + t9_config[28] = 0; + t9_config[29] = 0; + t9_config[30] = 0; +} + +static ssize_t herring_virtual_keys_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, + __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":71:839:73:62" + ":" __stringify(EV_KEY) ":" + __stringify(KEY_MENU) ":183:839:73:62" + ":" __stringify(EV_KEY) ":" + __stringify(KEY_SEARCH) ":294:839:73:62" + ":" __stringify(EV_KEY) ":" + __stringify(KEY_HOME) ":406:839:73:62" + "\n"); +} + +static struct kobj_attribute herring_virtual_keys_attr = { + .attr = { + .name = "virtualkeys.mxt224_ts_input", + .mode = S_IRUGO, + }, + .show = &herring_virtual_keys_show, +}; + +static struct attribute *herring_properties_attrs[] = { + &herring_virtual_keys_attr.attr, + NULL, +}; + +static struct attribute_group herring_properties_attr_group = { + .attrs = herring_properties_attrs, +}; + +static void herring_virtual_keys_init(void) +{ + struct kobject *properties_kobj; + int ret; + + properties_kobj = kobject_create_and_add("board_properties", NULL); + if (properties_kobj) + ret = sysfs_create_group(properties_kobj, + &herring_properties_attr_group); + if (!properties_kobj || ret) + pr_err("failed to create board_properties\n"); +} + +/* I2C2 */ +static struct i2c_board_info i2c_devs10[] __initdata = { + { + I2C_BOARD_INFO(CYPRESS_TOUCHKEY_DEV_NAME, 0x20), + .platform_data = &touchkey_data, + .irq = (IRQ_EINT_GROUP22_BASE + 1), + }, +}; + +static struct i2c_board_info i2c_devs5[] __initdata = { + { + I2C_BOARD_INFO("kr3dm", 0x09), + .platform_data = &kr3dm_data, + }, +}; + +static struct i2c_board_info i2c_devs8[] __initdata = { + { + I2C_BOARD_INFO("k3g", 0x69), + .platform_data = &k3g_pdata, + .irq = -1, + }, +}; + +static void k3g_irq_init(void) +{ + i2c_devs0[0].irq = (system_rev >= 0x0A) ? IRQ_EINT(29) : -1; +} + + +static void fsa9480_usb_cb(bool attached) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + if (gadget) { + if (attached) + usb_gadget_vbus_connect(gadget); + else + usb_gadget_vbus_disconnect(gadget); + } + + set_cable_status = attached ? CABLE_TYPE_USB : CABLE_TYPE_NONE; + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static void fsa9480_charger_cb(bool attached) +{ + set_cable_status = attached ? CABLE_TYPE_AC : CABLE_TYPE_NONE; + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static struct switch_dev switch_dock = { + .name = "dock", +}; + +static void fsa9480_deskdock_cb(bool attached) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + if (attached) + switch_set_state(&switch_dock, 1); + else + switch_set_state(&switch_dock, 0); + + if (gadget) { + if (attached) + usb_gadget_vbus_connect(gadget); + else + usb_gadget_vbus_disconnect(gadget); + } + + set_cable_status = attached ? CABLE_TYPE_USB : CABLE_TYPE_NONE; + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static void fsa9480_cardock_cb(bool attached) +{ + if (attached) + switch_set_state(&switch_dock, 2); + else + switch_set_state(&switch_dock, 0); +} + +static void fsa9480_reset_cb(void) +{ + int ret; + + /* for CarDock, DeskDock */ + ret = switch_dev_register(&switch_dock); + if (ret < 0) + pr_err("Failed to register dock switch. %d\n", ret); +} + +static struct fsa9480_platform_data fsa9480_pdata = { + .usb_cb = fsa9480_usb_cb, + .charger_cb = fsa9480_charger_cb, + .deskdock_cb = fsa9480_deskdock_cb, + .cardock_cb = fsa9480_cardock_cb, + .reset_cb = fsa9480_reset_cb, +}; + +static struct i2c_board_info i2c_devs7[] __initdata = { + { + I2C_BOARD_INFO("fsa9480", 0x4A >> 1), + .platform_data = &fsa9480_pdata, + .irq = IRQ_EINT(23), + }, +}; + +static struct i2c_board_info i2c_devs6[] __initdata = { +#ifdef CONFIG_REGULATOR_MAX8998 + { + /* The address is 0xCC used since SRAD = 0 */ + I2C_BOARD_INFO("max8998", (0xCC >> 1)), + .platform_data = &max8998_pdata, + .irq = IRQ_EINT7, + }, { + I2C_BOARD_INFO("rtc_max8998", (0x0D >> 1)), + }, +#endif +}; + +static struct pn544_i2c_platform_data pn544_pdata = { + .irq_gpio = NFC_IRQ, + .ven_gpio = NFC_EN, + .firm_gpio = NFC_FIRM, +}; + +static struct i2c_board_info i2c_devs14[] __initdata = { + { + I2C_BOARD_INFO("pn544", 0x2b), + .irq = IRQ_EINT(12), + .platform_data = &pn544_pdata, + }, +}; + +static int max17040_power_supply_register(struct device *parent, + struct power_supply *psy) +{ + herring_charger.psy_fuelgauge = psy; + return 0; +} + +static void max17040_power_supply_unregister(struct power_supply *psy) +{ + herring_charger.psy_fuelgauge = NULL; +} + +static struct max17040_platform_data max17040_pdata = { + .power_supply_register = max17040_power_supply_register, + .power_supply_unregister = max17040_power_supply_unregister, + .rcomp_value = 0xD700, +}; + +static struct i2c_board_info i2c_devs9[] __initdata = { + { + I2C_BOARD_INFO("max17040", (0x6D >> 1)), + .platform_data = &max17040_pdata, + }, +}; + +static void gp2a_gpio_init(void) +{ + int ret = gpio_request(GPIO_PS_ON, "gp2a_power_supply_on"); + if (ret) + printk(KERN_ERR "Failed to request gpio gp2a power supply.\n"); +} + +static int gp2a_power(bool on) +{ + /* this controls the power supply rail to the gp2a IC */ + gpio_direction_output(GPIO_PS_ON, on); + return 0; +} + +static int gp2a_light_adc_value(void) +{ + return s3c_adc_get_adc_data(9); +} + +static struct gp2a_platform_data gp2a_pdata = { + .power = gp2a_power, + .p_out = GPIO_PS_VOUT, + .light_adc_value = gp2a_light_adc_value, + .light_adc_max = 4095, + .light_adc_fuzz = 64, +}; + +static struct i2c_board_info i2c_devs11[] __initdata = { + { + I2C_BOARD_INFO("gp2a", (0x88 >> 1)), + .platform_data = &gp2a_pdata, + }, +}; + +static struct i2c_board_info i2c_devs12[] __initdata = { + { + I2C_BOARD_INFO("ak8973", 0x1c), + .platform_data = &akm8973_pdata, + }, +}; + +static struct resource ram_console_resource[] = { + { + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ram_console_device = { + .name = "ram_console", + .id = -1, + .num_resources = ARRAY_SIZE(ram_console_resource), + .resource = ram_console_resource, +}; + +#ifdef CONFIG_ANDROID_PMEM +static struct android_pmem_platform_data pmem_pdata = { + .name = "pmem", + .no_allocator = 1, + .cached = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_gpu1_pdata = { + .name = "pmem_gpu1", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_adsp_pdata = { + .name = "pmem_adsp", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct platform_device pmem_device = { + .name = "android_pmem", + .id = 0, + .dev = { .platform_data = &pmem_pdata }, +}; + +static struct platform_device pmem_gpu1_device = { + .name = "android_pmem", + .id = 1, + .dev = { .platform_data = &pmem_gpu1_pdata }, +}; + +static struct platform_device pmem_adsp_device = { + .name = "android_pmem", + .id = 2, + .dev = { .platform_data = &pmem_adsp_pdata }, +}; + +static void __init android_pmem_set_platdata(void) +{ + pmem_pdata.start = (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM, 0); + pmem_pdata.size = (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM, 0); + + pmem_gpu1_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_GPU1, 0); + pmem_gpu1_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_GPU1, 0); + + pmem_adsp_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_ADSP, 0); + pmem_adsp_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_ADSP, 0); +} +#endif + +struct platform_device sec_device_battery = { + .name = "sec-battery", + .id = -1, +}; + +static struct platform_device sec_device_rfkill = { + .name = "bt_rfkill", + .id = -1, +}; + +static struct platform_device sec_device_btsleep = { + .name = "bt_sleep", + .id = -1, +}; + +static struct sec_jack_zone sec_jack_zones[] = { + { + /* adc == 0, unstable zone, default to 3pole if it stays + * in this range for a half second (20ms delays, 25 samples) + */ + .adc_high = 0, + .delay_ms = 20, + .check_count = 25, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 0 < adc <= 1000, unstable zone, default to 3pole if it stays + * in this range for a second (10ms delays, 100 samples) + */ + .adc_high = 1000, + .delay_ms = 10, + .check_count = 100, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 1000 < adc <= 2000, unstable zone, default to 4pole if it + * stays in this range for a second (10ms delays, 100 samples) + */ + .adc_high = 2000, + .delay_ms = 10, + .check_count = 100, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* 2000 < adc <= 3700, 4 pole zone, default to 4pole if it + * stays in this range for 200ms (20ms delays, 10 samples) + */ + .adc_high = 3700, + .delay_ms = 20, + .check_count = 10, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* adc > 3700, unstable zone, default to 3pole if it stays + * in this range for a second (10ms delays, 100 samples) + */ + .adc_high = 0x7fffffff, + .delay_ms = 10, + .check_count = 100, + .jack_type = SEC_HEADSET_3POLE, + }, +}; + +/* To support 3-buttons earjack */ +static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = { + { + /* 0 <= adc <=110, stable zone */ + .code = KEY_MEDIA, + .adc_low = 0, + .adc_high = 110, + }, + { + /* 130 <= adc <= 365, stable zone */ + .code = KEY_PREVIOUSSONG, + .adc_low = 130, + .adc_high = 365, + }, + { + /* 385 <= adc <= 870, stable zone */ + .code = KEY_NEXTSONG, + .adc_low = 385, + .adc_high = 870, + }, +}; + +static int sec_jack_get_adc_value(void) +{ + return s3c_adc_get_adc_data(3); +} + +struct sec_jack_platform_data sec_jack_pdata = { + .set_micbias_state = sec_jack_set_micbias_state, + .get_adc_value = sec_jack_get_adc_value, + .zones = sec_jack_zones, + .num_zones = ARRAY_SIZE(sec_jack_zones), + .buttons_zones = sec_jack_buttons_zones, + .num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones), + .det_gpio = GPIO_DET_35, + .send_end_gpio = GPIO_EAR_SEND_END, +}; + +static struct platform_device sec_device_jack = { + .name = "sec_jack", + .id = 1, /* will be used also for gpio_event id */ + .dev.platform_data = &sec_jack_pdata, +}; + + +#define S3C_GPIO_SETPIN_ZERO 0 +#define S3C_GPIO_SETPIN_ONE 1 +#define S3C_GPIO_SETPIN_NONE 2 + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +static struct gpio_init_data herring_init_gpios[] = { + { + .num = S5PV210_GPB(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + + }, { + .num = S5PV210_GPB(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPC0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPC1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPD0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPD1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPE0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + + { + .num = S5PV210_GPE1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPF3(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPF3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG0(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG1(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG3(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_DET_35 - 3.5" ear jack */ + .num = S5PV210_GPH0(6), + .cfg = S3C_GPIO_SFN(GPIO_DET_35_AF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(7), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_IRQ */ + .num = S5PV210_GPH1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_EN */ + .num = S5PV210_GPH1(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_FIRM */ + .num = S5PV210_GPH1(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(7), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(5), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(6), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH3(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_UP, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(1), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(2), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_EAR_SEND_END */ + .num = S5PV210_GPH3(6), + .cfg = S3C_GPIO_SFN(GPIO_EAR_SEND_END_AF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPI(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(5), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ1(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ3(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_EAR_ADC_SEL */ + .num = S5PV210_GPJ3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ4(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(1), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP01(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP02(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP03(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP04(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_SCL_18V - has external pull up resistor */ + .num = S5PV210_MP04(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_SDA_18V - has external pull up resistor */ + .num = S5PV210_MP04(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP05(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +}; + +void s3c_config_gpio_table(void) +{ + u32 i, gpio; + + for (i = 0; i < ARRAY_SIZE(herring_init_gpios); i++) { + gpio = herring_init_gpios[i].num; + if (system_rev <= 0x07 && gpio == S5PV210_GPJ3(3)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ONE); + } else if (gpio <= S5PV210_MP05(7)) { + s3c_gpio_cfgpin(gpio, herring_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, herring_init_gpios[i].pud); + + if (herring_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, herring_init_gpios[i].val); + + s3c_gpio_set_drvstrength(gpio, + herring_init_gpios[i].drv); + } + } + + if (herring_is_cdma_wimax_dev()) { + /* WiMAX_I2C_CON */ + gpio = S5PV210_GPC1(1); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_GPC1(3); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_GPC1(4); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_GPG2(0); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(1); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(3); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(4); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(5); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(6); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + /* WIMAX_EN */ + gpio = S5PV210_GPH1(0); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ZERO); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_1X); + + /* GPIO_CP_RST, CDMA modem specific setting */ + gpio = S5PV210_GPH3(7); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ZERO); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_MP05(2); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_MP05(3); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + } +} + +#define S5PV210_PS_HOLD_CONTROL_REG (S3C_VA_SYS+0xE81C) +static void herring_power_off(void) +{ + int phone_wait_cnt = 0; + + if (herring_is_cdma_wimax_dev()) { + /* confirm phone is powered-off */ + while (1) { + if (gpio_get_value(GPIO_PHONE_ACTIVE)) { + pr_info("%s: Try to Turn Phone Off by CP_RST\n", + __func__); + gpio_set_value(GPIO_CP_RST, 0); + if (phone_wait_cnt > 1) { + pr_info("%s: PHONE OFF Fail\n", + __func__); + break; + } + phone_wait_cnt++; + mdelay(100); + } else { + pr_info("%s: PHONE OFF Success\n", __func__); + break; + } + } + } + + while (1) { + /* Check reboot charging */ + if (set_cable_status) { + /* watchdog reset */ + pr_info("%s: charger connected, rebooting\n", __func__); + writel(3, S5P_INFORM6); + arch_reset('r', NULL); + pr_crit("%s: waiting for reset!\n", __func__); + while (1); + } + + /* wait for power button release */ + if (gpio_get_value(GPIO_nPOWER)) { + pr_info("%s: set PS_HOLD low\n", __func__); + + /* PS_HOLD high PS_HOLD_CONTROL, R/W, 0xE010_E81C */ + writel(readl(S5PV210_PS_HOLD_CONTROL_REG) & 0xFFFFFEFF, + S5PV210_PS_HOLD_CONTROL_REG); + + pr_crit("%s: should not reach here!\n", __func__); + } + + /* if power button is not released, wait and check TA again */ + pr_info("%s: PowerButton is not released.\n", __func__); + mdelay(1000); + } +} + +/* this table only for B4 board */ +static unsigned int herring_sleep_gpio_table[][3] = { + { S5PV210_GPA0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPG1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPG2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + /* Alive part ending and off part start*/ + { S5PV210_GPI(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /* memory part */ + { S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP04(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /* Memory part ending and off part ending */ +}; + +static unsigned int herring_cdma_wimax_sleep_gpio_table[][3] = { + { S5PV210_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX PMIC SDA*/ + { S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*Wimax eeprom switch*/ + { S5PV210_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /*WIMAX PMIC SCL*/ + { S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX EEPROM I2C LINES*/ + { S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX DBGEN*/ + { S5PV210_GPD0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX RESET_N*/ + { S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + + { S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + + { S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + + { S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + + { S5PV210_GPG0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*wimax SDIO pins*/ + { S5PV210_GPG2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPG3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_GPH1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPH1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPH2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPH3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + { S5PV210_GPH3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /* Alive part ending and off part start*/ + { S5PV210_GPI(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /* memory part */ + { S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX*/ + { S5PV210_MP04(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX*/ + { S5PV210_MP04(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP05(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP05(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /* Memory part ending and off part ending */ +}; + +void s3c_config_sleep_gpio_table(int array_size, unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +void s3c_config_cdma_wimax_sleep_gpio(void) +{ + s3c_gpio_cfgpin(S5PV210_GPH0(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(0), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH0(1), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(1), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH0(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(2), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH0(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(4), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(4), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(4), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(5), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(0), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(1), S3C_GPIO_PULL_DOWN); + gpio_set_value(S5PV210_GPH1(1), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(2), S3C_GPIO_PULL_UP); + gpio_set_value(S5PV210_GPH1(2), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(4), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(5), S3C_GPIO_PULL_DOWN); + gpio_set_value(S5PV210_GPH1(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(6), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(6), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(7), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(7), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH2(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(0), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH2(2), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(2), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(2), 0); + + s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH2(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH3(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(0), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH3(3), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(3), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH3(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH3(5), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(5), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH3(7), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH3(7), S3C_GPIO_PULL_UP); + gpio_set_value(S5PV210_GPH3(7), 1); + +} + +void s3c_config_gsm_sleep_gpio(void) +{ + /* setting the alive mode registers */ + s3c_gpio_cfgpin(S5PV210_GPH0(1), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(1), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH0(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(4), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(4), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(4), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(5), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(1), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(1), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(2), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(4), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(5), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(6), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(6), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(7), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(7), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH2(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(0), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH2(2), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(2), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(2), 0); + + s3c_gpio_cfgpin(S5PV210_GPH2(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH3(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(0), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH3(3), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(3), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH3(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_DOWN); +} + +void s3c_config_sleep_gpio(void) +{ + if (herring_is_cdma_wimax_dev()) + s3c_config_cdma_wimax_sleep_gpio(); + else + s3c_config_gsm_sleep_gpio(); +} +EXPORT_SYMBOL(s3c_config_sleep_gpio); + +static unsigned int wlan_sdio_on_table[][4] = { + {GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, +}; + +static unsigned int wlan_sdio_off_table[][4] = { + {GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, +}; + +static int wlan_power_en(int onoff) +{ + if (onoff) { + s3c_gpio_cfgpin(GPIO_WLAN_HOST_WAKE, + S3C_GPIO_SFN(GPIO_WLAN_HOST_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_HOST_WAKE, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_WLAN_WAKE, + S3C_GPIO_SFN(GPIO_WLAN_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_WAKE, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_WAKE, GPIO_LEVEL_LOW); + + s3c_gpio_cfgpin(GPIO_WLAN_nRST, + S3C_GPIO_SFN(GPIO_WLAN_nRST_AF)); + s3c_gpio_setpull(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + msleep(200); + } else { + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + if (gpio_get_value(GPIO_BT_nRST) == 0) { + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + } + } + return 0; +} + +static int wlan_reset_en(int onoff) +{ + gpio_set_value(GPIO_WLAN_nRST, + onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); + return 0; +} + +static int wlan_carddetect_en(int onoff) +{ + u32 i; + u32 sdio; + + if (onoff) { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_on_table); i++) { + sdio = wlan_sdio_on_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wlan_sdio_on_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_on_table[i][3]); + if (wlan_sdio_on_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_on_table[i][2]); + } + } else { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_off_table); i++) { + sdio = wlan_sdio_off_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wlan_sdio_off_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_off_table[i][3]); + if (wlan_sdio_off_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_off_table[i][2]); + } + } + udelay(5); + + sdhci_s3c_force_presence_change(&s3c_device_hsmmc3); + msleep(500); /* wait for carddetect */ + return 0; +} + +static struct resource wifi_resources[] = { + [0] = { + .name = "bcm4329_wlan_irq", + .start = IRQ_EINT(20), + .end = IRQ_EINT(20), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = { + {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)} +}; + +static void *herring_mem_prealloc(int section, unsigned long size) +{ + if (section == PREALLOC_WLAN_SEC_NUM) + return wlan_static_skb; + + if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM)) + return NULL; + + if (wifi_mem_array[section].size < size) + return NULL; + + return wifi_mem_array[section].mem_ptr; +} + +int __init herring_init_wifi_mem(void) +{ + int i; + int j; + + for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) { + wlan_static_skb[i] = dev_alloc_skb( + ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192)); + + if (!wlan_static_skb[i]) + goto err_skb_alloc; + } + + for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) { + wifi_mem_array[i].mem_ptr = + kmalloc(wifi_mem_array[i].size, GFP_KERNEL); + + if (!wifi_mem_array[i].mem_ptr) + goto err_mem_alloc; + } + return 0; + + err_mem_alloc: + pr_err("Failed to mem_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + kfree(wifi_mem_array[j].mem_ptr); + + i = WLAN_SKB_BUF_NUM; + + err_skb_alloc: + pr_err("Failed to skb_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + dev_kfree_skb(wlan_static_skb[j]); + + return -ENOMEM; +} + +/* Customized Locale table : OPTIONAL feature */ +#define WLC_CNTRY_BUF_SZ 4 +typedef struct cntry_locales_custom { + char iso_abbrev[WLC_CNTRY_BUF_SZ]; + char custom_locale[WLC_CNTRY_BUF_SZ]; + int custom_locale_rev; +} cntry_locales_custom_t; + +static cntry_locales_custom_t herring_wlan_translate_custom_table[] = { +/* Table should be filled out based on custom platform regulatory requirement */ + {"", "XY", 4}, /* universal */ + {"US", "US", 69}, /* input ISO "US" to : US regrev 69 */ + {"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */ + {"EU", "EU", 5}, /* European union countries */ + {"AT", "EU", 5}, + {"BE", "EU", 5}, + {"BG", "EU", 5}, + {"CY", "EU", 5}, + {"CZ", "EU", 5}, + {"DK", "EU", 5}, + {"EE", "EU", 5}, + {"FI", "EU", 5}, + {"FR", "EU", 5}, + {"DE", "EU", 5}, + {"GR", "EU", 5}, + {"HU", "EU", 5}, + {"IE", "EU", 5}, + {"IT", "EU", 5}, + {"LV", "EU", 5}, + {"LI", "EU", 5}, + {"LT", "EU", 5}, + {"LU", "EU", 5}, + {"MT", "EU", 5}, + {"NL", "EU", 5}, + {"PL", "EU", 5}, + {"PT", "EU", 5}, + {"RO", "EU", 5}, + {"SK", "EU", 5}, + {"SI", "EU", 5}, + {"ES", "EU", 5}, + {"SE", "EU", 5}, + {"GB", "EU", 5}, /* input ISO "GB" to : EU regrev 05 */ + {"IL", "IL", 0}, + {"CH", "CH", 0}, + {"TR", "TR", 0}, + {"NO", "NO", 0}, + {"KR", "XY", 3}, + {"AU", "XY", 3}, + {"CN", "XY", 3}, /* input ISO "CN" to : XY regrev 03 */ + {"TW", "XY", 3}, + {"AR", "XY", 3}, + {"MX", "XY", 3} +}; + +static void *herring_wlan_get_country_code(char *ccode) +{ + int size = ARRAY_SIZE(herring_wlan_translate_custom_table); + int i; + + if (!ccode) + return NULL; + + for (i = 0; i < size; i++) + if (strcmp(ccode, herring_wlan_translate_custom_table[i].iso_abbrev) == 0) + return &herring_wlan_translate_custom_table[i]; + return &herring_wlan_translate_custom_table[0]; +} + + +static struct wifi_platform_data wifi_pdata = { + .set_power = wlan_power_en, + .set_reset = wlan_reset_en, + .set_carddetect = wlan_carddetect_en, + .mem_prealloc = herring_mem_prealloc, + .get_country_code = herring_wlan_get_country_code, +}; + +static struct platform_device sec_device_wifi = { + .name = "bcm4329_wlan", + .id = 1, + .num_resources = ARRAY_SIZE(wifi_resources), + .resource = wifi_resources, + .dev = { + .platform_data = &wifi_pdata, + }, +}; + +static struct platform_device watchdog_device = { + .name = "watchdog", + .id = -1, +}; + +static struct platform_device *herring_devices[] __initdata = { + &watchdog_device, +#ifdef CONFIG_FIQ_DEBUGGER + &s5pv210_device_fiqdbg_uart2, +#endif + &s5p_device_onenand, +#ifdef CONFIG_RTC_DRV_S3C + &s5p_device_rtc, +#endif + &herring_input_device, + + &s5pv210_device_iis0, + &s3c_device_wdt, + +#ifdef CONFIG_FB_S3C + &s3c_device_fb, +#endif + +#ifdef CONFIG_VIDEO_MFC50 + &s3c_device_mfc, +#endif +#ifdef CONFIG_S5P_ADC + &s3c_device_adc, +#endif +#ifdef CONFIG_VIDEO_FIMC + &s3c_device_fimc0, + &s3c_device_fimc1, + &s3c_device_fimc2, +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + &s3c_device_jpeg, +#endif + + &s3c_device_g3d, + &s3c_device_lcd, + +#ifdef CONFIG_FB_S3C_TL2796 + &s3c_device_spi_gpio, +#endif + &sec_device_jack, + + &s3c_device_i2c0, +#if defined(CONFIG_S3C_DEV_I2C1) + &s3c_device_i2c1, +#endif + +#if defined(CONFIG_S3C_DEV_I2C2) + &s3c_device_i2c2, +#endif + &herring_i2c4_device, + &herring_i2c6_device, + &herring_i2c7_device, + &herring_i2c8_device, /* gyro sensor */ + &herring_i2c9_device, /* max1704x:fuel_guage */ + &herring_i2c11_device, /* optical sensor */ + &herring_i2c12_device, /* magnetic sensor */ + &herring_i2c14_device, /* nfc sensor */ +#ifdef CONFIG_USB_GADGET + &s3c_device_usbgadget, +#endif +#ifdef CONFIG_USB_ANDROID + &s3c_device_android_usb, +#ifdef CONFIG_USB_ANDROID_MASS_STORAGE + &s3c_device_usb_mass_storage, +#endif +#ifdef CONFIG_USB_ANDROID_RNDIS + &s3c_device_rndis, +#endif +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + &s3c_device_hsmmc0, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + &s3c_device_hsmmc1, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + &s3c_device_hsmmc2, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + &s3c_device_hsmmc3, +#endif + + &sec_device_battery, + &herring_i2c10_device, + +#ifdef CONFIG_S5PV210_POWER_DOMAIN + &s5pv210_pd_audio, + &s5pv210_pd_cam, + &s5pv210_pd_tv, + &s5pv210_pd_lcd, + &s5pv210_pd_g3d, + &s5pv210_pd_mfc, +#endif + +#ifdef CONFIG_ANDROID_PMEM + &pmem_device, + &pmem_gpu1_device, + &pmem_adsp_device, +#endif + +#ifdef CONFIG_HAVE_PWM + &s3c_device_timer[0], + &s3c_device_timer[1], + &s3c_device_timer[2], + &s3c_device_timer[3], +#endif + +#ifdef CONFIG_CPU_FREQ + &s5pv210_device_cpufreq, +#endif + + &sec_device_rfkill, + &sec_device_btsleep, + &ram_console_device, + &sec_device_wifi, + &samsung_asoc_dma, +}; + +unsigned int HWREV; +EXPORT_SYMBOL(HWREV); + +static void __init herring_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s5pv210_gpiolib_init(); + s3c24xx_init_uarts(herring_uartcfgs, ARRAY_SIZE(herring_uartcfgs)); +#ifndef CONFIG_S5P_HIGH_RES_TIMERS + s5p_set_timer_source(S5P_PWM3, S5P_PWM4); +#endif + s5p_reserve_bootmem(herring_media_devs, + ARRAY_SIZE(herring_media_devs), S5P_RANGE_MFC); +#ifdef CONFIG_MTD_ONENAND + s5p_device_onenand.name = "s5pc110-onenand"; +#endif +} + +unsigned int pm_debug_scratchpad; + +static unsigned int ram_console_start; +static unsigned int ram_console_size; + +static void __init herring_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, + struct meminfo *mi) +{ + mi->bank[0].start = 0x30000000; + mi->bank[0].size = 80 * SZ_1M; + + mi->bank[1].start = 0x40000000; + mi->bank[1].size = 256 * SZ_1M; + + mi->bank[2].start = 0x50000000; + /* 1M for ram_console buffer */ + mi->bank[2].size = 127 * SZ_1M; + mi->nr_banks = 3; + + ram_console_start = mi->bank[2].start + mi->bank[2].size; + ram_console_size = SZ_1M - SZ_4K; + + pm_debug_scratchpad = ram_console_start + ram_console_size; +} + +/* this function are used to detect s5pc110 chip version temporally */ +int s5pc110_version ; + +void _hw_version_check(void) +{ + void __iomem *phy_address ; + int temp; + + phy_address = ioremap(0x40, 1); + + temp = __raw_readl(phy_address); + + if (temp == 0xE59F010C) + s5pc110_version = 0; + else + s5pc110_version = 1; + + printk(KERN_INFO "S5PC110 Hardware version : EVT%d\n", + s5pc110_version); + + iounmap(phy_address); +} + +/* + * Temporally used + * return value 0 -> EVT 0 + * value 1 -> evt 1 + */ + +int hw_version_check(void) +{ + return s5pc110_version ; +} +EXPORT_SYMBOL(hw_version_check); + +static void herring_init_gpio(void) +{ + s3c_config_gpio_table(); + s3c_config_sleep_gpio_table(ARRAY_SIZE(herring_sleep_gpio_table), + herring_sleep_gpio_table); + if (herring_is_cdma_wimax_dev()) + s3c_config_sleep_gpio_table( + ARRAY_SIZE(herring_cdma_wimax_sleep_gpio_table), + herring_cdma_wimax_sleep_gpio_table); + +} + +static void __init fsa9480_gpio_init(void) +{ + if (herring_is_cdma_wimax_dev()) { + s3c_gpio_cfgpin(GPIO_USB_HS_SEL, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_USB_HS_SEL, 1); + } else { + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_JACK_nINT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_JACK_nINT, S3C_GPIO_PULL_NONE); +} + +static void __init setup_ram_console_mem(void) +{ + ram_console_resource[0].start = ram_console_start; + ram_console_resource[0].end = ram_console_start + ram_console_size - 1; +} + +static void __init sound_init(void) +{ + u32 reg; + + reg = __raw_readl(S5P_OTHERS); + reg &= ~(0x3 << 8); + reg |= 3 << 8; + __raw_writel(reg, S5P_OTHERS); + + reg = __raw_readl(S5P_CLK_OUT); + reg &= ~(0x1f << 12); + reg |= 19 << 12; + __raw_writel(reg, S5P_CLK_OUT); + + reg = __raw_readl(S5P_CLK_OUT); + reg &= ~0x1; + reg |= 0x1; + __raw_writel(reg, S5P_CLK_OUT); + + gpio_request(GPIO_MICBIAS_EN, "micbias_enable"); +} + +static s8 accel_rotation_wimax_rev0[9] = { + 0, -1, 0, + -1, 0, 0, + 0, 0, -1, +}; + +static void __init accel_init(void) +{ + if (herring_is_cdma_wimax_rev0()) + kr3dm_data.rotation = accel_rotation_wimax_rev0; +} + +static bool console_flushed; + +static void flush_console(void) +{ + if (console_flushed) + return; + + console_flushed = true; + + printk("\n"); + pr_emerg("Restarting %s\n", linux_banner); + if (!is_console_locked()) + return; + + mdelay(50); + + local_irq_disable(); + if (!console_trylock()) + pr_emerg("flush_console: console was locked! busting!\n"); + else + pr_emerg("flush_console: console was locked!\n"); + console_unlock(); +} + +static void herring_pm_restart(char mode, const char *cmd) +{ + flush_console(); + + /* On a normal reboot, INFORM6 will contain a small integer + * reason code from the notifier hook. On a panic, it will + * contain the 0xee we set at boot. Write 0xbb to differentiate + * a watchdog-timeout-and-reboot (0xee) from a controlled reboot + * (0xbb) + */ + if (__raw_readl(S5P_INFORM6) == 0xee) + __raw_writel(0xbb, S5P_INFORM6); + + arm_machine_restart(mode, cmd); +} + +static void __init herring_machine_init(void) +{ + arm_pm_restart = herring_pm_restart; + + setup_ram_console_mem(); + platform_add_devices(herring_devices, ARRAY_SIZE(herring_devices)); + if (!herring_is_tft_dev()) + platform_device_register(&herring_i2c5_device); + + /* Find out S5PC110 chip version */ + _hw_version_check(); + + pm_power_off = herring_power_off ; + + s3c_gpio_cfgpin(GPIO_HWREV_MODE0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE0, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE1, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE1, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE2, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE2, S3C_GPIO_PULL_NONE); + HWREV = gpio_get_value(GPIO_HWREV_MODE0); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE1) << 1); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE2) << 2); + s3c_gpio_cfgpin(GPIO_HWREV_MODE3, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE3, S3C_GPIO_PULL_NONE); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE3) << 3); + printk(KERN_INFO "HWREV is 0x%x\n", HWREV); + + /*initialise the gpio's*/ + herring_init_gpio(); + +#ifdef CONFIG_ANDROID_PMEM + android_pmem_set_platdata(); +#endif + + /* headset/earjack detection */ + if (system_rev >= 0x09) + gpio_request(GPIO_EAR_MICBIAS_EN, "ear_micbias_enable"); + + gpio_request(GPIO_TOUCH_EN, "touch en"); + + /* i2c */ + s3c_i2c0_set_platdata(NULL); +#ifdef CONFIG_S3C_DEV_I2C1 + s3c_i2c1_set_platdata(NULL); +#endif + +#ifdef CONFIG_S3C_DEV_I2C2 + s3c_i2c2_set_platdata(NULL); +#endif + k3g_irq_init(); + set_adc_table(); + accel_init(); + /* H/W I2C lines */ + if (system_rev >= 0x05) { + /* gyro sensor */ + if (herring_is_cdma_wimax_dev() && herring_is_cdma_wimax_rev0()) + i2c_register_board_info(5, i2c_devs0, + ARRAY_SIZE(i2c_devs0)); + else + i2c_register_board_info(0, i2c_devs0, + ARRAY_SIZE(i2c_devs0)); + /* magnetic and accel sensor */ + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + } + mxt224_init(); + i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2)); + + /* wm8994 codec */ + sound_init(); + i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4)); + /* accel sensor for rev04 */ + if (system_rev == 0x04) + i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5)); + + if (herring_is_cdma_wimax_dev()) { + struct max8998_platform_data *pdata = + (struct max8998_platform_data *)&max8998_pdata; + pdata->num_regulators = + ARRAY_SIZE(herring_cdma_wimax_regulators); + pdata->regulators = herring_cdma_wimax_regulators; + } + + i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6)); + if (!herring_is_tft_dev()) { + /* Touch Key */ + touch_keypad_gpio_init(); + i2c_register_board_info(10, i2c_devs10, ARRAY_SIZE(i2c_devs10)); + } else { + herring_virtual_keys_init(); + } + /* FSA9480 */ + fsa9480_gpio_init(); + i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7)); + + /* gyro sensor for rev04 */ + if (system_rev == 0x04) + i2c_register_board_info(8, i2c_devs8, ARRAY_SIZE(i2c_devs8)); + + i2c_register_board_info(9, i2c_devs9, ARRAY_SIZE(i2c_devs9)); + /* optical sensor */ + gp2a_gpio_init(); + i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11)); + /* magnetic sensor for rev04 */ + if (system_rev == 0x04) + i2c_register_board_info(12, i2c_devs12, ARRAY_SIZE(i2c_devs12)); + + /* nfc sensor */ + i2c_register_board_info(14, i2c_devs14, ARRAY_SIZE(i2c_devs14)); + + /* max8893 wimax PMIC */ + if (herring_is_cdma_wimax_dev()) { + platform_device_register(&herring_i2c15_device); + i2c_register_board_info(15, i2c_devs15, ARRAY_SIZE(i2c_devs15)); + } + + if (!herring_is_tft_dev()) { + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + s3cfb_set_platdata(&tl2796_data); + } else { + switch (lcd_type) { + case 1: + spi_register_board_info(spi_board_info_hydis, + ARRAY_SIZE(spi_board_info_hydis)); + s3cfb_set_platdata(&nt35580_data); + break; + case 2: + spi_register_board_info(spi_board_info_hitachi, + ARRAY_SIZE(spi_board_info_hitachi)); + s3cfb_set_platdata(&r61408_data); + break; + default: + spi_register_board_info(spi_board_info_sony, + ARRAY_SIZE(spi_board_info_sony)); + s3cfb_set_platdata(&nt35580_data); + break; + } + } + +#if defined(CONFIG_S5P_ADC) + s3c_adc_set_platdata(&s3c_adc_platform); +#endif + +#if defined(CONFIG_PM) + s3c_pm_init(); +#endif + + s5ka3dfx_request_gpio(); + + s5k4ecgx_init(); + +#ifdef CONFIG_VIDEO_FIMC + /* fimc */ + s3c_fimc0_set_platdata(&fimc_plat_lsi); + s3c_fimc1_set_platdata(&fimc_plat_lsi); + s3c_fimc2_set_platdata(&fimc_plat_lsi); +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + s3c_jpeg_set_platdata(&jpeg_plat); +#endif + +#ifdef CONFIG_VIDEO_MFC50 + /* mfc */ + s3c_mfc_set_platdata(NULL); +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + s5pv210_default_sdhci0(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + s5pv210_default_sdhci1(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + s5pv210_default_sdhci2(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + s5pv210_default_sdhci3(); +#endif +#ifdef CONFIG_S5PV210_SETUP_SDHCI + s3c_sdhci_set_platdata(); +#endif + +#ifdef CONFIG_CPU_FREQ + s5pv210_cpufreq_set_platdata(&smdkc110_cpufreq_plat); +#endif + + regulator_has_full_constraints(); + + register_reboot_notifier(&herring_reboot_notifier); + + herring_switch_init(); + + gps_gpio_init(); + + uart_switch_init(); + + herring_init_wifi_mem(); + + if (herring_is_cdma_wimax_dev()) + platform_device_register(&s3c_device_cmc732); + + /* write something into the INFORM6 register that we can use to + * differentiate an unclear reboot from a clean reboot (which + * writes a small integer code to INFORM6). + */ + __raw_writel(0xee, S5P_INFORM6); +} + +#ifdef CONFIG_USB_SUPPORT +/* Initializes OTG Phy. */ +void otg_phy_init(void) +{ + /* USB PHY0 Enable */ + writel(readl(S5P_USB_PHY_CONTROL) | (0x1<<0), + S5P_USB_PHY_CONTROL); + writel((readl(S3C_USBOTG_PHYPWR) & ~(0x3<<3) & ~(0x1<<0)) | (0x1<<5), + S3C_USBOTG_PHYPWR); + writel((readl(S3C_USBOTG_PHYCLK) & ~(0x5<<2)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + writel((readl(S3C_USBOTG_RSTCON) & ~(0x3<<1)) | (0x1<<0), + S3C_USBOTG_RSTCON); + msleep(1); + writel(readl(S3C_USBOTG_RSTCON) & ~(0x7<<0), + S3C_USBOTG_RSTCON); + msleep(1); + + /* rising/falling time */ + writel(readl(S3C_USBOTG_PHYTUNE) | (0x1<<20), + S3C_USBOTG_PHYTUNE); + + /* set DC level as 0xf (24%) */ + writel(readl(S3C_USBOTG_PHYTUNE) | 0xf, S3C_USBOTG_PHYTUNE); +} +EXPORT_SYMBOL(otg_phy_init); + +/* USB Control request data struct must be located here for DMA transfer */ +struct usb_ctrlrequest usb_ctrl __attribute__((aligned(64))); + +/* OTG PHY Power Off */ +void otg_phy_off(void) +{ + writel(readl(S3C_USBOTG_PHYPWR) | (0x3<<3), + S3C_USBOTG_PHYPWR); + writel(readl(S5P_USB_PHY_CONTROL) & ~(1<<0), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(otg_phy_off); + +void usb_host_phy_init(void) +{ + struct clk *otg_clk; + + otg_clk = clk_get(NULL, "otg"); + clk_enable(otg_clk); + + if (readl(S5P_USB_PHY_CONTROL) & (0x1<<1)) + return; + + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) | (0x1<<1), + S5P_USB_PHY_CONTROL); + __raw_writel((__raw_readl(S3C_USBOTG_PHYPWR) + & ~(0x1<<7) & ~(0x1<<6)) | (0x1<<8) | (0x1<<5), + S3C_USBOTG_PHYPWR); + __raw_writel((__raw_readl(S3C_USBOTG_PHYCLK) & ~(0x1<<7)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + __raw_writel((__raw_readl(S3C_USBOTG_RSTCON)) | (0x1<<4) | (0x1<<3), + S3C_USBOTG_RSTCON); + __raw_writel(__raw_readl(S3C_USBOTG_RSTCON) & ~(0x1<<4) & ~(0x1<<3), + S3C_USBOTG_RSTCON); +} +EXPORT_SYMBOL(usb_host_phy_init); + +void usb_host_phy_off(void) +{ + __raw_writel(__raw_readl(S3C_USBOTG_PHYPWR) | (0x1<<7)|(0x1<<6), + S3C_USBOTG_PHYPWR); + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) & ~(1<<1), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(usb_host_phy_off); +#endif + +MACHINE_START(HERRING, "herring") + .boot_params = S5P_PA_SDRAM + 0x100, + .fixup = herring_fixup, + .init_irq = s5pv210_init_irq, + .map_io = herring_map_io, + .init_machine = herring_machine_init, +#ifdef CONFIG_S5P_HIGH_RES_TIMERS + .timer = &s5p_systimer, +#else + .timer = &s5p_timer, +#endif +MACHINE_END + +void s3c_setup_uart_cfg_gpio(unsigned char port) +{ + switch (port) { + case 0: + s3c_gpio_cfgpin(GPIO_BT_RXD, S3C_GPIO_SFN(GPIO_BT_RXD_AF)); + s3c_gpio_setpull(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_TXD, S3C_GPIO_SFN(GPIO_BT_TXD_AF)); + s3c_gpio_setpull(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_CTS, S3C_GPIO_SFN(GPIO_BT_CTS_AF)); + s3c_gpio_setpull(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_RTS, S3C_GPIO_SFN(GPIO_BT_RTS_AF)); + s3c_gpio_setpull(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_TXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_CTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + break; + case 1: + s3c_gpio_cfgpin(GPIO_GPS_RXD, S3C_GPIO_SFN(GPIO_GPS_RXD_AF)); + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_GPS_TXD, S3C_GPIO_SFN(GPIO_GPS_TXD_AF)); + s3c_gpio_setpull(GPIO_GPS_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_CTS, S3C_GPIO_SFN(GPIO_GPS_CTS_AF)); + s3c_gpio_setpull(GPIO_GPS_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_RTS, S3C_GPIO_SFN(GPIO_GPS_RTS_AF)); + s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_NONE); + break; + case 2: + s3c_gpio_cfgpin(GPIO_AP_RXD, S3C_GPIO_SFN(GPIO_AP_RXD_AF)); + s3c_gpio_setpull(GPIO_AP_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_AP_TXD, S3C_GPIO_SFN(GPIO_AP_TXD_AF)); + s3c_gpio_setpull(GPIO_AP_TXD, S3C_GPIO_PULL_NONE); + break; + case 3: + s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(GPIO_FLM_RXD_AF)); + s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(GPIO_FLM_TXD_AF)); + s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); + break; + default: + break; + } +} +EXPORT_SYMBOL(s3c_setup_uart_cfg_gpio); diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 24febae..39f3270 100644..100755 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -25,8 +25,16 @@ #include <mach/regs-irq.h> #include <mach/regs-clock.h> +#include <mach/regs-mem.h> +#include <mach/power-domain.h> + +static struct sleep_save core_save[] = { + /* PLL Control */ + SAVE_ITEM(S5P_APLL_CON), + SAVE_ITEM(S5P_MPLL_CON), + SAVE_ITEM(S5P_EPLL_CON), + SAVE_ITEM(S5P_VPLL_CON), -static struct sleep_save s5pv210_core_save[] = { /* Clock source */ SAVE_ITEM(S5P_CLK_SRC0), SAVE_ITEM(S5P_CLK_SRC1), @@ -72,7 +80,7 @@ static struct sleep_save s5pv210_core_save[] = { /* Clock Blcok and Bus gate */ SAVE_ITEM(S5P_CLKGATE_BLOCK), - SAVE_ITEM(S5P_CLKGATE_BUS0), + SAVE_ITEM(S5P_CLKGATE_IP5), /* Clock ETC */ SAVE_ITEM(S5P_CLK_OUT), @@ -115,10 +123,6 @@ static void s5pv210_pm_prepare(void) /* ensure at least INFORM0 has the resume address */ __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); - tmp = __raw_readl(S5P_SLEEP_CFG); - tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); - __raw_writel(tmp, S5P_SLEEP_CFG); - /* WFI for SLEEP mode configuration by SYSCON */ tmp = __raw_readl(S5P_PWR_CFG); tmp &= S5P_CFG_WFI_CLEAN; @@ -130,7 +134,12 @@ static void s5pv210_pm_prepare(void) tmp |= S5P_OTHER_SYSC_INTOFF; __raw_writel(tmp, S5P_OTHERS); - s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); + __raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR)); + + s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); } static int s5pv210_pm_add(struct sys_device *sysdev) @@ -153,14 +162,29 @@ arch_initcall(s5pv210_pm_drvinit); static void s5pv210_pm_resume(void) { - u32 tmp; + u32 tmp, audiodomain_on; + + tmp = __raw_readl(S5P_NORMAL_CFG); + if (tmp & S5PV210_PD_AUDIO) + audiodomain_on = 0; + else { + tmp |= S5PV210_PD_AUDIO; + __raw_writel(tmp , S5P_NORMAL_CFG); + audiodomain_on = 1; + } tmp = __raw_readl(S5P_OTHERS); tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\ S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART); __raw_writel(tmp , S5P_OTHERS); - s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); + if (audiodomain_on) { + tmp = __raw_readl(S5P_NORMAL_CFG); + tmp &= ~S5PV210_PD_AUDIO; + __raw_writel(tmp , S5P_NORMAL_CFG); + } + + s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); } static struct syscore_ops s5pv210_pm_syscore_ops = { diff --git a/arch/arm/mach-s5pv210/power-domain.c b/arch/arm/mach-s5pv210/power-domain.c new file mode 100644 index 0000000..683901c --- /dev/null +++ b/arch/arm/mach-s5pv210/power-domain.c @@ -0,0 +1,566 @@ +/* linux/arch/arm/mach-s5pv210/power-domain.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Power domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/mutex.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <mach/power-domain.h> + +#include <mach/regs-clock.h> +#include <plat/devs.h> + +struct s5pv210_pd_data { + struct regulator_desc desc; + struct regulator_dev *dev; + int microvolts; + unsigned startup_delay; + struct clk_should_be_running *clk_run; + int ctrlbit; +}; + +struct clk_should_be_running { + const char *clk_name; + struct device *dev; +}; +static spinlock_t pd_lock; + +static struct regulator_consumer_supply s5pv210_pd_audio_supply[] = { + REGULATOR_SUPPLY("pd", "samsung-i2s.0"), +}; + +static struct regulator_consumer_supply s5pv210_pd_cam_supply[] = { + REGULATOR_SUPPLY("pd", "s3c-fimc.0"), + REGULATOR_SUPPLY("pd", "s3c-fimc.1"), + REGULATOR_SUPPLY("pd", "s3c-fimc.2"), + REGULATOR_SUPPLY("pd", "s3c-jpg"), + REGULATOR_SUPPLY("pd", "s3c-csis"), + REGULATOR_SUPPLY("pd", "s5p-rotator"), +}; + +static struct regulator_consumer_supply s5pv210_pd_tv_supply[] = { + REGULATOR_SUPPLY("pd", "s5p-tvout"), +}; + +static struct regulator_consumer_supply s5pv210_pd_lcd_supply[] = { + REGULATOR_SUPPLY("pd", "s3cfb"), +}; + +static struct regulator_consumer_supply s5pv210_pd_g3d_supply[] = { + REGULATOR_SUPPLY("pd", "pvrsrvkm"), +}; + +static struct regulator_consumer_supply s5pv210_pd_mfc_supply[] = { + REGULATOR_SUPPLY("pd", "s3c-mfc"), +}; + +static struct regulator_init_data s5pv210_pd_audio_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_audio_supply), + .consumer_supplies = s5pv210_pd_audio_supply, +}; + +static struct regulator_init_data s5pv210_pd_cam_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_cam_supply), + .consumer_supplies = s5pv210_pd_cam_supply, +}; + +static struct regulator_init_data s5pv210_pd_tv_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_tv_supply), + .consumer_supplies = s5pv210_pd_tv_supply, +}; + +static struct regulator_init_data s5pv210_pd_lcd_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_lcd_supply), + .consumer_supplies = s5pv210_pd_lcd_supply, +}; + +static struct regulator_init_data s5pv210_pd_g3d_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_g3d_supply), + .consumer_supplies = s5pv210_pd_g3d_supply, +}; + +static struct regulator_init_data s5pv210_pd_mfc_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_mfc_supply), + .consumer_supplies = s5pv210_pd_mfc_supply, +}; + +struct clk_should_be_running s5pv210_pd_audio_clk[] = { + { + .clk_name = "i2scdclk", + .dev = &s5pv210_device_iis0.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_cam_clk[] = { + { + .clk_name = "fimc", + .dev = &s3c_device_fimc0.dev, + }, { + .clk_name = "fimc", + .dev = &s3c_device_fimc1.dev, + }, { + .clk_name = "fimc", + .dev = &s3c_device_fimc2.dev, + }, { + .clk_name = "sclk_csis", + .dev = &s5p_device_mipi_csis0.dev, + }, { + .clk_name = "jpeg", + .dev = &s3c_device_jpeg.dev, + }, { + .clk_name = "rot", + .dev = &s5p_device_rotator.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_tv_clk[] = { + { + .clk_name = "vp", + .dev = &s5p_device_tvout.dev, + }, { + .clk_name = "mixer", + .dev = &s5p_device_tvout.dev, + }, { + .clk_name = "tvenc", + .dev = &s5p_device_tvout.dev, + }, { + .clk_name = "hdmi", + .dev = &s5p_device_tvout.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_lcd_clk[] = { + { + .clk_name = "lcd", + .dev = &s3c_device_fb.dev, + }, { + .clk_name = "dsim", + .dev = &s3c_device_fb.dev, + }, { + .clk_name = "sclk_fimg2d", + .dev = &s3c_device_fb.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_g3d_clk[] = { + { + .clk_name = "sclk", + .dev = &s3c_device_g3d.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_mfc_clk[] = { + { + .clk_name = "mfc", + .dev = &s3c_device_mfc.dev, + }, { + /* end of the clock array */ + }, +}; + +static struct s5pv210_pd_config s5pv210_pd_audio_pdata = { + .supply_name = "pd_audio_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_audio_data, + .clk_run = s5pv210_pd_audio_clk, + .ctrlbit = S5PV210_PD_AUDIO, +}; + +static struct s5pv210_pd_config s5pv210_pd_cam_pdata = { + .supply_name = "pd_cam_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_cam_data, + .clk_run = s5pv210_pd_cam_clk, + .ctrlbit = S5PV210_PD_CAM, +}; + +static struct s5pv210_pd_config s5pv210_pd_tv_pdata = { + .supply_name = "pd_tv_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_tv_data, + .clk_run = s5pv210_pd_tv_clk, + .ctrlbit = S5PV210_PD_TV, +}; + +static struct s5pv210_pd_config s5pv210_pd_lcd_pdata = { + .supply_name = "pd_lcd_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_lcd_data, + .clk_run = s5pv210_pd_lcd_clk, + .ctrlbit = S5PV210_PD_LCD, +}; + +static struct s5pv210_pd_config s5pv210_pd_g3d_pdata = { + .supply_name = "pd_g3d_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_g3d_data, + .clk_run = s5pv210_pd_g3d_clk, + .ctrlbit = S5PV210_PD_G3D, +}; + +static struct s5pv210_pd_config s5pv210_pd_mfc_pdata = { + .supply_name = "pd_mfc_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_mfc_data, + .clk_run = s5pv210_pd_mfc_clk, + .ctrlbit = S5PV210_PD_MFC, +}; + +struct platform_device s5pv210_pd_audio = { + .name = "reg-s5pv210-pd", + .id = 0, + .dev = { + .platform_data = &s5pv210_pd_audio_pdata, + }, +}; + +struct platform_device s5pv210_pd_cam = { + .name = "reg-s5pv210-pd", + .id = 1, + .dev = { + .platform_data = &s5pv210_pd_cam_pdata, + }, +}; + +struct platform_device s5pv210_pd_tv = { + .name = "reg-s5pv210-pd", + .id = 2, + .dev = { + .platform_data = &s5pv210_pd_tv_pdata, + }, +}; + +struct platform_device s5pv210_pd_lcd = { + .name = "reg-s5pv210-pd", + .id = 3, + .dev = { + .platform_data = &s5pv210_pd_lcd_pdata, + }, +}; + +struct platform_device s5pv210_pd_g3d = { + .name = "reg-s5pv210-pd", + .id = 4, + .dev = { + .platform_data = &s5pv210_pd_g3d_pdata, + }, +}; + +struct platform_device s5pv210_pd_mfc = { + .name = "reg-s5pv210-pd", + .id = 5, + .dev = { + .platform_data = &s5pv210_pd_mfc_pdata, + }, +}; + +static int s5pv210_pd_pwr_done(int ctrl) +{ + unsigned int cnt; + cnt = 1000; + + do { + if (__raw_readl(S5P_BLK_PWR_STAT) & ctrl) + return 0; + udelay(1); + } while (cnt-- > 0); + + return -ETIME; +} + +static int s5pv210_pd_pwr_off(int ctrl) +{ + unsigned int cnt; + cnt = 1000; + + do { + if (!(__raw_readl(S5P_BLK_PWR_STAT) & ctrl)) + return 0; + udelay(1); + } while (cnt-- > 0); + + return -ETIME; +} + +static int s5pv210_pd_ctrl(int ctrlbit, int enable) +{ + u32 pd_reg; + + spin_lock(&pd_lock); + pd_reg = __raw_readl(S5P_NORMAL_CFG); + if (enable) { + __raw_writel((pd_reg | ctrlbit), S5P_NORMAL_CFG); + if (s5pv210_pd_pwr_done(ctrlbit)) + goto out; + } else { + __raw_writel((pd_reg & ~(ctrlbit)), S5P_NORMAL_CFG); + if (s5pv210_pd_pwr_off(ctrlbit)) + goto out; + } + spin_unlock(&pd_lock); + return 0; +out: + spin_unlock(&pd_lock); + return -ETIME; + +} + +static int s5pv210_pd_clk_enable(struct clk_should_be_running *clk_run) +{ + struct clk *clkp; + int i; + + for (i = 0;; i++) { + if (clk_run[i].clk_name == NULL) + break; + + clkp = clk_get(clk_run[i].dev, clk_run[i].clk_name); + + if (IS_ERR(clkp)) { + printk(KERN_ERR "unable to get clock %s\n", + clk_run[i].clk_name); + } else { + clk_enable(clkp); + clk_put(clkp); + } + } + + return 0; +} + +static int s5pv210_pd_clk_disable(struct clk_should_be_running *clk_run) +{ + struct clk *clkp; + int i; + + for (i = 0;; i++) { + if (clk_run[i].clk_name == NULL) + break; + + clkp = clk_get(clk_run[i].dev, clk_run[i].clk_name); + + if (IS_ERR(clkp)) { + printk(KERN_ERR "unable to get clock %s\n", + clk_run[i].clk_name); + } else { + clk_disable(clkp); + clk_put(clkp); + } + } + + return 0; +} + +static int s5pv210_pd_is_enabled(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + return (__raw_readl(S5P_BLK_PWR_STAT) & data->ctrlbit) ? 1 : 0; +} + +static int s5pv210_pd_enable(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + int ret = 0; + + if (data->clk_run) + s5pv210_pd_clk_enable(data->clk_run); + + ret = s5pv210_pd_ctrl(data->ctrlbit, 1); + if (ret < 0) { + printk(KERN_ERR "failed to enable power domain\n"); + } + + if (data->clk_run) + s5pv210_pd_clk_disable(data->clk_run); + + return ret; +} + +static int s5pv210_pd_disable(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + int ret; + + ret = s5pv210_pd_ctrl(data->ctrlbit, 0); + if (ret < 0) { + printk(KERN_ERR "faild to disable power domain\n"); + return ret; + } + + return 0; +} + +static int s5pv210_pd_enable_time(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + return data->startup_delay; +} + +static int s5pv210_pd_get_voltage(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + return data->microvolts; +} + +static int s5pv210_pd_list_voltage(struct regulator_dev *dev, + unsigned selector) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + if (selector != 0) + return -EINVAL; + + return data->microvolts; +} + +static struct regulator_ops s5pv210_pd_ops = { + .is_enabled = s5pv210_pd_is_enabled, + .enable = s5pv210_pd_enable, + .disable = s5pv210_pd_disable, + .enable_time = s5pv210_pd_enable_time, + .get_voltage = s5pv210_pd_get_voltage, + .list_voltage = s5pv210_pd_list_voltage, +}; + +static int __devinit reg_s5pv210_pd_probe(struct platform_device *pdev) +{ + struct s5pv210_pd_config *config = pdev->dev.platform_data; + struct s5pv210_pd_data *drvdata; + int ret; + + drvdata = kzalloc(sizeof(struct s5pv210_pd_data), GFP_KERNEL); + if (drvdata == NULL) { + dev_err(&pdev->dev, "Failed to allocate device data\n"); + ret = -ENOMEM; + goto err; + } + + drvdata->desc.name = kstrdup(config->supply_name, GFP_KERNEL); + if (drvdata->desc.name == NULL) { + dev_err(&pdev->dev, "Failed to allocate supply name\n"); + ret = -ENOMEM; + goto err; + } + + drvdata->desc.type = REGULATOR_VOLTAGE; + drvdata->desc.owner = THIS_MODULE; + drvdata->desc.ops = &s5pv210_pd_ops; + drvdata->desc.n_voltages = 1; + + drvdata->microvolts = config->microvolts; + drvdata->startup_delay = config->startup_delay; + + drvdata->clk_run = config->clk_run; + drvdata->ctrlbit = config->ctrlbit; + spin_lock_init(&pd_lock); + + drvdata->dev = regulator_register(&drvdata->desc, &pdev->dev, + config->init_data, drvdata); + if (IS_ERR(drvdata->dev)) { + ret = PTR_ERR(drvdata->dev); + dev_err(&pdev->dev, "Failed to register regulator: %d\n", ret); + goto err_name; + } + + platform_set_drvdata(pdev, drvdata); + + dev_dbg(&pdev->dev, "%s supplying %duV\n", drvdata->desc.name, + drvdata->microvolts); + + return 0; + +err_name: + kfree(drvdata->desc.name); +err: + kfree(drvdata); + return ret; +} + +static int __devexit reg_s5pv210_pd_remove(struct platform_device *pdev) +{ + struct s5pv210_pd_data *drvdata = platform_get_drvdata(pdev); + + regulator_unregister(drvdata->dev); + kfree(drvdata->desc.name); + kfree(drvdata); + + return 0; +} + +static struct platform_driver regulator_s5pv210_pd_driver = { + .probe = reg_s5pv210_pd_probe, + .remove = __devexit_p(reg_s5pv210_pd_remove), + .driver = { + .name = "reg-s5pv210-pd", + .owner = THIS_MODULE, + }, +}; + +static int __init regulator_s5pv210_pd_init(void) +{ + return platform_driver_register(®ulator_s5pv210_pd_driver); +} +subsys_initcall(regulator_s5pv210_pd_init); + +static void __exit regulator_s5pv210_pd_exit(void) +{ + platform_driver_unregister(®ulator_s5pv210_pd_driver); +} +module_exit(regulator_s5pv210_pd_exit); + +MODULE_AUTHOR("HuiSung Kang <hs1218.kang@samsung.com>"); +MODULE_DESCRIPTION("S5PV210 power domain regulator"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:reg-s5pv210-pd"); diff --git a/arch/arm/mach-s5pv210/sec_switch.c b/arch/arm/mach-s5pv210/sec_switch.c new file mode 100644 index 0000000..5408618 --- /dev/null +++ b/arch/arm/mach-s5pv210/sec_switch.c @@ -0,0 +1,293 @@ +/* + * UART/USB path switching driver for Samsung Electronics devices. + * + * Copyright (C) 2010 Samsung Electronics. + * + * Authors: Ikkeun Kim <iks.kim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/switch.h> +#include <linux/fsa9480.h> +#include <linux/mfd/max8998.h> +#include <linux/regulator/consumer.h> +#include <linux/moduleparam.h> +#include <asm/mach/arch.h> +#include <mach/param.h> +#include <mach/gpio.h> +#include <mach/gpio-p1.h> +#include <mach/sec_switch.h> +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> +#include <plat/gpio-cfg.h> + +struct sec_switch_struct { + struct sec_switch_platform_data *pdata; + int switch_sel; +}; + +struct sec_switch_wq { + struct delayed_work work_q; + struct sec_switch_struct *sdata; + struct list_head entry; +}; + +/* for sysfs control (/sys/class/sec/switch/) */ +extern struct device *switch_dev; + +static void usb_switch_mode(struct sec_switch_struct *secsw, int mode) +{ + if (mode == SWITCH_PDA) { + if (secsw->pdata && secsw->pdata->set_vbus_status) + secsw->pdata->set_vbus_status((u8)USB_VBUS_AP_ON); + mdelay(10); + fsa9480_manual_switching(SWITCH_PORT_AUTO); + } else { + if (secsw->pdata && secsw->pdata->set_vbus_status) + secsw->pdata->set_vbus_status((u8)USB_VBUS_CP_ON); + mdelay(10); + fsa9480_manual_switching(SWITCH_PORT_AUDIO); + } +} + +static ssize_t uart_sel_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + int uart_sel = secsw->switch_sel & UART_SEL_MASK; + + return sprintf(buf, "%s UART\n", uart_sel ? "PDA" : "MODEM"); +} + +static ssize_t uart_sel_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + + if (sec_get_param_value) + sec_get_param_value(__SWITCH_SEL, &secsw->switch_sel); + + if (strncmp(buf, "PDA", 3) == 0 || strncmp(buf, "pda", 3) == 0) { + gpio_set_value(GPIO_UART_SEL, 1); + secsw->switch_sel |= UART_SEL_MASK; + pr_debug("[UART Switch] Path : PDA\n"); + } + + if (strncmp(buf, "MODEM", 5) == 0 || strncmp(buf, "modem", 5) == 0) { + gpio_set_value(GPIO_UART_SEL, 0); + secsw->switch_sel &= ~UART_SEL_MASK; + pr_debug("[UART Switch] Path : MODEM\n"); + } + + if (sec_set_param_value) + sec_set_param_value(__SWITCH_SEL, &secsw->switch_sel); + + return size; +} + +static ssize_t usb_sel_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + int usb_path = secsw->switch_sel & USB_SEL_MASK; + return sprintf(buf, "%s USB\n", usb_path ? "PDA" : "MODEM"); +} + +static ssize_t usb_sel_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + + if (sec_get_param_value) + sec_get_param_value(__SWITCH_SEL, &secsw->switch_sel); + + if (strncmp(buf, "PDA", 3) == 0 || strncmp(buf, "pda", 3) == 0) { + usb_switch_mode(secsw, SWITCH_PDA); + secsw->switch_sel |= USB_SEL_MASK; + } + + if (strncmp(buf, "MODEM", 5) == 0 || strncmp(buf, "modem", 5) == 0) { + usb_switch_mode(secsw, SWITCH_MODEM); + secsw->switch_sel &= ~USB_SEL_MASK; + } + + if (sec_set_param_value) + sec_set_param_value(__SWITCH_SEL, &secsw->switch_sel); + + return size; +} + +static ssize_t usb_state_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + int cable_state = CABLE_TYPE_NONE; + + if (secsw->pdata && secsw->pdata->get_cable_status) + cable_state = secsw->pdata->get_cable_status(); + + return sprintf(buf, "%s\n", (cable_state == CABLE_TYPE_USB) ? + "USB_STATE_CONFIGURED" : "USB_STATE_NOTCONFIGURED"); +} + +static ssize_t usb_state_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + return 0; +} + +static ssize_t disable_vbus_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t disable_vbus_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + + if (IS_ERR_OR_NULL(secsw->pdata) || + IS_ERR_OR_NULL(secsw->pdata->set_vbus_status) || + IS_ERR_OR_NULL(secsw->pdata->set_usb_gadget_vbus)) + return size; + + secsw->pdata->set_usb_gadget_vbus(false); + secsw->pdata->set_vbus_status((u8)USB_VBUS_ALL_OFF); + msleep(10); + secsw->pdata->set_usb_gadget_vbus(true); + + return size; +} + +static DEVICE_ATTR(uart_sel, 0664, uart_sel_show, uart_sel_store); +static DEVICE_ATTR(usb_sel, 0664, usb_sel_show, usb_sel_store); +static DEVICE_ATTR(usb_state, 0664, usb_state_show, usb_state_store); +static DEVICE_ATTR(disable_vbus, 0664, disable_vbus_show, disable_vbus_store); + +static void sec_switch_init_work(struct work_struct *work) +{ + struct delayed_work *dw = container_of(work, struct delayed_work, work); + struct sec_switch_wq *wq = container_of(dw, struct sec_switch_wq, work_q); + struct sec_switch_struct *secsw = wq->sdata; + int usb_sel = 0; + int uart_sel = 0; + + if (sec_get_param_value && + secsw->pdata && + secsw->pdata->set_vbus_status && + secsw->pdata->get_phy_init_status && + secsw->pdata->get_phy_init_status()) { + sec_get_param_value(__SWITCH_SEL, &secsw->switch_sel); + cancel_delayed_work(&wq->work_q); + } else { + schedule_delayed_work(&wq->work_q, msecs_to_jiffies(1000)); + return; + } + + pr_debug("%s : initial sec switch value = 0x%X\n", __func__, secsw->switch_sel); + + usb_sel = secsw->switch_sel & USB_SEL_MASK; + uart_sel = secsw->switch_sel & UART_SEL_MASK; + + /* init UART/USB path */ + if (usb_sel) + usb_switch_mode(secsw, SWITCH_PDA); + else + usb_switch_mode(secsw, SWITCH_MODEM); + + if (uart_sel) + gpio_set_value(GPIO_UART_SEL, 1); + else + gpio_set_value(GPIO_UART_SEL, 0); +} + +static int sec_switch_probe(struct platform_device *pdev) +{ + struct sec_switch_struct *secsw; + struct sec_switch_platform_data *pdata = pdev->dev.platform_data; + struct sec_switch_wq *wq; + + + if (!pdata) { + pr_err("%s : pdata is NULL.\n", __func__); + return -ENODEV; + } + + secsw = kzalloc(sizeof(struct sec_switch_struct), GFP_KERNEL); + if (!secsw) { + pr_err("%s : failed to allocate memory\n", __func__); + return -ENOMEM; + } + + secsw->pdata = pdata; + secsw->switch_sel = 1; + + dev_set_drvdata(switch_dev, secsw); + + /* create sysfs files */ + if (device_create_file(switch_dev, &dev_attr_uart_sel) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_uart_sel.attr.name); + + if (device_create_file(switch_dev, &dev_attr_usb_sel) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_usb_sel.attr.name); + + if (device_create_file(switch_dev, &dev_attr_usb_state) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_usb_state.attr.name); + + if (device_create_file(switch_dev, &dev_attr_disable_vbus) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_usb_state.attr.name); + + /* run work queue */ + wq = kmalloc(sizeof(struct sec_switch_wq), GFP_ATOMIC); + if (wq) { + wq->sdata = secsw; + INIT_DELAYED_WORK(&wq->work_q, sec_switch_init_work); + schedule_delayed_work(&wq->work_q, msecs_to_jiffies(100)); + } else + return -ENOMEM; + + return 0; +} + +static int sec_switch_remove(struct platform_device *pdev) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(&pdev->dev); + kfree(secsw); + return 0; +} + +static struct platform_driver sec_switch_driver = { + .probe = sec_switch_probe, + .remove = sec_switch_remove, + .driver = { + .name = "sec_switch", + .owner = THIS_MODULE, + }, +}; + +static int __init sec_switch_init(void) +{ + return platform_driver_register(&sec_switch_driver); +} + +static void __exit sec_switch_exit(void) +{ + platform_driver_unregister(&sec_switch_driver); +} + +module_init(sec_switch_init); +module_exit(sec_switch_exit); + +MODULE_AUTHOR("Ikkeun Kim <iks.kim@samsung.com>"); +MODULE_DESCRIPTION("Samsung Electronics Corp Switch driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/setup-fb.c b/arch/arm/mach-s5pv210/setup-fb.c new file mode 100644 index 0000000..85adf23 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fb.c @@ -0,0 +1,226 @@ +/* linux/arch/arm/mach-s5pv210/setup-fb.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMD controller configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/types.h> +#include <plat/clock.h> +#include <plat/gpio-cfg.h> +#include <plat/fb.h> +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> +#include <linux/io.h> +#include <mach/map.h> + +struct platform_device; /* don't need the contents */ + +void s3cfb_cfg_gpio(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + } + + /* mDNIe SEL: why we shall write 0x2 ? */ + writel(0x2, S5P_MDNIE_SEL); + + /* drive strength to max */ + writel(0xffffffff, S5PV210_GPF0_BASE + 0xc); + writel(0xffffffff, S5PV210_GPF1_BASE + 0xc); + writel(0xffffffff, S5PV210_GPF2_BASE + 0xc); + writel(0x000000ff, S5PV210_GPF3_BASE + 0xc); +} + +int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk) +{ + struct clk *sclk = NULL; + struct clk *mout_mpll = NULL; + u32 rate = 0; + + sclk = clk_get(&pdev->dev, "sclk_fimd"); + if (IS_ERR(sclk)) { + dev_err(&pdev->dev, "failed to get sclk for fimd\n"); + goto err_clk1; + } + + mout_mpll = clk_get(&pdev->dev, "mout_mpll"); + if (IS_ERR(mout_mpll)) { + dev_err(&pdev->dev, "failed to get mout_mpll\n"); + goto err_clk2; + } + + clk_set_parent(sclk, mout_mpll); + + if (!rate) + rate = 166750000; + + clk_set_rate(sclk, rate); + dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate); + + clk_put(mout_mpll); + + clk_enable(sclk); + + *s3cfb_clk = sclk; + + return 0; + +err_clk2: + clk_put(sclk); + +err_clk1: + return -EINVAL; +} + +int s3cfb_clk_off(struct platform_device *pdev, struct clk **clk) +{ + clk_disable(*clk); + clk_put(*clk); + + *clk = NULL; + + return 0; +} + +void s3cfb_get_clk_name(char *clk_name) +{ + strcpy(clk_name, "sclk_fimd"); +} +#ifdef CONFIG_FB_S3C_LTE480WV +int s3cfb_backlight_onoff(struct platform_device *pdev, int onoff) +{ + int err; + + err = gpio_request(S5PV210_GPD0(3), "GPD0"); + + if (err) { + printk(KERN_ERR "failed to request GPD0 for " + "lcd backlight control\n"); + return err; + } + + if (onoff) { + gpio_direction_output(S5PV210_GPD0(3), 1); + /* 2009.12.28 by icarus : added for PWM backlight */ + s3c_gpio_cfgpin(S5PV210_GPD0(3), S5PV210_GPD_0_3_TOUT_3); + + } else { + gpio_direction_output(S5PV210_GPD0(3), 0); + } + gpio_free(S5PV210_GPD0(3)); + return 0; +} + +int s3cfb_reset_lcd(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_GPH0(6), "GPH0"); + if (err) { + printk(KERN_ERR "failed to request GPH0 for " + "lcd reset control\n"); + return err; + } + + gpio_direction_output(S5PV210_GPH0(6), 1); + mdelay(100); + + gpio_set_value(S5PV210_GPH0(6), 0); + mdelay(10); + + gpio_set_value(S5PV210_GPH0(6), 1); + mdelay(10); + + gpio_free(S5PV210_GPH0(6)); + + return 0; +} +#elif defined(CONFIG_FB_S3C_HT101HD1) +int s3cfb_backlight_on(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_GPB(2), "GPB"); + if (err) { + printk(KERN_ERR "failed to request GPB for " + "lcd backlight control\n"); + return err; + } + +#ifdef CONFIG_TYPE_PROTO3 + err = gpio_request(S5PV210_GPD0(1), "GPD0"); + if (err) { + printk(KERN_ERR "failed to request GPD0 for " + "lcd backlight control\n"); + return err; + } +#endif + + gpio_direction_output(S5PV210_GPB(2), 1); /* LED_EN (SPI1_MOSI) */ + +#ifdef CONFIG_TYPE_PROTO3 + /* LCD_PWR_EN is only for Proto3 */ + gpio_direction_output(S5PV210_GPD0(1), 1); + mdelay(10); +#endif + + gpio_free(S5PV210_GPB(2)); +#ifdef CONFIG_TYPE_PROTO3 + gpio_free(S5PV210_GPD0(1)); +#endif + + return 0; +} + +int s3cfb_reset_lcd(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_GPH0(1), "GPH0"); + if (err) { + printk(KERN_ERR "failed to request GPH0 for " + "lcd reset control\n"); + return err; + } + + gpio_direction_output(S5PV210_GPH0(1), 1); + + gpio_set_value(S5PV210_GPH0(1), 0); + + gpio_set_value(S5PV210_GPH0(1), 1); + + gpio_free(S5PV210_GPH0(1)); + + return 0; +} +#endif diff --git a/arch/arm/mach-s5pv210/setup-fimc0.c b/arch/arm/mach-s5pv210/setup-fimc0.c new file mode 100644 index 0000000..6b4b39b --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fimc0.c @@ -0,0 +1,122 @@ +/* linux/arch/arm/mach-s5pv210/setup-fimc0.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMC 0 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/gpio.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <plat/clock.h> +#include <plat/gpio-cfg.h> +#include <plat/map-s5p.h> +#include <mach/regs-gpio.h> +#include <mach/map.h> +#include <plat/regs-fimc.h> + +struct platform_device; /* don't need the contents */ + +void s3c_fimc0_cfg_gpio(struct platform_device *pdev) +{ + int i = 0; + + /* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */ + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPE0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPE0(i), S3C_GPIO_PULL_NONE); + } + /* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */ + for (i = 0; i < 3; i++) { + s3c_gpio_cfgpin(S5PV210_GPE1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPE1(i), S3C_GPIO_PULL_NONE); + } + +#if defined(CONFIG_MACH_SMDKC110) || defined(CONFIG_MACH_SMDKV210) + s3c_gpio_cfgpin(S5PV210_GPE1(4), S5PV210_GPE1_4_CAM_A_FIELD); + s3c_gpio_setpull(S5PV210_GPE1(4), S3C_GPIO_PULL_NONE); + + /* CAM B port(b0011) : DATA[0-7] */ + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPJ0(i), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PV210_GPJ0(i), S3C_GPIO_PULL_NONE); + } + /* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLCKOUT */ + for (i = 0; i < 5; i++) { + s3c_gpio_cfgpin(S5PV210_GPJ1(i), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PV210_GPJ1(i), S3C_GPIO_PULL_NONE); + } +#endif + + /* note : driver strength to max is unnecessary */ +} + +int s3c_fimc_clk_on(struct platform_device *pdev, struct clk *clk) +{ + struct clk *sclk_fimc_lclk = NULL; + struct clk *mout_fimc_lclk = NULL; + struct clk *mout_mpll = NULL; + + mout_mpll = clk_get(&pdev->dev, "mout_mpll"); + if (IS_ERR(mout_mpll)) { + dev_err(&pdev->dev, "failed to get mout_mpll\n"); + goto err_clk1; + } + + mout_fimc_lclk = clk_get(&pdev->dev, "mout_fimc_lclk"); + if (IS_ERR(mout_fimc_lclk)) { + dev_err(&pdev->dev, "failed to get mout_fimc_lclk\n"); + goto err_clk2; + } + + sclk_fimc_lclk = clk_get(&pdev->dev, "fimc"); + if (IS_ERR(sclk_fimc_lclk)) { + dev_err(&pdev->dev, "failed to get sclk_fimc_lclk\n"); + goto err_clk3; + } + + clk_set_parent(mout_fimc_lclk, mout_mpll); + clk_set_rate(sclk_fimc_lclk, 166750000); + + /* be able to handle clock on/off only with this clock */ + clk = clk_get(&pdev->dev, "fimc"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "failed to get interface clock\n"); + goto err_clk3; + } + + clk_put(mout_mpll); + clk_put(mout_fimc_lclk); + + clk_enable(clk); + + return 0; + +err_clk3: + clk_put(mout_fimc_lclk); + +err_clk2: + clk_put(mout_mpll); + +err_clk1: + return -EINVAL; +} + +int s3c_fimc_clk_off(struct platform_device *pdev, struct clk *clk) +{ + clk_disable(clk); + clk_put(clk); + + clk = NULL; + + return 0; +} diff --git a/arch/arm/mach-s5pv210/setup-fimc1.c b/arch/arm/mach-s5pv210/setup-fimc1.c new file mode 100644 index 0000000..5ec1301 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fimc1.c @@ -0,0 +1,21 @@ +/* linux/arch/arm/mach-s5pv210/setup-fimc1.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMC 1 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> + +void s3c_fimc1_cfg_gpio(struct platform_device *pdev) { } diff --git a/arch/arm/mach-s5pv210/setup-fimc2.c b/arch/arm/mach-s5pv210/setup-fimc2.c new file mode 100644 index 0000000..aaa6f6e --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fimc2.c @@ -0,0 +1,21 @@ +/* linux/arch/arm/mach-s5pv210/setup-fimc2.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMC 2 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> + +void s3c_fimc2_cfg_gpio(struct platform_device *pdev) { } diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c index 0f1cc3a..39b644f 100644 --- a/arch/arm/mach-s5pv210/setup-i2c0.c +++ b/arch/arm/mach-s5pv210/setup-i2c0.c @@ -24,5 +24,5 @@ struct platform_device; /* don't need the contents */ void s3c_i2c0_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); } diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c index f61365a..834b318 100644 --- a/arch/arm/mach-s5pv210/setup-i2c1.c +++ b/arch/arm/mach-s5pv210/setup-i2c1.c @@ -24,5 +24,5 @@ struct platform_device; /* don't need the contents */ void s3c_i2c1_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); } diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c index 2f91b5c..3bdc649 100644 --- a/arch/arm/mach-s5pv210/setup-i2c2.c +++ b/arch/arm/mach-s5pv210/setup-i2c2.c @@ -24,5 +24,5 @@ struct platform_device; /* don't need the contents */ void s3c_i2c2_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); } diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index 3e3ac05..26aaa87 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -23,82 +23,131 @@ #include <plat/regs-sdhci.h> #include <plat/sdhci.h> +#include "herring.h" + +#if defined (CONFIG_SAMSUNG_GALAXYS) || defined(CONFIG_SAMSUNG_FASCINATE) +# define DRVSTR S3C_GPIO_DRVSTR_3X +#else +# define DRVSTR S3C_GPIO_DRVSTR_2X +#endif + void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPG0/GPG1 pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2)); + unsigned int gpio; switch (width) { + /* Channel 0 supports 4 and 8-bit bus width */ case 8: - /* GPG1[3:6] special-function 3 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3)); + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s3c_gpio_set_drvstrength(gpio, DRVSTR); + } + + case 0: + case 1: case 4: - /* GPG0[3:6] special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2)); - default: + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG0(0); gpio <= S5PV210_GPG0(6); gpio++) { + if (gpio != S5PV210_GPG0(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + s3c_gpio_set_drvstrength(gpio, DRVSTR); + } break; + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); + } + + if (machine_is_herring() || machine_is_aries()) { + s3c_gpio_cfgpin(S5PV210_GPJ2(7), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPJ2(7), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPJ2(7), 1); } - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); + if (machine_is_herring()) { // This is not done for aries in the original kernel + gpio_direction_output(S5PV210_GPJ2(7), 1); + s3c_gpio_setpull(S5PV210_GPJ2(7), S3C_GPIO_PULL_NONE); } } void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPG1[0:1] pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2)); - - /* Data pin GPG1[3:6] to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2)); + unsigned int gpio; - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); + switch (width) { + /* Channel 1 supports 4-bit bus width */ + case 0: + case 1: + case 4: + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG1(0); gpio <= S5PV210_GPG1(6); gpio++) { + if (gpio != S5PV210_GPG1(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + s3c_gpio_set_drvstrength(gpio, DRVSTR); + } + break; + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } } void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPG2[0:1] pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2)); + unsigned int gpio; switch (width) { + /* Channel 2 supports 4 and 8-bit bus width */ case 8: - /* Data pin GPG3[3:6] to special-function 3 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3)); + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s3c_gpio_set_drvstrength(gpio, DRVSTR); + } + + case 0: + case 1: case 4: - /* Data pin GPG2[3:6] to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2)); - default: + if (machine_is_herring() && herring_is_cdma_wimax_dev()) + break; + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG2(0); gpio <= S5PV210_GPG2(6); gpio++) { + if (gpio != S5PV210_GPG2(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + s3c_gpio_set_drvstrength(gpio, DRVSTR); + } break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } } void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; - /* Set all the necessary GPG3[0:1] pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2)); - - /* Data pin GPG3[3:6] to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2)); - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2)); + switch (width) { + /* Channel 3 supports 4-bit bus width */ + case 0: + case 1: + case 4: + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG3(0); gpio <= S5PV210_GPG3(6); gpio++) { + if (gpio != S5PV210_GPG3(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + } + s3c_gpio_set_drvstrength(gpio, DRVSTR); + } + break; + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } } diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index a83b6c9..d778239 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -15,6 +15,7 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/irq.h> #include <linux/mmc/card.h> #include <linux/mmc/host.h> @@ -22,6 +23,13 @@ #include <plat/regs-sdhci.h> #include <plat/sdhci.h> +#include <plat/gpio-cfg.h> +#include <plat/devs.h> +#include <mach/regs-gpio.h> +#include <mach/gpio.h> + +#include "herring.h" + /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ char *s5pv210_hsmmc_clksrcs[4] = { @@ -31,33 +39,256 @@ char *s5pv210_hsmmc_clksrcs[4] = { /* [3] = NULL, - reserved */ }; +#define S3C_SDHCI_CTRL3_FCSELTX_INVERT (0) +#define S3C_SDHCI_CTRL3_FCSELTX_BASIC \ + (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2) +#define S3C_SDHCI_CTRL3_FCSELRX_INVERT (0) +#define S3C_SDHCI_CTRL3_FCSELRX_BASIC \ + (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0) + void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, struct mmc_card *card) { - u32 ctrl2, ctrl3; - - /* don't need to alter anything according to card-type */ - - writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); + u32 ctrl2; + u32 ctrl3; ctrl2 = readl(r + S3C_SDHCI_CONTROL2); ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | S3C_SDHCI_CTRL2_DFCNT_NONE | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + if (ios->clock <= (400 * 1000)) { + ctrl2 &= ~(S3C_SDHCI_CTRL2_ENFBCLKTX | + S3C_SDHCI_CTRL2_ENFBCLKRX); + ctrl3 = 0; + } else { + u32 range_start; + u32 range_end; + + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKTX | + S3C_SDHCI_CTRL2_ENFBCLKRX; + + if (card->type == MMC_TYPE_MMC) /* MMC */ + range_start = 20 * 1000 * 1000; + //else /* SD, SDIO */ + // range_start = 25 * 1000 * 1000; + + range_end = 37 * 1000 * 1000; + + if ((ios->clock > range_start) && (ios->clock < range_end)) + ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC | + S3C_SDHCI_CTRL3_FCSELRX_BASIC; + else if (machine_is_herring() && herring_is_cdma_wimax_dev() && + dev->id == 2) { + ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC; + //if(card->type & MMC_TYPE_SDIO) + ctrl3 |= S3C_SDHCI_CTRL3_FCSELRX_BASIC; + //else + // ctrl3 |= S3C_SDHCI_CTRL3_FCSELRX_INVERT; + } else + ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC | + S3C_SDHCI_CTRL3_FCSELRX_INVERT; + } + writel(ctrl2, r + S3C_SDHCI_CONTROL2); writel(ctrl3, r + S3C_SDHCI_CONTROL3); } + +void s5pv210_adjust_sdhci_cfg_card(struct s3c_sdhci_platdata *pdata, + void __iomem *r, int rw) +{ + u32 ctrl2, ctrl3; + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + ctrl3 = readl(r + S3C_SDHCI_CONTROL3); + + if (rw == 0) { + pdata->rx_cfg++; + if (pdata->rx_cfg == 1) { + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKRX; + ctrl3 |= S3C_SDHCI_CTRL3_FCSELRX_BASIC; + } else if (pdata->rx_cfg == 2) { + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKRX; + ctrl3 &= ~S3C_SDHCI_CTRL3_FCSELRX_BASIC; + } else if (pdata->rx_cfg == 3) { + ctrl2 &= ~(S3C_SDHCI_CTRL2_ENFBCLKTX | + S3C_SDHCI_CTRL2_ENFBCLKRX); + pdata->rx_cfg = 0; + } + } else if (rw == 1) { + pdata->tx_cfg++; + if (pdata->tx_cfg == 1) { + if (ctrl2 & S3C_SDHCI_CTRL2_ENFBCLKRX) { + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKTX; + ctrl3 |= S3C_SDHCI_CTRL3_FCSELTX_BASIC; + } else { + ctrl2 &= ~S3C_SDHCI_CTRL2_ENFBCLKTX; + } + } else if (pdata->tx_cfg == 2) { + ctrl2 &= ~S3C_SDHCI_CTRL2_ENFBCLKTX; + pdata->tx_cfg = 0; + } + } else { + printk(KERN_ERR "%s, unknown value rw:%d\n", __func__, rw); + return; + } + + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} + +void universal_sdhci2_cfg_ext_cd(void) +{ + printk(KERN_DEBUG "Universal :SD Detect configuration\n"); +#if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_VIBRANT) + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_UP); +#else + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_NONE); +#endif + irq_set_irq_type(IRQ_EINT(28), IRQ_TYPE_EDGE_BOTH); +} + +static struct s3c_sdhci_platdata hsmmc0_platdata = { +#if defined(CONFIG_S5PV210_SD_CH0_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +#if defined(CONFIG_S3C_DEV_HSMMC1) +static struct s3c_sdhci_platdata hsmmc1_platdata = { 0 }; +#endif + +#if defined(CONFIG_S3C_DEV_HSMMC2) +static struct s3c_sdhci_platdata hsmmc2_platdata = { +#if defined(CONFIG_S5PV210_SD_CH2_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; +#endif + +#if defined(CONFIG_S3C_DEV_HSMMC3) +static struct s3c_sdhci_platdata hsmmc3_platdata = { 0 }; +#endif + +static DEFINE_MUTEX(notify_lock); + +#define DEFINE_MMC_CARD_NOTIFIER(num) \ +static void (*hsmmc##num##_notify_func)(struct platform_device *, int state); \ +static int ext_cd_init_hsmmc##num(void (*notify_func)( \ + struct platform_device *, int state)) \ +{ \ + mutex_lock(¬ify_lock); \ + WARN_ON(hsmmc##num##_notify_func); \ + hsmmc##num##_notify_func = notify_func; \ + mutex_unlock(¬ify_lock); \ + return 0; \ +} \ +static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \ + struct platform_device *, int state)) \ +{ \ + mutex_lock(¬ify_lock); \ + WARN_ON(hsmmc##num##_notify_func != notify_func); \ + hsmmc##num##_notify_func = NULL; \ + mutex_unlock(¬ify_lock); \ + return 0; \ +} + +#ifdef CONFIG_S3C_DEV_HSMMC1 +DEFINE_MMC_CARD_NOTIFIER(1) +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 +DEFINE_MMC_CARD_NOTIFIER(2) +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 +DEFINE_MMC_CARD_NOTIFIER(3) +#endif + +/* + * call this when you need sd stack to recognize insertion or removal of card + * that can't be told by SDHCI regs + */ +void sdhci_s3c_force_presence_change(struct platform_device *pdev) +{ + void (*notify_func)(struct platform_device *, int state) = NULL; + mutex_lock(¬ify_lock); +#ifdef CONFIG_S3C_DEV_HSMMC1 + if (pdev == &s3c_device_hsmmc1) + notify_func = hsmmc1_notify_func; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + if (pdev == &s3c_device_hsmmc2) + notify_func = hsmmc2_notify_func; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + if (pdev == &s3c_device_hsmmc3) + notify_func = hsmmc3_notify_func; +#endif + + if (notify_func) + notify_func(pdev, 1); + else + pr_warn("%s: called for device with no notifier\n", __func__); + mutex_unlock(¬ify_lock); +} +EXPORT_SYMBOL_GPL(sdhci_s3c_force_presence_change); + +void s3c_sdhci_set_platdata(void) +{ +#if defined(CONFIG_S3C_DEV_HSMMC) + if (machine_is_herring() || machine_is_aries()) { /* TODO: move to mach-herring.c */ + hsmmc0_platdata.cd_type = S3C_SDHCI_CD_PERMANENT; + } + s3c_sdhci0_set_platdata(&hsmmc0_platdata); +#endif +#if defined(CONFIG_S3C_DEV_HSMMC1) + if (machine_is_aries()) { + hsmmc1_platdata.cd_type = S3C_SDHCI_CD_EXTERNAL; + hsmmc1_platdata.ext_cd_init = ext_cd_init_hsmmc1; + hsmmc1_platdata.ext_cd_cleanup = ext_cd_cleanup_hsmmc1; + hsmmc1_platdata.built_in = 1; + } + s3c_sdhci1_set_platdata(&hsmmc1_platdata); +#endif +#if defined(CONFIG_S3C_DEV_HSMMC2) + if (machine_is_herring()) { + if (herring_is_cdma_wimax_dev()) { + hsmmc2_platdata.cd_type = S3C_SDHCI_CD_EXTERNAL; + hsmmc2_platdata.ext_cd_init = ext_cd_init_hsmmc2; + hsmmc2_platdata.ext_cd_cleanup = ext_cd_cleanup_hsmmc2; + hsmmc2_platdata.built_in = 1; + hsmmc2_platdata.must_maintain_clock = 1; + hsmmc2_platdata.enable_intr_on_resume = 1; + } else { + hsmmc2_platdata.cd_type = S3C_SDHCI_CD_GPIO; + hsmmc2_platdata.ext_cd_gpio = S5PV210_GPH3(4); + hsmmc2_platdata.ext_cd_gpio_invert = true; + universal_sdhci2_cfg_ext_cd(); + } + } + + if (machine_is_aries()) { + hsmmc2_platdata.cd_type = S3C_SDHCI_CD_GPIO; + hsmmc2_platdata.ext_cd_gpio = S5PV210_GPH3(4); + hsmmc2_platdata.ext_cd_gpio_invert = true; + universal_sdhci2_cfg_ext_cd(); + } + + s3c_sdhci2_set_platdata(&hsmmc2_platdata); +#endif +#if defined(CONFIG_S3C_DEV_HSMMC3) + if (machine_is_herring() || machine_is_aries()) { + hsmmc3_platdata.cd_type = S3C_SDHCI_CD_EXTERNAL; + hsmmc3_platdata.ext_cd_init = ext_cd_init_hsmmc3; + hsmmc3_platdata.ext_cd_cleanup = ext_cd_cleanup_hsmmc3; + hsmmc3_platdata.built_in = 1; + } + s3c_sdhci3_set_platdata(&hsmmc3_platdata); +#endif +}; diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S index a3d6494..758c913 100644 --- a/arch/arm/mach-s5pv210/sleep.S +++ b/arch/arm/mach-s5pv210/sleep.S @@ -49,6 +49,10 @@ ENTRY(s3c_cpu_save) mov pc, r0 resume_with_mmu: + /* Invalidate TLB after mucking with MMU table. */ + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB + ldmfd sp!, { r3 - r12, pc } .ltorg |