diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/clocks.h | 20 | ||||
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/constants.h | 8 | ||||
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/dma.h | 79 | ||||
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/hardware.h | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/irqs.h | 7 | ||||
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/registers.h | 64 | ||||
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/ssp.h | 71 | ||||
| -rw-r--r-- | include/asm-arm/arch-lh7a40x/uncompress.h | 2 |
8 files changed, 234 insertions, 21 deletions
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h new file mode 100644 index 0000000..bee02fd --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/clocks.h @@ -0,0 +1,20 @@ +/* include/asm-arm/arch-lh7a40x/clocks.h + * + * Copyright (C) 2004 Marc Singer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/config.h> + +#ifndef __ASM_ARCH_CLOCKS_H +#define __ASM_ARCH_CLOCKS_H + +unsigned int fclkfreq_get (void); +unsigned int hclkfreq_get (void); +unsigned int pclkfreq_get (void); + +#endif /* _ASM_ARCH_CLOCKS_H */ diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h index 52c1cb9..2929e89 100644 --- a/include/asm-arm/arch-lh7a40x/constants.h +++ b/include/asm-arm/arch-lh7a40x/constants.h @@ -29,8 +29,7 @@ #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) -# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */ -/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */ +# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */ # define IOBARRIER_VIRT 0xf0000000 # define IOBARRIER_SIZE PAGE_SIZE @@ -53,6 +52,9 @@ # define CPLD08_PHYS CPLDX_PHYS (0x08) # define CPLD08_VIRT CPLDX_VIRT (0x08) # define CPLD08_SIZE PAGE_SIZE +# define CPLD0A_PHYS CPLDX_PHYS (0x0a) +# define CPLD0A_VIRT CPLDX_VIRT (0x0a) +# define CPLD0A_SIZE PAGE_SIZE # define CPLD0C_PHYS CPLDX_PHYS (0x0c) # define CPLD0C_VIRT CPLDX_VIRT (0x0c) # define CPLD0C_SIZE PAGE_SIZE @@ -84,5 +86,7 @@ #define XTAL_IN 14745600 /* 14.7456 MHz crystal */ #define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ #define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ +#define HCLK (99993600) +//#define HCLK (119808000) #endif /* __ASM_ARCH_CONSTANTS_H */ diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h index 15492e3..a8cbd14 100644 --- a/include/asm-arm/arch-lh7a40x/dma.h +++ b/include/asm-arm/arch-lh7a40x/dma.h @@ -1,9 +1,86 @@ /* include/asm-arm/arch-lh7a40x/dma.h * - * Copyright (C) 2003 Coastal Environmental Systems + * Copyright (C) 2005 Marc Singer * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * */ + +typedef enum { + DMA_M2M0 = 0, + DMA_M2M1 = 1, + DMA_M2P0 = 2, /* Tx */ + DMA_M2P1 = 3, /* Rx */ + DMA_M2P2 = 4, /* Tx */ + DMA_M2P3 = 5, /* Rx */ + DMA_M2P4 = 6, /* Tx - AC97 */ + DMA_M2P5 = 7, /* Rx - AC97 */ + DMA_M2P6 = 8, /* Tx */ + DMA_M2P7 = 9, /* Rx */ +} dma_device_t; + +#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */ + +#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80) +#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0) + +#define DMAC_GIR_MMI1 (1<<11) +#define DMAC_GIR_MMI0 (1<<10) +#define DMAC_GIR_MPI8 (1<<9) +#define DMAC_GIR_MPI9 (1<<8) +#define DMAC_GIR_MPI6 (1<<7) +#define DMAC_GIR_MPI7 (1<<6) +#define DMAC_GIR_MPI4 (1<<5) +#define DMAC_GIR_MPI5 (1<<4) +#define DMAC_GIR_MPI2 (1<<3) +#define DMAC_GIR_MPI3 (1<<2) +#define DMAC_GIR_MPI0 (1<<1) +#define DMAC_GIR_MPI1 (1<<0) + +#define DMAC_M2P0 0x0000 +#define DMAC_M2P1 0x0040 +#define DMAC_M2P2 0x0080 +#define DMAC_M2P3 0x00c0 +#define DMAC_M2P4 0x0240 +#define DMAC_M2P5 0x0200 +#define DMAC_M2P6 0x02c0 +#define DMAC_M2P7 0x0280 +#define DMAC_M2P8 0x0340 +#define DMAC_M2P9 0x0300 +#define DMAC_M2M0 0x0100 +#define DMAC_M2M1 0x0140 + +#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00) +#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04) +#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08) +#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c) +#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14) +#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20) +#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24) +#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28) +#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30) +#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34) +#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38) + +#define DMAC_PCONTROL_ENABLE (1<<4) + +#define DMAC_PORT_USB 0 +#define DMAC_PORT_SDMMC 1 +#define DMAC_PORT_AC97_1 2 +#define DMAC_PORT_AC97_2 3 +#define DMAC_PORT_AC97_3 4 +#define DMAC_PORT_UART1 6 +#define DMAC_PORT_UART2 7 +#define DMAC_PORT_UART3 8 + +#define DMAC_PSTATUS_CURRSTATE_SHIFT 4 +#define DMAC_PSTATUS_CURRSTATE_MASK 0x3 + +#define DMAC_PSTATUS_NEXTBUF (1<<6) +#define DMAC_PSTATUS_STALLRINT (1<<0) + +#define DMAC_INT_CHE (1<<3) +#define DMAC_INT_NFB (1<<1) +#define DMAC_INT_STALL (1<<0) diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h index aeb07c1..e9ff74f 100644 --- a/include/asm-arm/arch-lh7a40x/hardware.h +++ b/include/asm-arm/arch-lh7a40x/hardware.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H +#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */ + #define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) #define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) @@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8; #endif +#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s) + #include "registers.h" #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h index f91f3e5..7e8a217 100644 --- a/include/asm-arm/arch-lh7a40x/irqs.h +++ b/include/asm-arm/arch-lh7a40x/irqs.h @@ -154,9 +154,10 @@ #if !defined (IRQ_GPIO0INTR) # define IRQ_GPIO0INTR IRQ_GPIO0FIQ #endif -#define IRQ_TICK IRQ_TINTR +#define IRQ_TICK IRQ_TINTR #define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ #define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ +#define IRQ_USB IRQ_USBINTR /* USB device */ #ifdef CONFIG_MACH_KEV7A400 # define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ @@ -191,6 +192,10 @@ # define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ #endif +#if defined (CONFIG_MACH_LPD7A400) +# define IRQ_TOUCH IRQ_LPD7A400_TS +#endif + #define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) #endif diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h index 2edb22e..544307b 100644 --- a/include/asm-arm/arch-lh7a40x/registers.h +++ b/include/asm-arm/arch-lh7a40x/registers.h @@ -18,7 +18,7 @@ /* Physical register base addresses */ -#define AC97_PHYS (0x80000000) /* AC97 Controller */ +#define AC97C_PHYS (0x80000000) /* AC97 Controller */ #define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ #define USB_PHYS (0x80000200) /* USB Client */ #define SCI_PHYS (0x80000300) /* Secure Card Interface */ @@ -35,6 +35,8 @@ #define RTC_PHYS (0x80000d00) /* Real-time Clock */ #define GPIO_PHYS (0x80000e00) /* General Purpose IO */ #define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ +#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */ +#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */ #define WDT_PHYS (0x80001400) /* Watchdog Timer */ #define SMC_PHYS (0x80002000) /* Static Memory Controller */ #define SDRC_PHYS (0x80002400) /* SDRAM Controller */ @@ -43,6 +45,7 @@ /* Physical registers of the LH7A404 */ +#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */ #define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ #define USBH_PHYS (0x80009000) /* USB OHCI host controller */ #define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ @@ -53,10 +56,32 @@ /* Clock/State Controller register */ +#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */ #define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ +#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */ +#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */ #define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ - +#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27) +#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26) +#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25) +#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24) +#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23) +#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22) +#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21) +#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20) +#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19) +#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18) +#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17) +#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16) + +#define CSC_PWRSR_CHIPMAN_SHIFT (24) +#define CSC_PWRSR_CHIPMAN_MASK (0xff) +#define CSC_PWRSR_CHIPID_SHIFT (16) +#define CSC_PWRSR_CHIPID_MASK (0xff) + +#define CSC_USBDRESET_APBRESETREG (1<<1) +#define CSC_USBDRESET_IORESETREG (1<<0) /* Interrupt Controller registers */ @@ -109,6 +134,13 @@ #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ #define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ +#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c) +#define GPIO_PADD __REG(GPIO_PHYS + 0x10) +#define GPIO_PAD __REG(GPIO_PHYS + 0x00) +#define GPIO_PCD __REG(GPIO_PHYS + 0x08) +#define GPIO_PCDD __REG(GPIO_PHYS + 0x18) +#define GPIO_PEDD __REG(GPIO_PHYS + 0x24) +#define GPIO_PED __REG(GPIO_PHYS + 0x20) /* Static Memory Controller registers */ @@ -138,20 +170,21 @@ #endif #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) -# define CPLD_CONTROL __REG8(CPLD02_PHYS) -# define CPLD_SPI_DATA __REG8(CPLD06_PHYS) -# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS) -# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS) -# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */ -# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS) -# define CPLD_FLASH __REG8(CPLD10_PHYS) -# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS) -# define CPLD_REVISION __REG8(CPLD14_PHYS) -# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS) -# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS) -# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS) -#endif +# define CPLD_CONTROL __REG16(CPLD02_PHYS) +# define CPLD_SPI_DATA __REG16(CPLD06_PHYS) +# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS) +# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS) +# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */ +# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS) +# define CPLD_FLASH __REG16(CPLD10_PHYS) +# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS) +# define CPLD_REVISION __REG16(CPLD14_PHYS) +# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS) +# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS) +# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS) + +#endif /* Timer registers */ @@ -190,4 +223,3 @@ #endif /* _ASM_ARCH_REGISTERS_H */ - diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h new file mode 100644 index 0000000..132b1c4 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/ssp.h @@ -0,0 +1,71 @@ +/* ssp.h + $Id$ + + written by Marc Singer + 6 Dec 2004 + + Copyright (C) 2004 Marc Singer + + ----------- + DESCRIPTION + ----------- + + This SSP header is available throughout the kernel, for this + machine/architecture, because drivers that use it may be dispersed. + + This file was cloned from the 7952x implementation. It would be + better to share them, but we're taking an easier approach for the + time being. + +*/ + +#if !defined (__SSP_H__) +# define __SSP_H__ + +/* ----- Includes */ + +/* ----- Types */ + +struct ssp_driver { + int (*init) (void); + void (*exit) (void); + void (*acquire) (void); + void (*release) (void); + int (*configure) (int device, int mode, int speed, + int frame_size_write, int frame_size_read); + void (*chip_select) (int enable); + void (*set_callbacks) (void* handle, + irqreturn_t (*callback_tx)(void*), + irqreturn_t (*callback_rx)(void*)); + void (*enable) (void); + void (*disable) (void); +// int (*save_state) (void*); +// void (*restore_state) (void*); + int (*read) (void); + int (*write) (u16 data); + int (*write_read) (u16 data); + void (*flush) (void); + void (*write_async) (void* pv, size_t cb); + size_t (*write_pos) (void); +}; + + /* These modes are only available on the LH79524 */ +#define SSP_MODE_SPI (1) +#define SSP_MODE_SSI (2) +#define SSP_MODE_MICROWIRE (3) +#define SSP_MODE_I2S (4) + + /* CPLD SPI devices */ +#define DEVICE_EEPROM 0 /* Configuration eeprom */ +#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */ +#define DEVICE_CODEC 2 /* Audio codec */ +#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */ + +/* ----- Globals */ + +/* ----- Prototypes */ + +//extern struct ssp_driver lh79520_i2s_driver; +extern struct ssp_driver lh7a400_cpld_ssp_driver; + +#endif /* __SSP_H__ */ diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h index f805334..3d1ce04 100644 --- a/include/asm-arm/arch-lh7a40x/uncompress.h +++ b/include/asm-arm/arch-lh7a40x/uncompress.h @@ -16,7 +16,7 @@ #ifndef UART_R_STATUS # define UART_R_STATUS (0x10) #endif -#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ +#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ /* Access UART with physical addresses before MMU is setup */ #define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) |