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| * drm/radeon/kms: get_power_state early, not when processing IRQRafał Miłecki2010-02-091-4/+4
| | | | | | | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: use power states for dynamic reclockingAlex Deucher2010-02-092-21/+14
| | | | | | | | | | Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add code to select power stateAlex Deucher2010-02-092-0/+131
| | | | | | | | | | | | | | not hooked up yet. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add a power state type based on power state flagsAlex Deucher2010-02-094-1/+102
| | | | | | | | | | | | | | | | | | | | The idea is to flag a power state with a certain type and use that type to decide on what state to select. On r6xx+, we select a state and then transition between clock modes in that state. On pre-r6xx, we transition between states directly. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: don't set pcie lanes for ignored power_stateRafał Miłecki2010-02-091-4/+4
| | | | | | | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: pull power mode info from bios tables (v3)Alex Deucher2010-02-094-0/+506
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The general idea is to validate the current hw state against the set of power states and select a power state based on that. This patch just pulls the power states from the bios and prints the information. It is not currently hooked up in the actual power management code. Hooking it up will require reworking the the current power state selection code and will be handled in a future patch. Additionally, we'd need to decide on some default lower power states for cards without power tables. v2 - increment state_index after checking for default state v3 - fix typo in pm init on pre-atom cards, handle pre-atom cards without x86 bioses Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add functions to get current pcie lanesAlex Deucher2010-02-093-0/+44
| | | | | | | | | | | | | | Currently unused. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add dynamic engine reclocking (V9)Rafał Miłecki2010-02-099-4/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | V2: reorganize functions, fix modesetting calls V3: rebase patch, use radeon's workqueue V4: enable on tested chipsets only, request VBLANK IRQs V5: enable PM on older hardware (IRQs, mode_fixup, dpms) V6: use separate dynpm module parameter V7: drop RADEON_ prefix, set minimum mode for dpms off V8: update legacy encoder call, fix order in rs600 IRQ V9: update compute_clocks call in legacy, not only DPMS_OFF Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: consolidate crtc count in rdevAlex Deucher2010-02-093-9/+7
| | | | | | | | | | | | | | | | | | Set the number of crtcs in rdev at crtc init and use it whenever we need the crtc count rather than recalculating it everytime. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms/r600: reduce gpu cache flushingAlex Deucher2010-02-093-21/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only flush the gpu caches before we submit a fence. This leads to a small performance boost when we take the extra gpu cache flushes out of the ddx and mesa. Once this patch is in and the drm version is bumped, we can remove the flushes from the ddx and drm. Also, remove the extra cache flushes from the blit routine. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: switch all KMS driver ioctls to unlocked.Dave Airlie2010-02-091-12/+12
| | | | | | | | | | | | Internal locking should be sufficent for all these cases. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms/atom: add a helper function to get the radeon connector privAlex Deucher2010-02-091-59/+48
| | | | | | | | | | | | | | | | | | This is used in a lot of places in the atom encoder code. While here fix the spelling of crtc_source_params. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms/atom: clean up spread spectrum codeAlex Deucher2010-02-091-18/+20
| | | | | | | | | | | | | | use a union for the atom args. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add pll quirk for toshiba laptop panelAlex Deucher2010-02-091-0/+18
| | | | | | | | | | | | | | | | | | | | The panel on the Toshiba A300-1BU laptop does not like the PLL dividers selected by the avivo pll algo, but works fine using the older method. Add a quirk to handle it. Should fix fdo bug 26358. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
| * drm/radeon/kms: rework pll algo selectionAlex Deucher2010-02-095-34/+70
| | | | | | | | | | | | | | | | | | | | | | | | Rework the pll algo selection so that the pll algo in use can be selected more easily. This allows us to select different pll divider selection algos for specific monitors that work better with one algo or the other. This is needed for the next patch which adds an LVDS pll quirk for a specific notebook. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: clean up some low-hanging magic numbersAlex Deucher2010-02-093-30/+33
| | | | | | | | | | | | | | | | | | Switch some magic numbers to their proper defines. The register header madness needs to be cleaned up at some point. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add support for hardcoded edids in rom (v2)Alex Deucher2010-02-096-17/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | Some servers hardcode an edid in rom so that they will work properly with KVMs. This is a port of the relevant code from the ddx. [airlied: reworked to validate edid at boot stage - and remove special quirk, if there is a valid EDID in the BIOS rom we'll just try and use it.] Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add workaround for rn50/rv100 serversAlex Deucher2010-02-092-23/+65
| | | | | | | | | | | | | | | | | | | | Some servers have two VGA ports but only report one in the bios connector tables. On these systems always set up the TV DAC so that it displays properly even if the bios is wrong. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add support for hw i2c on r1xx-r5xxAlex Deucher2010-02-096-82/+736
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | wire hw i2c support into radeon i2c algo. fixes merged: - handle bus probing correctly - use meaningful error numbers - abort if transaction fails - The line mapping is different depending on the asic. - protect hw i2c engine with a mutex - rs300 doesn't have a pin select bit - r200 has a different pin select setup Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: add radeon i2c algoAlex Deucher2010-02-055-72/+102
| | | | | | | | | | | | | | Currently just a wrapper around bit algo Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | Merge remote branch 'anholt/drm-intel-next' into drm-next-stageDave Airlie2010-02-2514-313/+1063
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * anholt/drm-intel-next: drm/i915: Record batch buffer following GPU error drm/i915: give up on 8xx lid status drm/i915: reduce some of the duplication of tiling checking drm/i915: blow away userspace mappings before fence change drm/i915: move a gtt flush to the correct place agp/intel: official names for Pineview and Ironlake drm/i915: overlay: drop superflous gpu flushes drm/i915: overlay: nuke readback to flush wc caches drm/i915: provide self-refresh status in debugfs drm/i915: provide FBC status in debugfs drm/i915: fix drps disable so unload & re-load works drm/i915: Fix OGLC performance regression on 945 drm/i915: Deobfuscate the render p-state obfuscation drm/i915: add dynamic performance control support for Ironlake drm/i915: enable memory self refresh on 9xx drm/i915: Don't reserve compatibility fence regs in KMS mode. drm/i915: Keep MCHBAR always enabled drm/i915: Replace open-coded eviction in i915_gem_idle()
| * | drm/i915: Record batch buffer following GPU errorChris Wilson2010-02-225-7/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to improve our diagnostic capabilities following a GPU hang and subsequent reset, we need to record the batch buffer that triggered the error. We assume that the current batch buffer, plus a few details about what else is on the active list, will be sufficient -- at the very least an improvement over nothing. The extra information is stored in /debug/dri/.../i915_error_state following an error, and may be decoded using intel_gpu_tools/tools/intel_error_decode. v2: Avoid excessive work under spinlocks. v3: Include ringbuffer for later analysis. v4: Use kunmap correctly and record more buffer state. v5: Search ringbuffer for current batch buffer v6: Use a work fn for the impossible IRQ error case. v7: Avoid non-atomic paths whilst in IRQ context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: give up on 8xx lid statusJesse Barnes2010-02-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These old machines more often than not lie about their lid state. So don't use it to detect LVDS presence, but leave the event handler to deal with lid open/close, when we might need to reset the mode. Fixes kernel bug #15248 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: reduce some of the duplication of tiling checkingOwain Ainsworth2010-02-223-36/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i915_gem_object_fenceable was mostly just a repeat of the i915_gem_object_fence_offset_ok, but also checking the size (which was checkecd when we allowed that BO to be tiled in the first place). So instead, export the latter function and use it in place. Signed-Off-By: Owain G. Ainsworth <oga@openbsd.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: blow away userspace mappings before fence changeDaniel Vetter2010-02-222-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This aligns it with the other user of i915_gem_clear_fence_reg, which blows away the mapping before changing the fence reg. Only affects userspace if it races against itself when changing tiling parameters, i.e. behaviour is undefined, anyway. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: move a gtt flush to the correct placeDaniel Vetter2010-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change, because gtt flushing is a no-op. Still, try to keep the bookkeeping accurate. The if is still slightly wrong for with execbuf2 even i915-class hw doesn't always need a fence reg for gpu access. But that's for somewhen lateron. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | agp/intel: official names for Pineview and IronlakeZhenyu Wang2010-02-221-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Print official names for Pineview and Ironlake, which is Intel GMA3150 and Intel HD graphics. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: overlay: drop superflous gpu flushesDaniel Vetter2010-02-221-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cache-coherency is maintained by gem. Drop these leftover MI_FLUSH commands from the userspace code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: overlay: nuke readback to flush wc cachesDaniel Vetter2010-02-221-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I retested this and whatever this papered over, the problem doesn't seem to exist anymore. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Eric Anholt <eric@anholt.net> [anholt: fixed up compile warning] Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: provide self-refresh status in debugfsJesse Barnes2010-02-221-0/+21
| | | | | | | | | | | | | | | Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: provide FBC status in debugfsJesse Barnes2010-02-224-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tools like powertop want to check the current FBC status and report it to the user. So add a debugfs file indicating whether FBC is enabled, and if not, why. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: fix drps disable so unload & re-load worksJesse Barnes2010-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | At unload time, we need to disable DRPS, but we need to do it correctly or the GPU will hang and we won't be able to load the module again. So set the SFCAVM bit so we can properly restore the DRPS config at unload. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Fix OGLC performance regression on 945Li Peng2010-02-221-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | He Shuang reported an OGLC performance regression introduced in the patch "enable memory self refresh on 9xx", In that patch, SR on 945 is disabled everytime when calling intel_mark_busy(), while too much of such operation will impact performance. Actually disable SR is necessary only when GPU and Crtc changing from idle to busy. This patch make such optimization. It fixes upstream bug http://bugs.freedesktop.org/show_bug.cgi?id=26422 Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Deobfuscate the render p-state obfuscationMatthew Garrett2010-02-225-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: add dynamic performance control support for IronlakeJesse Barnes2010-02-228-10/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: ykzhao <yakui.zhao@intel.com> [anholt: Resolved against the irq handler loop removal] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: enable memory self refresh on 9xxLi Peng2010-02-222-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling memory self refresh (SR) on 9xx needs to set additional register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the write to self refresh bit and bit 16 to enable the write of self refresh watermark. On 915, bit 12 of INSTPM is used to enable SR. SR will take effect when CPU enters C3+ state and its entry/exit should be automatically controlled by H/W, driver only needs to set SR enable bits in wm update. But this isn't safe in my test on 945 because GPU is hung. So this patch explicitly enables SR when GPU is idle, and disables SR when it is busy. In my test on a netbook of 945GSE chipset, it saves about 0.8W idle power. Signed-off-by: Li Peng <peng.li@intel.com> [anholt: rebased against 33c5fd121eabbccc9103daf6cda36941eb3c349f by adding disable of INSTPM SR bit on 915GM for two pipe setup] Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Don't reserve compatibility fence regs in KMS mode.Eric Anholt2010-02-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The fence start is for compatibility with UMS X Servers before fence management. KMS X Servers only started doing tiling after fence management appeared. Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Keep MCHBAR always enabledZhenyu Wang2010-02-163-122/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | As we need more and more controls within MCHBAR for memory config and power management, this trys to keep MCHBAR enabled from driver load and only tear down in driver unload. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Replace open-coded eviction in i915_gem_idle()Chris Wilson2010-02-161-100/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introduction of the hang-check, we can safely expect that i915_wait_request() will always return even when the GPU hangs, and so do not need to open code the wait in order to manually check for the hang. Also we do not need to always evict all buffers, so only flush the GPU (and wait for it to idle) for KMS, but continue to evict for UMS. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* | | Merge remote branch 'korg/drm-core-next' into drm-next-stageDave Airlie2010-02-2521-187/+156
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * korg/drm-core-next: drm/ttm: handle OOM in ttm_tt_swapout drm/radeon/kms/atom: fix shr/shl ops drm/kms: fix spelling of "CLOCK" drm/kms: fix fb_changed = true else statement drivers/gpu/drm/drm_fb_helper.c: don't use private implementation of atoi() drm: switch all GEM/KMS ioctls to unlocked ioctl status. Use drm_gem_object_[handle_]unreference_unlocked where possible drm: introduce drm_gem_object_[handle_]unreference_unlocked
| * | | drm/ttm: handle OOM in ttm_tt_swapoutMaarten Maathuis2010-02-251-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Without this change I get a general protection fault. - Also use PTR_ERR where applicable. Signed-off-by: Maarten Maathuis <madman2003@gmail.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Acked-by: Thomas Hellstrom <thellstrom@vmware.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | drm/radeon/kms/atom: fix shr/shl opsAlex Deucher2010-02-251-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The whole attribute table is valid for shr/shl ops. Fixes fdo bug 26668 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | drm/kms: fix spelling of "CLOCK"Pavel Roskin2010-02-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Pavel Roskin <proski@gnu.org> [clemens@ladisch.de: merged into drm_fb_helper] Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | drm/kms: fix fb_changed = true else statementDave Airlie2010-02-111-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | a patch from Roel was wrong, fix this properly, really if the fb ptrs are different fb changed shuold be true. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | drivers/gpu/drm/drm_fb_helper.c: don't use private implementation of atoi()Andy Shevchenko2010-02-111-19/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel has simple_strtol() which would be used as atoi(). This is quite the same fix as in 2cb96f86628d6e97fcbda5fe4d8d74876239834c ("fbdev: drop custom atoi from drivers/video/modedb.c") because code in drivers/gpu/drm/drm_fb_helper.c is based on drivers/video/modedb.c. Signed-off-by: Andy Shevchenko <ext-andriy.shevchenko@nokia.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | drm: switch all GEM/KMS ioctls to unlocked ioctl status.Dave Airlie2010-02-111-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These ioctls are all protected by their own locking mechanisms so should be fine to not bother locking around. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | Use drm_gem_object_[handle_]unreference_unlocked where possibleLuca Barbieri2010-02-1115-121/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly obvious simplifications. The i915 pread/pwrite ioctls, intel_overlay_put_image and nouveau_gem_new were incorrectly using the locked versions without locking: this is also fixed in this patch. Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | drm: introduce drm_gem_object_[handle_]unreference_unlockedLuca Barbieri2010-02-112-8/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the drm_gem_object_unreference_unlocked and drm_gem_object_handle_unreference_unlocked functions that do not require holding struct_mutex. drm_gem_object_unreference_unlocked calls the new ->gem_free_object_unlocked entry point if available, and otherwise just takes struct_mutex and just calls ->gem_free_object Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | | | Linux 2.6.33Linus Torvalds2010-02-241-1/+1
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* | | | Merge branch 'urgent' of ↵Linus Torvalds2010-02-241-2/+5
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6 * 'urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6: parisc: Set PCI CLS early in boot.
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