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* MMC: Add support for the controller on JZ4740 SoCs.Lars-Peter Clausen2010-08-051-0/+15
| | | | | | | | | | | | | Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Matt Fleming <matt@console-pimps.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matt Fleming <matt@console-pimps.org> Cc: linux-mmc@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1463/ Patchwork: https://patchwork.linux-mips.org/patch/1523/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MTD: Nand: Add JZ4740 NAND driverLars-Peter Clausen2010-08-051-0/+34
| | | | | | | | | | | | Add support for the NAND controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1470/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* FBDEV: JZ4740: Add framebuffer driverLars-Peter Clausen2010-08-051-0/+67
| | | | | | | | | | | | Add support for the LCD controller on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-fbdev@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1470/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add platform devicesLars-Peter Clausen2010-08-051-0/+36
| | | | | | | | | | Add platform devices for all the JZ4740 platform drivers. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1469/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add DMA support.Lars-Peter Clausen2010-08-051-0/+90
| | | | | | | | | | Add support for DMA transfers on JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1401/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add GPIO supportLars-Peter Clausen2010-08-051-0/+398
| | | | | | | | | | Add gpiolib support for JZ4740 SoCs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1467/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add timer supportLars-Peter Clausen2010-08-051-0/+22
| | | | | | | | | | | | Add support for the timer/counter unit on a JZ4740 SoC. This code is used as a common base for the JZ4740 clocksource/clockevent implementation and PWM support. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1396/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add IRQ handler codeLars-Peter Clausen2010-08-051-0/+57
| | | | | | | | | | Add support for IRQ handling on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1465/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add clock API support.Lars-Peter Clausen2010-08-051-0/+28
| | | | | | | | | | | Add support for managing the clocks found on JZ4740 SoC through the Linux clock API. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1466/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-ChipLars-Peter Clausen2010-08-055-1/+116
| | | | | | | | | | | | Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code. It also adds the iomem addresses for the different components found on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1464/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: HOTPLUG_CPU fixes.David Daney2010-08-051-0/+2
| | | | | | | | | | | | | | | | | | | | * Rename camel-case InitTLBStart_addr to octeon_bootloader_entry_addr. * Convert calls to cvmx_read64_uint32(), to simple pointer dereferences. * Set proper ebase. * Don't confuse coreid and cpu numbers. * Try to maintain consistent bootloader coremask. * Update the signature and boot_init_vector of supported bootloaders. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1491/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Get rid of a bunch of MSI IRQ number definitions.David Daney2010-08-051-64/+2
| | | | | | | | | | MSI IRQ numbers are allocated dynamically, so there is no reason to have all these static definitions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: au1000_eth: Get ethernet address from platform_dataManuel Lauss2010-08-051-0/+1
| | | | | | | | | | | | | | | | | au1000_eth uses firmware calls to get a valid MAC address, and changes it depending on platform device id. This patch moves this logic out of the driver into the platform device registration part, where boards with supported chips can use whatever firmware interface they need; the default implementation maintains compatibility with existing, YAMON-based firmware. Tested-by: Wolfgang Grandegger <wg@denx.de> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: netdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1481/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: remove SOC_AU1X00 in favor of MIPS_ALCHEMYManuel Lauss2010-08-051-2/+2
| | | | | | | | | | Remove the CONFIG_SOC_AU1X00 Kconfig symbol since its job can also be done by MACH_ALCHEMY, now renamed to MIPS_ALCHEMY. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/1461/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: RM7000: Add support for tertiary cacheRicardo Mendoza2010-08-051-0/+2
| | | | | | | | | | Add support for the external T-cache interface. Allow for platform independent size probing from 512KB to 8MB in powers of two. Signed-off-by: Ricardo Mendoza <ricmm@gentoo.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1477/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable heap randomization.David Daney2010-08-051-0/+5
| | | | | | | | | | | | Based somewhat on the PPC implementation. 32-bit processes have the heap randomized in an 8MB space, 256MB for 64-bit processes. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1479/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Randomize mmap if randomize_va_space is setDavid Daney2010-08-051-0/+11
| | | | | | | | | | Fairly straight forward: For 32-bit address spaces randomize within a 16MB space, for 64-bit within a 256MB space. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1480/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: EMMA2RH: Replace EMMA2RH_SW_IRQ_INTxx with EMMA2RH_SW_IRQ(n)Shinya Kuribayashi2010-08-051-32/+1
| | | | | | | | | Don't duplicate worthless lines. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1390/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: EMMA2RH: Replace EMMA2RH_IRQ_INTxx with EMMA2RH_IRQ_INT(n)Shinya Kuribayashi2010-08-052-73/+10
| | | | | | | | | Don't duplicate worthless lines. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1389/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADEShinya Kuribayashi2010-08-051-1/+0
| | | | | | | | | | | | Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts, current EMMA2RH plat_irq_dispatch() supports IP2 only. We can make it configurable in the future, but for the time being, would like to make things explicitly allcated to IP2 in accordance with plat_irq_dispatch(). Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1388/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: EMMA2RH: Remove useless CPU_IRQ_BASEShinya Kuribayashi2010-08-051-3/+1
| | | | | | | | | | | | | | For historical reasons, we used to put MIPS CPU IRQs behind SoC-specific IRQs in the queue, and have been using CPU_IRQ_BASE as MIPS_CPU_IRQ_BASE. In recent years, however, we've brought it back to normal order, and now CPU_IRQ_BASE just redefines the generic MIPS_CPU_IRQ_BASE. At the same time, NUM_CPU_IRQ is also removed as useless. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1387/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Define ARCH_HAS_USABLE_BUILTIN_POPCOUNT for OCTEON.David Daney2010-08-051-0/+8
| | | | | | | | | | OCTEON implements __builtin_popcount with a single instruction, so lets use it. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/1431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Create and use asm/arch_hweight.hDavid Daney2010-08-052-1/+42
| | | | | | | | | | | | | | Some MIPS ISA processor varients can do hweight operations efficiently. Split arch_hweight.h into a seperate file, and implement the operations with __builtin_popcount{,ll} if supported. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/1430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Update comment for cpu_has_clo_clzRalf Baechle2010-08-051-1/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MSP71xx: Remove dead CONFIG_MTD_PMC_MSP_RAMROOTChristoph Egger2010-08-051-4/+0
| | | | | | | | | | | | | | CONFIG_MTD_PMC_MSP_RAMROOT doesn't exist in Kconfig, therefore removing all references for it from the source code. Signed-off-by: Christoph Egger <siccegge@cs.fau.de> To: Ralf Baechle <ralf@linux-mips.org>, Yoichi Yuasa <yuasa@linux-mips.org>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Cc: vamos@i4.informatik.uni-erlangen.de Acked-by: Shane McDonald <mcdonald.shane@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/1375/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove dead CONFIG_MTD_PB1550_BOOT, CONFIG_MTD_PB1550_USERChristoph Egger2010-08-051-8/+0
| | | | | | | | | | | | | | CONFIG_MTD_PB1550_BOOT, CONFIG_MTD_PB1550_USER doesn't exist in Kconfig, therefore removing all references for it from the source code. Signed-off-by: Christoph Egger <siccegge@cs.fau.de> To: Manuel Lauss <manuel.lauss@gmail.com>, To: linux-mips@linux-mips.org To: linux-kernel@vger.kernel.org Cc: vamos@i4.informatik.uni-erlangen.de Patchwork: https://patchwork.linux-mips.org/patch/1370/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Provide more elevant interface cu2_notifier for CP2 extensions.Ralf Baechle2010-08-051-0/+12
| | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/1504/
* MIPS: PowerTV: Correct ASIC device register names and locationsDavid VomLehn2010-08-051-1/+1
| | | | | | | | | Correct ASIC device register names and addresses for USB devices. Signed-off-by: David VomLehn <dvomlehn@cisco.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1258/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PowerTV: Use O(1) algorthm for phys_to_dma/dma_to_physDavid VomLehn2010-08-052-48/+125
| | | | | | | | | | | | | | | | | | | | | | | | Replace phys_to_dma()/dma_to_phys() looping algorithm with an O(1) algorithm The approach taken is inspired by the sparse memory implementation: take a certain number of high-order bits off the address them, use this as an index into a table containing an offset to the desired address and add it to the original value. There is a table for mapping physical addresses to DMA addresses and another one for the reverse mapping. The table sizes depend on how fine-grained the mappings need to be; Coarser granularity less to smaller tables. On a processor with 32-bit physical and DMA addresses, with 4 MIB granularity, memory usage is two 2048-byte arrays. Each 32-byte cache line thus covers 64 MiB of address space. Also, renames phys_to_bus() to phys_to_dma() and bus_to_phys() to dma_to_phys() to align with kernel usage. [Ralf: Fixed silly build breakage due to stackoverflow warning caused by huge array on stack.] Signed-off-by: David VomLehn <dvomlehn@cisco.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1257/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP27: Don't include <linux/topology.h> into <asm/sn/agent.h>.Ralf Baechle2010-08-051-1/+0
| | | | | | | The include is unecessary and will when building the IP35 result in recursive header inclusion spaghetti. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TX49xx: Define ARCH_KMALLOC_MINALIGNAtsushi Nemoto2010-08-051-3/+1
| | | | | | | | | | | With SLAB, it works without ARCH_KMALLOC_MINALIGN, but with SLOB/SLUB, ARCH_KMALLOC_MINALIGN is required to ensure alignment of kmalloced buffer. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1248/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Quit using undefined behavior of ADDU in 64-bit atomic operations.David Daney2010-07-261-12/+12
| | | | | | | | | For 64-bit, we must use DADDU and DSUBU. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: N32: Define getdents64.Ralf Baechle2010-07-261-2/+3
| | | | | | | | As a relativly new ABI N32 should only have received the getdents64(2) but instead it only had getdents(2). This was noticed as a performance anomaly in glibc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47xx: Add NVRAM support devicesWaldemar Brodkorb2010-07-051-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to netboot a Linksys WRT54GS WLAN router, the bootup fails, because of following error message: ... [ 0.424000] b44: b44.c:v2.0 [ 0.424000] b44: Invalid MAC address found in EEPROM [ 0.432000] b44 ssb0:1: Problem fetching invariants of chip,aborting [ 0.436000] b44: probe of ssb0:1 failed with error -22 ... The router uses a CFE bootloader, but most of the needed environment variables for network card initialization, are not available from CFE via printenv and even though not via cfe_getenv(). The required environment variables are saved in a special partition in flash memory. The attached patch implement nvram_getenv and enables bootup via NFS root on my router. Most of the patch is extracted from the OpenWrt subversion repository and stripped down and cleaned up to just fix this issue. [Ralf: sorted out header file inclusions. Lots of unneded headers and such that should have been included.] Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> Reviewed-by: Phil Sutter <phil@nwl.cc> To: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/1359/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: sleepcode without compile-time cputype dependenciesManuel Lauss2010-07-051-1/+2
| | | | | | | | | | Split the low-level sleepcode into per-cpu functions instead of relying on compile-time-defined cpu type. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1281/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7, BCM63xx: fix gpio_to_irq() return valueYoichi Yuasa2010-07-052-2/+2
| | | | | | | | | The return value of gpio_to_irq() is not a pointer but an integer. Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1280/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Fix typo in ar7.hFlorian Fainelli2010-07-051-3/+3
| | | | | | | | | This fixes a typo on the AR7_RESET_PERIPHERAL define. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: use use asm-generic/scatterlist.hFUJITA Tomonori2010-05-271-21/+1
| | | | | | | Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2010-05-216-17/+74
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (25 commits) MIPS: Use GCC __builtin_prefetch() to implement prefetch(). MIPS: Octeon: Serial port fixes for OCTEON simulator. MIPS: Octeon: Get rid of early serial. MIPS: AR7: prevent race between clock initialization and devices registration MIPS: AR7: use ar7_has_high_vlynq() to determine watchdog base address MIPS: BCM63xx: Avoid namespace clash on GPIO_DIR_{IN,OUT} MIPS: MTX-1: Update defconfig MIPS: BCM47xx: Update defconfig MIPS: RB532: Update defconfig MIPS: AR7: Update defconfig RTC: rtc-cmos: Fix binary mode support MIPS: Oprofile: Loongson: Cleanup the comments MIPS: Oprofile: Loongson: Cleanup of the macros MIPS: Oprofile: Loongson: Remove unused variable from loongson2_cpu_setup() MIPS: Oprofile: Loongson: Remove useless parentheses MIPS: Oprofile: Loongson: Unify macro for setting events MIPS: nofpu and nodsp only affect CPU0 MIPS: Clean up tables for bootmem allocation MIPS: Coding style cleanups of access of FCSR rounding mode bits MIPS: Loongson 2F: Add gpio/gpioilb support ...
| * MIPS: Use GCC __builtin_prefetch() to implement prefetch().David Daney2010-05-211-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC's __builtin_prefetch() was introduced a long time ago, all supported GCC versions have it. Lets do what the big boys up in linux/prefetch.h do, except we use '1' as the third parameter to provoke 'PREF 0,...' and 'PREF 1,...' instead of other prefetch hints. This allows for better code generation. In theory the existing embedded asm could be optimized, but the compiler has these builtins, so there is really no point. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1235/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: BCM63xx: Avoid namespace clash on GPIO_DIR_{IN,OUT}Florian Fainelli2010-05-211-2/+2
| | | | | | | | | | | | | | | | | | | | This is too generic a name, so prefix it with BCM63XX_ to avoid potential namespace clashes when including <asm/gpio.h>. Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1171/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Loongson 2F: Add gpio/gpioilb supportArnaud Patard2010-05-211-0/+35
| | | | | | | | | | | | | | Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1163/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: add sysdev for DBDMA PM.Manuel Lauss2010-05-211-4/+0
| | | | | | | | | | | | | | | | | | Add a sysdev for DBDMA PM. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1119/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: add sysdev for IRQ PM.Manuel Lauss2010-05-211-2/+32
| | | | | | | | | | | | | | | | | | Use a sysdev to implement PM methods for the Au1000 interrupt controllers. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1114/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Loongson: update cpu-feature-overrides.hWu Zhangjin2010-05-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | mips,kgdb: kdb low level trap catch and stack traceJason Wessel2010-05-201-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | The only way the debugger can handle a trap in inside rcu_lock, notify_die, or atomic_notifier_call_chain without a recursive fault is to have a low level "first opportunity handler" do_trap_or_bp() handler. Generally this will be something the vast majority of folks will not need, but for those who need it, it is added as a kernel .config option called KGDB_LOW_LEVEL_TRAP. Also added was a die notification for oops such that kdb can catch an oops for analysis. There appeared to be no obvious way to pass the struct pt_regs from the original exception back to the stack back tracer, so a special case was added to show_stack() for when kdb is active because you generally desire to generally look at the back trace of the original exception. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'for-linus' of ↵Linus Torvalds2010-05-201-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (44 commits) vlynq: make whole Kconfig-menu dependant on architecture add descriptive comment for TIF_MEMDIE task flag declaration. EEPROM: max6875: Header file cleanup EEPROM: 93cx6: Header file cleanup EEPROM: Header file cleanup agp: use NULL instead of 0 when pointer is needed rtc-v3020: make bitfield unsigned PCI: make bitfield unsigned jbd2: use NULL instead of 0 when pointer is needed cciss: fix shadows sparse warning doc: inode uses a mutex instead of a semaphore. uml: i386: Avoid redefinition of NR_syscalls fix "seperate" typos in comments cocbalt_lcdfb: correct sections doc: Change urls for sparse Powerpc: wii: Fix typo in comment i2o: cleanup some exit paths Documentation/: it's -> its where appropriate UML: Fix compiler warning due to missing task_struct declaration UML: add kernel.h include to signal.c ...
| * add descriptive comment for TIF_MEMDIE task flag declaration.Andreas Dilger2010-05-141-1/+1
| | | | | | | | | | | | Signed-off-by: Andreas Dilger <adilger@dilger.ca> Acked-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | Merge branch 'core-locking-for-linus' of ↵Linus Torvalds2010-05-181-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: lockdep: Reduce stack_trace usage lockdep: No need to disable preemption in debug atomic ops lockdep: Actually _dec_ in debug_atomic_dec lockdep: Provide off case for redundant_hardirqs_on increment lockdep: Simplify debug atomic ops lockdep: Fix redundant_hardirqs_on incremented with irqs enabled lockstat: Make lockstat counting per cpu i8253: Convert i8253_lock to raw_spinlock
| * \ Merge commit 'v2.6.34-rc6' into core/lockingIngo Molnar2010-05-0320-59/+119
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