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* MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit supportMark Salter2010-10-271-0/+10
| | | | | | | | Use an ELF HWCAP flag to indicate to the process that the CPU provides LL/SC equivalent atomic operations unit support in addition to BSET/BCLR. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Map userspace atomic op regs as a vmalloc pageMark Salter2010-10-272-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM34 processor has an atomic operation that's the equivalent of LL/SC on other architectures. However, rather than being done through a pair of instructions, it's driven by writing to a pair of memory-mapped CPU control registers. One set of these registers (AARU/ADRU/ASRU) is available for use by userspace, but for userspace to access them a PTE must be set up to cover the region. This is done by dedicating the first vmalloc region page to this purpose, setting the permissions on its PTE such that userspace can access the page. glibc is hardcoded to expect the registers to be there. The way atomic ops are done through these registers is straightforward: (1) Write the address of the word you wish to access into AARU. This causes the CPU to go and fetch that word and load it into ADRU. The status bits are also cleared in ASRU. (2) The current data value is read from the ADRU register and modified. (3) To alter the data in RAM, the revised data is written back to the ADRU register, which causes the CPU to attempt to write it back. (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch), ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then must be checked to confirm that the operation wasn't aborted. If any of the watches have been set to true, the operation was aborted. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: And Panasonic AM34 subarch and implement SMPAkira Takeuchi2010-10-2779-481/+4494
| | | | | | | | | | Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Delete idle_timestamp from irq_cpustat_tAkira Takeuchi2010-10-272-3/+0
| | | | | | | | Delete idle_timestamp from irq_cpustat_t as it's an unread relic. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make various interrupt priority settings configurableAkira Takeuchi2010-10-272-6/+76
| | | | | | | | | Make the settings of interrupt priorities used by various services configurable at run time. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Optimise do_csum()Akira Takeuchi2010-10-271-27/+22
| | | | | | | | | Optimise do_csum() to gang up the loads so they're less likely to get interruptions between. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Implement atomic ops using atomic ops unitMark Salter2010-10-272-47/+351
| | | | | | | | Implement atomic ops using the atomic ops unit available in the AM34 CPU. This allows the equivalent of the LL/SC instructions to be found on other CPUs. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make the FPU operate in non-lazy mode under SMPAkira Takeuchi2010-10-2714-248/+440
| | | | | | | | | | Make the FPU operate in non-lazy mode under SMP so that when the process that is currently using the FPU migrates to a different CPU, we don't have to ping its previous CPU to flush the FPU context. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: SMP TLB flushingAkira Takeuchi2010-10-274-29/+290
| | | | | | | | | Implement global TLB flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB controlAkira Takeuchi2010-10-273-47/+65
| | | | | | | | | Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make the use of PIDR to mark TLB entries controllableAkira Takeuchi2010-10-274-62/+84
| | | | | | | | | Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Rename __flush_tlb*() to local_flush_tlb*()David Howells2010-10-276-28/+42
| | | | | | | | | | Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready to differentiate local from global TLB flushes when SMP is introduced. Whilst we're at it, get rid of __flush_tlb_global() and make local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: AM34 erratum requires MMUCTR read and write on exception entryAkira Takeuchi2010-10-273-6/+37
| | | | | | | | | An AM34 erratum requires MMUCTR read and write on entry to certain exceptions, prior to EPSW.NMID being cleared to allow NMIs to happen. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Make the boot wrapper able to use writeback cachingAkira Takeuchi2010-10-271-1/+48
| | | | | | | | | Make the boot wrapper able to use writeback caching, including flushing the cache before jumping to the main kernel. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Cache: Implement SMP global cache flushingAkira Takeuchi2010-10-279-15/+535
| | | | | | | | | Implement SMP global cache flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Allow some cacheflushes to be avoided if cache snooping is availableDavid Howells2010-10-279-96/+309
| | | | | | | The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: AM34: Add cacheflushing by using the AM34 purge registersAkira Takeuchi2010-10-274-1/+678
| | | | | | | | | | The AM34 CPU core provides an automated way of purging the cache rather than manually iterating over all the tags in the cache. Make it possible to use these. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: SMP: Differentiate local cache flushingAkira Takeuchi2010-10-274-112/+289
| | | | | | | | | | | | | | | | | | | Differentiate local cache flushing from global cache flushing so that they can be done differently on SMP systems. Rename the cache functions from: mn10300_[id]cache_*() to: mn10300_[id]_localcache_*() and on a UP system, assign the global labels to the local labels. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Cacheflush functions should take unsigned long addressesAkira Takeuchi2010-10-272-15/+15
| | | | | | | | | The functions that perform cache flushing should take addresses of unsigned long type, not unsigned int. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: AM34: The current cacheflush routines operate by controlling tag regsDavid Howells2010-10-274-2/+23
| | | | | | | | | | The current cache flush and invalidate routines operate by controlling the cache tag registers. Rename the files and add config items to select them. This makes it easier to support the use of other cache flush methods instead, such as the use of AM34's area purge registers, if available. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Reorder asm/cacheflush.h to put primitives firstDavid Howells2010-10-271-44/+44
| | | | | | | | Reorder asm/cacheflush.h to put arch primitives first, before the main functions so that the main functions can be inline asm rather than #defines when non-trivial. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Provide a MN10300_CACHE_ENABLED config optionDavid Howells2010-10-276-10/+13
| | | | | | | Provide a MN10300_CACHE_ENABLED config option as inverted logic of MN10300_CACHE_DISABLED to make things simpler. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Cache: Split cache bits out of arch KconfigDavid Howells2010-10-272-28/+33
| | | | | | Split the cache bits out of arch/mn10300/Kconfig as they're quite complex. Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Remove monitor/JTAG functionsAkira Takeuchi2010-10-274-55/+2
| | | | | | | | | Remove the monitor trap function and the set_jtag_stub function as they're not really necessary. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Add CPU register bits for AM34Akira Takeuchi2010-10-272-5/+74
| | | | | | | | Add CPU register declarations for the AM34 subarch. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Don't hard code the cacheline size in register defsAkira Takeuchi2010-10-271-5/+9
| | | | | | | | Don't hard code the cacheline size in the cache control register definitions. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Move DMA engine control reg defs to MN103E010 processor directoryAkira Takeuchi2010-10-272-86/+103
| | | | | | | | | Move the DMA engine control register definitions to the MN103E010 processor directory so that the MN2WS0050 processor can have its own. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Differentiate AM33_2 and AM33_3 in configAkira Takeuchi2010-10-271-2/+9
| | | | | | | | | | | Differentiate AM33_2 and AM33_3 CPU cores in configuration. The MN103E010 processor contains an AM33_2 core. Whilst we're at it, prepare for AM34-based stuff by declaring AM34_2 too. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Provide the functions to fully disable maskable interruptsAkira Takeuchi2010-10-271-0/+77
| | | | | | | | | | | | | | The local_irq_disable() function and co. merely raise the interrupt mask on the MN10300 arch to exclude normal interrupts. This still lets other, higher priority maskable interrupts through, such as are used to service gdbstub's serial port and the MN10300 on-chip serial port virtual FIFOs. Provide functions to allow the maskable interrupts to be fully disabled, which will exclude those interrupts. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Add reads[bwl]() and writes[bwl]()Akira Takeuchi2010-10-271-0/+13
| | | | | | | | Add reads[bwl]() and writes[bwl]() for MN10300. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Don't cast away the volatile in test_bit()Akira Takeuchi2010-10-271-1/+1
| | | | | | | | | Don't cast away the volatile in test_bit()'s parameter when we change its type from const volatile void * so that we can dereference it. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: Prevent cnt32_to_63() from being preempted in sched_clock()David Howells2010-10-271-0/+5
| | | | | | | | | | | | | | | Prevent cnt32_to_63() from being preempted in sched_clock() because it may read its internal counter, get preempted, get delayed for more than the half period of the 'TSC' and then write the internal counter, thus corrupting it. Whilst some callers of sched_clock() have interrupts disabled or hold spinlocks, not all do, and so preemption must be held here. Note that sched_clock() is called from lockdep, but that shouldn't be a problem because although preempt_disable() calls into lockdep, lockdep has a recursion counter to deal with this. Signed-off-by: David Howells <dhowells@redhat.com>
* mn10300: Use pci_claim_resourceDavid Howells2010-10-271-10/+6
| | | | | | | | Instead of open-coding pci_find_parent_resource and request_resource, just call pci_claim_resource. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: David Howells <dhowells@redhat.com>
* bitops: Change the bitmap index from int to unsigned long [mn10300]Justin Chen2010-10-272-8/+8
| | | | | | | | Change the index to unsigned long in all bitops for [mn10300] Signed-off-by: Justin Chen <justin.chen@hp.com> Reviewed-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: David Howells <dhowells@redhat.com>
* MN10300: BUG to BUG_ON changesStoyan Gaydarov2010-10-275-10/+5
| | | | | Signed-off-by: Stoyan Gaydarov <stoyboyker@gmail.com> Signed-off-by: David Howells <dhowells@redhat.com>
*-. Merge branches 'upstream/xenfs' and 'upstream/core' of ↵Linus Torvalds2010-10-268-97/+576
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen * 'upstream/xenfs' of git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen: xen/privcmd: make privcmd visible in domU xen/privcmd: move remap_domain_mfn_range() to core xen code and export. privcmd: MMAPBATCH: Fix error handling/reporting xenbus: export xen_store_interface for xenfs xen/privcmd: make sure vma is ours before doing anything to it xen/privcmd: print SIGBUS faults xen/xenfs: set_page_dirty is supposed to return true if it dirties xen/privcmd: create address space to allow writable mmaps xen: add privcmd driver xen: add variable hypercall caller xen: add xen_set_domain_pte() xen: add /proc/xen/xsd_{kva,port} to xenfs * 'upstream/core' of git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen: (29 commits) xen: include xen/xen.h for definition of xen_initial_domain() xen: use host E820 map for dom0 xen: correctly rebuild mfn list list after migration. xen: improvements to VIRQ_DEBUG output xen: set up IRQ before binding virq to evtchn xen: ensure that all event channels start off bound to VCPU 0 xen/hvc: only notify if we actually sent something xen: don't add extra_pages for RAM after mem_end xen: add support for PAT xen: make sure xen_max_p2m_pfn is up to date xen: limit extra memory to a certain ratio of base xen: add extra pages for E820 RAM regions, even if beyond mem_end xen: make sure xen_extra_mem_start is beyond all non-RAM e820 xen: implement "extra" memory to reserve space for pages not present at boot xen: Use host-provided E820 map xen: don't map missing memory xen: defer building p2m mfn structures until kernel is mapped xen: add return value to set_phys_to_machine() xen: convert p2m to a 3 level tree xen: make install_p2mtop_page() static ... Fix up trivial conflict in arch/x86/xen/mmu.c, and fix the use of 'reserve_early()' - in the new memblock world order it is now 'memblock_x86_reserve_range()' instead. Pointed out by Jeremy.
| | * xen: include xen/xen.h for definition of xen_initial_domain()Ian Campbell2010-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | CC arch/x86/xen/setup.o arch/x86/xen/setup.c: In function 'xen_memory_setup': arch/x86/xen/setup.c:161: error: implicit declaration of function 'xen_initial_domain' Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: use host E820 map for dom0Ian Campbell2010-10-221-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running as initial domain, get the real physical memory map from xen using the XENMEM_machine_memory_map hypercall and use it to setup the e820 regions. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| | * xen: correctly rebuild mfn list list after migration.Ian Campbell2010-10-221-13/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise the second migration attempt fails because the mfn_list_list still refers to all the old mfns. We need to update the entires in both p2m_top_mfn and the mid_mfn pages which p2m_top_mfn refers to. In order to do this we need to keep track of the virtual addresses mapping the p2m_mid_mfn pages since we cannot rely on mfn_to_virt(p2m_top_mfn[idx]) since p2m_top_mfn[idx] will still contain the old MFN after a migration, which may now belong to another domain and hence have a different mapping in the m2p. Therefore add and maintain a third top level page, p2m_top_mfn_p[], which tracks the virtual addresses of the mfns contained in p2m_top_mfn[]. We also need to update the content of the p2m_mid_missing_mfn page on resume to refer to the page's new mfn. p2m_missing does not need updating since the migration process takes care of the leaf p2m pages for us. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: don't add extra_pages for RAM after mem_endJeremy Fitzhardinge2010-10-221-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an E820 region is entirely beyond mem_end, don't attempt to truncate it and add the truncated pages to extra_pages, as they will be negative. Also, make sure the extra memory region starts after all BIOS provided E820 regions (and in the case of RAM regions, post-clipping). Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: add support for PATJeremy Fitzhardinge2010-10-223-3/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert Linux PAT entries into Xen ones when constructing ptes. Linux doesn't use _PAGE_PAT for ptes, so the only difference in the first 4 entries is that Linux uses _PAGE_PWT for WC, whereas Xen (and default) use it for WT. xen_pte_val does the inverse conversion. We hard-code assumptions about Linux's current PAT layout, but a warning on the wrmsr to MSR_IA32_CR_PAT should point out any problems. If necessary we could go to a more general table-based conversion between Linux and Xen PAT entries. hugetlbfs poses a problem at the moment, the x86 architecture uses the same flag for _PAGE_PAT and _PAGE_PSE, which changes meaning depending on which pagetable level we're using. At the moment this should be OK so long as nobody tries to do a pte_val on a hugetlbfs pte. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: make sure xen_max_p2m_pfn is up to dateJeremy Fitzhardinge2010-10-223-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keep xen_max_p2m_pfn up to date with the end of the extra memory we're adding. It is possible that it will be too high since memory may be truncated by a "mem=" option on the kernel command line, but that won't matter. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: limit extra memory to a certain ratio of baseJeremy Fitzhardinge2010-10-221-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If extra memory is very much larger than the base memory size then all of the base memory can be filled with structures reserved to describe the extra memory, leaving no space for anything else. Even at the maximum ratio there will be little space for anything else, but this change is intended to at least allow the system to boot rather than crash mysteriously. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: add extra pages for E820 RAM regions, even if beyond mem_endJeremy Fitzhardinge2010-10-221-3/+4
| | | | | | | | | | | | | | | | | | | | | If an entire E820 RAM region is beyond mem_end, still add its pages to the extra area so that space can be used by the kernel. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: make sure xen_extra_mem_start is beyond all non-RAM e820Jeremy Fitzhardinge2010-10-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | If Xen gives us non-RAM E820 entries (dom0 only, typically), then make sure the extra RAM region is beyond them. It's OK for the extra space to grow into E820 regions, however. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: implement "extra" memory to reserve space for pages not present at bootJeremy Fitzhardinge2010-10-221-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using the e820 map to get the initial pseudo-physical address space, look for either Xen-provided memory which doesn't lie within an E820 region, or an E820 RAM region which extends beyond the Xen-provided memory range. Count these pages, and add them to a new "extra memory" range. This range has an E820 RAM range to describe it - so the kernel will allocate page structures for it - but it is also marked reserved so that the kernel will not attempt to use it. The balloon driver can then add this range as a set of currently ballooned-out pages, which can be used to extend the domain beyond its original size. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: Use host-provided E820 mapIan Campbell2010-10-221-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than simply using a flat memory map from Xen, use its provided E820 map. This allows the domain builder to tell the domain to reserve space for more pages than those initially provided at domain-build time. It also allows the host to specify holes in the address space (for PCI-passthrough, for example). Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: don't map missing memoryJeremy Fitzhardinge2010-10-222-2/+22
| | | | | | | | | | | | | | | | | | | | | When setting up a pte for a missing pfn (no matching mfn), just create an empty pte rather than a junk mapping. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: defer building p2m mfn structures until kernel is mappedJeremy Fitzhardinge2010-10-222-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building mfn parts of p2m structure, we rely on being able to use mfn_to_virt, which in turn requires kernel to be mapped into the linear area (which is distinct from the kernel image mapping on 64-bit). Defer calling xen_build_mfn_list_list() until after xen_setup_kernel_pagetable(); Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
| | * xen: add return value to set_phys_to_machine()Jeremy Fitzhardinge2010-10-222-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_phys_to_machine() can return false on failure, which means a memory allocation failure for the p2m structure. It can only fail if setting the mfn for a pfn in previously unused address space. It is guaranteed to succeed if you're setting a mapping to INVALID_P2M_ENTRY or updating the mfn for an existing pfn. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
generated by cgit v1.1 at 2025-01-18 00:43:40 +0000