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* drm/i915: Correct locking in the modesetting failure path, fixing a BUG_ON.Eric Anholt2010-02-261-0/+2
| | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Disable the surface tile swizzling on Sandybridge.Eric Anholt2010-02-261-1/+1
| | | | | | I can't explain this, except that it makes my display correct. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix sandybridge status page setup.Eric Anholt2010-02-263-2/+15
| | | | | | The register's moved to the same location as the one for the BCS, it seems. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Set up fence registers on sandybridge.Eric Anholt2010-02-262-3/+33
| | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.Eric Anholt2010-02-2611-56/+87
| | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge remote branch 'anholt/drm-intel-next' into drm-next-stageDave Airlie2010-02-2513-307/+1057
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * anholt/drm-intel-next: drm/i915: Record batch buffer following GPU error drm/i915: give up on 8xx lid status drm/i915: reduce some of the duplication of tiling checking drm/i915: blow away userspace mappings before fence change drm/i915: move a gtt flush to the correct place agp/intel: official names for Pineview and Ironlake drm/i915: overlay: drop superflous gpu flushes drm/i915: overlay: nuke readback to flush wc caches drm/i915: provide self-refresh status in debugfs drm/i915: provide FBC status in debugfs drm/i915: fix drps disable so unload & re-load works drm/i915: Fix OGLC performance regression on 945 drm/i915: Deobfuscate the render p-state obfuscation drm/i915: add dynamic performance control support for Ironlake drm/i915: enable memory self refresh on 9xx drm/i915: Don't reserve compatibility fence regs in KMS mode. drm/i915: Keep MCHBAR always enabled drm/i915: Replace open-coded eviction in i915_gem_idle()
| * drm/i915: Record batch buffer following GPU errorChris Wilson2010-02-225-7/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to improve our diagnostic capabilities following a GPU hang and subsequent reset, we need to record the batch buffer that triggered the error. We assume that the current batch buffer, plus a few details about what else is on the active list, will be sufficient -- at the very least an improvement over nothing. The extra information is stored in /debug/dri/.../i915_error_state following an error, and may be decoded using intel_gpu_tools/tools/intel_error_decode. v2: Avoid excessive work under spinlocks. v3: Include ringbuffer for later analysis. v4: Use kunmap correctly and record more buffer state. v5: Search ringbuffer for current batch buffer v6: Use a work fn for the impossible IRQ error case. v7: Avoid non-atomic paths whilst in IRQ context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: give up on 8xx lid statusJesse Barnes2010-02-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | These old machines more often than not lie about their lid state. So don't use it to detect LVDS presence, but leave the event handler to deal with lid open/close, when we might need to reset the mode. Fixes kernel bug #15248 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: reduce some of the duplication of tiling checkingOwain Ainsworth2010-02-223-36/+5
| | | | | | | | | | | | | | | | | | | | i915_gem_object_fenceable was mostly just a repeat of the i915_gem_object_fence_offset_ok, but also checking the size (which was checkecd when we allowed that BO to be tiled in the first place). So instead, export the latter function and use it in place. Signed-Off-By: Owain G. Ainsworth <oga@openbsd.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: blow away userspace mappings before fence changeDaniel Vetter2010-02-222-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | This aligns it with the other user of i915_gem_clear_fence_reg, which blows away the mapping before changing the fence reg. Only affects userspace if it races against itself when changing tiling parameters, i.e. behaviour is undefined, anyway. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: move a gtt flush to the correct placeDaniel Vetter2010-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | No functional change, because gtt flushing is a no-op. Still, try to keep the bookkeeping accurate. The if is still slightly wrong for with execbuf2 even i915-class hw doesn't always need a fence reg for gpu access. But that's for somewhen lateron. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: overlay: drop superflous gpu flushesDaniel Vetter2010-02-221-15/+5
| | | | | | | | | | | | | | | | | | Cache-coherency is maintained by gem. Drop these leftover MI_FLUSH commands from the userspace code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: overlay: nuke readback to flush wc cachesDaniel Vetter2010-02-221-5/+0
| | | | | | | | | | | | | | | | | | | | I retested this and whatever this papered over, the problem doesn't seem to exist anymore. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Eric Anholt <eric@anholt.net> [anholt: fixed up compile warning] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: provide self-refresh status in debugfsJesse Barnes2010-02-221-0/+21
| | | | | | | | | | Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: provide FBC status in debugfsJesse Barnes2010-02-224-0/+66
| | | | | | | | | | | | | | | | | | Tools like powertop want to check the current FBC status and report it to the user. So add a debugfs file indicating whether FBC is enabled, and if not, why. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: fix drps disable so unload & re-load worksJesse Barnes2010-02-221-1/+1
| | | | | | | | | | | | | | | | | | At unload time, we need to disable DRPS, but we need to do it correctly or the GPU will hang and we won't be able to load the module again. So set the SFCAVM bit so we can properly restore the DRPS config at unload. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix OGLC performance regression on 945Li Peng2010-02-221-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | He Shuang reported an OGLC performance regression introduced in the patch "enable memory self refresh on 9xx", In that patch, SR on 945 is disabled everytime when calling intel_mark_busy(), while too much of such operation will impact performance. Actually disable SR is necessary only when GPU and Crtc changing from idle to busy. This patch make such optimization. It fixes upstream bug http://bugs.freedesktop.org/show_bug.cgi?id=26422 Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Deobfuscate the render p-state obfuscationMatthew Garrett2010-02-225-13/+15
| | | | | | | | | | | | | | | | The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: add dynamic performance control support for IronlakeJesse Barnes2010-02-228-10/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: ykzhao <yakui.zhao@intel.com> [anholt: Resolved against the irq handler loop removal] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: enable memory self refresh on 9xxLi Peng2010-02-222-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling memory self refresh (SR) on 9xx needs to set additional register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the write to self refresh bit and bit 16 to enable the write of self refresh watermark. On 915, bit 12 of INSTPM is used to enable SR. SR will take effect when CPU enters C3+ state and its entry/exit should be automatically controlled by H/W, driver only needs to set SR enable bits in wm update. But this isn't safe in my test on 945 because GPU is hung. So this patch explicitly enables SR when GPU is idle, and disables SR when it is busy. In my test on a netbook of 945GSE chipset, it saves about 0.8W idle power. Signed-off-by: Li Peng <peng.li@intel.com> [anholt: rebased against 33c5fd121eabbccc9103daf6cda36941eb3c349f by adding disable of INSTPM SR bit on 915GM for two pipe setup] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Don't reserve compatibility fence regs in KMS mode.Eric Anholt2010-02-161-1/+2
| | | | | | | | | | | | | | | | The fence start is for compatibility with UMS X Servers before fence management. KMS X Servers only started doing tiling after fence management appeared. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Keep MCHBAR always enabledZhenyu Wang2010-02-163-122/+122
| | | | | | | | | | | | | | | | | | As we need more and more controls within MCHBAR for memory config and power management, this trys to keep MCHBAR enabled from driver load and only tear down in driver unload. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Replace open-coded eviction in i915_gem_idle()Chris Wilson2010-02-161-100/+44
| | | | | | | | | | | | | | | | | | | | | | With the introduction of the hang-check, we can safely expect that i915_wait_request() will always return even when the GPU hangs, and so do not need to open code the wait in order to manually check for the hang. Also we do not need to always evict all buffers, so only flush the GPU (and wait for it to idle) for KMS, but continue to evict for UMS. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* | Merge remote branch 'korg/drm-core-next' into drm-next-stageDave Airlie2010-02-254-23/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * korg/drm-core-next: drm/ttm: handle OOM in ttm_tt_swapout drm/radeon/kms/atom: fix shr/shl ops drm/kms: fix spelling of "CLOCK" drm/kms: fix fb_changed = true else statement drivers/gpu/drm/drm_fb_helper.c: don't use private implementation of atoi() drm: switch all GEM/KMS ioctls to unlocked ioctl status. Use drm_gem_object_[handle_]unreference_unlocked where possible drm: introduce drm_gem_object_[handle_]unreference_unlocked
| * | Use drm_gem_object_[handle_]unreference_unlocked where possibleLuca Barbieri2010-02-114-23/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly obvious simplifications. The i915 pread/pwrite ioctls, intel_overlay_put_image and nouveau_gem_new were incorrectly using the locked versions without locking: this is also fixed in this patch. Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | | i915 / PM: Fix hibernate regression caused by suspend/resume splittingRafael J. Wysocki2010-02-221-21/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 84b79f8d2882b0a84330c04839ed4d3cefd2ff77 (drm/i915: Fix crash while aborting hibernation) attempted to fix a regression introduced by commit cbda12d77ea590082edb6d30bd342a67ebc459e0 (drm/i915: implement new pm ops for i915), but it went too far trying to split the freeze/suspend and resume/thaw parts of the code. As a result, it introduced another regression, which only is visible on some systems. Fix the problem by merging i915_drm_suspend() with i915_drm_freeze() and moving some code from i915_resume() into i915_drm_thaw(), so that intel_opregion_free() and intel_opregion_init() are also executed in the freeze and thaw code paths, respectively. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Reported-and-tested-by: Pedro Ribeiro <pedrib@gmail.com> Tested-by: Tino Keitel <tino.keitel@tikei.de> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | ACPI, i915: blacklist Clevo M5x0N bad_lid stateZhang Rui2010-02-161-0/+7
| |/ |/| | | | | | | | | | | | | Wrong Lid state reported. Need to blacklist this machine for LVDS detection. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* | drm/i915: hold ref on flip object until it completesJesse Barnes2010-02-101-1/+3
| | | | | | | | | | | | | | | | | | | | This will prevent things from falling over if the user frees the flip buffer before we complete the flip, since we'll hold an internal reference. Reported-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Fix crash while aborting hibernationRafael J. Wysocki2010-02-101-67/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cbda12d77ea590082edb6d30bd342a67ebc459e0 (drm/i915: implement new pm ops for i915) introduced the problem that if s2disk hibernation is aborted, the system will crash, because i915_pm_freeze() does nothing, while it should at least reverse some operations carried out by i915_suspend(). Fix this issue by splitting the i915 suspend into a freeze part a suspend part, where the latter is not executed before creating a hibernation image, and the i915 resume into a "low-level" resume part and a thaw part, where the former is not executed after the image has been created. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Tested-by: Alan Jenkins <alan-jenkins@tuffmail.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Correctly return -ENOMEM on allocation failure in cmdbuf ioctls.Owain Ainsworth2010-02-102-2/+6
| | | | | | | | | | Signed-off-by: Owain G. Ainsworth <oga@openbsd.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: fix pipe source image setting in flip commandZhenyu Wang2010-02-101-2/+4
| | | | | | | | | | | | | | | | | | The MI_DISPLAY_FLIP command needs to be set the same pipe source image like in pipe source register, e.g source image size minus one. This fixes screen corrupt issue on Ironlake. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: fix flip done interrupt on IronlakeZhenyu Wang2010-02-101-8/+8
| | | | | | | | | | | | | | | | | | On Ironlake plane flip interrupt means flip done event already, the behavior is not like old chips, and perform like other usual interrupt. So only need to handle flip done event when receiving that interrupt. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: untangle page flip completionJesse Barnes2010-02-101-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a new page flip is requested, we need to both queue an unpin for the current framebuffer, and also increment the flip pending count on the newly submitted buffer. At flip finish time, we need to unpin the old fb and decrement the flip pending count on the new buffer. The old code was conflating the two, and led to hangs when new direct rendered apps were started, replacing the existing frame buffer. This patch splits out the buffers and prevents the hangs. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: handle FBC and self-refresh betterJesse Barnes2010-02-102-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | On 945, we need to avoid entering self-refresh if the compressor is busy, or we may cause display FIFO underruns leading to ugly flicker. Fixes fdo bug #24314, kernel bug #15043. Tested-by: Alexander Lam <lambchop468@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Julien Cristau <jcristau@debian.org> (fd.o #25371) Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Increase fb alignment to 64kChris Wilson2010-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An untiled framebuffer must be aligned to 64k. This is normally handled by intel_pin_and_fence_fb_obj(), but the intelfb_create() likes to be different and do the pinning itself. However, it aligns the buffer object incorrectly for pre-i965 chipsets causing a PGTBL_ERR when it is installed onto the output. Fixes: KMS error message while initializing modesetting - render error detected: EIR: 0x10 [i915] http://bugs.freedesktop.org/show_bug.cgi?id=22936 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Update write_domains on active list after flush.Daniel Vetter2010-02-102-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before changing the status of a buffer with a pending write we will await upon a new flush for that buffer. So we can take advantage of any flushes posted whilst the buffer is active and pending processing by the GPU, by clearing its write_domain and updating its last_rendering_seqno -- thus saving a potential flush in deep queues and improves flushing behaviour upon eviction for both GTT space and fences. In order to reduce the time spent searching the active list for matching write_domains, we move those to a separate list whose elements are the buffers belong to the active/flushing list with pending writes. Orignal patch by Chris Wilson <chris@chris-wilson.co.uk>, forward-ported by me. In addition to better performance, this also fixes a real bug. Before this changes, i915_gem_evict_everything didn't work as advertised. When the gpu was actually busy and processing request, the flush and subsequent wait would not move active and dirty buffers to the inactive list, but just to the flushing list. Which triggered the BUG_ON at the end of this function. With the more tight dirty buffer tracking, all currently busy and dirty buffers get moved to the inactive list by one i915_gem_flush operation. I've left the BUG_ON I've used to prove this in there. References: Bug 25911 - 2.10.0 causes kernel oops and system hangs http://bugs.freedesktop.org/show_bug.cgi?id=25911 Bug 26101 - [i915] xf86-video-intel 2.10.0 (and git) triggers kernel oops within seconds after login http://bugs.freedesktop.org/show_bug.cgi?id=26101 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Adam Lantos <hege@playma.org> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
* | drm/i915: Rework DPLL calculation parameters for IronlakeZhenyu Wang2010-02-101-50/+167
|/ | | | | | | | | | | | | | | | | | | | Got Ironlake DPLL parameter table, which reflects the hardware optimized values. So this one trys to list DPLL parameters for different output types, should potential fix clock issue seen on new Arrandale CPUs. This fixes DPLL setting failure on one 1920x1080 dual channel LVDS for Ironlake. Test has also been made on LVDS panels with smaller size and CRT/HDMI/DP ports for different monitors on their all supported modes. Update: - Change name of double LVDS to dual LVDS. - Fix SSC 120M reference clock to use the right range. Cc: CSJ <changsijay@gmail.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge branch 'for-linus' of ↵Linus Torvalds2010-02-067-19/+91
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Fix leak of relocs along do_execbuffer error path drm/i915: slow acpi_lid_open() causes flickering - V2 drm/i915: Disable SR when more than one pipe is enabled drm/i915: page flip support for Ironlake drm/i915: Fix the incorrect DMI string for Samsung SX20S laptop drm/i915: Add support for SDVO composite TV drm/i915: don't trigger ironlake vblank interrupt at irq install drm/i915: handle non-flip pending case when unpinning the scanout buffer drm/i915: Fix the device info of Pineview drm/i915: enable vblank interrupt on ironlake drm/i915: Prevent use of uninitialized pointers along error path. drm/i915: disable hotplug detect before Ironlake CRT detect
| * drm/i915: Fix leak of relocs along do_execbuffer error pathChris Wilson2010-02-041-2/+5
| | | | | | | | | | | | | | | | Following a gpu hang, we would leak the relocation buffer. So simply earrange the error path to always free the relocation buffer. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: slow acpi_lid_open() causes flickering - V2Thomas Meyer2010-02-041-1/+8
| | | | | | | | | | | | | | | | | | | | acpi_lid_open() could take up to 10ms on my computer. Some component is calling the drm GETCONNECTOR ioctl many times in a row. This results in flickering (for example, when starting a video). Fix it by assuming an always connected lid status. Signed-off-by: Thomas Meyer <thomas@m3y3r.de> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Disable SR when more than one pipe is enabledDavid John2010-02-041-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Self Refresh should be disabled on dual plane configs. Otherwise, as the SR watermark is not calculated for such configs, switching to non VGA mode causes FIFO underrun and display flicker. This fixes Korg Bug #14897. Signed-off-by: David John <davidjon@xenontk.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: page flip support for IronlakeJesse Barnes2010-01-291-3/+14
| | | | | | | | | | | | | | | | | | This patch adds support for page flipping on Ironlake, which uses different interrupt bits for triggering flip submit IRQs. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: hand-resolved for rebasing off of render power saving patch] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix the incorrect DMI string for Samsung SX20S laptopZhao Yakui2010-01-291-1/+1
| | | | | | | | | | | | Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reported-by: Philipp Kohlbecher <xt28@gmx.de> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Add support for SDVO composite TVZhao Yakui2010-01-291-0/+8
| | | | | | | | | | Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: don't trigger ironlake vblank interrupt at irq installLi Peng2010-01-291-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Zhenyu noticed that the ironlake vblank enabling patch has one issue that it will trigger vblank starting from irq postinstall, this isn't necessary. This patch addresses this issue by only adding the vblank into DEIER but mask them in DEIMR, so that it won't trigger vblank interrupt at irq install. Signed-off-by: Li Peng <peng.li@intel.com> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: handle non-flip pending case when unpinning the scanout bufferJesse Barnes2010-01-251-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | The first page flip queued will replace the current front buffer, which should have a 0 pending flip count. So at finish time we need to handle that case (i.e. if the flip count is 0 *or* dec_and_test is 0 we need to wake the waiters). Also fix up an error path in the queue function and add some debug output (only enabled with driver debugging). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix the device info of PineviewLi Peng2010-01-251-1/+1
| | | | | | | | | | | | | | | | | | Pineview doesn't has CXSR and need GTT-based hardware status page. It fixes a X boot hung issue on Pinview since commit cfdf1f Signed-off-by: Li Peng <peng.li@intel.com> Acked-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: enable vblank interrupt on ironlakeLi Peng2010-01-252-11/+20
| | | | | | | | | | | | | | | | | | | | | | so far vblank interrupt on ironlake is disabled, this would cause bad gfx performance if userspace calls drm_wait_vblank. This patch enables vblank interrupt on ironlake and follows vblank get/put model. Signed-off-by: Li Peng <peng.li@intel.com> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Prevent use of uninitialized pointers along error path.Chris Wilson2010-01-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X.org hang with [drm:i915_gem_do_execbuffer] *ERROR* in dmesg http://bugzilla.kernel.org/show_bug.cgi?id=15114 Matej found he was hitting an error path within i915_gem_do_execbuffer() that led to the attempt to dereference an uninitialised pointer during cleanup. This path used to be safe as we used to calloc the object lists, but this was changed in c8e0f93. Daniel Vetter had also spotted this error and proposed a similar patch. [ 6379.732892] [drm:i915_gem_do_execbuffer] *ERROR* Object ffff880098cd6540 appears more than once in object list [ 6379.740976] [drm:i915_gem_do_execbuffer] *ERROR* Object ffff880098cd6540 appears more than once in object list [ 6379.740995] BUG: unable to handle kernel NULL pointer dereference at 00000000000000a0 [ 6379.740998] IP: [<ffffffff8122ddb5>] i915_gem_do_execbuffer+0xba5/0x1260 [ 6379.741006] PGD babab067 PUD bb435067 PMD 0 [ 6379.741010] Oops: 0002 [#1] PREEMPT SMP [ 6379.741014] last sysfs file: /sys/devices/pci0000:00/0000:00:1c.2/0000:06:00.0/ieee80211/phy0/rfkill0/state [ 6379.741017] CPU 1 [ 6379.741021] Pid: 2186, comm: X Not tainted 2.6.33-rc4-00399-g24bc734 #142 M11D/ESPRIMO Mobile M9400 [ 6379.741023] RIP: 0010:[<ffffffff8122ddb5>] [<ffffffff8122ddb5>] i915_gem_do_execbuffer+0xba5/0x1260 [ 6379.741027] RSP: 0018:ffff8800b9047b78 EFLAGS: 00213206 [ 6379.741029] RAX: 0000000000000000 RBX: 000000000000004f RCX: ffff880098cac800 [ 6379.741032] RDX: ffff880098caca78 RSI: ffff8800b9047c98 RDI: ffff880098cd6540 [ 6379.741034] RBP: ffff8800b9047c78 R08: ffffffff814b96b5 R09: 0000000000000006 [ 6379.741036] R10: 0000000000000000 R11: 0000000000000003 R12: 000000000000004e [ 6379.741038] R13: 00000000fffffff7 R14: 0000000000000000 R15: 0000000000000001 [ 6379.741041] FS: 0000000000000000(0000) GS:ffff880001900000(0063) knlGS:00000000f72636c0 [ 6379.741043] CS: 0010 DS: 002b ES: 002b CR0: 0000000080050033 [ 6379.741041] FS: 0000000000000000(0000) GS:ffff880001900000(0063) knlGS:00000000f72636c0 [ 6379.741043] CS: 0010 DS: 002b ES: 002b CR0: 0000000080050033 [ 6379.741045] CR2: 00000000000000a0 CR3: 00000000b9000000 CR4: 00000000000006e0 [ 6379.741048] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 6379.741050] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 [ 6379.741052] Process X (pid: 2186, threadinfo ffff8800b9046000, task ffff8800bb5d8000) [ 6379.741054] Stack: [ 6379.741055] ffffc90023f57000 ffffc90023f56fff ffffc90023f56fff ffffc90023f55000 [ 6379.741059] <0> ffff8800b9047c98 ffff8800bb43c840 ffff8800bf1de800 ffff8800bf1de820 [ 6379.741063] <0> ffff8800b9047bd8 ffff880098cac800 0000000000000000 0000000000000002 [ 6379.741068] Call Trace: [ 6379.741072] [<ffffffff8122e6cb>] ? i915_gem_execbuffer+0x6b/0x370 [ 6379.741077] [<ffffffff810a5f52>] ? __vmalloc_node+0xa2/0xb0 [ 6379.741080] [<ffffffff8122e6cb>] ? i915_gem_execbuffer+0x6b/0x370 [ 6379.741083] [<ffffffff8122e816>] i915_gem_execbuffer+0x1b6/0x370 [ 6379.741086] [<ffffffff8120cd55>] drm_ioctl+0x1d5/0x460 [ 6379.741089] [<ffffffff8122e660>] ? i915_gem_execbuffer+0x0/0x370 [ 6379.741093] [<ffffffff81248c35>] i915_compat_ioctl+0x45/0x50 [ 6379.741097] [<ffffffff810f1659>] compat_sys_ioctl+0xa9/0x1570 [ 6379.741102] [<ffffffff810b1d5c>] ? vfs_read+0x13c/0x1a0 [ 6379.741106] [<ffffffff81028424>] sysenter_dispatch+0x7/0x2b [ 6379.741108] Code: 08 85 c0 74 52 31 db 0f 1f 80 00 00 00 00 48 63 c3 48 8b 8d 68 ff ff ff 48 8d 14 c1 48 8b 02 48 85 c0 74 25 48 8b 80 80 00 00 00 <c7> 80 a0 00 00 00 00 00 00 00 48 8b 3a 48 85 ff 74 0c 48 c7 c6 [ 6379.741142] RIP [<ffffffff8122ddb5>] i915_gem_do_execbuffer+0xba5/0x1260 [ 6379.741145] RSP <ffff8800b9047b78> [ 6379.741147] CR2: 00000000000000a0 [ 6379.741159] ---[ end trace 0598809afa4c31db ]--- Reported-by: Matej Laitl <strohel@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: disable hotplug detect before Ironlake CRT detectZhenyu Wang2010-01-251-0/+3
| | | | | | | | | | | | | | | | | | | | This tries to fix CRT detect loop hang seen on some Ironlake form factor, to clear up hotplug detect state before taking CRT detect to make sure next hotplug detect cycle is consistent. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
generated by cgit v1.1 at 2025-01-30 13:11:16 +0000