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* [MIPS] Qemu: Remove platform.Ralf Baechle2008-01-292-57/+0
| | | | | | | | | | The Qemu platform was originally implemented to have an easily supportable platform until Qemu reaches a state where it emulates a real world system. Since the latest release Qemu is capable of emulating the MIPSsim and Malta platforms, so this goal has been reached. The Qemu plaform is also rather underfeatured so less useful than a Malta emulation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Delete CONFIG_MSP_FPGARalf Baechle2008-01-291-4/+0
| | | | | | Originally noticed by Jiri Olsa <olsajiri@gmail.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] remove unneeded button check for resetYoichi Yuasa2008-01-291-14/+1
| | | | | | | | Removed unneeded button check for reset. Because, the Cobalt has power switch. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: remove unused mips_timer_state()Yoichi Yuasa2008-01-291-8/+1
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] fixmap: delete unused __set_fixmap, set_fixmap and set_fixmap_nocacheRalf Baechle2008-01-291-10/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] RM: Collected changesThomas Bogendoerfer2008-01-293-68/+94
| | | | | | | | | | | | | | | | - EISA support for non PCI RMs (RM200 and RM400-xxx). The major part is the splitting of the EISA and onboard ISA of the RM200, which makes the EISA bus on the RM200 look like on other RMs. - 64bit kernel support - system type detection is now common for big and little endian - moved sniprom code to arch/mips/fw - added call_o32 function to arch/mips/fw/lib, which uses a private stack for calling prom functions - fix problem with ISA interrupts, which makes using PIT clockevent possible Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss2008-01-291-2/+2
| | | | | | | | | | This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP28 supportThomas Bogendoerfer2008-01-295-4/+104
| | | | | | | | Add support for SGI IP28 machines (Indigo 2 with R10k CPUs) This work is mainly based on Peter Fuersts work. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove CONFIG_SIBYTE_PT{1120,1125,SWARM}Ralf Baechle2008-01-292-22/+2
| | | | | | | | According to Broadcom the PT systems are production test systems which never reached customers so no need to keep the fragmentary support we currently have. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP28: added cache barrier to assembly routinesThomas Bogendoerfer2008-01-291-0/+8
| | | | | | | | | | | IP28 needs special treatment to avoid speculative accesses. gcc takes care for .c code, but for assembly code we need to do it manually. This is taken from Peter Fuersts IP28 patches. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TXx9 watchdog support for rbhma3100,rbhma4200,rbhma4500Atsushi Nemoto2008-01-291-0/+1
| | | | | | | | This patch adds support for txx9wdt driver to rbhma3100, rbhma4200 and rbhma4500 platform. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP22/IP28: fix extracting board/chip revThomas Bogendoerfer2008-01-291-2/+2
| | | | | | | Taken from Peter Fuersts IP28 patches Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use real cache invalidateThomas Bogendoerfer2008-01-291-0/+7
| | | | | | | | | R10k non coherent machines need a real dma cache invalidate to get rid of speculative stores in cache. For other machines this promises a slight speedup. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMP: Call platform methods via ops structure.Ralf Baechle2008-01-293-58/+61
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Scheduler support for SMTRalf Baechle2008-01-293-1/+23
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Put cast inside macro instead of all the callersAndrew Sharp2008-01-291-1/+1
| | | | | | | | | | Since all the callers of the PHYS_TO_XKPHYS macro call with a constant, put the cast to LL inside the macro where it really should be rather than in all the callers. This makes macros like PHYS_TO_XKSEG_UNCACHED work without gcc whining. Signed-off-by: Andrew Sharp <andy.sharp@onstor.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] remove unused mips_machtypeYoichi Yuasa2008-01-291-104/+0
| | | | | | | Removed unused mips_machtype. These are only set but not used. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] CFE: Make code remotely resemble Linux code.Christoph Hellwig2008-01-292-87/+19
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] R4000/R4400 daddiu erratum workaroundMaciej W. Rozycki2008-01-293-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This complements the generic R4000/R4400 errata workaround code and adds bits for the daddiu problem. In most places it just modifies handwritten assembly code so that the assembler is allowed to use a temporary register as daddiu may now be treated as a macro that expands to a sequence of li and daddu. It is the AT register or, where AT is unavailable or used explicitly for another purpose, an explicitly-named register is selected, using the .set at=<reg> feature added recently to gas. This feature is only used if CONFIG_CPU_DADDI_WORKAROUNDS has been set, so if the workaround remains disabled, the required version of binutils stays unchanged. Similarly, daddiu instructions put in branch delay slots in noreorder fragments are now taken out of them and the assembler is allowed to reorder them itself as possible (which it does making the whole idea of scheduling them into delay slots manually questionable). Also in the very few places where such a simple conversion was not possible, a handcoded longer sequence is implemented. Other than that there are changes to code responsible for building the TLB fault and page clear/copy handlers to avoid daddiu as appropriate. These are only effective if the erratum is verified to be present at the run time. Finally there is a trivial update to __delay(), because it uses daddiu in a branch delay slot. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] R4000/R4400 errata workaroundsMaciej W. Rozycki2008-01-293-2/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the gereric part of R4000/R4400 errata workarounds. They include compiler and assembler support as well as some source code modifications to address the problems with some combinations of multiply/divide+shift instructions as well as the daddi and daddiu instructions. Changes included are as follows: 1. New Kconfig options to select workarounds by platforms as necessary. 2. Arch top-level Makefile to pass necessary options to the compiler; also incompatible configurations are detected (-mno-sym32 unsupported as horribly intrusive for little gain). 3. Bug detection updated and shuffled -- the multiply/divide+shift problem is lethal enough that if not worked around it makes the kernel crash in time_init() because of a division by zero; the daddiu erratum might also trigger early potentially, though I have not observed it. On the other hand the daddi detection code requires the exception subsystem to have been initialised (and is there mainly for information). 4. r4k_daddiu_bug() added so that the existence of the erratum can be queried by code at the run time as necessary; useful for generated code like TLB fault and copy/clear page handlers. 5. __udelay() updated as it uses multiplication in inline assembly. Note that -mdaddi requires modified toolchain (which has been maintained by myself and available from my site for ~4years now -- versions covered are GCC 2.95.4 - 4.1.2 and binutils from 2.13 onwards). The -mfix-r4000 and -mfix-r4400 have been standard for a while though. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix build error.Frank Rowand2008-01-221-3/+3
| | | | | | | | Fix compile warning (which becomes compile error due to -Werror). Type of argument "flags" for spin_lock_irqsave() was incorrect in some functions. Signed-off-by: Frank Rowand <frank.rowand@am.sony.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cacheops.h: Fix typo.Ralf Baechle2008-01-151-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix PCI resource conflictSergei Shtylyov2007-12-141-4/+5
| | | | | | | | | ... by getting the PCI resources back into the 32-bit range -- there's no need therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI work again while currently the kernel skips the bus scan. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Fix Au1x SD controller IRQManuel Lauss2007-12-091-2/+5
| | | | | | | | With the introduction of MIPS_CPU_IRQ_BASE, the hardcoded IRQ number of the au1100/au1200 SD controller(s) is no longer valid. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix IRQ basesSergei Shtylyov2007-12-061-10/+11
| | | | | | | | | Do what the commits commits f3e8d1da389fe2e514e31f6e93c690c8e1243849 and 9d360ab4a7568a8d177280f651a8a772ae52b9b9 failed to achieve -- actually convert the Alchemy code to irq_cpu. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix use of smp_processor_id() in preemptible code.Pavel Kiryukhin2007-12-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freeing prom memory: 956kb freed Freeing firmware memory: 978944k freed Freeing unused kernel memory: 180k freed BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1 caller is r4k_dma_cache_wback_inv+0x144/0x2a0 Call Trace: [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0 ... CONFIG_DEBUG_PREEMPT is enabled. -- Bug cause is blast_dcache_range() in preemptible code [in r4k_dma_cache_wback_inv()]. blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that uses cpu_dcache_line_size(). It uses current_cpu_data that use smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT smp_processor_id emits BUG if we are executing with preemption enabled. Cpu options of cpu0 are assumed to be the superset of all processors. Can I make the same assumptions for cache line size and fix this issue the following way: Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IP22ZILOG: fix lockup and sysrqThomas Bogendoerfer2007-11-291-2/+0
| | | | | | | | | | | | - fix lockup when switching from early console to real console - make sysrq reliable - fix panic, if sysrq is issued before console is opened Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] 64-bit Sibyte kernels need DMA32.Ralf Baechle2007-11-261-0/+1
| | | | | | | | | | | | Sibyte SOCs only have 32-bit PCI. Due to the sparse use of the address space only the first 1GB of memory is mapped at physical addresses below 1GB. If a system has more than 1GB of memory 32-bit DMA will not be able to reach all of it. For now this patch is good enough to keep Sibyte users happy but it seems eventually something like swiotlb will be needed for Sibyte. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Only build r4k clocksource for systems that work ok with it.Ralf Baechle2007-11-261-0/+11
| | | | | | | | | | In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle R4000/R4400 mfc0 from count register.Ralf Baechle2007-11-261-2/+3
| | | | | | | | | | | | | | | | | | | | | The R4000 and R4400 have an errata where if the cp0 count register is read in the exact moment when it matches the compare register no interrupt will be generated. This bug may be triggered if the cp0 count register is being used as clocksource and the compare interrupt as clockevent. So a simple workaround is to avoid using the compare for both facilities on the affected CPUs. This is different from the workaround suggested in the old errata documents; at some opportunity probably the official version should be implemented and tested. Another thing to find out is which processor versions exactly are affected. I only have errata documents upto R4400 V3.0 available so for the moment the code treats all R4000 and R4400 as broken. This is potencially a problem for some machines that have no other decent clocksource available; this workaround will cause them to fall back to another clocksource, worst case the "jiffies" source.
* [MIPS] Fix possible hang in LL/SC futex loops.Ralf Baechle2007-11-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LL / SC loops in __futex_atomic_op() have the usual fixups necessary for memory acccesses to userspace from kernel space installed: __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: ll %1, %4 # __futex_atomic_op \n" " .set mips0 \n" " " insn " \n" " .set mips3 \n" "2: sc $1, %2 \n" " beqz $1, 1b \n" __WEAK_LLSC_MB "3: \n" " .set pop \n" " .set mips0 \n" " .section .fixup,\"ax\" \n" "4: li %0, %6 \n" " j 2b \n" <----- " .previous \n" " .section __ex_table,\"a\" \n" " "__UA_ADDR "\t1b, 4b \n" " "__UA_ADDR "\t2b, 4b \n" " .previous \n" : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) : "memory"); The branch at the end of the fixup code, it goes back to the SC instruction, no matter if the fault was first taken by the LL or SC instruction resulting in an endless loop which will only terminate if the address become valid again due to another thread setting up an accessible mapping and the CPU happens to execute the SC instruction successfully which due to the preceeding ERET instruction of the fault handler would only happen if UNPREDICTABLE instruction behaviour of the SC instruction without a preceeding LL happens to favor that outcome. But normally processes are nice, pass valid arguments and we were just getting away with this. Thanks to Kaz Kylheku <kaz@zeugmasystems.com> for providing the original report and a test case. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix context DSP context / TLS pointer switching bug for new threads.Ralf Baechle2007-11-261-2/+6
| | | | | | | | | | | | | | | | | | | | | | | A new born thread starts execution not in schedule but rather in ret_from_fork which results in it bypassing the part of the code to load a new context written in C which are the DSP context and the userlocal register which Linux uses for the TLS pointer. Frequently we were just getting away with this bug for a number of reasons: o Real world application scenarios are very unlikely to use clone or fork in blocks of DSP code. o Linux by default runs the child process right after the fork, so the child by luck will find all the right context in the DSP and userlocal registers. o So far the rdhwr instruction was emulated on all hardware so userlocal wasn't getting referenced at all and the emulation wasn't suffering from the issue since it gets it's value straight from the thread's thread_info. Fixed by moving the code to load the context from switch_to() to finish_arch_switch which will be called by newborn and old threads. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: More interrupt renumbering fixes.Ralf Baechle2007-11-261-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix pcspeaker build.Ralf Baechle2007-11-262-10/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Lasat: Fix overlap of interrupt number ranges.Yoichi Yuasa2007-11-152-5/+13
| | | | | | | The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-151-0/+1
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Change get_cycles to always return 0.Ralf Baechle2007-11-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This avoids us executing an mfc0 c0_count instruction on processors which don't have but also on certain R4000 and R4400 versions where reading from the count register just in the very moment when its value equals c0_compare will result in the timer interrupt getting lost. There is still a number of users of get_cycles remaining outside the arch code: crypto/tcrypt.c: start = get_cycles(); crypto/tcrypt.c: end = get_cycles(); crypto/tcrypt.c: start = get_cycles(); crypto/tcrypt.c: end = get_cycles(); crypto/tcrypt.c: start = get_cycles(); crypto/tcrypt.c: end = get_cycles(); drivers/char/hangcheck-timer.c: return get_cycles(); drivers/char/hangcheck-timer.c: printk("Hangcheck: Using get_cycles().\n"); drivers/char/random.c: sample.cycles = get_cycles(); drivers/input/joystick/analog.c:#define GET_TIME(x) do { x = get_cycles(); } include/linux/arcdevice.h: _x = get_cycles(); \ include/linux/arcdevice.h: _y = get_cycles(); \ mm/slub.c: if (!s->defrag_ratio || get_cycles() % 1024 > s->defrag_ratio) mm/slub.c: p += 64 + (get_cycles() & 0xff) * sizeof(void *); Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Use i8253.c lock for PC speaker on MIPS, too.Ralf Baechle2007-11-021-0/+4
| | | | | | | | | | The Jazz machines have to use the PIT timer for dyntick and highresolution kernels. This may break because currently just like i386 used to do MIPS uses two separate spinlocks in the actual PIT code and the PC speaker code. So switch to do it the same that x86 currently does PIT locking. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] Fix and cleanup the MIPS part of the (ab)use of CLOCK_TICK_RATE.Ralf Baechle2007-11-026-91/+5
| | | | | | | | | This is the clock rate of the i8253 PIT. A MIPS system may not have a PIT by the symbol is used all over the kernel including some APIs. So keeping it defined to the number for the PIT is the only sane thing for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] i8253.h: Remove all i8259 related definitions.Ralf Baechle2007-11-021-15/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.Yoichi Yuasa2007-11-021-2/+1
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Code cleanupsAtsushi Nemoto2007-11-021-13/+0
| | | | | | | | | | | | | * Do not include unnecessary headers. * Do not mention time.README. * Do not mention mips_timer_ack. * Make clocksource_mips static. It is now dedicated to c0_timer. * Initialize clocksource_mips.read statically. * Remove null_hpt_read. * Remove an argument of plat_timer_setup. It is just a placeholder. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Remove now unused local_timer_interrupt.Ralf Baechle2007-11-021-5/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Replace plat_timer_setup with modern APIs.Ralf Baechle2007-10-291-0/+1
| | | | | | plat_timer_setup is no longer getting called. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] txx9tmr clockevent/clocksource driverAtsushi Nemoto2007-10-296-49/+72
| | | | | | | | | | | | | | Convert jmr3927_clock_event_device to more generic txx9tmr_clock_event_device which supports one-shot mode. The txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer interrupt was not available. Convert jmr3927_hpt_read to txx9_clocksource driver which does not depends jiffies anymore. The txx9_clocksource itself can be used for TX49, but normally TX49 uses higher precision clocksource_mips. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: Fixes after interrupt renumbering.Ralf Baechle2007-10-291-1/+3
| | | | | | And general untangling. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Remove declaration of plat_timer_setup, there is no caller.Ralf Baechle2007-10-291-1/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-10-223-5/+8
|\ | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] time: Make c0_compare_int_usable more bullet proof [MIPS] Kbuild: Use the new cc-cross-prefix feature. [MIPS] Fix include wrapper symbol to something sane. [MIPS] Malta: Delete dead code. [MIPS] time: Add GT641xx timer0 clockevent driver [MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code. [MIPS] time: SMP/NUMA-proofing of IP27 HUB RT timer code. [MIPS] time: Fix calculation in clockevent_set_clock()
| * [MIPS] Fix include wrapper symbol to something sane.Ralf Baechle2007-10-221-3/+3
| | | | | | | | | | | | And why are there i8253.h and 8253pit.h ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] time: Add GT641xx timer0 clockevent driverYoichi Yuasa2007-10-221-0/+5
| | | | | | | | | | | | | | | | And make use of it for Cobalt. A few others such as the Malta could make use of it as well. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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