From e9ac829185c5d17787d78c13c05a40c39d660239 Mon Sep 17 00:00:00 2001 From: Johannes Weiner Date: Tue, 21 Jul 2009 17:08:28 +0200 Subject: ARM: boolean bit testing Bit testing (test, testset, testclear, testchange) for bit numbers known at compile time returns a word with the tested-for bit set. Change it to return a true boolean value so to make it consistent with the out-of-line path and all the other bitops implementations. Signed-off-by: Johannes Weiner Signed-off-by: Russell King --- arch/arm/include/asm/bitops.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 63a481f..338ff19 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -84,7 +84,7 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p) *p = res | mask; raw_local_irq_restore(flags); - return res & mask; + return (res & mask) != 0; } static inline int @@ -101,7 +101,7 @@ ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p) *p = res & ~mask; raw_local_irq_restore(flags); - return res & mask; + return (res & mask) != 0; } static inline int @@ -118,7 +118,7 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p) *p = res ^ mask; raw_local_irq_restore(flags); - return res & mask; + return (res & mask) != 0; } #include -- cgit v1.1 From cde3f8607350666c4dd120dbbdbd9c70ffb2ea61 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 13 Oct 2009 08:54:30 +0100 Subject: ARM: 5759/1: Add register information of threads to coredump Defines ELF_CORE_COPY_TASK_REGS so that CPU register information of every thread is included in coredump. Without this, only the faulting thread is coredumped. Cc: Roger Quadros Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mika Westerberg Signed-off-by: Artem Bityutskiy Signed-off-by: Russell King --- arch/arm/include/asm/elf.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index c3b911e..6aac3f5 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -98,6 +98,9 @@ extern int elf_check_arch(const struct elf32_hdr *); extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk) +int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); +#define ELF_CORE_COPY_TASK_REGS dump_task_regs + #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 -- cgit v1.1 From daaeb6c93829806221b2ac533330c64f338ebb89 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 15 Oct 2009 15:06:47 +0100 Subject: ARM: 5763/1: ARM: SMP: Fix the BUG with CONFIG_PREEMPT enabled This patch fixes the BUG: using smp_processor_id() in preemptible Below is the stripped backtrace. BUG: using smp_processor_id() in preemptible [00000000] code: init/1 caller is flush_tlb_mm+0x44/0x70 Backtrace: [] (dump_backtrace+0x0/0x110) from [] (dump_stack+0x18/0x1c) r7:00000000 r6:c00234f0 r5:00000001 r4:c7828000 [] (dump_stack+0x0/0x1c) from [] (debug_smp_processor_id+0xc0/0xf0) [] (debug_smp_processor_id+0x0/0xf0) from [] (flush_tlb_mm+0x44/0x70) r7:00000000 r6:c60b41a0 r5:c60b4154 r4:00000001 [] (flush_tlb_mm+0x0/0x70) from [] (dup_mm+0x304/0x38c) r5:c1f09058 r4:00000000 [] (dup_mm+0x0/0x38c) from [] (copy_process+0x7b8/0xeb0) [] (copy_process+0x0/0xeb0) from [] (do_fork+0x15c/0x29c) [] (do_fork+0x0/0x29c) from [] (sys_clone+0x34/0x3c) [] (sys_clone+0x0/0x3c) from [] (ret_fast_syscall+0x0/0x2c) Signed-off-by: Santosh Shilimkar Signed-off-by: Russell King --- arch/arm/include/asm/tlbflush.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index a45ab5d..c2f1605 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -350,7 +350,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_WB)) dsb(); - if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) { + if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { if (tlb_flag(TLB_V3_FULL)) asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_U_FULL)) @@ -360,6 +360,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_V4_I_FULL)) asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); } + put_cpu(); if (tlb_flag(TLB_V6_U_ASID)) asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc"); -- cgit v1.1 From df71dfd4ca01130f98d9dbfab76c440d72a177c6 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 24 Oct 2009 22:36:36 +0100 Subject: ARM: Fix errata 411920 workarounds Errata 411920 indicates that any "invalidate entire instruction cache" operation can fail if the right conditions are present. This is not limited just to those operations in flush.c, but elsewhere. Place the workaround in the already existing __flush_icache_all() function instead. Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index fd03fb6..3d0cdd2 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -414,9 +414,14 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page static inline void __flush_icache_all(void) { +#ifdef CONFIG_ARM_ERRATA_411920 + extern void v6_icache_inval_all(void); + v6_icache_inval_all(); +#else asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" : : "r" (0)); +#endif } #define ARCH_HAS_FLUSH_ANON_PAGE -- cgit v1.1