From c05b48af822c415baeadafa6c4a4ea7f79f337db Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 6 Aug 2010 20:12:06 +0900 Subject: ARM: S5PV310: Add SMDKC210 board support file This patch adds Samsung SMDKC210 board support file. The SoC of SMDKC210, S5PC210(MCP) is one of package option of S5PV310. And because composition of SMDKC210 and SMDKV310 differs, need SMDKC210 with SMDKV310. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 8 ++++ arch/arm/mach-s5pv310/Makefile | 1 + arch/arm/mach-s5pv310/mach-smdkc210.c | 89 +++++++++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+) create mode 100644 arch/arm/mach-s5pv310/mach-smdkc210.c (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 331b5bd..ae8e554 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -27,6 +27,14 @@ config S5PV310_SETUP_I2C2 # machine support +config MACH_SMDKC210 + bool "SMDKC210" + select CPU_S5PV310 + select ARCH_SPARSEMEM_ENABLE + help + Machine support for Samsung SMDKC210 + S5PC210(MCP) is one of package option of S5PV310 + config MACH_SMDKV310 bool "SMDKV310" select CPU_S5PV310 diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index d5b51c7..aefb14f 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o # machine support +obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c new file mode 100644 index 0000000..656de01 --- /dev/null +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -0,0 +1,89 @@ +/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = SMDKC210_UCON_DEFAULT, + .ulcon = SMDKC210_ULCON_DEFAULT, + .ufcon = SMDKC210_UFCON_DEFAULT, + }, +}; + +static void __init smdkc210_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs)); +} + +static void __init smdkc210_machine_init(void) +{ +#ifdef CONFIG_CACHE_L2X0 + l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); +#endif +} + +MACHINE_START(SMDKC210, "SMDKC210") + /* Maintainer: Kukjin Kim */ + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5pv310_init_irq, + .map_io = smdkc210_map_io, + .init_machine = smdkc210_machine_init, + .timer = &s5pv310_timer, +MACHINE_END -- cgit v1.1 From ca0ffd469af6a00a24a1f888ac280e3e7d4951f5 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 6 Aug 2010 20:33:46 +0900 Subject: ARM: S5PV310: update S5PV310 Kconfig for supporting multiple machines This patch updates Kconfig of mach-s5pv310 for easily dividing S5PC210 and S5PV310 boards. S5PC210(MCP) machines and S5PV310 machines can be build into one kernel, this will be provied/submitted when new defconfig can be merged. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index ae8e554..9ac29fe 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -27,6 +27,8 @@ config S5PV310_SETUP_I2C2 # machine support +menu "S5PC210 Machines" + config MACH_SMDKC210 bool "SMDKC210" select CPU_S5PV310 @@ -35,13 +37,6 @@ config MACH_SMDKC210 Machine support for Samsung SMDKC210 S5PC210(MCP) is one of package option of S5PV310 -config MACH_SMDKV310 - bool "SMDKV310" - select CPU_S5PV310 - select ARCH_SPARSEMEM_ENABLE - help - Machine support for Samsung SMDKV310 - config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_S5PV310 @@ -50,4 +45,17 @@ config MACH_UNIVERSAL_C210 Machine support for Samsung Mobile Universal S5PC210 Reference Board. S5PC210(MCP) is one of package option of S5PV310 +endmenu + +menu "S5PV310 Machines" + +config MACH_SMDKV310 + bool "SMDKV310" + select CPU_S5PV310 + select ARCH_SPARSEMEM_ENABLE + help + Machine support for Samsung SMDKV310 + +endmenu + endif -- cgit v1.1 From 34d79315a22b743a8f4e26c2e11fa16469c71473 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Sat, 21 Aug 2010 09:49:49 +0900 Subject: ARM: S5PV310: Add GPIO keys at Universal board Universal board has 5 GPIO keys. Signed-off-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/mach-universal_c210.c | 62 +++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c index 2388cb9..b57efae 100644 --- a/arch/arm/mach-s5pv310/mach-universal_c210.c +++ b/arch/arm/mach-s5pv310/mach-universal_c210.c @@ -7,7 +7,11 @@ * published by the Free Software Foundation. */ +#include #include +#include +#include +#include #include #include @@ -60,6 +64,61 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = { }, }; +static struct gpio_keys_button universal_gpio_keys_tables[] = { + { + .code = KEY_VOLUMEUP, + .gpio = S5PV310_GPX2(0), /* XEINT16 */ + .desc = "gpio-keys: KEY_VOLUMEUP", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_VOLUMEDOWN, + .gpio = S5PV310_GPX2(1), /* XEINT17 */ + .desc = "gpio-keys: KEY_VOLUMEDOWN", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_CONFIG, + .gpio = S5PV310_GPX2(2), /* XEINT18 */ + .desc = "gpio-keys: KEY_CONFIG", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_CAMERA, + .gpio = S5PV310_GPX2(3), /* XEINT19 */ + .desc = "gpio-keys: KEY_CAMERA", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, { + .code = KEY_OK, + .gpio = S5PV310_GPX3(5), /* XEINT29 */ + .desc = "gpio-keys: KEY_OK", + .type = EV_KEY, + .active_low = 1, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data universal_gpio_keys_data = { + .buttons = universal_gpio_keys_tables, + .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables), +}; + +static struct platform_device universal_gpio_keys = { + .name = "gpio-keys", + .dev = { + .platform_data = &universal_gpio_keys_data, + }, +}; + +static struct platform_device *universal_devices[] __initdata = { + &universal_gpio_keys, +}; + static void __init universal_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -72,6 +131,9 @@ static void __init universal_machine_init(void) #ifdef CONFIG_CACHE_L2X0 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); #endif + + /* Last */ + platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); } MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") -- cgit v1.1 From 11adcc29f068229ca77fb91b42047f1a03cf500c Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Fri, 20 Aug 2010 18:17:51 +0900 Subject: ARM: S5PV310: Add CPU hotplug support for S5PV310 This patch adds CPU hotplug support for S5PV310/S5PC210. Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/hotplug.c | 144 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 arch/arm/mach-s5pv310/hotplug.c (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c new file mode 100644 index 0000000..03652c3 --- /dev/null +++ b/arch/arm/mach-s5pv310/hotplug.c @@ -0,0 +1,144 @@ +/* linux arch/arm/mach-s5pv310/hotplug.c + * + * Cloned from linux/arch/arm/mach-realview/hotplug.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include + +extern volatile int pen_release; + +static DECLARE_COMPLETION(cpu_killed); + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0) + : "cc"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + /* + * here's the WFI + */ + asm(".word 0xe320f003\n" + : + : + : "memory", "cc"); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * The trouble is, letting people know about this is not really + * possible, since we are currently running incoherently, and + * therefore cannot safely call printk() or anything else + */ +#ifdef DEBUG + printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu); +#endif + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ +#ifdef DEBUG + unsigned int this_cpu = hard_smp_processor_id(); + + if (cpu != this_cpu) { + printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", + this_cpu, cpu); + BUG(); + } +#endif + + printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); + complete(&cpu_killed); + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} -- cgit v1.1 From e33ed879f02182b01a601ae3de70acd536c894c2 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 18 Aug 2010 21:59:01 +0900 Subject: ARM: S5PV310: Adds clock addresses for S5PV310 This patch adds definition of clock address. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/regs-clock.h | 27 +++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h index 4013553..eda07fd 100644 --- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h @@ -26,11 +26,23 @@ #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) - +#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) +#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) +#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) +#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) +#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) +#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) - +#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) +#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) +#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) +#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) +#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) +#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) +#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) +#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C) #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) #define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) #define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) @@ -38,8 +50,19 @@ #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) +#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) +#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) +#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) +#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) +#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) +#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) +#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) +#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) +#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) +#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) +#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) #define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) -- cgit v1.1 From a6aa7a55848ff84b2f296ad30726f0e1ebc5f0ea Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 18 Aug 2010 22:03:19 +0900 Subject: ARM: S5PV310: Removed unused clock This pach removed unused clock on S5PV310/S5PC210. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 46 ++----------------------------------------- 1 file changed, 2 insertions(+), 44 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 26a0f03..823c29f 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -150,24 +150,6 @@ static struct clksrc_clk clk_periphclk = { .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, }; -static struct clksrc_clk clk_atclk = { - .clk = { - .name = "atclk", - .id = -1, - .parent = &clk_moutcore.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 }, -}; - -static struct clksrc_clk clk_pclk_dbg = { - .clk = { - .name = "pclk_dbg", - .id = -1, - .parent = &clk_atclk.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 }, -}; - /* Core list of CMU_CORE side */ static struct clk *clkset_corebus_list[] = { @@ -464,8 +446,6 @@ static struct clksrc_clk *sysclks[] = { &clk_aclk_cores, &clk_aclk_corem1, &clk_periphclk, - &clk_atclk, - &clk_pclk_dbg, &clk_mout_corebus, &clk_sclk_dmc, &clk_aclk_cored, @@ -490,15 +470,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) unsigned long vpllsrc; unsigned long xtal; unsigned long armclk; - unsigned long aclk_corem0; - unsigned long aclk_cores; - unsigned long aclk_corem1; - unsigned long periphclk; unsigned long sclk_dmc; - unsigned long aclk_cored; - unsigned long aclk_corep; - unsigned long aclk_acp; - unsigned long pclk_acp; unsigned int ptr; printk(KERN_DEBUG "%s: registering clocks\n", __func__); @@ -529,26 +501,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) apll, mpll, epll, vpll); armclk = clk_get_rate(&clk_armclk.clk); - aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk); - aclk_cores = clk_get_rate(&clk_aclk_cores.clk); - aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk); - periphclk = clk_get_rate(&clk_periphclk.clk); sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); - aclk_cored = clk_get_rate(&clk_aclk_cored.clk); - aclk_corep = clk_get_rate(&clk_aclk_corep.clk); - aclk_acp = clk_get_rate(&clk_aclk_acp.clk); - pclk_acp = clk_get_rate(&clk_pclk_acp.clk); - - printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n" - "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n" - "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld", - armclk, aclk_corem0, aclk_cores, aclk_corem1, - periphclk, sclk_dmc, aclk_cored, aclk_corep, - aclk_acp, pclk_acp); + + printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld\n", armclk, sclk_dmc); clk_f.rate = armclk; clk_h.rate = sclk_dmc; - clk_p.rate = periphclk; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); -- cgit v1.1 From 9e23552f8ecf85cd4a74741051ed2cfbab630164 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Wed, 18 Aug 2010 22:06:02 +0900 Subject: ARM: S5PV310: Adds clkset_aclk for removing clkset_aclk_xxx This patch adds 'clkset_aclk' to use commonly. And removed struct clksrc_sources clkset_aclk_200, clkset_aclk_100, clkset_aclk_160, and clkset_aclk_133. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 823c29f..20f3513 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -223,7 +223,7 @@ static struct clk *clkset_aclk_top_list[] = { [1] = &clk_sclk_apll.clk, }; -static struct clksrc_sources clkset_aclk_200 = { +static struct clksrc_sources clkset_aclk = { .sources = clkset_aclk_top_list, .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), }; @@ -233,52 +233,37 @@ static struct clksrc_clk clk_aclk_200 = { .name = "aclk_200", .id = -1, }, - .sources = &clkset_aclk_200, + .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, }; -static struct clksrc_sources clkset_aclk_100 = { - .sources = clkset_aclk_top_list, - .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), -}; - static struct clksrc_clk clk_aclk_100 = { .clk = { .name = "aclk_100", .id = -1, }, - .sources = &clkset_aclk_100, + .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, }; -static struct clksrc_sources clkset_aclk_160 = { - .sources = clkset_aclk_top_list, - .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), -}; - static struct clksrc_clk clk_aclk_160 = { .clk = { .name = "aclk_160", .id = -1, }, - .sources = &clkset_aclk_160, + .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, }; -static struct clksrc_sources clkset_aclk_133 = { - .sources = clkset_aclk_top_list, - .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), -}; - static struct clksrc_clk clk_aclk_133 = { .clk = { .name = "aclk_133", .id = -1, }, - .sources = &clkset_aclk_133, + .sources = &clkset_aclk, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, }; -- cgit v1.1 From b99380e1047842de199089cc0945d5d9f0ff6a17 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Wed, 18 Aug 2010 22:16:45 +0900 Subject: ARM: S5PV310: Adds clk_sclk_usbphy0, _usbphy1, and _hdmiphy This patch adds struct clk clk_sclk_usbphy0, _usbphy1, and _hdmiphy for adding member of clkset_group_list. Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 20f3513..7b7199a 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -30,6 +30,22 @@ static struct clk clk_sclk_hdmi27m = { .rate = 27000000, }; +static struct clk clk_sclk_hdmiphy = { + .name = "sclk_hdmiphy", + .id = -1, +}; + +static struct clk clk_sclk_usbphy0 = { + .name = "sclk_usbphy0", + .id = -1, + .rate = 27000000, +}; + +static struct clk clk_sclk_usbphy1 = { + .name = "sclk_usbphy1", + .id = -1, +}; + static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); @@ -354,6 +370,9 @@ static struct clk *clkset_group_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, [6] = &clk_mout_mpll.clk, [7] = &clk_mout_epll.clk, [8] = &clk_sclk_vpll.clk, -- cgit v1.1 From 228ef9872b5c7e6fdb67a7a04547b33284242940 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Wed, 18 Aug 2010 22:24:53 +0900 Subject: ARM: S5PV310: Adds printing ACLK200, ACLK100, ACLK160 and ACLK133 This patch adds log messages of aclk_200, aclk_100, aclk_160, and aclk_133. And adds clk_p.rate from calculated aclk_100. Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 7b7199a..2c9424f 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -475,6 +475,10 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) unsigned long xtal; unsigned long armclk; unsigned long sclk_dmc; + unsigned long aclk_200; + unsigned long aclk_100; + unsigned long aclk_160; + unsigned long aclk_133; unsigned int ptr; printk(KERN_DEBUG "%s: registering clocks\n", __func__); @@ -507,10 +511,19 @@ void __init_or_cpufreq s5pv310_setup_clocks(void) armclk = clk_get_rate(&clk_armclk.clk); sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); - printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld\n", armclk, sclk_dmc); + aclk_200 = clk_get_rate(&clk_aclk_200.clk); + aclk_100 = clk_get_rate(&clk_aclk_100.clk); + aclk_160 = clk_get_rate(&clk_aclk_160.clk); + aclk_133 = clk_get_rate(&clk_aclk_133.clk); + + printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" + "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", + armclk, sclk_dmc, aclk_200, + aclk_100, aclk_160, aclk_133); clk_f.rate = armclk; clk_h.rate = sclk_dmc; + clk_p.rate = aclk_100; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); -- cgit v1.1 From 37e017292f56f3d39fb497d7fc9038967095e230 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Wed, 18 Aug 2010 22:33:43 +0900 Subject: ARM: S5PV310: Adds enable and ctrlbit for clk_vpllsrc This patch adds enable and ctrlbit for struct clksrc_clk clk_vpllsrc Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 2c9424f..a0bcd9f 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -46,6 +46,11 @@ static struct clk clk_sclk_usbphy1 = { .id = -1, }; +static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); +} + static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); @@ -298,6 +303,8 @@ static struct clksrc_clk clk_vpllsrc = { .clk = { .name = "vpll_src", .id = -1, + .enable = s5pv310_clksrc_mask_top_ctrl, + .ctrlbit = (1 << 0), }, .sources = &clkset_vpllsrc, .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, -- cgit v1.1 From 340ea1ef4b3d14d621f7a696341bf6cdf2bc188f Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Wed, 18 Aug 2010 22:39:26 +0900 Subject: ARM: S5PV310: Adds SDMMC clock for S5PV310 This patch adds SDMMC clocks for S5PV310/S5PC210. Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 142 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index a0bcd9f..eb087dd 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -51,11 +51,21 @@ static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); } +static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); +} + static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); } +static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); +} + static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); @@ -336,6 +346,36 @@ static struct clk init_clocks_disable[] = { .parent = &clk_aclk_100.clk, .enable = s5pv310_clk_ip_peril_ctrl, .ctrlbit = (1<<24), + }, { + .name = "hsmmc", + .id = 0, + .parent = &clk_aclk_133.clk, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "hsmmc", + .id = 1, + .parent = &clk_aclk_133.clk, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "hsmmc", + .id = 2, + .parent = &clk_aclk_133.clk, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "hsmmc", + .id = 3, + .parent = &clk_aclk_133.clk, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "hsmmc", + .id = 4, + .parent = &clk_aclk_133.clk, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 9), } }; @@ -390,6 +430,56 @@ static struct clksrc_sources clkset_group = { .nr_sources = ARRAY_SIZE(clkset_group_list), }; +static struct clksrc_clk clk_dout_mmc0 = { + .clk = { + .name = "dout_mmc0", + .id = -1, + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_dout_mmc1 = { + .clk = { + .name = "dout_mmc1", + .id = -1, + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_dout_mmc2 = { + .clk = { + .name = "dout_mmc2", + .id = -1, + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_dout_mmc3 = { + .clk = { + .name = "dout_mmc3", + .id = -1, + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_dout_mmc4 = { + .clk = { + .name = "dout_mmc4", + .id = -1, + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk clksrcs[] = { { .clk = { @@ -441,7 +531,52 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, - }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 0, + .parent = &clk_dout_mmc0.clk, + .enable = s5pv310_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 0), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 1, + .parent = &clk_dout_mmc1.clk, + .enable = s5pv310_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 4), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 2, + .parent = &clk_dout_mmc2.clk, + .enable = s5pv310_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 8), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 3, + .parent = &clk_dout_mmc3.clk, + .enable = s5pv310_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 12), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 4, + .parent = &clk_dout_mmc4.clk, + .enable = s5pv310_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, + } }; /* Clock initialization code */ @@ -469,6 +604,11 @@ static struct clksrc_clk *sysclks[] = { &clk_aclk_100, &clk_aclk_160, &clk_aclk_133, + &clk_dout_mmc0, + &clk_dout_mmc1, + &clk_dout_mmc2, + &clk_dout_mmc3, + &clk_dout_mmc4, }; void __init_or_cpufreq s5pv310_setup_clocks(void) -- cgit v1.1 From 82260bf38f36950f413ea6beb29717a3944752c3 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Wed, 18 Aug 2010 22:49:24 +0900 Subject: ARM: S5PV310: Add various clocks This patch adds various clocks for S5PV310/S5PC210. Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 160 +++++++++++++++++++++++- arch/arm/mach-s5pv310/include/mach/regs-clock.h | 1 + 2 files changed, 160 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index eb087dd..1f9ed85 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -61,6 +61,26 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); } +static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); +} + +static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); +} + +static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); +} + +static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); +} + static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); @@ -71,6 +91,11 @@ static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); } +static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); +} + /* Core list of CMU_CPU side */ static struct clksrc_clk clk_mout_apll = { @@ -347,6 +372,46 @@ static struct clk init_clocks_disable[] = { .enable = s5pv310_clk_ip_peril_ctrl, .ctrlbit = (1<<24), }, { + .name = "csis", + .id = 0, + .enable = s5pv310_clk_ip_cam_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "csis", + .id = 1, + .enable = s5pv310_clk_ip_cam_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "fimc", + .id = 0, + .enable = s5pv310_clk_ip_cam_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "fimc", + .id = 1, + .enable = s5pv310_clk_ip_cam_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "fimc", + .id = 2, + .enable = s5pv310_clk_ip_cam_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "fimc", + .id = 3, + .enable = s5pv310_clk_ip_cam_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "fimd", + .id = 0, + .enable = s5pv310_clk_ip_lcd0_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "fimd", + .id = 1, + .enable = s5pv310_clk_ip_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, { .name = "hsmmc", .id = 0, .parent = &clk_aclk_133.clk, @@ -376,7 +441,100 @@ static struct clk init_clocks_disable[] = { .parent = &clk_aclk_133.clk, .enable = s5pv310_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), - } + }, { + .name = "sata", + .id = -1, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "adc", + .id = -1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "watchdog", + .id = -1, + .enable = s5pv310_clk_ip_perir_ctrl, + .ctrlbit = (1 << 14), + }, { + .name = "usbhost", + .id = -1, + .enable = s5pv310_clk_ip_fsys_ctrl , + .ctrlbit = (1 << 12), + }, { + .name = "otg", + .id = -1, + .enable = s5pv310_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "spi", + .id = 0, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .id = 1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .id = 2, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 18), + }, { + .name = "fimg2d", + .id = -1, + .enable = s5pv310_clk_ip_image_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "i2c", + .id = 0, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "i2c", + .id = 1, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "i2c", + .id = 2, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "i2c", + .id = 3, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "i2c", + .id = 4, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "i2c", + .id = 5, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "i2c", + .id = 6, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "i2c", + .id = 7, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 13), + }, }; static struct clk init_clocks[] = { diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h index eda07fd..12e983c 100644 --- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h @@ -64,6 +64,7 @@ #define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) +#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) #define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) #define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) -- cgit v1.1 From 06cba8d5b64945c137c47065ca864a16a2d5710c Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Wed, 18 Aug 2010 22:51:23 +0900 Subject: ARM: S5PV310: Add video clocks This patch adds video clocks for S5PV310/S5PC210. Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 48 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 1f9ed85..b6ad76f 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -588,6 +588,54 @@ static struct clksrc_sources clkset_group = { .nr_sources = ARRAY_SIZE(clkset_group_list), }; +static struct clk *clkset_mout_g2d0_list[] = { + [0] = &clk_mout_mpll.clk, + [1] = &clk_sclk_apll.clk, +}; + +static struct clksrc_sources clkset_mout_g2d0 = { + .sources = clkset_mout_g2d0_list, + .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list), +}; + +static struct clksrc_clk clk_mout_g2d0 = { + .clk = { + .name = "mout_g2d0", + .id = -1, + }, + .sources = &clkset_mout_g2d0, + .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, +}; + +static struct clk *clkset_mout_g2d1_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_mout_g2d1 = { + .sources = clkset_mout_g2d1_list, + .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list), +}; + +static struct clksrc_clk clk_mout_g2d1 = { + .clk = { + .name = "mout_g2d1", + .id = -1, + }, + .sources = &clkset_mout_g2d1, + .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, +}; + +static struct clk *clkset_mout_g2d_list[] = { + [0] = &clk_mout_g2d0.clk, + [1] = &clk_mout_g2d1.clk, +}; + +static struct clksrc_sources clkset_mout_g2d = { + .sources = clkset_mout_g2d_list, + .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), +}; + static struct clksrc_clk clk_dout_mmc0 = { .clk = { .name = "dout_mmc0", -- cgit v1.1 From 33f469d2d9ea1e4bd29b6840ea73cf0ea2f1515c Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Wed, 18 Aug 2010 22:54:48 +0900 Subject: ARM: S5PV310: Adds various special clocks This patch adds various special clocks for S5PV310/S5PC210. Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 168 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index b6ad76f..262a46f 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -51,6 +51,21 @@ static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); } +static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); +} + +static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); +} + +static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); +} + static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); @@ -61,6 +76,11 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); } +static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); +} + static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); @@ -739,6 +759,154 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, }, { .clk = { + .name = "sclk_csis", + .id = 0, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "sclk_csis", + .id = 1, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 28), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam", + .id = 0, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam", + .id = 1, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 0, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 1, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 2, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 3, + .enable = s5pv310_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .id = 0, + .enable = s5pv310_clksrc_mask_lcd0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .id = 1, + .enable = s5pv310_clksrc_mask_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_sata", + .id = -1, + .enable = s5pv310_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_mout_corebus, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 0, + .enable = s5pv310_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 1, + .enable = s5pv310_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 2, + .enable = s5pv310_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimg2d", + .id = -1, + }, + .sources = &clkset_mout_g2d, + .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, + }, { + .clk = { .name = "sclk_mmc", .id = 0, .parent = &clk_dout_mmc0.clk, -- cgit v1.1 From eda9c023b1d6c986c7191de78ba3f09acf366c0f Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 20 Aug 2010 21:09:18 +0900 Subject: ARM: SAMSUNG: Change the 3rd HSMMC interrupt name for compatibility This patch changes the 3rd HSMMC interrupt name for compatibility from IRQ_MMC to IRQ_HSMMC3. Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/irqs.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index 471fc3b..7b4b09f 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -68,6 +68,11 @@ #define IRQ_IIC COMBINER_IRQ(27, 0) +#define IRQ_HSMMC0 COMBINER_IRQ(29, 0) +#define IRQ_HSMMC1 COMBINER_IRQ(29, 1) +#define IRQ_HSMMC2 COMBINER_IRQ(29, 2) +#define IRQ_HSMMC3 COMBINER_IRQ(29, 3) + #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) /* Set the default NR_IRQS */ -- cgit v1.1 From 8f3b9cff23ed15c1ef2f4e60c677f3c7d5e535ce Mon Sep 17 00:00:00 2001 From: Jaecheol Lee Date: Sat, 18 Sep 2010 10:50:46 +0900 Subject: ARM: S5PV310: Fix clkset_moutcore_list This patch fixes source clocks of moutcore. That should be clk_mout_apll instead of clk_sclk_apll. Signed-off-by: Jaecheol Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 262a46f..32146db 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -155,7 +155,7 @@ static struct clksrc_clk clk_mout_mpll = { }; static struct clk *clkset_moutcore_list[] = { - [0] = &clk_sclk_apll.clk, + [0] = &clk_mout_apll.clk, [1] = &clk_mout_mpll.clk, }; -- cgit v1.1 From cdff6e6fd2d4360e2d5bc39afe3f1ef17d79dbf0 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Mon, 20 Sep 2010 15:25:51 +0900 Subject: ARM: S5PV310: Add support RTC This patch adds support RTC for S5PV310 and S5PC210. Signed-off-by: Changhwan Youn Signed-off-by: Jemings Ko Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 2 ++ arch/arm/mach-s5pv310/clock.c | 5 +++++ arch/arm/mach-s5pv310/include/mach/irqs.h | 3 +++ arch/arm/mach-s5pv310/include/mach/map.h | 2 ++ arch/arm/mach-s5pv310/mach-smdkc210.c | 7 +++++++ arch/arm/mach-s5pv310/mach-smdkv310.c | 7 +++++++ 6 files changed, 26 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 9ac29fe..4de5d72 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -33,6 +33,7 @@ config MACH_SMDKC210 bool "SMDKC210" select CPU_S5PV310 select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_RTC help Machine support for Samsung SMDKC210 S5PC210(MCP) is one of package option of S5PV310 @@ -53,6 +54,7 @@ config MACH_SMDKV310 bool "SMDKV310" select CPU_S5PV310 select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_RTC help Machine support for Samsung SMDKV310 diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index 32146db..58c9d33 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c @@ -472,6 +472,11 @@ static struct clk init_clocks_disable[] = { .enable = s5pv310_clk_ip_peril_ctrl, .ctrlbit = (1 << 15), }, { + .name = "rtc", + .id = -1, + .enable = s5pv310_clk_ip_perir_ctrl, + .ctrlbit = (1 << 15), + }, { .name = "watchdog", .id = -1, .enable = s5pv310_clk_ip_perir_ctrl, diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index 7b4b09f..e81332f 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -60,6 +60,9 @@ #define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3) #define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4) +#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0) +#define IRQ_RTC_TIC COMBINER_IRQ(23, 1) + #define IRQ_UART0 COMBINER_IRQ(26, 0) #define IRQ_UART1 COMBINER_IRQ(26, 1) #define IRQ_UART2 COMBINER_IRQ(26, 2) diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index aff6d23..7523653 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -40,6 +40,7 @@ #define S5PV310_PA_CMU (0x10030000) #define S5PV310_PA_WATCHDOG (0x10060000) +#define S5PV310_PA_RTC (0x10070000) #define S5PV310_PA_COMBINER (0x10448000) @@ -81,6 +82,7 @@ #define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) #define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3) #define S3C_PA_IIC S5PV310_PA_IIC0 +#define S3C_PA_RTC S5PV310_PA_RTC #define S3C_PA_WDT S5PV310_PA_WATCHDOG #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index 656de01..9464084 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -65,6 +66,10 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = { }, }; +static struct platform_device *smdkc210_devices[] __initdata = { + &s3c_device_rtc, +}; + static void __init smdkc210_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -77,6 +82,8 @@ static void __init smdkc210_machine_init(void) #ifdef CONFIG_CACHE_L2X0 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); #endif + + platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); } MACHINE_START(SMDKC210, "SMDKC210") diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index 0d6ab77..06062c8 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -65,6 +66,10 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { }, }; +static struct platform_device *smdkv310_devices[] __initdata = { + &s3c_device_rtc, +}; + static void __init smdkv310_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -77,6 +82,8 @@ static void __init smdkv310_machine_init(void) #ifdef CONFIG_CACHE_L2X0 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); #endif + + platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); } MACHINE_START(SMDKV310, "SMDKV310") -- cgit v1.1 From 8d75c9128a07bd1f81952a518ed818d1a3e90c96 Mon Sep 17 00:00:00 2001 From: Jemings Ko Date: Mon, 20 Sep 2010 15:33:04 +0900 Subject: ARM: S5PV310: Add support Watchdog Timer This patch adds support Watchdog Timer for S5PV310 and S5PC210. Signed-off-by: Jemings Ko Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 2 ++ arch/arm/mach-s5pv310/mach-smdkc210.c | 1 + arch/arm/mach-s5pv310/mach-smdkv310.c | 1 + 3 files changed, 4 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 4de5d72..1d59ce9 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -34,6 +34,7 @@ config MACH_SMDKC210 select CPU_S5PV310 select ARCH_SPARSEMEM_ENABLE select S3C_DEV_RTC + select S3C_DEV_WDT help Machine support for Samsung SMDKC210 S5PC210(MCP) is one of package option of S5PV310 @@ -55,6 +56,7 @@ config MACH_SMDKV310 select CPU_S5PV310 select ARCH_SPARSEMEM_ENABLE select S3C_DEV_RTC + select S3C_DEV_WDT help Machine support for Samsung SMDKV310 diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index 9464084..b062397 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -68,6 +68,7 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = { static struct platform_device *smdkc210_devices[] __initdata = { &s3c_device_rtc, + &s3c_device_wdt, }; static void __init smdkc210_map_io(void) diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index 06062c8..9cb827d 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -68,6 +68,7 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_rtc, + &s3c_device_wdt, }; static void __init smdkv310_map_io(void) -- cgit v1.1 From 0c0f909689c8387265a3682d4205c063071ec36a Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Wed, 29 Sep 2010 20:31:42 +0900 Subject: ARM: S5PV310: Optimize interrupt source searching code It is reported by Junseok Jung that using clz instruction is better instead of using for-loop to find the interrupt source. This patch modifies interrupt source searching code using __ffs(). The __ffs() is implemented using clz instruction. Suggested-by: Junseok Jung Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/irq-combiner.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c index 0f70521..c3f88c3 100644 --- a/arch/arm/mach-s5pv310/irq-combiner.c +++ b/arch/arm/mach-s5pv310/irq-combiner.c @@ -66,11 +66,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) if (status == 0) goto out; - for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) { - if (status & 0x1) - break; - status >>= 1; - } + combiner_irq = __ffs(status); cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); if (unlikely(cascade_irq >= NR_IRQS)) -- cgit v1.1 From 1114275674787ac2f5f27f2c10368890d27fae1c Mon Sep 17 00:00:00 2001 From: Boojin Kim Date: Wed, 29 Sep 2010 20:42:15 +0900 Subject: ARM: S5PV310: Fix physical address of System Controller Register The physical address of SYSCON(System Controller) is wrong. This patch fixs this wrong physical address value from 0x10020000 to 0x10010000. Signed-off-by: Boojin Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/map.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 7523653..8014c3a 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -34,7 +34,7 @@ #define S5PV310_PA_CHIPID (0x10000000) #define S5P_PA_CHIPID S5PV310_PA_CHIPID -#define S5PV310_PA_SYSCON (0x10020000) +#define S5PV310_PA_SYSCON (0x10010000) #define S5P_PA_SYSCON S5PV310_PA_SYSCON #define S5PV310_PA_CMU (0x10030000) -- cgit v1.1 From f567fa6f62d263b50125b3321f43ba77c221dd82 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 29 Sep 2010 21:33:29 +0900 Subject: ARM: S5PV310: Place the common SPARSEMEM at ARCH_S5PV310 In case of S5PV310/S5PC210, it uses the SPARSEMEM as default memory configuration. So moved to ARCH_S5PV310 config. Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: edited title] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 1d59ce9..289f668 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -32,7 +32,6 @@ menu "S5PC210 Machines" config MACH_SMDKC210 bool "SMDKC210" select CPU_S5PV310 - select ARCH_SPARSEMEM_ENABLE select S3C_DEV_RTC select S3C_DEV_WDT help @@ -42,7 +41,6 @@ config MACH_SMDKC210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_S5PV310 - select ARCH_SPARSEMEM_ENABLE help Machine support for Samsung Mobile Universal S5PC210 Reference Board. S5PC210(MCP) is one of package option of S5PV310 @@ -54,7 +52,6 @@ menu "S5PV310 Machines" config MACH_SMDKV310 bool "SMDKV310" select CPU_S5PV310 - select ARCH_SPARSEMEM_ENABLE select S3C_DEV_RTC select S3C_DEV_WDT help -- cgit v1.1 From 398151e6fe25d3e223f79f060f73ac17c73acbfb Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 29 Sep 2010 21:37:50 +0900 Subject: ARM: S5P: Remove redundant selection PLAT_S5P for S5PC100, S5PV210 and S5PV310 The selection PLAT_S5P is selected with plat-s5p/Kconfig. So remove it form each CPU_S5PXXXX config. Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: edited title] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 289f668..9941852 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -11,7 +11,6 @@ if ARCH_S5PV310 config CPU_S5PV310 bool - select PLAT_S5P help Enable S5PV310 CPU support -- cgit v1.1 From ce5d3ac1f57b7a4ff28c57ebef709b8f9fd30fab Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 1 Oct 2010 16:05:07 +0900 Subject: ARM: S5PV310: Change to using s3c_gpio_cfgpin_range() This patch changes the code setting ranges of GPIO pins in mach-s5pv310 using s3c_gpio_cfgpin() to use the recently introduced s3c_gpio_cfgpin_range(). Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/setup-i2c0.c | 3 +-- arch/arm/mach-s5pv310/setup-i2c1.c | 3 +-- arch/arm/mach-s5pv310/setup-i2c2.c | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c index 4367128..17c54c8 100644 --- a/arch/arm/mach-s5pv310/setup-i2c0.c +++ b/arch/arm/mach-s5pv310/setup-i2c0.c @@ -21,8 +21,7 @@ struct platform_device; /* don't need the contents */ void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PV310_GPD1(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin_range(S5PV310_GPD1(0), 2, S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV310_GPD1(0), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV310_GPD1(1), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV310_GPD1(1), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-s5pv310/setup-i2c1.c index 1ecd5bc..1740c9f 100644 --- a/arch/arm/mach-s5pv310/setup-i2c1.c +++ b/arch/arm/mach-s5pv310/setup-i2c1.c @@ -18,8 +18,7 @@ struct platform_device; /* don't need the contents */ void s3c_i2c1_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PV310_GPD1(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin_range(S5PV310_GPD1(2), 2, S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV310_GPD1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV310_GPD1(3), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV310_GPD1(3), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-s5pv310/setup-i2c2.c index 4c0d8de..860f77b 100644 --- a/arch/arm/mach-s5pv310/setup-i2c2.c +++ b/arch/arm/mach-s5pv310/setup-i2c2.c @@ -18,8 +18,7 @@ struct platform_device; /* don't need the contents */ void s3c_i2c2_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PV310_GPA0(6), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin_range(S5PV310_GPA0(6), 2, S3C_GPIO_SFN(3)); s3c_gpio_setpull(S5PV310_GPA0(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV310_GPA0(7), S3C_GPIO_SFN(3)); s3c_gpio_setpull(S5PV310_GPA0(7), S3C_GPIO_PULL_UP); } -- cgit v1.1 From 861004657e7a5d29a1e1fd1c58967b4e6c0438b4 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 1 Oct 2010 19:32:27 +0900 Subject: ARM: S5PV310: Change to using s3c_gpio_cfgall_range() Change the code setting a range of GPIO pins' configuration and pull state to use the recently introduced s3c_gpio_cfgall_range(). Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/setup-i2c0.c | 5 ++--- arch/arm/mach-s5pv310/setup-i2c1.c | 5 ++--- arch/arm/mach-s5pv310/setup-i2c2.c | 5 ++--- 3 files changed, 6 insertions(+), 9 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c index 17c54c8..f47f8f3 100644 --- a/arch/arm/mach-s5pv310/setup-i2c0.c +++ b/arch/arm/mach-s5pv310/setup-i2c0.c @@ -21,7 +21,6 @@ struct platform_device; /* don't need the contents */ void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin_range(S5PV310_GPD1(0), 2, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV310_GPD1(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PV310_GPD1(1), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-s5pv310/setup-i2c1.c index 1740c9f..9d07e4e 100644 --- a/arch/arm/mach-s5pv310/setup-i2c1.c +++ b/arch/arm/mach-s5pv310/setup-i2c1.c @@ -18,7 +18,6 @@ struct platform_device; /* don't need the contents */ void s3c_i2c1_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin_range(S5PV310_GPD1(2), 2, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PV310_GPD1(2), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PV310_GPD1(3), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-s5pv310/setup-i2c2.c index 860f77b..4163b12 100644 --- a/arch/arm/mach-s5pv310/setup-i2c2.c +++ b/arch/arm/mach-s5pv310/setup-i2c2.c @@ -18,7 +18,6 @@ struct platform_device; /* don't need the contents */ void s3c_i2c2_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin_range(S5PV310_GPA0(6), 2, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(S5PV310_GPA0(6), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PV310_GPA0(7), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); } -- cgit v1.1 From 193151142b736f25882f250b6db3b02efd2d3cab Mon Sep 17 00:00:00 2001 From: Hyuk Lee Date: Wed, 6 Oct 2010 11:09:42 +0900 Subject: ARM: S5PV310: Add support HSMMC and SDHCI configuration This patch adds support HSMMC for S5PV310 and S5PC210 and setup for HSMMC host controller and also related GPIO. At most 4 channel can be used at the same time. A user can configure SDHCI data bus as 8bit or 4bit. Signed-off-by: Hyuk Lee Signed-off-by: Jeongbae Seo Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 39 ++++++++ arch/arm/mach-s5pv310/Makefile | 2 + arch/arm/mach-s5pv310/setup-sdhci-gpio.c | 152 +++++++++++++++++++++++++++++++ arch/arm/mach-s5pv310/setup-sdhci.c | 69 ++++++++++++++ 4 files changed, 262 insertions(+) create mode 100644 arch/arm/mach-s5pv310/setup-sdhci-gpio.c create mode 100644 arch/arm/mach-s5pv310/setup-sdhci.c (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 9941852..8cb3dc5 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -24,6 +24,17 @@ config S5PV310_SETUP_I2C2 help Common setup code for i2c bus 2. +config S5PV310_SETUP_SDHCI + bool + select S5PV310_SETUP_SDHCI_GPIO + help + Internal helper functions for S5PV310 based SDHCI systems. + +config S5PV310_SETUP_SDHCI_GPIO + bool + help + Common setup code for SDHCI gpio. + # machine support menu "S5PC210 Machines" @@ -33,6 +44,11 @@ config MACH_SMDKC210 select CPU_S5PV310 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S5PV310_SETUP_SDHCI help Machine support for Samsung SMDKC210 S5PC210(MCP) is one of package option of S5PV310 @@ -53,9 +69,32 @@ config MACH_SMDKV310 select CPU_S5PV310 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S5PV310_SETUP_SDHCI help Machine support for Samsung SMDKV310 endmenu +comment "Configuration for HSMMC bus width" + +menu "Use 8-bit bus width" + +config S5PV310_SDHCI_CH0_8BIT + bool "Channel 0 with 8-bit bus" + help + Support HSMMC Channel 0 8-bit bus. + If selected, Channel 1 is disabled. + +config S5PV310_SDHCI_CH2_8BIT + bool "Channel 2 with 8-bit bus" + help + Support HSMMC Channel 2 8-bit bus. + If selected, Channel 3 is disabled. + +endmenu + endif diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index aefb14f..c89b6b0 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -29,3 +29,5 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o +obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o +obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c new file mode 100644 index 0000000..86d38cc --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c @@ -0,0 +1,152 @@ +/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK0[0:1] pins to special-function 2 */ + for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + switch (width) { + case 8: + for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { + /* Data pin GPK1[3:6] to special-funtion 3 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + case 4: + for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) { + /* Data pin GPK0[3:6] to special-funtion 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + default: + break; + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK1[0:1] pins to special-function 2 */ + for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { + /* Data pin GPK1[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK2[0:1] pins to special-function 2 */ + for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + switch (width) { + case 8: + for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { + /* Data pin GPK3[3:6] to special-function 3 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + case 4: + for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) { + /* Data pin GPK2[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + default: + break; + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} + +void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPK3[0:1] pins to special-function 2 */ + for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { + /* Data pin GPK3[3:6] to special-function 2 */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c new file mode 100644 index 0000000..db8358f --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-sdhci.c @@ -0,0 +1,69 @@ +/* linux/arch/arm/mach-s5pv310/setup-sdhci.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *s5pv310_hsmmc_clksrcs[4] = { + [0] = NULL, + [1] = NULL, + [2] = "sclk_mmc", /* mmc_bus */ + [3] = NULL, +}; + +void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, + struct mmc_ios *ios, struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + /* don't need to alter anything acording to card-type */ + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + + /* select base clock source to HCLK */ + + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + + /* + * clear async mode, enable conflict mask, rx feedback ctrl, SD + * clk hold and no use debounce count + */ + + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + /* Tx and Rx feedback clock delay control */ + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} -- cgit v1.1 From 1036c3ab6045ccf21b23427081c7b5d4149142dd Mon Sep 17 00:00:00 2001 From: Hyuk Lee Date: Tue, 5 Oct 2010 19:07:41 +0900 Subject: ARM: S5PV310: Add HSMMC platform data This patch adds initialization HSMMC device information. And HSMMC platform data like card detect, data bus width and capability is configured. Signed-off-by: Hyuk Lee Signed-off-by: Jeongbae Seo Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 4add398..66beac4 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -83,6 +84,12 @@ static void s5pv310_idle(void) void __init s5pv310_map_io(void) { iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc)); + + /* initialize device information early */ + s5pv310_default_sdhci0(); + s5pv310_default_sdhci1(); + s5pv310_default_sdhci2(); + s5pv310_default_sdhci3(); } void __init s5pv310_init_clocks(int xtal) -- cgit v1.1 From 2b11148a80bf1a022e8165ae0026bf6ff5778f03 Mon Sep 17 00:00:00 2001 From: Hyuk Lee Date: Wed, 6 Oct 2010 14:50:20 +0900 Subject: ARM: S5PV310: Add support HSMMC on SMDKV310 and SMDKC210 This patch adds support HSMMC for S5PV310(SMDKV310) and S5PC210(SMDKC210). Signed-off-by: Hyuk Lee Signed-off-by: Jeongbae Seo Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/mach-smdkc210.c | 45 +++++++++++++++++++++++++++++++++++ arch/arm/mach-s5pv310/mach-smdkv310.c | 45 +++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index b062397..da5e7e7 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -9,6 +9,9 @@ */ #include +#include +#include +#include #include #include @@ -18,6 +21,7 @@ #include #include #include +#include #include @@ -66,7 +70,43 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = { }, }; +static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK0(2), + .ext_cd_gpio_invert = 1, +#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK0(2), + .ext_cd_gpio_invert = 1, +}; + +static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK2(2), + .ext_cd_gpio_invert = 1, +#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK2(2), + .ext_cd_gpio_invert = 1, +}; + static struct platform_device *smdkc210_devices[] __initdata = { + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, &s3c_device_rtc, &s3c_device_wdt, }; @@ -80,6 +120,11 @@ static void __init smdkc210_map_io(void) static void __init smdkc210_machine_init(void) { + s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata); + s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata); + s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); + s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); + #ifdef CONFIG_CACHE_L2X0 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); #endif diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index 9cb827d..6eff6ce 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -9,6 +9,9 @@ */ #include +#include +#include +#include #include #include @@ -18,6 +21,7 @@ #include #include #include +#include #include @@ -66,7 +70,43 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { }, }; +static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK0(2), + .ext_cd_gpio_invert = 1, +#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK0(2), + .ext_cd_gpio_invert = 1, +}; + +static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK2(2), + .ext_cd_gpio_invert = 1, +#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = S5PV310_GPK2(2), + .ext_cd_gpio_invert = 1, +}; + static struct platform_device *smdkv310_devices[] __initdata = { + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, &s3c_device_rtc, &s3c_device_wdt, }; @@ -80,6 +120,11 @@ static void __init smdkv310_map_io(void) static void __init smdkv310_machine_init(void) { + s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); + s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata); + s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); + s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); + #ifdef CONFIG_CACHE_L2X0 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); #endif -- cgit v1.1 From 28c80aa707156d83f679442ea745db301316a4ea Mon Sep 17 00:00:00 2001 From: Jeongbae Seo Date: Fri, 8 Oct 2010 18:03:27 +0900 Subject: ARM: SAMSUNG: Add clock types into platform data This patch adds clock types into platform data to support external clock divider instead of internal clock divider. It is defined that what kinds of clock type is used in machine. Signed-off-by: Jeongbae Seo Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/mach-smdkc210.c | 4 ++++ arch/arm/mach-s5pv310/mach-smdkv310.c | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index da5e7e7..93d537b 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -74,6 +74,7 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK0(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -84,12 +85,14 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK0(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK2(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -100,6 +103,7 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK2(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct platform_device *smdkc210_devices[] __initdata = { diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index 6eff6ce..10f8056 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -74,6 +74,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK0(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -84,12 +85,14 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK0(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK2(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, #ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, @@ -100,6 +103,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = S5PV310_GPK2(2), .ext_cd_gpio_invert = 1, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; static struct platform_device *smdkv310_devices[] __initdata = { -- cgit v1.1 From acf5eda92da23c904d1e37ba80c75572f3e2c860 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Fri, 8 Oct 2010 22:34:52 +0900 Subject: ARM: S5PV310: Universal OneNAND support OneNAND device support for Universal board. Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: minor title fixes] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 1 + arch/arm/mach-s5pv310/mach-universal_c210.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 8cb3dc5..6b2b948 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -56,6 +56,7 @@ config MACH_SMDKC210 config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_S5PV310 + select S5P_DEV_ONENAND help Machine support for Samsung Mobile Universal S5PC210 Reference Board. S5PC210(MCP) is one of package option of S5PV310 diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c index b57efae..e169849 100644 --- a/arch/arm/mach-s5pv310/mach-universal_c210.c +++ b/arch/arm/mach-s5pv310/mach-universal_c210.c @@ -20,6 +20,7 @@ #include #include #include +#include #include @@ -117,6 +118,7 @@ static struct platform_device universal_gpio_keys = { static struct platform_device *universal_devices[] __initdata = { &universal_gpio_keys, + &s5p_device_onenand, }; static void __init universal_map_io(void) -- cgit v1.1 From 3b7998f529a18696baafb8cca63a7720565ad77f Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Fri, 8 Oct 2010 22:34:56 +0900 Subject: ARM: S5PV310: I2C0/1 devices support on Universal board Camera devices use the I2C0 and Gyro uese the I2C1 on universal board. Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: minor title fixes] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 2 ++ arch/arm/mach-s5pv310/mach-universal_c210.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index 6b2b948..f12f560 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -57,6 +57,8 @@ config MACH_UNIVERSAL_C210 bool "Mobile UNIVERSAL_C210 Board" select CPU_S5PV310 select S5P_DEV_ONENAND + select S3C_DEV_I2C1 + select S5PV310_SETUP_I2C1 help Machine support for Samsung Mobile Universal S5PC210 Reference Board. S5PC210(MCP) is one of package option of S5PV310 diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c index e169849..deffeb1 100644 --- a/arch/arm/mach-s5pv310/mach-universal_c210.c +++ b/arch/arm/mach-s5pv310/mach-universal_c210.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -116,6 +117,16 @@ static struct platform_device universal_gpio_keys = { }, }; +/* I2C0 */ +static struct i2c_board_info i2c0_devs[] __initdata = { + /* Camera, To be updated */ +}; + +/* I2C1 */ +static struct i2c_board_info i2c1_devs[] __initdata = { + /* Gyro, To be updated */ +}; + static struct platform_device *universal_devices[] __initdata = { &universal_gpio_keys, &s5p_device_onenand, @@ -134,6 +145,9 @@ static void __init universal_machine_init(void) l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); #endif + i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); + i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); + /* Last */ platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); } -- cgit v1.1 From 8a3710dfbfb9f2712e3df3861ee7d0e8573be943 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 12 Oct 2010 07:49:20 +0900 Subject: ARM: S5PV310: Define address & interrupt for all I2C blocks S5PV310 and S5PC210 support total 8 (+ 1 dedicated for HDMI) I2C devices. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/irqs.h | 7 +++++++ arch/arm/mach-s5pv310/include/mach/map.h | 11 +++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index e81332f..b2acc62 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -70,6 +70,13 @@ #define IRQ_UART4 COMBINER_IRQ(26, 4) #define IRQ_IIC COMBINER_IRQ(27, 0) +#define IRQ_IIC1 COMBINER_IRQ(27, 1) +#define IRQ_IIC2 COMBINER_IRQ(27, 2) +#define IRQ_IIC3 COMBINER_IRQ(27, 3) +#define IRQ_IIC4 COMBINER_IRQ(27, 4) +#define IRQ_IIC5 COMBINER_IRQ(27, 5) +#define IRQ_IIC6 COMBINER_IRQ(27, 6) +#define IRQ_IIC7 COMBINER_IRQ(27, 7) #define IRQ_HSMMC0 COMBINER_IRQ(29, 0) #define IRQ_HSMMC1 COMBINER_IRQ(29, 1) diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 8014c3a..1e3384f 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -67,7 +67,7 @@ #define S5P_SZ_UART SZ_256 -#define S5PV310_PA_IIC0 (0x13860000) +#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) #define S5PV310_PA_TIMER (0x139D0000) #define S5P_PA_TIMER S5PV310_PA_TIMER @@ -81,7 +81,14 @@ #define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) #define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) #define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3) -#define S3C_PA_IIC S5PV310_PA_IIC0 +#define S3C_PA_IIC S5PV310_PA_IIC(0) +#define S3C_PA_IIC1 S5PV310_PA_IIC(1) +#define S3C_PA_IIC2 S5PV310_PA_IIC(2) +#define S3C_PA_IIC3 S5PV310_PA_IIC(3) +#define S3C_PA_IIC4 S5PV310_PA_IIC(4) +#define S3C_PA_IIC5 S5PV310_PA_IIC(5) +#define S3C_PA_IIC6 S5PV310_PA_IIC(6) +#define S3C_PA_IIC7 S5PV310_PA_IIC(7) #define S3C_PA_RTC S5PV310_PA_RTC #define S3C_PA_WDT S5PV310_PA_WATCHDOG -- cgit v1.1 From b7a9825553e9213e5129f7e8e53065e918981a70 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 12 Oct 2010 07:49:24 +0900 Subject: ARM: S5PV310: Add I2C channel 3, 4, 5, 6, and 7 device support S5PV310 and S5PC210 support more I2C devices than previous SoCs. Add the device support code for them. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Kconfig | 25 +++++++++++++++++++++++++ arch/arm/mach-s5pv310/Makefile | 5 +++++ arch/arm/mach-s5pv310/setup-i2c3.c | 23 +++++++++++++++++++++++ arch/arm/mach-s5pv310/setup-i2c4.c | 23 +++++++++++++++++++++++ arch/arm/mach-s5pv310/setup-i2c5.c | 23 +++++++++++++++++++++++ arch/arm/mach-s5pv310/setup-i2c6.c | 23 +++++++++++++++++++++++ arch/arm/mach-s5pv310/setup-i2c7.c | 23 +++++++++++++++++++++++ 7 files changed, 145 insertions(+) create mode 100644 arch/arm/mach-s5pv310/setup-i2c3.c create mode 100644 arch/arm/mach-s5pv310/setup-i2c4.c create mode 100644 arch/arm/mach-s5pv310/setup-i2c5.c create mode 100644 arch/arm/mach-s5pv310/setup-i2c6.c create mode 100644 arch/arm/mach-s5pv310/setup-i2c7.c (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig index f12f560..1150b36 100644 --- a/arch/arm/mach-s5pv310/Kconfig +++ b/arch/arm/mach-s5pv310/Kconfig @@ -24,6 +24,31 @@ config S5PV310_SETUP_I2C2 help Common setup code for i2c bus 2. +config S5PV310_SETUP_I2C3 + bool + help + Common setup code for i2c bus 3. + +config S5PV310_SETUP_I2C4 + bool + help + Common setup code for i2c bus 4. + +config S5PV310_SETUP_I2C5 + bool + help + Common setup code for i2c bus 5. + +config S5PV310_SETUP_I2C6 + bool + help + Common setup code for i2c bus 6. + +config S5PV310_SETUP_I2C7 + bool + help + Common setup code for i2c bus 7. + config S5PV310_SETUP_SDHCI bool select S5PV310_SETUP_SDHCI_GPIO diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index c89b6b0..425cdd6 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -29,5 +29,10 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o +obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o +obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o +obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o +obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o +obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-s5pv310/setup-i2c3.c new file mode 100644 index 0000000..180f153 --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c3.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c3.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C3 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c3_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-s5pv310/setup-i2c4.c new file mode 100644 index 0000000..909e8df --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c4.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c4.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C4 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c4_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S5PV310_GPB(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-s5pv310/setup-i2c5.c new file mode 100644 index 0000000..5d0fa4a --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c5.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c5.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C5 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c5_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S5PV310_GPB(6), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-s5pv310/setup-i2c6.c new file mode 100644 index 0000000..34aafab --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c6.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c6.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C6 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c6_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2, + S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-s5pv310/setup-i2c7.c new file mode 100644 index 0000000..9b25b8d --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c7.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c7.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * I2C7 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include +#include +#include + +void s3c_i2c7_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +} -- cgit v1.1 From d4b34c6c849d67b7afaa90d55dc7fab981c72950 Mon Sep 17 00:00:00 2001 From: Seungwhan Youn Date: Thu, 14 Oct 2010 10:39:08 +0900 Subject: ARM: S5P: Reduce duplicated EPLL control codes S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn Acked-by: Jassi Brar Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/regs-clock.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h index 12e983c..f1028ca 100644 --- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h @@ -84,4 +84,8 @@ #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) +/* Compatibility defines */ + +#define S5P_EPLL_CON S5P_EPLL_CON0 + #endif /* __ASM_ARCH_REGS_CLOCK_H */ -- cgit v1.1 From 3e7d5e5a4aa7960e977a0434c1203eaff2ac44a4 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Thu, 14 Oct 2010 10:51:10 +0900 Subject: ARM: S5PV310: Update MAX_COMBINER_NR This patch updates MAX_COMBINER_NR from 39 to 40 because S5PV310 need 39th combiner for including EINT16_31. Signed-off-by: Jongpill Lee Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/irqs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index b2acc62..f301af7 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -89,6 +89,6 @@ #define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) -#define MAX_COMBINER_NR 39 +#define MAX_COMBINER_NR 40 #endif /* __ASM_ARCH_IRQS_H */ -- cgit v1.1 From 37ea63b14bec667957ca3cfaa899c6e103fdb854 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Thu, 14 Oct 2010 15:46:18 +0900 Subject: ARM: S5P: Add initial map for GPIO2 and GPIO3 This patch adds initial map for GPIO2 and GPIO3. S5PV310/S5PC210 has separated GPIO1, GPIO2 and GPIO3. Signed-off-by: Jongpill Lee Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 66beac4..5b97900 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -57,11 +57,21 @@ static struct map_desc s5pv310_iodesc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_GPIO, + .virtual = (unsigned long)S5P_VA_GPIO1, .pfn = __phys_to_pfn(S5PV310_PA_GPIO1), .length = SZ_4K, .type = MT_DEVICE, }, { + .virtual = (unsigned long)S5P_VA_GPIO2, + .pfn = __phys_to_pfn(S5PV310_PA_GPIO2), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GPIO3, + .pfn = __phys_to_pfn(S5PV310_PA_GPIO3), + .length = SZ_256, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)S3C_VA_UART, .pfn = __phys_to_pfn(S3C_PA_UART), .length = SZ_512K, -- cgit v1.1 From d2e7eca36dde5ee8979362bed5b27e47b37e94a0 Mon Sep 17 00:00:00 2001 From: Jongpill Lee Date: Thu, 14 Oct 2010 15:52:16 +0900 Subject: ARM: S5PV310: Add support GPIOlib This patch adds GPIOlib support for S5PV310 and S5PC210. Signed-off-by: Jongpill Lee Signed-off-by: Sangbeom Kim [kgene.kim@samsung.com: Fix NR_IRQS] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Makefile | 2 +- arch/arm/mach-s5pv310/gpiolib.c | 304 ++++++++++++++++++++++++++++++ arch/arm/mach-s5pv310/include/mach/irqs.h | 13 +- 3 files changed, 314 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-s5pv310/gpiolib.c (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index 425cdd6..ac3b4c1 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -13,7 +13,7 @@ obj- := # Core support for S5PV310 system obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o -obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o +obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-s5pv310/gpiolib.c new file mode 100644 index 0000000..55217b8 --- /dev/null +++ b/arch/arm/mach-s5pv310/gpiolib.c @@ -0,0 +1,304 @@ +/* linux/arch/arm/mach-s5pv310/gpiolib.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include + +#include +#include +#include + +static struct s3c_gpio_cfg gpio_cfg = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +/* + * Following are the gpio banks in v310. + * + * The 'config' member when left to NULL, is initialized to the default + * structure gpio_cfg in the init function below. + * + * The 'base' member is also initialized in the init function below. + * Note: The initialization of 'base' member of s3c_gpio_chip structure + * uses the above macro and depends on the banks being listed in order here. + */ +static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = { + { + .chip = { + .base = S5PV310_GPA0(0), + .ngpio = S5PV310_GPIO_A0_NR, + .label = "GPA0", + }, + }, { + .chip = { + .base = S5PV310_GPA1(0), + .ngpio = S5PV310_GPIO_A1_NR, + .label = "GPA1", + }, + }, { + .chip = { + .base = S5PV310_GPB(0), + .ngpio = S5PV310_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S5PV310_GPC0(0), + .ngpio = S5PV310_GPIO_C0_NR, + .label = "GPC0", + }, + }, { + .chip = { + .base = S5PV310_GPC1(0), + .ngpio = S5PV310_GPIO_C1_NR, + .label = "GPC1", + }, + }, { + .chip = { + .base = S5PV310_GPD0(0), + .ngpio = S5PV310_GPIO_D0_NR, + .label = "GPD0", + }, + }, { + .chip = { + .base = S5PV310_GPD1(0), + .ngpio = S5PV310_GPIO_D1_NR, + .label = "GPD1", + }, + }, { + .chip = { + .base = S5PV310_GPE0(0), + .ngpio = S5PV310_GPIO_E0_NR, + .label = "GPE0", + }, + }, { + .chip = { + .base = S5PV310_GPE1(0), + .ngpio = S5PV310_GPIO_E1_NR, + .label = "GPE1", + }, + }, { + .chip = { + .base = S5PV310_GPE2(0), + .ngpio = S5PV310_GPIO_E2_NR, + .label = "GPE2", + }, + }, { + .chip = { + .base = S5PV310_GPE3(0), + .ngpio = S5PV310_GPIO_E3_NR, + .label = "GPE3", + }, + }, { + .chip = { + .base = S5PV310_GPE4(0), + .ngpio = S5PV310_GPIO_E4_NR, + .label = "GPE4", + }, + }, { + .chip = { + .base = S5PV310_GPF0(0), + .ngpio = S5PV310_GPIO_F0_NR, + .label = "GPF0", + }, + }, { + .chip = { + .base = S5PV310_GPF1(0), + .ngpio = S5PV310_GPIO_F1_NR, + .label = "GPF1", + }, + }, { + .chip = { + .base = S5PV310_GPF2(0), + .ngpio = S5PV310_GPIO_F2_NR, + .label = "GPF2", + }, + }, { + .chip = { + .base = S5PV310_GPF3(0), + .ngpio = S5PV310_GPIO_F3_NR, + .label = "GPF3", + }, + }, +}; + +static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { + { + .chip = { + .base = S5PV310_GPJ0(0), + .ngpio = S5PV310_GPIO_J0_NR, + .label = "GPJ0", + }, + }, { + .chip = { + .base = S5PV310_GPJ1(0), + .ngpio = S5PV310_GPIO_J1_NR, + .label = "GPJ1", + }, + }, { + .chip = { + .base = S5PV310_GPK0(0), + .ngpio = S5PV310_GPIO_K0_NR, + .label = "GPK0", + }, + }, { + .chip = { + .base = S5PV310_GPK1(0), + .ngpio = S5PV310_GPIO_K1_NR, + .label = "GPK1", + }, + }, { + .chip = { + .base = S5PV310_GPK2(0), + .ngpio = S5PV310_GPIO_K2_NR, + .label = "GPK2", + }, + }, { + .chip = { + .base = S5PV310_GPK3(0), + .ngpio = S5PV310_GPIO_K3_NR, + .label = "GPK3", + }, + }, { + .chip = { + .base = S5PV310_GPL0(0), + .ngpio = S5PV310_GPIO_L0_NR, + .label = "GPL0", + }, + }, { + .chip = { + .base = S5PV310_GPL1(0), + .ngpio = S5PV310_GPIO_L1_NR, + .label = "GPL1", + }, + }, { + .chip = { + .base = S5PV310_GPL2(0), + .ngpio = S5PV310_GPIO_L2_NR, + .label = "GPL2", + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC00), + .config = &gpio_cfg_noint, + .irq_base = IRQ_EINT(0), + .chip = { + .base = S5PV310_GPX0(0), + .ngpio = S5PV310_GPIO_X0_NR, + .label = "GPX0", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC20), + .config = &gpio_cfg_noint, + .irq_base = IRQ_EINT(8), + .chip = { + .base = S5PV310_GPX1(0), + .ngpio = S5PV310_GPIO_X1_NR, + .label = "GPX1", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC40), + .config = &gpio_cfg_noint, + .irq_base = IRQ_EINT(16), + .chip = { + .base = S5PV310_GPX2(0), + .ngpio = S5PV310_GPIO_X2_NR, + .label = "GPX2", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC60), + .config = &gpio_cfg_noint, + .irq_base = IRQ_EINT(24), + .chip = { + .base = S5PV310_GPX3(0), + .ngpio = S5PV310_GPIO_X3_NR, + .label = "GPX3", + .to_irq = samsung_gpiolib_to_irq, + }, + }, +}; + +static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = { + { + .chip = { + .base = S5PV310_GPZ(0), + .ngpio = S5PV310_GPIO_Z_NR, + .label = "GPZ", + }, + }, +}; + +static __init int s5pv310_gpiolib_init(void) +{ + struct s3c_gpio_chip *chip; + int i; + int nr_chips; + + /* GPIO part 1 */ + + chip = s5pv310_gpio_part1_4bit; + nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit); + + for (i = 0; i < nr_chips; i++, chip++) { + if (chip->config == NULL) + chip->config = &gpio_cfg; + if (chip->base == NULL) + chip->base = S5P_VA_GPIO1 + (i) * 0x20; + } + + samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips); + + /* GPIO part 2 */ + + chip = s5pv310_gpio_part2_4bit; + nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit); + + for (i = 0; i < nr_chips; i++, chip++) { + if (chip->config == NULL) + chip->config = &gpio_cfg; + if (chip->base == NULL) + chip->base = S5P_VA_GPIO2 + (i) * 0x20; + } + + samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips); + + /* GPIO part 3 */ + + chip = s5pv310_gpio_part3_4bit; + nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit); + + for (i = 0; i < nr_chips; i++, chip++) { + if (chip->config == NULL) + chip->config = &gpio_cfg; + if (chip->base == NULL) + chip->base = S5P_VA_GPIO3 + (i) * 0x20; + } + + samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips); + + return 0; +} +core_initcall(s5pv310_gpiolib_init); diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index f301af7..fa7a8a3 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -3,7 +3,7 @@ * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * - * S5PV210 - IRQ definitions + * S5PV310 - IRQ definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -85,10 +85,15 @@ #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) -/* Set the default NR_IRQS */ +#define MAX_COMBINER_NR 40 -#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) +#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) -#define MAX_COMBINER_NR 40 +#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) +#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) + +/* Set the default NR_IRQS */ + +#define NR_IRQS (S5P_IRQ_EINT_BASE + 32) #endif /* __ASM_ARCH_IRQS_H */ -- cgit v1.1 From 57c1f8713605489b3d4914f68a96564858d7c91d Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Thu, 21 Oct 2010 16:28:20 +0900 Subject: ARM: S5PV310: Remove L2 cache init in machine Basically, need L2 cache initialize function in ARCH_S5PV310. So it would be better to move it into ARCH_S5PV310 common part. This patch removes L2 cache initialization code at the each board file. Signed-off-by: Kyungmin Park Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/mach-smdkc210.c | 5 ----- arch/arm/mach-s5pv310/mach-smdkv310.c | 5 ----- arch/arm/mach-s5pv310/mach-universal_c210.c | 5 ----- 3 files changed, 15 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index 93d537b..9f7f77d 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -15,7 +15,6 @@ #include #include -#include #include #include @@ -129,10 +128,6 @@ static void __init smdkc210_machine_init(void) s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); -#ifdef CONFIG_CACHE_L2X0 - l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); -#endif - platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); } diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index 10f8056..e350a75 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -15,7 +15,6 @@ #include #include -#include #include #include @@ -129,10 +128,6 @@ static void __init smdkv310_machine_init(void) s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); -#ifdef CONFIG_CACHE_L2X0 - l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); -#endif - platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); } diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c index deffeb1..9ea7836 100644 --- a/arch/arm/mach-s5pv310/mach-universal_c210.c +++ b/arch/arm/mach-s5pv310/mach-universal_c210.c @@ -16,7 +16,6 @@ #include #include -#include #include #include @@ -141,10 +140,6 @@ static void __init universal_map_io(void) static void __init universal_machine_init(void) { -#ifdef CONFIG_CACHE_L2X0 - l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); -#endif - i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); -- cgit v1.1 From 1cf0eb799759b24199374955976fee8469835203 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Thu, 21 Oct 2010 15:22:36 +0900 Subject: ARM: S5PV310: Add L2 cache init function in cpu.c This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310. It includes TAG and Data latency, Prefetch, and Power configurations. Signed-off-by: Kyungmin Park Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 5b97900..4e3f5be 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -148,6 +149,28 @@ static int __init s5pv310_core_init(void) core_initcall(s5pv310_core_init); +#ifdef CONFIG_CACHE_L2X0 +static int __init s5pv310_l2x0_cache_init(void) +{ + /* TAG, Data Latency Control: 2cycle */ + __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + + /* L2X0 Prefetch Control */ + __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff); + + return 0; +} + +early_initcall(s5pv310_l2x0_cache_init); +#endif + int __init s5pv310_init(void) { printk(KERN_INFO "S5PV310: Initializing architecture\n"); -- cgit v1.1 From 40c9bc5c3cf6a6742485f282feed5c7e3839e2d9 Mon Sep 17 00:00:00 2001 From: Jongsun Han Date: Thu, 21 Oct 2010 15:59:20 +0900 Subject: ARM: S5PV310: Add the definition for external interrupt This patch adds the definition for both IRQs and GPIO registers for external interrupts. Signed-off-by: Jongsun Han Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/irqs.h | 16 ++++++++++ arch/arm/mach-s5pv310/include/mach/regs-gpio.h | 42 ++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-gpio.h (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index fa7a8a3..99e7dad 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -85,6 +85,22 @@ #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) +#define IRQ_EINT4 COMBINER_IRQ(37, 0) +#define IRQ_EINT5 COMBINER_IRQ(37, 1) +#define IRQ_EINT6 COMBINER_IRQ(37, 2) +#define IRQ_EINT7 COMBINER_IRQ(37, 3) +#define IRQ_EINT8 COMBINER_IRQ(38, 0) + +#define IRQ_EINT9 COMBINER_IRQ(38, 1) +#define IRQ_EINT10 COMBINER_IRQ(38, 2) +#define IRQ_EINT11 COMBINER_IRQ(38, 3) +#define IRQ_EINT12 COMBINER_IRQ(38, 4) +#define IRQ_EINT13 COMBINER_IRQ(38, 5) +#define IRQ_EINT14 COMBINER_IRQ(38, 6) +#define IRQ_EINT15 COMBINER_IRQ(38, 7) + +#define IRQ_EINT16_31 COMBINER_IRQ(39, 0) + #define MAX_COMBINER_NR 40 #define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h new file mode 100644 index 0000000..82e9e0c --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h @@ -0,0 +1,42 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - GPIO (including EINT) register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_GPIO_H +#define __ASM_ARCH_REGS_GPIO_H __FILE__ + +#include +#include + +#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00) +#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4)) + +#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80) +#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4)) + +#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00) +#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4)) + +#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40) +#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4)) + +#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) + +#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) + +#define EINT_MODE S3C_GPIO_SFN(0xf) + +#define EINT_GPIO_0(x) S5PV310_GPX0(x) +#define EINT_GPIO_1(x) S5PV310_GPX1(x) +#define EINT_GPIO_2(x) S5PV310_GPX2(x) +#define EINT_GPIO_3(x) S5PV310_GPX3(x) + +#endif /* __ASM_ARCH_REGS_GPIO_H */ -- cgit v1.1 From d8bb31e68f618ad10ea1088a9e9dd426d5e54bfc Mon Sep 17 00:00:00 2001 From: Jongsun Han Date: Thu, 21 Oct 2010 15:18:55 +0900 Subject: ARM: S5PV310: Add support External Interrupt This patch adds EINT(External Interrupt) support on S5PV310 and S5PC210. All EINTs are transferred to GIC through interrupt combiner. Signed-off-by: Jongsun Han Signed-off-by: Jongpill Lee Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/Makefile | 2 +- arch/arm/mach-s5pv310/irq-eint.c | 228 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 229 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-s5pv310/irq-eint.c (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile index ac3b4c1..84afc64 100644 --- a/arch/arm/mach-s5pv310/Makefile +++ b/arch/arm/mach-s5pv310/Makefile @@ -13,7 +13,7 @@ obj- := # Core support for S5PV310 system obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o -obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o +obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c new file mode 100644 index 0000000..5877503 --- /dev/null +++ b/arch/arm/mach-s5pv310/irq-eint.c @@ -0,0 +1,228 @@ +/* linux/arch/arm/mach-s5pv310/irq-eint.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - IRQ EINT support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +static DEFINE_SPINLOCK(eint_lock); + +static unsigned int eint0_15_data[16]; + +static unsigned int s5pv310_get_irq_nr(unsigned int number) +{ + u32 ret = 0; + + switch (number) { + case 0 ... 3: + ret = (number + IRQ_EINT0); + break; + case 4 ... 7: + ret = (number + (IRQ_EINT4 - 4)); + break; + case 8 ... 15: + ret = (number + (IRQ_EINT8 - 8)); + break; + default: + printk(KERN_ERR "number available : %d\n", number); + } + + return ret; +} + +static inline void s5pv310_irq_eint_mask(unsigned int irq) +{ + u32 mask; + + spin_lock(&eint_lock); + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); + mask |= eint_irq_to_bit(irq); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); + spin_unlock(&eint_lock); +} + +static void s5pv310_irq_eint_unmask(unsigned int irq) +{ + u32 mask; + + spin_lock(&eint_lock); + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); + mask &= ~(eint_irq_to_bit(irq)); + __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); + spin_unlock(&eint_lock); +} + +static inline void s5pv310_irq_eint_ack(unsigned int irq) +{ + __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); +} + +static void s5pv310_irq_eint_maskack(unsigned int irq) +{ + s5pv310_irq_eint_mask(irq); + s5pv310_irq_eint_ack(irq); +} + +static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type) +{ + int offs = EINT_OFFSET(irq); + int shift; + u32 ctrl, mask; + u32 newvalue = 0; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + newvalue = S5P_IRQ_TYPE_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_FALLING: + newvalue = S5P_IRQ_TYPE_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_BOTH: + newvalue = S5P_IRQ_TYPE_EDGE_BOTH; + break; + + case IRQ_TYPE_LEVEL_LOW: + newvalue = S5P_IRQ_TYPE_LEVEL_LOW; + break; + + case IRQ_TYPE_LEVEL_HIGH: + newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; + break; + + default: + printk(KERN_ERR "No such irq type %d", type); + return -EINVAL; + } + + shift = (offs & 0x7) * 4; + mask = 0x7 << shift; + + spin_lock(&eint_lock); + ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); + ctrl &= ~mask; + ctrl |= newvalue << shift; + __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); + spin_unlock(&eint_lock); + + switch (offs) { + case 0 ... 7: + s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); + break; + case 8 ... 15: + s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); + break; + case 16 ... 23: + s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); + break; + case 24 ... 31: + s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); + break; + default: + printk(KERN_ERR "No such irq number %d", offs); + } + + return 0; +} + +static struct irq_chip s5pv310_irq_eint = { + .name = "s5pv310-eint", + .mask = s5pv310_irq_eint_mask, + .unmask = s5pv310_irq_eint_unmask, + .mask_ack = s5pv310_irq_eint_maskack, + .ack = s5pv310_irq_eint_ack, + .set_type = s5pv310_irq_eint_set_type, +#ifdef CONFIG_PM + .set_wake = s3c_irqext_wake, +#endif +}; + +/* s5pv310_irq_demux_eint + * + * This function demuxes the IRQ from from EINTs 16 to 31. + * It is designed to be inlined into the specific handler + * s5p_irq_demux_eintX_Y. + * + * Each EINT pend/mask registers handle eight of them. + */ +static inline void s5pv310_irq_demux_eint(unsigned int start) +{ + unsigned int irq; + + u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); + u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); + + status &= ~mask; + status &= 0xff; + + while (status) { + irq = fls(status) - 1; + generic_handle_irq(irq + start); + status &= ~(1 << irq); + } +} + +static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) +{ + s5pv310_irq_demux_eint(IRQ_EINT(16)); + s5pv310_irq_demux_eint(IRQ_EINT(24)); +} + +static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc) +{ + u32 *irq_data = get_irq_data(irq); + struct irq_chip *chip = get_irq_chip(irq); + + chip->mask(irq); + + if (chip->ack) + chip->ack(irq); + + generic_handle_irq(*irq_data); + + chip->unmask(irq); +} + +int __init s5pv310_init_irq_eint(void) +{ + int irq; + + for (irq = 0 ; irq <= 31 ; irq++) { + set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint); + set_irq_handler(IRQ_EINT(irq), handle_level_irq); + set_irq_flags(IRQ_EINT(irq), IRQF_VALID); + } + + set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31); + + for (irq = 0 ; irq <= 15 ; irq++) { + eint0_15_data[irq] = IRQ_EINT(irq); + + set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]); + set_irq_chained_handler(s5pv310_get_irq_nr(irq), + s5pv310_irq_eint0_15); + } + + return 0; +} + +arch_initcall(s5pv310_init_irq_eint); -- cgit v1.1 From d07dc60c6caf94dcf42e53f4db105de970abf4db Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 22 Oct 2010 10:49:17 +0900 Subject: ARM: S5P: Change VMALLOC_END to use more vmalloc()/ioremap() area This patch changes VMALLOC_END from 0xE0000000 to 0xF6000000, because some systems want to use more vmalloc()/ioremap() area and now don't use from at 0xE0000000 to 0xF6000000 (the start of Samsung SoCs' VA space) Cc: Ben Dooks Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/include/mach/vmalloc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h index 256f221..65759fb 100644 --- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h +++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h @@ -17,6 +17,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H __FILE__ -#define VMALLOC_END (0xF0000000UL) +#define VMALLOC_END 0xF6000000UL #endif /* __ASM_ARCH_VMALLOC_H */ -- cgit v1.1 From 09596ba07e81655dd8d90eb648cb443d48cdc9da Mon Sep 17 00:00:00 2001 From: Daein Moon Date: Mon, 25 Oct 2010 16:30:40 +0900 Subject: ARM: S5PV310: Add support SROMC This patch adds support SROMC for S5PV310 and S5PC210. Signed-off-by: Daein Moon Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/cpu.c | 5 +++ arch/arm/mach-s5pv310/include/mach/map.h | 4 +++ arch/arm/mach-s5pv310/include/mach/regs-srom.h | 50 ++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-srom.h (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 4e3f5be..82ce4aa 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -77,6 +77,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C_PA_UART), .length = SZ_512K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(S5PV310_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, }, }; diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 1e3384f..7acf4e7 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -25,6 +25,8 @@ #define S5PV310_PA_SYSRAM (0x02025000) +#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) + #define S5PC210_PA_ONENAND (0x0C000000) #define S5P_PA_ONENAND S5PC210_PA_ONENAND @@ -56,6 +58,8 @@ #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) +#define S5PV310_PA_SROMC (0x12570000) + #define S5PV310_PA_UART (0x13800000) #define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h new file mode 100644 index 0000000..1898b3e --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-srom.h @@ -0,0 +1,50 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 - SROMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_SROM_H +#define __ASM_ARCH_REGS_SROM_H __FILE__ + +#include + +#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x)) + +#define S5PV310_SROM_BW S5PV310_SROMREG(0x0) +#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4) +#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8) +#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc) +#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10) + +/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ + +#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0 +#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1 +#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2 +#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3 + +#define S5PV310_SROM_BW__CS_MASK 0xf + +#define S5PV310_SROM_BW__NCS0__SHIFT 0 +#define S5PV310_SROM_BW__NCS1__SHIFT 4 +#define S5PV310_SROM_BW__NCS2__SHIFT 8 +#define S5PV310_SROM_BW__NCS3__SHIFT 12 + +/* applies to same to BCS0 - BCS3 */ + +#define S5PV310_SROM_BCX__PMC__SHIFT 0 +#define S5PV310_SROM_BCX__TACP__SHIFT 4 +#define S5PV310_SROM_BCX__TCAH__SHIFT 8 +#define S5PV310_SROM_BCX__TCOH__SHIFT 12 +#define S5PV310_SROM_BCX__TACC__SHIFT 16 +#define S5PV310_SROM_BCX__TCOS__SHIFT 24 +#define S5PV310_SROM_BCX__TACS__SHIFT 28 + +#endif /* __ASM_ARCH_REGS_SROM_H */ -- cgit v1.1 From cbff3eb3e6e3c618583a7435f87c1548aa12b0ad Mon Sep 17 00:00:00 2001 From: Daein Moon Date: Tue, 26 Oct 2010 12:51:17 +0900 Subject: ARM: S5PV310: Support ethernet for SMDKV310 and SMDKC210 This patch adds to support ethernet for SMDKV310 and SMDKC210 board. - define smc911x resources - define configurations of smc911x platform data - define platform device "smsc911x" - initialize srom controller for lan9215 chip Signed-off-by: Daein Moon Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv310/mach-smdkc210.c | 61 +++++++++++++++++++++++++++++++++++ arch/arm/mach-s5pv310/mach-smdkv310.c | 61 +++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index 9f7f77d..2b8d4fc 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include @@ -23,6 +25,7 @@ #include #include +#include /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -105,6 +108,37 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; +static struct resource smdkc210_smsc911x_resources[] = { + [0] = { + .start = S5PV310_PA_SROM_BANK(1), + .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EINT(5), + .end = IRQ_EINT(5), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct smsc911x_platform_config smsc9215_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, + .phy_interface = PHY_INTERFACE_MODE_MII, + .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, +}; + +static struct platform_device smdkc210_smsc911x = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources), + .resource = smdkc210_smsc911x_resources, + .dev = { + .platform_data = &smsc9215_config, + }, +}; + static struct platform_device *smdkc210_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, @@ -112,8 +146,33 @@ static struct platform_device *smdkc210_devices[] __initdata = { &s3c_device_hsmmc3, &s3c_device_rtc, &s3c_device_wdt, + &smdkc210_smsc911x, }; +static void __init smdkc210_smsc911x_init(void) +{ + u32 cs1; + + /* configure nCS1 width to 16 bits */ + cs1 = __raw_readl(S5PV310_SROM_BW) & + ~(S5PV310_SROM_BW__CS_MASK << + S5PV310_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | + (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << + S5PV310_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S5PV310_SROM_BW); + + /* set timing for nCS1 suitable for ethernet chip */ + __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | + (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | + (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | + (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); +} + static void __init smdkc210_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -123,6 +182,8 @@ static void __init smdkc210_map_io(void) static void __init smdkc210_machine_init(void) { + smdkc210_smsc911x_init(); + s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata); s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata); s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index e350a75..2e625a3 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include @@ -23,6 +25,7 @@ #include #include +#include /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -105,6 +108,37 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; +static struct resource smdkv310_smsc911x_resources[] = { + [0] = { + .start = S5PV310_PA_SROM_BANK(1), + .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EINT(5), + .end = IRQ_EINT(5), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct smsc911x_platform_config smsc9215_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, + .phy_interface = PHY_INTERFACE_MODE_MII, + .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, +}; + +static struct platform_device smdkv310_smsc911x = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources), + .resource = smdkv310_smsc911x_resources, + .dev = { + .platform_data = &smsc9215_config, + }, +}; + static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, @@ -112,8 +146,33 @@ static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_hsmmc3, &s3c_device_rtc, &s3c_device_wdt, + &smdkv310_smsc911x, }; +static void __init smdkv310_smsc911x_init(void) +{ + u32 cs1; + + /* configure nCS1 width to 16 bits */ + cs1 = __raw_readl(S5PV310_SROM_BW) & + ~(S5PV310_SROM_BW__CS_MASK << + S5PV310_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | + (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << + S5PV310_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S5PV310_SROM_BW); + + /* set timing for nCS1 suitable for ethernet chip */ + __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | + (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | + (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | + (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | + (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); +} + static void __init smdkv310_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -123,6 +182,8 @@ static void __init smdkv310_map_io(void) static void __init smdkv310_machine_init(void) { + smdkv310_smsc911x_init(); + s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata); s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); -- cgit v1.1