diff options
Diffstat (limited to 'arch/arm/plat-s5p/include')
19 files changed, 2037 insertions, 16 deletions
diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h new file mode 100644 index 0000000..23a9b527b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/csis.h @@ -0,0 +1,29 @@ +/* linux/arch/arm/plat-s5p/include/plat/csis.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Platform header file for MIPI-CSI2 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_PLAT_CSIS_H +#define __ASM_PLAT_CSIS_H __FILE__ + +struct platform_device; + +struct s3c_platform_csis { + const char srclk_name[16]; + const char clk_name[16]; + unsigned long clk_rate; + + void (*cfg_gpio)(void); + void (*cfg_phy_global)(int on); +}; + +extern void s3c_csis_set_platdata(struct s3c_platform_csis *csis); + +#endif /* __ASM_PLAT_CSIS_H */ diff --git a/arch/arm/plat-s5p/include/plat/fb.h b/arch/arm/plat-s5p/include/plat/fb.h new file mode 100644 index 0000000..de4725b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/fb.h @@ -0,0 +1,127 @@ +/* linux/arch/arm/plat-s3c/include/plat/fb.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - FB platform data definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C_FB_H +#define __PLAT_S3C_FB_H __FILE__ + +#ifdef CONFIG_FB_S3C + +#define FB_SWAP_WORD (1 << 24) +#define FB_SWAP_HWORD (1 << 16) +#define FB_SWAP_BYTE (1 << 8) +#define FB_SWAP_BIT (1 << 0) + +struct platform_device; +struct clk; + +struct s3c_platform_fb { + int hw_ver; + char clk_name[16]; + int nr_wins; + int nr_buffers[5]; + int default_win; + int swap; + phys_addr_t pmem_start[5]; /* starting physical address of memory region */ + size_t pmem_size[5]; /* size of memory region */ + void *lcd; + void (*cfg_gpio)(struct platform_device *dev); + int (*backlight_on)(struct platform_device *dev); + int (*backlight_onoff)(struct platform_device *dev, int onoff); + int (*reset_lcd)(struct platform_device *dev); + int (*clk_on)(struct platform_device *pdev, struct clk **s3cfb_clk); + int (*clk_off)(struct platform_device *pdev, struct clk **clk); +}; + +extern void s3cfb_set_platdata(struct s3c_platform_fb *fimd); + +/* defined by architecture to configure gpio */ +extern void s3cfb_cfg_gpio(struct platform_device *pdev); +extern int s3cfb_backlight_on(struct platform_device *pdev); +extern int s3cfb_backlight_onoff(struct platform_device *pdev, int onoff); +extern int s3cfb_reset_lcd(struct platform_device *pdev); +extern int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk); +extern int s3cfb_clk_off(struct platform_device *pdev, struct clk **clk); +extern void s3cfb_get_clk_name(char *clk_name); + +#else + +#ifdef CONFIG_S3C_FB + +/** + * struct s3c_fb_pd_win - per window setup data + * @win_mode: The display parameters to initialise (not for window 0) + * @virtual_x: The virtual X size. + * @virtual_y: The virtual Y size. + */ +struct s3c_fb_pd_win { + struct fb_videomode win_mode; + + unsigned short default_bpp; + unsigned short max_bpp; + unsigned short virtual_x; + unsigned short virtual_y; +}; + +/** + * struct s3c_fb_platdata - S3C driver platform specific information + * @setup_gpio: Setup the external GPIO pins to the right state to transfer + * the data from the display system to the connected display + * device. + * @vidcon0: The base vidcon0 values to control the panel data format. + * @vidcon1: The base vidcon1 values to control the panel data output. + * @win: The setup data for each hardware window, or NULL for unused. + * @display_mode: The LCD output display mode. + * + * The platform data supplies the video driver with all the information + * it requires to work with the display(s) attached to the machine. It + * controls the initial mode, the number of display windows (0 is always + * the base framebuffer) that are initialised etc. + * + */ +struct s3c_fb_platdata { + void (*setup_gpio)(void); + + struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN]; + + u32 vidcon0; + u32 vidcon1; +}; + +/** + * s3c_fb_set_platdata() - Setup the FB device with platform data. + * @pd: The platform data to set. The data is copied from the passed structure + * so the machine data can mark the data __initdata so that any unused + * machines will end up dumping their data at runtime. + */ +extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); + +/** + * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s3c64xx_fb_gpio_setup_24bpp(void); + +/** + * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s5pc100_fb_gpio_setup_24bpp(void); + +#endif /* CONFIG_FB */ + +#endif + +#endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-s5p/include/plat/fimc.h b/arch/arm/plat-s5p/include/plat/fimc.h new file mode 100644 index 0000000..5685ed1 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/fimc.h @@ -0,0 +1,129 @@ +/* linux/arch/arm/plat-s5p/include/plat/fimc.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Platform header file for Samsung Camera Interface (FIMC) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef __ASM_PLAT_FIMC_H +#define __ASM_PLAT_FIMC_H __FILE__ + +#include <linux/videodev2.h> + +#define FIMC_SRC_MAX_W 1920 +#define FIMC_SRC_MAX_H 1280 + +struct platform_device; + +/* For exnternal camera device */ +enum fimc_cam_type { + CAM_TYPE_ITU = 0, + CAM_TYPE_MIPI = 1, +}; + +enum fimc_cam_format { + ITU_601_YCBCR422_8BIT = (1 << 31), + ITU_656_YCBCR422_8BIT = (0 << 31), + ITU_601_YCBCR422_16BIT = (1 << 29), + MIPI_CSI_YCBCR422_8BIT = 0x1e, + MIPI_CSI_RAW8 = 0x2a, + MIPI_CSI_RAW10 = 0x2b, + MIPI_CSI_RAW12 = 0x2c, + MIPI_USER_DEF_PACKET_1 = 0x30, /* User defined Byte-based packet 1 */ +}; + +enum fimc_cam_order422 { + CAM_ORDER422_8BIT_YCBYCR = (0 << 14), + CAM_ORDER422_8BIT_YCRYCB = (1 << 14), + CAM_ORDER422_8BIT_CBYCRY = (2 << 14), + CAM_ORDER422_8BIT_CRYCBY = (3 << 14), + CAM_ORDER422_16BIT_Y4CBCRCBCR = (0 << 14), + CAM_ORDER422_16BIT_Y4CRCBCRCB = (1 << 14), +}; + +enum fimc_cam_index { + CAMERA_PAR_A = 0, + CAMERA_PAR_B = 1, + CAMERA_CSI_C = 2, + CAMERA_PATTERN = 3, /* Not actual camera but test pattern */ + CAMERA_WB = 4, /* Not actual camera but write back */ +}; + +/* struct s3c_platform_camera: abstraction for input camera */ +struct s3c_platform_camera { + /* + * ITU cam A,B: 0,1 + * CSI-2 cam C: 2 + */ + enum fimc_cam_index id; + + enum fimc_cam_type type; /* ITU or MIPI */ + enum fimc_cam_format fmt; /* input format */ + enum fimc_cam_order422 order422; /* YCBCR422 order for ITU */ + u32 pixelformat; /* default fourcc */ + + int i2c_busnum; + struct i2c_board_info *info; + struct v4l2_subdev *sd; + + const char srclk_name[16]; /* source of mclk name */ + const char clk_name[16]; /* mclk name */ + u32 clk_rate; /* mclk ratio */ + struct clk *srclk; /* parent for mclk */ + struct clk *clk; /* mclk */ + int line_length; /* max length */ + int width; /* default resol */ + int height; /* default resol */ + struct v4l2_rect window; /* real cut region from source */ + + int mipi_lanes; /* MIPI data lanes */ + int mipi_settle; /* MIPI settle */ + int mipi_align; /* MIPI data align: 24/32 */ + + /* Polarity: 1 if inverted polarity used */ + int inv_pclk; + int inv_vsync; + int inv_href; + int inv_hsync; + + int initialized; + + /* Board specific power pin control */ + int (*cam_power)(int onoff); +}; + +/* For camera interface driver */ +struct s3c_platform_fimc { + const char srclk_name[16]; /* source of interface clock name */ + const char clk_name[16]; /* interface clock name */ + const char lclk_name[16]; /* interface clock name */ + u32 clk_rate; /* clockrate for interface clock */ + enum fimc_cam_index default_cam; /* index of default cam */ + struct s3c_platform_camera *camera[5]; /* FIXME */ + int hw_ver; + phys_addr_t pmem_start; /* starting physical address of memory region */ + size_t pmem_size; /* size of memory region */ + + void (*cfg_gpio)(struct platform_device *pdev); + int (*clk_on)(struct platform_device *pdev, struct clk *clk); + int (*clk_off)(struct platform_device *pdev, struct clk *clk); +}; + +extern void s3c_fimc0_set_platdata(struct s3c_platform_fimc *fimc); +extern void s3c_fimc1_set_platdata(struct s3c_platform_fimc *fimc); +extern void s3c_fimc2_set_platdata(struct s3c_platform_fimc *fimc); + +/* defined by architecture to configure gpio */ +extern void s3c_fimc0_cfg_gpio(struct platform_device *pdev); +extern void s3c_fimc1_cfg_gpio(struct platform_device *pdev); +extern void s3c_fimc2_cfg_gpio(struct platform_device *pdev); + +/* platform specific clock functions */ +extern int s3c_fimc_clk_on(struct platform_device *pdev, struct clk *clk); +extern int s3c_fimc_clk_off(struct platform_device *pdev, struct clk *clk); + +#endif /*__ASM_PLAT_FIMC_H */ diff --git a/arch/arm/plat-s5p/include/plat/irq-eint-group.h b/arch/arm/plat-s5p/include/plat/irq-eint-group.h new file mode 100644 index 0000000..430985b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irq-eint-group.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/plat-s5p/include/plat/irq-eint-group.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P Common IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S5P_IRQ_EINT_GROUP_H +#define __PLAT_S5P_IRQ_EINT_GROUP_H +void s5pv210_restore_eint_group(void); +#endif /* __PLAT_S5P_IRQ_EINT_GROUP_H */ diff --git a/arch/arm/plat-s5p/include/plat/irq-pm.h b/arch/arm/plat-s5p/include/plat/irq-pm.h new file mode 100644 index 0000000..a104998 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irq-pm.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/plat-s5p/include/plat/irq-pm.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P Common IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S5P_IRQ_PM_H +#define __PLAT_S5P_IRQ_PM_H +int s3c_irq_wake(struct irq_data *data, unsigned int state); +#endif /* __PLAT_S5P_IRQ_PM_H */ diff --git a/arch/arm/plat-s5p/include/plat/jpeg.h b/arch/arm/plat-s5p/include/plat/jpeg.h new file mode 100755 index 0000000..cf52000 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/jpeg.h @@ -0,0 +1,27 @@ +/* linux/arch/arm/plat-s5p/include/plat/jpeg.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Platform header file for JPEG device driver driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef __ASM_PLAT_JPEG_H +#define __ASM_PLAT_JPEG_H __FILE__ + +struct platform_device; + +/* For camera interface driver */ +struct s3c_platform_jpeg { + unsigned int max_main_width; + unsigned int max_main_height; + unsigned int max_thumb_width; + unsigned int max_thumb_height; +}; + +extern void s3c_jpeg_set_platdata(struct s3c_platform_jpeg *jpeg); + +#endif /*__ASM_PLAT_FIMC_H */ diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index d973d39..56b0432 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -25,6 +25,7 @@ #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) #define S5P_VA_SROMC S3C_ADDR(0x024C0000) +#define S5P_VA_AUDSS S3C_ADDR(0X01600000) #define S5P_VA_SYSTIMER S3C_ADDR(0x02500000) #define S5P_VA_L2CC S3C_ADDR(0x02600000) diff --git a/arch/arm/plat-s5p/include/plat/media.h b/arch/arm/plat-s5p/include/plat/media.h new file mode 100644 index 0000000..79761da --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/media.h @@ -0,0 +1,34 @@ +/* linux/arch/arm/plat-s5p/include/plat/media.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung Media device descriptions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _S5P_MEDIA_H +#define _S5P_MEDIA_H + +#include <linux/types.h> +#include <asm/setup.h> + +struct s5p_media_device { + u32 id; + const char *name; + u32 bank; + size_t memsize; + dma_addr_t paddr; +}; + +extern struct meminfo meminfo; +extern dma_addr_t s5p_get_media_memory_bank(int dev_id, int bank); +extern size_t s5p_get_media_memsize_bank(int dev_id, int bank); +extern dma_addr_t s5p_get_media_membase_bank(int bank); +extern void s5p_reserve_bootmem(struct s5p_media_device *mdevs, int nr_mdevs, size_t boundary); + +#endif + diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h new file mode 100644 index 0000000..bba97a9 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/mfc.h @@ -0,0 +1,24 @@ +/* arch/arm/plat-s5p/include/plat/mfc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Platform header file for MFC driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _S3C_MFC_H +#define _S3C_MFC_H + +#include <linux/types.h> + +struct s3c_platform_mfc { + dma_addr_t buf_phy_base[2]; + size_t buf_phy_size[2]; +}; + +extern void s3c_mfc_set_platdata(struct s3c_platform_mfc *pd); +#endif diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index bf28fad..9c2332f 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -94,10 +94,12 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, return result; } +#define PLL90XX_VDIV_MASK (0x1) #define PLL90XX_MDIV_MASK (0xFF) #define PLL90XX_PDIV_MASK (0x3F) #define PLL90XX_SDIV_MASK (0x7) #define PLL90XX_KDIV_MASK (0xffff) +#define PLL90XX_VDIV_SHIFT (27) #define PLL90XX_MDIV_SHIFT (16) #define PLL90XX_PDIV_SHIFT (8) #define PLL90XX_SDIV_SHIFT (0) diff --git a/arch/arm/plat-s5p/include/plat/regs-csis.h b/arch/arm/plat-s5p/include/plat/regs-csis.h new file mode 100644 index 0000000..aaab7bc --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-csis.h @@ -0,0 +1,105 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-csis.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Register definition file for MIPI-CSI2 Driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_CSIS_H +#define _REGS_CSIS_H + +#define S3C_CSISREG(x) (x) + +/************************************************************************* + * Registers + ************************************************************************/ +#define S3C_CSIS_CONTROL S3C_CSISREG(0x00) +#define S3C_CSIS_DPHYCTRL S3C_CSISREG(0x04) +#define S3C_CSIS_CONFIG S3C_CSISREG(0x08) +#define S3C_CSIS_DPHYSTS S3C_CSISREG(0x0c) +#define S3C_CSIS_INTMSK S3C_CSISREG(0x10) +#define S3C_CSIS_INTSRC S3C_CSISREG(0x14) +#define S3C_CSIS_RESOL S3C_CSISREG(0x2c) + +/************************************************************************* + * Bit Definitions + ************************************************************************/ +/* Control Register */ +#define S3C_CSIS_CONTROL_DPDN_DEFAULT (0 << 31) +#define S3C_CSIS_CONTROL_DPDN_SWAP (1 << 31) +#define S3C_CSIS_CONTROL_ALIGN_32BIT (1 << 20) +#define S3C_CSIS_CONTROL_ALIGN_24BIT (0 << 20) +#define S3C_CSIS_CONTROL_ALIGN_MASK (1 << 20) +#define S3C_CSIS_CONTROL_UPDATE_SHADOW (1 << 16) +#define S3C_CSIS_CONTROL_WCLK_PCLK (0 << 8) +#define S3C_CSIS_CONTROL_WCLK_EXTCLK (1 << 8) +#define S3C_CSIS_CONTROL_WCLK_MASK (1 << 8) +#define S3C_CSIS_CONTROL_RESET (1 << 4) +#define S3C_CSIS_CONTROL_DISABLE (0 << 0) +#define S3C_CSIS_CONTROL_ENABLE (1 << 0) + +/* D-PHY Control Register */ +#define S3C_CSIS_DPHYCTRL_HS_SETTLE_MASK (0x1f << 27) +#define S3C_CSIS_DPHYCTRL_HS_SETTLE_SHIFT (27) +#define S3C_CSIS_DPHYCTRL_DISABLE (0xf << 0) +#define S3C_CSIS_DPHYCTRL_ENABLE (0xf << 0) + +/* Configuration Register */ +#define S3C_CSIS_CONFIG_FORMAT_SHIFT (2) +#define S3C_CSIS_CONFIG_FORMAT_MASK (0x1f << 2) +#define S3C_CSIS_CONFIG_NR_LANE_1 (0 << 0) +#define S3C_CSIS_CONFIG_NR_LANE_2 (1 << 0) +#define S3C_CSIS_CONFIG_NR_LANE_MASK (1 << 0) + +/* D-PHY Status Register */ +#define S3C_CSIS_DPHYSTS_STOPSTATE_LANE1 (1 << 5) +#define S3C_CSIS_DPHYSTS_STOPSTATE_LANE0 (1 << 4) +#define S3C_CSIS_DPHYSTS_STOPSTATE_CLOCK (1 << 0) + +/* Interrupt Mask Register */ +#define S3C_CSIS_INTMSK_EVEN_BEFORE_DISABLE (0 << 31) +#define S3C_CSIS_INTMSK_EVEN_BEFORE_ENABLE (1 << 31) +#define S3C_CSIS_INTMSK_EVEN_AFTER_DISABLE (0 << 30) +#define S3C_CSIS_INTMSK_EVEN_AFTER_ENABLE (1 << 30) +#define S3C_CSIS_INTMSK_ODD_BEFORE_DISABLE (0 << 29) +#define S3C_CSIS_INTMSK_ODD_BEFORE_ENABLE (1 << 29) +#define S3C_CSIS_INTMSK_ODD_AFTER_DISABLE (0 << 28) +#define S3C_CSIS_INTMSK_ODD_AFTER_ENABLE (1 << 28) +#define S3C_CSIS_INTMSK_ERR_SOT_HS_DISABLE (0 << 12) +#define S3C_CSIS_INTMSK_ERR_SOT_HS_ENABLE (1 << 12) +#define S3C_CSIS_INTMSK_ERR_ESC_DISABLE (0 << 8) +#define S3C_CSIS_INTMSK_ERR_ESC_ENABLE (1 << 8) +#define S3C_CSIS_INTMSK_ERR_CTRL_DISABLE (0 << 4) +#define S3C_CSIS_INTMSK_ERR_CTRL_ENABLE (1 << 4) +#define S3C_CSIS_INTMSK_ERR_ECC_DISABLE (0 << 2) +#define S3C_CSIS_INTMSK_ERR_ECC_ENABLE (1 << 2) +#define S3C_CSIS_INTMSK_ERR_CRC_DISABLE (0 << 1) +#define S3C_CSIS_INTMSK_ERR_CRC_ENABLE (1 << 1) +#define S3C_CSIS_INTMSK_ERR_ID_DISABLE (0 << 0) +#define S3C_CSIS_INTMSK_ERR_ID_ENABLE (1 << 0) + +/* Interrupt Source Register */ +#define S3C_CSIS_INTSRC_EVEN_BEFORE (1 << 31) +#define S3C_CSIS_INTSRC_EVEN_AFTER (1 << 30) +#define S3C_CSIS_INTSRC_ODD_BEFORE (1 << 29) +#define S3C_CSIS_INTSRC_ODD_AFTER (1 << 28) +#define S3C_CSIS_INTSRC_ERR_SOT_HS_LANE1 (1 << 13) +#define S3C_CSIS_INTSRC_ERR_SOT_HS_LANE0 (1 << 12) +#define S3C_CSIS_INTSRC_ERR_ESC_LANE1 (1 << 9) +#define S3C_CSIS_INTSRC_ERR_ESC_LANE0 (1 << 8) +#define S3C_CSIS_INTSRC_ERR_CTRL1 (1 << 5) +#define S3C_CSIS_INTSRC_ERR_CTRL0 (1 << 4) +#define S3C_CSIS_INTSRC_ERR_ECC (1 << 2) +#define S3C_CSIS_INTSRC_ERR_CRC (1 << 1) +#define S3C_CSIS_INTSRC_ERR_ID (1 << 0) + +/* Resolution Register */ +#define S3C_CSIS_RESOL_HOR_SHIFT (16) +#define S3C_CSIS_RESOL_VER_SHIFT (0) + +#endif /* _REGS_CSIS_H */ diff --git a/arch/arm/plat-s5p/include/plat/regs-fb.h b/arch/arm/plat-s5p/include/plat/regs-fb.h new file mode 100644 index 0000000..9945ebf --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-fb.h @@ -0,0 +1,396 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-fb.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Register definition file for Samsung Display Controller (FIMD) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_FB_H +#define _REGS_FB_H + +#define S3C_LCDREG(x) (x) +#define S3C_WINCON(x) S3C_LCDREG(0x0020 + (x * 0x04)) +#define S3C_VIDOSD_A(x) S3C_LCDREG(0x0040 + (x * 0x10)) +#define S3C_VIDOSD_B(x) S3C_LCDREG(0x0044 + (x * 0x10)) +#define S3C_VIDOSD_C(x) S3C_LCDREG(0x0048 + (x * 0x10)) +#define S3C_VIDOSD_D(x) S3C_LCDREG(0x004C + (x * 0x10)) +#define S3C_VIDADDR_START0(x) S3C_LCDREG(0x00A0 + (x * 0x08)) +#define S3C_VIDADDR_START1(x) S3C_LCDREG(0x00A4 + (x * 0x08)) +#define S3C_VIDADDR_END0(x) S3C_LCDREG(0x00D0 + (x * 0x08)) +#define S3C_VIDADDR_END1(x) S3C_LCDREG(0x00D4 + (x * 0x08)) +#define S3C_VIDADDR_SIZE(x) S3C_LCDREG(0x0100 + (x * 0x04)) +#define S3C_KEYCON(x) S3C_LCDREG(0x0140 + ((x - 1) * 0x08)) +#define S3C_KEYVAL(x) S3C_LCDREG(0x0144 + ((x - 1) * 0x08)) +#define S3C_WINMAP(x) S3C_LCDREG(0x0180 + (x * 0x04)) + +/* + * Register Map +*/ +#define S3C_VIDCON0 S3C_LCDREG(0x0000) /* Video control 0 */ +#define S3C_VIDCON1 S3C_LCDREG(0x0004) /* Video control 1 */ +#define S3C_VIDCON2 S3C_LCDREG(0x0008) /* Video control 2 */ +#define S3C_PRTCON S3C_LCDREG(0x000C) /* Protect control */ + +#define S3C_VIDTCON0 S3C_LCDREG(0x0010) /* Video time control 0 */ +#define S3C_VIDTCON1 S3C_LCDREG(0x0014) /* Video time control 1 */ +#define S3C_VIDTCON2 S3C_LCDREG(0x0018) /* Video time control 2 */ + +#define S3C_WINCON0 S3C_LCDREG(0x0020) /* Window control 0 */ +#define S3C_WINCON1 S3C_LCDREG(0x0024) /* Window control 1 */ +#define S3C_WINCON2 S3C_LCDREG(0x0028) /* Window control 2 */ +#define S3C_WINCON3 S3C_LCDREG(0x002C) /* Window control 3 */ +#define S3C_WINCON4 S3C_LCDREG(0x0030) /* Window control 4 */ + +#define S3C_WINSHMAP S3C_LCDREG(0x0034) /* Window Shadow control */ + +#define S3C_VIDOSD0A S3C_LCDREG(0x0040) /* Video Window 0 position control */ +#define S3C_VIDOSD0B S3C_LCDREG(0x0044) /* Video Window 0 position control1 */ +#define S3C_VIDOSD0C S3C_LCDREG(0x0048) /* Video Window 0 position control */ + +#define S3C_VIDOSD1A S3C_LCDREG(0x0050) /* Video Window 1 position control */ +#define S3C_VIDOSD1B S3C_LCDREG(0x0054) /* Video Window 1 position control */ +#define S3C_VIDOSD1C S3C_LCDREG(0x0058) /* Video Window 1 position control */ +#define S3C_VIDOSD1D S3C_LCDREG(0x005C) /* Video Window 1 position control */ + +#define S3C_VIDOSD2A S3C_LCDREG(0x0060) /* Video Window 2 position control */ +#define S3C_VIDOSD2B S3C_LCDREG(0x0064) /* Video Window 2 position control */ +#define S3C_VIDOSD2C S3C_LCDREG(0x0068) /* Video Window 2 position control */ +#define S3C_VIDOSD2D S3C_LCDREG(0x006C) /* Video Window 2 position control */ + +#define S3C_VIDOSD3A S3C_LCDREG(0x0070) /* Video Window 3 position control */ +#define S3C_VIDOSD3B S3C_LCDREG(0x0074) /* Video Window 3 position control */ +#define S3C_VIDOSD3C S3C_LCDREG(0x0078) /* Video Window 3 position control */ + +#define S3C_VIDOSD4A S3C_LCDREG(0x0080) /* Video Window 4 position control */ +#define S3C_VIDOSD4B S3C_LCDREG(0x0084) /* Video Window 4 position control */ +#define S3C_VIDOSD4C S3C_LCDREG(0x0088) /* Video Window 4 position control */ + +#define S3C_VIDW00ADD0B0 S3C_LCDREG(0x00A0) /* Window 0 buffer start address, buffer 0 */ +#define S3C_VIDW00ADD0B1 S3C_LCDREG(0x00A4) /* Window 0 buffer start address, buffer 1 */ +#define S3C_VIDW01ADD0B0 S3C_LCDREG(0x00A8) /* Window 1 buffer start address, buffer 0 */ +#define S3C_VIDW01ADD0B1 S3C_LCDREG(0x00AC) /* Window 1 buffer start address, buffer 1 */ +#define S3C_VIDW02ADD0 S3C_LCDREG(0x00B0) /* Window 2 buffer start address, buffer 0 */ +#define S3C_VIDW03ADD0 S3C_LCDREG(0x00B8) /* Window 3 buffer start address, buffer 0 */ +#define S3C_VIDW04ADD0 S3C_LCDREG(0x00C0) /* Window 4 buffer start address, buffer 0 */ +#define S3C_VIDW00ADD1B0 S3C_LCDREG(0x00D0) /* Window 0 buffer end address, buffer 0 */ +#define S3C_VIDW00ADD1B1 S3C_LCDREG(0x00D4) /* Window 0 buffer end address, buffer 1 */ +#define S3C_VIDW01ADD1B0 S3C_LCDREG(0x00D8) /* Window 1 buffer end address, buffer 0 */ +#define S3C_VIDW01ADD1B1 S3C_LCDREG(0x00DC) /* Window 1 buffer end address, buffer 1 */ +#define S3C_VIDW02ADD1 S3C_LCDREG(0x00E0) /* Window 2 buffer end address */ +#define S3C_VIDW03ADD1 S3C_LCDREG(0x00E8) /* Window 3 buffer end address */ +#define S3C_VIDW04ADD1 S3C_LCDREG(0x00F0) /* Window 4 buffer end address */ +#define S3C_VIDW00ADD2 S3C_LCDREG(0x0100) /* Window 0 buffer size */ +#define S3C_VIDW01ADD2 S3C_LCDREG(0x0104) /* Window 1 buffer size */ +#define S3C_VIDW02ADD2 S3C_LCDREG(0x0108) /* Window 2 buffer size */ +#define S3C_VIDW03ADD2 S3C_LCDREG(0x010C) /* Window 3 buffer size */ +#define S3C_VIDW04ADD2 S3C_LCDREG(0x0110) /* Window 4 buffer size */ + +#define S3C_VP1TCON0 S3C_LCDREG(0x0118) /* VP1 interface timing control 0 */ +#define S3C_VP1TCON1 S3C_LCDREG(0x011C) /* VP1 interface timing control 1 */ + +#define S3C_VIDINTCON0 S3C_LCDREG(0x0130) /* Indicate the Video interrupt control */ +#define S3C_VIDINTCON1 S3C_LCDREG(0x0134) /* Video Interrupt Pending */ + +#define S3C_W1KEYCON0 S3C_LCDREG(0x0140) /* Color key control */ +#define S3C_W1KEYCON1 S3C_LCDREG(0x0144) /* Color key value (transparent value) */ +#define S3C_W2KEYCON0 S3C_LCDREG(0x0148) /* Color key control */ +#define S3C_W2KEYCON1 S3C_LCDREG(0x014C) /* Color key value (transparent value) */ +#define S3C_W3KEYCON0 S3C_LCDREG(0x0150) /* Color key control */ +#define S3C_W3KEYCON1 S3C_LCDREG(0x0154) /* Color key value (transparent value) */ +#define S3C_W4KEYCON0 S3C_LCDREG(0x0158) /* Color key control */ +#define S3C_W4KEYCON1 S3C_LCDREG(0x015C) /* Color key value (transparent value) */ + +#define S3C_W1KEYALPHA S3C_LCDREG(0x0160) /* Color key alpha value */ +#define S3C_W2KEYALPHA S3C_LCDREG(0x0164) /* Color key alpha value */ +#define S3C_W3KEYALPHA S3C_LCDREG(0x0168) /* Color key alpha value */ +#define S3C_W4KEYALPHA S3C_LCDREG(0x016C) /* Color key alpha value */ + +#define S3C_DITHMODE S3C_LCDREG(0x0170) /* Dithering mode */ + +#define S3C_WIN0MAP S3C_LCDREG(0x0180) /* Window color control */ +#define S3C_WIN1MAP S3C_LCDREG(0x0184) /* Window color control */ +#define S3C_WIN2MAP S3C_LCDREG(0x0188) /* Window color control */ +#define S3C_WIN3MAP S3C_LCDREG(0x018C) /* Window color control */ +#define S3C_WIN4MAP S3C_LCDREG(0x0190) /* Window color control */ + +#define S3C_WPALCON_H S3C_LCDREG(0x019C) /* Window Palette control */ +#define S3C_WPALCON_L S3C_LCDREG(0x01A0) /* Window Palette control */ + +#define S3C_VIDW0ALPHA0 S3C_LCDREG(0x0200) /* Window 0 alpha value 0 */ +#define S3C_VIDW0ALPHA1 S3C_LCDREG(0x0204) /* Window 0 alpha value 1 */ +#define S3C_VIDW1ALPHA0 S3C_LCDREG(0x0208) /* Window 1 alpha value 0 */ +#define S3C_VIDW1ALPHA1 S3C_LCDREG(0x020C) /* Window 1 alpha value 1 */ +#define S3C_VIDW2ALPHA0 S3C_LCDREG(0x0210) /* Window 2 alpha value 0 */ +#define S3C_VIDW2ALPHA1 S3C_LCDREG(0x0214) /* Window 2 alpha value 1 */ +#define S3C_VIDW3ALPHA0 S3C_LCDREG(0x0218) /* Window 3 alpha value 0 */ +#define S3C_VIDW3ALPHA1 S3C_LCDREG(0x021C) /* Window 3 alpha value 1 */ +#define S3C_VIDW4ALPHA0 S3C_LCDREG(0x0220) /* Window 4 alpha value 0 */ +#define S3C_VIDW4ALPHA1 S3C_LCDREG(0x0224) /* Window 4 alpha value 1 */ + +#define S3C_BLENDEQ1 S3C_LCDREG(0x0244) /* Window 1 blending equation control */ +#define S3C_BLENDEQ2 S3C_LCDREG(0x0248) /* Window 2 blending equation control */ +#define S3C_BLENDEQ3 S3C_LCDREG(0x024C) /* Window 3 blending equation control */ +#define S3C_BLENDEQ4 S3C_LCDREG(0x0250) /* Window 4 blending equation control */ +#define S3C_BLENDCON S3C_LCDREG(0x0260) /* Blending control */ + +/* + * Bit Definitions +*/ + +/* VIDCON0 */ +#define S3C_VIDCON0_DSI_DISABLE (0 << 30) +#define S3C_VIDCON0_DSI_ENABLE (1 << 30) +#define S3C_VIDCON0_SCAN_PROGRESSIVE (0 << 29) +#define S3C_VIDCON0_SCAN_INTERLACE (1 << 29) +#define S3C_VIDCON0_SCAN_MASK (1 << 29) +#define S3C_VIDCON0_VIDOUT_RGB (0 << 26) +#define S3C_VIDCON0_VIDOUT_ITU (1 << 26) +#define S3C_VIDCON0_VIDOUT_I80LDI0 (2 << 26) +#define S3C_VIDCON0_VIDOUT_I80LDI1 (3 << 26) +#define S3C_VIDCON0_VIDOUT_WB_RGB (4 << 26) +#define S3C_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26) +#define S3C_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26) +#define S3C_VIDCON0_VIDOUT_MASK (7 << 26) +#define S3C_VIDCON0_PNRMODE_RGB_P (0 << 17) +#define S3C_VIDCON0_PNRMODE_BGR_P (1 << 17) +#define S3C_VIDCON0_PNRMODE_RGB_S (2 << 17) +#define S3C_VIDCON0_PNRMODE_BGR_S (3 << 17) +#define S3C_VIDCON0_PNRMODE_MASK (3 << 17) +#define S3C_VIDCON0_PNRMODE_SHIFT (17) +#define S3C_VIDCON0_CLKVALUP_ALWAYS (0 << 16) +#define S3C_VIDCON0_CLKVALUP_START_FRAME (1 << 16) +#define S3C_VIDCON0_CLKVALUP_MASK (1 << 16) +#define S3C_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) +#define S3C_VIDCON0_VCLKEN_NORMAL (0 << 5) +#define S3C_VIDCON0_VCLKEN_FREERUN (1 << 5) +#define S3C_VIDCON0_VCLKEN_MASK (1 << 5) +#define S3C_VIDCON0_CLKDIR_DIRECTED (0 << 4) +#define S3C_VIDCON0_CLKDIR_DIVIDED (1 << 4) +#define S3C_VIDCON0_CLKDIR_MASK (1 << 4) +#define S3C_VIDCON0_CLKSEL_HCLK (0 << 2) +#define S3C_VIDCON0_CLKSEL_SCLK (1 << 2) +#define S3C_VIDCON0_CLKSEL_MASK (1 << 2) +#define S3C_VIDCON0_ENVID_ENABLE (1 << 1) +#define S3C_VIDCON0_ENVID_DISABLE (0 << 1) +#define S3C_VIDCON0_ENVID_F_ENABLE (1 << 0) +#define S3C_VIDCON0_ENVID_F_DISABLE (0 << 0) + +/* VIDCON1 */ +#define S3C_VIDCON1_IVCLK_FALLING_EDGE (0 << 7) +#define S3C_VIDCON1_IVCLK_RISING_EDGE (1 << 7) +#define S3C_VIDCON1_IHSYNC_NORMAL (0 << 6) +#define S3C_VIDCON1_IHSYNC_INVERT (1 << 6) +#define S3C_VIDCON1_IVSYNC_NORMAL (0 << 5) +#define S3C_VIDCON1_IVSYNC_INVERT (1 << 5) +#define S3C_VIDCON1_IVDEN_NORMAL (0 << 4) +#define S3C_VIDCON1_IVDEN_INVERT (1 << 4) + +/* VIDCON2 */ +#define S3C_VIDCON2_EN601_DISABLE (0 << 23) +#define S3C_VIDCON2_EN601_ENABLE (1 << 23) +#define S3C_VIDCON2_EN601_MASK (1 << 23) +#define S3C_VIDCON2_WB_DISABLE (0 << 15) +#define S3C_VIDCON2_WB_ENABLE (1 << 15) +#define S3C_VIDCON2_WB_MASK (1 << 15) +#define S3C_VIDCON2_TVFORMATSEL_HW (0 << 14) +#define S3C_VIDCON2_TVFORMATSEL_SW (1 << 14) +#define S3C_VIDCON2_TVFORMATSEL_MASK (1 << 14) +#define S3C_VIDCON2_TVFORMATSEL_YUV422 (1 << 12) +#define S3C_VIDCON2_TVFORMATSEL_YUV444 (2 << 12) +#define S3C_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12) +#define S3C_VIDCON2_ORGYUV_YCBCR (0 << 8) +#define S3C_VIDCON2_ORGYUV_CBCRY (1 << 8) +#define S3C_VIDCON2_ORGYUV_MASK (1 << 8) +#define S3C_VIDCON2_YUVORD_CBCR (0 << 7) +#define S3C_VIDCON2_YUVORD_CRCB (1 << 7) +#define S3C_VIDCON2_YUVORD_MASK (1 << 7) + +/* PRTCON */ +#define S3C_PRTCON_UPDATABLE (0 << 11) +#define S3C_PRTCON_PROTECT (1 << 11) + +/* VIDTCON0 */ +#define S3C_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) +#define S3C_VIDTCON0_VBPD(x) (((x) & 0xff) << 16) +#define S3C_VIDTCON0_VFPD(x) (((x) & 0xff) << 8) +#define S3C_VIDTCON0_VSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON1 */ +#define S3C_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24) +#define S3C_VIDTCON1_HBPD(x) (((x) & 0xff) << 16) +#define S3C_VIDTCON1_HFPD(x) (((x) & 0xff) << 8) +#define S3C_VIDTCON1_HSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON2 */ +#define S3C_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) +#define S3C_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) + +/* Window 0~4 Control - WINCONx */ +#define S3C_WINCON_DATAPATH_DMA (0 << 22) +#define S3C_WINCON_DATAPATH_LOCAL (1 << 22) +#define S3C_WINCON_DATAPATH_MASK (1 << 22) +#define S3C_WINCON_BUFSEL_0 (0 << 20) +#define S3C_WINCON_BUFSEL_1 (1 << 20) +#define S3C_WINCON_BUFSEL_MASK (1 << 20) +#define S3C_WINCON_BUFSEL_SHIFT (20) +#define S3C_WINCON_BUFAUTO_DISABLE (0 << 19) +#define S3C_WINCON_BUFAUTO_ENABLE (1 << 19) +#define S3C_WINCON_BUFAUTO_MASK (1 << 19) +#define S3C_WINCON_BITSWP_DISABLE (0 << 18) +#define S3C_WINCON_BITSWP_ENABLE (1 << 18) +#define S3C_WINCON_BITSWP_SHIFT (18) +#define S3C_WINCON_BYTESWP_DISABLE (0 << 17) +#define S3C_WINCON_BYTESWP_ENABLE (1 << 17) +#define S3C_WINCON_BYTESWP_SHIFT (17) +#define S3C_WINCON_HAWSWP_DISABLE (0 << 16) +#define S3C_WINCON_HAWSWP_ENABLE (1 << 16) +#define S3C_WINCON_HAWSWP_SHIFT (16) +#define S3C_WINCON_WSWP_DISABLE (0 << 15) +#define S3C_WINCON_WSWP_ENABLE (1 << 15) +#define S3C_WINCON_WSWP_SHIFT (15) +#define S3C_WINCON_INRGB_RGB (0 << 13) +#define S3C_WINCON_INRGB_YUV (1 << 13) +#define S3C_WINCON_INRGB_MASK (1 << 13) +#define S3C_WINCON_BURSTLEN_16WORD (0 << 9) +#define S3C_WINCON_BURSTLEN_8WORD (1 << 9) +#define S3C_WINCON_BURSTLEN_4WORD (2 << 9) +#define S3C_WINCON_BURSTLEN_MASK (3 << 9) +#define S3C_WINCON_ALPHA_MULTI_DISABLE (0 << 7) +#define S3C_WINCON_ALPHA_MULTI_ENABLE (1 << 7) +#define S3C_WINCON_BLD_PLANE (0 << 6) +#define S3C_WINCON_BLD_PIXEL (1 << 6) +#define S3C_WINCON_BLD_MASK (1 << 6) +#define S3C_WINCON_BPPMODE_1BPP (0 << 2) +#define S3C_WINCON_BPPMODE_2BPP (1 << 2) +#define S3C_WINCON_BPPMODE_4BPP (2 << 2) +#define S3C_WINCON_BPPMODE_8BPP_PAL (3 << 2) +#define S3C_WINCON_BPPMODE_8BPP (4 << 2) +#define S3C_WINCON_BPPMODE_16BPP_565 (5 << 2) +#define S3C_WINCON_BPPMODE_16BPP_A555 (6 << 2) +#define S3C_WINCON_BPPMODE_18BPP_666 (8 << 2) +#define S3C_WINCON_BPPMODE_18BPP_A665 (9 << 2) +#define S3C_WINCON_BPPMODE_24BPP_888 (0xb << 2) +#define S3C_WINCON_BPPMODE_24BPP_A887 (0xc << 2) +#define S3C_WINCON_BPPMODE_32BPP (0xd << 2) +#define S3C_WINCON_BPPMODE_16BPP_A444 (0xe << 2) +#define S3C_WINCON_BPPMODE_15BPP_555 (0xf << 2) +#define S3C_WINCON_BPPMODE_MASK (0xf << 2) +#define S3C_WINCON_BPPMODE_SHIFT (2) +#define S3C_WINCON_ALPHA0_SEL (0 << 1) +#define S3C_WINCON_ALPHA1_SEL (1 << 1) +#define S3C_WINCON_ALPHA_SEL_MASK (1 << 1) +#define S3C_WINCON_ENWIN_DISABLE (0 << 0) +#define S3C_WINCON_ENWIN_ENABLE (1 << 0) + +/* WINCON1 special */ +#define S3C_WINCON1_VP_DISABLE (0 << 24) +#define S3C_WINCON1_VP_ENABLE (1 << 24) +#define S3C_WINCON1_LOCALSEL_FIMC1 (0 << 23) +#define S3C_WINCON1_LOCALSEL_VP (1 << 23) +#define S3C_WINCON1_LOCALSEL_MASK (1 << 23) + +/* WINSHMAP */ +#define S3C_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10) +#define S3C_WINSHMAP_CH_ENABLE(x) (1 << (x)) +#define S3C_WINSHMAP_CH_DISABLE(x) (1 << (x)) +#define S3C_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x)) +#define S3C_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x)) + + +/* VIDOSDxA, VIDOSDxB */ +#define S3C_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11) +#define S3C_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) +#define S3C_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) +#define S3C_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) + +/* VIDOSD0C, VIDOSDxD */ +#define S3C_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) + +/* VIDOSDxC (1~4) */ +#define S3C_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20) +#define S3C_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16) +#define S3C_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12) +#define S3C_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8) +#define S3C_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4) +#define S3C_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0) +#define S3C_VIDOSD_ALPHA0_SHIFT (12) +#define S3C_VIDOSD_ALPHA1_SHIFT (0) + +/* Start Address */ +#define S3C_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24) +#define S3C_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0) + +/* End Address */ +#define S3C_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0) + +/* Buffer Size */ +#define S3C_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) +#define S3C_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) + +/* WIN Color Map */ +#define S3C_WINMAP_COLOR(x) ((x) & 0xffffff) + +/* VIDINTCON0 */ +#define S3C_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19) +#define S3C_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19) +#define S3C_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18) +#define S3C_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18) +#define S3C_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17) +#define S3C_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17) +#define S3C_VIDINTCON0_FRAMESEL0_BACK (0 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_FRONT (3 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_MASK (3 << 15) +#define S3C_VIDINTCON0_FRAMESEL1_NONE (0 << 13) +#define S3C_VIDINTCON0_FRAMESEL1_BACK (1 << 13) +#define S3C_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13) +#define S3C_VIDINTCON0_FRAMESEL1_FRONT (3 << 13) +#define S3C_VIDINTCON0_INTFRMEN_DISABLE (0 << 12) +#define S3C_VIDINTCON0_INTFRMEN_ENABLE (1 << 12) +#define S3C_VIDINTCON0_FIFOSEL_WIN4 (1 << 11) +#define S3C_VIDINTCON0_FIFOSEL_WIN3 (1 << 10) +#define S3C_VIDINTCON0_FIFOSEL_WIN2 (1 << 9) +#define S3C_VIDINTCON0_FIFOSEL_WIN1 (1 << 6) +#define S3C_VIDINTCON0_FIFOSEL_WIN0 (1 << 5) +#define S3C_VIDINTCON0_FIFOSEL_ALL (0x73 << 5) +#define S3C_VIDINTCON0_FIFOSEL_MASK (0x73 << 5) +#define S3C_VIDINTCON0_FIFOLEVEL_25 (0 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_50 (1 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_75 (2 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_FULL (4 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_MASK (7 << 2) +#define S3C_VIDINTCON0_INTFIFO_DISABLE (0 << 1) +#define S3C_VIDINTCON0_INTFIFO_ENABLE (1 << 1) +#define S3C_VIDINTCON0_INT_DISABLE (0 << 0) +#define S3C_VIDINTCON0_INT_ENABLE (1 << 0) +#define S3C_VIDINTCON0_INT_MASK (1 << 0) + +/* VIDINTCON1 */ +#define S3C_VIDINTCON1_INTVPPEND (1 << 5) +#define S3C_VIDINTCON1_INTI80PEND (1 << 2) +#define S3C_VIDINTCON1_INTFRMPEND (1 << 1) +#define S3C_VIDINTCON1_INTFIFOPEND (1 << 0) + +/* WINMAP */ +#define S3C_WINMAP_ENABLE (1 << 24) + +/* WxKEYCON0 (1~4) */ +#define S3C_KEYCON0_KEYBLEN_DISABLE (0 << 26) +#define S3C_KEYCON0_KEYBLEN_ENABLE (1 << 26) +#define S3C_KEYCON0_KEY_DISABLE (0 << 25) +#define S3C_KEYCON0_KEY_ENABLE (1 << 25) +#define S3C_KEYCON0_DIRCON_MATCH_FG (0 << 24) +#define S3C_KEYCON0_DIRCON_MATCH_BG (1 << 24) +#define S3C_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0) + +/* WxKEYCON1 (1~4) */ +#define S3C_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0) + +#endif /* _REGS_FB_H */ diff --git a/arch/arm/plat-s5p/include/plat/regs-fimc.h b/arch/arm/plat-s5p/include/plat/regs-fimc.h new file mode 100644 index 0000000..26cd622 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-fimc.h @@ -0,0 +1,446 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-fimc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Register definition file for Samsung Camera Interface (FIMC) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_REGS_FIMC_H +#define __ASM_PLAT_REGS_FIMC_H __FILE__ + +/* + * Register part +*/ +#define S3C_CIOYSA(__x) (0x18 + (__x) * 4) +#define S3C_CIOCBSA(__x) (0x28 + (__x) * 4) +#define S3C_CIOCRSA(__x) (0x38 + (__x) * 4) + +#define S3C_CISRCFMT (0x00) /* Input source format */ +#define S3C_CIWDOFST (0x04) /* Window offset */ +#define S3C_CIGCTRL (0x08) /* Global control */ +#define S3C_CIWDOFST2 (0x14) /* Window offset 2 */ +#define S3C_CIOYSA1 (0x18) /* Y 1st frame start address for output DMA */ +#define S3C_CIOYSA2 (0x1c) /* Y 2nd frame start address for output DMA */ +#define S3C_CIOYSA3 (0x20) /* Y 3rd frame start address for output DMA */ +#define S3C_CIOYSA4 (0x24) /* Y 4th frame start address for output DMA */ +#define S3C_CIOCBSA1 (0x28) /* Cb 1st frame start address for output DMA */ +#define S3C_CIOCBSA2 (0x2c) /* Cb 2nd frame start address for output DMA */ +#define S3C_CIOCBSA3 (0x30) /* Cb 3rd frame start address for output DMA */ +#define S3C_CIOCBSA4 (0x34) /* Cb 4th frame start address for output DMA */ +#define S3C_CIOCRSA1 (0x38) /* Cr 1st frame start address for output DMA */ +#define S3C_CIOCRSA2 (0x3c) /* Cr 2nd frame start address for output DMA */ +#define S3C_CIOCRSA3 (0x40) /* Cr 3rd frame start address for output DMA */ +#define S3C_CIOCRSA4 (0x44) /* Cr 4th frame start address for output DMA */ +#define S3C_CITRGFMT (0x48) /* Target image format */ +#define S3C_CIOCTRL (0x4c) /* Output DMA control */ +#define S3C_CISCPRERATIO (0x50) /* Pre-scaler control 1 */ +#define S3C_CISCPREDST (0x54) /* Pre-scaler control 2 */ +#define S3C_CISCCTRL (0x58) /* Main scaler control */ +#define S3C_CITAREA (0x5c) /* Target area */ +#define S3C_CISTATUS (0x64) /* Status */ +#define S3C_CIIMGCPT (0xc0) /* Image capture enable command */ +#define S3C_CICPTSEQ (0xc4) /* Capture sequence */ +#define S3C_CIIMGEFF (0xd0) /* Image effects */ +#define S3C_CIIYSA0 (0xd4) /* Y frame start address for input DMA */ +#define S3C_CIICBSA0 (0xd8) /* Cb frame start address for input DMA */ +#define S3C_CIICRSA0 (0xdc) /* Cr frame start address for input DMA */ +#define S3C_CIILINESKIP_Y (0xec) /* Input DMA Y Line Skip */ +#define S3C_CIILINESKIP_CB (0xf0) /* Input DMA Cb Line Skip */ +#define S3C_CIILINESKIP_CR (0xf4) /* Input DMA Cr Line Skip */ +#define S3C_CIREAL_ISIZE (0xf8) /* Real input DMA image size */ +#define S3C_MSCTRL (0xfc) /* Input DMA control */ +#define S3C_CIOYOFF (0x168) /* Output DMA Y offset */ +#define S3C_CIOCBOFF (0x16c) /* Output DMA CB offset */ +#define S3C_CIOCROFF (0x170) /* Output DMA CR offset */ +#define S3C_CIIYOFF (0x174) /* Input DMA Y offset */ +#define S3C_CIICBOFF (0x178) /* Input DMA CB offset */ +#define S3C_CIICROFF (0x17c) /* Input DMA CR offset */ +#define S3C_ORGISIZE (0x180) /* Input DMA original image size */ +#define S3C_ORGOSIZE (0x184) /* Output DMA original image size */ +#define S3C_CIEXTEN (0x188) /* Real output DMA image size */ +#define S3C_CIDMAPARAM (0x18c) /* DMA parameter */ +#define S3C_CSIIMGFMT (0x194) /* MIPI CSI image format */ +#define S3C_MISC_FIMC (0x198) /* FIMC Clock Source Select */ + +/* + * Macro part +*/ +#define S3C_CISRCFMT_SOURCEHSIZE(x) ((x) << 16) +#define S3C_CISRCFMT_SOURCEVSIZE(x) ((x) << 0) + +#define S3C_CIWDOFST_WINHOROFST(x) ((x) << 16) +#define S3C_CIWDOFST_WINVEROFST(x) ((x) << 0) + +#define S3C_CIWDOFST2_WINHOROFST2(x) ((x) << 16) +#define S3C_CIWDOFST2_WINVEROFST2(x) ((x) << 0) + +#define S3C_CITRGFMT_TARGETHSIZE(x) (((x) & 0x1fff) << 16) +#define S3C_CITRGFMT_TARGETVSIZE(x) (((x) & 0x1fff) << 0) + +#define S3C_CISCPRERATIO_SHFACTOR(x) ((x) << 28) +#define S3C_CISCPRERATIO_PREHORRATIO(x) ((x) << 16) +#define S3C_CISCPRERATIO_PREVERRATIO(x) ((x) << 0) + +#define S3C_CISCPREDST_PREDSTWIDTH(x) ((x) << 16) +#define S3C_CISCPREDST_PREDSTHEIGHT(x) ((x) << 0) + +#define S3C_CISCCTRL_MAINHORRATIO(x) ((x) << 16) +#define S3C_CISCCTRL_MAINVERRATIO(x) ((x) << 0) + +#define S3C_CITAREA_TARGET_AREA(x) ((x) << 0) + +#define S3C_CISTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) +#define S3C_CISTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1) +#define S3C_CISTATUS_GET_LAST_CAPTURE_END(x) (((x) >> 16) & 0x1) +#define S3C_CISTATUS_GET_LCD_STATUS(x) (((x) >> 9) & 0x1) +#define S3C_CISTATUS_GET_ENVID_STATUS(x) ((x) & 0x1) + +#define S3C_CIIMGEFF_FIN(x) ((x & 0x7) << 26) +#define S3C_CIIMGEFF_PAT_CB(x) ((x) << 13) +#define S3C_CIIMGEFF_PAT_CR(x) ((x) << 0) + +#define S3C_CIILINESKIP(x) (((x) & 0xf) << 24) + +#define S3C_CIREAL_ISIZE_HEIGHT(x) ((x) << 16) +#define S3C_CIREAL_ISIZE_WIDTH(x) ((x) << 0) + +#define S3C_MSCTRL_SUCCESSIVE_COUNT(x) ((x) << 24) +#define S3C_MSCTRL_GET_INDMA_STATUS(x) ((x) & 0x1) + +#define S3C_CIOYOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIOYOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIOCBOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIOCBOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIOCROFF_VERTICAL(x) ((x) << 16) +#define S3C_CIOCROFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIIYOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIIYOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIICBOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIICBOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIICROFF_VERTICAL(x) ((x) << 16) +#define S3C_CIICROFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_ORGISIZE_VERTICAL(x) ((x) << 16) +#define S3C_ORGISIZE_HORIZONTAL(x) ((x) << 0) + +#define S3C_ORGOSIZE_VERTICAL(x) ((x) << 16) +#define S3C_ORGOSIZE_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIEXTEN_TARGETH_EXT(x) (((x) & 0x2000) << 26) +#define S3C_CIEXTEN_TARGETV_EXT(x) (((x) & 0x2000) << 24) +#define S3C_CIEXTEN_MAINHORRATIO_EXT(x) (((x) & 0x3F) << 10) +#define S3C_CIEXTEN_MAINVERRATIO_EXT(x) ((x) & 0x3F) + +/* + * Bit definition part +*/ +/* Source format register */ +#define S3C_CISRCFMT_ITU601_8BIT (1 << 31) +#define S3C_CISRCFMT_ITU656_8BIT (0 << 31) +#define S3C_CISRCFMT_ITU601_16BIT (1 << 29) +#define S3C_CISRCFMT_ORDER422_YCBYCR (0 << 14) +#define S3C_CISRCFMT_ORDER422_YCRYCB (1 << 14) +#define S3C_CISRCFMT_ORDER422_CBYCRY (2 << 14) +#define S3C_CISRCFMT_ORDER422_CRYCBY (3 << 14) +#define S3C_CISRCFMT_ORDER422_Y4CBCRCBCR (0 << 14) /* ITU601 16bit only */ +#define S3C_CISRCFMT_ORDER422_Y4CRCBCRCB (1 << 14) /* ITU601 16bit only */ + +/* Window offset register */ +#define S3C_CIWDOFST_WINOFSEN (1 << 31) +#define S3C_CIWDOFST_CLROVFIY (1 << 30) +#define S3C_CIWDOFST_CLROVRLB (1 << 29) +#define S3C_CIWDOFST_WINHOROFST_MASK (0x7ff << 16) +#define S3C_CIWDOFST_CLROVFICB (1 << 15) +#define S3C_CIWDOFST_CLROVFICR (1 << 14) +#define S3C_CIWDOFST_WINVEROFST_MASK (0xfff << 0) + +/* Global control register */ +#define S3C_CIGCTRL_SWRST (1 << 31) +#define S3C_CIGCTRL_CAMRST_A (1 << 30) +#define S3C_CIGCTRL_SELCAM_ITU_B (0 << 29) +#define S3C_CIGCTRL_SELCAM_ITU_A (1 << 29) +#define S3C_CIGCTRL_SELCAM_ITU_MASK (1 << 29) +#define S3C_CIGCTRL_TESTPATTERN_NORMAL (0 << 27) +#define S3C_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) +#define S3C_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) +#define S3C_CIGCTRL_TESTPATTERN_VER_INC (3 << 27) +#define S3C_CIGCTRL_TESTPATTERN_MASK (3 << 27) +#define S3C_CIGCTRL_TESTPATTERN_SHIFT (27) +#define S3C_CIGCTRL_INVPOLPCLK (1 << 26) +#define S3C_CIGCTRL_INVPOLVSYNC (1 << 25) +#define S3C_CIGCTRL_INVPOLHREF (1 << 24) +#define S3C_CIGCTRL_IRQ_OVFEN (1 << 22) +#define S3C_CIGCTRL_HREF_MASK (1 << 21) +#define S3C_CIGCTRL_IRQ_EDGE (0 << 20) +#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20) +#define S3C_CIGCTRL_IRQ_CLR (1 << 19) +#define S3C_CIGCTRL_IRQ_DISABLE (0 << 16) +#define S3C_CIGCTRL_IRQ_ENABLE (1 << 16) +#define S3C_CIGCTRL_SHADOW_DISABLE (1 << 12) +#define S3C_CIGCTRL_CAM_JPEG (1 << 8) +#define S3C_CIGCTRL_SELCAM_MIPI_B (0 << 7) +#define S3C_CIGCTRL_SELCAM_MIPI_A (1 << 7) +#define S3C_CIGCTRL_SELCAM_MIPI_MASK (1 << 7) +#define S3C_CIGCTRL_SELWB_CAMIF_CAMERA (0 << 6) +#define S3C_CIGCTRL_SELWB_CAMIF_WRITEBACK (1 << 6) +#define S3C_CIGCTRL_SELWB_CAMIF_MASK (1 << 6) +#define S3C_CIGCTRL_CSC_ITU601 (0 << 5) +#define S3C_CIGCTRL_CSC_ITU709 (1 << 5) +#define S3C_CIGCTRL_CSC_MASK (1 << 5) +#define S3C_CIGCTRL_INVPOLHSYNC (1 << 4) +#define S3C_CIGCTRL_SELCAM_FIMC_ITU (0 << 3) +#define S3C_CIGCTRL_SELCAM_FIMC_MIPI (1 << 3) +#define S3C_CIGCTRL_SELCAM_FIMC_MASK (1 << 3) +#define S3C_CIGCTRL_PROGRESSIVE (0 << 0) +#define S3C_CIGCTRL_INTERLACE (1 << 0) + +/* Window offset2 register */ +#define S3C_CIWDOFST_WINHOROFST2_MASK (0xfff << 16) +#define S3C_CIWDOFST_WINVEROFST2_MASK (0xfff << 16) + +/* Target format register */ +#define S3C_CITRGFMT_INROT90_CLOCKWISE (1 << 31) +#define S3C_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) +#define S3C_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) +#define S3C_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE (2 << 29) +#define S3C_CITRGFMT_OUTFORMAT_RGB (3 << 29) +#define S3C_CITRGFMT_OUTFORMAT_MASK (3 << 29) +#define S3C_CITRGFMT_FLIP_SHIFT (14) +#define S3C_CITRGFMT_FLIP_NORMAL (0 << 14) +#define S3C_CITRGFMT_FLIP_X_MIRROR (1 << 14) +#define S3C_CITRGFMT_FLIP_Y_MIRROR (2 << 14) +#define S3C_CITRGFMT_FLIP_180 (3 << 14) +#define S3C_CITRGFMT_FLIP_MASK (3 << 14) +#define S3C_CITRGFMT_OUTROT90_CLOCKWISE (1 << 13) +#define S3C_CITRGFMT_TARGETV_MASK (0x1fff << 0) +#define S3C_CITRGFMT_TARGETH_MASK (0x1fff << 16) + +/* Output DMA control register */ +#define S3C_CIOCTRL_WEAVE_OUT (1 << 31) +#define S3C_CIOCTRL_WEAVE_MASK (1 << 31) +#define S3C_CIOCTRL_ORDER2P_LSB_CBCR (0 << 24) +#define S3C_CIOCTRL_ORDER2P_LSB_CRCB (1 << 24) +#define S3C_CIOCTRL_ORDER2P_MSB_CRCB (2 << 24) +#define S3C_CIOCTRL_ORDER2P_MSB_CBCR (3 << 24) +#define S3C_CIOCTRL_ORDER2P_SHIFT (24) +#define S3C_CIOCTRL_ORDER2P_MASK (3 << 24) +#define S3C_CIOCTRL_YCBCR_3PLANE (0 << 3) +#define S3C_CIOCTRL_YCBCR_2PLANE (1 << 3) +#define S3C_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) +#define S3C_CIOCTRL_LASTIRQ_ENABLE (1 << 2) +#define S3C_CIOCTRL_ORDER422_YCBYCR (0 << 0) +#define S3C_CIOCTRL_ORDER422_YCRYCB (1 << 0) +#define S3C_CIOCTRL_ORDER422_CBYCRY (2 << 0) +#define S3C_CIOCTRL_ORDER422_CRYCBY (3 << 0) +#define S3C_CIOCTRL_ORDER422_MASK (3 << 0) + +/* Main scaler control register */ +#define S3C_CISCCTRL_SCALERBYPASS (1 << 31) +#define S3C_CISCCTRL_SCALEUP_H (1 << 30) +#define S3C_CISCCTRL_SCALEUP_V (1 << 29) +#define S3C_CISCCTRL_CSCR2Y_NARROW (0 << 28) +#define S3C_CISCCTRL_CSCR2Y_WIDE (1 << 28) +#define S3C_CISCCTRL_CSCY2R_NARROW (0 << 27) +#define S3C_CISCCTRL_CSCY2R_WIDE (1 << 27) +#define S3C_CISCCTRL_LCDPATHEN_FIFO (1 << 26) +#define S3C_CISCCTRL_PROGRESSIVE (0 << 25) +#define S3C_CISCCTRL_INTERLACE (1 << 25) +#define S3C_CISCCTRL_SCAN_MASK (1 << 25) +#define S3C_CISCCTRL_SCALERSTART (1 << 15) +#define S3C_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) +#define S3C_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) +#define S3C_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) +#define S3C_CISCCTRL_INRGB_FMT_RGB_MASK (3 << 13) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB_MASK (3 << 11) +#define S3C_CISCCTRL_EXTRGB_NORMAL (0 << 10) +#define S3C_CISCCTRL_EXTRGB_EXTENSION (1 << 10) +#define S3C_CISCCTRL_ONE2ONE (1 << 9) +#define S3C_CISCCTRL_MAIN_V_RATIO_MASK (0x1ff << 0) +#define S3C_CISCCTRL_MAIN_H_RATIO_MASK (0x1ff << 16) + +/* Status register */ +#define S3C_CISTATUS_OVFIY (1 << 31) +#define S3C_CISTATUS_OVFICB (1 << 30) +#define S3C_CISTATUS_OVFICR (1 << 29) +#define S3C_CISTATUS_VSYNC (1 << 28) +#define S3C_CISTATUS_WINOFSTEN (1 << 25) +#define S3C_CISTATUS_IMGCPTEN (1 << 22) +#define S3C_CISTATUS_IMGCPTENSC (1 << 21) +#define S3C_CISTATUS_VSYNC_A (1 << 20) +#define S3C_CISTATUS_VSYNC_B (1 << 19) +#define S3C_CISTATUS_OVRLB (1 << 18) +#define S3C_CISTATUS_FRAMEEND (1 << 17) +#define S3C_CISTATUS_LASTCAPTUREEND (1 << 16) +#define S3C_CISTATUS_VVALID_A (1 << 15) +#define S3C_CISTATUS_VVALID_B (1 << 14) + +/* Image capture enable register */ +#define S3C_CIIMGCPT_IMGCPTEN (1 << 31) +#define S3C_CIIMGCPT_IMGCPTEN_SC (1 << 30) +#define S3C_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) +#define S3C_CIIMGCPT_CPT_FRMOD_EN (0 << 18) +#define S3C_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) + +/* Image effects register */ +#define S3C_CIIMGEFF_IE_DISABLE (0 << 30) +#define S3C_CIIMGEFF_IE_ENABLE (1 << 30) +#define S3C_CIIMGEFF_IE_SC_BEFORE (0 << 29) +#define S3C_CIIMGEFF_IE_SC_AFTER (1 << 29) +#define S3C_CIIMGEFF_FIN_BYPASS (0 << 26) +#define S3C_CIIMGEFF_FIN_ARBITRARY (1 << 26) +#define S3C_CIIMGEFF_FIN_NEGATIVE (2 << 26) +#define S3C_CIIMGEFF_FIN_ARTFREEZE (3 << 26) +#define S3C_CIIMGEFF_FIN_EMBOSSING (4 << 26) +#define S3C_CIIMGEFF_FIN_SILHOUETTE (5 << 26) +#define S3C_CIIMGEFF_FIN_MASK (7 << 26) +#define S3C_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0)) + +/* Real input DMA size register */ +#define S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31) +#define S3C_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30) +#define S3C_CIREAL_ISIZE_HEIGHT_MASK (0x3FFF << 16) +#define S3C_CIREAL_ISIZE_WIDTH_MASK (0x3FFF << 0) + +/* Input DMA control register */ +#define S3C_MSCTRL_FIELD_MASK (1 << 31) +#define S3C_MSCTRL_FIELD_WEAVE (1 << 31) +#define S3C_MSCTRL_FIELD_NORMAL (0 << 31) +#define S3C_MSCTRL_BURST_CNT (24) +#define S3C_MSCTRL_BURST_CNT_MASK (0xf << 24) +#define S3C_MSCTRL_ORDER2P_LSB_CBCR (0 << 16) +#define S3C_MSCTRL_ORDER2P_LSB_CRCB (1 << 16) +#define S3C_MSCTRL_ORDER2P_MSB_CRCB (2 << 16) +#define S3C_MSCTRL_ORDER2P_MSB_CBCR (3 << 16) +#define S3C_MSCTRL_ORDER2P_SHIFT (16) +#define S3C_MSCTRL_ORDER2P_SHIFT_MASK (0x3 << 16) +#define S3C_MSCTRL_C_INT_IN_3PLANE (0 << 15) +#define S3C_MSCTRL_C_INT_IN_2PLANE (1 << 15) +#define S3C_MSCTRL_FLIP_SHIFT (13) +#define S3C_MSCTRL_FLIP_NORMAL (0 << 13) +#define S3C_MSCTRL_FLIP_X_MIRROR (1 << 13) +#define S3C_MSCTRL_FLIP_Y_MIRROR (2 << 13) +#define S3C_MSCTRL_FLIP_180 (3 << 13) +#define S3C_MSCTRL_FLIP_MASK (3 << 13) +#define S3C_MSCTRL_ORDER422_CRYCBY (0 << 4) +#define S3C_MSCTRL_ORDER422_YCRYCB (1 << 4) +#define S3C_MSCTRL_ORDER422_CBYCRY (2 << 4) +#define S3C_MSCTRL_ORDER422_YCBYCR (3 << 4) +#define S3C_MSCTRL_INPUT_EXTCAM (0 << 3) +#define S3C_MSCTRL_INPUT_MEMORY (1 << 3) +#define S3C_MSCTRL_INPUT_MASK (1 << 3) +#define S3C_MSCTRL_INFORMAT_YCBCR420 (0 << 1) +#define S3C_MSCTRL_INFORMAT_YCBCR422 (1 << 1) +#define S3C_MSCTRL_INFORMAT_YCBCR422_1PLANE (2 << 1) +#define S3C_MSCTRL_INFORMAT_RGB (3 << 1) +#define S3C_MSCTRL_ENVID (1 << 0) + +/* DMA parameter register */ +#define S3C_CIDMAPARAM_R_MODE_LINEAR (0 << 29) +#define S3C_CIDMAPARAM_R_MODE_CONFTILE (1 << 29) +#define S3C_CIDMAPARAM_R_MODE_16X16 (2 << 29) +#define S3C_CIDMAPARAM_R_MODE_64X32 (3 << 29) +#define S3C_CIDMAPARAM_R_MODE_MASK (3 << 29) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_64 (0 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_128 (1 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_256 (2 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_512 (3 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_1 (0 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_2 (1 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_4 (2 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_8 (3 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_32 (5 << 20) +#define S3C_CIDMAPARAM_W_MODE_LINEAR (0 << 13) +#define S3C_CIDMAPARAM_W_MODE_CONFTILE (1 << 13) +#define S3C_CIDMAPARAM_W_MODE_16X16 (2 << 13) +#define S3C_CIDMAPARAM_W_MODE_64X32 (3 << 13) +#define S3C_CIDMAPARAM_W_MODE_MASK (3 << 13) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_64 (0 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_128 (1 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_256 (2 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_512 (3 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4) + +/* Gathering Extension register */ +#define S3C_CIEXTEN_TARGETH_EXT_MASK (1 << 26) +#define S3C_CIEXTEN_TARGETV_EXT_MASK (1 << 24) +#define S3C_CIEXTEN_MAINHORRATIO_EXT_MASK (0x3F << 10) +#define S3C_CIEXTEN_MAINVERRATIO_EXT_MASK (0x3F) +#define S3C_CIEXTEN_YUV444_OUT (1 << 22) + +/* FIMC Clock Source Select register */ +#define S3C_CLKSRC_HCLK (0 << 1) +#define S3C_CLKSRC_HCLK_MASK (1 << 1) +#define S3C_CLKSRC_SCLK (1 << 1) + +/* FIMC GPIO */ +#define S5PV210_GPE0_0_CAM_A_PCLK (0x2 << 0) +#define S5PV210_GPE0_0_GPIO_INT8_0 (0xf << 0) + +#define S5PV210_GPE0_1_CAM_A_VSYNC (0x2 << 4) +#define S5PV210_GPE0_1_GPIO_INT8_1 (0xf << 4) + +#define S5PV210_GPE0_2_CAM_A_HREF (0x2 << 8) +#define S5PV210_GPE0_2_GPIO_INT8_2 (0xf << 8) + +#define S5PV210_GPE0_3_CAM_A_DATA_0 (0x2 << 12) +#define S5PV210_GPE0_3_GPIO_INT8_3 (0xf << 12) + +#define S5PV210_GPE0_4_CAM_A_DATA_1 (0x2 << 16) +#define S5PV210_GPE0_4_GPIO_INT8_4 (0xf << 16) + +#define S5PV210_GPE0_5_CAM_A_DATA_2 (0x2 << 20) +#define S5PV210_GPE0_5_GPIO_INT8_5 (0xf << 20) + +#define S5PV210_GPE0_6_CAM_A_DATA_3 (0x2 << 24) +#define S5PV210_GPE0_6_GPIO_INT8_6 (0xf << 24) + +#define S5PV210_GPE0_7_CAM_A_DATA_4 (0x2 << 28) +#define S5PV210_GPE0_7_GPIO_INT8_7 (0xf << 28) + +#define S5PV210_GPE1_0_CAM_A_DATA_5 (0x2 << 0) +#define S5PV210_GPE1_1_CAM_A_DATA_6 (0x2 << 4) +#define S5PV210_GPE1_2_CAM_A_DATA_7 (0x2 << 8) +#define S5PV210_GPE1_3_CAM_A_CLKOUT (0x2 << 12) +#define S5PV210_GPE1_4_CAM_A_FIELD (0x2 << 16) + +#define S5PV210_GPJ0_0_CAM_B_DATA_0 (0x3 << 0) +#define S5PV210_GPJ0_1_CAM_B_DATA_1 (0x3 << 4) +#define S5PV210_GPJ0_2_CAM_B_DATA_2 (0x3 << 8) +#define S5PV210_GPJ0_3_CAM_B_DATA_3 (0x3 << 12) +#define S5PV210_GPJ0_4_CAM_B_DATA_4 (0x3 << 16) +#define S5PV210_GPJ0_5_CAM_B_DATA_5 (0x3 << 20) +#define S5PV210_GPJ0_6_CAM_B_DATA_6 (0x3 << 24) +#define S5PV210_GPJ0_7_CAM_B_DATA_7 (0x3 << 28) + +#define S5PV210_GPJ1_0_CAM_B_PCLK (0x3 << 0) +#define S5PV210_GPJ1_1_CAM_B_VSYNC (0x3 << 4) +#define S5PV210_GPJ1_2_CAM_B_HREF (0x3 << 8) +#define S5PV210_GPJ1_3_CAM_B_FIELD (0x3 << 12) +#define S5PV210_GPJ1_4_CAM_B_CLKOUT (0x3 << 16) + +#endif /* __ASM_PLAT_REGS_FIMC_H */ diff --git a/arch/arm/plat-s5p/include/plat/regs-iis.h b/arch/arm/plat-s5p/include/plat/regs-iis.h new file mode 100644 index 0000000..db94a13 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-iis.h @@ -0,0 +1,147 @@ +/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h + * + * Copyright 2007 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2412 IIS register definition +*/ + +#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H +#define __ASM_ARCH_REGS_S3C2412_IIS_H + +#define S3C2412_IISCON (0x00) +#define S3C2412_IISMOD (0x04) +#define S3C2412_IISFIC (0x08) +#define S3C2412_IISPSR (0x0C) +#define S3C2412_IISTXD (0x10) +#define S3C2412_IISRXD (0x14) +#define S5P_IISFICS (0x18) +#define S5P_IISTXDS (0x1C) +#define S5P_IISAHB (0x20) +#define S5P_IISSTR (0x24) +#define S5P_IISSIZE (0x28) +#define S5P_IISTRNCNT (0x2C) +#define S5P_IISADDR0 (0x30) +#define S5P_IISADDR1 (0x34) +#define S5P_IISADDR2 (0x38) +#define S5P_IISADDR3 (0x3C) + +#define S5P_IISCON_FTXSURSTAT (1 << 24) +#define S5P_IISCON_FTXSURINTEN (1 << 23) +#define S5P_IISCON_TXSDMAPAUSE (1 << 20) +#define S5P_IISCON_TXSDMACTIVE (1 << 18) +#define S5P_IISCON_FTXURSTATUS (1 << 17) +#define S5P_IISCON_FTXURINTEN (1 << 16) + +#define S3C2412_IISCON_LRINDEX (1 << 11) +#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10) +#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9) +#define S3C2412_IISCON_TXFIFO_FULL (1 << 8) +#define S3C2412_IISCON_RXFIFO_FULL (1 << 7) +#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6) +#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5) +#define S3C2412_IISCON_TXCH_PAUSE (1 << 4) +#define S3C2412_IISCON_RXCH_PAUSE (1 << 3) +#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2) +#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1) +#define S3C2412_IISCON_IIS_ACTIVE (1 << 0) + +#define S3C64XX_IISMOD_OPPCLK (3<<30) + +#define S5P_IISMOD_TXSLP (1<<28) +#define S5P_IISMOD_BLCPMASK (3<<24) +#define S5P_IISMOD_BLCSMASK (3<<26) + +#define S3C64XX_IISMOD_BLC_16BIT (0 << 13) +#define S3C64XX_IISMOD_BLC_8BIT (1 << 13) +#define S3C64XX_IISMOD_BLC_24BIT (2 << 13) +#define S3C64XX_IISMOD_BLC_MASK (3 << 13) + +#define S3C64XX_IISMOD_IMSMASK (3 << 10) +#define S3C64XX_IISMOD_IMS_PCLK (0 << 10) +#define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10) +#define S3C64XX_CLKSRC_I2SEXT (3 << 10) +#define S3C64XX_CDCLKSRC_EXT (5 << 10) + +#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10) +#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10) +#define S3C2412_IISMOD_SLAVE (2 << 10) +#define S3C2412_IISMOD_MASTER_MASK (3 << 10) +#define S3C2412_IISMOD_MODE_TXONLY (0 << 8) +#define S3C2412_IISMOD_MODE_RXONLY (1 << 8) +#define S3C2412_IISMOD_MODE_TXRX (2 << 8) +#define S3C2412_IISMOD_MODE_MASK (3 << 8) +#define S3C2412_IISMOD_LR_LLOW (0 << 7) +#define S3C2412_IISMOD_LR_RLOW (1 << 7) +#define S3C2412_IISMOD_SDF_IIS (0 << 5) +#define S3C2412_IISMOD_SDF_MSB (1 << 5) +#define S3C2412_IISMOD_SDF_LSB (2 << 5) +#define S3C2412_IISMOD_SDF_MASK (3 << 5) +#define S3C2412_IISMOD_RCLK_256FS (0 << 3) +#define S3C2412_IISMOD_RCLK_512FS (1 << 3) +#define S3C2412_IISMOD_RCLK_384FS (2 << 3) +#define S3C2412_IISMOD_RCLK_768FS (3 << 3) +#define S3C2412_IISMOD_RCLK_MASK (3 << 3) +#define S3C2412_IISMOD_BCLK_32FS (0 << 1) +#define S3C2412_IISMOD_BCLK_48FS (1 << 1) +#define S3C2412_IISMOD_BCLK_16FS (2 << 1) +#define S3C2412_IISMOD_BCLK_24FS (3 << 1) +#define S3C2412_IISMOD_BCLK_MASK (3 << 1) +#define S3C2412_IISMOD_8BIT (1 << 0) + +#define S3C64XX_IISMOD_CDCLKCON (1 << 12) + +#define S3C2412_IISPSR_PSREN (1 << 15) + +#define S3C2412_IISFIC_TXFLUSH (1 << 15) +#define S3C2412_IISFIC_RXFLUSH (1 << 7) +#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf) +#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf) + +#define S5P_IISAHB_INTENLVL3 (1<<27) +#define S5P_IISAHB_INTENLVL2 (1<<26) +#define S5P_IISAHB_INTENLVL1 (1<<25) +#define S5P_IISAHB_INTENLVL0 (1<<24) +#define S5P_IISAHB_LVL3INT (1<<23) +#define S5P_IISAHB_LVL2INT (1<<22) +#define S5P_IISAHB_LVL1INT (1<<21) +#define S5P_IISAHB_LVL0INT (1<<20) +#define S5P_IISAHB_CLRLVL3 (1<<19) +#define S5P_IISAHB_CLRLVL2 (1<<18) +#define S5P_IISAHB_CLRLVL1 (1<<17) +#define S5P_IISAHB_CLRLVL0 (1<<16) +#define S5P_IISAHB_DMARLD (1<<5) +#define S5P_IISAHB_DISRLDINT (1<<3) +#define S5P_IISAHB_DMAEND (1<<2) +#define S5P_IISAHB_DMACLR (1<<1) +#define S5P_IISAHB_DMAEN (1<<0) + +#define S5P_IISSIZE_SHIFT (16) +#define S5P_IISSIZE_TRNMSK (0xffff) +#define S5P_IISTRNCNT_MASK (0xffffff) + +#define S5P_IISADDR_MASK (0x3fffff) +#define S5P_IISADDR_SHIFT (10) +#define S5P_IISADDR_ENSTOP (1<<0) + +/* clock sources */ +#define S3C_IISMOD_IMSMASK (3<<10) +#define S3C_IISMOD_MSTPCLK (0<<10) +#define S3C_IISMOD_MSTCLKAUDIO (1<<10) +#define S3C_IISMOD_SLVPCLK (2<<10) +#define S3C_IISMOD_SLVI2SCLK (3<<10) + +#define S3C_CLKSRC_PCLK S3C_IISMOD_MSTPCLK +#define S3C_CLKSRC_CLKAUDIO S3C_IISMOD_MSTCLKAUDIO +#define S3C_CLKSRC_SLVPCLK S3C_IISMOD_SLVPCLK +#define S3C_CLKSRC_I2SEXT S3C_IISMOD_SLVI2SCLK +#define S3C_CDCLKSRC_INT (4<<10) +#define S3C_CDCLKSRC_EXT (5<<10) + + +#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */ + diff --git a/arch/arm/plat-s5p/include/plat/regs-ipc.h b/arch/arm/plat-s5p/include/plat/regs-ipc.h new file mode 100644 index 0000000..4d1172a --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-ipc.h @@ -0,0 +1,147 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-ipc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Register definition file for IPC driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_IPC_H +#define _REGS_IPC_H + +#define S3C_IPCREG(x) (x) + +#define IPC_2D_ENABLE 0x10000 +#define IPC_HOR_SCALING_ENABLE 0x8000 + +/************************************************************************* + * Registers + ************************************************************************/ +#define S3C_IPC_ENABLE S3C_IPCREG(0x00) +#define S3C_IPC_SRESET S3C_IPCREG(0x04) +#define S3C_IPC_SHADOW_UPDATE S3C_IPCREG(0x08) +#define S3C_IPC_FIELD_ID S3C_IPCREG(0x0c) +#define S3C_IPC_MODE S3C_IPCREG(0x10) +#define S3C_IPC_PEL_RATE_CTRL S3C_IPCREG(0x1C) +#define S3C_IPC_ENDIAN_MODE S3C_IPCREG(0x3C) +#define S3C_IPC_SRC_WIDTH S3C_IPCREG(0x4C) +#define S3C_IPC_SRC_HEIGHT S3C_IPCREG(0x50) +#define S3C_IPC_DST_WIDTH S3C_IPCREG(0x5C) +#define S3C_IPC_DST_HEIGHT S3C_IPCREG(0x60) +#define S3C_IPC_H_RATIO S3C_IPCREG(0x64) +#define S3C_IPC_V_RATIO S3C_IPCREG(0x68) + +#define S3C_IPC_POLY8_Y0_LL S3C_IPCREG(0x6C) +#define S3C_IPC_POLY8_Y0_LH S3C_IPCREG(0x70) +#define S3C_IPC_POLY8_Y0_HL S3C_IPCREG(0x74) +#define S3C_IPC_POLY8_Y0_HH S3C_IPCREG(0x78) +#define S3C_IPC_POLY8_Y1_LL S3C_IPCREG(0x7C) +#define S3C_IPC_POLY8_Y1_LH S3C_IPCREG(0x80) +#define S3C_IPC_POLY8_Y1_HL S3C_IPCREG(0x84) +#define S3C_IPC_POLY8_Y1_HH S3C_IPCREG(0x88) +#define S3C_IPC_POLY8_Y2_LL S3C_IPCREG(0x8C) +#define S3C_IPC_POLY8_Y2_LH S3C_IPCREG(0x90) +#define S3C_IPC_POLY8_Y2_HL S3C_IPCREG(0x94) +#define S3C_IPC_POLY8_Y2_HH S3C_IPCREG(0x98) +#define S3C_IPC_POLY8_Y3_LL S3C_IPCREG(0x9C) +#define S3C_IPC_POLY8_Y3_LH S3C_IPCREG(0xA0) +#define S3C_IPC_POLY8_Y3_HL S3C_IPCREG(0xA4) +#define S3C_IPC_POLY8_Y3_HH S3C_IPCREG(0xA8) +#define S3C_IPC_POLY4_Y0_LL S3C_IPCREG(0xEC) +#define S3C_IPC_POLY4_Y0_LH S3C_IPCREG(0xF0) +#define S3C_IPC_POLY4_Y0_HL S3C_IPCREG(0xF4) +#define S3C_IPC_POLY4_Y0_HH S3C_IPCREG(0xF8) +#define S3C_IPC_POLY4_Y1_LL S3C_IPCREG(0xFC) +#define S3C_IPC_POLY4_Y1_LH S3C_IPCREG(0x100) +#define S3C_IPC_POLY4_Y1_HL S3C_IPCREG(0x104) +#define S3C_IPC_POLY4_Y1_HH S3C_IPCREG(0x108) +#define S3C_IPC_POLY4_Y2_LL S3C_IPCREG(0x10C) +#define S3C_IPC_POLY4_Y2_LH S3C_IPCREG(0x110) +#define S3C_IPC_POLY4_Y2_HL S3C_IPCREG(0x114) +#define S3C_IPC_POLY4_Y2_HH S3C_IPCREG(0x118) +#define S3C_IPC_POLY4_Y3_LL S3C_IPCREG(0x11C) +#define S3C_IPC_POLY4_Y3_LH S3C_IPCREG(0x120) +#define S3C_IPC_POLY4_Y3_HL S3C_IPCREG(0x124) +#define S3C_IPC_POLY4_Y3_HH S3C_IPCREG(0x128) +#define S3C_IPC_POLY4_C0_LL S3C_IPCREG(0x12C) +#define S3C_IPC_POLY4_C0_LH S3C_IPCREG(0x130) +#define S3C_IPC_POLY4_C0_HL S3C_IPCREG(0x134) +#define S3C_IPC_POLY4_C0_HH S3C_IPCREG(0x138) +#define S3C_IPC_POLY4_C1_LL S3C_IPCREG(0x13C) +#define S3C_IPC_POLY4_C1_LH S3C_IPCREG(0x140) +#define S3C_IPC_POLY4_C1_HL S3C_IPCREG(0x144) +#define S3C_IPC_POLY4_C1_HH S3C_IPCREG(0x148) +#define S3C_IPC_BYPASS S3C_IPCREG(0x200) +#define S3C_IPC_PP_SATURATION S3C_IPCREG(0x20C) +#define S3C_IPC_PP_SHARPNESS S3C_IPCREG(0x210) +#define S3C_IPC_PP_LINE_EQ0 S3C_IPCREG(0x218) +#define S3C_IPC_PP_LINE_EQ1 S3C_IPCREG(0x21C) +#define S3C_IPC_PP_LINE_EQ2 S3C_IPCREG(0x220) +#define S3C_IPC_PP_LINE_EQ3 S3C_IPCREG(0x224) +#define S3C_IPC_PP_LINE_EQ4 S3C_IPCREG(0x228) +#define S3C_IPC_PP_LINE_EQ5 S3C_IPCREG(0x22C) +#define S3C_IPC_PP_LINE_EQ6 S3C_IPCREG(0x230) +#define S3C_IPC_PP_LINE_EQ7 S3C_IPCREG(0x234) +#define S3C_IPC_PP_BRIGHT_OFFSET S3C_IPCREG(0x238) +#define S3C_IPC_VERSION_INFO S3C_IPCREG(0x3FC) + +/* Bit Definitions + ************************************************************************/ +/* ENABLE/DISABLE CONTROL */ +#define S3C_IPC_ON (1 << 0) +#define S3C_IPC_OFF (0 << 0) + +/* SOFTWARE RESET */ +#define S3C_IPC_SRESET_ENABLE (1 << 0) +#define S3C_IPC_SRESET_MASK (1 << 0) + +/* SHADOW UPDATE ENABLE CONTROL */ +#define S3C_IPC_SHADOW_UPDATE_ENABLE (1 << 0) +#define S3C_IPC_SHADOW_UPDATE_DISABLE (0 << 0) + +/* OPERATION MODE CONTROL */ +#define S3C_IPC_2D_ENABLE (1 << 0) +#define S3C_IPC_2D_DISABLE (0 << 0) +#define S3C_IPC_2D_MASK (1 << 1) + +/* VERTICAL SCALER PIXEL RATE CONTROL */ +#define S3C_IPC_PEL_RATE_SET (0 << 0) + +/* HORIZONTAL ZOOM RATIO */ +#define S3C_IPC_H_RATIO_MASK (0x7fff << 0) +#define S3C_IPC_V_RATIO_MASK (0x7fff << 0) + +/* POST PROCESSING IMAGE BYPASS MODE CONTROL */ +#define S3C_IPC_PP_BYPASS_ENABLE (0 << 0) +#define S3C_IPC_PP_BYPASS_DISABLE (1 << 0) +#define S3C_IPC_PP_BYPASS_MASK (1 << 0) + +/* BRIGHTNESS AND CONTRAST CONTROL */ +#define S3C_IPC_PP_LINE_CONTRAST_MASK (0xff << 0) +#define S3C_IPC_PP_LINE_BRIGTHNESS_MASK (0xffff << 8) + +/*************************************************************************/ +/* Macro part */ +/*************************************************************************/ +#define S3C_IPC_FIELD_ID_SELECTION(x) ((x) << 6) +#define S3C_IPC_FIELD_ID_AUTO_TOGGLING(x) ((x) << 2) +#define S3C_IPC_2D_CTRL(x) ((x) << 1) +#define S3C_IPC_SRC_WIDTH_SET(x) ((x) & 0x7ff << 0) +#define S3C_IPC_SRC_HEIGHT_SET(x) ((x) & 0x3ff << 0) +#define S3C_IPC_DST_WIDTH_SET(x) ((x) & 0x7ff << 0) +#define S3C_IPC_DST_HEIGHT_SET(x) ((x) & 0x3ff << 0) +#define S3C_IPC_PP_SATURATION_SET(x) ((x) & 0xff << 0) +#define S3C_IPC_PP_TH_HNOISE_SET(x) ((x) & 0xff << 8) +#define S3C_IPC_PP_SHARPNESS_SET(x) ((x) & 0x3 << 8) +#define S3C_IPC_PP_BRIGHT_OFFSET_SET(x) ((x) & 0x1ff << 8) +#define S3C_IPC_PP_LINE_CONTRAST(x)\ + (((x) & S3C_IPC_PP_LINE_CONTRAST_MASK) << 0) +#define S3C_IPC_PP_LINE_BRIGHT(x)\ + (((x) & S3C_IPC_PP_LINE_BRIGTHNESS_MASK) << 8) + +#endif /* _REGS_IPC_H */ + diff --git a/arch/arm/plat-s5p/include/plat/regs-mfc.h b/arch/arm/plat-s5p/include/plat/regs-mfc.h new file mode 100644 index 0000000..1cecb53 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-mfc.h @@ -0,0 +1,256 @@ +/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h + * + * Register definition file for Samsung MFC V5.0 Interface (FIMV) driver + * + * Jaeryul Oh, Copyright (c) 2009 Samsung Electronics + * http://www.samsungsemi.com/ + * + * history: + * 2009.09.14 : Delete MFC v4.0 codes & rewrite defintion (Key-Young, Park) + * 2009.10.08 - Apply 9/30 firmware(Key Young, Park) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_FIMV_H +#define _REGS_FIMV_H + +#if defined(CONFIG_CPU_S5PV210) +#define MFC_REG(x) (x) +#define MFC_START_ADDR MFC_REG(0x0000) +#define MFC_END_ADDR MFC_REG(0xe008 + 4) +#define MFC_REG_SIZE (MFC_END_ADDR - MFC_START_ADDR) +#define MFC_REG_COUNT ((MFC_END_ADDR - MFC_START_ADDR) / 4) + +/*====================================================================================================*/ +/* MFC Core Control Register */ +/*====================================================================================================*/ +#define MFC_SW_RESET MFC_REG(0x0000) /* MFC Software Reset Register */ +#define MFC_RISC_HOST_INT MFC_REG(0x0008) /* RISC to HOST Interrupt Reigser */ + +#define MFC_HOST2RISC_COMMAND MFC_REG(0x0030) /* HOST to RISC Command Register */ +#define MFC_HOST2RISC_ARG1 MFC_REG(0x0034) /* first argument register */ +#define MFC_HOST2RISC_ARG2 MFC_REG(0x0038) /* second argument register */ +#define MFC_HOST2RISC_ARG3 MFC_REG(0x003c) /* third argument register */ +#define MFC_HOST2RISC_ARG4 MFC_REG(0x0040) /* fourth argument register */ + +#define MFC_RISC2HOST_COMMAND MFC_REG(0x0044) /* RISC to HOST Command Register */ +#define MFC_RISC2HOST_ARG1 MFC_REG(0x0048) /* first argument register */ +#define MFC_RISC2HOST_ARG2 MFC_REG(0x004c) /* second argument register */ +#define MFC_RISC2HOST_ARG3 MFC_REG(0x0050) /* third argument register */ +#define MFC_RISC2HOST_ARG4 MFC_REG(0x0054) /* fourth argument register */ + +#define MFC_FW_VERSION MFC_REG(0x0058) /* firmware version register */ +#define MFC_FW_STATUS MFC_REG(0x0080) /* 0: Not ready, 1: Ready */ + + +/*====================================================================================================*/ +/* Memory Controller Register */ +/*====================================================================================================*/ +#define MFC_MC_DRAMBASE_ADDR_A MFC_REG(0x0508) /* Port A DRAM base address */ +#define MFC_MC_DRAMBASE_ADDR_B MFC_REG(0x050c) /* Port B DRAM base address */ +#define MFC_MC_STATUS MFC_REG(0x0510) /* Bus arbiter's status */ + + +/*====================================================================================================*/ +/* Common Address Control */ +/*====================================================================================================*/ +/*----------------------------------------------------------------------------------------------------*/ +/* H264 Decoder Buffer Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_H264DEC_VERT_NB_MV MFC_REG(0x068c) /* Base:35, vertical neighbor motion vector */ +#define MFC_H264DEC_NB_IP MFC_REG(0x0690) /* Base:36, neighbor pixels for intra pred */ +#define MFC_H264DEC_LUMA MFC_REG(0x0700) /* Base:64, Luma0 ~ Luma31 */ +#define MFC_H264DEC_CHROMA MFC_REG(0x0600) /* Base:0, Chroma0 ~ Chroma31 */ +#define MFC_H264DEC_MV MFC_REG(0x0780) /* Base:96, Mv0 ~ Mv31 */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Other Decoder Buffer Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_NB_DCAC MFC_REG(0x068c) /* Base:35, neighbor AC/DC coeff. buffer */ +#define MFC_UPNB_MV MFC_REG(0x0690) /* Base:36, upper neighbor motion vector buffer */ +#define MFC_SUB_ANCHOR_MV MFC_REG(0x0694) /* Base:37, subseq. anchor motion vector buffer */ +#define MFC_OVERLAP_TRANSFORM MFC_REG(0x0698) /* Base:38, overlap transform line buffer */ +#define MFC_STX_PARSER MFC_REG(0x06A8) /* Base:42, syntax parser addr */ +#define MFC_DEC_LUMA MFC_REG(0x0700) /* Base:64, Luma0 ~ Luma5 */ +#define MFC_DEC_CHROMA MFC_REG(0x0600) /* Base:0, Chroma0 ~ Chroma5 */ +#define MFC_BITPLANE1 MFC_REG(0x06A4) /* Base:41, bitplane1 addr */ +#define MFC_BITPLANE2 MFC_REG(0x06A0) /* Base:40, bitplane2 addr */ +#define MFC_BITPLANE3 MFC_REG(0x069C) /* Base:39, bitplane3 addr */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Encoder Buffer Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_UPPER_MV_ADDR MFC_REG(0x0600) /* Base:0, upper motion vector addr */ +#define MFC_DIRECT_COLZERO_FLAG_ADDR MFC_REG(0x0610) /* Base:4, direct cozero flag addr */ +#define MFC_UPPER_INTRA_MD_ADDR MFC_REG(0x0608) /* Base:2, upper intra MD addr */ +#define MFC_UPPER_INTRA_PRED_ADDR MFC_REG(0x0740) /* Base:80, upper intra PRED addr */ +#define MFC_NBOR_INFO_MPENC_ADDR MFC_REG(0x0604) /* Base:1, entropy engine's AC/DC coeff. */ +#define MFC_ACDC_COEF_BASE_ADDR MFC_REG(0x0604) /* Base:1, entropy engine's AC/DC coeff. */ +#define MFC_ENC_DPB_Y0_ADDR MFC_REG(0x061C) /* Base:7, ref0 Luma addr */ +#define MFC_ENC_DPB_C0_ADDR MFC_REG(0x0700) /* Base:64, ref0 Chroma addr */ +#define MFC_ENC_DPB_Y1_ADDR MFC_REG(0x0620) /* Base:8, ref1 Luma addr */ +#define MFC_ENC_DPB_C1_ADDR MFC_REG(0x0704) /* Base:65, ref1 Chroma addr */ +#define MFC_ENC_DPB_Y2_ADDR MFC_REG(0x0710) /* Base:68, ref2 Luma addr */ +#define MFC_ENC_DPB_C2_ADDR MFC_REG(0x0708) /* Base:66, ref2 Chroma addr */ +#define MFC_ENC_DPB_Y3_ADDR MFC_REG(0x0714) /* Base:69, ref3 Luma addr */ +#define MFC_ENC_DPB_C3_ADDR MFC_REG(0x070c) /* Base:67, ref3 Chroma addr */ + + +/*====================================================================================================*/ +/* Channel & Stream Interface Register */ +/*====================================================================================================*/ +#define MFC_HSIZE_PX MFC_REG(0x0818) /* frame width at encoder */ +#define MFC_VSIZE_PX MFC_REG(0x081c) /* frame height at encoder */ +#define MFC_PROFILE MFC_REG(0x0830) /* profile register */ +#define MFC_PICTURE_STRUCT MFC_REG(0x083c) /* picture field/frame flag */ +#define MFC_LF_CONTROL MFC_REG(0x0848) /* loop filter control */ +#define MFC_LF_ALPHA_OFF MFC_REG(0x084c) /* H.264 loop filter alpha offset */ +#define MFC_LF_BETA_OFF MFC_REG(0x0850) /* H.264 loop filter beta offset */ +#define MFC_QP_OFFSET MFC_REG(0x0c30) /* QP information offset from the DPB address */ +#define MFC_QP_OUT_EN MFC_REG(0x0c34) /* QP infomration enable at decoder */ + + +/*====================================================================================================*/ +/* Channel & Stream Interface Register */ +/*====================================================================================================*/ +#define MFC_SI_RTN_CHID MFC_REG(0x2000) /* Return CH instance ID register */ +#define MFC_SI_CH0_INST_ID MFC_REG(0x2040) /* CH0 instance ID and control register */ +#define MFC_SI_CH1_INST_ID MFC_REG(0x2080) /* CH1 instance ID and control register */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Decoder Channel and Stream Interface Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_SI_VER_RESOL MFC_REG(0x2004) /* vertical resolution of decoder */ +#define MFC_SI_HOR_RESOL MFC_REG(0x2008) /* horizontal resolution of decoder */ +#define MFC_SI_MIN_NUM_DPB MFC_REG(0x200c) /* number of frames in the decoded pic */ +#define MFC_SI_DISPLAY_Y_ADR MFC_REG(0x2010) /* luma address of displayed pic */ +#define MFC_SI_DISPLAY_C_ADR MFC_REG(0x2014) /* chroma address of displayed pic */ +#define MFC_SI_DEC_FRM_SIZE MFC_REG(0x2018) /* consumed number of bytes to decode a frame */ +#define MFC_SI_DISPLAY_STATUS MFC_REG(0x201c) /* status of displayed picture */ +#define MFC_SI_FRAME_TYPE MFC_REG(0x2020) /* frame type such as skip/I/P/B */ +#define MFC_SI_DECODE_Y_ADR MFC_REG(0x2024) /* luma address of decoded pic */ +#define MFC_SI_DECODE_C_ADR MFC_REG(0x2028) /* chroma address of decoded pic */ +#define MFC_SI_DECODE_STATUS MFC_REG(0x202c) /* status of decoded picture */ + +#define MFC_SI_CH0_ES_ADDR MFC_REG(0x2044) /* start addr of stream buf */ +#define MFC_SI_CH0_ES_DEC_UNIT_SIZE MFC_REG(0x2048) /* size of stream buf */ +#define MFC_SI_CH0_DESC_ADDR MFC_REG(0x204c) /* addr of descriptor buf */ +#define MFC_SI_CH0_FIMV1_VRESOL MFC_REG(0x2050) /* horizontal resolution */ +#define MFC_SI_CH0_FIMV1_HRESOL MFC_REG(0x2054) /* vertical resolution */ +#define MFC_SI_CH0_CPB_SIZE MFC_REG(0x2058) /* max size of coded pic. buf */ +#define MFC_SI_CH0_DESC_SIZE MFC_REG(0x205c) /* max size of descriptor buf */ +#define MFC_SI_CH0_RELEASE_BUFFER MFC_REG(0x2060) /* specifices the availability of each DPB */ +#define MFC_SI_CH0_HOST_WR_ADR MFC_REG(0x2064) /* start addr of shared memory */ +#define MFC_SI_CH0_DPB_CONFIG_CTRL MFC_REG(0x2068) /* DPB configuarion control */ +#define MFC_SI_CH0_CMD_SEQ_NUM MFC_REG(0x206c) /* Command sequence number from the host */ + +#define MFC_SI_CH1_ES_ADDR MFC_REG(0x2084) /* start addr of stream buf */ +#define MFC_SI_CH1_ES_DEC_UNIT_SIZE MFC_REG(0x2088) /* size of stream buf */ +#define MFC_SI_CH1_DESC_ADDR MFC_REG(0x208c) /* addr of descriptor buf */ +#define MFC_SI_CH1_FIMV1_VRESOL MFC_REG(0x2090) /* horizontal resolution */ +#define MFC_SI_CH1_FIMV1_HRESOL MFC_REG(0x2094) /* vertical resolution */ +#define MFC_SI_CH1_CPB_SIZE MFC_REG(0x2098) /* max size of coded pic. buf */ +#define MFC_SI_CH1_DESC_SIZE MFC_REG(0x209c) /* max size of descriptor buf */ +#define MFC_SI_CH1_RELEASE_BUFFER MFC_REG(0x20a0) /* specifices the availability of each DPB */ +#define MFC_SI_CH1_HOST_WR_ADR MFC_REG(0x20a4) /* start addr of shared memory */ +#define MFC_SI_CH1_DPB_CONFIG_CTRL MFC_REG(0x20a8) /* DPB configuarion control */ +#define MFC_SI_CH1_CMD_SEQ_NUM MFC_REG(0x20ac) /* Command sequence number from the host */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Encoder Channel and Stream Interface Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_CRC_LUMA0 MFC_REG(0x2030) /* luma crc data per frame(or top field) */ +#define MFC_CRC_CHROMA0 MFC_REG(0x2034) /* chroma crc data per frame(or top field) */ +#define MFC_CRC_LUMA1 MFC_REG(0x2038) /* luma crc data per bottom field */ +#define MFC_CRC_CHROMA1 MFC_REG(0x203c) /* chroma crc data per bottom field */ + +#define MFC_SI_ENC_STREAM_SIZE MFC_REG(0x2004) /* stream size */ +#define MFC_SI_ENC_PICTURE_CNT MFC_REG(0x2008) /* picture count */ +#define MFC_SI_WRITE_POINTER MFC_REG(0x200c) /* stream buffer write pointer */ +#define MFC_SI_ENC_SLICE_TYPE MFC_REG(0x2010) /* slice type(I/P/B/IDR) */ +#define MFC_SI_ENCODED_Y_ADDR MFC_REG(0x2014) /* address of the encoded luminance picture */ +#define MFC_SI_ENCODED_C_ADDR MFC_REG(0x2018) /* address of the encoded chroma address */ + +#define MFC_SI_CH0_SB_U_ADDR MFC_REG(0x2044) /* addr of upper stream buf */ +#define MFC_SI_CH0_SB_L_ADDR MFC_REG(0x2048) /* addr of lower stream buf */ +#define MFC_SI_CH0_BUFFER_SIZE MFC_REG(0x204c) /* size of stream buf */ +#define MFC_SI_CH0_CURRENT_Y_ADDR MFC_REG(0x2050) /* current Luma addr */ +#define MFC_SI_CH0_CURRENT_C_ADDR MFC_REG(0x2054) /* current Chroma addr */ +#define MFC_SI_CH0_ENC_PARA MFC_REG(0x2058) /* frame insertion control register */ + +#define MFC_SI_CH1_SB_U_ADDR MFC_REG(0x2084) /* addr of upper stream buf */ +#define MFC_SI_CH1_SB_L_ADDR MFC_REG(0x2088) /* addr of lower stream buf */ +#define MFC_SI_CH1_BUFFER_SIZE MFC_REG(0x208c) /* size of stream buf */ +#define MFC_SI_CH1_CURRENT_Y_ADDR MFC_REG(0x2090) /* current Luma addr */ +#define MFC_SI_CH1_CURRENT_C_ADDR MFC_REG(0x2094) /* current Chroma addr */ +#define MFC_SI_CH1_ENC_PARA MFC_REG(0x2098) /* frame insertion control register */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Encoded Data Formatter Unit Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_STR_BF_U_FULL MFC_REG(0xc004) /* upper stream buf full status */ +#define MFC_STR_BF_U_EMPTY MFC_REG(0xc008) /* upper stream buf empty status */ +#define MFC_STR_BF_L_FULL MFC_REG(0xc00c) /* lower stream buf full status */ +#define MFC_STR_BF_L_EMPTY MFC_REG(0xc010) /* lower stream buf empty status */ +#define MFC_STR_BF_STATUS MFC_REG(0xc018) /* stream buf interrupt status */ +#define MFC_EDFU_SF_EPB_ON_CTRL MFC_REG(0xc054) /* EDFU stream control */ +#define MFC_EDFU_SF_BUF_CTRL MFC_REG(0xc058) /* EDFU buffer control */ +#define MFC_STR_BF_MODE_CTRL MFC_REG(0xc05c) /* stream buffer mode control */ + + +/*====================================================================================================*/ +/* Encoding Registers */ +/*====================================================================================================*/ +/*----------------------------------------------------------------------------------------------------*/ +/* Common Encoder Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_RC_CONTROL_CONFIG MFC_REG(0x00a0) /* Rate Control Configuration */ +#define MFC_ENC_PIC_TYPE_CTRL MFC_REG(0xc504) /* pic type level control */ +#define MFC_ENC_B_RECON_WRITE_ON MFC_REG(0xc508) /* B frame recon data write cotrl */ +#define MFC_ENC_MSLICE_CTRL MFC_REG(0xc50c) /* multi slice control */ +#define MFC_ENC_MSLICE_MB MFC_REG(0xc510) /* MB number in the one slice */ +#define MFC_ENC_MSLICE_BYTE MFC_REG(0xc514) /* byte count number for one slice */ +#define MFC_ENC_CIR_CTRL MFC_REG(0xc518) /* number of intra refresh MB */ +#define MFC_ENC_MAP_FOR_CUR MFC_REG(0xc51c) /* linear or 64x32 tiled mode */ +#define MFC_ENC_PADDING_CTRL MFC_REG(0xc520) /* padding control */ +#define MFC_ENC_INT_MASK MFC_REG(0xc528) /* interrupt mask */ +#define MFC_ENC_COMMON_INTRA_BIAS MFC_REG(0xc528) /* intra mode bias register */ +#define MFC_ENC_COMMON_BI_DIRECT_BIAS MFC_REG(0xc528) /* bi-directional mode bias register */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Rate Control Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_RC_CONFIG MFC_REG(0xc5a0) /* RC config */ +#define MFC_RC_FRAME_RATE MFC_REG(0xc5a4) /* frame rate */ +#define MFC_RC_BIT_RATE MFC_REG(0xc5a8) /* bit rate */ +#define MFC_RC_QBOUND MFC_REG(0xc5ac) /* max/min QP */ +#define MFC_RC_RPARA MFC_REG(0xc5b0) /* rate control reaction coeff. */ +#define MFC_RC_MB_CTRL MFC_REG(0xc5b4) /* MB adaptive scaling */ + +/*----------------------------------------------------------------------------------------------------*/ +/* H.264 Encoder Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_H264_ENC_ENTRP_MODE MFC_REG(0xd004) /* CAVLC or CABAC */ +#define MFC_H264_ENC_NUM_OF_REF MFC_REG(0xd010) /* number of reference for P/B */ +#define MFC_H264_ENC_MDINTER_WEIGHT MFC_REG(0xd01c) /* inter weighted parameter */ +#define MFC_H264_ENC_MDINTRA_WEIGHT MFC_REG(0xd020) /* intra weighted parameter */ +#define MFC_H264_ENC_TRANS_8X8_FLAG MFC_REG(0xd034) /* 8x8 transform flag in PPS & high profile */ + +/*----------------------------------------------------------------------------------------------------*/ +/* MPEG4 Encoder Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_MPEG4_ENC_QUART_PXL MFC_REG(0xe008) /* quarter pel interpolation control */ + + +/*====================================================================================================*/ +/* Etc Registers */ +/*====================================================================================================*/ +#define MFC_NUM_MASTER MFC_REG(0x0b14) /* Number of master port */ + +//#define MFC_SI_DEC_FRM_SIZE MFC_REG(0x2018) +#endif /* CONFIG_CPU_S5PC1xx */ + +#endif diff --git a/arch/arm/plat-s5p/include/plat/regs-systimer.h b/arch/arm/plat-s5p/include/plat/regs-systimer.h new file mode 100644 index 0000000..7091c40 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-systimer.h @@ -0,0 +1,77 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-systimer.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P System Timer Driver Header information + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_REGS_SYSTIMER_H +#define __ASM_PLAT_REGS_SYSTIMER_H __FILE__ + +#define S5P_SYSTIMERREG(x) (S5P_VA_SYSTIMER + (x)) + +#define S5P_SYSTIMER_TCFG S5P_SYSTIMERREG(0x00) +#define S5P_SYSTIMER_TCON S5P_SYSTIMERREG(0x04) +#define S5P_SYSTIMER_TICNTB S5P_SYSTIMERREG(0x08) +#define S5P_SYSTIMER_TICNTO S5P_SYSTIMERREG(0x0c) +#define S5P_SYSTIMER_TFCNTB S5P_SYSTIMERREG(0x10) +#define S5P_SYSTIMER_ICNTB S5P_SYSTIMERREG(0x18) +#define S5P_SYSTIMER_ICNTO S5P_SYSTIMERREG(0x1c) +#define S5P_SYSTIMER_INT_CSTAT S5P_SYSTIMERREG(0x20) + +/* Value for TCFG */ + +#define S5P_SYSTIMER_SWRST (1<<16) + +#define S5P_SYSTIMER_DIV_GEN (0<<15) +#define S5P_SYSTIMER_DIV_RTC (1<<15) + +#define S5P_SYSTIMER_TICK_INT (0<<14) +#define S5P_SYSTIMER_TICK_FRA (1<<14) + +#define S5P_SYSTIMER_TCLK_MASK (3<<12) +#define S5P_SYSTIMER_TCLK_XXTI (0<<12) +#define S5P_SYSTIMER_TCLK_RTC (1<<12) +#define S5P_SYSTIMER_TCLK_USB (2<<12) +#define S5P_SYSTIMER_TCLK_PCLK (3<<12) + +#define S5P_SYSTIMER_DIV_MASK (7<<8) +#define S5P_SYSTIMER_DIV_1 (0<<8) +#define S5P_SYSTIMER_DIV_2 (1<<8) +#define S5P_SYSTIMER_DIV_4 (2<<8) +#define S5P_SYSTIMER_DIV_8 (3<<8) +#define S5P_SYSTIMER_DIV_16 (4<<8) + +#define S5P_SYSTIMER_TARGET_HZ 200 +#define S5P_SYSTIMER_PRESCALER 5 +#define S5P_SYSTIMER_PRESCALER_MASK (0x3f<<0) + +/* value for TCON */ + +#define S5P_SYSTIMER_INT_AUTO (1<<5) +#define S5P_SYSTIMER_INT_IMM (1<<4) +#define S5P_SYSTIMER_INT_START (1<<3) +#define S5P_SYSTIMER_AUTO_RELOAD (1<<2) +#define S5P_SYSTIMER_IMM_UPDATE (1<<1) +#define S5P_SYSTIMER_START (1<<0) + +/* Value for INT_CSTAT */ + +#define S5P_SYSTIMER_INT_TWIE (1<<10) +#define S5P_SYSTIMER_INT_IWIE (1<<9) +#define S5P_SYSTIMER_INT_TFWIE (1<<8) +#define S5P_SYSTIMER_INT_TIWIE (1<<7) +#define S5P_SYSTIMER_INT_ICNTEIE (1<<6) +#define S5P_SYSTIMER_INT_TCON (1<<5) +#define S5P_SYSTIMER_INT_ICNTB (1<<4) +#define S5P_SYSTIMER_INT_TFCNTB (1<<3) +#define S5P_SYSTIMER_INT_TICNTB (1<<2) +#define S5P_SYSTIMER_INT_INTCNT (1<<1) +#define S5P_SYSTIMER_INT_INTENABLE (1<<0) + +#endif /* __ASM_PLAT_REGS_SYSTIMER_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5p-otghost.h b/arch/arm/plat-s5p/include/plat/s5p-otghost.h new file mode 100644 index 0000000..a466c93 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p-otghost.h @@ -0,0 +1,56 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5p-otghost.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Platform header file for Samsung OTG Host driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef _PLAT_S5P_OTGHOST_H +#define _PLAT_S5P_OTGHOST_H __FILE__ + +#include <linux/wakelock.h> + +/*#define CONFIG_USB_S3C_OTG_HOST_HANDLING_CLOCK*/ +#define CONFIG_USB_S3C_OTG_HOST_DTGDRVVBUS + +union port_flags_t { + /** raw register data */ + u32 d32; + /** register bits */ + struct { + unsigned port_connect_status_change:1; + unsigned port_connect_status:1; + unsigned port_reset_change:1; + unsigned port_enable_change:1; + unsigned port_suspend_change:1; + unsigned port_over_current_change:1; + unsigned reserved:26; + } b; +}; + +struct sec_otghost_data { + bool clk_usage; + void (*set_pwr_cb)(int on); + int host_notify; + int sec_whlist_table_num; +}; + +struct sec_otghost { + spinlock_t lock; + + bool ch_halt; + bool is_hs; + union port_flags_t port_flag; + struct wake_lock wake_lock; + + struct work_struct work; + struct workqueue_struct *wq; + + struct sec_otghost_data *otg_data; +}; + +#endif /*_PLAT_S5P_OTGHOST_H */ diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h index f307f34..9e0a095 100644 --- a/arch/arm/plat-s5p/include/plat/system-reset.h +++ b/arch/arm/plat-s5p/include/plat/system-reset.h @@ -12,20 +12,6 @@ * published by the Free Software Foundation. */ -#include <plat/watchdog-reset.h> +extern void (*s5p_reset_hook)(void); -void (*s5p_reset_hook)(void); - -static void arch_reset(char mode, const char *cmd) -{ - /* SWRESET support in s5p_reset_hook() */ - - if (s5p_reset_hook) - s5p_reset_hook(); - - /* Perform reset using Watchdog reset - * if there is no s5p_reset_hook() - */ - - arch_wdt_reset(); -} +void arch_reset(char mode, const char *cmd); |