diff options
Diffstat (limited to 'arch')
159 files changed, 24279 insertions, 551 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fad8e72..ac2ef95 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -20,6 +20,7 @@ config ARM select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZO select HAVE_KERNEL_LZMA + select HAVE_KERNEL_XZ select HAVE_IRQ_WORK select HAVE_PERF_EVENTS select PERF_USE_VMALLOC @@ -749,12 +750,13 @@ config ARCH_S5PV210 bool "Samsung S5PV210/S5PC110" select CPU_V7 select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_HOLES_MEMORYMODEL select GENERIC_GPIO select HAVE_CLK select ARM_L1_CACHE_SHIFT_6 select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS - select HAVE_SCHED_CLOCK + select HAVE_SCHED_CLOCK if !S5P_HIGH_RES_TIMERS select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -1434,6 +1436,7 @@ source kernel/Kconfig.preempt config HZ int + default 256 if S5P_HIGH_RES_TIMERS default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ ARCH_S5PV210 || ARCH_EXYNOS4 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER @@ -1697,6 +1700,15 @@ config DEPRECATED_PARAM_STRUCT This was deprecated in 2001 and announced to live on for 5 years. Some old boot loaders still use this way. +config ARM_FLUSH_CONSOLE_ON_RESTART + bool "Force flush the console on restart" + help + If the console is locked while the system is rebooted, the messages + in the temporary logbuffer would not have propogated to all the + console drivers. This option forces the console lock to be + released if it failed to be acquired, which will cause all the + pending messages to be flushed. + endmenu menu "Boot options" diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 23aad07..777f70d 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -79,16 +79,17 @@ endif SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ -suffix_$(CONFIG_KERNEL_GZIP) = gzip -suffix_$(CONFIG_KERNEL_LZO) = lzo -suffix_$(CONFIG_KERNEL_LZMA) = lzma +suffix_$(CONFIG_KERNEL_GZIP) := gzip +suffix_$(CONFIG_KERNEL_LZO) := lzo +suffix_$(CONFIG_KERNEL_LZMA) := lzma +suffix_$(CONFIG_KERNEL_XZ) := xzkern targets := vmlinux vmlinux.lds \ piggy.$(suffix_y) piggy.$(suffix_y).o \ font.o font.c head.o misc.o $(OBJS) # Make sure files are removed during clean -extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S +extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern lib1funcs.S ashldi3.S ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) @@ -120,6 +121,12 @@ lib1funcs = $(obj)/lib1funcs.o $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE $(call cmd,shipped) +# For __aeabi_llsl +ashldi3 = $(obj)/ashldi3.o + +$(obj)/ashldi3.S: $(srctree)/arch/$(SRCARCH)/lib/ashldi3.S FORCE + $(call cmd,shipped) + # We need to prevent any GOTOFF relocs being used with references # to symbols in the .bss section since we cannot relocate them # independently from the rest at run time. This can be achieved by @@ -134,7 +141,7 @@ bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \ echo "$$bad_syms" >&2; rm -f $@; false ) $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ - $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE + $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) FORCE $(call if_changed,ld) @$(check_for_bad_syms) diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index 07be5a2..0ecd8b4 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -44,6 +44,10 @@ extern void error(char *); #include "../../../../lib/decompress_unlzma.c" #endif +#ifdef CONFIG_KERNEL_XZ +#include "../../../../lib/decompress_unxz.c" +#endif + int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) { return decompress(input, len, NULL, NULL, output, NULL, error); diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 940b201..e58603b 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -656,6 +656,8 @@ proc_types: @ b __arm6_mmu_cache_off @ b __armv3_mmu_cache_flush +#if !defined(CONFIG_CPU_V7) + /* This collides with some V7 IDs, preventing correct detection */ .word 0x00000000 @ old ARM ID .word 0x0000f000 mov pc, lr @@ -664,6 +666,7 @@ proc_types: THUMB( nop ) mov pc, lr THUMB( nop ) +#endif .word 0x41007000 @ ARM7/710 .word 0xfff8fe00 diff --git a/arch/arm/boot/compressed/piggy.xzkern.S b/arch/arm/boot/compressed/piggy.xzkern.S new file mode 100644 index 0000000..fc6f6a5 --- /dev/null +++ b/arch/arm/boot/compressed/piggy.xzkern.S @@ -0,0 +1,7 @@ + .section .piggydata,#alloc + .globl input_data +input_data: + .incbin "arch/arm/boot/compressed/piggy.xzkern" + .globl input_data_end +input_data_end: + diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 4b71766..6382566 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -39,3 +39,53 @@ config SHARP_PARAM config SHARP_SCOOP bool + +config FIQ_GLUE + bool + select FIQ + +config FIQ_DEBUGGER + bool "FIQ Mode Serial Debugger" + select FIQ + select FIQ_GLUE + default n + help + The FIQ serial debugger can accept commands even when the + kernel is unresponsive due to being stuck with interrupts + disabled. + + +config FIQ_DEBUGGER_NO_SLEEP + bool "Keep serial debugger active" + depends on FIQ_DEBUGGER + default n + help + Enables the serial debugger at boot. Passing + fiq_debugger.no_sleep on the kernel commandline will + override this config option. + +config FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON + bool "Don't disable wakeup IRQ when debugger is active" + depends on FIQ_DEBUGGER + default n + help + Don't disable the wakeup irq when enabling the uart clock. This will + cause extra interrupts, but it makes the serial debugger usable with + on some MSM radio builds that ignore the uart clock request in power + collapse. + +config FIQ_DEBUGGER_CONSOLE + bool "Console on FIQ Serial Debugger port" + depends on FIQ_DEBUGGER + default n + help + Enables a console so that printk messages are displayed on + the debugger serial port as the occur. + +config FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE + bool "Put the FIQ debugger into console mode by default" + depends on FIQ_DEBUGGER_CONSOLE + default n + help + If enabled, this puts the fiq debugger into console mode by default. + Otherwise, the fiq debugger will start out in debug mode. diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 6ea9b6f..3ab5d76 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_IXP2000) += uengine.o obj-$(CONFIG_ARCH_IXP23XX) += uengine.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o +obj-$(CONFIG_FIQ_GLUE) += fiq_glue.o fiq_glue_setup.o +obj-$(CONFIG_FIQ_DEBUGGER) += fiq_debugger.o diff --git a/arch/arm/common/fiq_debugger.c b/arch/arm/common/fiq_debugger.c new file mode 100644 index 0000000..8e5bddb --- /dev/null +++ b/arch/arm/common/fiq_debugger.c @@ -0,0 +1,1183 @@ +/* + * arch/arm/common/fiq_debugger.c + * + * Serial Debugger Interface accessed through an FIQ interrupt. + * + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdarg.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/console.h> +#include <linux/interrupt.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/kernel_stat.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/smp.h> +#include <linux/timer.h> +#include <linux/tty.h> +#include <linux/tty_flip.h> +#include <linux/wakelock.h> + +#include <asm/fiq_debugger.h> +#include <asm/fiq_glue.h> +#include <asm/stacktrace.h> + +#include <mach/system.h> + +#include <linux/uaccess.h> + +#include "fiq_debugger_ringbuf.h" + +#define DEBUG_MAX 64 +#define MAX_UNHANDLED_FIQ_COUNT 1000000 + +#define THREAD_INFO(sp) ((struct thread_info *) \ + ((unsigned long)(sp) & ~(THREAD_SIZE - 1))) + +struct fiq_debugger_state { + struct fiq_glue_handler handler; + + int fiq; + int uart_irq; + int signal_irq; + int wakeup_irq; + bool wakeup_irq_no_set_wake; + struct clk *clk; + struct fiq_debugger_pdata *pdata; + struct platform_device *pdev; + + char debug_cmd[DEBUG_MAX]; + int debug_busy; + int debug_abort; + + char debug_buf[DEBUG_MAX]; + int debug_count; + + bool no_sleep; + bool debug_enable; + bool ignore_next_wakeup_irq; + struct timer_list sleep_timer; + spinlock_t sleep_timer_lock; + bool uart_enabled; + struct wake_lock debugger_wake_lock; + bool console_enable; + int current_cpu; + atomic_t unhandled_fiq_count; + bool in_fiq; + +#ifdef CONFIG_FIQ_DEBUGGER_CONSOLE + struct console console; + struct tty_driver *tty_driver; + struct tty_struct *tty; + int tty_open_count; + struct fiq_debugger_ringbuf *tty_rbuf; + bool syslog_dumping; +#endif + + unsigned int last_irqs[NR_IRQS]; +}; + +#ifdef CONFIG_FIQ_DEBUGGER_NO_SLEEP +static bool initial_no_sleep = true; +#else +static bool initial_no_sleep; +#endif + +#ifdef CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE +static bool initial_debug_enable = true; +static bool initial_console_enable = true; +#else +static bool initial_debug_enable; +static bool initial_console_enable; +#endif + +module_param_named(no_sleep, initial_no_sleep, bool, 0644); +module_param_named(debug_enable, initial_debug_enable, bool, 0644); +module_param_named(console_enable, initial_console_enable, bool, 0644); + +#ifdef CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON +static inline void enable_wakeup_irq(struct fiq_debugger_state *state) {} +static inline void disable_wakeup_irq(struct fiq_debugger_state *state) {} +#else +static inline void enable_wakeup_irq(struct fiq_debugger_state *state) +{ + if (state->wakeup_irq < 0) + return; + enable_irq(state->wakeup_irq); + if (!state->wakeup_irq_no_set_wake) + enable_irq_wake(state->wakeup_irq); +} +static inline void disable_wakeup_irq(struct fiq_debugger_state *state) +{ + if (state->wakeup_irq < 0) + return; + disable_irq_nosync(state->wakeup_irq); + if (!state->wakeup_irq_no_set_wake) + disable_irq_wake(state->wakeup_irq); +} +#endif + +static bool inline debug_have_fiq(struct fiq_debugger_state *state) +{ + return (state->fiq >= 0); +} + +static void debug_force_irq(struct fiq_debugger_state *state) +{ + unsigned int irq = state->signal_irq; + + if (WARN_ON(!debug_have_fiq(state))) + return; + if (state->pdata->force_irq) { + state->pdata->force_irq(state->pdev, irq); + } else { + struct irq_chip *chip = irq_get_chip(irq); + if (chip && chip->irq_retrigger) + chip->irq_retrigger(irq_get_irq_data(irq)); + } +} + +static void debug_uart_enable(struct fiq_debugger_state *state) +{ + if (state->clk) + clk_enable(state->clk); + if (state->pdata->uart_enable) + state->pdata->uart_enable(state->pdev); +} + +static void debug_uart_disable(struct fiq_debugger_state *state) +{ + if (state->pdata->uart_disable) + state->pdata->uart_disable(state->pdev); + if (state->clk) + clk_disable(state->clk); +} + +static void debug_uart_flush(struct fiq_debugger_state *state) +{ + if (state->pdata->uart_flush) + state->pdata->uart_flush(state->pdev); +} + +static void debug_puts(struct fiq_debugger_state *state, char *s) +{ + unsigned c; + while ((c = *s++)) { + if (c == '\n') + state->pdata->uart_putc(state->pdev, '\r'); + state->pdata->uart_putc(state->pdev, c); + } +} + +static void debug_prompt(struct fiq_debugger_state *state) +{ + debug_puts(state, "debug> "); +} + +int log_buf_copy(char *dest, int idx, int len); +static void dump_kernel_log(struct fiq_debugger_state *state) +{ + char buf[1024]; + int idx = 0; + int ret; + int saved_oip; + + /* setting oops_in_progress prevents log_buf_copy() + * from trying to take a spinlock which will make it + * very unhappy in some cases... + */ + saved_oip = oops_in_progress; + oops_in_progress = 1; + for (;;) { + ret = log_buf_copy(buf, idx, 1023); + if (ret <= 0) + break; + buf[ret] = 0; + debug_puts(state, buf); + idx += ret; + } + oops_in_progress = saved_oip; +} + +static char *mode_name(unsigned cpsr) +{ + switch (cpsr & MODE_MASK) { + case USR_MODE: return "USR"; + case FIQ_MODE: return "FIQ"; + case IRQ_MODE: return "IRQ"; + case SVC_MODE: return "SVC"; + case ABT_MODE: return "ABT"; + case UND_MODE: return "UND"; + case SYSTEM_MODE: return "SYS"; + default: return "???"; + } +} + +static int debug_printf(void *cookie, const char *fmt, ...) +{ + struct fiq_debugger_state *state = cookie; + char buf[256]; + va_list ap; + + va_start(ap, fmt); + vsnprintf(buf, sizeof(buf), fmt, ap); + va_end(ap); + + debug_puts(state, buf); + return state->debug_abort; +} + +/* Safe outside fiq context */ +static int debug_printf_nfiq(void *cookie, const char *fmt, ...) +{ + struct fiq_debugger_state *state = cookie; + char buf[256]; + va_list ap; + unsigned long irq_flags; + + va_start(ap, fmt); + vsnprintf(buf, 128, fmt, ap); + va_end(ap); + + local_irq_save(irq_flags); + debug_puts(state, buf); + debug_uart_flush(state); + local_irq_restore(irq_flags); + return state->debug_abort; +} + +static void dump_regs(struct fiq_debugger_state *state, unsigned *regs) +{ + debug_printf(state, " r0 %08x r1 %08x r2 %08x r3 %08x\n", + regs[0], regs[1], regs[2], regs[3]); + debug_printf(state, " r4 %08x r5 %08x r6 %08x r7 %08x\n", + regs[4], regs[5], regs[6], regs[7]); + debug_printf(state, " r8 %08x r9 %08x r10 %08x r11 %08x mode %s\n", + regs[8], regs[9], regs[10], regs[11], + mode_name(regs[16])); + if ((regs[16] & MODE_MASK) == USR_MODE) + debug_printf(state, " ip %08x sp %08x lr %08x pc %08x " + "cpsr %08x\n", regs[12], regs[13], regs[14], + regs[15], regs[16]); + else + debug_printf(state, " ip %08x sp %08x lr %08x pc %08x " + "cpsr %08x spsr %08x\n", regs[12], regs[13], + regs[14], regs[15], regs[16], regs[17]); +} + +struct mode_regs { + unsigned long sp_svc; + unsigned long lr_svc; + unsigned long spsr_svc; + + unsigned long sp_abt; + unsigned long lr_abt; + unsigned long spsr_abt; + + unsigned long sp_und; + unsigned long lr_und; + unsigned long spsr_und; + + unsigned long sp_irq; + unsigned long lr_irq; + unsigned long spsr_irq; + + unsigned long r8_fiq; + unsigned long r9_fiq; + unsigned long r10_fiq; + unsigned long r11_fiq; + unsigned long r12_fiq; + unsigned long sp_fiq; + unsigned long lr_fiq; + unsigned long spsr_fiq; +}; + +void __naked get_mode_regs(struct mode_regs *regs) +{ + asm volatile ( + "mrs r1, cpsr\n" + "msr cpsr_c, #0xd3 @(SVC_MODE | PSR_I_BIT | PSR_F_BIT)\n" + "stmia r0!, {r13 - r14}\n" + "mrs r2, spsr\n" + "msr cpsr_c, #0xd7 @(ABT_MODE | PSR_I_BIT | PSR_F_BIT)\n" + "stmia r0!, {r2, r13 - r14}\n" + "mrs r2, spsr\n" + "msr cpsr_c, #0xdb @(UND_MODE | PSR_I_BIT | PSR_F_BIT)\n" + "stmia r0!, {r2, r13 - r14}\n" + "mrs r2, spsr\n" + "msr cpsr_c, #0xd2 @(IRQ_MODE | PSR_I_BIT | PSR_F_BIT)\n" + "stmia r0!, {r2, r13 - r14}\n" + "mrs r2, spsr\n" + "msr cpsr_c, #0xd1 @(FIQ_MODE | PSR_I_BIT | PSR_F_BIT)\n" + "stmia r0!, {r2, r8 - r14}\n" + "mrs r2, spsr\n" + "stmia r0!, {r2}\n" + "msr cpsr_c, r1\n" + "bx lr\n"); +} + + +static void dump_allregs(struct fiq_debugger_state *state, unsigned *regs) +{ + struct mode_regs mode_regs; + dump_regs(state, regs); + get_mode_regs(&mode_regs); + debug_printf(state, " svc: sp %08x lr %08x spsr %08x\n", + mode_regs.sp_svc, mode_regs.lr_svc, mode_regs.spsr_svc); + debug_printf(state, " abt: sp %08x lr %08x spsr %08x\n", + mode_regs.sp_abt, mode_regs.lr_abt, mode_regs.spsr_abt); + debug_printf(state, " und: sp %08x lr %08x spsr %08x\n", + mode_regs.sp_und, mode_regs.lr_und, mode_regs.spsr_und); + debug_printf(state, " irq: sp %08x lr %08x spsr %08x\n", + mode_regs.sp_irq, mode_regs.lr_irq, mode_regs.spsr_irq); + debug_printf(state, " fiq: r8 %08x r9 %08x r10 %08x r11 %08x " + "r12 %08x\n", + mode_regs.r8_fiq, mode_regs.r9_fiq, mode_regs.r10_fiq, + mode_regs.r11_fiq, mode_regs.r12_fiq); + debug_printf(state, " fiq: sp %08x lr %08x spsr %08x\n", + mode_regs.sp_fiq, mode_regs.lr_fiq, mode_regs.spsr_fiq); +} + +static void dump_irqs(struct fiq_debugger_state *state) +{ + int n; + debug_printf(state, "irqnr total since-last status name\n"); + for (n = 0; n < NR_IRQS; n++) { + struct irqaction *act = irq_desc[n].action; + if (!act && !kstat_irqs(n)) + continue; + debug_printf(state, "%5d: %10u %11u %8x %s\n", n, + kstat_irqs(n), + kstat_irqs(n) - state->last_irqs[n], + irq_desc[n].status_use_accessors, + (act && act->name) ? act->name : "???"); + state->last_irqs[n] = kstat_irqs(n); + } +} + +struct stacktrace_state { + struct fiq_debugger_state *state; + unsigned int depth; +}; + +static int report_trace(struct stackframe *frame, void *d) +{ + struct stacktrace_state *sts = d; + + if (sts->depth) { + debug_printf(sts->state, + " pc: %p (%pF), lr %p (%pF), sp %p, fp %p\n", + frame->pc, frame->pc, frame->lr, frame->lr, + frame->sp, frame->fp); + sts->depth--; + return 0; + } + debug_printf(sts->state, " ...\n"); + + return sts->depth == 0; +} + +struct frame_tail { + struct frame_tail *fp; + unsigned long sp; + unsigned long lr; +} __attribute__((packed)); + +static struct frame_tail *user_backtrace(struct fiq_debugger_state *state, + struct frame_tail *tail) +{ + struct frame_tail buftail[2]; + + /* Also check accessibility of one struct frame_tail beyond */ + if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) { + debug_printf(state, " invalid frame pointer %p\n", tail); + return NULL; + } + if (__copy_from_user_inatomic(buftail, tail, sizeof(buftail))) { + debug_printf(state, + " failed to copy frame pointer %p\n", tail); + return NULL; + } + + debug_printf(state, " %p\n", buftail[0].lr); + + /* frame pointers should strictly progress back up the stack + * (towards higher addresses) */ + if (tail >= buftail[0].fp) + return NULL; + + return buftail[0].fp-1; +} + +void dump_stacktrace(struct fiq_debugger_state *state, + struct pt_regs * const regs, unsigned int depth, void *ssp) +{ + struct frame_tail *tail; + struct thread_info *real_thread_info = THREAD_INFO(ssp); + struct stacktrace_state sts; + + sts.depth = depth; + sts.state = state; + *current_thread_info() = *real_thread_info; + + if (!current) + debug_printf(state, "current NULL\n"); + else + debug_printf(state, "pid: %d comm: %s\n", + current->pid, current->comm); + dump_regs(state, (unsigned *)regs); + + if (!user_mode(regs)) { + struct stackframe frame; + frame.fp = regs->ARM_fp; + frame.sp = regs->ARM_sp; + frame.lr = regs->ARM_lr; + frame.pc = regs->ARM_pc; + debug_printf(state, + " pc: %p (%pF), lr %p (%pF), sp %p, fp %p\n", + regs->ARM_pc, regs->ARM_pc, regs->ARM_lr, regs->ARM_lr, + regs->ARM_sp, regs->ARM_fp); + walk_stackframe(&frame, report_trace, &sts); + return; + } + + tail = ((struct frame_tail *) regs->ARM_fp) - 1; + while (depth-- && tail && !((unsigned long) tail & 3)) + tail = user_backtrace(state, tail); +} + +static void do_ps(struct fiq_debugger_state *state) +{ + struct task_struct *g; + struct task_struct *p; + unsigned task_state; + static const char stat_nam[] = "RSDTtZX"; + + debug_printf(state, "pid ppid prio task pc\n"); + read_lock(&tasklist_lock); + do_each_thread(g, p) { + task_state = p->state ? __ffs(p->state) + 1 : 0; + debug_printf(state, + "%5d %5d %4d ", p->pid, p->parent->pid, p->prio); + debug_printf(state, "%-13.13s %c", p->comm, + task_state >= sizeof(stat_nam) ? '?' : stat_nam[task_state]); + if (task_state == TASK_RUNNING) + debug_printf(state, " running\n"); + else + debug_printf(state, " %08lx\n", thread_saved_pc(p)); + } while_each_thread(g, p); + read_unlock(&tasklist_lock); +} + +#ifdef CONFIG_FIQ_DEBUGGER_CONSOLE +static void begin_syslog_dump(struct fiq_debugger_state *state) +{ + state->syslog_dumping = true; +} + +static void end_syslog_dump(struct fiq_debugger_state *state) +{ + state->syslog_dumping = false; +} +#else +extern int do_syslog(int type, char __user *bug, int count); +static void begin_syslog_dump(struct fiq_debugger_state *state) +{ + do_syslog(5 /* clear */, NULL, 0); +} + +static void end_syslog_dump(struct fiq_debugger_state *state) +{ + char buf[128]; + int ret; + int idx = 0; + + while (1) { + ret = log_buf_copy(buf, idx, sizeof(buf) - 1); + if (ret <= 0) + break; + buf[ret] = 0; + debug_printf(state, "%s", buf); + idx += ret; + } +} +#endif + +static void do_sysrq(struct fiq_debugger_state *state, char rq) +{ + begin_syslog_dump(state); + handle_sysrq(rq); + end_syslog_dump(state); +} + +/* This function CANNOT be called in FIQ context */ +static void debug_irq_exec(struct fiq_debugger_state *state, char *cmd) +{ + if (!strcmp(cmd, "ps")) + do_ps(state); + if (!strcmp(cmd, "sysrq")) + do_sysrq(state, 'h'); + if (!strncmp(cmd, "sysrq ", 6)) + do_sysrq(state, cmd[6]); +} + +static void debug_help(struct fiq_debugger_state *state) +{ + debug_printf(state, "FIQ Debugger commands:\n" + " pc PC status\n" + " regs Register dump\n" + " allregs Extended Register dump\n" + " bt Stack trace\n" + " reboot Reboot\n" + " irqs Interupt status\n" + " kmsg Kernel log\n" + " version Kernel version\n"); + debug_printf(state, " sleep Allow sleep while in FIQ\n" + " nosleep Disable sleep while in FIQ\n" + " console Switch terminal to console\n" + " cpu Current CPU\n" + " cpu <number> Switch to CPU<number>\n"); + debug_printf(state, " ps Process list\n" + " sysrq sysrq options\n" + " sysrq <param> Execute sysrq with <param>\n"); +} + +static void take_affinity(void *info) +{ + struct fiq_debugger_state *state = info; + struct cpumask cpumask; + + cpumask_clear(&cpumask); + cpumask_set_cpu(get_cpu(), &cpumask); + + irq_set_affinity(state->uart_irq, &cpumask); +} + +static void switch_cpu(struct fiq_debugger_state *state, int cpu) +{ + if (!debug_have_fiq(state)) + smp_call_function_single(cpu, take_affinity, state, false); + state->current_cpu = cpu; +} + +static bool debug_fiq_exec(struct fiq_debugger_state *state, + const char *cmd, unsigned *regs, void *svc_sp) +{ + bool signal_helper = false; + + if (!strcmp(cmd, "help") || !strcmp(cmd, "?")) { + debug_help(state); + } else if (!strcmp(cmd, "pc")) { + debug_printf(state, " pc %08x cpsr %08x mode %s\n", + regs[15], regs[16], mode_name(regs[16])); + } else if (!strcmp(cmd, "regs")) { + dump_regs(state, regs); + } else if (!strcmp(cmd, "allregs")) { + dump_allregs(state, regs); + } else if (!strcmp(cmd, "bt")) { + dump_stacktrace(state, (struct pt_regs *)regs, 100, svc_sp); + } else if (!strcmp(cmd, "reboot")) { + arch_reset(0, 0); + } else if (!strcmp(cmd, "irqs")) { + dump_irqs(state); + } else if (!strcmp(cmd, "kmsg")) { + dump_kernel_log(state); + } else if (!strcmp(cmd, "version")) { + debug_printf(state, "%s\n", linux_banner); + } else if (!strcmp(cmd, "sleep")) { + state->no_sleep = false; + debug_printf(state, "enabling sleep\n"); + } else if (!strcmp(cmd, "nosleep")) { + state->no_sleep = true; + debug_printf(state, "disabling sleep\n"); + } else if (!strcmp(cmd, "console")) { + state->console_enable = true; + debug_printf(state, "console mode\n"); + } else if (!strcmp(cmd, "cpu")) { + debug_printf(state, "cpu %d\n", state->current_cpu); + } else if (!strncmp(cmd, "cpu ", 4)) { + unsigned long cpu = 0; + if (strict_strtoul(cmd + 4, 10, &cpu) == 0) + switch_cpu(state, cpu); + else + debug_printf(state, "invalid cpu\n"); + debug_printf(state, "cpu %d\n", state->current_cpu); + } else { + if (state->debug_busy) { + debug_printf(state, + "command processor busy. trying to abort.\n"); + state->debug_abort = -1; + } else { + strcpy(state->debug_cmd, cmd); + state->debug_busy = 1; + } + + return true; + } + if (!state->console_enable) + debug_prompt(state); + + return signal_helper; +} + +static void sleep_timer_expired(unsigned long data) +{ + struct fiq_debugger_state *state = (struct fiq_debugger_state *)data; + unsigned long flags; + + spin_lock_irqsave(&state->sleep_timer_lock, flags); + if (state->uart_enabled && !state->no_sleep) { + if (state->debug_enable && !state->console_enable) { + state->debug_enable = false; + debug_printf_nfiq(state, "suspending fiq debugger\n"); + } + state->ignore_next_wakeup_irq = true; + debug_uart_disable(state); + state->uart_enabled = false; + enable_wakeup_irq(state); + } + wake_unlock(&state->debugger_wake_lock); + spin_unlock_irqrestore(&state->sleep_timer_lock, flags); +} + +static void handle_wakeup(struct fiq_debugger_state *state) +{ + unsigned long flags; + + spin_lock_irqsave(&state->sleep_timer_lock, flags); + if (state->wakeup_irq >= 0 && state->ignore_next_wakeup_irq) { + state->ignore_next_wakeup_irq = false; + } else if (!state->uart_enabled) { + wake_lock(&state->debugger_wake_lock); + debug_uart_enable(state); + state->uart_enabled = true; + disable_wakeup_irq(state); + mod_timer(&state->sleep_timer, jiffies + HZ / 2); + } + spin_unlock_irqrestore(&state->sleep_timer_lock, flags); +} + +static irqreturn_t wakeup_irq_handler(int irq, void *dev) +{ + struct fiq_debugger_state *state = dev; + + if (!state->no_sleep) + debug_puts(state, "WAKEUP\n"); + handle_wakeup(state); + + return IRQ_HANDLED; +} + + +static void debug_handle_irq_context(struct fiq_debugger_state *state) +{ + if (!state->no_sleep) { + unsigned long flags; + + spin_lock_irqsave(&state->sleep_timer_lock, flags); + wake_lock(&state->debugger_wake_lock); + mod_timer(&state->sleep_timer, jiffies + HZ * 5); + spin_unlock_irqrestore(&state->sleep_timer_lock, flags); + } +#if defined(CONFIG_FIQ_DEBUGGER_CONSOLE) + if (state->tty) { + int i; + int count = fiq_debugger_ringbuf_level(state->tty_rbuf); + for (i = 0; i < count; i++) { + int c = fiq_debugger_ringbuf_peek(state->tty_rbuf, 0); + tty_insert_flip_char(state->tty, c, TTY_NORMAL); + if (!fiq_debugger_ringbuf_consume(state->tty_rbuf, 1)) + pr_warn("fiq tty failed to consume byte\n"); + } + tty_flip_buffer_push(state->tty); + } +#endif + if (state->debug_busy) { + debug_irq_exec(state, state->debug_cmd); + debug_prompt(state); + state->debug_busy = 0; + } +} + +static int debug_getc(struct fiq_debugger_state *state) +{ + return state->pdata->uart_getc(state->pdev); +} + +static bool debug_handle_uart_interrupt(struct fiq_debugger_state *state, + int this_cpu, void *regs, void *svc_sp) +{ + int c; + static int last_c; + int count = 0; + bool signal_helper = false; + + if (this_cpu != state->current_cpu) { + if (state->in_fiq) + return false; + + if (atomic_inc_return(&state->unhandled_fiq_count) != + MAX_UNHANDLED_FIQ_COUNT) + return false; + + debug_printf(state, "fiq_debugger: cpu %d not responding, " + "reverting to cpu %d\n", state->current_cpu, + this_cpu); + + atomic_set(&state->unhandled_fiq_count, 0); + switch_cpu(state, this_cpu); + return false; + } + + state->in_fiq = true; + + while ((c = debug_getc(state)) != FIQ_DEBUGGER_NO_CHAR) { + count++; + if (!state->debug_enable) { + if ((c == 13) || (c == 10)) { + state->debug_enable = true; + state->debug_count = 0; + debug_prompt(state); + } + } else if (c == FIQ_DEBUGGER_BREAK) { + state->console_enable = false; + debug_puts(state, "fiq debugger mode\n"); + state->debug_count = 0; + debug_prompt(state); +#ifdef CONFIG_FIQ_DEBUGGER_CONSOLE + } else if (state->console_enable && state->tty_rbuf) { + fiq_debugger_ringbuf_push(state->tty_rbuf, c); + signal_helper = true; +#endif + } else if ((c >= ' ') && (c < 127)) { + if (state->debug_count < (DEBUG_MAX - 1)) { + state->debug_buf[state->debug_count++] = c; + state->pdata->uart_putc(state->pdev, c); + } + } else if ((c == 8) || (c == 127)) { + if (state->debug_count > 0) { + state->debug_count--; + state->pdata->uart_putc(state->pdev, 8); + state->pdata->uart_putc(state->pdev, ' '); + state->pdata->uart_putc(state->pdev, 8); + } + } else if ((c == 13) || (c == 10)) { + if (c == '\r' || (c == '\n' && last_c != '\r')) { + state->pdata->uart_putc(state->pdev, '\r'); + state->pdata->uart_putc(state->pdev, '\n'); + } + if (state->debug_count) { + state->debug_buf[state->debug_count] = 0; + state->debug_count = 0; + signal_helper |= + debug_fiq_exec(state, state->debug_buf, + regs, svc_sp); + } else { + debug_prompt(state); + } + } + last_c = c; + } + debug_uart_flush(state); + if (state->pdata->fiq_ack) + state->pdata->fiq_ack(state->pdev, state->fiq); + + /* poke sleep timer if necessary */ + if (state->debug_enable && !state->no_sleep) + signal_helper = true; + + atomic_set(&state->unhandled_fiq_count, 0); + state->in_fiq = false; + + return signal_helper; +} + +static void debug_fiq(struct fiq_glue_handler *h, void *regs, void *svc_sp) +{ + struct fiq_debugger_state *state = + container_of(h, struct fiq_debugger_state, handler); + unsigned int this_cpu = THREAD_INFO(svc_sp)->cpu; + bool need_irq; + + need_irq = debug_handle_uart_interrupt(state, this_cpu, regs, svc_sp); + if (need_irq) + debug_force_irq(state); +} + +/* + * When not using FIQs, we only use this single interrupt as an entry point. + * This just effectively takes over the UART interrupt and does all the work + * in this context. + */ +static irqreturn_t debug_uart_irq(int irq, void *dev) +{ + struct fiq_debugger_state *state = dev; + bool not_done; + + handle_wakeup(state); + + /* handle the debugger irq in regular context */ + not_done = debug_handle_uart_interrupt(state, smp_processor_id(), + get_irq_regs(), + current_thread_info()); + if (not_done) + debug_handle_irq_context(state); + + return IRQ_HANDLED; +} + +/* + * If FIQs are used, not everything can happen in fiq context. + * FIQ handler does what it can and then signals this interrupt to finish the + * job in irq context. + */ +static irqreturn_t debug_signal_irq(int irq, void *dev) +{ + struct fiq_debugger_state *state = dev; + + if (state->pdata->force_irq_ack) + state->pdata->force_irq_ack(state->pdev, state->signal_irq); + + debug_handle_irq_context(state); + + return IRQ_HANDLED; +} + +static void debug_resume(struct fiq_glue_handler *h) +{ + struct fiq_debugger_state *state = + container_of(h, struct fiq_debugger_state, handler); + if (state->pdata->uart_resume) + state->pdata->uart_resume(state->pdev); +} + +#if defined(CONFIG_FIQ_DEBUGGER_CONSOLE) +struct tty_driver *debug_console_device(struct console *co, int *index) +{ + struct fiq_debugger_state *state; + state = container_of(co, struct fiq_debugger_state, console); + *index = 0; + return state->tty_driver; +} + +static void debug_console_write(struct console *co, + const char *s, unsigned int count) +{ + struct fiq_debugger_state *state; + + state = container_of(co, struct fiq_debugger_state, console); + + if (!state->console_enable && !state->syslog_dumping) + return; + + debug_uart_enable(state); + while (count--) { + if (*s == '\n') + state->pdata->uart_putc(state->pdev, '\r'); + state->pdata->uart_putc(state->pdev, *s++); + } + debug_uart_flush(state); + debug_uart_disable(state); +} + +static struct console fiq_debugger_console = { + .name = "ttyFIQ", + .device = debug_console_device, + .write = debug_console_write, + .flags = CON_PRINTBUFFER | CON_ANYTIME | CON_ENABLED, +}; + +int fiq_tty_open(struct tty_struct *tty, struct file *filp) +{ + struct fiq_debugger_state *state = tty->driver->driver_state; + if (state->tty_open_count++) + return 0; + + tty->driver_data = state; + state->tty = tty; + return 0; +} + +void fiq_tty_close(struct tty_struct *tty, struct file *filp) +{ + struct fiq_debugger_state *state = tty->driver_data; + if (--state->tty_open_count) + return; + state->tty = NULL; +} + +int fiq_tty_write(struct tty_struct *tty, const unsigned char *buf, int count) +{ + int i; + struct fiq_debugger_state *state = tty->driver_data; + + if (!state->console_enable) + return count; + + debug_uart_enable(state); + for (i = 0; i < count; i++) + state->pdata->uart_putc(state->pdev, *buf++); + debug_uart_disable(state); + + return count; +} + +int fiq_tty_write_room(struct tty_struct *tty) +{ + return 1024; +} + +static const struct tty_operations fiq_tty_driver_ops = { + .write = fiq_tty_write, + .write_room = fiq_tty_write_room, + .open = fiq_tty_open, + .close = fiq_tty_close, +}; + +static int fiq_debugger_tty_init(struct fiq_debugger_state *state) +{ + int ret = -EINVAL; + + state->tty_driver = alloc_tty_driver(1); + if (!state->tty_driver) { + pr_err("Failed to allocate fiq debugger tty\n"); + return -ENOMEM; + } + + state->tty_driver->owner = THIS_MODULE; + state->tty_driver->driver_name = "fiq-debugger"; + state->tty_driver->name = "ttyFIQ"; + state->tty_driver->type = TTY_DRIVER_TYPE_SERIAL; + state->tty_driver->subtype = SERIAL_TYPE_NORMAL; + state->tty_driver->init_termios = tty_std_termios; + state->tty_driver->init_termios.c_cflag = + B115200 | CS8 | CREAD | HUPCL | CLOCAL; + state->tty_driver->init_termios.c_ispeed = + state->tty_driver->init_termios.c_ospeed = 115200; + state->tty_driver->flags = TTY_DRIVER_REAL_RAW; + tty_set_operations(state->tty_driver, &fiq_tty_driver_ops); + state->tty_driver->driver_state = state; + + ret = tty_register_driver(state->tty_driver); + if (ret) { + pr_err("Failed to register fiq tty: %d\n", ret); + goto err; + } + + state->tty_rbuf = fiq_debugger_ringbuf_alloc(1024); + if (!state->tty_rbuf) { + pr_err("Failed to allocate fiq debugger ringbuf\n"); + ret = -ENOMEM; + goto err; + } + + pr_info("Registered FIQ tty driver %p\n", state->tty_driver); + return 0; + +err: + fiq_debugger_ringbuf_free(state->tty_rbuf); + state->tty_rbuf = NULL; + put_tty_driver(state->tty_driver); + return ret; +} +#endif + +static int fiq_debugger_dev_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct fiq_debugger_state *state = platform_get_drvdata(pdev); + + if (state->pdata->uart_dev_suspend) + return state->pdata->uart_dev_suspend(pdev); + return 0; +} + +static int fiq_debugger_dev_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct fiq_debugger_state *state = platform_get_drvdata(pdev); + + if (state->pdata->uart_dev_resume) + return state->pdata->uart_dev_resume(pdev); + return 0; +} + +static int fiq_debugger_probe(struct platform_device *pdev) +{ + int ret; + struct fiq_debugger_pdata *pdata = dev_get_platdata(&pdev->dev); + struct fiq_debugger_state *state; + int fiq; + int uart_irq; + + if (!pdata->uart_getc || !pdata->uart_putc) + return -EINVAL; + if ((pdata->uart_enable && !pdata->uart_disable) || + (!pdata->uart_enable && pdata->uart_disable)) + return -EINVAL; + + fiq = platform_get_irq_byname(pdev, "fiq"); + uart_irq = platform_get_irq_byname(pdev, "uart_irq"); + + /* uart_irq mode and fiq mode are mutually exclusive, but one of them + * is required */ + if ((uart_irq < 0 && fiq < 0) || (uart_irq >= 0 && fiq >= 0)) + return -EINVAL; + if (fiq >= 0 && !pdata->fiq_enable) + return -EINVAL; + + state = kzalloc(sizeof(*state), GFP_KERNEL); + setup_timer(&state->sleep_timer, sleep_timer_expired, + (unsigned long)state); + state->pdata = pdata; + state->pdev = pdev; + state->no_sleep = initial_no_sleep; + state->debug_enable = initial_debug_enable; + state->console_enable = initial_console_enable; + + state->fiq = fiq; + state->uart_irq = uart_irq; + state->signal_irq = platform_get_irq_byname(pdev, "signal"); + state->wakeup_irq = platform_get_irq_byname(pdev, "wakeup"); + + platform_set_drvdata(pdev, state); + + spin_lock_init(&state->sleep_timer_lock); + + if (state->wakeup_irq < 0 && debug_have_fiq(state)) + state->no_sleep = true; + state->ignore_next_wakeup_irq = !state->no_sleep; + + wake_lock_init(&state->debugger_wake_lock, + WAKE_LOCK_SUSPEND, "serial-debug"); + + state->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(state->clk)) + state->clk = NULL; + + /* do not call pdata->uart_enable here since uart_init may still + * need to do some initialization before uart_enable can work. + * So, only try to manage the clock during init. + */ + if (state->clk) + clk_enable(state->clk); + + if (pdata->uart_init) { + ret = pdata->uart_init(pdev); + if (ret) + goto err_uart_init; + } + + debug_printf_nfiq(state, "<hit enter %sto activate fiq debugger>\n", + state->no_sleep ? "" : "twice "); + + if (debug_have_fiq(state)) { + state->handler.fiq = debug_fiq; + state->handler.resume = debug_resume; + ret = fiq_glue_register_handler(&state->handler); + if (ret) { + pr_err("%s: could not install fiq handler\n", __func__); + goto err_register_fiq; + } + + pdata->fiq_enable(pdev, state->fiq, 1); + } else { + ret = request_irq(state->uart_irq, debug_uart_irq, + IRQF_NO_SUSPEND, "debug", state); + if (ret) { + pr_err("%s: could not install irq handler\n", __func__); + goto err_register_irq; + } + + /* for irq-only mode, we want this irq to wake us up, if it + * can. + */ + enable_irq_wake(state->uart_irq); + } + + if (state->clk) + clk_disable(state->clk); + + if (state->signal_irq >= 0) { + ret = request_irq(state->signal_irq, debug_signal_irq, + IRQF_TRIGGER_RISING, "debug-signal", state); + if (ret) + pr_err("serial_debugger: could not install signal_irq"); + } + + if (state->wakeup_irq >= 0) { + ret = request_irq(state->wakeup_irq, wakeup_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_DISABLED, + "debug-wakeup", state); + if (ret) { + pr_err("serial_debugger: " + "could not install wakeup irq\n"); + state->wakeup_irq = -1; + } else { + ret = enable_irq_wake(state->wakeup_irq); + if (ret) { + pr_err("serial_debugger: " + "could not enable wakeup\n"); + state->wakeup_irq_no_set_wake = true; + } + } + } + if (state->no_sleep) + handle_wakeup(state); + +#if defined(CONFIG_FIQ_DEBUGGER_CONSOLE) + state->console = fiq_debugger_console; + register_console(&state->console); + fiq_debugger_tty_init(state); +#endif + return 0; + +err_register_irq: +err_register_fiq: + if (pdata->uart_free) + pdata->uart_free(pdev); +err_uart_init: + if (state->clk) + clk_disable(state->clk); + if (state->clk) + clk_put(state->clk); + wake_lock_destroy(&state->debugger_wake_lock); + platform_set_drvdata(pdev, NULL); + kfree(state); + return ret; +} + +static const struct dev_pm_ops fiq_debugger_dev_pm_ops = { + .suspend = fiq_debugger_dev_suspend, + .resume = fiq_debugger_dev_resume, +}; + +static struct platform_driver fiq_debugger_driver = { + .probe = fiq_debugger_probe, + .driver = { + .name = "fiq_debugger", + .pm = &fiq_debugger_dev_pm_ops, + }, +}; + +static int __init fiq_debugger_init(void) +{ + return platform_driver_register(&fiq_debugger_driver); +} + +postcore_initcall(fiq_debugger_init); diff --git a/arch/arm/common/fiq_debugger_ringbuf.h b/arch/arm/common/fiq_debugger_ringbuf.h new file mode 100644 index 0000000..2649b55 --- /dev/null +++ b/arch/arm/common/fiq_debugger_ringbuf.h @@ -0,0 +1,94 @@ +/* + * arch/arm/common/fiq_debugger_ringbuf.c + * + * simple lockless ringbuffer + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/slab.h> + +struct fiq_debugger_ringbuf { + int len; + int head; + int tail; + u8 buf[]; +}; + + +static inline struct fiq_debugger_ringbuf *fiq_debugger_ringbuf_alloc(int len) +{ + struct fiq_debugger_ringbuf *rbuf; + + rbuf = kzalloc(sizeof(*rbuf) + len, GFP_KERNEL); + if (rbuf == NULL) + return NULL; + + rbuf->len = len; + rbuf->head = 0; + rbuf->tail = 0; + smp_mb(); + + return rbuf; +} + +static inline void fiq_debugger_ringbuf_free(struct fiq_debugger_ringbuf *rbuf) +{ + kfree(rbuf); +} + +static inline int fiq_debugger_ringbuf_level(struct fiq_debugger_ringbuf *rbuf) +{ + int level = rbuf->head - rbuf->tail; + + if (level < 0) + level = rbuf->len + level; + + return level; +} + +static inline int fiq_debugger_ringbuf_room(struct fiq_debugger_ringbuf *rbuf) +{ + return rbuf->len - fiq_debugger_ringbuf_level(rbuf) - 1; +} + +static inline u8 +fiq_debugger_ringbuf_peek(struct fiq_debugger_ringbuf *rbuf, int i) +{ + return rbuf->buf[(rbuf->tail + i) % rbuf->len]; +} + +static inline int +fiq_debugger_ringbuf_consume(struct fiq_debugger_ringbuf *rbuf, int count) +{ + count = min(count, fiq_debugger_ringbuf_level(rbuf)); + + rbuf->tail = (rbuf->tail + count) % rbuf->len; + smp_mb(); + + return count; +} + +static inline int +fiq_debugger_ringbuf_push(struct fiq_debugger_ringbuf *rbuf, u8 datum) +{ + if (fiq_debugger_ringbuf_room(rbuf) == 0) + return 0; + + rbuf->buf[rbuf->head] = datum; + smp_mb(); + rbuf->head = (rbuf->head + 1) % rbuf->len; + smp_mb(); + + return 1; +} diff --git a/arch/arm/common/fiq_glue.S b/arch/arm/common/fiq_glue.S new file mode 100644 index 0000000..9e3455a --- /dev/null +++ b/arch/arm/common/fiq_glue.S @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + + .text + + .global fiq_glue_end + + /* fiq stack: r0-r15,cpsr,spsr of interrupted mode */ + +ENTRY(fiq_glue) + /* store pc, cpsr from previous mode */ + mrs r12, spsr + sub r11, lr, #4 + subs r10, #1 + bne nested_fiq + + stmfd sp!, {r11-r12, lr} + + /* store r8-r14 from previous mode */ + sub sp, sp, #(7 * 4) + stmia sp, {r8-r14}^ + nop + + /* store r0-r7 from previous mode */ + stmfd sp!, {r0-r7} + + /* setup func(data,regs) arguments */ + mov r0, r9 + mov r1, sp + mov r3, r8 + + mov r7, sp + + /* Get sp and lr from non-user modes */ + and r4, r12, #MODE_MASK + cmp r4, #USR_MODE + beq fiq_from_usr_mode + + mov r7, sp + orr r4, r4, #(PSR_I_BIT | PSR_F_BIT) + msr cpsr_c, r4 + str sp, [r7, #(4 * 13)] + str lr, [r7, #(4 * 14)] + mrs r5, spsr + str r5, [r7, #(4 * 17)] + + cmp r4, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT) + /* use fiq stack if we reenter this mode */ + subne sp, r7, #(4 * 3) + +fiq_from_usr_mode: + msr cpsr_c, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT) + mov r2, sp + sub sp, r7, #12 + stmfd sp!, {r2, ip, lr} + /* call func(data,regs) */ + blx r3 + ldmfd sp, {r2, ip, lr} + mov sp, r2 + + /* restore/discard saved state */ + cmp r4, #USR_MODE + beq fiq_from_usr_mode_exit + + msr cpsr_c, r4 + ldr sp, [r7, #(4 * 13)] + ldr lr, [r7, #(4 * 14)] + msr spsr_cxsf, r5 + +fiq_from_usr_mode_exit: + msr cpsr_c, #(FIQ_MODE | PSR_I_BIT | PSR_F_BIT) + + ldmfd sp!, {r0-r7} + add sp, sp, #(7 * 4) + ldmfd sp!, {r11-r12, lr} +exit_fiq: + msr spsr_cxsf, r12 + add r10, #1 + movs pc, r11 + +nested_fiq: + orr r12, r12, #(PSR_F_BIT) + b exit_fiq + +fiq_glue_end: + +ENTRY(fiq_glue_setup) /* func, data, sp */ + mrs r3, cpsr + msr cpsr_c, #(FIQ_MODE | PSR_I_BIT | PSR_F_BIT) + movs r8, r0 + mov r9, r1 + mov sp, r2 + moveq r10, #0 + movne r10, #1 + msr cpsr_c, r3 + bx lr + diff --git a/arch/arm/common/fiq_glue_setup.c b/arch/arm/common/fiq_glue_setup.c new file mode 100644 index 0000000..4044c7d --- /dev/null +++ b/arch/arm/common/fiq_glue_setup.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/percpu.h> +#include <linux/slab.h> +#include <asm/fiq.h> +#include <asm/fiq_glue.h> + +extern unsigned char fiq_glue, fiq_glue_end; +extern void fiq_glue_setup(void *func, void *data, void *sp); + +static struct fiq_handler fiq_debbuger_fiq_handler = { + .name = "fiq_glue", +}; +DEFINE_PER_CPU(void *, fiq_stack); +static struct fiq_glue_handler *current_handler; +static DEFINE_MUTEX(fiq_glue_lock); + +static void fiq_glue_setup_helper(void *info) +{ + struct fiq_glue_handler *handler = info; + fiq_glue_setup(handler->fiq, handler, + __get_cpu_var(fiq_stack) + THREAD_START_SP); +} + +int fiq_glue_register_handler(struct fiq_glue_handler *handler) +{ + int ret; + int cpu; + + if (!handler || !handler->fiq) + return -EINVAL; + + mutex_lock(&fiq_glue_lock); + if (fiq_stack) { + ret = -EBUSY; + goto err_busy; + } + + for_each_possible_cpu(cpu) { + void *stack; + stack = (void *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); + if (WARN_ON(!stack)) { + ret = -ENOMEM; + goto err_alloc_fiq_stack; + } + per_cpu(fiq_stack, cpu) = stack; + } + + ret = claim_fiq(&fiq_debbuger_fiq_handler); + if (WARN_ON(ret)) + goto err_claim_fiq; + + current_handler = handler; + on_each_cpu(fiq_glue_setup_helper, handler, true); + set_fiq_handler(&fiq_glue, &fiq_glue_end - &fiq_glue); + + mutex_unlock(&fiq_glue_lock); + return 0; + +err_claim_fiq: +err_alloc_fiq_stack: + for_each_possible_cpu(cpu) { + __free_pages(per_cpu(fiq_stack, cpu), THREAD_SIZE_ORDER); + per_cpu(fiq_stack, cpu) = NULL; + } +err_busy: + mutex_unlock(&fiq_glue_lock); + return ret; +} + +/** + * fiq_glue_resume - Restore fiqs after suspend or low power idle states + * + * This must be called before calling local_fiq_enable after returning from a + * power state where the fiq mode registers were lost. If a driver provided + * a resume hook when it registered the handler it will be called. + */ + +void fiq_glue_resume(void) +{ + if (!current_handler) + return; + fiq_glue_setup(current_handler->fiq, current_handler, + __get_cpu_var(fiq_stack) + THREAD_START_SP); + if (current_handler->resume) + current_handler->resume(current_handler); +} + diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index 97912fa..3af5e11 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c @@ -1281,17 +1281,17 @@ int pl330_submit_req(void *ch_id, struct pl330_req *r) goto xfer_exit; } - /* Prefer Secure Channel */ - if (!_manager_ns(thrd)) - r->cfg->nonsecure = 0; - else - r->cfg->nonsecure = 1; - /* Use last settings, if not provided */ - if (r->cfg) + if (r->cfg) { + /* Prefer Secure Channel */ + if (!_manager_ns(thrd)) + r->cfg->nonsecure = 0; + else + r->cfg->nonsecure = 1; ccr = _prepare_ccr(r->cfg); - else + } else { ccr = readl(regs + CC(thrd->id)); + } /* If this req doesn't have valid xfer settings */ if (!_is_valid(ccr)) { diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 7aa4262..3a3622c 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -82,8 +82,6 @@ static void resume_one_vic(struct vic_device *vic) { void __iomem *base = vic->base; - printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); - /* re-initialise static settings */ vic_init2(base); @@ -112,8 +110,6 @@ static void suspend_one_vic(struct vic_device *vic) { void __iomem *base = vic->base; - printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); - vic->int_select = readl(base + VIC_INT_SELECT); vic->int_enable = readl(base + VIC_INT_ENABLE); vic->soft_int = readl(base + VIC_INT_SOFT); @@ -208,6 +204,37 @@ static void vic_unmask_irq(struct irq_data *d) writel(1 << irq, base + VIC_INT_ENABLE); } +static int vic_retrigger_irq(struct irq_data *d) +{ + void __iomem *base = irq_data_get_irq_chip_data(d); + unsigned int irq = d->irq & 31; + writel(1 << irq, base + VIC_INT_SOFT); + return 1; +} + +static DEFINE_SPINLOCK(vic_intselect_lock); +int vic_set_fiq(unsigned int irq, bool enable) +{ + u32 int_select; + u32 mask; + unsigned long irq_flags; + void __iomem *base = irq_get_chip_data(irq); + irq &= 31; + mask = 1 << irq; + + spin_lock_irqsave(&vic_intselect_lock, irq_flags); + int_select = readl(base + VIC_INT_SELECT); + if (enable) + int_select |= mask; + else + int_select &= ~mask; + writel(int_select, base + VIC_INT_SELECT); + spin_unlock_irqrestore(&vic_intselect_lock, irq_flags); + + return 0; +} +EXPORT_SYMBOL(vic_set_fiq); + #if defined(CONFIG_PM) static struct vic_device *vic_from_irq(unsigned int irq) { @@ -251,6 +278,7 @@ static struct irq_chip vic_chip = { .irq_ack = vic_ack_irq, .irq_mask = vic_mask_irq, .irq_unmask = vic_unmask_irq, + .irq_retrigger = vic_retrigger_irq, .irq_set_wake = vic_set_wake, }; diff --git a/arch/arm/configs/crespo_defconfig b/arch/arm/configs/crespo_defconfig new file mode 100644 index 0000000..daee1a8 --- /dev/null +++ b/arch/arm/configs/crespo_defconfig @@ -0,0 +1,2664 @@ +# +# Automatically generated make config: don't edit +# Linux/arm 3.0.36 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_NO_IOPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_FIQ=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="-Cyanogenmod" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_CHIP=y +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +CONFIG_TINY_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_TRACE is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_RCU_BOOST=y +CONFIG_RCU_BOOST_PRIO=1 +CONFIG_RCU_BOOST_DELAY=500 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +# CONFIG_CGROUP_MEM_RES_CTLR is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +# CONFIG_BLK_CGROUP is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_ASHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_COUNTERS=y +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +CONFIG_ARCH_S5PV210=y +# CONFIG_ARCH_EXYNOS4 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_PLAT_SAMSUNG=y + +# +# Boot options +# +# CONFIG_S3C_BOOT_ERROR_RESET is not set +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_SAMSUNG_IRQ_VIC_TIMER=y +CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_SAMSUNG_GPIOLIB_4BIT=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_CFG_S3C64XX=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S5P_GPIO_DRVSTR=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +# CONFIG_S3C_ADC is not set +CONFIG_S3C_DEV_HSMMC=y +CONFIG_S3C_DEV_HSMMC2=y +CONFIG_S3C_DEV_HSMMC3=y +CONFIG_S3C_DEV_I2C1=y +CONFIG_S3C_DEV_I2C2=y +CONFIG_S3C_DEV_WDT=y +CONFIG_SAMSUNG_DEV_PWM=y +# CONFIG_S3C24XX_PWM is not set +CONFIG_S3C_PL330_DMA=y + +# +# Power management +# +# CONFIG_SAMSUNG_PM_DEBUG is not set +# CONFIG_SAMSUNG_PM_CHECK is not set + +# +# Power Domain +# +CONFIG_PLAT_S5P=y +CONFIG_S5P_EXT_INT=y +CONFIG_S5P_HRT=y + +# +# System MMU +# +CONFIG_S5P_DEV_ONENAND=y +CONFIG_S5P_DEV_CSIS0=y +CONFIG_S5P_SETUP_MIPIPHY=y +CONFIG_S5P_DEV_FB=y +CONFIG_S5P_HIGH_RES_TIMERS=y +CONFIG_HRT_RTC=y +CONFIG_S5P_DEV_MFC=y +CONFIG_S5P_SETUP_MFC=y +CONFIG_CPU_S5PV210=y +# CONFIG_CPU_DIDLE is not set +CONFIG_S5PV210_SETUP_I2C1=y +CONFIG_S5PV210_SETUP_I2C2=y +CONFIG_S5PV210_SETUP_SDHCI=y +CONFIG_S5PV210_SETUP_SDHCI_GPIO=y +CONFIG_S5PV210_POWER_DOMAIN=y +CONFIG_S5PV210_CORESIGHT=y + +# +# MMC/SD slot setup +# + +# +# Use 8-bit bus width +# +CONFIG_S5PV210_SD_CH0_8BIT=y +# CONFIG_S5PV210_SD_CH2_8BIT is not set + +# +# S5PC110 Machines +# +# CONFIG_MACH_AQUILA is not set +# CONFIG_MACH_GONI is not set +# CONFIG_MACH_SMDKC110 is not set + +# +# S5PV210 Machines +# +# CONFIG_MACH_SMDKV210 is not set +# CONFIG_MACH_TORBRECK is not set +CONFIG_S5PV210_PM=y +CONFIG_MACH_HERRING=y +CONFIG_S5PV210_SETUP_FB=y +CONFIG_S5P_ADC=y +CONFIG_S5PV210_SETUP_FIMC0=y +CONFIG_S5PV210_SETUP_FIMC1=y +CONFIG_S5PV210_SETUP_FIMC2=y +CONFIG_WIFI_CONTROL_FUNC=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_754322 is not set +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=4 +CONFIG_PL330=y +CONFIG_FIQ_GLUE=y +CONFIG_FIQ_DEBUGGER=y +# CONFIG_FIQ_DEBUGGER_NO_SLEEP is not set +# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set +CONFIG_FIQ_DEBUGGER_CONSOLE=y +# CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=256 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttyFIQ0" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HAS_WAKELOCK=y +CONFIG_HAS_EARLYSUSPEND=y +CONFIG_WAKELOCK=y +CONFIG_WAKELOCK_STAT=y +CONFIG_USER_WAKELOCK=y +CONFIG_EARLYSUSPEND=y +# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set +CONFIG_FB_EARLYSUSPEND=y +CONFIG_PM_SLEEP=y +# CONFIG_PM_RUNTIME is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_APM_EMULATION=y +# CONFIG_SUSPEND_TIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +CONFIG_INET_ESP=y +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_CUBIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +CONFIG_TCP_CONG_VENO=y +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +CONFIG_DEFAULT_VENO=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="veno" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +# CONFIG_IPV6_ROUTE_INFO is not set +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_ANDROID_PARANOID_NETWORK=y +CONFIG_NET_ACTIVITY_STATS=y +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_BROADCAST=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_HL=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_LOG=y +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_NF_NAT_PROTO_DCCP=y +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_PROTO_UDPLITE=y +CONFIG_NF_NAT_PROTO_SCTP=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=y +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_AMANDA=y +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_PHONET=y +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +CONFIG_NET_SCH_SFB=y +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_INGRESS is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +CONFIG_NET_EMATCH_U32=y +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +# CONFIG_GACT_PROB is not set +CONFIG_NET_ACT_MIRRED=y +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +# CONFIG_BT_BNEP_MC_FILTER is not set +# CONFIG_BT_BNEP_PROTO_FILTER is not set +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +# CONFIG_CFG80211_WEXT is not set +# CONFIG_LIB80211 is not set +CONFIG_CFG80211_ALLOW_RECONNECT=y +# CONFIG_MAC80211 is not set +CONFIG_WIMAX=y +CONFIG_WIMAX_DEBUG_LEVEL=8 +CONFIG_RFKILL=y +CONFIG_RFKILL_PM=y +CONFIG_RFKILL_INPUT=y +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND_IDS is not set +# CONFIG_MTD_NAND is not set +CONFIG_MTD_ONENAND=y +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set +# CONFIG_MTD_ONENAND_GENERIC is not set +CONFIG_MTD_ONENAND_SAMSUNG=y +# CONFIG_MTD_ONENAND_OTP is not set +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set +# CONFIG_MTD_ONENAND_SIM is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ANDROID_PMEM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +CONFIG_SENSORS_AK8973=y +# CONFIG_SENSORS_AK8975 is not set +CONFIG_SENSORS_KR3DM=y +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_UID_STAT=y +# CONFIG_BMP085 is not set +# CONFIG_WL127X_RFKILL is not set +CONFIG_APANIC=y +CONFIG_APANIC_PLABEL="kpanic" +CONFIG_SAMSUNG_JACK=y +CONFIG_USB_SWITCH_FSA9480=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +CONFIG_SAMSUNG_MODEMCTL=y +CONFIG_PN544=y +CONFIG_GENERIC_BLN=y +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_IFB=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_MII is not set +# CONFIG_PHYLIB is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +# CONFIG_STMMAC_ETH is not set +CONFIG_NETDEV_10000=y +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_BCM4329 is not set +CONFIG_BCMDHD=y +CONFIG_BCMDHD_FW_PATH="/vendor/firmware/fw_bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/vendor/firmware/nvram_net.txt" +# CONFIG_DHD_USE_STATIC_BUF is not set +# CONFIG_DHD_USE_SCHED_SCAN is not set +# CONFIG_DHD_ENABLE_P2P is not set +# CONFIG_HOSTAP is not set +# CONFIG_IWM is not set +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set + +# +# WiMAX Wireless Broadband devices +# +# CONFIG_WIMAX_I2400M_USB is not set +# CONFIG_WIMAX_I2400M_SDIO is not set +CONFIG_WIMAX_CMC7XX=y +# CONFIG_WIMAX_CMC7XX_DEBUG is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_CDC_PHONET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set + +# +# CAIF transport drivers +# +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +# CONFIG_PPPOE is not set +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set +# CONFIG_INPUT_KEYRESET is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYPAD_CYPRESS_TOUCH=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXT224=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +CONFIG_GYRO_K3G=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +CONFIG_INPUT_KEYCHORD=y +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set +CONFIG_OPTICAL_GP2A=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS_4=y +CONFIG_SERIAL_SAMSUNG_UARTS=4 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S5PV210=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DCC_TTY is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +CONFIG_HAVE_S3C2410_I2C=y +CONFIG_I2C_S3C2410=y +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_BASIC_MMIO is not set +# CONFIG_GPIO_IT8761E is not set +CONFIG_GPIO_PLAT_SAMSUNG=y +CONFIG_GPIO_S5PV210=y +# CONFIG_GPIO_PL061 is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_APM_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ20Z75 is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_BATTERY_MAX17040=y +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_S3C is not set +CONFIG_BATTERY_S5PC110=y +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set +CONFIG_MFD_SUPPORT=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +CONFIG_MFD_MAX8998=y +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65910 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=y +# CONFIG_REGULATOR_MAX8952 is not set +CONFIG_REGULATOR_MAX8998=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_MEDIA_CONTROLLER is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_VIDEO_SAMSUNG_S5P_FIMC is not set +# CONFIG_V4L_USB_DRIVERS is not set +CONFIG_VIDEO_S5KA3DFX=y +CONFIG_VIDEO_S5K4ECGX=y +# CONFIG_VIDEO_S5K4ECGX_DEBUG is not set +CONFIG_VIDEO_S5K4ECGX_V_1_0=y +CONFIG_VIDEO_S5K4ECGX_V_1_1=y +CONFIG_VIDEO_SAMSUNG=y +CONFIG_VIDEO_SAMSUNG_V4L2=y +CONFIG_VIDEO_FIMC=y +CONFIG_VIDEO_FIMC_RANGE_NARROW=y +# CONFIG_VIDEO_FIMC_RANGE_WIDE is not set +# CONFIG_VIDEO_FIMC_DEBUG is not set +# CONFIG_VIDEO_FIMC_MIPI is not set +CONFIG_VIDEO_MFC50=y +CONFIG_VIDEO_MFC_MAX_INSTANCE=4 +# CONFIG_VIDEO_MFC50_DEBUG is not set +CONFIG_VIDEO_JPEG_V2=y +# CONFIG_VIDEO_JPEG_DEBUG is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_ION is not set +CONFIG_PVR_SGX=y +CONFIG_PVR_BUILD_RELEASE=y +# CONFIG_PVR_BUILD_DEBUG is not set +CONFIG_PVR_NEED_PVR_DPF=y +CONFIG_PVR_NEED_PVR_ASSERT=y +CONFIG_PVR_PERCONTEXT_PB=y +CONFIG_PVR_ACTIVE_POWER_MANAGEMENT=y +CONFIG_PVR_ACTIVE_POWER_LATENCY_MS=100 +CONFIG_PVR_SGX_LOW_LATENCY_SCHEDULING=y +CONFIG_PVR_USSE_EDM_STATUS_DEBUG=y +CONFIG_PVR_DUMP_MK_TRACE=y +# CONFIG_PVR_PDUMP is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_S3C=y +# CONFIG_FB_S3C_SPLASH_SCREEN is not set +CONFIG_FB_S3C_LCD_INIT=y +# CONFIG_FB_S3C_DEBUG is not set +# CONFIG_FB_S3C_TRACE_UNDERRUN is not set +CONFIG_FB_S3C_DEFAULT_WINDOW=2 +CONFIG_FB_S3C_NR_BUFFERS=7 +CONFIG_FB_S3C_NUM_OVLY_WIN=1 +CONFIG_FB_S3C_NUM_BUF_OVLY_WIN=3 +# CONFIG_FB_S3C_VIRTUAL is not set +CONFIG_FB_S3C_TL2796=y +CONFIG_FB_VOODOO=y +# CONFIG_FB_VOODOO_DEBUG_LOG is not set +CONFIG_FB_S3C_NT35580=y +# CONFIG_FB_S3C_LVDS is not set +# CONFIG_FB_S3C_AMS701KA is not set +# CONFIG_FB_S3C_MDNIE is not set +CONFIG_TL2796_CONVERT_COLORS_RES=y +# CONFIG_FB_S3C_CMC623 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_PWM is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_SOC=y +# CONFIG_SND_SOC_CACHE_LZO is not set +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_S5PC1XX_I2S=y +CONFIG_S5P_INTERNAL_DMA=y +CONFIG_SND_S5P_WM8994_MASTER=y +CONFIG_SND_SOC_SAMSUNG_HERRING_WM8994=y +CONFIG_SND_VOODOO=y +CONFIG_SND_VOODOO_HP_LEVEL_CONTROL=y +CONFIG_SND_VOODOO_HP_LEVEL=54 +CONFIG_SND_VOODOO_RECORD_PRESETS=y +# CONFIG_SND_VOODOO_DEVELOPMENT is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_WM8994_SAMSUNG=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +# CONFIG_HID_APPLE is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_WACOM is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_S3C_OTG_HOST=y +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC_OTG=y +CONFIG_DWC_DEBUG=y +CONFIG_DWC_HOST_ONLY=y +# CONFIG_DWC_OTG_MODE is not set +# CONFIG_DWC_DEVICE_ONLY is not set +# CONFIG_DWC_SLAVE is not set +CONFIG_DWC_DMA_MODE=y +CONFIG_DWC_OTG_REG_LE=y +CONFIG_DWC_OTG_FIFO_LE=y + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_FUSB300 is not set +# CONFIG_USB_GADGET_R8A66597 is not set +CONFIG_USB_GADGET_S3C_OTGD=y +# CONFIG_USB_GADGET_PXA_U2O is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set + +# +# NOTE: S3C OTG device role enables the controller driver below +# +CONFIG_USB_S3C_OTGD=y +CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y +# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_G_ANDROID=y +CONFIG_USB_ANDROID_RNDIS_DWORD_ALIGNED=y +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_OTG_WAKELOCK is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +CONFIG_NOP_USB_XCEIV=y +# CONFIG_USB_HOST_NOTIFY is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_EMBEDDED_SDIO is not set +# CONFIG_MMC_PARANOID_SD_INIT is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PLTFM is not set +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_NFC_DEVICES is not set +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_ALARM=y +CONFIG_RTC_INTF_ALARM_DEV=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX8998 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_HAVE_S3C_RTC=y +CONFIG_RTC_DRV_S3C=y +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +CONFIG_STAGING=y +# CONFIG_USBIP_CORE is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_ECHO is not set +# CONFIG_BRCMUTIL is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_R8712U is not set +# CONFIG_TRANZPORT is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128 +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16 +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8 +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d +# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set +CONFIG_ANDROID_TIMED_OUTPUT=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +# CONFIG_POHMELFS is not set +# CONFIG_LINE6_USB is not set +# CONFIG_VT6656 is not set +# CONFIG_IIO is not set +CONFIG_XVMALLOC=y +CONFIG_ZRAM=y +# CONFIG_ZRAM_DEBUG is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_EASYCAP is not set +CONFIG_MACH_NO_WESTBRIDGE=y +# CONFIG_ATH6K_LEGACY is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +# CONFIG_EXT4_FS_XATTR is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set +# CONFIG_YAFFS_DISABLE_BACKGROUND is not set +CONFIG_YAFFS_XATTR=y +# CONFIG_JFFS2_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_PSTORE is not set +CONFIG_SYSV_FS=y +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +CONFIG_NFSD_DEPRECATED=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_SOLARIS_X86_PARTITION=y +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_LL is not set +CONFIG_OC_ETM=y +CONFIG_DEBUG_S3C_UART=2 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_S5P is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=y +CONFIG_TEXTSEARCH_BM=y +CONFIG_TEXTSEARCH_FSM=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +# CONFIG_AVERAGE is not set diff --git a/arch/arm/configs/herring_defconfig b/arch/arm/configs/herring_defconfig new file mode 100644 index 0000000..74d6850 --- /dev/null +++ b/arch/arm/configs/herring_defconfig @@ -0,0 +1,408 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_ASHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_PERF_COUNTERS=y +CONFIG_PROFILING=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_S5PV210=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_S5P_HIGH_RES_TIMERS=y +CONFIG_S5PV210_SD_CH0_8BIT=y +CONFIG_MACH_HERRING=y +CONFIG_WIFI_CONTROL_FUNC=y +CONFIG_ARM_THUMBEE=y +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_COMPACTION=y +CONFIG_KSM=y +CONFIG_CMDLINE="console=ttyFIQ0" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_WAKELOCK=y +CONFIG_APM_EMULATION=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_PHONET=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_WEXT is not set +CONFIG_CFG80211_ALLOW_RECONNECT=y +CONFIG_WIMAX=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_SAMSUNG=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_MISC_DEVICES=y +CONFIG_SENSORS_AK8973=y +CONFIG_SENSORS_KR3DM=y +CONFIG_UID_STAT=y +CONFIG_APANIC=y +CONFIG_SAMSUNG_JACK=y +CONFIG_USB_SWITCH_FSA9480=y +CONFIG_SAMSUNG_MODEMCTL=y +CONFIG_PN544=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_IFB=y +CONFIG_TUN=y +CONFIG_BCMDHD=y +CONFIG_BCMDHD_FW_PATH="/vendor/firmware/fw_bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/vendor/firmware/nvram_net.txt" +CONFIG_WIMAX_CMC7XX=y +CONFIG_PPP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYPAD_CYPRESS_TOUCH=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=y +CONFIG_TABLET_USB_AIPTEK=y +CONFIG_TABLET_USB_GTCO=y +CONFIG_TABLET_USB_HANWANG=y +CONFIG_TABLET_USB_KBTAB=y +CONFIG_TABLET_USB_WACOM=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_MXT224=y +CONFIG_INPUT_MISC=y +CONFIG_GYRO_K3G=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +CONFIG_OPTICAL_GP2A=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_S3C2410=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_BATTERY_MAX17040=y +CONFIG_BATTERY_S5PC110=y +# CONFIG_HWMON is not set +CONFIG_MFD_MAX8998=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_MAX8893=y +CONFIG_REGULATOR_MAX8998=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_S5KA3DFX=y +CONFIG_VIDEO_S5K4ECGX=y +CONFIG_VIDEO_SAMSUNG=y +CONFIG_VIDEO_SAMSUNG_V4L2=y +CONFIG_VIDEO_FIMC=y +# CONFIG_VIDEO_FIMC_MIPI is not set +CONFIG_VIDEO_MFC50=y +CONFIG_VIDEO_JPEG_V2=y +CONFIG_PVR_SGX=y +CONFIG_PVR_NEED_PVR_DPF=y +CONFIG_PVR_NEED_PVR_ASSERT=y +CONFIG_PVR_USSE_EDM_STATUS_DEBUG=y +CONFIG_PVR_LINUX_MEM_AREA_POOL=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_FB_S3C_NR_BUFFERS=7 +CONFIG_FB_S3C_TL2796=y +CONFIG_FB_S3C_NT35580=y +# CONFIG_FB_S3C_LVDS is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_SAMSUNG_HERRING_WM8994=y +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +CONFIG_HID_ELECOM=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWII_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +CONFIG_HID_QUANTA=y +CONFIG_HID_ROCCAT_ARVO=y +CONFIG_HID_ROCCAT_KONE=y +CONFIG_HID_ROCCAT_KONEPLUS=y +CONFIG_HID_ROCCAT_KOVAPLUS=y +CONFIG_HID_ROCCAT_PYRA=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=y +CONFIG_HID_ZEROPLUS=y +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_G_ANDROID=y +CONFIG_USB_ANDROID_RNDIS_DWORD_ALIGNED=y +CONFIG_USB=y +CONFIG_USB_S3C_OTG_HOST=y +CONFIG_USB_DWC_OTG=y +CONFIG_DWC_DEBUG=y +CONFIG_DWC_HOST_ONLY=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_ACM=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_EXT2_FS=y +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_XATTR is not set +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_YAFFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_SYSV_FS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_SCHED_TRACER=y +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_S3C_UART=2 +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRC_CCITT=y diff --git a/arch/arm/include/asm/fiq_debugger.h b/arch/arm/include/asm/fiq_debugger.h new file mode 100644 index 0000000..4d27488 --- /dev/null +++ b/arch/arm/include/asm/fiq_debugger.h @@ -0,0 +1,64 @@ +/* + * arch/arm/include/asm/fiq_debugger.h + * + * Copyright (C) 2010 Google, Inc. + * Author: Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARCH_ARM_MACH_TEGRA_FIQ_DEBUGGER_H_ +#define _ARCH_ARM_MACH_TEGRA_FIQ_DEBUGGER_H_ + +#include <linux/serial_core.h> + +#define FIQ_DEBUGGER_NO_CHAR NO_POLL_CHAR +#define FIQ_DEBUGGER_BREAK 0x00ff0100 + +#define FIQ_DEBUGGER_FIQ_IRQ_NAME "fiq" +#define FIQ_DEBUGGER_SIGNAL_IRQ_NAME "signal" +#define FIQ_DEBUGGER_WAKEUP_IRQ_NAME "wakeup" + +/** + * struct fiq_debugger_pdata - fiq debugger platform data + * @uart_resume: used to restore uart state right before enabling + * the fiq. + * @uart_enable: Do the work necessary to communicate with the uart + * hw (enable clocks, etc.). This must be ref-counted. + * @uart_disable: Do the work necessary to disable the uart hw + * (disable clocks, etc.). This must be ref-counted. + * @uart_dev_suspend: called during PM suspend, generally not needed + * for real fiq mode debugger. + * @uart_dev_resume: called during PM resume, generally not needed + * for real fiq mode debugger. + */ +struct fiq_debugger_pdata { + int (*uart_init)(struct platform_device *pdev); + void (*uart_free)(struct platform_device *pdev); + int (*uart_resume)(struct platform_device *pdev); + int (*uart_getc)(struct platform_device *pdev); + void (*uart_putc)(struct platform_device *pdev, unsigned int c); + void (*uart_flush)(struct platform_device *pdev); + void (*uart_enable)(struct platform_device *pdev); + void (*uart_disable)(struct platform_device *pdev); + + int (*uart_dev_suspend)(struct platform_device *pdev); + int (*uart_dev_resume)(struct platform_device *pdev); + + void (*fiq_enable)(struct platform_device *pdev, unsigned int fiq, + bool enable); + void (*fiq_ack)(struct platform_device *pdev, unsigned int fiq); + + void (*force_irq)(struct platform_device *pdev, unsigned int irq); + void (*force_irq_ack)(struct platform_device *pdev, unsigned int irq); +}; + +#endif diff --git a/arch/arm/include/asm/fiq_glue.h b/arch/arm/include/asm/fiq_glue.h new file mode 100644 index 0000000..d54c29d --- /dev/null +++ b/arch/arm/include/asm/fiq_glue.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_FIQ_GLUE_H +#define __ASM_FIQ_GLUE_H + +struct fiq_glue_handler { + void (*fiq)(struct fiq_glue_handler *h, void *regs, void *svc_sp); + void (*resume)(struct fiq_glue_handler *h); +}; + +int fiq_glue_register_handler(struct fiq_glue_handler *handler); + +#ifdef CONFIG_FIQ_GLUE +void fiq_glue_resume(void); +#else +static inline void fiq_glue_resume(void) {} +#endif + +#endif diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index 89ad180..2635c8b 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -5,7 +5,7 @@ #include <linux/threads.h> #include <asm/irq.h> -#define NR_IPI 5 +#define NR_IPI 6 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index bfa706f..2a20876 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -57,6 +57,7 @@ #define L2X0_STNDBY_MODE_EN (1 << 0) /* Registers shifts and masks */ +#define L2X0_CACHE_ID_REV_MASK (0x3f) #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L210 (1 << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) @@ -72,6 +73,8 @@ #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 +#define REV_PL310_R2P0 4 + #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); #endif diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index 7ecd793..6643d6c 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -17,15 +17,17 @@ #define TRACER_ACCESSED_BIT 0 #define TRACER_RUNNING_BIT 1 #define TRACER_CYCLE_ACC_BIT 2 +#define TRACER_TRACE_DATA_BIT 3 #define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT) #define TRACER_RUNNING BIT(TRACER_RUNNING_BIT) #define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT) +#define TRACER_TRACE_DATA BIT(TRACER_TRACE_DATA_BIT) #define TRACER_TIMEOUT 10000 -#define etm_writel(t, v, x) \ - (__raw_writel((v), (t)->etm_regs + (x))) -#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x))) +#define etm_writel(t, id, v, x) \ + (__raw_writel((v), (t)->etm_regs[(id)] + (x))) +#define etm_readl(t, id, x) (__raw_readl((t)->etm_regs[(id)] + (x))) /* CoreSight Management Registers */ #define CSMR_LOCKACCESS 0xfb0 @@ -113,11 +115,19 @@ #define ETMR_TRACEENCTRL 0x24 #define ETMTE_INCLEXCL BIT(24) #define ETMR_TRACEENEVT 0x20 + +#define ETMR_VIEWDATAEVT 0x30 +#define ETMR_VIEWDATACTRL1 0x34 +#define ETMR_VIEWDATACTRL2 0x38 +#define ETMR_VIEWDATACTRL3 0x3c +#define ETMVDC3_EXCLONLY BIT(16) + #define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ - ETMCTRL_DATA_DO_ADDR | \ ETMCTRL_BRANCH_OUTPUT | \ ETMCTRL_DO_CONTEXTID) +#define ETMR_TRACEIDR 0x200 + /* ETM management registers, "ETM Architecture", 3.5.24 */ #define ETMMR_OSLAR 0x300 #define ETMMR_OSLSR 0x304 @@ -140,14 +150,16 @@ #define ETBFF_TRIGIN BIT(8) #define ETBFF_TRIGEVT BIT(9) #define ETBFF_TRIGFL BIT(10) +#define ETBFF_STOPFL BIT(12) #define etb_writel(t, v, x) \ (__raw_writel((v), (t)->etb_regs + (x))) #define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x))) -#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0) -#define etm_unlock(t) \ - do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) +#define etm_lock(t, id) \ + do { etm_writel((t), (id), 0, CSMR_LOCKACCESS); } while (0) +#define etm_unlock(t, id) \ + do { etm_writel((t), (id), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) #define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0) #define etb_unlock(t) \ diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h index 5d72550..ec34fc7 100644 --- a/arch/arm/include/asm/hardware/vic.h +++ b/arch/arm/include/asm/hardware/vic.h @@ -42,6 +42,7 @@ #ifndef __ASSEMBLY__ void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); +int vic_set_fiq(unsigned int irq, bool enable); #endif #endif diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 2721a58..28810c6 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -25,6 +25,9 @@ extern void migrate_irqs(void); extern void asm_do_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); +void arch_trigger_all_cpu_backtrace(void); +#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace + #endif #endif diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h new file mode 100644 index 0000000..bca864a --- /dev/null +++ b/arch/arm/include/asm/mach/mmc.h @@ -0,0 +1,28 @@ +/* + * arch/arm/include/asm/mach/mmc.h + */ +#ifndef ASMARM_MACH_MMC_H +#define ASMARM_MACH_MMC_H + +#include <linux/mmc/host.h> +#include <linux/mmc/card.h> +#include <linux/mmc/sdio_func.h> + +struct embedded_sdio_data { + struct sdio_cis cis; + struct sdio_cccr cccr; + struct sdio_embedded_func *funcs; + int num_funcs; +}; + +struct mmc_platform_data { + unsigned int ocr_mask; /* available voltages */ + int built_in; /* built-in device flag */ + int card_present; /* card detect state */ + u32 (*translate_vdd)(struct device *, unsigned int); + unsigned int (*status)(struct device *); + struct embedded_sdio_data *embedded_sdio; + int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); +}; + +#endif diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index e42d96a..74f288f 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -93,4 +93,6 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); */ extern void show_local_irqs(struct seq_file *, int); +extern void smp_send_all_cpu_backtrace(void); + #endif /* ifndef __ASM_ARM_SMP_H */ diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 90c62cd..2cd0076 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -496,7 +496,7 @@ __und_usr: blo __und_usr_unknown 3: ldrht r0, [r4] add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 - orr r0, r0, r5, lsl #16 + orr r0, r0, r5, lsl #16 #else b __und_usr_unknown #endif diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 1bec8b5..496b8b8 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/types.h> #include <linux/io.h> +#include <linux/slab.h> #include <linux/sysrq.h> #include <linux/device.h> #include <linux/clk.h> @@ -36,26 +37,36 @@ MODULE_AUTHOR("Alexander Shishkin"); struct tracectx { unsigned int etb_bufsz; void __iomem *etb_regs; - void __iomem *etm_regs; + void __iomem **etm_regs; + int etm_regs_count; unsigned long flags; int ncmppairs; int etm_portsz; + u32 etb_fc; + unsigned long range_start; + unsigned long range_end; + unsigned long data_range_start; + unsigned long data_range_end; + bool dump_initial_etb; struct device *dev; struct clk *emu_clk; struct mutex mutex; }; -static struct tracectx tracer; +static struct tracectx tracer = { + .range_start = (unsigned long)_stext, + .range_end = (unsigned long)_etext, +}; static inline bool trace_isrunning(struct tracectx *t) { return !!(t->flags & TRACER_RUNNING); } -static int etm_setup_address_range(struct tracectx *t, int n, +static int etm_setup_address_range(struct tracectx *t, int id, int n, unsigned long start, unsigned long end, int exclude, int data) { - u32 flags = ETMAAT_ARM | ETMAAT_IGNCONTEXTID | ETMAAT_NSONLY | \ + u32 flags = ETMAAT_ARM | ETMAAT_IGNCONTEXTID | ETMAAT_IGNSECURITY | ETMAAT_NOVALCMP; if (n < 1 || n > t->ncmppairs) @@ -71,95 +82,155 @@ static int etm_setup_address_range(struct tracectx *t, int n, flags |= ETMAAT_IEXEC; /* first comparator for the range */ - etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2)); - etm_writel(t, start, ETMR_COMP_VAL(n * 2)); + etm_writel(t, id, flags, ETMR_COMP_ACC_TYPE(n * 2)); + etm_writel(t, id, start, ETMR_COMP_VAL(n * 2)); /* second comparator is right next to it */ - etm_writel(t, flags, ETMR_COMP_ACC_TYPE(n * 2 + 1)); - etm_writel(t, end, ETMR_COMP_VAL(n * 2 + 1)); - - flags = exclude ? ETMTE_INCLEXCL : 0; - etm_writel(t, flags | (1 << n), ETMR_TRACEENCTRL); + etm_writel(t, id, flags, ETMR_COMP_ACC_TYPE(n * 2 + 1)); + etm_writel(t, id, end, ETMR_COMP_VAL(n * 2 + 1)); + + if (data) { + flags = exclude ? ETMVDC3_EXCLONLY : 0; + if (exclude) + n += 8; + etm_writel(t, id, flags | BIT(n), ETMR_VIEWDATACTRL3); + } else { + flags = exclude ? ETMTE_INCLEXCL : 0; + etm_writel(t, id, flags | (1 << n), ETMR_TRACEENCTRL); + } return 0; } -static int trace_start(struct tracectx *t) +static int trace_start_etm(struct tracectx *t, int id) { u32 v; unsigned long timeout = TRACER_TIMEOUT; - etb_unlock(t); - - etb_writel(t, 0, ETBR_FORMATTERCTRL); - etb_writel(t, 1, ETBR_CTRL); - - etb_lock(t); - - /* configure etm */ v = ETMCTRL_OPTS | ETMCTRL_PROGRAM | ETMCTRL_PORTSIZE(t->etm_portsz); if (t->flags & TRACER_CYCLE_ACC) v |= ETMCTRL_CYCLEACCURATE; - etm_unlock(t); + if (t->flags & TRACER_TRACE_DATA) + v |= ETMCTRL_DATA_DO_ADDR; + + etm_unlock(t, id); - etm_writel(t, v, ETMR_CTRL); + etm_writel(t, id, v, ETMR_CTRL); - while (!(etm_readl(t, ETMR_CTRL) & ETMCTRL_PROGRAM) && --timeout) + while (!(etm_readl(t, id, ETMR_CTRL) & ETMCTRL_PROGRAM) && --timeout) ; if (!timeout) { dev_dbg(t->dev, "Waiting for progbit to assert timed out\n"); - etm_lock(t); + etm_lock(t, id); return -EFAULT; } - etm_setup_address_range(t, 1, (unsigned long)_stext, - (unsigned long)_etext, 0, 0); - etm_writel(t, 0, ETMR_TRACEENCTRL2); - etm_writel(t, 0, ETMR_TRACESSCTRL); - etm_writel(t, 0x6f, ETMR_TRACEENEVT); + if (t->range_start || t->range_end) + etm_setup_address_range(t, id, 1, + t->range_start, t->range_end, 0, 0); + else + etm_writel(t, id, ETMTE_INCLEXCL, ETMR_TRACEENCTRL); + + etm_writel(t, id, 0, ETMR_TRACEENCTRL2); + etm_writel(t, id, 0, ETMR_TRACESSCTRL); + etm_writel(t, id, 0x6f, ETMR_TRACEENEVT); + + etm_writel(t, id, 0, ETMR_VIEWDATACTRL1); + etm_writel(t, id, 0, ETMR_VIEWDATACTRL2); + + if (t->data_range_start || t->data_range_end) + etm_setup_address_range(t, id, 2, t->data_range_start, + t->data_range_end, 0, 1); + else + etm_writel(t, id, ETMVDC3_EXCLONLY, ETMR_VIEWDATACTRL3); + + etm_writel(t, id, 0x6f, ETMR_VIEWDATAEVT); v &= ~ETMCTRL_PROGRAM; v |= ETMCTRL_PORTSEL; - etm_writel(t, v, ETMR_CTRL); + etm_writel(t, id, v, ETMR_CTRL); timeout = TRACER_TIMEOUT; - while (etm_readl(t, ETMR_CTRL) & ETMCTRL_PROGRAM && --timeout) + while (etm_readl(t, id, ETMR_CTRL) & ETMCTRL_PROGRAM && --timeout) ; if (!timeout) { dev_dbg(t->dev, "Waiting for progbit to deassert timed out\n"); - etm_lock(t); + etm_lock(t, id); return -EFAULT; } - etm_lock(t); + etm_lock(t, id); + return 0; +} + +static int trace_start(struct tracectx *t) +{ + int ret; + int id; + u32 etb_fc = t->etb_fc; + + etb_unlock(t); + + t->dump_initial_etb = false; + etb_writel(t, 0, ETBR_WRITEADDR); + etb_writel(t, etb_fc, ETBR_FORMATTERCTRL); + etb_writel(t, 1, ETBR_CTRL); + + etb_lock(t); + + /* configure etm(s) */ + for (id = 0; id < t->etm_regs_count; id++) { + ret = trace_start_etm(t, id); + if (ret) + return ret; + } t->flags |= TRACER_RUNNING; return 0; } -static int trace_stop(struct tracectx *t) +static int trace_stop_etm(struct tracectx *t, int id) { unsigned long timeout = TRACER_TIMEOUT; - etm_unlock(t); + etm_unlock(t, id); - etm_writel(t, 0x440, ETMR_CTRL); - while (!(etm_readl(t, ETMR_CTRL) & ETMCTRL_PROGRAM) && --timeout) + etm_writel(t, id, 0x441, ETMR_CTRL); + while (!(etm_readl(t, id, ETMR_CTRL) & ETMCTRL_PROGRAM) && --timeout) ; if (!timeout) { dev_dbg(t->dev, "Waiting for progbit to assert timed out\n"); - etm_lock(t); + etm_lock(t, id); return -EFAULT; } - etm_lock(t); + etm_lock(t, id); + return 0; +} + +static int trace_stop(struct tracectx *t) +{ + int id; + int ret; + unsigned long timeout = TRACER_TIMEOUT; + u32 etb_fc = t->etb_fc; + + for (id = 0; id < t->etm_regs_count; id++) { + ret = trace_stop_etm(t, id); + if (ret) + return ret; + } etb_unlock(t); - etb_writel(t, ETBFF_MANUAL_FLUSH, ETBR_FORMATTERCTRL); + if (etb_fc) { + etb_fc |= ETBFF_STOPFL; + etb_writel(t, t->etb_fc, ETBR_FORMATTERCTRL); + } + etb_writel(t, etb_fc | ETBFF_MANUAL_FLUSH, ETBR_FORMATTERCTRL); timeout = TRACER_TIMEOUT; while (etb_readl(t, ETBR_FORMATTERCTRL) & @@ -184,24 +255,15 @@ static int trace_stop(struct tracectx *t) static int etb_getdatalen(struct tracectx *t) { u32 v; - int rp, wp; + int wp; v = etb_readl(t, ETBR_STATUS); if (v & 1) return t->etb_bufsz; - rp = etb_readl(t, ETBR_READADDR); wp = etb_readl(t, ETBR_WRITEADDR); - - if (rp > wp) { - etb_writel(t, 0, ETBR_READADDR); - etb_writel(t, 0, ETBR_WRITEADDR); - - return 0; - } - - return wp - rp; + return wp; } /* sysrq+v will always stop the running trace and leave it at that */ @@ -234,21 +296,18 @@ static void etm_dump(void) printk("%08x", cpu_to_be32(etb_readl(t, ETBR_READMEM))); printk(KERN_INFO "\n--- ETB buffer end ---\n"); - /* deassert the overflow bit */ - etb_writel(t, 1, ETBR_CTRL); - etb_writel(t, 0, ETBR_CTRL); - - etb_writel(t, 0, ETBR_TRIGGERCOUNT); - etb_writel(t, 0, ETBR_READADDR); - etb_writel(t, 0, ETBR_WRITEADDR); - etb_lock(t); } static void sysrq_etm_dump(int key) { + if (!mutex_trylock(&tracer.mutex)) { + printk(KERN_INFO "Tracing hardware busy\n"); + return; + } dev_dbg(tracer.dev, "Dumping ETB buffer\n"); etm_dump(); + mutex_unlock(&tracer.mutex); } static struct sysrq_key_op sysrq_etm_op = { @@ -275,6 +334,10 @@ static ssize_t etb_read(struct file *file, char __user *data, struct tracectx *t = file->private_data; u32 first = 0; u32 *buf; + int wpos; + int skip; + long wlength; + loff_t pos = *ppos; mutex_lock(&t->mutex); @@ -286,31 +349,39 @@ static ssize_t etb_read(struct file *file, char __user *data, etb_unlock(t); total = etb_getdatalen(t); + if (total == 0 && t->dump_initial_etb) + total = t->etb_bufsz; if (total == t->etb_bufsz) first = etb_readl(t, ETBR_WRITEADDR); + if (pos > total * 4) { + skip = 0; + wpos = total; + } else { + skip = (int)pos % 4; + wpos = (int)pos / 4; + } + total -= wpos; + first = (first + wpos) % t->etb_bufsz; + etb_writel(t, first, ETBR_READADDR); - length = min(total * 4, (int)len); - buf = vmalloc(length); + wlength = min(total, DIV_ROUND_UP(skip + (int)len, 4)); + length = min(total * 4 - skip, (int)len); + buf = vmalloc(wlength * 4); - dev_dbg(t->dev, "ETB buffer length: %d\n", total); + dev_dbg(t->dev, "ETB read %ld bytes to %lld from %ld words at %d\n", + length, pos, wlength, first); + dev_dbg(t->dev, "ETB buffer length: %d\n", total + wpos); dev_dbg(t->dev, "ETB status reg: %x\n", etb_readl(t, ETBR_STATUS)); - for (i = 0; i < length / 4; i++) + for (i = 0; i < wlength; i++) buf[i] = etb_readl(t, ETBR_READMEM); - /* the only way to deassert overflow bit in ETB status is this */ - etb_writel(t, 1, ETBR_CTRL); - etb_writel(t, 0, ETBR_CTRL); - - etb_writel(t, 0, ETBR_WRITEADDR); - etb_writel(t, 0, ETBR_READADDR); - etb_writel(t, 0, ETBR_TRIGGERCOUNT); - etb_lock(t); - length -= copy_to_user(data, buf, length); + length -= copy_to_user(data, (u8 *)buf + skip, length); vfree(buf); + *ppos = pos + length; out: mutex_unlock(&t->mutex); @@ -347,28 +418,17 @@ static int __devinit etb_probe(struct amba_device *dev, const struct amba_id *id if (ret) goto out; + mutex_lock(&t->mutex); t->etb_regs = ioremap_nocache(dev->res.start, resource_size(&dev->res)); if (!t->etb_regs) { ret = -ENOMEM; goto out_release; } + t->dev = &dev->dev; + t->dump_initial_etb = true; amba_set_drvdata(dev, t); - etb_miscdev.parent = &dev->dev; - - ret = misc_register(&etb_miscdev); - if (ret) - goto out_unmap; - - t->emu_clk = clk_get(&dev->dev, "emu_src_ck"); - if (IS_ERR(t->emu_clk)) { - dev_dbg(&dev->dev, "Failed to obtain emu_src_ck.\n"); - return -EFAULT; - } - - clk_enable(t->emu_clk); - etb_unlock(t); t->etb_bufsz = etb_readl(t, ETBR_DEPTH); dev_dbg(&dev->dev, "Size: %x\n", t->etb_bufsz); @@ -377,6 +437,20 @@ static int __devinit etb_probe(struct amba_device *dev, const struct amba_id *id etb_writel(t, 0, ETBR_CTRL); etb_writel(t, 0x1000, ETBR_FORMATTERCTRL); etb_lock(t); + mutex_unlock(&t->mutex); + + etb_miscdev.parent = &dev->dev; + + ret = misc_register(&etb_miscdev); + if (ret) + goto out_unmap; + + /* Get optional clock. Currently used to select clock source on omap3 */ + t->emu_clk = clk_get(&dev->dev, "emu_src_ck"); + if (IS_ERR(t->emu_clk)) + dev_dbg(&dev->dev, "Failed to obtain emu_src_ck.\n"); + else + clk_enable(t->emu_clk); dev_dbg(&dev->dev, "ETB AMBA driver initialized.\n"); @@ -384,10 +458,13 @@ out: return ret; out_unmap: + mutex_lock(&t->mutex); amba_set_drvdata(dev, NULL); iounmap(t->etb_regs); + t->etb_regs = NULL; out_release: + mutex_unlock(&t->mutex); amba_release_regions(dev); return ret; @@ -402,8 +479,10 @@ static int etb_remove(struct amba_device *dev) iounmap(t->etb_regs); t->etb_regs = NULL; - clk_disable(t->emu_clk); - clk_put(t->emu_clk); + if (!IS_ERR(t->emu_clk)) { + clk_disable(t->emu_clk); + clk_put(t->emu_clk); + } amba_release_regions(dev); @@ -447,7 +526,10 @@ static ssize_t trace_running_store(struct kobject *kobj, return -EINVAL; mutex_lock(&tracer.mutex); - ret = value ? trace_start(&tracer) : trace_stop(&tracer); + if (!tracer.etb_regs) + ret = -ENODEV; + else + ret = value ? trace_start(&tracer) : trace_stop(&tracer); mutex_unlock(&tracer.mutex); return ret ? : n; @@ -462,36 +544,50 @@ static ssize_t trace_info_show(struct kobject *kobj, { u32 etb_wa, etb_ra, etb_st, etb_fc, etm_ctrl, etm_st; int datalen; + int id; + int ret; - etb_unlock(&tracer); - datalen = etb_getdatalen(&tracer); - etb_wa = etb_readl(&tracer, ETBR_WRITEADDR); - etb_ra = etb_readl(&tracer, ETBR_READADDR); - etb_st = etb_readl(&tracer, ETBR_STATUS); - etb_fc = etb_readl(&tracer, ETBR_FORMATTERCTRL); - etb_lock(&tracer); - - etm_unlock(&tracer); - etm_ctrl = etm_readl(&tracer, ETMR_CTRL); - etm_st = etm_readl(&tracer, ETMR_STATUS); - etm_lock(&tracer); + mutex_lock(&tracer.mutex); + if (tracer.etb_regs) { + etb_unlock(&tracer); + datalen = etb_getdatalen(&tracer); + etb_wa = etb_readl(&tracer, ETBR_WRITEADDR); + etb_ra = etb_readl(&tracer, ETBR_READADDR); + etb_st = etb_readl(&tracer, ETBR_STATUS); + etb_fc = etb_readl(&tracer, ETBR_FORMATTERCTRL); + etb_lock(&tracer); + } else { + etb_wa = etb_ra = etb_st = etb_fc = ~0; + datalen = -1; + } - return sprintf(buf, "Trace buffer len: %d\nComparator pairs: %d\n" + ret = sprintf(buf, "Trace buffer len: %d\nComparator pairs: %d\n" "ETBR_WRITEADDR:\t%08x\n" "ETBR_READADDR:\t%08x\n" "ETBR_STATUS:\t%08x\n" - "ETBR_FORMATTERCTRL:\t%08x\n" - "ETMR_CTRL:\t%08x\n" - "ETMR_STATUS:\t%08x\n", + "ETBR_FORMATTERCTRL:\t%08x\n", datalen, tracer.ncmppairs, etb_wa, etb_ra, etb_st, - etb_fc, + etb_fc + ); + + for (id = 0; id < tracer.etm_regs_count; id++) { + etm_unlock(&tracer, id); + etm_ctrl = etm_readl(&tracer, id, ETMR_CTRL); + etm_st = etm_readl(&tracer, id, ETMR_STATUS); + etm_lock(&tracer, id); + ret += sprintf(buf + ret, "ETMR_CTRL:\t%08x\n" + "ETMR_STATUS:\t%08x\n", etm_ctrl, etm_st ); + } + mutex_unlock(&tracer.mutex); + + return ret; } static struct kobj_attribute trace_info_attr = @@ -530,42 +626,121 @@ static ssize_t trace_mode_store(struct kobject *kobj, static struct kobj_attribute trace_mode_attr = __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store); +static ssize_t trace_range_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + return sprintf(buf, "%08lx %08lx\n", + tracer.range_start, tracer.range_end); +} + +static ssize_t trace_range_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long range_start, range_end; + + if (sscanf(buf, "%lx %lx", &range_start, &range_end) != 2) + return -EINVAL; + + mutex_lock(&tracer.mutex); + tracer.range_start = range_start; + tracer.range_end = range_end; + mutex_unlock(&tracer.mutex); + + return n; +} + + +static struct kobj_attribute trace_range_attr = + __ATTR(trace_range, 0644, trace_range_show, trace_range_store); + +static ssize_t trace_data_range_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long range_start; + u64 range_end; + mutex_lock(&tracer.mutex); + range_start = tracer.data_range_start; + range_end = tracer.data_range_end; + if (!range_end && (tracer.flags & TRACER_TRACE_DATA)) + range_end = 0x100000000ULL; + mutex_unlock(&tracer.mutex); + return sprintf(buf, "%08lx %08llx\n", range_start, range_end); +} + +static ssize_t trace_data_range_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long range_start; + u64 range_end; + + if (sscanf(buf, "%lx %llx", &range_start, &range_end) != 2) + return -EINVAL; + + mutex_lock(&tracer.mutex); + tracer.data_range_start = range_start; + tracer.data_range_end = (unsigned long)range_end; + if (range_end) + tracer.flags |= TRACER_TRACE_DATA; + else + tracer.flags &= ~TRACER_TRACE_DATA; + mutex_unlock(&tracer.mutex); + + return n; +} + + +static struct kobj_attribute trace_data_range_attr = + __ATTR(trace_data_range, 0644, + trace_data_range_show, trace_data_range_store); + static int __devinit etm_probe(struct amba_device *dev, const struct amba_id *id) { struct tracectx *t = &tracer; int ret = 0; + void __iomem **new_regs; + int new_count; - if (t->etm_regs) { - dev_dbg(&dev->dev, "ETM already initialized\n"); - ret = -EBUSY; + mutex_lock(&t->mutex); + new_count = t->etm_regs_count + 1; + new_regs = krealloc(t->etm_regs, + sizeof(t->etm_regs[0]) * new_count, GFP_KERNEL); + + if (!new_regs) { + dev_dbg(&dev->dev, "Failed to allocate ETM register array\n"); + ret = -ENOMEM; goto out; } + t->etm_regs = new_regs; ret = amba_request_regions(dev, NULL); if (ret) goto out; - t->etm_regs = ioremap_nocache(dev->res.start, resource_size(&dev->res)); - if (!t->etm_regs) { + t->etm_regs[t->etm_regs_count] = + ioremap_nocache(dev->res.start, resource_size(&dev->res)); + if (!t->etm_regs[t->etm_regs_count]) { ret = -ENOMEM; goto out_release; } - amba_set_drvdata(dev, t); + amba_set_drvdata(dev, t->etm_regs[t->etm_regs_count]); - mutex_init(&t->mutex); - t->dev = &dev->dev; - t->flags = TRACER_CYCLE_ACC; + t->flags = TRACER_CYCLE_ACC | TRACER_TRACE_DATA; t->etm_portsz = 1; - etm_unlock(t); - (void)etm_readl(t, ETMMR_PDSR); + etm_unlock(t, t->etm_regs_count); + (void)etm_readl(t, t->etm_regs_count, ETMMR_PDSR); /* dummy first read */ - (void)etm_readl(&tracer, ETMMR_OSSRR); + (void)etm_readl(&tracer, t->etm_regs_count, ETMMR_OSSRR); - t->ncmppairs = etm_readl(t, ETMR_CONFCODE) & 0xf; - etm_writel(t, 0x440, ETMR_CTRL); - etm_lock(t); + t->ncmppairs = etm_readl(t, t->etm_regs_count, ETMR_CONFCODE) & 0xf; + etm_writel(t, t->etm_regs_count, 0x441, ETMR_CTRL); + etm_writel(t, t->etm_regs_count, new_count, ETMR_TRACEIDR); + etm_lock(t, t->etm_regs_count); ret = sysfs_create_file(&dev->dev.kobj, &trace_running_attr.attr); @@ -581,36 +756,68 @@ static int __devinit etm_probe(struct amba_device *dev, const struct amba_id *id if (ret) dev_dbg(&dev->dev, "Failed to create trace_mode in sysfs\n"); - dev_dbg(t->dev, "ETM AMBA driver initialized.\n"); + ret = sysfs_create_file(&dev->dev.kobj, &trace_range_attr.attr); + if (ret) + dev_dbg(&dev->dev, "Failed to create trace_range in sysfs\n"); + + ret = sysfs_create_file(&dev->dev.kobj, &trace_data_range_attr.attr); + if (ret) + dev_dbg(&dev->dev, + "Failed to create trace_data_range in sysfs\n"); + + dev_dbg(&dev->dev, "ETM AMBA driver initialized.\n"); + + /* Enable formatter if there are multiple trace sources */ + if (new_count > 1) + t->etb_fc = ETBFF_ENFCONT | ETBFF_ENFTC; + + t->etm_regs_count = new_count; out: + mutex_unlock(&t->mutex); return ret; out_unmap: amba_set_drvdata(dev, NULL); - iounmap(t->etm_regs); + iounmap(t->etm_regs[t->etm_regs_count]); out_release: amba_release_regions(dev); + mutex_unlock(&t->mutex); return ret; } static int etm_remove(struct amba_device *dev) { - struct tracectx *t = amba_get_drvdata(dev); + int i; + struct tracectx *t = &tracer; + void __iomem *etm_regs = amba_get_drvdata(dev); + + sysfs_remove_file(&dev->dev.kobj, &trace_running_attr.attr); + sysfs_remove_file(&dev->dev.kobj, &trace_info_attr.attr); + sysfs_remove_file(&dev->dev.kobj, &trace_mode_attr.attr); + sysfs_remove_file(&dev->dev.kobj, &trace_range_attr.attr); + sysfs_remove_file(&dev->dev.kobj, &trace_data_range_attr.attr); amba_set_drvdata(dev, NULL); - iounmap(t->etm_regs); - t->etm_regs = NULL; + mutex_lock(&t->mutex); + for (i = 0; i < t->etm_regs_count; i++) + if (t->etm_regs[i] == etm_regs) + break; + for (; i < t->etm_regs_count - 1; i++) + t->etm_regs[i] = t->etm_regs[i + 1]; + t->etm_regs_count--; + if (!t->etm_regs_count) { + kfree(t->etm_regs); + t->etm_regs = NULL; + } + mutex_unlock(&t->mutex); + iounmap(etm_regs); amba_release_regions(dev); - sysfs_remove_file(&dev->dev.kobj, &trace_running_attr.attr); - sysfs_remove_file(&dev->dev.kobj, &trace_info_attr.attr); - sysfs_remove_file(&dev->dev.kobj, &trace_mode_attr.attr); - return 0; } @@ -619,6 +826,10 @@ static struct amba_id etm_ids[] = { .id = 0x0003b921, .mask = 0x0007ffff, }, + { + .id = 0x0003b950, + .mask = 0x0007ffff, + }, { 0, 0 }, }; @@ -636,6 +847,8 @@ static int __init etm_init(void) { int retval; + mutex_init(&tracer.mutex); + retval = amba_driver_register(&etb_driver); if (retval) { printk(KERN_ERR "Failed to register etb\n"); diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c index 0f107dc..136e837 100644 --- a/arch/arm/kernel/leds.c +++ b/arch/arm/kernel/leds.c @@ -9,6 +9,8 @@ */ #include <linux/module.h> #include <linux/init.h> +#include <linux/notifier.h> +#include <linux/cpu.h> #include <linux/sysdev.h> #include <linux/syscore_ops.h> @@ -101,6 +103,25 @@ static struct syscore_ops leds_syscore_ops = { .resume = leds_resume, }; +static int leds_idle_notifier(struct notifier_block *nb, unsigned long val, + void *data) +{ + switch (val) { + case IDLE_START: + leds_event(led_idle_start); + break; + case IDLE_END: + leds_event(led_idle_end); + break; + } + + return 0; +} + +static struct notifier_block leds_idle_nb = { + .notifier_call = leds_idle_notifier, +}; + static int __init leds_init(void) { int ret; @@ -109,8 +130,12 @@ static int __init leds_init(void) ret = sysdev_register(&leds_device); if (ret == 0) ret = sysdev_create_file(&leds_device, &attr_event); - if (ret == 0) + + if (ret == 0) { register_syscore_ops(&leds_syscore_ops); + idle_notifier_register(&leds_idle_nb); + } + return ret; } diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 74ae833..c132e81 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -30,9 +30,9 @@ #include <linux/uaccess.h> #include <linux/random.h> #include <linux/hw_breakpoint.h> +#include <linux/console.h> #include <asm/cacheflush.h> -#include <asm/leds.h> #include <asm/processor.h> #include <asm/system.h> #include <asm/thread_notify.h> @@ -62,6 +62,18 @@ static volatile int hlt_counter; #include <mach/system.h> +#ifdef CONFIG_SMP +void arch_trigger_all_cpu_backtrace(void) +{ + smp_send_all_cpu_backtrace(); +} +#else +void arch_trigger_all_cpu_backtrace(void) +{ + dump_stack(); +} +#endif + void disable_hlt(void) { hlt_counter++; @@ -91,8 +103,37 @@ static int __init hlt_setup(char *__unused) __setup("nohlt", nohlt_setup); __setup("hlt", hlt_setup); +#ifdef CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART +void arm_machine_flush_console(void) +{ + printk("\n"); + pr_emerg("Restarting %s\n", linux_banner); + if (console_trylock()) { + console_unlock(); + return; + } + + mdelay(50); + + local_irq_disable(); + if (!console_trylock()) + pr_emerg("arm_restart: Console was locked! Busting\n"); + else + pr_emerg("arm_restart: Console was locked!\n"); + console_unlock(); +} +#else +void arm_machine_flush_console(void) +{ +} +#endif + void arm_machine_restart(char mode, const char *cmd) { + /* Flush the console to make sure all the relevant messages make it + * out to the console drivers */ + arm_machine_flush_console(); + /* Disable interrupts first */ local_irq_disable(); local_fiq_disable(); @@ -182,8 +223,8 @@ void cpu_idle(void) /* endless idle loop with no priority at all */ while (1) { + idle_notifier_call_chain(IDLE_START); tick_nohz_stop_sched_tick(1); - leds_event(led_idle_start); while (!need_resched()) { #ifdef CONFIG_HOTPLUG_CPU if (cpu_is_offline(smp_processor_id())) @@ -210,8 +251,8 @@ void cpu_idle(void) local_irq_enable(); } } - leds_event(led_idle_end); tick_nohz_restart_sched_tick(); + idle_notifier_call_chain(IDLE_END); preempt_enable_no_resched(); schedule(); preempt_disable(); @@ -231,6 +272,15 @@ __setup("reboot=", reboot_setup); void machine_shutdown(void) { #ifdef CONFIG_SMP + /* + * Disable preemption so we're guaranteed to + * run to power off or reboot and prevent + * the possibility of switching to another + * thread that might wind up blocking on + * one of the stopped CPUs. + */ + preempt_disable(); + smp_send_stop(); #endif } @@ -254,6 +304,77 @@ void machine_restart(char *cmd) arm_pm_restart(reboot_mode, cmd); } +/* + * dump a block of kernel memory from around the given address + */ +static void show_data(unsigned long addr, int nbytes, const char *name) +{ + int i, j; + int nlines; + u32 *p; + + /* + * don't attempt to dump non-kernel addresses or + * values that are probably just small negative numbers + */ + if (addr < PAGE_OFFSET || addr > -256UL) + return; + + printk("\n%s: %#lx:\n", name, addr); + + /* + * round address down to a 32 bit boundary + * and always dump a multiple of 32 bytes + */ + p = (u32 *)(addr & ~(sizeof(u32) - 1)); + nbytes += (addr & (sizeof(u32) - 1)); + nlines = (nbytes + 31) / 32; + + + for (i = 0; i < nlines; i++) { + /* + * just display low 16 bits of address to keep + * each line of the dump < 80 characters + */ + printk("%04lx ", (unsigned long)p & 0xffff); + for (j = 0; j < 8; j++) { + u32 data; + if (probe_kernel_address(p, data)) { + printk(" ********"); + } else { + printk(" %08x", data); + } + ++p; + } + printk("\n"); + } +} + +static void show_extra_register_data(struct pt_regs *regs, int nbytes) +{ + mm_segment_t fs; + + fs = get_fs(); + set_fs(KERNEL_DS); + show_data(regs->ARM_pc - nbytes, nbytes * 2, "PC"); + show_data(regs->ARM_lr - nbytes, nbytes * 2, "LR"); + show_data(regs->ARM_sp - nbytes, nbytes * 2, "SP"); + show_data(regs->ARM_ip - nbytes, nbytes * 2, "IP"); + show_data(regs->ARM_fp - nbytes, nbytes * 2, "FP"); + show_data(regs->ARM_r0 - nbytes, nbytes * 2, "R0"); + show_data(regs->ARM_r1 - nbytes, nbytes * 2, "R1"); + show_data(regs->ARM_r2 - nbytes, nbytes * 2, "R2"); + show_data(regs->ARM_r3 - nbytes, nbytes * 2, "R3"); + show_data(regs->ARM_r4 - nbytes, nbytes * 2, "R4"); + show_data(regs->ARM_r5 - nbytes, nbytes * 2, "R5"); + show_data(regs->ARM_r6 - nbytes, nbytes * 2, "R6"); + show_data(regs->ARM_r7 - nbytes, nbytes * 2, "R7"); + show_data(regs->ARM_r8 - nbytes, nbytes * 2, "R8"); + show_data(regs->ARM_r9 - nbytes, nbytes * 2, "R9"); + show_data(regs->ARM_r10 - nbytes, nbytes * 2, "R10"); + set_fs(fs); +} + void __show_regs(struct pt_regs *regs) { unsigned long flags; @@ -313,6 +434,8 @@ void __show_regs(struct pt_regs *regs) printk("Control: %08x%s\n", ctrl, buf); } #endif + + show_extra_register_data(regs, 128); } void show_regs(struct pt_regs * regs) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 4469924..84953bb 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -53,6 +53,7 @@ enum ipi_msg_type { IPI_CALL_FUNC, IPI_CALL_FUNC_SINGLE, IPI_CPU_STOP, + IPI_CPU_BACKTRACE, }; int __cpuinit __cpu_up(unsigned int cpu) @@ -301,17 +302,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void) */ platform_secondary_init(cpu); - /* - * Enable local interrupts. - */ notify_cpu_starting(cpu); - local_irq_enable(); - local_fiq_enable(); - - /* - * Setup the percpu timer for this CPU. - */ - percpu_timer_setup(); calibrate_delay(); @@ -323,10 +314,23 @@ asmlinkage void __cpuinit secondary_start_kernel(void) * before we continue. */ set_cpu_online(cpu, true); + + /* + * Setup the percpu timer for this CPU. + */ + percpu_timer_setup(); + while (!cpu_active(cpu)) cpu_relax(); /* + * cpu_active bit is set, so it's safe to enable interrupts + * now. + */ + local_irq_enable(); + local_fiq_enable(); + + /* * OK, it's off to the idle thread for us */ cpu_idle(); @@ -405,6 +409,7 @@ static const char *ipi_types[NR_IPI] = { S(IPI_CALL_FUNC, "Function call interrupts"), S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), S(IPI_CPU_STOP, "CPU stop interrupts"), + S(IPI_CPU_BACKTRACE, "CPU backtrace"), }; void show_ipi_list(struct seq_file *p, int prec) @@ -555,6 +560,58 @@ static void ipi_cpu_stop(unsigned int cpu) cpu_relax(); } +static cpumask_t backtrace_mask; +static DEFINE_RAW_SPINLOCK(backtrace_lock); + +/* "in progress" flag of arch_trigger_all_cpu_backtrace */ +static unsigned long backtrace_flag; + +void smp_send_all_cpu_backtrace(void) +{ + unsigned int this_cpu = smp_processor_id(); + int i; + + if (test_and_set_bit(0, &backtrace_flag)) + /* + * If there is already a trigger_all_cpu_backtrace() in progress + * (backtrace_flag == 1), don't output double cpu dump infos. + */ + return; + + cpumask_copy(&backtrace_mask, cpu_online_mask); + cpu_clear(this_cpu, backtrace_mask); + + pr_info("Backtrace for cpu %d (current):\n", this_cpu); + dump_stack(); + + pr_info("\nsending IPI to all other CPUs:\n"); + smp_cross_call(&backtrace_mask, IPI_CPU_BACKTRACE); + + /* Wait for up to 10 seconds for all other CPUs to do the backtrace */ + for (i = 0; i < 10 * 1000; i++) { + if (cpumask_empty(&backtrace_mask)) + break; + mdelay(1); + } + + clear_bit(0, &backtrace_flag); + smp_mb__after_clear_bit(); +} + +/* + * ipi_cpu_backtrace - handle IPI from smp_send_all_cpu_backtrace() + */ +static void ipi_cpu_backtrace(unsigned int cpu, struct pt_regs *regs) +{ + if (cpu_isset(cpu, backtrace_mask)) { + raw_spin_lock(&backtrace_lock); + pr_warning("IPI backtrace for cpu %d\n", cpu); + show_regs(regs); + raw_spin_unlock(&backtrace_lock); + cpu_clear(cpu, backtrace_mask); + } +} + /* * Main handler for inter-processor interrupts */ @@ -568,31 +625,35 @@ asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) switch (ipinr) { case IPI_TIMER: - irq_enter(); + irq_enter(); ipi_timer(); - irq_exit(); - break; + irq_exit(); + break; case IPI_RESCHEDULE: scheduler_ipi(); break; case IPI_CALL_FUNC: - irq_enter(); + irq_enter(); generic_smp_call_function_interrupt(); - irq_exit(); + irq_exit(); break; case IPI_CALL_FUNC_SINGLE: - irq_enter(); + irq_enter(); generic_smp_call_function_single_interrupt(); - irq_exit(); + irq_exit(); break; case IPI_CPU_STOP: - irq_enter(); + irq_enter(); ipi_cpu_stop(cpu); - irq_exit(); + irq_exit(); + break; + + case IPI_CPU_BACKTRACE: + ipi_cpu_backtrace(cpu, regs); break; default: diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 37b5a97..26672b0 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -18,13 +18,24 @@ config CPU_S5PV210 help Enable S5PV210 CPU support +config CPU_DIDLE + bool "Enable DEEP IDLE support for S5PV210 CPU" + depends on CPU_IDLE + default n + help + Enable DEEP IDLE support for S5PV210 CPU. + config S5PV210_SETUP_I2C1 bool + default y + select HAVE_S3C2410_I2C help Common setup code for i2c bus 1. config S5PV210_SETUP_I2C2 bool + default y + select HAVE_S3C2410_I2C help Common setup code for i2c bus 2. @@ -59,6 +70,39 @@ config S5PV210_SETUP_FIMC help Common setup code for the camera interfaces. +config S5PV210_POWER_DOMAIN + bool + depends on REGULATOR + default y + help + Enable S5PV210 power domain support. + +config S5PV210_CORESIGHT + bool "Coresight" + select OC_ETM + default y + help + Support embedded trace cell + +comment "MMC/SD slot setup" +depends on PLAT_S5P + +menu "Use 8-bit bus width" +config S5PV210_SD_CH0_8BIT +bool "Channel 0" +depends on PLAT_S5P +default n +help +IF channel 0 uses 8-bit bus, channel 1 is disabled. + +config S5PV210_SD_CH2_8BIT +bool "Channel 2" +depends on PLAT_S5P +default n +help +IF channel 2 uses 8-bit bus, channel 3 is disabled. +endmenu + menu "S5PC110 Machines" config MACH_AQUILA @@ -108,6 +152,7 @@ config MACH_SMDKC110 select S3C_DEV_I2C1 select S3C_DEV_I2C2 select S3C_DEV_RTC + select HAVE_S3C_RTC select S3C_DEV_WDT select SAMSUNG_DEV_IDE select S5PV210_SETUP_I2C1 @@ -172,4 +217,63 @@ config S5PV210_PM help Power Management code common to S5PV210 +config MACH_HERRING + bool "Herring" + select CPU_S5PV210 + select S3C_DEV_WDT + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S5P_DEV_ONENAND + select HAVE_PWM + select SAMSUNG_DEV_PWM + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 if !S5PV210_SD_CH0_8BIT + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 if !S5PV210_SD_CH2_8BIT + select S5PV210_SETUP_SDHCI + select S5PV210_POWER_DOMAIN + select S5P_DEV_CSIS0 + select S5P_SETUP_MIPIPHY + help + Machine support for Herring + +config S5PV210_SETUP_FB + bool + depends on FB_S3C + default y + help + Common setup code for FIMD controller. + +config S5P_ADC + bool "S5PXXXX ADC driver" + depends on PLAT_S5P + default y + help + ADC ( A/D Conversion ) driver for Samsung S5PXXXX + +config S5PV210_SETUP_FIMC0 + bool + depends on VIDEO_FIMC || CPU_FREQ + default y + help + Common setup code for FIMC controller 0. + +config S5PV210_SETUP_FIMC1 + bool + depends on VIDEO_FIMC || CPU_FREQ + default y + help + Common setup code for FIMC controller 1. + +config S5PV210_SETUP_FIMC2 + bool + depends on VIDEO_FIMC || CPU_FREQ + default y + help + Common setup code for FIMC controller 2. + +config WIFI_CONTROL_FUNC + bool "Enable WiFi control function abstraction" + help + Enables Power/Reset/Carddetect function abstraction endif diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 50907ac..1c79fc9 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -1,7 +1,7 @@ # arch/arm/mach-s5pv210/Makefile # # Copyright (c) 2010 Samsung Electronics Co., Ltd. -# http://www.samsung.com/ +# http://www.samsung.com/ # # Licensed under GPLv2 @@ -17,6 +17,9 @@ obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o +obj-$(CONFIG_S5PV210_POWER_DOMAIN) += power-domain.o +obj-$(CONFIG_S5PV210_CORESIGHT) += coresight.o + # machine support obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o @@ -24,13 +27,25 @@ obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o obj-$(CONFIG_MACH_GONI) += mach-goni.o obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o +obj-$(CONFIG_MACH_HERRING) += mach-herring.o herring-rfkill.o +obj-$(CONFIG_MACH_HERRING) += herring-vibrator.o +obj-$(CONFIG_MACH_HERRING) += herring-btlpm.o +obj-$(CONFIG_MACH_HERRING) += herring-watchdog.o +obj-$(CONFIG_MACH_HERRING) += herring-panel.o +obj-$(CONFIG_MACH_HERRING) += herring-touchkey-led.o + +obj-$(CONFIG_MACH_HERRING) += dev-herring-phone.o # device support obj-y += dev-audio.o +obj-y += dev-fiqdbg.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o -obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o + +obj-$(CONFIG_S5P_ADC) += adc.o + +obj-$(CONFIG_S5PV210_SETUP_FB) += setup-fb.o obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o @@ -38,3 +53,10 @@ obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o +obj-$(CONFIG_S5PV210_SETUP_FIMC0) += setup-fimc0.o +obj-$(CONFIG_S5PV210_SETUP_FIMC1) += setup-fimc1.o +obj-$(CONFIG_S5PV210_SETUP_FIMC2) += setup-fimc2.o + +obj-$(CONFIG_CPU_IDLE) += cpuidle.o +obj-$(CONFIG_CPU_FREQ) += dev-cpufreq.o +obj-$(CONFIG_CPU_DIDLE) += didle.o diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot index ff90aa1..58ed679 100644 --- a/arch/arm/mach-s5pv210/Makefile.boot +++ b/arch/arm/mach-s5pv210/Makefile.boot @@ -1,2 +1,6 @@ - zreladdr-y := 0x20008000 +zreladdr-y := 0x20008000 params_phys-y := 0x20000100 + +# override for Herring +zreladdr-$(CONFIG_MACH_HERRING) := 0x30008000 +params_phys-$(CONFIG_MACH_HERRING) := 0x30000100 diff --git a/arch/arm/mach-s5pv210/adc.c b/arch/arm/mach-s5pv210/adc.c new file mode 100644 index 0000000..d7945fb --- /dev/null +++ b/arch/arm/mach-s5pv210/adc.c @@ -0,0 +1,401 @@ +/* linux/arch/arm/mach-s5pv210/adc.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> + * iPAQ H1940 touchscreen support + * + * ChangeLog + * + * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at> + * - added clock (de-)allocation code + * + * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org> + * - h1940_ -> s3c24xx (this driver is now also used on the n30 + * machines :P) + * - Debug messages are now enabled with the config option + * TOUCHSCREEN_S3C_DEBUG + * - Changed the way the value are read + * - Input subsystem should now work + * - Use ioremap and readl/writel + * + * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org> + * - Make use of some undocumented features of the touchscreen + * controller + * + */ + + +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/input.h> +#include <linux/init.h> +#include <linux/serio.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/miscdevice.h> +#include <linux/clk.h> +#include <linux/mutex.h> +#include <linux/io.h> +#include <linux/uaccess.h> + +#include <asm/irq.h> +#include <mach/hardware.h> +#include <linux/uaccess.h> + +#include <mach/regs-adc.h> +#include <mach/adc.h> +#include <mach/irqs.h> + +#define ADC_MINOR 131 +#define ADC_INPUT_PIN _IOW('S', 0x0c, unsigned long) + +#define ADC_WITH_TOUCHSCREEN + +static struct clk *adc_clock; + +static void __iomem *base_addr; +static int adc_port; +struct s3c_adc_mach_info *plat_data; + +#ifdef ADC_WITH_TOUCHSCREEN +static DEFINE_MUTEX(adc_mutex); + +static unsigned long data_for_ADCCON; +static unsigned long data_for_ADCTSC; + +static void s3c_adc_save_SFR_on_ADC(void) +{ + data_for_ADCCON = readl(base_addr + S3C_ADCCON); + data_for_ADCTSC = readl(base_addr + S3C_ADCTSC); +} + +static void s3c_adc_restore_SFR_on_ADC(void) +{ + writel(data_for_ADCCON, base_addr + S3C_ADCCON); + writel(data_for_ADCTSC, base_addr + S3C_ADCTSC); +} +#else +static struct resource *adc_mem; +#endif + +static int s3c_adc_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static unsigned int s3c_adc_convert(void) +{ + unsigned int adc_return = 0; + unsigned long data0; + unsigned long data1; + + writel((readl(base_addr + S3C_ADCCON) | S3C_ADCCON_PRSCEN) & ~S3C_ADCCON_STDBM, + base_addr + S3C_ADCCON); + + writel((adc_port & 0xF), base_addr + S3C_ADCMUX); + + udelay(10); + + writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_ENABLE_START, + base_addr + S3C_ADCCON); + + do { + data0 = readl(base_addr + S3C_ADCCON); + } while (!(data0 & S3C_ADCCON_ECFLG)); + + data1 = readl(base_addr + S3C_ADCDAT0); + + writel((readl(base_addr + S3C_ADCCON) | S3C_ADCCON_STDBM) & ~S3C_ADCCON_PRSCEN, + base_addr + S3C_ADCCON); + + if (plat_data->resolution == 12) + adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT; + else + adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK; + + return adc_return; +} + + +int s3c_adc_get_adc_data(int channel) +{ + int adc_value = 0; + int cur_adc_port = 0; + +#ifdef ADC_WITH_TOUCHSCREEN + mutex_lock(&adc_mutex); + s3c_adc_save_SFR_on_ADC(); +#else + mutex_lock(&adc_mutex); +#endif + + cur_adc_port = adc_port; + adc_port = channel; + + adc_value = s3c_adc_convert(); + + adc_port = cur_adc_port; + +#ifdef ADC_WITH_TOUCHSCREEN + s3c_adc_restore_SFR_on_ADC(); + mutex_unlock(&adc_mutex); +#else + mutex_unlock(&adc_mutex); +#endif + + pr_debug("%s : Converted Value: %03d\n", __func__, adc_value); + + return adc_value; +} +EXPORT_SYMBOL(s3c_adc_get_adc_data); + +int s3c_adc_get(struct s3c_adc_request *req) +{ + unsigned adc_channel = req->channel; + int adc_value_ret = 0; + + adc_value_ret = s3c_adc_convert(); + + req->callback(adc_channel, req->param, adc_value_ret); + + return 0; +} +EXPORT_SYMBOL(s3c_adc_get); + +static ssize_t +s3c_adc_read(struct file *file, char __user *buffer, + size_t size, loff_t *pos) +{ + int adc_value = 0; + +#ifdef ADC_WITH_TOUCHSCREEN + mutex_lock(&adc_mutex); + s3c_adc_save_SFR_on_ADC(); +#endif + printk(KERN_INFO "## delay: %d\n", readl(base_addr + S3C_ADCDLY)); + adc_value = s3c_adc_convert(); + +#ifdef ADC_WITH_TOUCHSCREEN + s3c_adc_restore_SFR_on_ADC(); + mutex_unlock(&adc_mutex); +#endif + + if (copy_to_user(buffer, &adc_value, sizeof(unsigned int))) + return -EFAULT; + + return sizeof(unsigned int); +} + + +static long s3c_adc_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + + switch (cmd) { + case ADC_INPUT_PIN: + adc_port = (unsigned int) arg; + + if (adc_port >= 4) + printk(KERN_WARNING + " %d is already reserved for TouchScreen\n", + adc_port); + return 0; + + default: + return -ENOIOCTLCMD; + } +} + +static const struct file_operations s3c_adc_fops = { + .owner = THIS_MODULE, + .read = s3c_adc_read, + .open = s3c_adc_open, + .unlocked_ioctl = s3c_adc_ioctl, +}; + +static struct miscdevice s3c_adc_miscdev = { + .minor = ADC_MINOR, + .name = "adc", + .fops = &s3c_adc_fops, +}; + +static struct s3c_adc_mach_info *s3c_adc_get_platdata(struct device *dev) +{ + if (dev->platform_data != NULL) + return (struct s3c_adc_mach_info *) dev->platform_data; + else + return 0; +} + +/* + * The functions for inserting/removing us as a module. + */ + +static int __devinit s3c_adc_probe(struct platform_device *pdev) +{ + struct resource *res; + struct device *dev; + int ret; + int size; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dev = &pdev->dev; + + if (res == NULL) { + dev_err(dev, "no memory resource specified\n"); + return -ENOENT; + } + + size = (res->end - res->start) + 1; + +#if !defined(ADC_WITH_TOUCHSCREEN) + adc_mem = request_mem_region(res->start, size, pdev->name); + if (adc_mem == NULL) { + dev_err(dev, "failed to get memory region\n"); + ret = -ENOENT; + goto err_req; + } +#endif + + base_addr = ioremap(res->start, size); + if (base_addr == NULL) { + dev_err(dev, "fail to ioremap() region\n"); + ret = -ENOENT; + goto err_map; + } + + adc_clock = clk_get(&pdev->dev, "adc"); + + if (IS_ERR(adc_clock)) { + dev_err(dev, "failed to fine ADC clock source\n"); + ret = PTR_ERR(adc_clock); + goto err_clk; + } + + clk_enable(adc_clock); + + /* read platform data from device struct */ + plat_data = s3c_adc_get_platdata(&pdev->dev); + + if ((plat_data->presc & 0xff) > 0) + writel(S3C_ADCCON_PRSCEN | + S3C_ADCCON_PRSCVL(plat_data->presc & 0xff), + base_addr + S3C_ADCCON); + else + writel(0, base_addr + S3C_ADCCON); + + /* Initialise registers */ + if ((plat_data->delay & 0xffff) > 0) + writel(plat_data->delay & 0xffff, base_addr + S3C_ADCDLY); + + if (plat_data->resolution == 12) + writel(readl(base_addr + S3C_ADCCON) | + S3C_ADCCON_RESSEL_12BIT, base_addr + S3C_ADCCON); + + writel((readl(base_addr + S3C_ADCCON) | S3C_ADCCON_STDBM) & ~S3C_ADCCON_PRSCEN, + base_addr + S3C_ADCCON); + + ret = misc_register(&s3c_adc_miscdev); + if (ret) { + printk(KERN_ERR "cannot register miscdev on minor=%d (%d)\n", + ADC_MINOR, ret); + goto err_clk; + } + + return 0; + +err_clk: + clk_disable(adc_clock); + clk_put(adc_clock); + +err_map: + iounmap(base_addr); + +#if !defined(ADC_WITH_TOUCHSCREEN) +err_req: + release_resource(adc_mem); + kfree(adc_mem); +#endif + + return ret; +} + + +static int s3c_adc_remove(struct platform_device *dev) +{ + clk_disable(adc_clock); + clk_put(adc_clock); + return 0; +} + +#ifdef CONFIG_PM +static unsigned int adccon, adctsc, adcdly; + +static int s3c_adc_suspend(struct platform_device *dev, pm_message_t state) +{ + adccon = readl(base_addr + S3C_ADCCON); + adctsc = readl(base_addr + S3C_ADCTSC); + adcdly = readl(base_addr + S3C_ADCDLY); + + return 0; +} + +static int s3c_adc_resume(struct platform_device *pdev) +{ + writel(adccon, base_addr + S3C_ADCCON); + writel(adctsc, base_addr + S3C_ADCTSC); + writel(adcdly, base_addr + S3C_ADCDLY); + + return 0; +} +#else +#define s3c_adc_suspend NULL +#define s3c_adc_resume NULL +#endif + +static struct platform_driver s3c_adc_driver = { + .probe = s3c_adc_probe, + .remove = s3c_adc_remove, + .suspend = s3c_adc_suspend, + .resume = s3c_adc_resume, + .driver = { + .owner = THIS_MODULE, + .name = "s3c-adc", + }, +}; + +static char banner[] __initdata = KERN_INFO \ + "S5PV210 ADC driver, (c) 2010 Samsung Electronics\n"; + +int __init s3c_adc_init(void) +{ + printk(banner); + return platform_driver_register(&s3c_adc_driver); +} + +void __exit s3c_adc_exit(void) +{ + platform_driver_unregister(&s3c_adc_driver); +} + +module_init(s3c_adc_init); +module_exit(s3c_adc_exit); + +MODULE_AUTHOR("dsfine.ha@samsung.com"); +MODULE_DESCRIPTION("S5PV210 ADC driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 2d59949..6d3e609 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -19,6 +19,8 @@ #include <linux/clk.h> #include <linux/sysdev.h> #include <linux/io.h> +#include <linux/device.h> +#include <linux/platform_device.h> #include <mach/map.h> @@ -30,9 +32,13 @@ #include <plat/s5p-clock.h> #include <plat/clock-clksrc.h> #include <plat/s5pv210.h> +#include <plat/devs.h> +#include <mach/regs-audss.h> static unsigned long xtal; +static int s5pv210_usbosc_enable(struct clk *clk, int enable); + static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", @@ -175,6 +181,16 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); } +static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable); +} + +static int s5pv210_clk_ip5_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP5, clk, enable); +} + static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); @@ -185,6 +201,11 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); } +static int s5pv210_clk_audss_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable); +} + static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .id = -1, @@ -206,6 +227,21 @@ static struct clk clk_sclk_usbphy1 = { .id = -1, }; +static struct clk clk_i2scdclk0 = { + .name = "i2scdclk", + .id = 0, +}; + +static struct clk clk_i2scdclk1 = { + .name = "i2scdclk", + .id = 1, +}; + +static struct clk clk_i2scdclk2 = { + .name = "i2scdclk", + .id = 2, +}; + static struct clk clk_pcmcdclk0 = { .name = "pcmcdclk", .id = -1, @@ -311,18 +347,6 @@ static struct clk_ops clk_fout_apll_ops = { static struct clk init_clocks_off[] = { { - .name = "pdma", - .id = 0, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "pdma", - .id = 1, - .parent = &clk_hclk_psys.clk, - .enable = s5pv210_clk_ip0_ctrl, - .ctrlbit = (1 << 4), - }, { .name = "rot", .id = -1, .parent = &clk_hclk_dsys.clk, @@ -359,11 +383,30 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<17), }, { - .name = "lcd", + .name = "jpeg", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip5_ctrl, + .ctrlbit = S5P_CLKGATE_IP5_JPEG, + }, { + .name = "mfc", + .id = -1, + .parent = &clk_hclk_msys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<16), + }, { + .name = "dsim", .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip1_ctrl, - .ctrlbit = (1<<0), + .ctrlbit = (1<<2), + }, { + .name = "onenand", + .id = -1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 24), + .dev = &s5p_device_onenand.dev, }, { .name = "cfcon", .id = 0, @@ -401,12 +444,6 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<16), }, { - .name = "watchdog", - .id = -1, - .parent = &clk_pclk_psys.clk, - .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1<<22), - }, { .name = "rtc", .id = -1, .parent = &clk_pclk_psys.clk, @@ -490,11 +527,117 @@ static struct clk init_clocks_off[] = { .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 0), + }, { + .name = "pcm", + .id = 2, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_PCM2, + }, { +#if 0 + .name = "pcm", + .id = 1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_PCM1 | S5P_CLKGATE_IP3_I2S1 , + }, { + .name = "pcm", + .id = 0, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_PCM0, + }, { +#endif + .name = "i2c-hdmiphy", + .id = -1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "hdmi", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "tvenc", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "mixer", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "vp", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "usb_osc", + .id = -1, + .enable = s5pv210_usbosc_enable, + .ctrlbit = (1 << 1), + }, { + .name = "secss", + .id = -1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "seckey", + .id = -1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip4_ctrl, + .ctrlbit = (1 << 3), }, }; +static struct clk init_dmaclocks[] = { + { + .name = "pdma", + .id = 0, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<2), + .dev = &s5pv210_device_mdma.dev, + }, { + .name = "pdma", + .id = 1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<3), + .dev = &s5pv210_device_pdma0.dev, + }, { + .name = "pdma", + .id = 2, + .parent = &init_dmaclocks[1], + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1<<4), + .dev = &s5pv210_device_pdma1.dev, + }, +}; + +static int s5pc11x_clk_out_set_rate(struct clk *clk, unsigned long rate); +static int s5pc11x_clk_out_set_parent(struct clk *clk, struct clk *parent); + +static struct clk_ops s5pc11x_clkout_ops = { + .set_parent = s5pc11x_clk_out_set_parent, + .set_rate = s5pc11x_clk_out_set_rate, +}; + static struct clk init_clocks[] = { { + .name = "watchdog", + .id = -1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1<<22), + }, { .name = "hclk_imem", .id = -1, .parent = &clk_hclk_msys.clk, @@ -502,6 +645,12 @@ static struct clk init_clocks[] = { .enable = s5pv210_clk_ip0_ctrl, .ops = &clk_hclk_imem_ops, }, { + .name = "lcd", + .id = -1, + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1<<0), + }, { .name = "uart", .id = 0, .parent = &clk_pclk_psys.clk, @@ -531,6 +680,21 @@ static struct clk init_clocks[] = { .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1 << 26), + }, { +#if 1 + .name = "i2s_v50", + .id = 0, + .parent = &clk_p, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = S5P_CLKGATE_IP3_I2S0 | S5P_CLKGATE_IP3_PCM0, + }, { +#endif + .name = "clk_out", + .id = -1, + .ops = &s5pc11x_clkout_ops, + }, { + .name = "apb_pclk", + .id = -1, }, }; @@ -627,6 +791,54 @@ static struct clksrc_sources clkset_sclk_mixer = { .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), }; +static int s5pc11x_clk_out_set_rate(struct clk *clk, unsigned long rate) +{ + u32 val = 0, div = 0, rate_div = 1; + int err = -EINVAL; + + if (rate && clk->parent) { + if (clk->parent == &clk_fout_apll) + rate_div = 4; + if (clk->parent == &clk_fout_mpll) + rate_div = 2; + + div = clk_get_rate(clk->parent) / rate / rate_div; + val = __raw_readl(S5P_CLK_OUT); + val &= (~(0xF << 20)); + val |= (div - 1) << 20; + __raw_writel(val, S5P_CLK_OUT); + err = 0; + } + return err; +} + +static int s5pc11x_clk_out_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val = 0; + int err = 0; + clk->parent = parent; + val = __raw_readl(S5P_CLK_OUT); + + if (parent == &clk_fout_apll) { + val = val & (~(0x1F << 12)); + val |= (0x0 << 12); + } else if (parent == &clk_fout_mpll) { + val = val & (~(0x1F << 12)); + val |= (0x1 << 12); + } else if (parent == &clk_fout_epll) { + val = val & (~(0x1F << 12)); + val |= (0x2 << 12); + } else if (parent == &clk_sclk_vpll.clk) { + val = val & (~(0x1F << 12)); + val |= (0x3 << 12); + } else { + err = -EINVAL; + } + + __raw_writel(val, S5P_CLK_OUT); + return err; +} + static struct clk *clkset_sclk_audio0_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_pcmcdclk0, @@ -656,6 +868,59 @@ static struct clksrc_clk clk_sclk_audio0 = { .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, }; +static struct clk *clkset_mout_audss_list[] = { + &clk_ext_xtal_mux, + &clk_fout_epll, +}; + +static struct clksrc_sources clkset_mout_audss = { + .sources = clkset_mout_audss_list, + .nr_sources = ARRAY_SIZE(clkset_mout_audss_list), +}; + +static struct clksrc_clk clk_mout_audss = { + .clk = { + .name = "mout_audss", + .id = -1, + }, + .sources = &clkset_mout_audss, + .reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 0, .size = 1 }, +}; + +static struct clk *clkset_mout_i2s_a_list[] = { + &clk_mout_audss.clk, + &clk_pcmcdclk0, + &clk_sclk_audio0.clk, +}; + +static struct clksrc_sources clkset_mout_i2s_a = { + .sources = clkset_mout_i2s_a_list, + .nr_sources = ARRAY_SIZE(clkset_mout_i2s_a_list), +}; + +static struct clksrc_clk clk_mout_i2s_a = { + .clk = { + .name = "audio-bus", + .id = 0, + .enable = s5pv210_clk_audss_ctrl, + .ctrlbit = (1 << 6), + }, + .sources = &clkset_mout_i2s_a, + .reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 2, .size = 2 }, + .reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_dout_audio_bus_clk_i2s = { + .clk = { + .name = "dout_audio_bus_clk_i2s", + .id = -1, + .parent = &clk_mout_audss.clk, + .enable = s5pv210_clk_audss_ctrl, + .ctrlbit = (1 << 5), + }, + .reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 0, .size = 4 }, +}; + static struct clk *clkset_sclk_audio1_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_pcmcdclk1, @@ -808,40 +1073,44 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 0, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 12), + .dev = &s3c24xx_uart_device0.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 13), + .dev = &s3c24xx_uart_device1.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 2, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 14), + .dev = &s3c24xx_uart_device2.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, }, { .clk = { - .name = "uclk1", + .name = "sclk", .id = 3, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 15), + .dev = &s3c24xx_uart_device3.dev, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, @@ -909,8 +1178,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimd", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 5), + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 0), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, @@ -967,7 +1236,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, }, { .clk = { - .name = "sclk_g2d", + .name = "sclk_fimg2d", .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 12), @@ -977,10 +1246,11 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, }, { .clk = { - .name = "sclk_g3d", + .name = "sclk", .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 8), + .dev = &s3c_device_g3d.dev, }, .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, @@ -1035,7 +1305,41 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_mdnie", + .id = -1, + .enable = s5pv210_clk_mask1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, + .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_mdnie_pwm", + .id = -1, + .enable = s5pv210_clk_mask1_ctrl, + .ctrlbit = (1 << 1), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 4, + .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, + }, +}; + +/* MOUT CSIS */ +static struct clksrc_clk clk_mout_csis = { + .clk = { + .name = "mout_csis", + .id = -1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 6), }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, }; /* Clock initialisation code */ @@ -1058,12 +1362,29 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_hdmi, &clk_mout_dmc0, &clk_sclk_dmc0, + &clk_mout_csis, &clk_sclk_audio0, &clk_sclk_audio1, &clk_sclk_audio2, &clk_sclk_spdif, + &clk_mout_audss, + &clk_mout_i2s_a, + &clk_dout_audio_bus_clk_i2s, }; +static int s5pv210_usbosc_enable(struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + unsigned int usbosc_con = __raw_readl(S5P_SLEEP_CFG) & ~ctrlbit; + + if (enable) + usbosc_con |= ctrlbit; + + writel(usbosc_con, S5P_SLEEP_CFG); + + return 0; +} + static u32 epll_div[][6] = { { 48000000, 0, 48, 3, 3, 0 }, { 96000000, 0, 48, 3, 2, 0 }, @@ -1157,6 +1478,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) unsigned long vpll; unsigned int ptr; u32 clkdiv0, clkdiv1; + struct clksrc_clk *pclkSrc; /* Set functions for clk_fout_epll */ clk_fout_epll.enable = s5p_epll_enable; @@ -1210,8 +1532,38 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) clk_h.rate = hclk_psys; clk_p.rate = pclk_psys; - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_set_clksrc(&clksrcs[ptr], true); + /*Assign clock source and rates for IP's*/ + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) { + pclkSrc = &clksrcs[ptr]; + if (!strcmp(pclkSrc->clk.name, "sclk_mdnie")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + clk_set_rate(&pclkSrc->clk, 167*MHZ); + } else if (!strcmp(pclkSrc->clk.name, "sclk_mmc")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + + if (pclkSrc->clk.id == 0) + clk_set_rate(&pclkSrc->clk, 52*MHZ); + else + clk_set_rate(&pclkSrc->clk, 50*MHZ); + } else if (!strcmp(pclkSrc->clk.name, "sclk_spi")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_epll.clk); + } else if (!strcmp(pclkSrc->clk.name, "sclk_cam") && + (pclkSrc->clk.id == 0)) { + clk_set_parent(&pclkSrc->clk, &clk_xusbxti); + } else if (!strcmp(pclkSrc->clk.name, "sclk_g2d")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + clk_set_rate(&pclkSrc->clk, 250*MHZ); + } else if (!strcmp(pclkSrc->clk.name, "sclk")) { + clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); + + if (pclkSrc->clk.id == 0) + clk_set_rate(&pclkSrc->clk, 133400000); + else + clk_set_rate(&pclkSrc->clk, 66700000); + } + /* Display the clock source */ + s3c_set_clksrc(pclkSrc, true); + } } static struct clk *clks[] __initdata = { @@ -1219,6 +1571,9 @@ static struct clk *clks[] __initdata = { &clk_sclk_hdmiphy, &clk_sclk_usbphy0, &clk_sclk_usbphy1, + &clk_i2scdclk0, + &clk_i2scdclk1, + &clk_i2scdclk2, &clk_pcmcdclk0, &clk_pcmcdclk1, &clk_pcmcdclk2, @@ -1239,5 +1594,9 @@ void __init s5pv210_register_clocks(void) s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + /* Register DMA Clock */ + s3c_register_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks)); + s3c_disable_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks)); + s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pv210/coresight.c b/arch/arm/mach-s5pv210/coresight.c new file mode 100755 index 0000000..b8c29c7 --- /dev/null +++ b/arch/arm/mach-s5pv210/coresight.c @@ -0,0 +1,163 @@ +/* coresight.c + * + * Copyright (C) 2011 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm/hardware/coresight.h> +#include <linux/amba/bus.h> +#include <linux/io.h> +#include <plat/pm.h> + +#define CS_ETB_BASE (0xE0D00000 + 0x1000) +#define CS_FUNNEL_BASE (0xE0D00000 + 0x4000) +#define CS_ETM_BASE (0xE0D00000 + 0x6000) +#define TZPC3_BASE (0xE1C00000) + +static void __iomem *cs_etb_regs; +static void __iomem *cs_funnel_regs; +static void __iomem *cs_etm_regs; +static void __iomem *tzpc3_regs; + +static void cs_unlock(void *regs) +{ + writel(UNLOCK_MAGIC, regs + CSMR_LOCKACCESS); + readl(regs + CSMR_LOCKSTATUS); +} + +static void cs_relock(void *regs) +{ + writel(0, regs + CSMR_LOCKACCESS); +} + +static void cs_init_static_regs(void) +{ + /* Enable NIDEN and SPNIDEN */ + writel(0x5, tzpc3_regs + 0x828); + + /* Set funnel control: Enable ATB port0 */ + cs_unlock(cs_funnel_regs); + writel(0x301, cs_funnel_regs); + cs_relock(cs_funnel_regs); +} + +#ifdef CONFIG_PM +static void (*orig_pm_cpu_prep)(void); +static void (*orig_pm_cpu_restore)(void); + +static u32 etm_state[64]; +static int etm_state_count; +static u32 etb_ffcr; +static u32 etb_ctl; + +static void cs_pm_prep(void) +{ + int save_count; + + if (orig_pm_cpu_prep) + orig_pm_cpu_prep(); + + cs_unlock(cs_etb_regs); + etb_ctl = readl(cs_etb_regs + ETBR_CTRL); + etb_ffcr = readl(cs_etb_regs + ETBR_FORMATTERCTRL); + cs_relock(cs_etb_regs); + + cs_unlock(cs_etm_regs); + writel(UNLOCK_MAGIC, cs_etm_regs + ETMMR_OSLAR); + save_count = readl(cs_etm_regs + ETMMR_OSSRR); + pr_debug("%s: trace_pm_prep reg count %d\n", __func__, save_count); + if (save_count > ARRAY_SIZE(etm_state)) + save_count = 0; + etm_state_count = 0; + while (save_count--) + etm_state[etm_state_count++] = readl(cs_etm_regs + ETMMR_OSSRR); + writel(0, cs_etm_regs + ETMMR_OSLAR); + cs_relock(cs_etm_regs); +} + +static void cs_pm_resume(void) +{ + int i; + + cs_init_static_regs(); + + cs_unlock(cs_etb_regs); + writel(etb_ffcr, cs_etb_regs + ETBR_FORMATTERCTRL); + writel(etb_ctl, cs_etb_regs + ETBR_CTRL); + cs_relock(cs_etb_regs); + + cs_unlock(cs_etm_regs); + readl(cs_etm_regs + ETMMR_PDSR); + writel(UNLOCK_MAGIC, cs_etm_regs + ETMMR_OSLAR); + readl(cs_etm_regs + ETMMR_OSSRR); + for (i = 0; i < etm_state_count; i++) { + writel(etm_state[i], cs_etm_regs + ETMMR_OSSRR); + pr_debug("%s: restore %d %08x\n", __func__, i, etm_state[i]); + } + writel(0, cs_etm_regs + ETMMR_OSLAR); + cs_relock(cs_etm_regs); + + if (orig_pm_cpu_restore) + orig_pm_cpu_restore(); +} + +static void cs_pm_init(void) +{ + orig_pm_cpu_restore = pm_cpu_restore; + orig_pm_cpu_prep = pm_cpu_prep; + pm_cpu_restore = cs_pm_resume; + pm_cpu_prep = cs_pm_prep; +} +#else +static inline void cs_pm_init(void) {} +#endif + +static struct amba_device s5pv210_etb_device = { + .dev = { + .init_name = "etb", + }, + .res = { + .start = CS_ETB_BASE, + .end = CS_ETB_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = 0x000bb907, +}; + +static struct amba_device s5pv210_etm_device = { + .dev = { + .init_name = "etm", + }, + .res = { + .start = CS_ETM_BASE, + .end = CS_ETM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = 0x005bb921, +}; + +static int trace_init(void) +{ + cs_etb_regs = ioremap(CS_ETB_BASE, SZ_4K); + cs_funnel_regs = ioremap(CS_FUNNEL_BASE, SZ_4K); + cs_etm_regs = ioremap(CS_ETM_BASE, SZ_4K); + tzpc3_regs = ioremap(TZPC3_BASE, SZ_4K); + + cs_init_static_regs(); + + cs_pm_init(); + + amba_device_register(&s5pv210_etb_device, &iomem_resource); + amba_device_register(&s5pv210_etm_device, &iomem_resource); + return 0; +} +device_initcall(trace_init); diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 61e6c24..9974724 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -25,6 +25,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <asm/mach-types.h> #include <asm/proc-fns.h> #include <mach/map.h> #include <mach/regs-clock.h> @@ -95,7 +96,31 @@ static struct map_desc s5pv210_iodesc[] __initdata = { .pfn =__phys_to_pfn(S5PV210_PA_HSPHY), .length = SZ_4K, .type = MT_DEVICE, - } + }, { + .virtual = (unsigned long)S3C_VA_OTG, + .pfn = __phys_to_pfn(S5PV210_PA_OTG), + .length = SZ_1M, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_OTGSFR, + .pfn = __phys_to_pfn(S5PV210_PA_OTGSFR), + .length = SZ_1M, + .type = MT_DEVICE, + }, +#if defined(CONFIG_HRT_RTC) + { + .virtual = (unsigned long)S5P_VA_RTC, + .pfn = __phys_to_pfn(S5PV210_PA_RTC), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif + { + .virtual = (unsigned long)S5P_VA_AUDSS, + .pfn = __phys_to_pfn(S5PV210_PA_AUDSS), + .length = SZ_1M, + .type = MT_DEVICE, + }, }; static void s5pv210_idle(void) @@ -191,7 +216,8 @@ int __init s5pv210_init(void) pm_idle = s5pv210_idle; /* set sw_reset function */ - s5p_reset_hook = s5pv210_sw_reset; + if (!machine_is_herring()) + s5p_reset_hook = s5pv210_sw_reset; return sysdev_register(&s5pv210_sysdev); } diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c index 153af8b..8d07351 100644 --- a/arch/arm/mach-s5pv210/cpufreq.c +++ b/arch/arm/mach-s5pv210/cpufreq.c @@ -16,20 +16,48 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/suspend.h> +#include <linux/reboot.h> +#include <linux/regulator/consumer.h> #include <linux/cpufreq.h> +#include <linux/platform_device.h> #include <mach/map.h> #include <mach/regs-clock.h> +#include <mach/cpu-freq-v210.h> + +#ifdef CONFIG_CPU_DIDLE +#include <linux/deep_idle.h> +#endif static struct clk *cpu_clk; static struct clk *dmc0_clk; static struct clk *dmc1_clk; static struct cpufreq_freqs freqs; - -/* APLL M,P,S values for 1G/800Mhz */ +static DEFINE_MUTEX(set_freq_lock); + +/* APLL M,P,S values for 1.4GHz/1.2GHz/1.0GHz/800MHz */ +#define APLL_VAL_1400 ((1 << 31) | (175 << 16) | (3 << 8) | 1) +#define APLL_VAL_1320 ((1 << 31) | (330 << 16) | (6 << 8) | 1) +#define APLL_VAL_1300 ((1 << 31) | (325 << 16) | (6 << 8) | 0) +#define APLL_VAL_1200 ((1 << 31) | (150 << 16) | (3 << 8) | 1) +#define APLL_VAL_1100 ((1 << 31) | (275 << 16) | (6 << 8) | 1) #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1) #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1) +#define SLEEP_FREQ (800 * 1000) /* Use 800MHz when entering sleep */ + +/* + * relation has an additional symantics other than the standard of cpufreq + * DISALBE_FURTHER_CPUFREQ: disable further access to target until being re-enabled. + * ENABLE_FURTUER_CPUFREQ: re-enable access to target +*/ +enum cpufreq_access { + DISABLE_FURTHER_CPUFREQ = 0x10, + ENABLE_FURTHER_CPUFREQ = 0x20, +}; +static bool no_cpufreq_access; + /* * DRAM configurations to calculate refresh counter for changing * frequency of memory. @@ -43,7 +71,7 @@ struct dram_conf { static struct dram_conf s5pv210_dram_conf[2]; enum perf_level { - L0, L1, L2, L3, L4, + L0, L1, L2, L3, L4, L5, L6 }; enum s5pv210_mem_type { @@ -58,15 +86,82 @@ enum s5pv210_dmc_port { }; static struct cpufreq_frequency_table s5pv210_freq_table[] = { - {L0, 1000*1000}, - {L1, 800*1000}, - {L2, 400*1000}, - {L3, 200*1000}, - {L4, 100*1000}, + {L0, 1400*1000}, + {L1, 1200*1000}, + {L2, 1000*1000}, + {L3, 800*1000}, + {L4, 400*1000}, + {L5, 200*1000}, + {L6, 100*1000}, {0, CPUFREQ_TABLE_END}, }; -static u32 clkdiv_val[5][11] = { +// Define the freqs affected on the code to reduce changes +// if we add or remove a new freq on the table +unsigned int L_100 = L6; +unsigned int L_1000 = L2; +unsigned int L_200 = L5; +#define SpeedSteeps 7 + +static u32 sAPLL_confs[] = { + APLL_VAL_1400, + APLL_VAL_1200, + APLL_VAL_1000, + APLL_VAL_800, + APLL_VAL_800, + APLL_VAL_800, + APLL_VAL_800, + APLL_VAL_800, +}; + +static struct regulator *arm_regulator; +static struct regulator *internal_regulator; + +struct s5pv210_dvs_conf { + unsigned long arm_volt; /* uV */ + unsigned long int_volt; /* uV */ +}; + +#ifdef CONFIG_CUSTOM_VOLTAGE +unsigned long arm_volt_max = 1450000; +unsigned long int_volt_max = 1250000; +#else +const unsigned long arm_volt_max = 1450000; +const unsigned long int_volt_max = 1250000; +#endif + +static struct s5pv210_dvs_conf dvs_conf[] = { + [L0] = { + .arm_volt = 1420000, + .int_volt = 1180000, + }, + [L1] = { + .arm_volt = 1320000, + .int_volt = 1110000, + }, + [L2] = { + .arm_volt = 1250000, + .int_volt = 1100000, + }, + [L3] = { + .arm_volt = 1200000, + .int_volt = 1100000, + }, + [L4] = { + .arm_volt = 1050000, + .int_volt = 1100000, + }, + [L5] = { + .arm_volt = 950000, + .int_volt = 1100000, + }, + [L6] = { + .arm_volt = 950000, + .int_volt = 1000000, + }, +}; + +static u32 clkdiv_val[SpeedSteeps][11] = { /* * Clock divider value for following * { APLL, A2M, HCLK_MSYS, PCLK_MSYS, @@ -74,19 +169,25 @@ static u32 clkdiv_val[5][11] = { * ONEDRAM, MFC, G3D } */ - /* L0 : [1000/200/100][166/83][133/66][200/200] */ + /* L0 : [1400/200/100][166/83][133/66][200/200] */ + {0, 6, 6, 1, 3, 1, 4, 1, 3, 0, 0}, + + /* L1 : [1200/200/100][166/83][133/66][200/200] */ + {0, 5, 5, 1, 3, 1, 4, 1, 3, 0, 0}, + + /* L2 : [1000/200/100][166/83][133/66][200/200] */ {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0}, - /* L1 : [800/200/100][166/83][133/66][200/200] */ + /* L3 : [800/200/100][166/83][133/66][200/200] */ {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0}, - /* L2 : [400/200/100][166/83][133/66][200/200] */ + /* L4 : [400/200/100][166/83][133/66][200/200] */ {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, - /* L3 : [200/200/100][166/83][133/66][200/200] */ + /* L5 : [200/200/100][166/83][133/66][200/200] */ {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, - /* L4 : [100/100/100][83/83][66/66][100/100] */ + /* L6 : [100/100/100][83/83][66/66][100/100] */ {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0}, }; @@ -143,39 +244,82 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int relation) { unsigned long reg; - unsigned int index, priv_index; + unsigned int index; unsigned int pll_changing = 0; unsigned int bus_speed_changing = 0; + unsigned int arm_volt, int_volt; + int ret = 0; + + mutex_lock(&set_freq_lock); + + if (relation & ENABLE_FURTHER_CPUFREQ) + no_cpufreq_access = false; + +#ifdef CONFIG_CPU_DIDLE + // Ensures no application decreases the min freq when deepidle enabled at + // suspend mement + if (deepidle_is_enabled()) { + if (uIsSuspended == 1) { + if (policy->max != 800000) { + policy->user_policy.max = 800000; + policy->max = 800000; + } + } + } +#endif + + if (no_cpufreq_access) { +#ifdef CONFIG_PM_VERBOSE + pr_err("%s:%d denied access to %s as it is disabled" + "temporarily\n", __FILE__, __LINE__, __func__); +#endif + ret = -EINVAL; + goto out; + } + if (relation & DISABLE_FURTHER_CPUFREQ) + no_cpufreq_access = true; + relation &= ~(ENABLE_FURTHER_CPUFREQ | DISABLE_FURTHER_CPUFREQ); freqs.old = s5pv210_getspeed(0); if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, - target_freq, relation, &index)) - return -EINVAL; + target_freq, relation, &index)) { + ret = -EINVAL; + goto out; + } freqs.new = s5pv210_freq_table[index].frequency; freqs.cpu = 0; if (freqs.new == freqs.old) - return 0; + goto out; - /* Finding current running level index */ - if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, - freqs.old, relation, &priv_index)) - return -EINVAL; - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + arm_volt = dvs_conf[index].arm_volt; + int_volt = dvs_conf[index].int_volt; if (freqs.new > freqs.old) { - /* Voltage up: will be implemented */ + /* Voltage up code: increase ARM first */ + if (!IS_ERR_OR_NULL(arm_regulator) && + !IS_ERR_OR_NULL(internal_regulator)) { + ret = regulator_set_voltage(arm_regulator, + arm_volt, arm_volt_max); + if (ret) + goto out; + ret = regulator_set_voltage(internal_regulator, + int_volt, int_volt_max); + if (ret) + goto out; + } } + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + /* Check if there need to change PLL */ - if ((index == L0) || (priv_index == L0)) + if ((index <= L_1000) || (freqs.old >= s5pv210_freq_table[L_1000].frequency)) pll_changing = 1; /* Check if there need to change System bus clock */ - if ((index == L4) || (priv_index == L4)) + if ((index == L_100) || (freqs.old == s5pv210_freq_table[L_100].frequency)) bus_speed_changing = 1; if (bus_speed_changing) { @@ -229,7 +373,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, } while (reg & ((1 << 7) | (1 << 3))); /* - * 3. DMC1 refresh count for 133Mhz if (index == L4) is + * 3. DMC1 refresh count for 133Mhz if (index == L_100) is * true refresh counter is already programed in upper * code. 0x287@83Mhz */ @@ -274,7 +418,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, /* ARM MCS value changed */ reg = __raw_readl(S5P_ARM_MCS_CON); reg &= ~0x3; - if (index >= L3) + if (index >= L_200) reg |= 0x3; else reg |= 0x1; @@ -290,10 +434,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, * 6-1. Set PMS values * 6-2. Wait untile the PLL is locked */ - if (index == L0) - __raw_writel(APLL_VAL_1000, S5P_APLL_CON); - else - __raw_writel(APLL_VAL_800, S5P_APLL_CON); + __raw_writel(sAPLL_confs[index], S5P_APLL_CON); do { reg = __raw_readl(S5P_APLL_CON); @@ -341,7 +482,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, /* * 10. DMC1 refresh counter - * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c + * L_100 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618 */ if (!bus_speed_changing) @@ -349,7 +490,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, } /* - * L4 level need to change memory bus speed, hence onedram clock divier + * L_100 level need to change memory bus speed, hence onedram clock divier * and memory refresh parameter should be changed */ if (bus_speed_changing) { @@ -363,7 +504,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, } while (reg & (1 << 15)); /* Reconfigure DRAM refresh counter value */ - if (index != L4) { + if (index != L_100) { /* * DMC0 : 166Mhz * DMC1 : 200Mhz @@ -380,15 +521,23 @@ static int s5pv210_target(struct cpufreq_policy *policy, } } - if (freqs.new < freqs.old) { - /* Voltage down: will be implemented */ - } - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - printk(KERN_DEBUG "Perf changed[L%d]\n", index); + if (freqs.new < freqs.old) { + /* Voltage down: decrease INT first */ + if (!IS_ERR_OR_NULL(arm_regulator) && + !IS_ERR_OR_NULL(internal_regulator)) { + regulator_set_voltage(internal_regulator, + int_volt, int_volt_max); + regulator_set_voltage(arm_regulator, + arm_volt, arm_volt_max); + } + } - return 0; + pr_debug("Perf changed[L%d]\n", index); +out: + mutex_unlock(&set_freq_lock); + return ret; } #ifdef CONFIG_PM @@ -417,6 +566,8 @@ static int __init s5pv210_cpu_init(struct cpufreq_policy *policy) { unsigned long mem_type; + int ret; + cpu_clk = clk_get(NULL, "armclk"); if (IS_ERR(cpu_clk)) return PTR_ERR(cpu_clk); @@ -461,9 +612,54 @@ static int __init s5pv210_cpu_init(struct cpufreq_policy *policy) policy->cpuinfo.transition_latency = 40000; - return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table); + ret = cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table); + + if (!ret) + policy->max = 1000000; + + return ret; +} + +static int s5pv210_cpufreq_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int ret; + + switch (event) { + case PM_SUSPEND_PREPARE: + ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, + DISABLE_FURTHER_CPUFREQ); + if (ret < 0) + return NOTIFY_BAD; + return NOTIFY_OK; + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, + ENABLE_FURTHER_CPUFREQ); + return NOTIFY_OK; + } + return NOTIFY_DONE; } +static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int ret = 0; + + ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, + DISABLE_FURTHER_CPUFREQ); + + if (ret < 0) + return NOTIFY_BAD; + + return NOTIFY_DONE; +} + +static struct freq_attr *s5pv210_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + static struct cpufreq_driver s5pv210_driver = { .flags = CPUFREQ_STICKY, .verify = s5pv210_verify_speed, @@ -471,15 +667,78 @@ static struct cpufreq_driver s5pv210_driver = { .get = s5pv210_getspeed, .init = s5pv210_cpu_init, .name = "s5pv210", + .attr = s5pv210_cpufreq_attr, #ifdef CONFIG_PM .suspend = s5pv210_cpufreq_suspend, .resume = s5pv210_cpufreq_resume, #endif }; -static int __init s5pv210_cpufreq_init(void) +static struct notifier_block s5pv210_cpufreq_notifier = { + .notifier_call = s5pv210_cpufreq_notifier_event, +}; + +static struct notifier_block s5pv210_cpufreq_reboot_notifier = { + .notifier_call = s5pv210_cpufreq_reboot_notifier_event, +}; + +static int __init s5pv210_cpufreq_probe(struct platform_device *pdev) { + struct s5pv210_cpufreq_data *pdata = dev_get_platdata(&pdev->dev); + int i, j; + + if (pdata && pdata->size) { + for (i = 0; i < pdata->size; i++) { + j = 0; + while (s5pv210_freq_table[j].frequency != CPUFREQ_TABLE_END) { + if (s5pv210_freq_table[j].frequency == pdata->volt[i].freq) { + dvs_conf[j].arm_volt = pdata->volt[i].varm; + dvs_conf[j].int_volt = pdata->volt[i].vint; + break; + } + j++; + } + } + } + + arm_regulator = regulator_get(NULL, "vddarm"); + if (IS_ERR(arm_regulator)) { + pr_err("failed to get regulater resource vddarm\n"); + goto error; + } + internal_regulator = regulator_get(NULL, "vddint"); + if (IS_ERR(internal_regulator)) { + pr_err("failed to get regulater resource vddint\n"); + goto error; + } + goto finish; +error: + pr_warn("Cannot get vddarm or vddint. CPUFREQ Will not" + " change the voltage.\n"); +finish: + register_pm_notifier(&s5pv210_cpufreq_notifier); + register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier); + return cpufreq_register_driver(&s5pv210_driver); } +static struct platform_driver s5pv210_cpufreq_drv = { + .probe = s5pv210_cpufreq_probe, + .driver = { + .owner = THIS_MODULE, + .name = "s5pv210-cpufreq", + }, +}; + +static int __init s5pv210_cpufreq_init(void) +{ + int ret; + + ret = platform_driver_register(&s5pv210_cpufreq_drv); + if (!ret) + pr_info("%s: S5PV210 cpu-freq driver\n", __func__); + + return ret; +} + late_initcall(s5pv210_cpufreq_init); diff --git a/arch/arm/mach-s5pv210/cpuidle.c b/arch/arm/mach-s5pv210/cpuidle.c new file mode 100644 index 0000000..742bcfa --- /dev/null +++ b/arch/arm/mach-s5pv210/cpuidle.c @@ -0,0 +1,551 @@ +/* + * arch/arm/mach-s5pv210/cpuidle.c + * + * Copyright (c) Samsung Electronics Co. Ltd + * (c) 2011 Ezekeel <notezekeel@googlemail.com> + * + * CPU idle driver for S5PV210 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/cpuidle.h> +#include <linux/io.h> +#include <asm/proc-fns.h> +#include <asm/cacheflush.h> + +#include <mach/map.h> +#include <mach/regs-irq.h> +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> +#include <plat/pm.h> +#include <plat/devs.h> + +#ifdef CONFIG_CPU_DIDLE +#include <linux/dma-mapping.h> +#include <linux/deep_idle.h> + +#include <plat/regs-otg.h> +#include <mach/cpuidle.h> +#include <mach/power-domain.h> + +extern bool suspend_ongoing(void); +extern bool bt_is_running(void); +extern bool gps_is_running(void); +extern bool vibrator_is_running(void); + +/* + * For saving & restoring VIC register before entering + * didle mode + */ +static unsigned long vic_regs[4]; +static unsigned long *regs_save; +static dma_addr_t phy_regs_save; + +#define MAX_CHK_DEV 0xf + +/* + * Specific device list for checking before entering + * didle mode + */ +struct check_device_op { + void __iomem *base; + struct platform_device *pdev; +}; + +/* Array of checking devices list */ +static struct check_device_op chk_dev_op[] = { +#if defined(CONFIG_S3C_DEV_HSMMC) + {.base = 0, .pdev = &s3c_device_hsmmc0}, +#endif +#if defined(CONFIG_S3C_DEV_HSMMC1) + {.base = 0, .pdev = &s3c_device_hsmmc1}, +#endif +#if 0 + {.base = 0, .pdev = &s3c_device_hsmmc2}, +#endif +#if defined(CONFIG_S3C_DEV_HSMMC3) + {.base = 0, .pdev = &s3c_device_hsmmc3}, +#endif + {.base = 0, .pdev = NULL}, +}; + +#define S3C_HSMMC_PRNSTS (0x24) +#define S3C_HSMMC_CLKCON (0x2c) +#define S3C_HSMMC_CMD_INHIBIT 0x00000001 +#define S3C_HSMMC_DATA_INHIBIT 0x00000002 +#define S3C_HSMMC_CLOCK_CARD_EN 0x0004 + +static int sdmmc_dev_num; +/* If SD/MMC interface is working: return = 1 or not 0 */ +static int check_sdmmc_op(unsigned int ch) +{ + unsigned int reg1, reg2; + void __iomem *base_addr; + + if (unlikely(ch > sdmmc_dev_num)) { + printk(KERN_ERR "Invalid ch[%d] for SD/MMC\n", ch); + return 0; + } + + base_addr = chk_dev_op[ch].base; + /* Check CMDINHDAT[1] and CMDINHCMD [0] */ + reg1 = readl(base_addr + S3C_HSMMC_PRNSTS); + /* Check CLKCON [2]: ENSDCLK */ + reg2 = readl(base_addr + S3C_HSMMC_CLKCON); + + return !!(reg1 & (S3C_HSMMC_CMD_INHIBIT | S3C_HSMMC_DATA_INHIBIT)) || + (reg2 & (S3C_HSMMC_CLOCK_CARD_EN)); +} + +/* Check all sdmmc controller */ +static int loop_sdmmc_check(void) +{ + unsigned int iter; + + for (iter = 0; iter < sdmmc_dev_num + 1; iter++) { + if (check_sdmmc_op(iter)) + return 1; + } + return 0; +} + +/* + * Check USBOTG is working or not + * GOTGCTL(0xEC000000) + * BSesVld (Indicates the Device mode transceiver status) + * BSesVld = 1b : B-session is valid + * 0b : B-session is not valid + */ +static int check_usbotg_op(void) +{ + unsigned int val; + + val = __raw_readl(S3C_UDC_OTG_GOTGCTL); + + return val & (B_SESSION_VALID); +} + +/* + * Check power gating : LCD, CAM, TV, MFC, G3D + * Check clock gating : DMA, USBHOST, I2C + */ +extern volatile int s5p_rp_is_running; +extern int s5p_rp_get_op_level(void); + +static int check_power_clock_gating(void) +{ + unsigned long val; + + /* check power gating */ + val = __raw_readl(S5P_NORMAL_CFG); + if (val & (S5PV210_PD_LCD | S5PV210_PD_CAM | S5PV210_PD_TV + | S5PV210_PD_MFC | S5PV210_PD_G3D)) + return 1; + +#ifdef CONFIG_SND_S5P_RP + if (s5p_rp_get_op_level()) + return 1; +#endif + /* check clock gating */ + val = __raw_readl(S5P_CLKGATE_IP0); + if (val & (S5P_CLKGATE_IP0_MDMA | S5P_CLKGATE_IP0_PDMA0 + | S5P_CLKGATE_IP0_PDMA1)) + return 1; + + val = __raw_readl(S5P_CLKGATE_IP1); + if (val & S5P_CLKGATE_IP1_USBHOST) + return 1; + + val = __raw_readl(S5P_CLKGATE_IP3); + if (val & (S5P_CLKGATE_IP3_I2C0 | S5P_CLKGATE_IP3_I2C_HDMI_DDC + | S5P_CLKGATE_IP3_I2C2)) + return 1; + + return 0; +} + +/* + * Skipping enter the didle mode when RTC & I2S interrupts be issued + * during critical section of entering didle mode (around 20ms). + */ +#ifdef CONFIG_S5P_INTERNAL_DMA +static int check_idmapos(void) +{ + dma_addr_t src; + + i2sdma_getpos(&src); + src = src & 0x3FFF; + src = 0x4000 - src; + + return src < 0x150; +} +#endif + +static int check_rtcint(void) +{ + unsigned int current_cnt = get_rtc_cnt(); + + return current_cnt < 0x40; +} + +/* + * Before entering, didle mode GPIO Powe Down Mode + * Configuration register has to be set with same state + * in Normal Mode + */ +#define GPIO_OFFSET 0x20 +#define GPIO_CON_PDN_OFFSET 0x10 +#define GPIO_PUD_PDN_OFFSET 0x14 +#define GPIO_PUD_OFFSET 0x08 + +static unsigned int pud_pdn[(S5PV210_MP28_BASE - S5PV210_GPA0_BASE) / GPIO_OFFSET + 1]; +static unsigned int con_pdn[(S5PV210_MP28_BASE - S5PV210_GPA0_BASE) / GPIO_OFFSET + 1]; + +static void s5p_gpio_pdn_conf(void) +{ + void __iomem *gpio_base = S5PV210_GPA0_BASE; + unsigned int val; + int i = 0; + + do { + /* Save power down control state */ + con_pdn[i] = __raw_readl(gpio_base + GPIO_CON_PDN_OFFSET); + /* Keep the previous state in didle mode */ + __raw_writel(0xffff, gpio_base + GPIO_CON_PDN_OFFSET); + + /* Save power down pull up-down state */ + pud_pdn[i] = __raw_readl(gpio_base + GPIO_PUD_PDN_OFFSET); + /* Pull up-down state in didle is same as normal */ + val = __raw_readl(gpio_base + GPIO_PUD_OFFSET); + __raw_writel(val, gpio_base + GPIO_PUD_PDN_OFFSET); + + gpio_base += GPIO_OFFSET; + i++; + + } while (gpio_base <= S5PV210_MP28_BASE); + + return; +} + +static void s5p_gpio_restore_conf(void) +{ + void __iomem *gpio_base = S5PV210_GPA0_BASE; + int i = 0; + + do { + /* Restore power down control state */ + __raw_writel(con_pdn[i], gpio_base + GPIO_CON_PDN_OFFSET); + + /* Restore power down pull up-down state */ + __raw_writel(pud_pdn[i], gpio_base + GPIO_PUD_PDN_OFFSET); + + gpio_base += GPIO_OFFSET; + i++; + + } while (gpio_base <= S5PV210_MP28_BASE); + + return; +} + +static void s5p_enter_didle(bool top_on) +{ + unsigned long tmp; + unsigned long save_eint_mask; + + /* store the physical address of the register recovery block */ + __raw_writel(phy_regs_save, S5P_INFORM2); + + /* ensure at least INFORM0 has the resume address */ + __raw_writel(virt_to_phys(s5pv210_didle_resume), S5P_INFORM0); + + /* Save current VIC_INT_ENABLE register*/ + vic_regs[0] = __raw_readl(S5P_VIC0REG(VIC_INT_ENABLE)); + vic_regs[1] = __raw_readl(S5P_VIC1REG(VIC_INT_ENABLE)); + vic_regs[2] = __raw_readl(S5P_VIC2REG(VIC_INT_ENABLE)); + vic_regs[3] = __raw_readl(S5P_VIC3REG(VIC_INT_ENABLE)); + + /* Disable all interrupt through VIC */ + __raw_writel(0xffffffff, S5P_VIC0REG(VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, S5P_VIC1REG(VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, S5P_VIC2REG(VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, S5P_VIC3REG(VIC_INT_ENABLE_CLEAR)); + + if (!top_on) { + /* GPIO Power Down Control */ + s5p_gpio_pdn_conf(); + } + + /* + * Configure external interrupt wakeup mask + * We use the same wakeup mask as for sleep state plus make sure + * that at least XEINT[22] = GPH2[6] = GPIO_nPOWER = GPIO_N_POWER + * and XEINT[29] = GPH3[5] = GPIO_OK_KEY are enabled + */ + save_eint_mask = __raw_readl(S5P_EINT_WAKEUP_MASK); + tmp = s3c_irqwake_eintmask; + tmp &= ~((1<<22) | (1<<29)); + __raw_writel(tmp, S5P_EINT_WAKEUP_MASK); + + /* Clear wakeup status register */ + tmp = __raw_readl(S5P_WAKEUP_STAT); + __raw_writel(tmp, S5P_WAKEUP_STAT); + + /* + * Wakeup source configuration for didle + * We use the same wakeup mask as for sleep state plus make + * sure that at least RTC ALARM, RTC TICK, KEY, I2S and ST are + * enabled as wakeup sources + */ + tmp = s3c_irqwake_intmask; + tmp &= ~((1<<1) | (1<<2) | (1<<5) | (1<<13) | (1<<14)); + __raw_writel(tmp, S5P_WAKEUP_MASK); + + tmp = __raw_readl(S5P_IDLE_CFG); + tmp &= ~(0x3fU << 26); + if (top_on) { + /* + * IDLE config register set + * TOP_LOGIC = ON + * TOP_MEMORY = ON + * ARM_L2CACHE = Retention + * CFG_DIDLE = DEEP + */ + tmp |= ((2<<30) | (2<<28) | (1<<26) | (1<<0)); + } else { + /* + * IDLE config register set + * TOP_LOGIC = Retention + * TOP_MEMORY = Retention + * ARM_L2CACHE = Retention + * CFG_DIDLE = DEEP + */ + tmp |= ((1<<30) | (1<<28) | (1<<26) | (1<<0)); + } + __raw_writel(tmp, S5P_IDLE_CFG); + + /* Power mode Config setting */ + tmp = __raw_readl(S5P_PWR_CFG); + tmp &= S5P_CFG_WFI_CLEAN; + tmp |= S5P_CFG_WFI_IDLE; + __raw_writel(tmp, S5P_PWR_CFG); + + /* To check VIC Status register before enter didle mode */ + if ((__raw_readl(S5P_VIC0REG(VIC_RAW_STATUS)) & vic_regs[0]) | + (__raw_readl(S5P_VIC1REG(VIC_RAW_STATUS)) & vic_regs[1]) | + (__raw_readl(S5P_VIC2REG(VIC_RAW_STATUS)) & vic_regs[2]) | + (__raw_readl(S5P_VIC3REG(VIC_RAW_STATUS)) & vic_regs[3])) + goto skipped_didle; + + /* SYSCON_INT_DISABLE */ + tmp = __raw_readl(S5P_OTHERS); + tmp |= S5P_OTHER_SYSC_INTOFF; + __raw_writel(tmp, S5P_OTHERS); + + /* + * s5pv210_didle_save will also act as our return point from when + * we resume as it saves its own register state and restore it + * during the resume. + */ + s5pv210_didle_save(regs_save); + + /* restore the cpu state using the kernel's cpu init code. */ + cpu_init(); + +skipped_didle: + __raw_writel(save_eint_mask, S5P_EINT_WAKEUP_MASK); + + tmp = __raw_readl(S5P_IDLE_CFG); + tmp &= ~((3<<30) | (3<<28) | (3<<26) | (1<<0)); + tmp |= ((2<<30) | (2<<28)); + __raw_writel(tmp, S5P_IDLE_CFG); + + /* Power mode Config setting */ + tmp = __raw_readl(S5P_PWR_CFG); + tmp &= S5P_CFG_WFI_CLEAN; + __raw_writel(tmp, S5P_PWR_CFG); + + if (!top_on) { + /* Release retention GPIO/CF/MMC/UART IO */ + tmp = __raw_readl(S5P_OTHERS); + tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | \ + S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART); + __raw_writel(tmp, S5P_OTHERS); + } + + if (!top_on) { + /* Restore GPIO Power Down Configuration */ + s5p_gpio_restore_conf(); + } + + __raw_writel(vic_regs[0], S5P_VIC0REG(VIC_INT_ENABLE)); + __raw_writel(vic_regs[1], S5P_VIC1REG(VIC_INT_ENABLE)); + __raw_writel(vic_regs[2], S5P_VIC2REG(VIC_INT_ENABLE)); + __raw_writel(vic_regs[3], S5P_VIC3REG(VIC_INT_ENABLE)); +} +#endif + +static void s5p_enter_idle(void) +{ + unsigned long tmp; + + tmp = __raw_readl(S5P_IDLE_CFG); + tmp &= ~((3U<<30)|(3<<28)|(1<<0)); + tmp |= ((2U<<30)|(2<<28)); + __raw_writel(tmp, S5P_IDLE_CFG); + + tmp = __raw_readl(S5P_PWR_CFG); + tmp &= S5P_CFG_WFI_CLEAN; + __raw_writel(tmp, S5P_PWR_CFG); + + cpu_do_idle(); +} + +/* Actual code that puts the SoC in different idle states */ +static int s5p_enter_idle_state(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + struct timeval before, after; + int idle_time; +#ifdef CONFIG_CPU_DIDLE + int idle_state = 0; +#endif + + local_irq_disable(); + do_gettimeofday(&before); + +#ifdef CONFIG_CPU_DIDLE +#ifdef CONFIG_S5P_INTERNAL_DMA + if (!deepidle_is_enabled() || check_power_clock_gating() || suspend_ongoing() || loop_sdmmc_check() || check_usbotg_op() || check_rtcint() || check_idmapos()) { +#else + if (!deepidle_is_enabled() || check_power_clock_gating() || suspend_ongoing() || loop_sdmmc_check() || check_usbotg_op() || check_rtcint()) { +#endif + s5p_enter_idle(); + } else if (bt_is_running() || gps_is_running() || vibrator_is_running()) { + s5p_enter_didle(true); + idle_state = 1; + } else { + s5p_enter_didle(false); + idle_state = 2; + } +#else + s5p_enter_idle(); +#endif + + do_gettimeofday(&after); + local_irq_enable(); + idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + + (after.tv_usec - before.tv_usec); +#ifdef CONFIG_CPU_DIDLE + report_idle_time(idle_state, idle_time); +#endif + return idle_time; +} + +static DEFINE_PER_CPU(struct cpuidle_device, s5p_cpuidle_device); + +static struct cpuidle_driver s5p_idle_driver = { + .name = "s5p_idle", + .owner = THIS_MODULE, +}; + +/* Initialize CPU idle by registering the idle states */ +static int s5p_init_cpuidle(void) +{ + struct cpuidle_device *device; + int ret; + +#ifdef CONFIG_CPU_DIDLE + struct resource *res; + struct platform_device *pdev; + int i = 0; +#endif + + ret = cpuidle_register_driver(&s5p_idle_driver); + if (ret) { + printk(KERN_ERR "%s: Failed registering driver\n", __func__); + goto err; + } + + device = &per_cpu(s5p_cpuidle_device, smp_processor_id()); + device->state_count = 1; + + /* Wait for interrupt state */ + device->states[0].enter = s5p_enter_idle_state; + device->states[0].exit_latency = 1; /* uS */ + device->states[0].target_residency = 10000; + device->states[0].flags = CPUIDLE_FLAG_TIME_VALID; +#ifdef CONFIG_CPU_DIDLE + strcpy(device->states[0].name, "(DEEP)IDLE"); + strcpy(device->states[0].desc, "ARM clock/power gating - WFI"); +#else + strcpy(device->states[0].name, "IDLE"); + strcpy(device->states[0].desc, "ARM clock gating - WFI"); +#endif + + ret = cpuidle_register_device(device); + if (ret) { + printk(KERN_ERR "%s: Failed registering device\n", __func__); + goto err_register_driver; + } + +#ifdef CONFIG_CPU_DIDLE + regs_save = dma_alloc_coherent(NULL, 4096, &phy_regs_save, GFP_KERNEL); + if (regs_save == NULL) { + printk(KERN_ERR "%s: DMA alloc error\n", __func__); + ret = -ENOMEM; + goto err_register_device; + } + printk(KERN_INFO "cpuidle: phy_regs_save:0x%x\n", phy_regs_save); + + /* Allocate memory region to access IP's directly */ + for (i = 0 ; i < MAX_CHK_DEV ; i++) { + + pdev = chk_dev_op[i].pdev; + + if (pdev == NULL) { + sdmmc_dev_num = i - 1; + break; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk(KERN_ERR "%s: failed to get io memory region\n", + __func__); + ret = -EINVAL; + goto err_alloc; + } + chk_dev_op[i].base = ioremap_nocache(res->start, 4096); + + if (!chk_dev_op[i].base) { + printk(KERN_ERR "failed to remap io region\n"); + ret = -EINVAL; + goto err_resource; + } + } +#endif + + return 0; + +#ifdef CONFIG_CPU_DIDLE +err_alloc: + while (--i >= 0) { + iounmap(chk_dev_op[i].base); + } +err_resource: + dma_free_coherent(NULL, 4096, regs_save, phy_regs_save); +err_register_device: + cpuidle_unregister_device(device); +#endif +err_register_driver: + cpuidle_unregister_driver(&s5p_idle_driver); +err: + return ret; +} + +device_initcall(s5p_init_cpuidle); diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 8d58f19..c6109b1 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -80,8 +80,8 @@ static struct resource s5pv210_iis0_resource[] = { }; struct platform_device s5pv210_device_iis0 = { - .name = "samsung-i2s", - .id = 0, + .name = "samsung-i2s", + .id = 0, .num_resources = ARRAY_SIZE(s5pv210_iis0_resource), .resource = s5pv210_iis0_resource, .dev = { diff --git a/arch/arm/mach-s5pv210/dev-cpufreq.c b/arch/arm/mach-s5pv210/dev-cpufreq.c new file mode 100644 index 0000000..ff0e0f1 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-cpufreq.c @@ -0,0 +1,28 @@ +/* + * linux/arch/arm/mach-s5pv210/dev-cpufreq.c + * + * Copyright (c) 2008-2010 Samsung Electronics + * Taekki Kim <taekki.kim@samsung.com> + * + * S5PV210 series device definition for cpufreq devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <mach/cpu-freq-v210.h> + +struct platform_device s5pv210_device_cpufreq = { + .name = "s5pv210-cpufreq", + .id = -1, +}; + +void s5pv210_cpufreq_set_platdata(struct s5pv210_cpufreq_data *pdata) +{ + s5pv210_device_cpufreq.dev.platform_data = pdata; +} + diff --git a/arch/arm/mach-s5pv210/dev-fiqdbg.c b/arch/arm/mach-s5pv210/dev-fiqdbg.c new file mode 100644 index 0000000..16ef49b --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-fiqdbg.c @@ -0,0 +1,161 @@ +/* linux/arch/arm/mach-s5pv210/dev-fiqdbg.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/irq.h> +#include <linux/sysdev.h> + +#include <asm/hardware/vic.h> +#include <asm/fiq_debugger.h> + +#include <mach/irqs.h> +#include <mach/map.h> +#include <plat/regs-serial.h> + +static void *s5pv210_fiqdbg_get_base(struct platform_device *pdev) +{ + return S5P_VA_UART0 + S3C_UART_OFFSET * pdev->id; +} + +static unsigned int s5pv210_fiqdbg_tx_empty(void *base) +{ + unsigned long ufstat = readl(base + S3C2410_UFSTAT); + + return !(ufstat & (S5PV210_UFSTAT_TXMASK | S5PV210_UFSTAT_TXFULL)); +} + +static void s5pv210_fiqdbg_wait_for_tx_empty(void *base) +{ + unsigned int tmout = 10000; + + while (true) { + if (s5pv210_fiqdbg_tx_empty(base)) + return; + if (--tmout == 0) + break; + udelay(1); + } +} + +static int s5pv210_fiqdbg_uart_getc(struct platform_device *pdev) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + unsigned int ufstat; + + if (readl(base + S3C2410_UERSTAT) & S3C2410_UERSTAT_BREAK) + return FIQ_DEBUGGER_BREAK; + + ufstat = readl(base + S3C2410_UFSTAT); + if (!(ufstat & (S5PV210_UFSTAT_RXMASK | S5PV210_UFSTAT_RXFULL))) + return FIQ_DEBUGGER_NO_CHAR; + return readb(base + S3C2410_URXH); +} + +static void s5pv210_fiqdbg_uart_putc(struct platform_device *pdev, + unsigned int c) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + s5pv210_fiqdbg_wait_for_tx_empty(base); + writeb(c, base + S3C2410_UTXH); + if (c == 10) { + s5pv210_fiqdbg_wait_for_tx_empty(base); + writeb(13, base + S3C2410_UTXH); + } + s5pv210_fiqdbg_wait_for_tx_empty(base); +} + +static void fiq_enable(struct platform_device *pdev, + unsigned int fiq, bool enabled) +{ + struct irq_chip *chip = irq_get_chip(fiq); + struct irq_data *d = irq_get_irq_data(fiq); + + vic_set_fiq(fiq, enabled); + if (enabled) + chip->irq_unmask(d); + else + chip->irq_mask(d); +} + +static void fiq_ack(struct platform_device *pdev, unsigned int fiq) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + writel(0x3, base + S5P_UINTP); +} + +static int s5pv210_fiqdbg_uart_init(struct platform_device *pdev) +{ + void *base = s5pv210_fiqdbg_get_base(pdev); + + writel(S3C2410_UCON_TXILEVEL | + S3C2410_UCON_RXILEVEL | + S3C2410_UCON_TXIRQMODE | + S3C2410_UCON_RXIRQMODE | + S3C2410_UCON_RXFIFO_TOI | + S3C2443_UCON_RXERR_IRQEN, base + S3C2410_UCON); + writel(S3C2410_LCON_CS8, base + S3C2410_ULCON); + writel(S3C2410_UFCON_FIFOMODE | + S5PV210_UFCON_TXTRIG4 | + S5PV210_UFCON_RXTRIG4 | + S3C2410_UFCON_RESETRX, base + S3C2410_UFCON); + writel(0, base + S3C2410_UMCON); + /* 115200 */ + writel(35, base + S3C2410_UBRDIV); + writel(0x808, base + S3C2443_DIVSLOT); + writel(0xc, base + S5P_UINTM); + writel(0xf, base + S5P_UINTP); + + return 0; +} + +static struct fiq_debugger_pdata s5pv210_fiqdbg_pdata = { + .uart_init = s5pv210_fiqdbg_uart_init, + .uart_resume = s5pv210_fiqdbg_uart_init, + .uart_getc = s5pv210_fiqdbg_uart_getc, + .uart_putc = s5pv210_fiqdbg_uart_putc, + .fiq_enable = fiq_enable, + .fiq_ack = fiq_ack, +}; + +#define DEFINE_FIQDBG_UART(uart) \ +static struct resource s5pv210_fiqdbg_uart##uart##_resource[] = { \ + { \ + .start = IRQ_UART##uart, \ + .end = IRQ_UART##uart, \ + .name = "fiq", \ + .flags = IORESOURCE_IRQ, \ + }, \ + { \ + .start = IRQ_VIC_END-uart, \ + .end = IRQ_VIC_END-uart, \ + .name = "signal", \ + .flags = IORESOURCE_IRQ, \ + }, \ +}; \ +struct platform_device s5pv210_device_fiqdbg_uart##uart = { \ + .name = "fiq_debugger", \ + .id = uart, \ + .num_resources = ARRAY_SIZE(s5pv210_fiqdbg_uart##uart##_resource), \ + .resource = s5pv210_fiqdbg_uart##uart##_resource, \ + .dev = { \ + .platform_data = &s5pv210_fiqdbg_pdata, \ + }, \ +} + +DEFINE_FIQDBG_UART(0); +DEFINE_FIQDBG_UART(1); +DEFINE_FIQDBG_UART(2); +DEFINE_FIQDBG_UART(3); diff --git a/arch/arm/mach-s5pv210/dev-herring-phone.c b/arch/arm/mach-s5pv210/dev-herring-phone.c new file mode 100755 index 0000000..b605e02 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-herring-phone.c @@ -0,0 +1,79 @@ +/* linux/arch/arm/mach-s5pv210/dev-herring-phone.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/gpio-herring.h> + +#include "../../../drivers/misc/samsung_modemctl/modem_ctl.h" +#include "herring.h" + +/* Modem control */ +static struct modemctl_data mdmctl_data = { + .name = "xmm", + .gpio_phone_active = GPIO_PHONE_ACTIVE, + .gpio_pda_active = GPIO_PDA_ACTIVE, + .gpio_cp_reset = GPIO_CP_RST, + .gpio_phone_on = GPIO_PHONE_ON, + .is_cdma_modem = 0, + .num_pdp_contexts = 3, +}; + +static struct resource mdmctl_res[] = { + [0] = { + .name = "active", + .start = IRQ_EINT15, + .end = IRQ_EINT15, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "onedram", + .start = IRQ_EINT11, + .end = IRQ_EINT11, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "onedram", + .start = (S5PV210_PA_SDRAM + 0x05000000), + .end = (S5PV210_PA_SDRAM + 0x05000000 + SZ_16M - 1), + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device modemctl = { + .name = "modemctl", + .id = -1, + .num_resources = ARRAY_SIZE(mdmctl_res), + .resource = mdmctl_res, + .dev = { + .platform_data = &mdmctl_data, + }, +}; + +static int __init herring_init_phone_interface(void) +{ + /* CDMA device */ + if (herring_is_cdma_wimax_dev()) { + mdmctl_data.is_cdma_modem = 1; + mdmctl_data.num_pdp_contexts = 1; + } + + platform_device_register(&modemctl); + return 0; +} +device_initcall(herring_init_phone_interface); diff --git a/arch/arm/mach-s5pv210/didle.S b/arch/arm/mach-s5pv210/didle.S new file mode 100644 index 0000000..2abaca0 --- /dev/null +++ b/arch/arm/mach-s5pv210/didle.S @@ -0,0 +1,218 @@ +/* linux/arch/arm/mach-s5pv210/didle.S + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/hardware.h> +#include <mach/map.h> +#include <asm/asm-offsets.h> +#include <asm/memory.h> +#include <asm/system.h> + +/* + * v7_flush_l1_dcache() + * + * Flush the L1 D-cache. + */ +ENTRY(v7_flush_l1_dcache) + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt finished @ finish if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb + isb + mov pc, lr +ENDPROC(v7_flush_l1_dcache) + +ENTRY(v7_flush_cache_for_didle) + stmfd sp!, {r4-r5, r7, r9-r11, lr} + bl v7_flush_l1_dcache + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + ldmfd sp!, {r4-r5, r7, r9-r11, lr} + mov pc, lr +ENDPROC(v7_flush_cache_for_didle) + +ENTRY(s5pv210_didle) + stmfd sp!, {r4-r5, r7, r9-r11, lr} + + bl v7_flush_cache_for_didle + + ldmfd sp!, {r4-r5, r7, r9-r11, lr} + dmb + dsb + wfi + + b . + + .text + + /* s5pv210_didle_save + * + * entry: + * r0 = save address (virtual addr of s3c_sleep_save_phys) + */ + +ENTRY(s5pv210_didle_save) + + stmfd sp!, { r3 - r12, lr } + + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control + mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mrc p15, 0, r12, c10, c2, 0 @ Read PRRR + mrc p15, 0, r3, c10, c2, 1 @ READ NMRR + + /* Save CP15 registers */ + stmia r0, { r3 - r13 } + + bl s5pv210_didle + + @@ return to the caller, after having the MMU + @@ turned on, this restores the last bits from the + @@ stack +resume_with_mmu: + mrc p15, 0, r0, c1, c0, 1 @enable L2 cache + orr r0, r0, #(1<<1) + mcr p15, 0, r0, c1, c0, 1 + + mov r0, #1 + /* delete added mmu table list */ + ldr r9 , =(PAGE_OFFSET - PLAT_PHYS_OFFSET) + add r4, r4, r9 + str r12, [r4] + + ldmfd sp!, { r3 - r12, pc } + + .ltorg + + /* s5pv210_didle_resume + * + * resume code entry for bootloader to call + * + * we must put this code here in the data segment as we have no + * other way of restoring the stack pointer after sleep, and we + * must not write to the code segment (code is read-only) + */ + +ENTRY(s5pv210_didle_resume) + mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE + msr cpsr_c, r0 + + @@ load UART to allow us to print the two characters for + @@ resume debug + + mov r1, #0 + mcr p15, 0, r1, c8, c7, 0 @@ invalidate TLBs + mcr p15, 0, r1, c7, c5, 0 @@ invalidate I Cache + + ldr r1, =0xe010f008 @ Read INFORM2 register + ldr r0, [r1] @ Load phy_regs_save value + ldmia r0, { r3 - r13 } + + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + + mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control + mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + + bic r10, r10, #(1<<1) @ disable L2cache + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB + + mov r0, #0 @ restore copro access controls + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mcr p15, 0, r0, c7, c5, 4 + + mcr p15, 0, r12, c10, c2, 0 @ write PRRR + mcr p15, 0, r3, c10, c2, 1 @ write NMRR + + /* calculate first section address into r8 */ + mov r4, r6 + ldr r5, =0x3fff + bic r4, r4, r5 + ldr r11, =0xe010f000 + ldr r10, [r11, #0] + mov r10, r10 ,LSR #18 + bic r10, r10, #0x3 + orr r4, r4, r10 + + /* calculate mmu list value into r9 */ + mov r10, r10, LSL #18 + ldr r5, =0x40e + orr r10, r10, r5 + + /* back up originally data */ + ldr r12, [r4] + + /* Added list about mmu */ + str r10, [r4] + + ldr r2, =resume_with_mmu + mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc + + nop + nop + nop + nop + nop @ second-to-last before mmu + + mov pc, r2 @ go back to virtual address + + .ltorg diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index 497d343..34cfacc 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -30,6 +30,71 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); +static struct resource s5pv210_mdma_resource[] = { + [0] = { + .start = S5PV210_PA_MDMA, + .end = S5PV210_PA_MDMA + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MDMA, + .end = IRQ_MDMA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pv210_mdma_pdata = { + .peri = { + /* The DMAC can have max 8 channel so there + * can be 8 M<->M requests served at any time. + */ + [0] = DMACH_MTOM_0, + [1] = DMACH_MTOM_1, + [2] = DMACH_MTOM_2, + [3] = DMACH_MTOM_3, + [4] = DMACH_MTOM_4, + [5] = DMACH_MTOM_5, + [6] = DMACH_MTOM_6, + [7] = DMACH_MTOM_7, + [8] = DMACH_MAX, + [9] = DMACH_MAX, + [10] = DMACH_MAX, + [11] = DMACH_MAX, + [12] = DMACH_MAX, + [13] = DMACH_MAX, + [14] = DMACH_MAX, + [15] = DMACH_MAX, + [16] = DMACH_MAX, + [17] = DMACH_MAX, + [18] = DMACH_MAX, + [19] = DMACH_MAX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_MAX, + [23] = DMACH_MAX, + [24] = DMACH_MAX, + [25] = DMACH_MAX, + [26] = DMACH_MAX, + [27] = DMACH_MAX, + [28] = DMACH_MAX, + [29] = DMACH_MAX, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +struct platform_device s5pv210_device_mdma = { + .name = "s3c-pl330", + .id = 0, + .num_resources = ARRAY_SIZE(s5pv210_mdma_resource), + .resource = s5pv210_mdma_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_mdma_pdata, + }, +}; + static struct resource s5pv210_pdma0_resource[] = { [0] = { .start = S5PV210_PA_PDMA0, @@ -80,9 +145,9 @@ static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { }, }; -static struct platform_device s5pv210_device_pdma0 = { +struct platform_device s5pv210_device_pdma0 = { .name = "s3c-pl330", - .id = 0, + .id = 1, .num_resources = ARRAY_SIZE(s5pv210_pdma0_resource), .resource = s5pv210_pdma0_resource, .dev = { @@ -142,9 +207,9 @@ static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { }, }; -static struct platform_device s5pv210_device_pdma1 = { +struct platform_device s5pv210_device_pdma1 = { .name = "s3c-pl330", - .id = 1, + .id = 2, .num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), .resource = s5pv210_pdma1_resource, .dev = { @@ -155,6 +220,7 @@ static struct platform_device s5pv210_device_pdma1 = { }; static struct platform_device *s5pv210_dmacs[] __initdata = { + &s5pv210_device_mdma, &s5pv210_device_pdma0, &s5pv210_device_pdma1, }; diff --git a/arch/arm/mach-s5pv210/herring-btlpm.c b/arch/arm/mach-s5pv210/herring-btlpm.c new file mode 100644 index 0000000..362f35a --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-btlpm.c @@ -0,0 +1,66 @@ +/* linux/arch/arm/mach-s5pv210/herring-btlpm.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/hrtimer.h> + +#include <asm/mach-types.h> + +#include <mach/gpio-herring.h> + +#include "herring.h" + +static struct herring_bt_lpm { + struct hrtimer bt_lpm_timer; + ktime_t bt_lpm_delay; +} bt_lpm; + +static enum hrtimer_restart bt_enter_lpm(struct hrtimer *timer) +{ + gpio_set_value(GPIO_BT_WAKE, 0); + + return HRTIMER_NORESTART; +} + +void herring_bt_uart_wake_peer(struct uart_port *port) +{ + if (!bt_lpm.bt_lpm_timer.function) + return; + + hrtimer_try_to_cancel(&bt_lpm.bt_lpm_timer); + gpio_set_value(GPIO_BT_WAKE, 1); + hrtimer_start(&bt_lpm.bt_lpm_timer, bt_lpm.bt_lpm_delay, HRTIMER_MODE_REL); +} + +static int __init bt_lpm_init(void) +{ + int ret; + + if (!machine_is_herring()) + return 0; + + ret = gpio_request(GPIO_BT_WAKE, "gpio_bt_wake"); + if (ret) { + printk(KERN_ERR "Failed to request gpio_bt_wake control\n"); + return 0; + } + + gpio_direction_output(GPIO_BT_WAKE, GPIO_LEVEL_LOW); + + hrtimer_init(&bt_lpm.bt_lpm_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + bt_lpm.bt_lpm_delay = ktime_set(1, 0); /* 1 sec */ + bt_lpm.bt_lpm_timer.function = bt_enter_lpm; + return 0; +} +device_initcall(bt_lpm_init); diff --git a/arch/arm/mach-s5pv210/herring-panel.c b/arch/arm/mach-s5pv210/herring-panel.c new file mode 100755 index 0000000..e84d6e8 --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-panel.c @@ -0,0 +1,1018 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/tl2796.h> +#include <linux/nt35580.h> +#include <mach/gpio.h> +#include <linux/delay.h> + +static const u16 s6e63m0_SEQ_STANDBY_ON[] = { + 0x010, /* Stand-by On Command */ + SLEEPMSEC, 160, + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_STANDBY_OFF[] = { + 0x011, /* Stand-by Off Command */ + SLEEPMSEC, 120, + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_DISPLAY_SETTING[] = { + SLEEPMSEC, 10, + 0x0F8, /* Panel Condition Set Command*/ + 0x101, /* DOCT */ + 0x127, /* CLWEA */ + 0x127, /* CLWEB*/ + 0x107, /* CLTE */ + 0x107, /* SHE */ + 0x154, /* FLTE */ + 0x19F, /* FLWE */ + 0x163, /* SCTE */ + 0x186, /* SCWE */ + 0x11A, /* INTE */ + 0x133, /* INWE */ + 0x10D, /* EMPS */ + 0x100, /* E_INTE */ + 0x100, /* E_INWE */ + 0x0F2, /* Display Condition Set Command*/ + 0x102, /* Number of Line */ + 0x103, /* VBP */ + 0x11C, /* VFP */ + 0x110, /* HBP */ + 0x110, /* HFP */ + 0x0F7, /* Command */ + 0x103, /* GTCON */ + 0x100, /* Display Mode */ + 0x100, /* Vsync/Hsync, DOCCLK, RGB mode */ + ENDDEF, 0x0000 +}; + +static const u16 s6e63m0_SEQ_ETC_SETTING[] = { + /* ETC Condition Set Command */ + 0x0F6, + 0x100, 0x18E, + 0x107, + 0x0B3, + 0x16C, + 0x0B5, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0B6, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x0B7, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0B8, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x0B9, + 0x127, 0x10A, + 0x109, 0x107, + 0x130, 0x11C, + 0x113, 0x109, + 0x110, 0x11A, + 0x12A, 0x124, + 0x11F, 0x11B, + 0x11A, 0x117, + 0x12B, 0x126, + 0x122, 0x120, + 0x13A, 0x134, + 0x130, 0x12C, + 0x129, 0x126, + 0x125, 0x123, + 0x121, 0x120, + 0x11E, 0x11E, + 0x0BA, + 0x100, 0x100, + 0x123, 0x111, + 0x132, 0x144, + 0x144, 0x144, + 0x155, 0x155, + 0x166, 0x166, + 0x166, 0x166, + 0x166, 0x166, + 0x011, + SLEEPMSEC, 120, + 0x029, + ENDDEF, 0x0000 +}; + +static const struct tl2796_gamma_adj_points gamma_adj_points = { + .v0 = 0, + .v1 = BV_1, + .v19 = BV_19, + .v43 = BV_43, + .v87 = BV_87, + .v171 = BV_171, + .v255 = BV_255, +}; + +#ifdef CONFIG_FB_VOODOO +struct gamma_entry gamma_table[] = { +#else +static const struct gamma_entry gamma_table[] = { +#endif + { BV_0, { 4200000, 4200000, 4200000, }, }, + { 1, { 3994200, 4107600, 3910200, }, }, + { 0x00000400, { 3669486, 3738030, 3655093, }, }, + { 0x000004C2, { 3664456, 3732059, 3649872, }, }, + { 0x000005A8, { 3659356, 3726019, 3644574, }, }, + { 0x000006BA, { 3654160, 3719879, 3639171, }, }, + { 0x00000800, { 3648872, 3713646, 3633668, }, }, + { 0x00000983, { 3643502, 3707331, 3628075, }, }, + { 0x00000B50, { 3638029, 3700909, 3622368, }, }, + { 0x00000D74, { 3632461, 3694392, 3616558, }, }, + { 0x00001000, { 3626792, 3687772, 3610636, }, }, + { 0x00001307, { 3621022, 3681052, 3604605, }, }, + { 0x000016A1, { 3615146, 3674224, 3598455, }, }, + { 0x00001AE9, { 3609163, 3667289, 3592189, }, }, + { 0x00002000, { 3603070, 3660245, 3585801, }, }, + { 0x0000260E, { 3596860, 3653083, 3579284, }, }, + { 0x00002D41, { 3590532, 3645805, 3572637, }, }, + { 0x000035D1, { 3584081, 3638403, 3565854, }, }, + { 0x00004000, { 3577504, 3630876, 3558930, }, }, + { 0x00004C1C, { 3570797, 3623221, 3551863, }, }, + { 0x00005A82, { 3563956, 3615434, 3544649, }, }, + { 0x00006BA2, { 3556976, 3607510, 3537279, }, }, + { 0x00008000, { 3549853, 3599444, 3529750, }, }, + { 0x00009838, { 3542582, 3591234, 3522056, }, }, + { 0x0000B505, { 3535159, 3582874, 3514193, }, }, + { 0x0000D745, { 3527577, 3574360, 3506153, }, }, + { 0x00010000, { 3519832, 3565687, 3497931, }, }, + { 0x00013070, { 3511918, 3556849, 3489519, }, }, + { 0x00016A0A, { 3503829, 3547842, 3480912, }, }, + { 0x0001AE8A, { 3495559, 3538659, 3472102, }, }, + { 0x00020000, { 3487101, 3529295, 3463080, }, }, + { 0x000260E0, { 3478447, 3519742, 3453839, }, }, + { 0x0002D414, { 3469592, 3509996, 3444372, }, }, + { 0x00035D14, { 3460527, 3500049, 3434667, }, }, + { 0x00040000, { 3451244, 3489893, 3424717, }, }, + { 0x0004C1C0, { 3441734, 3479522, 3414512, }, }, + { 0x0005A828, { 3431990, 3468927, 3404040, }, }, + { 0x0006BA28, { 3422000, 3458099, 3393292, }, }, + { 0x00080000, { 3411756, 3447030, 3382254, }, }, + { 0x0009837F, { 3401247, 3435711, 3370915, }, }, + { 0x000B504F, { 3390462, 3424131, 3359262, }, }, + { 0x000D7450, { 3379388, 3412280, 3347281, }, }, + { 0x00100000, { 3368014, 3400147, 3334957, }, }, + { 0x001306FE, { 3356325, 3387721, 3322274, }, }, + { 0x0016A09E, { 3344309, 3374988, 3309216, }, }, + { 0x001AE8A0, { 3331950, 3361936, 3295765, }, }, + { 0x00200000, { 3319231, 3348550, 3281902, }, }, + { 0x00260DFC, { 3306137, 3334817, 3267607, }, }, + { 0x002D413D, { 3292649, 3320719, 3252859, }, }, + { 0x0035D13F, { 3278748, 3306240, 3237634, }, }, + { 0x00400000, { 3264413, 3291361, 3221908, }, }, + { 0x004C1BF8, { 3249622, 3276065, 3205654, }, }, + { 0x005A827A, { 3234351, 3260329, 3188845, }, }, + { 0x006BA27E, { 3218576, 3244131, 3171449, }, }, + { 0x00800000, { 3202268, 3227448, 3153434, }, }, + { 0x009837F0, { 3185399, 3210255, 3134765, }, }, + { 0x00B504F3, { 3167936, 3192523, 3115404, }, }, + { 0x00D744FD, { 3149847, 3174223, 3095308, }, }, + { 0x01000000, { 3131093, 3155322, 3074435, }, }, + { 0x01306FE1, { 3111635, 3135786, 3052735, }, }, + { 0x016A09E6, { 3091431, 3115578, 3030156, }, }, + { 0x01AE89FA, { 3070432, 3094655, 3006641, }, }, + { 0x02000000, { 3048587, 3072974, 2982127, }, }, + { 0x0260DFC1, { 3025842, 3050485, 2956547, }, }, + { 0x02D413CD, { 3002134, 3027135, 2929824, }, }, + { 0x035D13F3, { 2977397, 3002865, 2901879, }, }, + { 0x04000000, { 2951558, 2977611, 2872620, }, }, + { 0x04C1BF83, { 2924535, 2951302, 2841948, }, }, + { 0x05A8279A, { 2896240, 2923858, 2809753, }, }, + { 0x06BA27E6, { 2866574, 2895192, 2775914, }, }, + { 0x08000000, { 2835426, 2865207, 2740295, }, }, + { 0x09837F05, { 2802676, 2833793, 2702744, }, }, + { 0x0B504F33, { 2768187, 2800829, 2663094, }, }, + { 0x0D744FCD, { 2731806, 2766175, 2621155, }, }, + { 0x10000000, { 2693361, 2729675, 2576712, }, }, + { 0x1306FE0A, { 2652659, 2691153, 2529527, }, }, + { 0x16A09E66, { 2609480, 2650402, 2479324, }, }, + { 0x1AE89F99, { 2563575, 2607191, 2425793, }, }, + { 0x20000000, { 2514655, 2561246, 2368579, }, }, + { 0x260DFC14, { 2462394, 2512251, 2307272, }, }, + { 0x2D413CCD, { 2406412, 2459834, 2241403, }, }, + { 0x35D13F32, { 2346266, 2403554, 2170425, }, }, + { 0x40000000, { 2281441, 2342883, 2093706, }, }, + { 0x4C1BF828, { 2211332, 2277183, 2010504, }, }, + { 0x5A82799A, { 2135220, 2205675, 1919951, }, }, + { 0x6BA27E65, { 2052250, 2127391, 1821028, }, }, + { 0x80000000, { 1961395, 2041114, 1712536, }, }, + { 0x9837F051, { 1861415, 1945288, 1593066, }, }, + { 0xB504F333, { 1750800, 1837874, 1460986, }, }, + { 0xD744FCCA, { 1627706, 1716150, 1314437, }, }, + { 0xFFFFFFFF, { 1489879, 1576363, 1151415, }, }, +}; + +static void reset_lcd(struct s5p_panel_data *pdata) +{ + gpio_direction_output(pdata->gpio_rst, 1); + msleep(10); + + gpio_set_value(pdata->gpio_rst, 0); + msleep(10); + + gpio_set_value(pdata->gpio_rst, 1); + msleep(10); +} + +static int configure_mtp_gpios(struct s5p_panel_data *pdata, bool enable) +{ + int i; + int ret = 0; + if (enable) { + /* wrx and csx are already requested by the spi driver */ + ret = gpio_request(pdata->gpio_rdx, "tl2796_rdx"); + if (ret) + goto err_rdx; + ret = gpio_request(pdata->gpio_dcx, "tl2796_dcx"); + if (ret) + goto err_dcx; + ret = gpio_request(pdata->gpio_rst, "tl2796_rst"); + if (ret) + goto err_rst; + for (i = 0; i < 8; i++) { + ret = gpio_request(pdata->gpio_db[i], "tl2796_dbx"); + if (ret) + goto err_dbx; + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF0(i), 0); + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_UP); + gpio_set_value(S5PV210_GPF1(i), 0); + } + return 0; + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + reset_lcd(pdata); + + for (i = 7; i >= 0; i--) { + gpio_free(pdata->gpio_db[i]); +err_dbx: + ; + } + gpio_free(pdata->gpio_rst); +err_rst: + gpio_free(pdata->gpio_dcx); +err_dcx: + gpio_free(pdata->gpio_rdx); +err_rdx: + return ret; +} + +struct s5p_panel_data herring_panel_data = { + .seq_display_set = s6e63m0_SEQ_DISPLAY_SETTING, + .seq_etc_set = s6e63m0_SEQ_ETC_SETTING, + .standby_on = s6e63m0_SEQ_STANDBY_ON, + .standby_off = s6e63m0_SEQ_STANDBY_OFF, + .gpio_dcx = S5PV210_GPF0(0), /* H_SYNC pad */ + .gpio_rdx = S5PV210_GPF0(2), /* Enable */ + .gpio_csx = S5PV210_MP01(1), + .gpio_wrx = S5PV210_MP04(1), /* SCL pad */ + .gpio_rst = S5PV210_MP05(5), + .gpio_db = { + S5PV210_GPF0(4), + S5PV210_GPF0(5), + S5PV210_GPF0(6), + S5PV210_GPF0(7), + S5PV210_GPF1(0), + S5PV210_GPF1(1), + S5PV210_GPF1(2), + S5PV210_GPF1(3), + }, + .configure_mtp_gpios = configure_mtp_gpios, + .factory_v255_regs = { + 0x0b9, + 0x0b8, + 0x0fc, + }, +#ifdef CONFIG_TL2796_CONVERT_COLORS_RES + .color_adj = { + /* Convert from 8500K to D65, assuming: + * Rx 0.66950, Ry 0.33100 + * Gx 0.18800, Gy 0.74350 + * Bx 0.14142, By 0.04258 + */ + .mult = { + 2318372099U, + 2117262806U, + 1729744557U, + }, + .rshift = 31, + }, +#endif + + .gamma_adj_points = &gamma_adj_points, + .gamma_table = gamma_table, + .gamma_table_size = ARRAY_SIZE(gamma_table), +}; + +static const u16 brightness_setting_table[] = { + 0x051, 0x17f, + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_DISPLAY_ON[] = { + 0x029, + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_DISPLAY_OFF[] = { + 0x028, + SLEEPMSEC, 27, /* more than 25ms */ + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_SETTING[] = { + /* SET_PIXEL_FORMAT */ + 0x3A, + 0x177, /* 24 bpp */ + /* RGBCTRL */ + 0x3B, + /* RGB Mode1, DE is sampled at the rising edge of PCLK, + * P-rising edge, EP- low active, HSP-low active, VSP-low active */ + 0x107, + 0x10A, + 0x10E, + 0x10A, + 0x10A, + /* SET_HORIZONTAL_ADDRESS (Frame Memory Area define) */ + 0x2A, + 0x100, + 0x100, + 0x101, /* 480x800 */ + 0x1DF, /* 480x800 */ + /* SET_VERTICAL_ADDRESS (Frame Memory Area define) */ + 0x2B, + 0x100, + 0x100, + 0x103, /* 480x800 */ + 0x11F, /* 480x800 */ + /* SET_ADDRESS_MODE */ + 0x36, + 0x1D4, + SLEEPMSEC, 30, /* recommend by Sony-LCD, */ + /* SLPOUT */ + 0x11, + SLEEPMSEC, 155, /* recommend by Sony */ + /* WRCTRLD-1 */ + 0x55, + 0x100, /* CABC Off 1: UI-Mode, 2:Still-Mode, 3:Moving-Mode */ + /* WRCABCMB */ + 0x5E, + /* Minimum Brightness Value Setting 0:the lowest, 0xFF:the highest */ + 0x100, + /* WRCTRLD-2 */ + 0x53, + /* BCTRL(1)-PWM Output Enable, A(0)-LABC Off, + * DD(1)-Enable Dimming Function Only for CABC, + * BL(1)-turn on Backlight Control without dimming effect */ + 0x12C, + ENDDEF, 0x0000 +}; + +static const u16 nt35580_SEQ_SLEEP_IN[] = { + 0x010, + SLEEPMSEC, 155, /* more than 150ms */ + ENDDEF, 0x0000 +}; + +struct s5p_tft_panel_data herring_sony_panel_data = { + .seq_set = nt35580_SEQ_SETTING, + .sleep_in = nt35580_SEQ_SLEEP_IN, + .display_on = nt35580_SEQ_DISPLAY_ON, + .display_off = nt35580_SEQ_DISPLAY_OFF, + .brightness_set = brightness_setting_table, + .pwm_reg_offset = 1, +}; + +/* Hydis Panel (nt35510) */ +static const u16 nt35510_SEQ_SETTING[] = { + 0xFF, + 0x1AA, + 0x155, + 0x125, + 0x101, + + 0xF3, + 0x100, + 0x132, + 0x100, + 0x138, + 0x131, + 0x108, + 0x111, + 0x100, + + /* Enable CMD2_Page1 */ + 0xF0, + 0x155, + 0x1AA, + 0x152, + 0x108, + 0x100, + + 0xB0, + 0x104, + 0x10A, + 0x10E, + 0x109, + 0x104, + + 0xB1, + 0x1CC, + 0x104, + + 0x36, 0x102, + 0xB3, 0x100, + + /* AVDD */ + 0xB6, + 0x103, + + 0xB7, + 0x170, + 0x170, + + 0xB8, + 0x100, + 0x106, + 0x106, + 0x106, + + 0xBC, + 0x100, + 0x100, + 0x100, + + 0xBD, + 0x101, + 0x184, + 0x106, + 0x150, + 0x100, + + 0xCC, + 0x101, + 0x101, + 0x106, + + 0xF0, + 0x155, + 0x1AA, + 0x152, + 0x108, + 0x1101, + + 0xB0, + 0x104, + 0x10A, + 0x10E, + 0x109, + 0x104, + + 0xB1, + 0x105, + 0x105, + 0x105, + + 0xB2, + 0x103, + 0x103, + 0x103, + + 0xB8, + 0x125, + 0x125, + 0x125, + + 0xB3, + 0x100, + + 0xB9, + 0x134, + 0x134, + 0x134, + + /* VGH */ + 0xBF, + 0x101, + + 0xB5, + 0x109, + 0x109, + 0x109, + + /* VGL */ + 0xBA, + 0x124, + 0x124, + 0x124, + + 0xB4, + 0x124, + 0x124, + 0x124, + + 0xBC, + 0x100, + 0x168, + 0x100, + + 0xBD, + 0x100, + 0x17c, + 0x100, + + 0xBE, + 0x100, + 0x145, + + 0xD0, + 0x10A, + 0x114, + 0x10A, + 0x10E, + + 0xD1, + 0x100, + 0x137, + 0x100, + 0x161, + 0x100, + 0x192, + 0x100, + 0x1B4, + 0x100, + 0x1CF, + 0x100, + 0x1F6, + 0x101, + 0x12F, + 0x101, + 0x17F, + 0x101, + 0x197, + 0x101, + 0x1C0, + 0x101, + 0x1E5, + 0x102, + 0x125, + 0x102, + 0x15E, + 0x102, + 0x160, + 0x102, + 0x187, + 0x102, + 0x1BE, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD2, + 0x100, + 0x137, + 0x100, + 0x161, + 0x100, + 0x192, + 0x100, + 0x1B4, + 0x100, + 0x1CF, + 0x100, + 0x1F6, + 0x101, + 0x12F, + 0x101, + 0x17F, + 0x101, + 0x197, + 0x101, + 0x1C0, + 0x101, + 0x1E5, + 0x102, + 0x125, + 0x102, + 0x15E, + 0x102, + 0x160, + 0x102, + 0x187, + 0x102, + 0x1BE, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD3, + 0x100, + 0x137, + 0x100, + 0x161, + 0x100, + 0x192, + 0x100, + 0x1B4, + 0x100, + 0x1CF, + 0x100, + 0x1F6, + 0x101, + 0x12F, + 0x101, + 0x17F, + 0x101, + 0x197, + 0x101, + 0x1C0, + 0x101, + 0x1E5, + 0x102, + 0x125, + 0x102, + 0x15E, + 0x102, + 0x160, + 0x102, + 0x187, + 0x102, + 0x1BE, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD4, + 0x100, + 0x137, + 0x100, + 0x150, + 0x100, + 0x189, + 0x100, + 0x1A9, + 0x100, + 0x1C0, + 0x100, + 0x1F6, + 0x101, + 0x114, + 0x101, + 0x148, + 0x101, + 0x16B, + 0x101, + 0x1A7, + 0x101, + 0x1D3, + 0x102, + 0x117, + 0x102, + 0x14F, + 0x102, + 0x151, + 0x102, + 0x186, + 0x102, + 0x1BD, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD5, + 0x100, + 0x137, + 0x100, + 0x150, + 0x100, + 0x189, + 0x100, + 0x1A9, + 0x100, + 0x1C0, + 0x100, + 0x1F6, + 0x101, + 0x114, + 0x101, + 0x148, + 0x101, + 0x16B, + 0x101, + 0x1A7, + 0x101, + 0x1D3, + 0x102, + 0x117, + 0x102, + 0x14F, + 0x102, + 0x151, + 0x102, + 0x186, + 0x102, + 0x1BD, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xD6, + 0x100, + 0x137, + 0x100, + 0x150, + 0x100, + 0x189, + 0x100, + 0x1A9, + 0x100, + 0x1C0, + 0x100, + 0x1F6, + 0x101, + 0x114, + 0x101, + 0x148, + 0x101, + 0x16B, + 0x101, + 0x1A7, + 0x101, + 0x1D3, + 0x102, + 0x117, + 0x102, + 0x14F, + 0x102, + 0x151, + 0x102, + 0x186, + 0x102, + 0x1BD, + 0x102, + 0x1E2, + 0x103, + 0x10F, + 0x103, + 0x130, + 0x103, + 0x15C, + 0x103, + 0x177, + 0x103, + 0x194, + 0x103, + 0x19F, + 0x103, + 0x1AC, + 0x103, + 0x1BA, + 0x103, + 0x1F1, + + 0xF0, + 0x155, + 0x1AA, + 0x152, + 0x108, + 0x101, + + ENDDEF, 0x0000 +}; + +static const u16 nt35510_SEQ_DISPLAY_ON[] = { + 0x53, 0x12C, + 0x11, + SLEEPMSEC, 120, + 0x29, + ENDDEF, 0x0000 +}; + +static const u16 nt35510_SEQ_DISPLAY_OFF[] = { + 0x28, + SLEEPMSEC, 27, + ENDDEF, 0x0000 +}; +static const u16 nt35510_SEQ_SLEEP_IN[] = { + 0x10, + SLEEPMSEC, 155, /* more than 150ms */ + ENDDEF, 0x0000 +}; + +struct s5p_tft_panel_data herring_hydis_panel_data = { + .seq_set = nt35510_SEQ_SETTING, + .display_on = nt35510_SEQ_DISPLAY_ON, + .sleep_in = nt35510_SEQ_SLEEP_IN, + .display_off = nt35510_SEQ_DISPLAY_OFF, + .brightness_set = brightness_setting_table, + .pwm_reg_offset = 1, +}; + +/* hitachi panel (R61408) */ +static const u16 R61408_SEQ_SETTING[] = { + 0x36, 0x100, + 0x3A, 0x177, + + 0x11, + SLEEPMSEC, 150, + + 0xB0, 0x104, + 0xC1, 0x142, + 0x131, 0x104, + 0xB0, 0x103, + ENDDEF, 0x0000 +}; + +static const u16 R61408_SEQ_DISPLAY_ON[] = { + 0x29, + ENDDEF, 0x0000 +}; + +static const u16 R61408_SEQ_DISPLAY_OFF[] = { + 0xB0, 0x104, + 0xB1, 0x101, + SLEEPMSEC, 2, + ENDDEF, 0x0000 +}; +static const u16 R61408_SEQ_SLEEP_IN[] = { + 0x10, + SLEEPMSEC, 150, /* more than 150ms */ + ENDDEF, 0x0000 +}; + +static const u16 R61408_brightness_setting_table[] = { + 0xB0, 0x102, + 0xB9, 0x100, + 0x1F7, 0x102, + 0x108, + 0xB0, 0x103, + ENDDEF, 0x0000 +}; +struct s5p_tft_panel_data herring_hitachi_panel_data = { + .seq_set = R61408_SEQ_SETTING, + .display_on = R61408_SEQ_DISPLAY_ON, + .sleep_in = R61408_SEQ_SLEEP_IN, + .display_off = R61408_SEQ_DISPLAY_OFF, + .brightness_set = R61408_brightness_setting_table, + .pwm_reg_offset = 4, +}; + diff --git a/arch/arm/mach-s5pv210/herring-rfkill.c b/arch/arm/mach-s5pv210/herring-rfkill.c new file mode 100644 index 0000000..ce7408f --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-rfkill.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co., Ltd. + * + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Modified for Crespo on August, 2010 By Samsung Electronics Co. + * This is modified operate according to each status. + * + */ + +/* Control bluetooth power for Crespo platform */ + +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/rfkill.h> +#include <linux/delay.h> +#include <linux/types.h> +#include <linux/wakelock.h> +#include <linux/irq.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <mach/gpio.h> +#include <mach/gpio-herring.h> +#include <mach/hardware.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> +#include "herring.h" + +#define IRQ_BT_HOST_WAKE IRQ_EINT(21) + +static struct wake_lock rfkill_wake_lock; + +#ifndef GPIO_LEVEL_LOW +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#endif + +static struct rfkill *bt_rfk; +static const char bt_name[] = "bcm4329"; + +#ifdef CONFIG_CPU_DIDLE +static bool bt_running = false; + +bool bt_is_running(void) +{ + return bt_running; +} +EXPORT_SYMBOL(bt_is_running); +#endif + +static int bluetooth_set_power(void *data, enum rfkill_user_states state) +{ + int ret = 0; + int irq; + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + switch (state) { + + case RFKILL_USER_STATE_UNBLOCKED: + pr_debug("[BT] Device Powering ON\n"); + + s3c_setup_uart_cfg_gpio(0); + + if (gpio_is_valid(GPIO_WLAN_BT_EN)) + gpio_direction_output(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + if (gpio_is_valid(GPIO_BT_nRST)) + gpio_direction_output(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* Set GPIO_BT_WLAN_REG_ON high */ + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + /* + * FIXME sleep should be enabled disabled since the device is + * not booting if its enabled + */ + /* + * 100msec, delay between reg_on & rst. + * (bcm4329 powerup sequence) + */ + msleep(100); + + /* Set GPIO_BT_nRST high */ + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* + * 50msec, delay after bt rst + * (bcm4329 powerup sequence) + */ + msleep(50); + + ret = enable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] set wakeup src failed\n"); + + enable_irq(irq); + break; + + case RFKILL_USER_STATE_SOFT_BLOCKED: + pr_debug("[BT] Device Powering OFF\n"); + +#ifdef CONFIG_CPU_DIDLE + bt_running = false; +#endif + + ret = disable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] unset wakeup src failed\n"); + + disable_irq(irq); + wake_unlock(&rfkill_wake_lock); + + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + if (gpio_get_value(GPIO_WLAN_nRST) == 0) { + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + } + + break; + + default: + pr_err("[BT] Bad bluetooth rfkill state %d\n", state); + } + + return 0; +} + +irqreturn_t bt_host_wake_irq_handler(int irq, void *dev_id) +{ + pr_debug("[BT] bt_host_wake_irq_handler start\n"); + +#ifdef CONFIG_CPU_DIDLE + bt_running = true; +#endif + + if (gpio_get_value(GPIO_BT_HOST_WAKE)) + wake_lock(&rfkill_wake_lock); + else + wake_lock_timeout(&rfkill_wake_lock, HZ); + + return IRQ_HANDLED; +} + +static int bt_rfkill_set_block(void *data, bool blocked) +{ + unsigned int ret = 0; + + ret = bluetooth_set_power(data, blocked ? + RFKILL_USER_STATE_SOFT_BLOCKED : + RFKILL_USER_STATE_UNBLOCKED); + + return ret; +} + +static const struct rfkill_ops bt_rfkill_ops = { + .set_block = bt_rfkill_set_block, +}; + +static int __init herring_rfkill_probe(struct platform_device *pdev) +{ + int irq; + int ret; + + /* Initialize wake locks */ + wake_lock_init(&rfkill_wake_lock, WAKE_LOCK_SUSPEND, "bt_host_wake"); + + ret = gpio_request(GPIO_WLAN_BT_EN, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_WLAN_BT_EN!\n"); + goto err_req_gpio_wlan_bt_en; + } + + ret = gpio_request(GPIO_BT_nRST, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_BT_nRST!\n"); + goto err_req_gpio_bt_nrst; + } + + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + ret = request_irq(irq, bt_host_wake_irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "bt_host_wake_irq_handler", NULL); + + if (ret < 0) { + pr_err("[BT] Request_irq failed\n"); + goto err_req_irq; + } + + disable_irq(irq); + + bt_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &bt_rfkill_ops, NULL); + + if (!bt_rfk) { + pr_err("[BT] bt_rfk : rfkill_alloc is failed\n"); + ret = -ENOMEM; + goto err_alloc; + } + + rfkill_init_sw_state(bt_rfk, 0); + + pr_debug("[BT] rfkill_register(bt_rfk)\n"); + + ret = rfkill_register(bt_rfk); + if (ret) { + pr_debug("********ERROR IN REGISTERING THE RFKILL********\n"); + goto err_register; + } + + rfkill_set_sw_state(bt_rfk, 1); + bluetooth_set_power(NULL, RFKILL_USER_STATE_SOFT_BLOCKED); + + return ret; + + err_register: + rfkill_destroy(bt_rfk); + + err_alloc: + free_irq(irq, NULL); + + err_req_irq: + gpio_free(GPIO_BT_nRST); + + err_req_gpio_bt_nrst: + gpio_free(GPIO_WLAN_BT_EN); + + err_req_gpio_wlan_bt_en: + return ret; +} + +static struct platform_driver herring_device_rfkill = { + .probe = herring_rfkill_probe, + .driver = { + .name = "bt_rfkill", + .owner = THIS_MODULE, + }, +}; + +static int __init herring_rfkill_init(void) +{ + int rc = 0; + rc = platform_driver_register(&herring_device_rfkill); + + return rc; +} + +module_init(herring_rfkill_init); +MODULE_DESCRIPTION("herring rfkill"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/herring-touchkey-led.c b/arch/arm/mach-s5pv210/herring-touchkey-led.c new file mode 100644 index 0000000..47c26a5 --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-touchkey-led.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. All Rights Reserved. + * Author: Rom Lemarchand <rlemarchand@sta.samsung.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/earlysuspend.h> +#include <linux/bln.h> +#include <asm/mach-types.h> + +#ifdef CONFIG_BLD +#include <linux/bld.h> +#endif + +#include "herring.h" + +static int led_gpios[] = { 2, 3, 6, 7 }; + +static void herring_touchkey_led_onoff(int onoff) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) + gpio_direction_output(S5PV210_GPJ3(led_gpios[i]), !!onoff); +} + +#ifdef CONFIG_GENERIC_BLN +static void herring_touchkey_bln_enable(void) +{ + herring_touchkey_led_onoff(1); +} + +static void herring_touchkey_bln_disable(void) +{ + herring_touchkey_led_onoff(0); +} + +static struct bln_implementation herring_touchkey_bln = { + .enable = herring_touchkey_bln_enable, + .disable = herring_touchkey_bln_disable, +}; +#endif + +#ifdef CONFIG_BLD +static void herring_touchkey_bld_enable(void) +{ + herring_touchkey_led_onoff(1); +} + +static void herring_touchkey_bld_disable(void) +{ + herring_touchkey_led_onoff(0); +} + +static struct bld_implementation herring_touchkey_bld = + { + .enable = herring_touchkey_bld_enable, + .disable = herring_touchkey_bld_disable, + }; +#endif + +static void herring_touchkey_led_early_suspend(struct early_suspend *h) +{ + herring_touchkey_led_onoff(0); +} + +static void herring_touchkey_led_late_resume(struct early_suspend *h) +{ + herring_touchkey_led_onoff(1); +} + +static struct early_suspend early_suspend = { + .level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1, + .suspend = herring_touchkey_led_early_suspend, + .resume = herring_touchkey_led_late_resume, +}; + +static int __init herring_init_touchkey_led(void) +{ + int i; + int ret = 0; + u32 gpio; + + if (!machine_is_herring() || !herring_is_tft_dev()) + return 0; + + for (i = 0; i < ARRAY_SIZE(led_gpios); i++) { + gpio = S5PV210_GPJ3(led_gpios[i]); + ret = gpio_request(gpio, "touchkey led"); + if (ret) { + pr_err("Failed to request touchkey led gpio %d\n", i); + goto err_req; + } + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(gpio, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(gpio, S3C_GPIO_PULL_NONE); + } + + herring_touchkey_led_onoff(1); + + register_early_suspend(&early_suspend); + +#ifdef CONFIG_GENERIC_BLN + register_bln_implementation(&herring_touchkey_bln); +#endif +#ifdef CONFIG_BLD + register_bld_implementation(&herring_touchkey_bld); +#endif + + return 0; + +err_req: + while (--i >= 0) + gpio_free(S5PV210_GPJ3(led_gpios[i])); + return ret; +} + +device_initcall(herring_init_touchkey_led); diff --git a/arch/arm/mach-s5pv210/herring-vibrator.c b/arch/arm/mach-s5pv210/herring-vibrator.c new file mode 100644 index 0000000..82959f5 --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-vibrator.c @@ -0,0 +1,167 @@ +/* arch/arm/mach-s5pv210/herring-vibrator.c + * + * Copyright (C) 2010 Samsung Electronics Co. Ltd. All Rights Reserved. + * Author: Rom Lemarchand <rlemarchand@sta.samsung.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/hrtimer.h> +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/pwm.h> +#include <linux/wakelock.h> +#include <linux/mutex.h> +#include <linux/clk.h> +#include <linux/workqueue.h> + +#include <asm/mach-types.h> + +#include <../../../drivers/staging/android/timed_output.h> + +#include <mach/gpio-herring.h> + +#define GPD0_TOUT_1 2 << 4 + +#define PWM_PERIOD (89284 / 2) +#define PWM_DUTY (87280 / 2) +#define MAX_TIMEOUT 10000 /* 10s */ + +static struct vibrator { + struct wake_lock wklock; + struct pwm_device *pwm_dev; + struct hrtimer timer; + struct mutex lock; + struct work_struct work; +} vibdata; + +#ifdef CONFIG_CPU_DIDLE +static bool vibrator_running = false; + +bool vibrator_is_running(void) +{ + return vibrator_running; +} +EXPORT_SYMBOL(vibrator_is_running); +#endif + +static void herring_vibrator_off(void) +{ + pwm_disable(vibdata.pwm_dev); + gpio_direction_output(GPIO_VIBTONE_EN1, GPIO_LEVEL_LOW); + wake_unlock(&vibdata.wklock); + +#ifdef CONFIG_CPU_DIDLE + vibrator_running = false; +#endif +} + +static int herring_vibrator_get_time(struct timed_output_dev *dev) +{ + if (hrtimer_active(&vibdata.timer)) { + ktime_t r = hrtimer_get_remaining(&vibdata.timer); + return ktime_to_ms(r); + } + + return 0; +} + +static void herring_vibrator_enable(struct timed_output_dev *dev, int value) +{ + mutex_lock(&vibdata.lock); + + /* cancel previous timer and set GPIO according to value */ + hrtimer_cancel(&vibdata.timer); + cancel_work_sync(&vibdata.work); + if (value) { +#ifdef CONFIG_CPU_DIDLE + vibrator_running = true; +#endif + + wake_lock(&vibdata.wklock); + pwm_config(vibdata.pwm_dev, PWM_DUTY, PWM_PERIOD); + pwm_enable(vibdata.pwm_dev); + gpio_direction_output(GPIO_VIBTONE_EN1, GPIO_LEVEL_HIGH); + + if (value > 0) { + if (value > MAX_TIMEOUT) + value = MAX_TIMEOUT; + + hrtimer_start(&vibdata.timer, + ns_to_ktime((u64)value * NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + } else + herring_vibrator_off(); + + mutex_unlock(&vibdata.lock); +} + +static struct timed_output_dev to_dev = { + .name = "vibrator", + .get_time = herring_vibrator_get_time, + .enable = herring_vibrator_enable, +}; + +static enum hrtimer_restart herring_vibrator_timer_func(struct hrtimer *timer) +{ + schedule_work(&vibdata.work); + return HRTIMER_NORESTART; +} + +static void herring_vibrator_work(struct work_struct *work) +{ + herring_vibrator_off(); +} + +static int __init herring_init_vibrator(void) +{ + int ret = 0; + +#ifdef CONFIG_MACH_HERRING + if (!machine_is_herring()) + return 0; +#endif + hrtimer_init(&vibdata.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + vibdata.timer.function = herring_vibrator_timer_func; + INIT_WORK(&vibdata.work, herring_vibrator_work); + + ret = gpio_request(GPIO_VIBTONE_EN1, "vibrator-en"); + if (ret < 0) + return ret; + + s3c_gpio_cfgpin(GPIO_VIBTONE_PWM, GPD0_TOUT_1); + + vibdata.pwm_dev = pwm_request(1, "vibrator-pwm"); + if (IS_ERR(vibdata.pwm_dev)) { + ret = PTR_ERR(vibdata.pwm_dev); + goto err_pwm_req; + } + + wake_lock_init(&vibdata.wklock, WAKE_LOCK_SUSPEND, "vibrator"); + mutex_init(&vibdata.lock); + + ret = timed_output_dev_register(&to_dev); + if (ret < 0) + goto err_to_dev_reg; + + return 0; + +err_to_dev_reg: + mutex_destroy(&vibdata.lock); + wake_lock_destroy(&vibdata.wklock); + pwm_free(vibdata.pwm_dev); +err_pwm_req: + gpio_free(GPIO_VIBTONE_EN1); + return ret; +} + +device_initcall(herring_init_vibrator); diff --git a/arch/arm/mach-s5pv210/herring-watchdog.c b/arch/arm/mach-s5pv210/herring-watchdog.c new file mode 100644 index 0000000..7ff9fee --- /dev/null +++ b/arch/arm/mach-s5pv210/herring-watchdog.c @@ -0,0 +1,111 @@ +/* herring-watchdog.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <plat/regs-watchdog.h> +#include <mach/map.h> + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/cpufreq.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/workqueue.h> +#include <linux/io.h> + +/* reset timeout in PCLK/256/128 (~2048:1s) */ +static unsigned watchdog_reset = (30 * 2048); + +/* pet timeout in jiffies */ +static unsigned watchdog_pet = (10 * HZ); + +static struct workqueue_struct *watchdog_wq; +static void watchdog_workfunc(struct work_struct *work); +static DECLARE_DELAYED_WORK(watchdog_work, watchdog_workfunc); + +static void watchdog_workfunc(struct work_struct *work) +{ + writel(watchdog_reset, S3C2410_WTCNT); + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_start(void) +{ + unsigned int val; + + /* set to PCLK / 256 / 128 */ + val = S3C2410_WTCON_DIV128; + val |= S3C2410_WTCON_PRESCALE(255); + writel(val, S3C2410_WTCON); + + /* program initial count */ + writel(watchdog_reset, S3C2410_WTCNT); + writel(watchdog_reset, S3C2410_WTDAT); + + /* start timer */ + val |= S3C2410_WTCON_RSTEN | S3C2410_WTCON_ENABLE; + writel(val, S3C2410_WTCON); + + /* make sure we're ready to pet the dog */ + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_stop(void) +{ + writel(0, S3C2410_WTCON); +} + +static int watchdog_probe(struct platform_device *pdev) +{ + watchdog_wq = alloc_workqueue("pet_watchdog", + WQ_UNBOUND | WQ_HIGHPRI, 1); + watchdog_start(); + return 0; +} + +static int watchdog_suspend(struct device *dev) +{ + watchdog_stop(); + return 0; +} + +static int watchdog_resume(struct device *dev) +{ + watchdog_start(); + return 0; +} + +static struct dev_pm_ops watchdog_pm_ops = { + .suspend_noirq = watchdog_suspend, + .resume_noirq = watchdog_resume, +}; + +static struct platform_driver watchdog_driver = { + .probe = watchdog_probe, + .driver = { + .owner = THIS_MODULE, + .name = "watchdog", + .pm = &watchdog_pm_ops, + }, +}; + +static int __init watchdog_init(void) +{ + return platform_driver_register(&watchdog_driver); +} + +module_init(watchdog_init); diff --git a/arch/arm/mach-s5pv210/herring.h b/arch/arm/mach-s5pv210/herring.h new file mode 100755 index 0000000..9f8622e --- /dev/null +++ b/arch/arm/mach-s5pv210/herring.h @@ -0,0 +1,34 @@ +/* + * arch/arm/mach-s5pv210/herring.h + */ + +#include <asm/system.h> +#include <asm/mach-types.h> + +#ifndef __HERRING_H__ +#define __HERRING_H__ + +struct uart_port; + +void herring_bt_uart_wake_peer(struct uart_port *port); +extern void s3c_setup_uart_cfg_gpio(unsigned char port); + +#ifdef CONFIG_MACH_HERRING +# define herring_is_cdma_wimax_dev() (machine_is_herring() && \ + ((system_rev & 0xFFF0) == 0x20)) +# define herring_is_cdma_wimax_rev(n) (herring_is_cdma_wimax_dev() && \ + (system_rev & 0xF) == ((n) & 0xF)) +# define herring_is_cdma_wimax_rev0() herring_is_cdma_wimax_rev(0) +# define herring_is_tft_dev() (machine_is_herring() && (system_rev >= 0x30)) +#else +# define herring_is_cdma_wimax_dev() (0) +# define herring_is_cdma_wimax_rev0() (0) +# define herring_is_cdma_wimax_rev(n) (0) +# define herring_is_tft_dev() (0) +#endif + +extern struct s5p_panel_data herring_panel_data; +extern struct s5p_tft_panel_data herring_sony_panel_data; +extern struct s5p_tft_panel_data herring_hydis_panel_data; +extern struct s5p_tft_panel_data herring_hitachi_panel_data; +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/adc.h b/arch/arm/mach-s5pv210/include/mach/adc.h new file mode 100644 index 0000000..a0f703a --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/adc.h @@ -0,0 +1,36 @@ +/* arch/arm/plat-s3c/include/plat/adc.h + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simnte.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_ADC_H +#define __ASM_PLAT_ADC_H __FILE__ + +struct s3c_adc_request { + /* for linked list */ + struct list_head *list; + /* after finish ADC sampling, s3c_adc_request function call this function with three parameter */ + void (*callback)(int channel, unsigned long int param, unsigned short sample); + /* for private data */ + unsigned long int param; + /* selected channel for ADC sampling */ + int channel; +}; + +struct s3c_adc_mach_info { + /* if you need to use some platform data, add in here*/ + int delay; + int presc; + int resolution; +}; + +extern int s3c_adc_get_adc_data(int channel); +void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd); + +#endif /* __ASM_PLAT_ADC_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/battery.h b/arch/arm/mach-s5pv210/include/mach/battery.h new file mode 100644 index 0000000..b5f7339 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/battery.h @@ -0,0 +1,13 @@ +#ifndef __BATTERY_H_ +#define __BATTERY_H_ + +typedef enum +{ + PM_CHARGER_NULL, + PM_CHARGER_TA, + PM_CHARGER_USB_CABLE, //after enumeration + PM_CHARGER_USB_INSERT,// when usb is connected. + PM_CHARGER_DEFAULT +} charging_device_type; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h new file mode 100644 index 0000000..8274a01 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h @@ -0,0 +1,31 @@ +/* arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * S5PV210/S5PC110 CPU frequency scaling support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_CPU_FREQ_H +#define __ASM_ARCH_CPU_FREQ_H + +#include <linux/cpufreq.h> + +/* For cpu-freq driver */ +struct s5pv210_cpufreq_voltage { + unsigned int freq; /* kHz */ + unsigned long varm; /* uV */ + unsigned long vint; /* uV */ +}; + +struct s5pv210_cpufreq_data { + struct s5pv210_cpufreq_voltage *volt; + unsigned int size; +}; + +extern void s5pv210_cpufreq_set_platdata(struct s5pv210_cpufreq_data *pdata); + +#endif /* __ASM_ARCH_CPU_FREQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/cpuidle.h b/arch/arm/mach-s5pv210/include/mach/cpuidle.h new file mode 100644 index 0000000..7454ae4 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/cpuidle.h @@ -0,0 +1,16 @@ +/* arch/arm/mach-s5pv210/include/mach/cpuidle.h + * + * Copyright 2010 Samsung Electronics + * Jaecheol Lee <jc.lee@samsung> + * + * S5PV210 - CPUIDLE support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern int s5pv210_didle_save(unsigned long *saveblk); +extern void s5pv210_didle_resume(void); +extern void i2sdma_getpos(dma_addr_t *src); +extern unsigned int get_rtc_cnt(void); diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-herring.h b/arch/arm/mach-s5pv210/include/mach/gpio-herring.h new file mode 100644 index 0000000..b55d0f0 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/gpio-herring.h @@ -0,0 +1,603 @@ +#ifndef __GPIO_HERRING_H_ +#define __GPIO_HERRING_H_ + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 + +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 + +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 + +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 + +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 + +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 + +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 + +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 + +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 + +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 + +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) + +#define GPIO_MSENSE_nRST S5PV210_GPB(1) + +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) + +#define GPIO_BT_nRST S5PV210_GPB(3) + +#define GPIO_BOOT_MODE S5PV210_GPB(4) + +#define GPIO_WLAN_BT_EN S5PV210_GPB(5) + +#define GPIO_GPB6 S5PV210_GPB(6) + +#define GPIO_GPB7 S5PV210_GPB(7) + +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 + +#define GPIO_GPC01 S5PV210_GPC0(1) + +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 + +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 + +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 + +#define GPIO_WIMAX_PM_SDA S5PV210_GPC1(0) + +#define GPIO_WIMAX_I2C_CON S5PV210_GPC1(1) + +#define GPIO_WIMAX_PM_SCL S5PV210_GPC1(2) + +#define GPIO_GPC13 S5PV210_GPC1(3) + +#define GPIO_GPC14 S5PV210_GPC1(4) + +#define GPIO_WIMAX_DBGEN_28V S5PV210_GPD0(0) + +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) + +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) + +#define GPIO_WIMAX_RESET_N S5PV210_GPD0(3) + +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 + +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 + +#define GYRO_SDA_28V S5PV210_GPD1(2) +#define GYRO_SCL_28V S5PV210_GPD1(3) + +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 + +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 + +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 + +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 + +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 + +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 + +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 + +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 + +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 + +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 + +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 + +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 + +#define GPIO_GPE14 S5PV210_GPE1(4) + +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF 2 + +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF 2 + +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF 2 + +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF 2 + +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF 2 + +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF 2 + +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF 2 + +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF 2 + +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF 2 + +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF 2 + +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF 2 + +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF 2 + +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF 2 + +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF 2 + +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF 2 + +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF 2 + +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF 2 + +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF 2 + +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF 2 + +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF 2 + +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF 2 + +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF 2 + +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF 2 + +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF 2 + +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF 2 + +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF 2 + +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF 2 + +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF 2 + +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) + +#define GPIO_GPF35 S5PV210_GPF3(5) + +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 + +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#define GPIO_ALS_SCL_28V S5PV210_GPG0(2) + +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 + +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 + +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 + +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 + +#define GPIO_GPS_nRST S5PV210_GPG1(0) + +#define GPIO_GPS_PWR_EN S5PV210_GPG1(1) + +#define GPIO_WLAN_RST S5PV210_GPG1(2) + +#define GPIO_NAND_D4 S5PV210_GPG1(3) +#define GPIO_NAND_D4_AF 3 + +#define GPIO_NAND_D5 S5PV210_GPG1(4) +#define GPIO_NAND_D5_AF 3 + +#define GPIO_NAND_D6 S5PV210_GPG1(5) +#define GPIO_NAND_D6_AF 3 + +#define GPIO_NAND_D7 S5PV210_GPG1(6) +#define GPIO_NAND_D7_AF 3 + +#define GPIO_WIMAX_SDIO_CLK S5PV210_GPG2(0) + +#define GPIO_WIMAX_SDIO_CMD S5PV210_GPG2(1) + +#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) + +#define GPIO_WIMAX_SDIO_D0 S5PV210_GPG2(3) + +#define GPIO_WIMAX_SDIO_D1 S5PV210_GPG2(4) + +#define GPIO_WIMAX_SDIO_D2 S5PV210_GPG2(5) + +#define GPIO_WIMAX_SDIO_D3 S5PV210_GPG2(6) + +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_nRST S5PV210_GPG3(2) +#define GPIO_WLAN_nRST_AF 1 + +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) + +#define GPIO_ACC_INT S5PV210_GPH0(1) + +#define GPIO_PS_VOUT S5PV210_GPH0(2) +#define GPIO_PS_VOUT_AF 0xFF + +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) + +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) + +#define GPIO_BUCK_2_EN S5PV210_GPH0(5) +#define GPIO_DET_35 S5PV210_GPH0(6) +#define GPIO_DET_35_AF 0xFF + +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +#define GPIO_WIMAX_EN S5PV210_GPH1(0) + +#define GPIO_PDA_ACTIVE S5PV210_GPH1(1) + +#define GPIO_WIMAX_WAKEUP S5PV210_GPH1(2) + +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF + +#define GPIO_GPH14 S5PV210_GPH1(4) + +#define GPIO_GPH15 S5PV210_GPH1(5) + +#define GPIO_GPH16 S5PV210_GPH1(6) + +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) +#define GPIO_PHONE_ACTIVE_AF 2 + +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 +#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_KBC1_AF 3 +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 + +#define GPIO_BT_WAKE S5PV210_GPH2(2) +#define GPIO_WLAN_WAKE S5PV210_GPH2(3) +#define GPIO_WLAN_WAKE_AF 1 + +#define GPIO_KBC_DATA (GPIO_KBC2 + 0x04) + +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF + +#define GPIO_nPOWER S5PV210_GPH2(6) + +#define GPIO_JACK_nINT S5PV210_GPH2(7) + +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPH3(0) + +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 + +#define GPIO_KBR2 S5PV210_GPH3(2) +#define GPIO_KBR2_AF 3 + +#define GPIO_MSENSE_IRQ S5PV210_GPH3(3) + +#define GPIO_KBR_DATA (GPIO_KBR1 + 0x04) + +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) + +/* EAR_SEN_END_OPEN */ +#define GPIO_OK_KEY S5PV210_GPH3(5) + +#define GPIO_EAR_SEND_END S5PV210_GPH3(6) +#define GPIO_EAR_SEND_END_AF 0xFF +#define GPIO_CP_RST S5PV210_GPH3(7) + +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 + +#define GPIO_GPI1 S5PV210_GPI(1) + +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 + +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 + +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 + +#define GPIO_GPI5 S5PV210_GPI(5) + +#define GPIO_GPI6 S5PV210_GPI(6) + +#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) +#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) + +#define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) +#define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) +#define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) + +#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) + +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) + +#define GPIO_CAM_FLASH_EN_SET S5PV210_GPJ1(0) + +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) + +#define GPIO_USB_HS_SEL S5PV210_GPJ2(0) +#define GPIO_PHONE_ON S5PV210_GPJ2(1) + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_UART_SEL1 S5PV210_GPJ2(4) + +#define GPIO_FLASH_EN S5PV210_GPJ1(2) +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#define GPIO_PS_ON S5PV210_GPJ1(4) + +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) + +#define GPIO_OLED_DET S5PV210_GPJ2(2) + +#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_FM_INT S5PV210_GPJ2(4) +#define GPIO_FM_RST S5PV210_GPJ2(5) +#define GPIO_TV_OUT_SEL S5PV210_GPJ2(6) + +#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) + +#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) +#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 +#define GPIO_EAR_ADC_SEL S5PV210_GPJ3(3) +#define GPIO_EAR_ADC_SEL_AF 1 + +#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) + +#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) + +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) + +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) + +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF 0xFF +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) + +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) + +#define GPIO_EAR_MICBIAS_EN S5PV210_GPJ4(4) + +#define GPIO_MP010 S5PV210_MP01(0) + +#define GPIO_DISPLAY_CS S5PV210_MP01(1) + +#define GPIO_WIMAX_CON0 S5PV210_MP01(2) + +#define GPIO_OLED_ID S5PV210_MP01(3) + +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 + +#define GPIO_DIC_ID S5PV210_MP01(5) + +#define GPIO_MP016 S5PV210_MP01(6) + +#define GPIO_MP017 S5PV210_MP01(7) + +#define GPIO_MP020 S5PV210_MP02(0) + +#define GPIO_MP021 S5PV210_MP02(1) + +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) + +#define GPIO_MP023 S5PV210_MP02(3) + +#define GPIO_MP030 S5PV210_MP03(0) + +#define GPIO_MP031 S5PV210_MP03(1) + +#define GPIO_MP032 S5PV210_MP03(2) + +#define GPIO_MP033 S5PV210_MP03(3) + +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) + +#define GPIO_CP_nRST S5PV210_MP03(5) + +#define GPIO_MP036 S5PV210_MP03(6) + +#define GPIO_PCM_SEL S5PV210_MP03(7) + +#define GPIO_USB_SEL S5PV210_MP04(0) + +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) + +#define GPIO_WIMAX_IF_MODE0 S5PV210_MP04(2) + +#define GPIO_DISPLAY_SI S5PV210_MP04(3) + +#define GPIO_MP044 S5PV210_MP04(4) + +#define GPIO_LVDS_RST S5PV210_MP04(5) + +#define GPIO_GPS_CLK_EN S5PV210_MP04(6) + +#define GPIO_WIMAX_CON1 S5PV210_MP04(7) + +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) + +#define GPIO_AP_SCL_18V S5PV210_MP05(2) + +#define GPIO_AP_SDA_18V S5PV210_MP05(3) + +#define GPIO_WIMAX_IF_MODE1 S5PV210_MP05(4) + +#define GPIO_MLCD_RST S5PV210_MP05(5) + +#define GPIO_WIMAX_CON2 S5PV210_MP05(6) + +#define GPIO_UART_SEL S5PV210_MP05(7) + +#define GPOI_WIMAX_WAKEUP S5PV210_MP06(5) + +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +#define NFC_SCL_18V S5PV210_MP04(4) +#define NFC_SDA_18V S5PV210_MP04(5) +#define NFC_IRQ S5PV210_GPH1(4) +#define NFC_EN S5PV210_GPH1(5) +#define NFC_FIRM S5PV210_GPH1(6) + +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +#define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#define GPIO_TOUCH_INT_AF 0xFF + +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 + +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 + +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 + +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 + +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#endif +/* end of __GPIO_HERRING_H_ */ + diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index a5a1e33..16b38f1 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -54,6 +54,34 @@ #define S5PV210_GPIO_MP03_NR (8) #define S5PV210_GPIO_MP04_NR (8) #define S5PV210_GPIO_MP05_NR (8) +#define S5PV210_GPIO_MP06_NR (8) +#define S5PV210_GPIO_MP07_NR (8) + +#define S5PV210_GPIO_MP10_NR (8) +#define S5PV210_GPIO_MP11_NR (8) +#define S5PV210_GPIO_MP12_NR (8) +#define S5PV210_GPIO_MP13_NR (8) +#define S5PV210_GPIO_MP14_NR (8) +#define S5PV210_GPIO_MP15_NR (8) +#define S5PV210_GPIO_MP16_NR (8) +#define S5PV210_GPIO_MP17_NR (8) +#define S5PV210_GPIO_MP18_NR (7) + +#define S5PV210_GPIO_MP20_NR (8) +#define S5PV210_GPIO_MP21_NR (8) +#define S5PV210_GPIO_MP22_NR (8) +#define S5PV210_GPIO_MP23_NR (8) +#define S5PV210_GPIO_MP24_NR (8) +#define S5PV210_GPIO_MP25_NR (8) +#define S5PV210_GPIO_MP26_NR (8) +#define S5PV210_GPIO_MP27_NR (8) +#define S5PV210_GPIO_MP28_NR (7) + +#define S5PV210_GPIO_ETC0_NR (6) +#define S5PV210_GPIO_ETC1_NR (8) +#define S5PV210_GPIO_ETC2_NR (8) +#define S5PV210_GPIO_ETC4_NR (6) + /* GPIO bank numbers */ @@ -98,6 +126,30 @@ enum s5p_gpio_number { S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03), S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04), + S5PV210_GPIO_MP06_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP05), + S5PV210_GPIO_MP07_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP06), + S5PV210_GPIO_MP10_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP07), + S5PV210_GPIO_MP11_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP10), + S5PV210_GPIO_MP12_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP11), + S5PV210_GPIO_MP13_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP12), + S5PV210_GPIO_MP14_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP13), + S5PV210_GPIO_MP15_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP14), + S5PV210_GPIO_MP16_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP15), + S5PV210_GPIO_MP17_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP16), + S5PV210_GPIO_MP18_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP17), + S5PV210_GPIO_MP20_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP18), + S5PV210_GPIO_MP21_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP20), + S5PV210_GPIO_MP22_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP21), + S5PV210_GPIO_MP23_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP22), + S5PV210_GPIO_MP24_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP23), + S5PV210_GPIO_MP25_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP24), + S5PV210_GPIO_MP26_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP25), + S5PV210_GPIO_MP27_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP26), + S5PV210_GPIO_MP28_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP27), + S5PV210_GPIO_ETC0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP28), + S5PV210_GPIO_ETC1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC0), + S5PV210_GPIO_ETC2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC1), + S5PV210_GPIO_ETC4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_ETC2), }; /* S5PV210 GPIO number definitions */ @@ -133,15 +185,69 @@ enum s5p_gpio_number { #define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) #define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr)) #define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr)) +#define S5PV210_MP06(_nr) (S5PV210_GPIO_MP06_START + (_nr)) +#define S5PV210_MP07(_nr) (S5PV210_GPIO_MP07_START + (_nr)) +#define S5PV210_MP10(_nr) (S5PV210_GPIO_MP10_START + (_nr)) +#define S5PV210_MP11(_nr) (S5PV210_GPIO_MP11_START + (_nr)) +#define S5PV210_MP12(_nr) (S5PV210_GPIO_MP12_START + (_nr)) +#define S5PV210_MP13(_nr) (S5PV210_GPIO_MP13_START + (_nr)) +#define S5PV210_MP14(_nr) (S5PV210_GPIO_MP14_START + (_nr)) +#define S5PV210_MP15(_nr) (S5PV210_GPIO_MP15_START + (_nr)) +#define S5PV210_MP16(_nr) (S5PV210_GPIO_MP16_START + (_nr)) +#define S5PV210_MP17(_nr) (S5PV210_GPIO_MP17_START + (_nr)) +#define S5PV210_MP18(_nr) (S5PV210_GPIO_MP18_START + (_nr)) +#define S5PV210_MP20(_nr) (S5PV210_GPIO_MP20_START + (_nr)) +#define S5PV210_MP21(_nr) (S5PV210_GPIO_MP21_START + (_nr)) +#define S5PV210_MP22(_nr) (S5PV210_GPIO_MP22_START + (_nr)) +#define S5PV210_MP23(_nr) (S5PV210_GPIO_MP23_START + (_nr)) +#define S5PV210_MP24(_nr) (S5PV210_GPIO_MP24_START + (_nr)) +#define S5PV210_MP25(_nr) (S5PV210_GPIO_MP25_START + (_nr)) +#define S5PV210_MP26(_nr) (S5PV210_GPIO_MP26_START + (_nr)) +#define S5PV210_MP27(_nr) (S5PV210_GPIO_MP27_START + (_nr)) +#define S5PV210_MP28(_nr) (S5PV210_GPIO_MP28_START + (_nr)) +#define S5PV210_ETC0(_nr) (S5PV210_GPIO_ETC0_START + (_nr)) +#define S5PV210_ETC1(_nr) (S5PV210_GPIO_ETC1_START + (_nr)) +#define S5PV210_ETC2(_nr) (S5PV210_GPIO_ETC2_START + (_nr)) +#define S5PV210_ETC4(_nr) (S5PV210_GPIO_ETC4_START + (_nr)) + +/* Define EXT INT GPIO */ +#define S5P_EXT_INT0(x) S5PV210_GPH0(x) +#define S5P_EXT_INT1(x) S5PV210_GPH1(x) +#define S5P_EXT_INT2(x) S5PV210_GPH2(x) +#define S5P_EXT_INT3(x) S5PV210_GPH3(x) /* the end of the S5PV210 specific gpios */ -#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1) +#define S5PV210_GPIO_END (S5PV210_ETC4(S5PV210_GPIO_ETC4_NR) + 1) #define S3C_GPIO_END S5PV210_GPIO_END -/* define the number of gpios we need to the one after the MP05() range */ -#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \ +/* define the number of gpios we need to the one after the GPJ4() range */ +#define ARCH_NR_GPIOS (S5PV210_ETC4(S5PV210_GPIO_ETC4_NR) + \ CONFIG_SAMSUNG_GPIO_EXTRA + 1) #include <asm-generic/gpio.h> +#include <plat/gpio-cfg.h> + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int to); +extern s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin); + +#define S3C_GPIO_SLP_OUT0 ((__force s3c_gpio_pull_t)0x00) +#define S3C_GPIO_SLP_OUT1 ((__force s3c_gpio_pull_t)0x01) +#define S3C_GPIO_SLP_INPUT ((__force s3c_gpio_pull_t)0x02) +#define S3C_GPIO_SLP_PREV ((__force s3c_gpio_pull_t)0x03) + +extern int s3c_gpio_set_drvstrength(unsigned int pin, unsigned int config); +extern int s3c_gpio_set_slewrate(unsigned int pin, unsigned int config); + +#define S3C_GPIO_DRVSTR_1X (0) +#define S3C_GPIO_DRVSTR_2X (1) +#define S3C_GPIO_DRVSTR_3X (2) +#define S3C_GPIO_DRVSTR_4X (3) + +#define S3C_GPIO_SLEWRATE_FAST (0) +#define S3C_GPIO_SLEWRATE_SLOW (1) + +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, s3c_gpio_pull_t pull); +extern int s5pv210_gpiolib_init(void); + #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index b9f9ec3..b747128 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -17,6 +17,22 @@ /* VIC0: System, DMA, Timer */ +#define IRQ_EINT0 S5P_IRQ_VIC0(0) +#define IRQ_EINT1 S5P_IRQ_VIC0(1) +#define IRQ_EINT2 S5P_IRQ_VIC0(2) +#define IRQ_EINT3 S5P_IRQ_VIC0(3) +#define IRQ_EINT4 S5P_IRQ_VIC0(4) +#define IRQ_EINT5 S5P_IRQ_VIC0(5) +#define IRQ_EINT6 S5P_IRQ_VIC0(6) +#define IRQ_EINT7 S5P_IRQ_VIC0(7) +#define IRQ_EINT8 S5P_IRQ_VIC0(8) +#define IRQ_EINT9 S5P_IRQ_VIC0(9) +#define IRQ_EINT10 S5P_IRQ_VIC0(10) +#define IRQ_EINT11 S5P_IRQ_VIC0(11) +#define IRQ_EINT12 S5P_IRQ_VIC0(12) +#define IRQ_EINT13 S5P_IRQ_VIC0(13) +#define IRQ_EINT14 S5P_IRQ_VIC0(14) +#define IRQ_EINT15 S5P_IRQ_VIC0(15) #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) #define IRQ_BATF S5P_IRQ_VIC0(17) #define IRQ_MDMA S5P_IRQ_VIC0(18) @@ -116,17 +132,19 @@ #define IRQ_MDNIE1 S5P_IRQ_VIC3(6) #define IRQ_MDNIE2 S5P_IRQ_VIC3(7) #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) +#define IRQ_ADC1 S5P_IRQ_VIC3(9) +#define IRQ_PENDN1 S5P_IRQ_VIC3(10) #define IRQ_VIC_END S5P_IRQ_VIC3(31) #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) +#define S5P_IRQ_EINT_BASE S5P_EINT_BASE2 /* GPIO interrupt */ #define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) #define S5P_GPIOINT_GROUP_MAXNR 22 -/* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) +#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) /* Compatibility */ #define IRQ_LCD_FIFO IRQ_LCD0 @@ -134,4 +152,73 @@ #define IRQ_LCD_SYSTEM IRQ_LCD2 #define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (8) /* A0 */ +#define IRQ_EINT_GROUP2_NR (4) /* A1 */ +#define IRQ_EINT_GROUP3_NR (8) /* B */ +#define IRQ_EINT_GROUP4_NR (5) /* C0 */ +#define IRQ_EINT_GROUP5_NR (5) /* C1 */ +#define IRQ_EINT_GROUP6_NR (4) /* D0 */ +#define IRQ_EINT_GROUP7_NR (6) /* D1 */ +#define IRQ_EINT_GROUP8_NR (8) /* E0 */ +#define IRQ_EINT_GROUP9_NR (5) /* E1 */ +#define IRQ_EINT_GROUP10_NR (8) /* F0 */ +#define IRQ_EINT_GROUP11_NR (8) /* F1 */ +#define IRQ_EINT_GROUP12_NR (8) /* F2 */ +#define IRQ_EINT_GROUP13_NR (6) /* F3 */ +#define IRQ_EINT_GROUP14_NR (7) /* G0 */ +#define IRQ_EINT_GROUP15_NR (7) /* G1 */ +#define IRQ_EINT_GROUP16_NR (7) /* G2 */ +#define IRQ_EINT_GROUP17_NR (7) /* G3 */ +#define IRQ_EINT_GROUP18_NR (8) /* J0 */ +#define IRQ_EINT_GROUP19_NR (6) /* J1 */ +#define IRQ_EINT_GROUP20_NR (8) /* J2 */ +#define IRQ_EINT_GROUP21_NR (8) /* J3 */ +#define IRQ_EINT_GROUP22_NR (5) /* J4 */ + +#define IRQ_EINT_GROUP_BASE S5P_EINT(31 + 1) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) +#define IRQ_EINT_GROUP10_BASE (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR) +#define IRQ_EINT_GROUP11_BASE (IRQ_EINT_GROUP10_BASE + IRQ_EINT_GROUP10_NR) +#define IRQ_EINT_GROUP12_BASE (IRQ_EINT_GROUP11_BASE + IRQ_EINT_GROUP11_NR) +#define IRQ_EINT_GROUP13_BASE (IRQ_EINT_GROUP12_BASE + IRQ_EINT_GROUP12_NR) +#define IRQ_EINT_GROUP14_BASE (IRQ_EINT_GROUP13_BASE + IRQ_EINT_GROUP13_NR) +#define IRQ_EINT_GROUP15_BASE (IRQ_EINT_GROUP14_BASE + IRQ_EINT_GROUP14_NR) +#define IRQ_EINT_GROUP16_BASE (IRQ_EINT_GROUP15_BASE + IRQ_EINT_GROUP15_NR) +#define IRQ_EINT_GROUP17_BASE (IRQ_EINT_GROUP16_BASE + IRQ_EINT_GROUP16_NR) +#define IRQ_EINT_GROUP18_BASE (IRQ_EINT_GROUP17_BASE + IRQ_EINT_GROUP17_NR) +#define IRQ_EINT_GROUP19_BASE (IRQ_EINT_GROUP18_BASE + IRQ_EINT_GROUP18_NR) +#define IRQ_EINT_GROUP20_BASE (IRQ_EINT_GROUP19_BASE + IRQ_EINT_GROUP19_NR) +#define IRQ_EINT_GROUP21_BASE (IRQ_EINT_GROUP20_BASE + IRQ_EINT_GROUP20_NR) +#define IRQ_EINT_GROUP22_BASE (IRQ_EINT_GROUP21_BASE + IRQ_EINT_GROUP21_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) + +/* Set the default NR_IRQS */ +//#define NR_IRQS (IRQ_EINT(31) + 1) +#define NR_IRQS (IRQ_EINT_GROUP22_BASE + IRQ_EINT_GROUP22_NR + 1) + +#define HALL_SENSOR_IRQ IRQ_EINT3 + +#define FIQ_START 0 + #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 1dd5883..704e192 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -16,7 +16,11 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> -#define S5PV210_PA_SDRAM 0x20000000 +#if defined(CONFIG_MACH_SMDKV210) +#define S5PV210_PA_SDRAM (0x20000000) +#else +#define S5PV210_PA_SDRAM (0x30000000) +#endif #define S5PV210_PA_SROM_BANK5 0xA8000000 @@ -53,6 +57,9 @@ #define S5PV210_PA_WATCHDOG 0xE2700000 #define S5PV210_PA_RTC 0xE2800000 +#define S5PV210_VA_RTC S3C_ADDR(0x00c00000) +#define S5P_VA_RTC S5PV210_VA_RTC + #define S5PV210_PA_UART 0xE2900000 #define S5PV210_PA_SROMC 0xE8000000 @@ -61,9 +68,27 @@ #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) +/* usb */ +#define S5PV210_PA_OTG (0xEC000000) +#define S5PV210_SZ_OTG SZ_1M + +#define S5PV210_PA_OTGSFR (0xEC100000) +#define S5PV210_SZ_OTGSFR SZ_1M + +#define S5PV210_PA_USB_EHCI (0xEC200000) +#define S5P_PA_USB_EHCI S5PV210_PA_USB_EHCI +#define S5P_SZ_USB_EHCI SZ_1M + +#define S5PV210_PA_USB_OHCI (0xEC300000) +#define S5P_PA_USB_OHCI S5PV210_PA_USB_OHCI +#define S5P_SZ_USB_OHCI SZ_1M +/* end usb */ + #define S5PV210_PA_HSOTG 0xEC000000 #define S5PV210_PA_HSPHY 0xEC100000 +#define S5PV210_PA_AUDSS (0xEEE10000) + #define S5PV210_PA_IIS0 0xEEE30000 #define S5PV210_PA_IIS1 0xE2100000 #define S5PV210_PA_IIS2 0xE2A00000 @@ -71,6 +96,31 @@ #define S5PV210_PA_DMC0 0xF0000000 #define S5PV210_PA_DMC1 0xF1400000 +#define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0) +#define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define S5P_VA_VIC2 (S3C_VA_IRQ + 0x20000) +#define S5P_VA_VIC3 (S3C_VA_IRQ + 0x30000) + +#define S5PV210_PA_LCD (0xF8000000) +#define S5P_PA_LCD S5PV210_PA_LCD +#define S5PV210_SZ_LCD SZ_1M +#define S5P_SZ_LCD S5PV210_SZ_LCD + +#define S5PV210_PA_JPEG (0xFB600000) +#define S5PV210_SZ_JPEG SZ_1M + +#define S5PV210_SZ_FIMC0 SZ_1M +#define S5P_SZ_FIMC0 S5PV210_SZ_FIMC0 +#define S5PV210_SZ_FIMC1 SZ_1M +#define S5P_SZ_FIMC1 S5PV210_SZ_FIMC1 +#define S5PV210_SZ_FIMC2 SZ_1M +#define S5P_SZ_FIMC2 S5PV210_SZ_FIMC2 + +#define S5PV210_PA_IPC (0xFB700000) +#define S5P_PA_IPC S5PV210_PA_IPC +#define S5PV210_SZ_IPC SZ_1M +#define S5P_SZ_IPC S5PV210_SZ_IPC + #define S5PV210_PA_VIC0 0xF2000000 #define S5PV210_PA_VIC1 0xF2100000 #define S5PV210_PA_VIC2 0xF2200000 @@ -88,6 +138,28 @@ #define S5PV210_PA_FIMC1 0xFB300000 #define S5PV210_PA_FIMC2 0xFB400000 +/* mfc */ +#define S5PV210_PA_MFC (0xF1700000) +#define S5PV210_SZ_MFC SZ_1M +#define S5P_PA_MFC S5PV210_PA_MFC +#define S5P_SZ_MFC S5PV210_SZ_MFC + + +/* jpeg */ +#define S5PV210_PA_JPEG (0xFB600000) +#define S5P_PA_JPEG S5PV210_PA_JPEG +#define S5P_SZ_JPEG SZ_1M + +/* rotator */ +#define S5PV210_PA_ROTATOR (0xFA300000) +#define S5P_PA_ROTATOR S5PV210_PA_ROTATOR +#define S5P_SZ_ROTATOR SZ_1M + +/* fimg2d */ +#define S5PV210_PA_FIMG2D (0xFA000000) +#define S5P_PA_FIMG2D S5PV210_PA_FIMG2D +#define S5P_SZ_FIMG2D SZ_1M + /* Compatibiltiy Defines */ #define S3C_PA_FB S5PV210_PA_FB @@ -132,4 +204,38 @@ #define S5P_SZ_UART SZ_256 +/* CEC */ +#define S5PV210_PA_CEC (0xE1B00000) +#define S5P_PA_CEC S5PV210_PA_CEC +#define S5P_SZ_CEC SZ_4K + +/* TVOUT */ +#define S5PV210_PA_TVENC (0xF9000000) +#define S5P_PA_TVENC S5PV210_PA_TVENC +#define S5P_SZ_TVENC SZ_1M + +#define S5PV210_PA_VP (0xF9100000) +#define S5P_PA_VP S5PV210_PA_VP +#define S5P_SZ_VP SZ_1M + +#define S5PV210_PA_MIXER (0xF9200000) +#define S5P_PA_MIXER S5PV210_PA_MIXER +#define S5P_SZ_MIXER SZ_1M + +#define S5PV210_PA_HDMI (0xFA100000) +#define S5P_PA_HDMI S5PV210_PA_HDMI +#define S5P_SZ_HDMI SZ_1M + +#define S5PV210_I2C_HDMI_PHY (0xFA900000) +#define S5P_I2C_HDMI_PHY S5PV210_I2C_HDMI_PHY +#define S5P_I2C_HDMI_SZ_PHY SZ_1K + +/* usb */ +#define S3C_PA_OTG S5PV210_PA_OTG +#define S3C_SZ_OTG S5PV210_SZ_OTG + +#define S3C_PA_OTGSFR S5PV210_PA_OTGSFR +#define S3C_SZ_OTGSFR S5PV210_SZ_OTGSFR + +/* end usb */ #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/media.h b/arch/arm/mach-s5pv210/include/mach/media.h new file mode 100755 index 0000000..ad9eb82 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/media.h @@ -0,0 +1,32 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/media.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung Media device descriptions for smdkv210 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _S5PV210_MEDIA_H +#define _S5PV210_MEDIA_H + +/* 3 fimc indexes should be fixed as n, n+1 and n+2 */ +#define S5P_MDEV_FIMC0 0 +#define S5P_MDEV_FIMC1 1 +#define S5P_MDEV_FIMC2 2 +#define S5P_MDEV_TV 3 +#define S5P_MDEV_MFC 4 +#define S5P_MDEV_JPEG 5 +#define S5P_MDEV_PMEM 6 +#define S5P_MDEV_PMEM_GPU1 7 +#define S5P_MDEV_PMEM_ADSP 8 +#define S5P_MDEV_TEXSTREAM 9 +#define S5P_MDEV_FIMD 10 +#define S5P_MDEV_MAX 11 + +#define S5P_RANGE_MFC SZ_256M +#endif + diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h index 7b5fcf0..003d287 100644 --- a/arch/arm/mach-s5pv210/include/mach/memory.h +++ b/arch/arm/mach-s5pv210/include/mach/memory.h @@ -13,7 +13,12 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H +#if defined(CONFIG_MACH_SMDKV210) #define PLAT_PHYS_OFFSET UL(0x20000000) +#else +#define PLAT_PHYS_OFFSET UL(0x30000000) +#endif + #define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) /* @@ -24,5 +29,6 @@ #define MAX_PHYSMEM_BITS 31 #define SECTION_SIZE_BITS 28 +#define NODE_MEM_SIZE_BITS 28 #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/param.h b/arch/arm/mach-s5pv210/include/mach/param.h new file mode 100644 index 0000000..dbba308 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/param.h @@ -0,0 +1,89 @@ +
+/*
+ * Parameter Infomation
+ */
+
+#ifndef ASM_MACH_PARAM_H
+#define ASM_MACH_PARAM_H
+
+#define PARAM_MAGIC 0x72726624
+#define PARAM_VERSION 0x13 /* Rev 1.3 */
+#define PARAM_STRING_SIZE 1024 /* 1024 Characters */
+
+#define MAX_PARAM 20
+#define MAX_STRING_PARAM 5
+
+/* Default Parameter Values */
+
+#define SERIAL_SPEED 7 /* Baudrate */
+#define LCD_LEVEL 0x061 /* Backlight Level */
+#define BOOT_DELAY 0 /* Boot Wait Time */
+#define LOAD_RAMDISK 0 /* Enable Ramdisk Loading */
+#define SWITCH_SEL 1 /* Switch Setting (UART[1], USB[0]) */
+#define PHONE_DEBUG_ON 0 /* Enable Phone Debug Mode */
+#define LCD_DIM_LEVEL 0x011 /* Backlight Dimming Level */
+#define LCD_DIM_TIME 0
+#define MELODY_MODE 0 /* Melody Mode */
+#define REBOOT_MODE 0 /* Reboot Mode */
+#define NATION_SEL 0 /* Language Configuration */
+#define LANGUAGE_SEL 0
+#define SET_DEFAULT_PARAM 0 /* Set Param to Default */
+#define VERSION_LINE "I8315XXIE00" /* Set Image Info */
+#define COMMAND_LINE "console=ttySAC2,115200"
+#define BOOT_VERSION " version=Sbl(1.0.0) "
+
+typedef enum {
+ __SERIAL_SPEED,
+ __LOAD_RAMDISK,
+ __BOOT_DELAY,
+ __LCD_LEVEL,
+ __SWITCH_SEL,
+ __PHONE_DEBUG_ON,
+ __LCD_DIM_LEVEL,
+ __LCD_DIM_TIME,
+ __MELODY_MODE,
+ __REBOOT_MODE,
+ __NATION_SEL,
+ __LANGUAGE_SEL,
+ __SET_DEFAULT_PARAM,
+ __PARAM_INT_13, /* Reserved. */
+ __PARAM_INT_14, /* Reserved. */
+ __VERSION,
+ __CMDLINE,
+ __PARAM_STR_2,
+ __PARAM_STR_3, /* Reserved. */
+ __PARAM_STR_4 /* Reserved. */
+} param_idx;
+
+typedef struct _param_int_t {
+ param_idx ident;
+ int value;
+} param_int_t;
+
+typedef struct _param_str_t {
+ param_idx ident;
+ char value[PARAM_STRING_SIZE];
+} param_str_t;
+
+typedef struct {
+ int param_magic;
+ int param_version;
+ param_int_t param_list[MAX_PARAM - MAX_STRING_PARAM];
+ param_str_t param_str_list[MAX_STRING_PARAM];
+} status_t;
+
+/* REBOOT_MODE */
+#define REBOOT_MODE_NONE 0
+#define REBOOT_MODE_DOWNLOAD 1
+#define REBOOT_MODE_CHARGING 3
+#define REBOOT_MODE_RECOVERY 4
+#define REBOOT_MODE_ARM11_FOTA 5
+#define REBOOT_MODE_ARM9_FOTA 6
+
+extern void (*sec_set_param_value)(int idx, void *value);
+extern void (*sec_get_param_value)(int idx, void *value);
+
+#define USB_SEL_MASK (1 << 0)
+#define UART_SEL_MASK (1 << 1)
+
+#endif /* ASM_MACH_PARAM_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index e8d394f..e0db671 100644..100755 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h @@ -14,6 +14,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <mach/regs-gpio.h> static inline void s3c_pm_debug_init_uart(void) { @@ -33,7 +34,10 @@ static inline void s3c_pm_arch_stop_clocks(void) static inline void s3c_pm_arch_show_resume_irqs(void) { - /* nothing here yet */ + printk(KERN_DEBUG "S5P_WAKEUP_STAT 0x%X\n", __raw_readl(S5P_WAKEUP_STAT)); + printk(KERN_DEBUG "EINT_PEND 0x%X, 0x%X, 0x%X, 0x%X\n", + __raw_readl(S5P_EINT_PEND(0)), __raw_readl(S5P_EINT_PEND(1)), + __raw_readl(S5P_EINT_PEND(2)), __raw_readl(S5P_EINT_PEND(3))); } static inline void s3c_pm_arch_update_uart(void __iomem *regs, @@ -41,3 +45,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, { /* nothing here yet */ } + diff --git a/arch/arm/mach-s5pv210/include/mach/power-domain.h b/arch/arm/mach-s5pv210/include/mach/power-domain.h new file mode 100644 index 0000000..8456c10 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/power-domain.h @@ -0,0 +1,57 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/power-domain.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Power domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_POWER_DOMAIN_H +#define __ASM_ARCH_POWER_DOMAIN_H __FILE__ + +#define S5PV210_PD_IROM (1 << 20) +#define S5PV210_PD_AUDIO (1 << 7) +#define S5PV210_PD_CAM (1 << 5) +#define S5PV210_PD_TV (1 << 4) +#define S5PV210_PD_LCD (1 << 3) +#define S5PV210_PD_G3D (1 << 2) +#define S5PV210_PD_MFC (1 << 1) + +struct regulator_init_data; + +/** + * struct s5pv210_pd_config - s5pv210_pd_config structure + * @supply_name: Name of the regulator supply + * @microvolts: Output voltage of regulator + * @startup_delay: Start-up time in microseconds + * @init_data: regulator_init_data + * @clk_should_be_running: the clocks for the IPs in the power domain + * should be running when the power domain + * is turned on + * @ctrlbit: register control bit + * + * This structure contains samsung power domain regulator configuration + * information that must be passed by platform code to the samsung + * power domain regulator driver. + */ +struct s5pv210_pd_config { + const char *supply_name; + int microvolts; + unsigned startup_delay; + struct regulator_init_data *init_data; + struct clk_should_be_running *clk_run; + int ctrlbit; +}; + +extern struct platform_device s5pv210_pd_audio; +extern struct platform_device s5pv210_pd_cam; +extern struct platform_device s5pv210_pd_tv; +extern struct platform_device s5pv210_pd_lcd; +extern struct platform_device s5pv210_pd_g3d; +extern struct platform_device s5pv210_pd_mfc; + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/regs-adc.h b/arch/arm/mach-s5pv210/include/mach/regs-adc.h new file mode 100644 index 0000000..200fed9 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-adc.h @@ -0,0 +1,119 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-adc.h + * + * Copyright (c) 2004 Shannon Holland <holland@loser.net> + * + * This program is free software; yosu can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 ADC registers +*/ + +#ifndef __ASM_ARCH_REGS_ADC_H +#define __ASM_ARCH_REGS_ADC_H "regs-adc.h" + +#define S3C2410_ADCREG(x) (x) + +#define S3C2410_ADCCON S3C2410_ADCREG(0x00) +#define S3C2410_ADCTSC S3C2410_ADCREG(0x04) +#define S3C2410_ADCDLY S3C2410_ADCREG(0x08) +#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) +#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) + + +/* ADCCON Register Bits */ +#define S3C2410_ADCCON_ECFLG (1<<15) +#define S3C2410_ADCCON_PRSCEN (1<<14) +#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C2410_ADCCON_MUXMASK (0x7<<3) +#define S3C2410_ADCCON_STDBM (1<<2) +#define S3C2410_ADCCON_READ_START (1<<1) +#define S3C2410_ADCCON_ENABLE_START (1<<0) +#define S3C2410_ADCCON_STARTMASK (0x3<<0) + + +/* ADCTSC Register Bits */ +#define S3C2410_ADCTSC_YM_SEN (1<<7) +#define S3C2410_ADCTSC_YP_SEN (1<<6) +#define S3C2410_ADCTSC_XM_SEN (1<<5) +#define S3C2410_ADCTSC_XP_SEN (1<<4) +#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C2410_ADCTSC_AUTO_PST (1<<2) +#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0) + +/* ADCDAT0 Bits */ +#define S3C2410_ADCDAT0_UPDOWN (1<<15) +#define S3C2410_ADCDAT0_AUTO_PST (1<<14) +#define S3C2410_ADCDAT0_XY_PST (0x3<<12) +#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF) + +/* ADCDAT1 Bits */ +#define S3C2410_ADCDAT1_UPDOWN (1<<15) +#define S3C2410_ADCDAT1_AUTO_PST (1<<14) +#define S3C2410_ADCDAT1_XY_PST (0x3<<12) +#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) + +/*--------------------------- Common definitions for S3C ---------------------------*/ +/* The following definitions will be applied to S3C24XX, S3C64XX, S5PC1XX. */ +/*-----------------------------------------------------------------------------------*/ + +#define S3C_ADCREG(x) (x) + +#define S3C_ADCCON S3C_ADCREG(0x00) +#define S3C_ADCTSC S3C_ADCREG(0x04) +#define S3C_ADCDLY S3C_ADCREG(0x08) +#define S3C_ADCDAT0 S3C_ADCREG(0x0C) +#define S3C_ADCDAT1 S3C_ADCREG(0x10) +#define S3C_ADCUPDN S3C_ADCREG(0x14) +#define S3C_ADCCLRINT S3C_ADCREG(0x18) +#define S3C_ADCMUX S3C_ADCREG(0x1C) +#define S3C_ADCCLRWK S3C_ADCREG(0x20) + + +/* ADCCON Register Bits */ +#define S3C_ADCCON_RESSEL_10BIT (0x0<<16) +#define S3C_ADCCON_RESSEL_12BIT (0x1<<16) +#define S3C_ADCCON_ECFLG (1<<15) +#define S3C_ADCCON_PRSCEN (1<<14) +#define S3C_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) +#define S3C_ADCCON_PRSCVLMASK (0xFF<<6) +#define S3C_ADCCON_SELMUX(x) (((x)&0x7)<<3) +#define S3C_ADCCON_SELMUX_1(x) (((x)&0xF)<<0) +#define S3C_ADCCON_MUXMASK (0x7<<3) +#define S3C_ADCCON_RESSEL_10BIT_1 (0x0<<3) +#define S3C_ADCCON_RESSEL_12BIT_1 (0x1<<3) +#define S3C_ADCCON_STDBM (1<<2) +#define S3C_ADCCON_READ_START (1<<1) +#define S3C_ADCCON_ENABLE_START (1<<0) +#define S3C_ADCCON_STARTMASK (0x3<<0) + + +/* ADCTSC Register Bits */ +#define S3C_ADCTSC_UD_SEN (1<<8) +#define S3C_ADCTSC_YM_SEN (1<<7) +#define S3C_ADCTSC_YP_SEN (1<<6) +#define S3C_ADCTSC_XM_SEN (1<<5) +#define S3C_ADCTSC_XP_SEN (1<<4) +#define S3C_ADCTSC_PULL_UP_DISABLE (1<<3) +#define S3C_ADCTSC_AUTO_PST (1<<2) +#define S3C_ADCTSC_XY_PST(x) (((x)&0x3)<<0) + +/* ADCDAT0 Bits */ +#define S3C_ADCDAT0_UPDOWN (1<<15) +#define S3C_ADCDAT0_AUTO_PST (1<<14) +#define S3C_ADCDAT0_XY_PST (0x3<<12) +#define S3C_ADCDAT0_XPDATA_MASK (0x03FF) +#define S3C_ADCDAT0_XPDATA_MASK_12BIT (0x0FFF) + +/* ADCDAT1 Bits */ +#define S3C_ADCDAT1_UPDOWN (1<<15) +#define S3C_ADCDAT1_AUTO_PST (1<<14) +#define S3C_ADCDAT1_XY_PST (0x3<<12) +#define S3C_ADCDAT1_YPDATA_MASK (0x03FF) +#define S3C_ADCDAT1_YPDATA_MASK_12BIT (0x0FFF) + +#endif /* __ASM_ARCH_REGS_ADC_H */ + + diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h new file mode 100644 index 0000000..b2cc2fd --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h @@ -0,0 +1,44 @@ +/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h + * + * Copyright 2008 Samsung Electronics + * + * S5PV2XX Audio SubSystem clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_AUDSS_H +#define __PLAT_REGS_AUDSS_H __FILE__ + +#define S5P_AUDSSREG(x) (S5P_VA_AUDSS + (x)) + +#define S5P_CLKSRC_AUDSS S5P_AUDSSREG(0x0) +#define S5P_CLKDIV_AUDSS S5P_AUDSSREG(0x4) +#define S5P_CLKGATE_AUDSS S5P_AUDSSREG(0x8) + +/* CLKSRC0 */ +#define S5P_AUDSS_CLKSRC_MAIN_MASK (0x1<<0) +#define S5P_AUDSS_CLKSRC_MAIN_SHIFT (0) +#define S5P_AUDSS_CLKSRC_BUSCLK_MASK (0x1<<1) +#define S5P_AUDSS_CLKSRC_BUSCLK_SHIFT (1) +#define S5P_AUDSS_CLKSRC_I2SCLK_MASK (0x3<<2) +#define S5P_AUDSS_CLKSRC_I2SCLK_SHIFT (2) + +/* CLKDIV0 */ +#define S5P_AUDSS_CLKDIV_BUSCLK_MASK (0xf<<0) +#define S5P_AUDSS_CLKDIV_BUSCLK_SHIFT (0) +#define S5P_AUDSS_CLKDIV_I2SCLK_MASK (0xf<<4) +#define S5P_AUDSS_CLKDIV_I2SCLK_SHIFT (4) + +/* IP Clock Gate 0 Registers */ +#define S5P_AUDSS_CLKGATE_HCLKRP (1<<0) +#define S5P_AUDSS_CLKGATE_HCLKBUF (1<<1) +#define S5P_AUDSS_CLKGATE_HCLKDMA (1<<2) +#define S5P_AUDSS_CLKGATE_HCLKHWA (1<<3) +#define S5P_AUDSS_CLKGATE_HCLKUART (1<<4) +#define S5P_AUDSS_CLKGATE_HCLKI2S (1<<5) +#define S5P_AUDSS_CLKGATE_CLKI2S (1<<6) + +#endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 78925c5..d5d51cd 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -17,6 +17,9 @@ #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) +#define S5P_IECREG(x) (S5PC11X_VA_IEC + (x)) +#define S5P_APCREG(x) (S5PC11X_VA_APC + (x)) + #define S5P_APLL_LOCK S5P_CLKREG(0x00) #define S5P_MPLL_LOCK S5P_CLKREG(0x08) #define S5P_EPLL_LOCK S5P_CLKREG(0x10) @@ -64,8 +67,7 @@ #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) -#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) -#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) +#define S5P_CLKGATE_IP5 S5P_CLKREG(0x484) #define S5P_CLK_OUT S5P_CLKREG(0x500) /* DIV/MUX STATUS */ @@ -77,6 +79,17 @@ /* CLKSRC0 */ #define S5P_CLKSRC0_MUX200_SHIFT (16) #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) + +#define S5P_MIXER_OUT_SEL S5P_CLKREG(0x7004) + +#define S5P_EPLL_EN (1<<31) +#define S5P_EPLL_MASK 0xffffffff +#define S5P_EPLLVAL(_v,_m,_p,_s) ((_v) << 27 | (_m) << 16 | ((_p) << 8) | ((_s))) + +#define S5P_EPLL_MASK_VSEL (0x1<<27) +#define S5P_EPLL_MASK_M (0x1FF<<16) +#define S5P_EPLL_MASK_P (0x3F<<8) +#define S5P_EPLL_MASK_S (0x3<<0) #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) @@ -122,6 +135,161 @@ #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) +/* IP Clock Gate 0 Registers */ +#define S5P_CLKGATE_IP0_CSIS (1<<31) +#define S5P_CLKGATE_IP0_IPC (1<<30) +#define S5P_CLKGATE_IP0_ROTATOR (1<<29) +#define S5P_CLKGATE_IP0_JPEG (1<<28) +#define S5P_CLKGATE_IP0_FIMC2 (1<<26) +#define S5P_CLKGATE_IP0_FIMC1 (1<<25) +#define S5P_CLKGATE_IP0_FIMC0 (1<<24) +#define S5P_CLKGATE_IP0_MFC (1<<16) +#define S5P_CLKGATE_IP0_G2D (1<<12) +#define S5P_CLKGATE_IP0_G3D (1<<8) +#define S5P_CLKGATE_IP0_IMEM (1<<5) +#define S5P_CLKGATE_IP0_PDMA1 (1<<4) +#define S5P_CLKGATE_IP0_PDMA0 (1<<3) +#define S5P_CLKGATE_IP0_MDMA (1<<2) +#define S5P_CLKGATE_IP0_DMC1 (1<<1) +#define S5P_CLKGATE_IP0_DMC0 (1<<0) + +/* IP Clock Gate 1 Registers */ +#define S5P_CLKGATE_IP1_NFCON (1<<28) +#define S5P_CLKGATE_IP1_SROMC (1<<26) +#define S5P_CLKGATE_IP1_CFCON (1<<25) +#define S5P_CLKGATE_IP1_NANDXL (1<<24) +#define S5P_CLKGATE_IP1_USBHOST (1<<17) +#define S5P_CLKGATE_IP1_USBOTG (1<<16) +#define S5P_CLKGATE_IP1_HDMI (1<<11) +#define S5P_CLKGATE_IP1_TVENC (1<<10) +#define S5P_CLKGATE_IP1_MIXER (1<<9) +#define S5P_CLKGATE_IP1_VP (1<<8) +#define S5P_CLKGATE_IP1_DSIM (1<<2) +#define S5P_CLKGATE_IP1_MIE (1<<1) +#define S5P_CLKGATE_IP1_FIMD (1<<0) + +/* IP Clock Gate 2 Registers */ +#define S5P_CLKGATE_IP2_TZIC3 (1<<31) +#define S5P_CLKGATE_IP2_TZIC2 (1<<30) +#define S5P_CLKGATE_IP2_TZIC1 (1<<29) +#define S5P_CLKGATE_IP2_TZIC0 (1<<28) +#define S5P_CLKGATE_IP2_VIC3 (1<<27) +#define S5P_CLKGATE_IP2_VIC2 (1<<26) +#define S5P_CLKGATE_IP2_VIC1 (1<<25) +#define S5P_CLKGATE_IP2_VIC0 (1<<24) +#define S5P_CLKGATE_IP2_TSI (1<<20) +#define S5P_CLKGATE_IP2_HSMMC3 (1<<19) +#define S5P_CLKGATE_IP2_HSMMC2 (1<<18) +#define S5P_CLKGATE_IP2_HSMMC1 (1<<17) +#define S5P_CLKGATE_IP2_HSMMC0 (1<<16) +#define S5P_CLKGATE_IP2_SECJTAG (1<<11) +#define S5P_CLKGATE_IP2_HOSTIF (1<<10) +#define S5P_CLKGATE_IP2_MODEM (1<<9) +#define S5P_CLKGATE_IP2_CORESIGHT (1<<8) +#define S5P_CLKGATE_IP2_SDM (1<<1) +#define S5P_CLKGATE_IP2_SECSS (1<<0) + +/* IP Clock Gate 3 Registers */ +#define S5P_CLKGATE_IP3_PCM2 (1<<30) +#define S5P_CLKGATE_IP3_PCM1 (1<<29) +#define S5P_CLKGATE_IP3_PCM0 (1<<28) +#define S5P_CLKGATE_IP3_SYSCON (1<<27) +#define S5P_CLKGATE_IP3_GPIO (1<<26) +#define S5P_CLKGATE_IP3_TSADC (1<<24) +#define S5P_CLKGATE_IP3_PWM (1<<23) +#define S5P_CLKGATE_IP3_WDT (1<<22) +#define S5P_CLKGATE_IP3_KEYIF (1<<21) +#define S5P_CLKGATE_IP3_UART3 (1<<20) +#define S5P_CLKGATE_IP3_UART2 (1<<19) +#define S5P_CLKGATE_IP3_UART1 (1<<18) +#define S5P_CLKGATE_IP3_UART0 (1<<17) +#define S5P_CLKGATE_IP3_SYSTIMER (1<<16) +#define S5P_CLKGATE_IP3_RTC (1<<15) +#define S5P_CLKGATE_IP3_SPI2 (1<<14) +#define S5P_CLKGATE_IP3_SPI1 (1<<13) +#define S5P_CLKGATE_IP3_SPI0 (1<<12) +#define S5P_CLKGATE_IP3_I2C_HDMI_PHY (1<<11) +#define S5P_CLKGATE_IP3_I2C_HDMI_DDC (1<<10) +#define S5P_CLKGATE_IP3_I2C2 (1<<9) +#define S5P_CLKGATE_IP3_I2C1 (1<<8) +#define S5P_CLKGATE_IP3_I2C0 (1<<7) +#define S5P_CLKGATE_IP3_I2S2 (1<<6) +#define S5P_CLKGATE_IP3_I2S1 (1<<5) +#define S5P_CLKGATE_IP3_I2S0 (1<<4) +#define S5P_CLKGATE_IP3_AC97 (1<<1) +#define S5P_CLKGATE_IP3_SPDIF (1<<0) + +/* IP Clock Gate 4 Registers */ +#define S5P_CLKGATE_IP4_TZPC3 (1<<8) +#define S5P_CLKGATE_IP4_TZPC2 (1<<7) +#define S5P_CLKGATE_IP4_TZPC1 (1<<6) +#define S5P_CLKGATE_IP4_TZPC0 (1<<5) +#define S5P_CLKGATE_IP4_SECKEY (1<<3) +#define S5P_CLKGATE_IP4_IEM_APC (1<<2) +#define S5P_CLKGATE_IP4_IEM_IEC (1<<1) +#define S5P_CLKGATE_IP4_CHIP_ID (1<<0) + +/* Block Clock Gate Registers */ +#define S5P_CLKGATE_BLOCK_INTC (1<<10) +#define S5P_CLKGATE_BLOCK_HSMMC (1<<9) +#define S5P_CLKGATE_BLOCK_DEBUG (1<<8) +#define S5P_CLKGATE_BLOCK_SECURITY (1<<7) +#define S5P_CLKGATE_BLOCK_MEMORY (1<<6) +#define S5P_CLKGATE_BLOCK_USB (1<<5) +#define S5P_CLKGATE_BLOCK_TV (1<<4) +#define S5P_CLKGATE_BLOCK_LCD (1<<3) +#define S5P_CLKGATE_BLOCK_IMG (1<<2) +#define S5P_CLKGATE_BLOCK_MFC (1<<1) +#define S5P_CLKGATE_BLOCK_G3D (1<<0) + +/* IP Clock Gate 5 Registers */ +#define S5P_CLKGATE_IP5_JPEG (1<<29) + + +/* Bus Clock Gate Registers (hidden) */ + +/* register for EINT on PM Driver */ +#define S5P_APM_REG(x) ((x) + 0xE0200C00) + +#define S5P_APM_BASE S5P_APM_REG(0x000) + +#define S5P_APM_GPH0CON (0x000) +#define S5P_APM_GPH0DAT (0x004) +#define S5P_APM_GPH0PUD (0x008) +#define S5P_APM_GPH0DRV (0x00C) +#define S5P_APM_GPH1CON (0x020) +#define S5P_APM_GPH1DAT (0x024) +#define S5P_APM_GPH1PUD (0x028) +#define S5P_APM_GPH1DRV (0x02C) +#define S5P_APM_GPH2CON (0x040) +#define S5P_APM_GPH2DAT (0x044) +#define S5P_APM_GPH2PUD (0x048) +#define S5P_APM_GPH2DRV (0x04C) +#define S5P_APM_GPH3CON (0x060) +#define S5P_APM_GPH3DAT (0x064) +#define S5P_APM_GPH3PUD (0x068) +#define S5P_APM_GPH3DRV (0x06C) +#define S5P_APM_WEINT0_CON (0x200) +#define S5P_APM_WEINT1_CON (0x204) +#define S5P_APM_WEINT2_CON (0x208) +#define S5P_APM_WEINT3_CON (0x20C) +#define S5P_APM_WEINT0_FLTCON0 (0x280) +#define S5P_APM_WEINT0_FLTCON1 (0x284) +#define S5P_APM_WEINT1_FLTCON0 (0x288) +#define S5P_APM_WEINT1_FLTCON1 (0x28C) +#define S5P_APM_WEINT2_FLTCON0 (0x290) +#define S5P_APM_WEINT2_FLTCON1 (0x294) +#define S5P_APM_WEINT3_FLTCON0 (0x298) +#define S5P_APM_WEINT3_FLTCON1 (0x29C) +#define S5P_APM_WEINT0_MASK (0x300) +#define S5P_APM_WEINT1_MASK (0x304) +#define S5P_APM_WEINT2_MASK (0x308) +#define S5P_APM_WEINT3_MASK (0x30C) +#define S5P_APM_WEINT0_PEND (0x340) +#define S5P_APM_WEINT1_PEND (0x344) +#define S5P_APM_WEINT2_PEND (0x348) +#define S5P_APM_WEINT3_PEND (0x34C) + /* Registers related to power management */ #define S5P_PWR_CFG S5P_CLKREG(0xC000) #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) @@ -141,15 +309,21 @@ #define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) #define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) +#define S5P_ABB_VALUE S5P_CLKREG(0xC300) #define S5P_OTHERS S5P_CLKREG(0xE000) #define S5P_OM_STAT S5P_CLKREG(0xE100) +#define S5P_MIE_CONTROL S5P_CLKREG(0xE800) +#define S5P_HDMI_CONTROL S5P_CLKREG(0xE804) #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) #define S5P_DAC_CONTROL S5P_CLKREG(0xE810) #define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814) #define S5P_MIPI_DPHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_SRESETN (1 << 1) #define S5P_MIPI_DPHY_MRESETN (1 << 2) +#define S5P_ADC_CONTROL S5P_CLKREG(0xE818) +#define S5P_PSHOLD_CONTROL S5P_CLKREG(0xE81C) #define S5P_INFORM0 S5P_CLKREG(0xF000) #define S5P_INFORM1 S5P_CLKREG(0xF004) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h index de0c899..b2c69e8 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h @@ -15,11 +15,230 @@ #include <mach/map.h> +/* Base addresses for each of the banks */ + +#define S5PV210_GPA0_BASE (S5P_VA_GPIO + 0x000) +#define S5PV210_GPA1_BASE (S5P_VA_GPIO + 0x020) +#define S5PV210_GPB_BASE (S5P_VA_GPIO + 0x040) +#define S5PV210_GPC0_BASE (S5P_VA_GPIO + 0x060) +#define S5PV210_GPC1_BASE (S5P_VA_GPIO + 0x080) +#define S5PV210_GPD0_BASE (S5P_VA_GPIO + 0x0A0) +#define S5PV210_GPD1_BASE (S5P_VA_GPIO + 0x0C0) +#define S5PV210_GPE0_BASE (S5P_VA_GPIO + 0x0E0) +#define S5PV210_GPE1_BASE (S5P_VA_GPIO + 0x100) +#define S5PV210_GPF0_BASE (S5P_VA_GPIO + 0x120) +#define S5PV210_GPF1_BASE (S5P_VA_GPIO + 0x140) +#define S5PV210_GPF2_BASE (S5P_VA_GPIO + 0x160) +#define S5PV210_GPF3_BASE (S5P_VA_GPIO + 0x180) +#define S5PV210_GPG0_BASE (S5P_VA_GPIO + 0x1A0) +#define S5PV210_GPG1_BASE (S5P_VA_GPIO + 0x1C0) +#define S5PV210_GPG2_BASE (S5P_VA_GPIO + 0x1E0) +#define S5PV210_GPG3_BASE (S5P_VA_GPIO + 0x200) +#define S5PV210_GPH0_BASE (S5P_VA_GPIO + 0xC00) +#define S5PV210_GPH1_BASE (S5P_VA_GPIO + 0xC20) +#define S5PV210_GPH2_BASE (S5P_VA_GPIO + 0xC40) +#define S5PV210_GPH3_BASE (S5P_VA_GPIO + 0xC60) +#define S5PV210_GPI_BASE (S5P_VA_GPIO + 0x220) +#define S5PV210_GPJ0_BASE (S5P_VA_GPIO + 0x240) +#define S5PV210_GPJ1_BASE (S5P_VA_GPIO + 0x260) +#define S5PV210_GPJ2_BASE (S5P_VA_GPIO + 0x280) +#define S5PV210_GPJ3_BASE (S5P_VA_GPIO + 0x2A0) +#define S5PV210_GPJ4_BASE (S5P_VA_GPIO + 0x2C0) +#define S5PV210_MP01_BASE (S5P_VA_GPIO + 0x2E0) +#define S5PV210_MP02_BASE (S5P_VA_GPIO + 0x300) +#define S5PV210_MP03_BASE (S5P_VA_GPIO + 0x320) +#define S5PV210_MP04_BASE (S5P_VA_GPIO + 0x340) +#define S5PV210_MP05_BASE (S5P_VA_GPIO + 0x360) +#define S5PV210_MP06_BASE (S5P_VA_GPIO + 0x380) +#define S5PV210_MP07_BASE (S5P_VA_GPIO + 0x3A0) +#define S5PV210_MP10_BASE (S5P_VA_GPIO + 0x3C0) +#define S5PV210_MP11_BASE (S5P_VA_GPIO + 0x3E0) +#define S5PV210_MP12_BASE (S5P_VA_GPIO + 0x400) +#define S5PV210_MP13_BASE (S5P_VA_GPIO + 0x420) +#define S5PV210_MP14_BASE (S5P_VA_GPIO + 0x440) +#define S5PV210_MP15_BASE (S5P_VA_GPIO + 0x460) +#define S5PV210_MP16_BASE (S5P_VA_GPIO + 0x480) +#define S5PV210_MP17_BASE (S5P_VA_GPIO + 0x4A0) +#define S5PV210_MP18_BASE (S5P_VA_GPIO + 0x4C0) +#define S5PV210_MP20_BASE (S5P_VA_GPIO + 0x4E0) +#define S5PV210_MP21_BASE (S5P_VA_GPIO + 0x500) +#define S5PV210_MP22_BASE (S5P_VA_GPIO + 0x520) +#define S5PV210_MP23_BASE (S5P_VA_GPIO + 0x540) +#define S5PV210_MP24_BASE (S5P_VA_GPIO + 0x560) +#define S5PV210_MP25_BASE (S5P_VA_GPIO + 0x580) +#define S5PV210_MP26_BASE (S5P_VA_GPIO + 0x5A0) +#define S5PV210_MP27_BASE (S5P_VA_GPIO + 0x5C0) +#define S5PV210_MP28_BASE (S5P_VA_GPIO + 0x5E0) +#define S5PV210_ETC0_BASE (S5P_VA_GPIO + 0x600) +#define S5PV210_ETC1_BASE (S5P_VA_GPIO + 0x620) +#define S5PV210_ETC2_BASE (S5P_VA_GPIO + 0x640) +#define S5PV210_ETC4_BASE (S5P_VA_GPIO + 0x660) + +#define S5PV210_GPA0_INT_CON (S5P_VA_GPIO + 0x700) +#define S5PV210_GPA0_INT_FLTCON0 (S5P_VA_GPIO + 0x800) +#define S5PV210_GPA0_INT_FLTCON1 (S5P_VA_GPIO + 0x804) +#define S5PV210_GPA0_INT_MASK (S5P_VA_GPIO + 0x900) +#define S5PV210_GPA0_INT_PEND (S5P_VA_GPIO + 0xA00) +#define S5PV210_GPA0_INT_FIXPRI (S5P_VA_GPIO + 0xB14) + +#define S5PV210_GPA1_INT_CON (S5P_VA_GPIO + 0x704) +#define S5PV210_GPA1_INT_FLTCON0 (S5P_VA_GPIO + 0x808) +#define S5PV210_GPA1_INT_FLTCON1 (S5P_VA_GPIO + 0x80C) +#define S5PV210_GPA1_INT_MASK (S5P_VA_GPIO + 0x904) +#define S5PV210_GPA1_INT_PEND (S5P_VA_GPIO + 0xA04) +#define S5PV210_GPA1_INT_FIXPRI (S5P_VA_GPIO + 0xB18) + +#define S5PV210_GPB_INT_CON (S5P_VA_GPIO + 0x708) +#define S5PV210_GPB_INT_FLTCON0 (S5P_VA_GPIO + 0x810) +#define S5PV210_GPB_INT_FLTCON1 (S5P_VA_GPIO + 0x814) +#define S5PV210_GPB_INT_MASK (S5P_VA_GPIO + 0x908) +#define S5PV210_GPB_INT_PEND (S5P_VA_GPIO + 0xA08) +#define S5PV210_GPB_INT_FIXPRI (S5P_VA_GPIO + 0xB1C) + +#define S5PV210_GPC0_INT_CON (S5P_VA_GPIO + 0x70C) +#define S5PV210_GPC0_INT_FLTCON0 (S5P_VA_GPIO + 0x818) +#define S5PV210_GPC0_INT_FLTCON1 (S5P_VA_GPIO + 0x81C) +#define S5PV210_GPC0_INT_MASK (S5P_VA_GPIO + 0x90C) +#define S5PV210_GPC0_INT_PEND (S5P_VA_GPIO + 0xA0C) +#define S5PV210_GPC0_INT_FIXPRI (S5P_VA_GPIO + 0xB20) + +#define S5PV210_GPC1_INT_CON (S5P_VA_GPIO + 0x710) +#define S5PV210_GPC1_INT_FLTCON0 (S5P_VA_GPIO + 0x820) +#define S5PV210_GPC1_INT_FLTCON1 (S5P_VA_GPIO + 0x824) +#define S5PV210_GPC1_INT_MASK (S5P_VA_GPIO + 0x910) +#define S5PV210_GPC1_INT_PEND (S5P_VA_GPIO + 0xA10) +#define S5PV210_GPC1_INT_FIXPRI (S5P_VA_GPIO + 0xB24) + +#define S5PV210_GPD0_INT_CON (S5P_VA_GPIO + 0x714) +#define S5PV210_GPD0_INT_FLTCON0 (S5P_VA_GPIO + 0x828) +#define S5PV210_GPD0_INT_FLTCON1 (S5P_VA_GPIO + 0x82C) +#define S5PV210_GPD0_INT_MASK (S5P_VA_GPIO + 0x914) +#define S5PV210_GPD0_INT_PEND (S5P_VA_GPIO + 0xA14) +#define S5PV210_GPD0_INT_FIXPRI (S5P_VA_GPIO + 0xB28) + +#define S5PV210_GPD1_INT_CON (S5P_VA_GPIO + 0x718) +#define S5PV210_GPD1_INT_FLTCON0 (S5P_VA_GPIO + 0x830) +#define S5PV210_GPD1_INT_FLTCON1 (S5P_VA_GPIO + 0x834) +#define S5PV210_GPD1_INT_MASK (S5P_VA_GPIO + 0x918) +#define S5PV210_GPD1_INT_PEND (S5P_VA_GPIO + 0xA18) +#define S5PV210_GPD1_INT_FIXPRI (S5P_VA_GPIO + 0xB2C) + +#define S5PV210_GPE0_INT_CON (S5P_VA_GPIO + 0x71C) +#define S5PV210_GPE0_INT_FLTCON0 (S5P_VA_GPIO + 0x838) +#define S5PV210_GPE0_INT_FLTCON1 (S5P_VA_GPIO + 0x83C) +#define S5PV210_GPE0_INT_MASK (S5P_VA_GPIO + 0x91C) +#define S5PV210_GPE0_INT_PEND (S5P_VA_GPIO + 0xA1C) +#define S5PV210_GPE0_INT_FIXPRI (S5P_VA_GPIO + 0xB30) + +#define S5PV210_GPE1_INT_CON (S5P_VA_GPIO + 0x720) +#define S5PV210_GPE1_INT_FLTCON0 (S5P_VA_GPIO + 0x840) +#define S5PV210_GPE1_INT_FLTCON1 (S5P_VA_GPIO + 0x844) +#define S5PV210_GPE1_INT_MASK (S5P_VA_GPIO + 0x920) +#define S5PV210_GPE1_INT_PEND (S5P_VA_GPIO + 0xA20) +#define S5PV210_GPE1_INT_FIXPRI (S5P_VA_GPIO + 0xB34) + +#define S5PV210_GPF0_INT_CON (S5P_VA_GPIO + 0x724) +#define S5PV210_GPF0_INT_FLTCON0 (S5P_VA_GPIO + 0x848) +#define S5PV210_GPF0_INT_FLTCON1 (S5P_VA_GPIO + 0x84C) +#define S5PV210_GPF0_INT_MASK (S5P_VA_GPIO + 0x924) +#define S5PV210_GPF0_INT_PEND (S5P_VA_GPIO + 0xA24) +#define S5PV210_GPF0_INT_FIXPRI (S5P_VA_GPIO + 0xB38) + +#define S5PV210_GPF1_INT_CON (S5P_VA_GPIO + 0x728) +#define S5PV210_GPF1_INT_FLTCON0 (S5P_VA_GPIO + 0x850) +#define S5PV210_GPF1_INT_FLTCON1 (S5P_VA_GPIO + 0x854) +#define S5PV210_GPF1_INT_MASK (S5P_VA_GPIO + 0x928) +#define S5PV210_GPF1_INT_PEND (S5P_VA_GPIO + 0xA28) +#define S5PV210_GPF1_INT_FIXPRI (S5P_VA_GPIO + 0xB3C) + +#define S5PV210_GPF2_INT_CON (S5P_VA_GPIO + 0x72C) +#define S5PV210_GPF2_INT_FLTCON0 (S5P_VA_GPIO + 0x858) +#define S5PV210_GPF2_INT_FLTCON1 (S5P_VA_GPIO + 0x85C) +#define S5PV210_GPF2_INT_MASK (S5P_VA_GPIO + 0x92C) +#define S5PV210_GPF2_INT_PEND (S5P_VA_GPIO + 0xA2C) +#define S5PV210_GPF2_INT_FIXPRI (S5P_VA_GPIO + 0xB40) + +#define S5PV210_GPF3_INT_CON (S5P_VA_GPIO + 0x730) +#define S5PV210_GPF3_INT_FLTCON0 (S5P_VA_GPIO + 0x860) +#define S5PV210_GPF3_INT_FLTCON1 (S5P_VA_GPIO + 0x864) +#define S5PV210_GPF3_INT_MASK (S5P_VA_GPIO + 0x930) +#define S5PV210_GPF3_INT_PEND (S5P_VA_GPIO + 0xA30) +#define S5PV210_GPF3_INT_FIXPRI (S5P_VA_GPIO + 0xB44) + +#define S5PV210_GPG0_INT_CON (S5P_VA_GPIO + 0x734) +#define S5PV210_GPG0_INT_FLTCON0 (S5P_VA_GPIO + 0x868) +#define S5PV210_GPG0_INT_FLTCON1 (S5P_VA_GPIO + 0x86C) +#define S5PV210_GPG0_INT_MASK (S5P_VA_GPIO + 0x934) +#define S5PV210_GPG0_INT_PEND (S5P_VA_GPIO + 0xA34) +#define S5PV210_GPG0_INT_FIXPRI (S5P_VA_GPIO + 0xB48) + +#define S5PV210_GPG1_INT_CON (S5P_VA_GPIO + 0x738) +#define S5PV210_GPG1_INT_FLTCON0 (S5P_VA_GPIO + 0x870) +#define S5PV210_GPG1_INT_FLTCON1 (S5P_VA_GPIO + 0x874) +#define S5PV210_GPG1_INT_MASK (S5P_VA_GPIO + 0x938) +#define S5PV210_GPG1_INT_PEND (S5P_VA_GPIO + 0xA38) +#define S5PV210_GPG1_INT_FIXPRI (S5P_VA_GPIO + 0xB4C) + +#define S5PV210_GPG2_INT_CON (S5P_VA_GPIO + 0x73C) +#define S5PV210_GPG2_INT_FLTCON0 (S5P_VA_GPIO + 0x878) +#define S5PV210_GPG2_INT_FLTCON1 (S5P_VA_GPIO + 0x87C) +#define S5PV210_GPG2_INT_MASK (S5P_VA_GPIO + 0x93C) +#define S5PV210_GPG2_INT_PEND (S5P_VA_GPIO + 0xA3C) +#define S5PV210_GPG2_INT_FIXPRI (S5P_VA_GPIO + 0xB50) + +#define S5PV210_GPG3_INT_CON (S5P_VA_GPIO + 0x740) +#define S5PV210_GPG3_INT_FLTCON0 (S5P_VA_GPIO + 0x880) +#define S5PV210_GPG3_INT_FLTCON1 (S5P_VA_GPIO + 0x884) +#define S5PV210_GPG3_INT_MASK (S5P_VA_GPIO + 0x940) +#define S5PV210_GPG3_INT_PEND (S5P_VA_GPIO + 0xA40) +#define S5PV210_GPG3_INT_FIXPRI (S5P_VA_GPIO + 0xB54) + +#define S5PV210_GPJ0_INT_CON (S5P_VA_GPIO + 0x744) +#define S5PV210_GPJ0_INT_FLTCON0 (S5P_VA_GPIO + 0x888) +#define S5PV210_GPJ0_INT_FLTCON1 (S5P_VA_GPIO + 0x88C) +#define S5PV210_GPJ0_INT_MASK (S5P_VA_GPIO + 0x944) +#define S5PV210_GPJ0_INT_PEND (S5P_VA_GPIO + 0xA44) +#define S5PV210_GPJ0_INT_FIXPRI (S5P_VA_GPIO + 0xB58) + +#define S5PV210_GPJ1_INT_CON (S5P_VA_GPIO + 0x748) +#define S5PV210_GPJ1_INT_FLTCON0 (S5P_VA_GPIO + 0x890) +#define S5PV210_GPJ1_INT_FLTCON1 (S5P_VA_GPIO + 0x894) +#define S5PV210_GPJ1_INT_MASK (S5P_VA_GPIO + 0x948) +#define S5PV210_GPJ1_INT_PEND (S5P_VA_GPIO + 0xA48) +#define S5PV210_GPJ1_INT_FIXPRI (S5P_VA_GPIO + 0xB5C) + +#define S5PV210_GPJ2_INT_CON (S5P_VA_GPIO + 0x74C) +#define S5PV210_GPJ2_INT_FLTCON0 (S5P_VA_GPIO + 0x898) +#define S5PV210_GPJ2_INT_FLTCON1 (S5P_VA_GPIO + 0x89C) +#define S5PV210_GPJ2_INT_MASK (S5P_VA_GPIO + 0x94C) +#define S5PV210_GPJ2_INT_PEND (S5P_VA_GPIO + 0xA4C) +#define S5PV210_GPJ2_INT_FIXPRI (S5P_VA_GPIO + 0xB60) + +#define S5PV210_GPJ3_INT_CON (S5P_VA_GPIO + 0x750) +#define S5PV210_GPJ3_INT_FLTCON0 (S5P_VA_GPIO + 0x8A0) +#define S5PV210_GPJ3_INT_FLTCON1 (S5P_VA_GPIO + 0x8A4) +#define S5PV210_GPJ3_INT_MASK (S5P_VA_GPIO + 0x950) +#define S5PV210_GPJ3_INT_PEND (S5P_VA_GPIO + 0xA50) +#define S5PV210_GPJ3_INT_FIXPRI (S5P_VA_GPIO + 0xB64) + +#define S5PV210_GPJ4_INT_CON (S5P_VA_GPIO + 0x754) +#define S5PV210_GPJ4_INT_FLTCON0 (S5P_VA_GPIO + 0x8A8) +#define S5PV210_GPJ4_INT_FLTCON1 (S5P_VA_GPIO + 0x8AC) +#define S5PV210_GPJ4_INT_MASK (S5P_VA_GPIO + 0x954) +#define S5PV210_GPJ4_INT_PEND (S5P_VA_GPIO + 0xA54) +#define S5PV210_GPJ4_INT_FIXPRI (S5P_VA_GPIO + 0xB68) + +#define S5PV210_EXT_INT_GRPPRI (S5P_VA_GPIO + 0xB00) +#define S5PV210_EXT_INT_PRIO (S5P_VA_GPIO + 0xB04) +#define S5PV210_EXT_INT_SVC (S5P_VA_GPIO + 0xB08) +#define S5PV210_EXT_INT_SVC_PND (S5P_VA_GPIO + 0xB0C) +#define S5PV210_EXT_INT_GRPFIXPRI (S5P_VA_GPIO + 0xB10) + #define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00) #define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4)) #define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) -#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4)) +#define S5P_EINT_FLTCON(x,y) (S5PV210_EINT30FLTCON0 + ((x) * 0x8) + ((y) * 0x4)) #define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00) #define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4)) @@ -29,8 +248,16 @@ #define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) +#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq)-IRQ_EINT0)\ + : (irq-S5P_IRQ_EINT_BASE)) + #define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) +#define eint_conf_reg(irq) ((eint_offset(irq)) >> 3) +#define eint_filt_reg(irq) ((eint_offset(irq)) >> 2) +#define eint_mask_reg(irq) ((eint_offset(irq)) >> 3) +#define eint_pend_reg(irq) ((eint_offset(irq)) >> 3) + #define EINT_MODE S3C_GPIO_SFN(0xf) #define EINT_GPIO_0(x) S5PV210_GPH0(x) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h index 5c3b104..e3b86f1 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h @@ -16,4 +16,10 @@ #include <asm/hardware/vic.h> #include <mach/map.h> +/* interrupt controller */ +#define S5P_VIC0REG(x) ((x) + S5P_VA_VIC0) +#define S5P_VIC1REG(x) ((x) + S5P_VA_VIC1) +#define S5P_VIC2REG(x) ((x) + S5P_VA_VIC2) +#define S5P_VIC3REG(x) ((x) + S5P_VA_VIC3) + #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-mem.h b/arch/arm/mach-s5pv210/include/mach/regs-mem.h new file mode 100644 index 0000000..1c79d54 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-mem.h @@ -0,0 +1,28 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/regs-mem.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Memory Control register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MEM_H +#define __ASM_ARCH_REGS_MEM_H __FILE__ + +#include <mach/map.h> + +#define S5P_MEMREG(x) (S5P_VA_SROMC + (x)) + +#define S5P_SROM_BW S5P_MEMREG(0x00) +#define S5P_SROM_BC0 S5P_MEMREG(0x04) +#define S5P_SROM_BC1 S5P_MEMREG(0x08) +#define S5P_SROM_BC2 S5P_MEMREG(0x0C) +#define S5P_SROM_BC3 S5P_MEMREG(0x10) +#define S5P_SROM_BC4 S5P_MEMREG(0x14) +#define S5P_SROM_BC5 S5P_MEMREG(0x18) + +#endif /* __ASM_ARCH_REGS_MEM_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/tick.h b/arch/arm/mach-s5pv210/include/mach/tick.h index 7993b36..9fc5a8d 100644 --- a/arch/arm/mach-s5pv210/include/mach/tick.h +++ b/arch/arm/mach-s5pv210/include/mach/tick.h @@ -21,6 +21,12 @@ static inline u32 s3c24xx_ostimer_pending(void) return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); } +static inline u32 s5p_ostimer_pending(void) +{ + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_SYSTIMER - S5P_IRQ_VIC0(0))); +} + #define TICK_MAX (0xffffffff) #endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h index a6c659d..223e21a 100644 --- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h +++ b/arch/arm/mach-s5pv210/include/mach/vmalloc.h @@ -17,6 +17,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H __FILE__ -#define VMALLOC_END 0xF6000000UL +#define VMALLOC_END (0xFC000000) #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5pv210/init.c b/arch/arm/mach-s5pv210/init.c index 4865ae2..aca3789 100644 --- a/arch/arm/mach-s5pv210/init.c +++ b/arch/arm/mach-s5pv210/init.c @@ -20,7 +20,7 @@ static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = { [0] = { - .name = "pclk", + .name = "sclk", .divisor = 1, .min_baud = 0, .max_baud = 0, diff --git a/arch/arm/mach-s5pv210/mach-herring.c b/arch/arm/mach-s5pv210/mach-herring.c new file mode 100755 index 0000000..ae7be4b --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-herring.c @@ -0,0 +1,6162 @@ +/* linux/arch/arm/mach-s5pv210/mach-herring.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/gpio.h> +#include <linux/gpio_event.h> +#include <linux/videodev2.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/mfd/max8998.h> +#include <linux/i2c/ak8973.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/usb/ch9.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/clk.h> +#include <linux/usb/ch9.h> +#include <linux/input/cypress-touchkey.h> +#include <linux/input.h> +#include <linux/irq.h> +#include <linux/skbuff.h> +#include <linux/console.h> +#include <linux/earlysuspend.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/system.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/gpio.h> +#include <mach/gpio-herring.h> +#include <mach/adc.h> +#include <mach/param.h> +#include <mach/system.h> + +#include <linux/usb/gadget.h> +#include <linux/fsa9480.h> +#include <linux/pn544.h> +#include <linux/notifier.h> +#include <linux/reboot.h> +#include <linux/wlan_plat.h> +#include <linux/mfd/wm8994/wm8994_pdata.h> + +#ifdef CONFIG_ANDROID_PMEM +#include <linux/android_pmem.h> +#endif +#include <plat/media.h> +#include <mach/media.h> + +#ifdef CONFIG_S5PV210_POWER_DOMAIN +#include <mach/power-domain.h> +#endif +#include <mach/cpu-freq-v210.h> + +#include <media/s5ka3dfx_platform.h> +#include <media/s5k4ecgx.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv210.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/fb.h> +#include <plat/mfc.h> +#include <plat/iic.h> +#include <plat/pm.h> +#include <plat/s5p-time.h> + +#include <plat/sdhci.h> +#include <plat/fimc.h> +#include <plat/jpeg.h> +#include <plat/clock.h> +#include <plat/regs-otg.h> +#include <linux/gp2a.h> +#include <linux/kr3dm.h> +#include <linux/input/k3g.h> +#include <../../../drivers/video/samsung/s3cfb.h> +#include <linux/sec_jack.h> +#include <linux/input/mxt224.h> +#include <linux/max17040_battery.h> +#include <linux/mfd/max8998.h> +#include <linux/regulator/max8893.h> +#include <linux/wimax/samsung/wimax732.h> +#include <linux/switch.h> + +#include "herring.h" + +struct class *sec_class; +EXPORT_SYMBOL(sec_class); + +struct device *switch_dev; +EXPORT_SYMBOL(switch_dev); + +void (*sec_set_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_set_param_value); + +void (*sec_get_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_get_param_value); + +unsigned int is_device_lcd; + +#define REBOOT_MODE_FAST_BOOT 7 + +#define PREALLOC_WLAN_SEC_NUM 4 +#define PREALLOC_WLAN_BUF_NUM 160 +#define PREALLOC_WLAN_SECTION_HEADER 24 + +#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512) +#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024) + +#define WLAN_SKB_BUF_NUM 16 + +static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM]; + +struct wifi_mem_prealloc { + void *mem_ptr; + unsigned long size; +}; + +static int herring_notifier_call(struct notifier_block *this, + unsigned long code, void *_cmd) +{ + int mode = REBOOT_MODE_NONE; + + if ((code == SYS_RESTART) && _cmd) { + if (!strcmp((char *)_cmd, "recovery")) + mode = REBOOT_MODE_RECOVERY; + else if (!strcmp((char *)_cmd, "bootloader")) + mode = REBOOT_MODE_FAST_BOOT; + else + mode = REBOOT_MODE_NONE; + } + __raw_writel(mode, S5P_INFORM6); + + return NOTIFY_DONE; +} + +static struct notifier_block herring_reboot_notifier = { + .notifier_call = herring_notifier_call, +}; + +static void gps_gpio_init(void) +{ + struct device *gps_dev; + + gps_dev = device_create(sec_class, NULL, 0, NULL, "gps"); + if (IS_ERR(gps_dev)) { + pr_err("Failed to create device(gps)!\n"); + goto err; + } + + gpio_request(GPIO_GPS_nRST, "GPS_nRST"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_nRST, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_nRST, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_nRST, 1); + + gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_PWR_EN, 0); + + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + gpio_export(GPIO_GPS_nRST, 1); + gpio_export(GPIO_GPS_PWR_EN, 1); + + gpio_export_link(gps_dev, "GPS_nRST", GPIO_GPS_nRST); + gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN); + + err: + return; +} + +static void uart_switch_init(void) +{ + int ret; + struct device *uartswitch_dev; + + uartswitch_dev = device_create(sec_class, NULL, 0, NULL, "uart_switch"); + if (IS_ERR(uartswitch_dev)) { + pr_err("Failed to create device(uart_switch)!\n"); + return; + } + + ret = gpio_request(GPIO_UART_SEL, "UART_SEL"); + if (ret < 0) { + pr_err("Failed to request GPIO_UART_SEL!\n"); + return; + } + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + + gpio_direction_output(GPIO_UART_SEL, 1); + + gpio_export(GPIO_UART_SEL, 1); + + gpio_export_link(uartswitch_dev, "UART_SEL", GPIO_UART_SEL); + + if (herring_is_cdma_wimax_dev()) { + ret = gpio_request(GPIO_UART_SEL1, "UART_SEL1"); + if (ret < 0) { + pr_err("Failed to request GPIO_UART_SEL1!\n"); + gpio_free(GPIO_UART_SEL); + return; + } + + s3c_gpio_cfgpin(GPIO_UART_SEL1, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL1, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_UART_SEL1, 0); + + gpio_export(GPIO_UART_SEL1, 1); + gpio_export_link(uartswitch_dev, "UART_SEL1", GPIO_UART_SEL1); + } +} + +static void herring_switch_init(void) +{ + sec_class = class_create(THIS_MODULE, "sec"); + + if (IS_ERR(sec_class)) + pr_err("Failed to create class(sec)!\n"); + + switch_dev = device_create(sec_class, NULL, 0, NULL, "switch"); + + if (IS_ERR(switch_dev)) + pr_err("Failed to create device(switch)!\n"); +}; + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg herring_uartcfgs[] __initdata = { + { + .hwport = 0, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + .wake_peer = herring_bt_uart_wake_peer, + }, + { + .hwport = 1, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#ifndef CONFIG_FIQ_DEBUGGER + { + .hwport = 2, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#endif + { + .hwport = 3, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +}; + +#define S5PV210_LCD_WIDTH 480 +#define S5PV210_LCD_HEIGHT 800 + +static struct s3cfb_lcd s6e63m0 = { + .width = S5PV210_LCD_WIDTH, + .height = S5PV210_LCD_HEIGHT, + .p_width = 52, + .p_height = 86, + .bpp = 24, + .freq = 60, + + .timing = { + .h_fp = 16, + .h_bp = 16, + .h_sw = 2, + .v_fp = 28, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 1, + }, +}; + +static struct s3cfb_lcd nt35580 = { + .width = 480, + .height = 800, + .p_width = 52, + .p_height = 86, + .bpp = 24, + .freq = 60, + .timing = { + .h_fp = 10, + .h_bp = 20, + .h_sw = 10, + .v_fp = 6, + .v_fpe = 1, + .v_bp = 8, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 1, + }, +}; + +static struct s3cfb_lcd r61408 = { + .width = 480, + .height = 800, + .p_width = 52, + .p_height = 86, + .bpp = 24, + .freq = 60, + .timing = { + .h_fp = 100, + .h_bp = 2, + .h_sw = 2, + .v_fp = 8, + .v_fpe = 1, + .v_bp = 10, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 0, + }, +}; + +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0 (6144 * SZ_1K) +// #define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1 (4 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2 (6144 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0 (11264 * SZ_1K) // 11Mb +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (11264 * SZ_1K) // 11Mb +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD (S5PV210_LCD_WIDTH * \ + S5PV210_LCD_HEIGHT * 4 * \ + (CONFIG_FB_S3C_NR_BUFFERS + \ + (CONFIG_FB_S3C_NUM_OVLY_WIN * \ + CONFIG_FB_S3C_NUM_BUF_OVLY_WIN))) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG (4092 * SZ_1K) + +static struct s5p_media_device herring_media_devs[] = { + [0] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0, + .paddr = 0, + }, + [1] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1, + .paddr = 0, + }, + [2] = { + .id = S5P_MDEV_FIMC0, + .name = "fimc0", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0, + .paddr = 0, + }, + [4] = { + .id = S5P_MDEV_FIMC2, + .name = "fimc2", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2, + .paddr = 0, + }, + [5] = { + .id = S5P_MDEV_JPEG, + .name = "jpeg", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG, + .paddr = 0, + }, + [6] = { + .id = S5P_MDEV_FIMD, + .name = "fimd", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD, + .paddr = 0, + }, +}; + +#ifdef CONFIG_CPU_FREQ +static struct s5pv210_cpufreq_voltage smdkc110_cpufreq_volt[] = { + { + .freq = 1400000, + .varm = 1420000, + .vint = 1180000, + }, { + .freq = 1200000, + .varm = 1320000, + .vint = 1110000, + }, { + .freq = 1000000, + .varm = 1275000, + .vint = 1100000, + }, { + .freq = 800000, + .varm = 1200000, + .vint = 1100000, + }, { + .freq = 400000, + .varm = 1050000, + .vint = 1100000, + }, { + .freq = 200000, + .varm = 950000, + .vint = 1100000, + }, { + .freq = 100000, + .varm = 950000, + .vint = 1000000, + }, +}; + +static struct s5pv210_cpufreq_data smdkc110_cpufreq_plat = { + .volt = smdkc110_cpufreq_volt, + .size = ARRAY_SIZE(smdkc110_cpufreq_volt), +}; +#endif + +static struct regulator_consumer_supply ldo3_consumer[] = { + REGULATOR_SUPPLY("pd_io", "s3c-usbgadget") +}; + +static struct regulator_consumer_supply ldo7_consumer[] = { + { .supply = "vlcd", }, +}; + +static struct regulator_consumer_supply ldo8_consumer[] = { + REGULATOR_SUPPLY("pd_core", "s3c-usbgadget") +}; + +static struct regulator_consumer_supply ldo11_consumer[] = { + { .supply = "cam_af", }, +}; + +static struct regulator_consumer_supply ldo12_consumer[] = { + { .supply = "cam_sensor", }, +}; + +static struct regulator_consumer_supply ldo13_consumer[] = { + { .supply = "vga_vddio", }, +}; + +static struct regulator_consumer_supply ldo14_consumer[] = { + { .supply = "vga_dvdd", }, +}; + +static struct regulator_consumer_supply ldo15_consumer[] = { + { .supply = "cam_isp_host", }, +}; + +static struct regulator_consumer_supply ldo16_consumer[] = { + { .supply = "vga_avdd", }, +}; + +static struct regulator_consumer_supply ldo17_consumer[] = { + { .supply = "vcc_lcd", }, +}; + +static struct regulator_consumer_supply buck1_consumer[] = { + { .supply = "vddarm", }, +}; + +static struct regulator_consumer_supply buck2_consumer[] = { + { .supply = "vddint", }, +}; + +static struct regulator_consumer_supply buck4_consumer[] = { + { .supply = "cam_isp_core", }, +}; + +static struct regulator_init_data herring_ldo2_data = { + .constraints = { + .name = "VALIVE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data herring_ldo3_data = { + .constraints = { + .name = "VUSB_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), + .consumer_supplies = ldo3_consumer, +}; + +static struct regulator_init_data herring_ldo4_data = { + .constraints = { + .name = "VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, +}; + +static struct regulator_init_data herring_ldo7_data = { + .constraints = { + .name = "VLCD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), + .consumer_supplies = ldo7_consumer, +}; + +static struct regulator_init_data herring_ldo8_data = { + .constraints = { + .name = "VUSB_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), + .consumer_supplies = ldo8_consumer, +}; + +static struct regulator_init_data herring_ldo9_data = { + .constraints = { + .name = "VCC_2.8V_PDA", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data herring_ldo11_data = { + .constraints = { + .name = "CAM_AF_3.0V", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), + .consumer_supplies = ldo11_consumer, +}; + +static struct regulator_init_data herring_ldo12_data = { + .constraints = { + .name = "CAM_SENSOR_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo12_consumer), + .consumer_supplies = ldo12_consumer, +}; + +static struct regulator_init_data herring_ldo13_data = { + .constraints = { + .name = "VGA_VDDIO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo13_consumer), + .consumer_supplies = ldo13_consumer, +}; + +static struct regulator_init_data herring_ldo14_data = { + .constraints = { + .name = "VGA_DVDD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), + .consumer_supplies = ldo14_consumer, +}; + +static struct regulator_init_data herring_ldo15_data = { + .constraints = { + .name = "CAM_ISP_HOST_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo15_consumer), + .consumer_supplies = ldo15_consumer, +}; + +static struct regulator_init_data herring_ldo16_data = { + .constraints = { + .name = "VGA_AVDD_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo16_consumer), + .consumer_supplies = ldo16_consumer, +}; + +static struct regulator_init_data herring_ldo17_data = { + .constraints = { + .name = "VCC_3.0V_LCD", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), + .consumer_supplies = ldo17_consumer, +}; + +static struct regulator_init_data herring_buck1_data = { + .constraints = { + .name = "VDD_ARM", + .min_uV = 750000, + .max_uV = 1600000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1600000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), + .consumer_supplies = buck1_consumer, +}; + +static struct regulator_init_data herring_buck2_data = { + .constraints = { + .name = "VDD_INT", + .min_uV = 750000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1250000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), + .consumer_supplies = buck2_consumer, +}; + +static struct regulator_init_data herring_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data herring_buck4_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck4_consumer), + .consumer_supplies = buck4_consumer, +}; + +static struct max8998_regulator_data herring_regulators[] = { + { MAX8998_LDO2, &herring_ldo2_data }, + { MAX8998_LDO3, &herring_ldo3_data }, + { MAX8998_LDO4, &herring_ldo4_data }, + { MAX8998_LDO7, &herring_ldo7_data }, + { MAX8998_LDO8, &herring_ldo8_data }, + { MAX8998_LDO9, &herring_ldo9_data }, + { MAX8998_LDO11, &herring_ldo11_data }, + { MAX8998_LDO12, &herring_ldo12_data }, + { MAX8998_LDO13, &herring_ldo13_data }, + { MAX8998_LDO14, &herring_ldo14_data }, + { MAX8998_LDO15, &herring_ldo15_data }, + { MAX8998_LDO16, &herring_ldo16_data }, + { MAX8998_LDO17, &herring_ldo17_data }, + { MAX8998_BUCK1, &herring_buck1_data }, + { MAX8998_BUCK2, &herring_buck2_data }, + { MAX8998_BUCK3, &herring_buck3_data }, + { MAX8998_BUCK4, &herring_buck4_data }, +}; + +static struct max8998_regulator_data herring_cdma_wimax_regulators[] = { + { MAX8998_LDO2, &herring_ldo2_data }, + { MAX8998_LDO3, &herring_ldo3_data }, + { MAX8998_LDO4, &herring_ldo4_data }, + { MAX8998_LDO7, &herring_ldo7_data }, + { MAX8998_LDO8, &herring_ldo8_data }, + { MAX8998_LDO9, &herring_ldo9_data }, + { MAX8998_LDO11, &herring_ldo11_data }, + { MAX8998_LDO13, &herring_ldo13_data }, + { MAX8998_LDO14, &herring_ldo14_data }, + { MAX8998_LDO15, &herring_ldo15_data }, + { MAX8998_LDO16, &herring_ldo16_data }, + { MAX8998_LDO17, &herring_ldo17_data }, + { MAX8998_BUCK1, &herring_buck1_data }, + { MAX8998_BUCK2, &herring_buck2_data }, + { MAX8998_BUCK3, &herring_buck3_data }, + { MAX8998_BUCK4, &herring_buck4_data }, +}; + +static struct max8998_adc_table_data temper_table_oled[] = { + /* ADC, Temperature (C/10) */ + { 222, 700 }, + { 230, 690 }, + { 238, 680 }, + { 245, 670 }, + { 253, 660 }, + { 261, 650 }, + { 274, 640 }, + { 287, 630 }, + { 300, 620 }, + { 314, 610 }, + { 327, 600 }, + { 339, 590 }, + { 350, 580 }, + { 362, 570 }, + { 374, 560 }, + { 386, 550 }, + { 401, 540 }, + { 415, 530 }, + { 430, 520 }, + { 444, 510 }, + { 459, 500 }, + { 477, 490 }, + { 495, 480 }, + { 513, 470 }, + { 526, 460 }, + { 539, 450 }, + { 559, 440 }, + { 580, 430 }, + { 600, 420 }, + { 618, 410 }, + { 642, 400 }, + { 649, 390 }, + { 674, 380 }, + { 695, 370 }, + { 717, 360 }, + { 739, 350 }, + { 760, 340 }, + { 782, 330 }, + { 803, 320 }, + { 825, 310 }, + { 847, 300 }, + { 870, 290 }, + { 894, 280 }, + { 918, 270 }, + { 942, 260 }, + { 966, 250 }, + { 990, 240 }, + { 1014, 230 }, + { 1038, 220 }, + { 1062, 210 }, + { 1086, 200 }, + { 1110, 190 }, + { 1134, 180 }, + { 1158, 170 }, + { 1182, 160 }, + { 1206, 150 }, + { 1228, 140 }, + { 1251, 130 }, + { 1274, 120 }, + { 1297, 110 }, + { 1320, 100 }, + { 1341, 90 }, + { 1362, 80 }, + { 1384, 70 }, + { 1405, 60 }, + { 1427, 50 }, + { 1450, 40 }, + { 1474, 30 }, + { 1498, 20 }, + { 1514, 10 }, + { 1533, 0 }, + { 1544, (-10) }, + { 1567, (-20) }, + { 1585, (-30) }, + { 1604, (-40) }, + { 1623, (-50) }, + { 1641, (-60) }, + { 1659, (-70) }, + { 1678, (-80) }, + { 1697, (-90) }, + { 1715, (-100) }, +}; +static struct max8998_adc_table_data temper_table_tft[] = { + /* ADC, Temperature (C/10) */ + { 242, 700 }, + { 253, 690 }, + { 264, 680 }, + { 275, 670 }, + { 286, 660 }, + { 297, 650 }, + { 310, 640 }, + { 323, 630 }, + { 336, 620 }, + { 349, 610 }, + { 362, 600 }, + { 375, 590 }, + { 388, 580 }, + { 401, 570 }, + { 414, 560 }, + { 430, 550 }, + { 444, 540 }, + { 458, 530 }, + { 472, 520 }, + { 486, 510 }, + { 500, 500 }, + { 515, 490 }, + { 530, 480 }, + { 545, 470 }, + { 560, 460 }, + { 575, 450 }, + { 590, 440 }, + { 605, 430 }, + { 625, 420 }, + { 645, 410 }, + { 665, 400 }, + { 683, 390 }, + { 702, 380 }, + { 735, 370 }, + { 768, 360 }, + { 768, 350 }, + { 790, 340 }, + { 812, 330 }, + { 834, 320 }, + { 856, 310 }, + { 881, 300 }, + { 905, 290 }, + { 929, 280 }, + { 955, 270 }, + { 979, 260 }, + { 1002, 250 }, + { 1027, 240 }, + { 1053, 230 }, + { 1078, 220 }, + { 1105, 210 }, + { 1130, 200 }, + { 1151, 190 }, + { 1174, 180 }, + { 1195, 170 }, + { 1219, 160 }, + { 1237, 150 }, + { 1261, 140 }, + { 1285, 130 }, + { 1309, 120 }, + { 1331, 110 }, + { 1359, 100 }, + { 1381, 90 }, + { 1404, 80 }, + { 1426, 70 }, + { 1438, 60 }, + { 1470, 50 }, + { 1488, 40 }, + { 1506, 30 }, + { 1524, 20 }, + { 1532, 10 }, + { 1560, 0 }, + { 1586, (-10) }, + { 1604, (-20) }, + { 1614, (-30) }, + { 1622, (-40) }, + { 1630, (-50) }, + { 1648, (-60) }, + { 1666, (-70) }, + { 1684, (-80) }, + { 1702, (-90) }, + { 1720, (-100) }, +}; + +static struct max8998_adc_table_data temper_table_cdma_wimax_oled[] = { + /* ADC, Temperature (C/10) */ + { 116, 700 }, + { 122, 690 }, + { 128, 680 }, + { 134, 670 }, + { 140, 660 }, + { 146, 650 }, + { 152, 640 }, + { 158, 630 }, + { 164, 620 }, + { 170, 610 }, + { 176, 600 }, + { 182, 590 }, + { 188, 580 }, + { 194, 570 }, + { 200, 560 }, + { 206, 550 }, + { 212, 540 }, + { 218, 530 }, + { 222, 520 }, + { 230, 510 }, + { 238, 500 }, + { 245, 490 }, + { 260, 480 }, + { 290, 470 }, + { 325, 460 }, + { 360, 450 }, + { 395, 440 }, + { 430, 430 }, + { 465, 420 }, + { 500, 410 }, + { 535, 400 }, + { 575, 390 }, + { 615, 380 }, + { 642, 370 }, + { 695, 360 }, + { 717, 350 }, + { 737, 340 }, + { 760, 330 }, + { 782, 320 }, + { 803, 310 }, + { 825, 300 }, + { 847, 290 }, + { 870, 280 }, + { 900, 270 }, + { 942, 260 }, + { 966, 250 }, + { 990, 240 }, + { 1014, 230 }, + { 1038, 220 }, + { 1062, 210 }, + { 1086, 200 }, + { 1110, 190 }, + { 1134, 180 }, + { 1158, 170 }, + { 1182, 160 }, + { 1206, 150 }, + { 1228, 140 }, + { 1251, 130 }, + { 1274, 120 }, + { 1297, 110 }, + { 1320, 100 }, + { 1341, 90 }, + { 1362, 80 }, + { 1384, 70 }, + { 1405, 60 }, + { 1427, 50 }, + { 1450, 40 }, + { 1474, 30 }, + { 1498, 20 }, + { 1514, 10 }, + { 1533, 0 }, + { 1544, (-10) }, + { 1567, (-20) }, + { 1585, (-30) }, + { 1604, (-40) }, + { 1623, (-50) }, + { 1641, (-60) }, + { 1659, (-70) }, + { 1678, (-80) }, + { 1697, (-90) }, + { 1715, (-100) }, +}; + +struct max8998_charger_callbacks *callbacks; +static enum cable_type_t set_cable_status; + +static void max8998_charger_register_callbacks( + struct max8998_charger_callbacks *ptr) +{ + callbacks = ptr; + /* if there was a cable status change before the charger was + ready, send this now */ + if ((set_cable_status != 0) && callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static struct max8998_charger_data herring_charger = { + .register_callbacks = &max8998_charger_register_callbacks, +}; + +static void set_adc_table(void) +{ + if (!herring_is_tft_dev()) { + if (herring_is_cdma_wimax_dev()) { + herring_charger.adc_table = + temper_table_cdma_wimax_oled; + herring_charger.adc_array_size = + ARRAY_SIZE(temper_table_cdma_wimax_oled); + } else { + herring_charger.adc_table = temper_table_oled; + herring_charger.adc_array_size = + ARRAY_SIZE(temper_table_oled); + } + } else { + herring_charger.adc_table = temper_table_tft; + herring_charger.adc_array_size = + ARRAY_SIZE(temper_table_tft); + } +} + +static struct max8998_platform_data max8998_pdata = { + .num_regulators = ARRAY_SIZE(herring_regulators), + .regulators = herring_regulators, + .charger = &herring_charger, + /* Preloads must be in increasing order of voltage value */ + .buck1_voltage4 = 950000, + .buck1_voltage3 = 1050000, + .buck1_voltage2 = 1200000, + .buck1_voltage1 = 1275000, + .buck2_voltage2 = 1000000, + .buck2_voltage1 = 1100000, + .buck1_set1 = GPIO_BUCK_1_EN_A, + .buck1_set2 = GPIO_BUCK_1_EN_B, + .buck2_set3 = GPIO_BUCK_2_EN, + .buck1_default_idx = 1, + .buck2_default_idx = 0, +}; + +struct platform_device sec_device_dpram = { + .name = "dpram-device", + .id = -1, +}; + +static unsigned int lcd_type; +module_param_named(lcd_type, lcd_type, uint, 0444); +MODULE_PARM_DESC(lcd_type, "LCD type: default= sony, 1= hydis, 2= hitachi"); + +static void panel_cfg_gpio(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + } + + /* mDNIe SEL: why we shall write 0x2 ? */ +#ifdef CONFIG_FB_S3C_MDNIE + writel(0x1, S5P_MDNIE_SEL); +#else + writel(0x2, S5P_MDNIE_SEL); +#endif + + /* DISPLAY_CS */ + s3c_gpio_cfgpin(S5PV210_MP01(1), S3C_GPIO_SFN(1)); + /* DISPLAY_CLK */ + s3c_gpio_cfgpin(S5PV210_MP04(1), S3C_GPIO_SFN(1)); + /* DISPLAY_SO */ + s3c_gpio_cfgpin(S5PV210_MP04(2), S3C_GPIO_SFN(1)); + /* DISPLAY_SI */ + s3c_gpio_cfgpin(S5PV210_MP04(3), S3C_GPIO_SFN(1)); + + /* DISPLAY_CS */ + s3c_gpio_setpull(S5PV210_MP01(1), S3C_GPIO_PULL_NONE); + /* DISPLAY_CLK */ + s3c_gpio_setpull(S5PV210_MP04(1), S3C_GPIO_PULL_NONE); + /* DISPLAY_SO */ + s3c_gpio_setpull(S5PV210_MP04(2), S3C_GPIO_PULL_NONE); + /* DISPLAY_SI */ + s3c_gpio_setpull(S5PV210_MP04(3), S3C_GPIO_PULL_NONE); + + /* OLED_ID */ + if (herring_is_tft_dev()) { + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_DOWN); + } +} + +void lcd_cfg_gpio_early_suspend(void) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF0(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF1(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF2(i), 0); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF3(i), 0); + } + /* drive strength to min */ + writel(0x00000000, S5P_VA_GPIO + 0x12c); /* GPF0DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x14c); /* GPF1DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x16c); /* GPF2DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x18c); /* GPF3DRV */ + + /* OLED_DET */ + s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_OLED_DET, 0); + + /* LCD_RST */ + s3c_gpio_cfgpin(GPIO_MLCD_RST, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_MLCD_RST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_MLCD_RST, 0); + + /* DISPLAY_CS */ + s3c_gpio_cfgpin(GPIO_DISPLAY_CS, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_CS, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_CS, 0); + + /* DISPLAY_CLK */ + s3c_gpio_cfgpin(GPIO_DISPLAY_CLK, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_CLK, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_CLK, 0); + + /* DISPLAY_SO */ + /* + s3c_gpio_cfgpin(S5PV210_MP04(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_MP04(2), S3C_GPIO_PULL_DOWN); + */ + + /* DISPLAY_SI */ + s3c_gpio_cfgpin(GPIO_DISPLAY_SI, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_SI, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_SI, 0); + + /* OLED_ID */ + if (!herring_is_tft_dev()) { + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_DOWN); + /* gpio_set_value(GPIO_OLED_ID, 0); */ + } + + /* DIC_ID */ + s3c_gpio_cfgpin(GPIO_DIC_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_DOWN); + /* gpio_set_value(GPIO_DIC_ID, 0); */ +} +EXPORT_SYMBOL(lcd_cfg_gpio_early_suspend); + +void lcd_cfg_gpio_late_resume(void) +{ + /* OLED_DET */ + s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); + /* OLED_ID */ + if (!herring_is_tft_dev()) { + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_NONE); + /* gpio_set_value(GPIO_OLED_ID, 0); */ + } + /* DIC_ID */ + s3c_gpio_cfgpin(GPIO_DIC_ID, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_NONE); + /* gpio_set_value(GPIO_DIC_ID, 0); */ +} +EXPORT_SYMBOL(lcd_cfg_gpio_late_resume); + +static int panel_reset_lcd(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_MP05(5), "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request MP0(5) for " + "lcd reset control\n"); + return err; + } + + gpio_direction_output(S5PV210_MP05(5), 1); + msleep(10); + + gpio_set_value(S5PV210_MP05(5), 0); + msleep(10); + + gpio_set_value(S5PV210_MP05(5), 1); + msleep(10); + + gpio_free(S5PV210_MP05(5)); + + return 0; +} + +static int panel_backlight_on(struct platform_device *pdev) +{ + return 0; +} + +static struct s3c_platform_fb tl2796_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &s6e63m0, + .cfg_gpio = panel_cfg_gpio, + .backlight_on = panel_backlight_on, + .reset_lcd = panel_reset_lcd, +}; + +static struct s3c_platform_fb nt35580_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &nt35580, + .cfg_gpio = panel_cfg_gpio, + .backlight_on = panel_backlight_on, + .reset_lcd = panel_reset_lcd, +}; + +static struct s3c_platform_fb r61408_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &r61408, + .cfg_gpio = panel_cfg_gpio, + .backlight_on = panel_backlight_on, + .reset_lcd = panel_reset_lcd, +}; + +#define LCD_BUS_NUM 3 +#define DISPLAY_CS S5PV210_MP01(1) +#define SUB_DISPLAY_CS S5PV210_MP01(2) +#define DISPLAY_CLK S5PV210_MP04(1) +#define DISPLAY_SI S5PV210_MP04(3) + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "tl2796", + .platform_data = &herring_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +static struct spi_board_info spi_board_info_sony[] __initdata = { + { + .modalias = "nt35580", + .platform_data = &herring_sony_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +static struct spi_board_info spi_board_info_hydis[] __initdata = { + { + .modalias = "nt35580", + .platform_data = &herring_hydis_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +static struct spi_board_info spi_board_info_hitachi[] __initdata = { + { + .modalias = "nt35580", + .platform_data = &herring_hitachi_panel_data, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + + +static struct spi_gpio_platform_data tl2796_spi_gpio_data = { + .sck = DISPLAY_CLK, + .mosi = DISPLAY_SI, + .miso = -1, + .num_chipselect = 2, +}; + +static struct platform_device s3c_device_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s3c_device_fb.dev, + .platform_data = &tl2796_spi_gpio_data, + }, +}; + +static struct i2c_gpio_platform_data herring_i2c4_platdata = { + .sda_pin = GPIO_AP_SDA_18V, + .scl_pin = GPIO_AP_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c4_device = { + .name = "i2c-gpio", + .id = 4, + .dev.platform_data = &herring_i2c4_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c5_platdata = { + .sda_pin = GPIO_AP_SDA_28V, + .scl_pin = GPIO_AP_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c5_device = { + .name = "i2c-gpio", + .id = 5, + .dev.platform_data = &herring_i2c5_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c6_platdata = { + .sda_pin = GPIO_AP_PMIC_SDA, + .scl_pin = GPIO_AP_PMIC_SCL, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c6_device = { + .name = "i2c-gpio", + .id = 6, + .dev.platform_data = &herring_i2c6_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c7_platdata = { + .sda_pin = GPIO_USB_SDA_28V, + .scl_pin = GPIO_USB_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c7_device = { + .name = "i2c-gpio", + .id = 7, + .dev.platform_data = &herring_i2c7_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c8_platdata = { + .sda_pin = GYRO_SDA_28V, + .scl_pin = GYRO_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c8_device = { + .name = "i2c-gpio", + .id = 8, + .dev.platform_data = &herring_i2c8_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c9_platdata = { + .sda_pin = FUEL_SDA_18V, + .scl_pin = FUEL_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c9_device = { + .name = "i2c-gpio", + .id = 9, + .dev.platform_data = &herring_i2c9_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c10_platdata = { + .sda_pin = _3_TOUCH_SDA_28V, + .scl_pin = _3_TOUCH_SCL_28V, + .udelay = 0, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c10_device = { + .name = "i2c-gpio", + .id = 10, + .dev.platform_data = &herring_i2c10_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c11_platdata = { + .sda_pin = GPIO_ALS_SDA_28V, + .scl_pin = GPIO_ALS_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c11_device = { + .name = "i2c-gpio", + .id = 11, + .dev.platform_data = &herring_i2c11_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c12_platdata = { + .sda_pin = GPIO_MSENSE_SDA_28V, + .scl_pin = GPIO_MSENSE_SCL_28V, + .udelay = 0, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c12_device = { + .name = "i2c-gpio", + .id = 12, + .dev.platform_data = &herring_i2c12_platdata, +}; + +static struct i2c_gpio_platform_data herring_i2c14_platdata = { + .sda_pin = NFC_SDA_18V, + .scl_pin = NFC_SCL_18V, + .udelay = 2, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device herring_i2c14_device = { + .name = "i2c-gpio", + .id = 14, + .dev.platform_data = &herring_i2c14_platdata, +}; + +/* max8893 wimax PMIC */ +static struct i2c_gpio_platform_data herring_i2c15_platdata = { + .sda_pin = GPIO_WIMAX_PM_SDA, + .scl_pin = GPIO_WIMAX_PM_SCL, +}; + +static struct platform_device herring_i2c15_device = { + .name = "i2c-gpio", + .id = 15, + .dev.platform_data = &herring_i2c15_platdata, +}; + +static struct regulator_init_data herring_max8893_buck_data = { + .constraints = { + .name = "max8893_buck", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo1_data = { + .constraints = { + .name = "max8893_ldo1", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo2_data = { + .constraints = { + .name = "max8893_ldo2", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo3_data = { + .constraints = { + .name = "max8893_ldo3", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo4_data = { + .constraints = { + .name = "max8893_ldo4", + .min_uV = 2900000, + .max_uV = 2900000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data herring_max8893_ldo5_data = { + .constraints = { + .name = "max8893_ldo5", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct max8893_subdev_data herring_max8893_subdev_data[] = { + { + .id = MAX8893_BUCK, + .initdata = &herring_max8893_buck_data, + }, + { + .id = MAX8893_LDO1, + .initdata = &herring_max8893_ldo1_data, + }, + { + .id = MAX8893_LDO2, + .initdata = &herring_max8893_ldo2_data, + }, + { + .id = MAX8893_LDO3, + .initdata = &herring_max8893_ldo3_data, + }, + { + .id = MAX8893_LDO4, + .initdata = &herring_max8893_ldo4_data, + }, + { + .id = MAX8893_LDO5, + .initdata = &herring_max8893_ldo5_data, + }, +}; + +static struct max8893_platform_data herring_max8893_pdata = { + .num_subdevs = ARRAY_SIZE(herring_max8893_subdev_data), + .subdevs = herring_max8893_subdev_data, +}; + +static struct i2c_board_info i2c_devs15[] __initdata = { + { + I2C_BOARD_INFO("max8893", 0x3E), + .platform_data = &herring_max8893_pdata, + }, +}; + +static struct wimax_cfg wimax_config; + +static unsigned int wimax_sdio_on_table[][4] = { + {GPIO_WIMAX_SDIO_CLK, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_CMD, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D0, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D1, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D2, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, + {GPIO_WIMAX_SDIO_D3, 2, GPIO_LEVEL_NONE, S3C_GPIO_PULL_UP}, +}; + +static unsigned int wimax_sdio_off_table[][4] = { + {GPIO_WIMAX_SDIO_CLK, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WIMAX_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, +}; + +static int wimax_sdio_en(int onoff) +{ + u32 i; + u32 sdio; + unsigned int (*wimax_gpio_table)[4]; + + wimax_gpio_table = onoff ? wimax_sdio_on_table : wimax_sdio_off_table; + + for (i = 0; i < ARRAY_SIZE(wimax_sdio_on_table); i++) { + sdio = wimax_gpio_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wimax_gpio_table[i][1])); + s3c_gpio_setpull(sdio, wimax_gpio_table[i][3]); + s3c_gpio_set_drvstrength(sdio, S3C_GPIO_DRVSTR_2X); + + if (wimax_gpio_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wimax_gpio_table[i][2]); + } + return 0; +} + +static void wimax_deinit_gpios(void); +/* signal wimax modem to wakeup if asleep */ +static void wimax_wakeup_assert(int enable) +{ + if (herring_is_cdma_wimax_rev(0) || herring_is_cdma_wimax_rev(1)) + gpio_set_value(GPIO_WIMAX_WAKEUP, !enable); + else + gpio_set_value(GPIO_USB_SEL, !enable); +} + +static int get_wimax_sleep_mode(void) +{ + return gpio_get_value(GPIO_WIMAX_IF_MODE1); +} + +static int is_wimax_active(void) +{ + return gpio_get_value(GPIO_WIMAX_CON0); +} + +/* signal AP is active*/ +static void signal_ap_active(int enable) +{ + gpio_set_value(GPIO_WIMAX_CON1, enable); +} + +/* switch USB path to AP */ +void switch_usb_ap(void) +{ + gpio_set_value(GPIO_USB_HS_SEL, 1); + msleep(10); +} + +/* switch USB path to WiMAX */ +void switch_usb_wimax(void) +{ + gpio_set_value(GPIO_USB_HS_SEL, 0); + msleep(10); +} + +void wimax_init_gpios(void) +{ + s3c_gpio_cfgpin(GPIO_WIMAX_RESET_N, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_RESET_N, 0); + + s3c_gpio_cfgpin(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_DBGEN_28V, 0); + + s3c_gpio_cfgpin(GPIO_WIMAX_I2C_CON, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_I2C_CON, 1); + msleep(10); + + if (herring_is_cdma_wimax_rev(0) || herring_is_cdma_wimax_rev(1)) { + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_WIMAX_WAKEUP, S3C_GPIO_OUTPUT); + } else { + /* g_pdata->wimax_int set Input and Pull up */ + s3c_gpio_setpull(GPIO_WIMAX_WAKEUP, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_OUTPUT); + } + wimax_wakeup_assert(0); + + /* + * IDLE, VI setting pin: high for suspend idle, + * low for suspend vi + */ + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE1, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_IF_MODE1, 1); + + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE0, S3C_GPIO_OUTPUT); + + /* IDLE, VI interrupt for WiMAX */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON2, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_WIMAX_CON2, 1);/* active low interrupt */ + + /* PDA Active */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON1, S3C_GPIO_OUTPUT); + s3c_gpio_set_drvstrength(GPIO_WIMAX_CON1, S3C_GPIO_DRVSTR_2X); + signal_ap_active(1); + +} + +static void hw_set_wimax_mode(void) +{ + bool legacy_rev; + + legacy_rev = herring_is_cdma_wimax_rev(0) || + herring_is_cdma_wimax_rev(1); + + switch (wimax_config.wimax_mode) { + case SDIO_MODE: + pr_debug("SDIO MODE"); + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 1); + else + gpio_set_value(GPIO_USB_SEL, 1); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 1); + break; + case WTM_MODE: + case AUTH_MODE: + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 0); + else + gpio_set_value(GPIO_USB_SEL, 0); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 0); + break; + case DM_MODE: + pr_debug("DM MODE"); + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 1); + else + gpio_set_value(GPIO_USB_SEL, 1); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 0); + break; + case USB_MODE: + case USIM_RELAY_MODE: + pr_debug("USB MODE"); + if (legacy_rev) + gpio_set_value(GPIO_WIMAX_WAKEUP, 0); + else + gpio_set_value(GPIO_USB_SEL, 0); + gpio_set_value(GPIO_WIMAX_IF_MODE0, 1); + break; + } +} + +void wimax_hsmmc_presence_check(void) +{ + sdhci_s3c_force_presence_change(&s3c_device_hsmmc2); +} + +int gpio_wimax_power(int enable) +{ + if (!enable) + goto wimax_power_off; + + if (gpio_get_value(GPIO_WIMAX_EN)) { + pr_debug("Already Wimax powered ON"); + return WIMAX_ALREADY_POWER_ON; + } + /* wait for sdio remove complete*/ + while (!wimax_config.card_removed) + msleep(100); + + pr_debug("Wimax power ON"); + + wimax_sdio_en(1); + wimax_init_gpios(); + + if (wimax_config.wimax_mode != SDIO_MODE) + switch_usb_wimax(); + + gpio_set_value(GPIO_WIMAX_I2C_CON, 1); + msleep(10); + + gpio_set_value(GPIO_WIMAX_EN, 1); + + msleep(10); + pr_debug("RESET"); + + gpio_set_value(GPIO_WIMAX_RESET_N, 1); + + /* Delay important for bootloader initialization */ + msleep(1800); + + /*Dont force detect if the card is already detected*/ + if (wimax_config.card_removed) + wimax_hsmmc_presence_check(); + + return WIMAX_POWER_SUCCESS; + +wimax_power_off: + /*Wait for modem to flush EEPROM data*/ + msleep(500); + wimax_deinit_gpios(); + + pr_debug("Wimax power OFF"); + + /*Dont force detect if the card is already detected as removed*/ + if (!wimax_config.card_removed) + wimax_hsmmc_presence_check(); + + /*Not critial, just some safty margin*/ + msleep(300); + wimax_sdio_en(0); + + return WIMAX_POWER_SUCCESS; +} + +static struct wimax732_platform_data wimax732_pdata = { + .power = gpio_wimax_power, + .set_mode = hw_set_wimax_mode, + .signal_ap_active = signal_ap_active, + .get_sleep_mode = get_wimax_sleep_mode, + .is_modem_awake = is_wimax_active, + .wakeup_assert = wimax_wakeup_assert, + .g_cfg = &wimax_config, + .wimax_int = GPIO_USB_SEL, /* GPIO_USB_SEL,*/ +}; + +static struct platform_device s3c_device_cmc732 = { + .name = "wimax732_driver", + .id = 1, + .dev.platform_data = &wimax732_pdata, +}; + +void wimax_deinit_gpios(void) +{ + /* Disable WiMAX JTAG for freerun */ + s3c_gpio_cfgpin(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_PULL_NONE); + + /* g_pdata->wimax_int set Output low */ + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_NONE); + + /* MODE pin */ + s3c_gpio_cfgpin(GPIO_WIMAX_WAKEUP, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_WAKEUP, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_IF_MODE0, S3C_GPIO_PULL_NONE); + + /* WiMAX active */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON0, S3C_GPIO_PULL_NONE); + + /* IDLE, VI setting pin: high for suspend idle, + low for suspend vi */ + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE1, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_IF_MODE1, S3C_GPIO_PULL_NONE); + + /* IDLE, VI interrupt for WiMAX */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON2, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON2, S3C_GPIO_PULL_NONE); + + /* PDA Active */ + s3c_gpio_cfgpin(GPIO_WIMAX_CON1, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON1, S3C_GPIO_PULL_NONE); + + /* power related */ + s3c_gpio_cfgpin(GPIO_WIMAX_RESET_N, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_RESET_N, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WIMAX_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_EN, S3C_GPIO_PULL_NONE); + + /* EEPROM switch to WiMAX */ + s3c_gpio_cfgpin(GPIO_WIMAX_I2C_CON, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_I2C_CON, S3C_GPIO_PULL_NONE); + + gpio_set_value(GPIO_WIMAX_EN, 0); + s3c_gpio_cfgpin(GPIO_WIMAX_I2C_CON, S3C_GPIO_INPUT); + + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_UART_SEL1, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL1, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_USB_HS_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_USB_HS_SEL, S3C_GPIO_PULL_NONE); + switch_usb_ap(); + + if (herring_is_cdma_wimax_rev(0) || herring_is_cdma_wimax_rev(1)) + wimax732_pdata.wimax_int = GPIO_USB_SEL; + else + wimax732_pdata.wimax_int = GPIO_WIMAX_WAKEUP; +} + +static void touch_keypad_gpio_init(void) +{ + int ret = 0; + + ret = gpio_request(_3_GPIO_TOUCH_EN, "TOUCH_EN"); + if (ret) + printk(KERN_ERR "Failed to request gpio touch_en.\n"); +} + +static void touch_keypad_onoff(int onoff) +{ + gpio_direction_output(_3_GPIO_TOUCH_EN, onoff); + + if (onoff == TOUCHKEY_OFF) + msleep(30); + else + msleep(50); +} + +static void touch_keypad_gpio_sleep(int onoff) +{ + if (onoff == TOUCHKEY_ON) { + /* + * reconfigure gpio to activate touchkey controller vdd in sleep mode + */ + s3c_gpio_slp_cfgpin(_3_GPIO_TOUCH_EN, S3C_GPIO_SLP_OUT1); + //s3c_gpio_slp_setpull_updown(_3_GPIO_TOUCH_EN, S3C_GPIO_PULL_NONE); + } else { + /* + * reconfigure gpio to deactivate touchkey vdd in sleep mode, + * this is the default + */ + s3c_gpio_slp_cfgpin(_3_GPIO_TOUCH_EN, S3C_GPIO_SLP_OUT0); + //s3c_gpio_slp_setpull_updown(_3_GPIO_TOUCH_EN, S3C_GPIO_PULL_NONE); + } + +} + +static const int touch_keypad_code[] = { + KEY_MENU, + KEY_HOME, + KEY_BACK, + KEY_SEARCH +}; + +static struct touchkey_platform_data touchkey_data = { + .keycode_cnt = ARRAY_SIZE(touch_keypad_code), + .keycode = touch_keypad_code, + .touchkey_onoff = touch_keypad_onoff, + .touchkey_sleep_onoff = touch_keypad_gpio_sleep, + .fw_name = "cypress-touchkey.bin", + .scl_pin = _3_TOUCH_SCL_28V, + .sda_pin = _3_TOUCH_SDA_28V, + .en_pin = _3_GPIO_TOUCH_EN, +}; + +static struct gpio_event_direct_entry herring_keypad_key_map[] = { + { + .gpio = S5PV210_GPH2(6), + .code = KEY_POWER, + }, + { + .gpio = S5PV210_GPH3(1), + .code = KEY_VOLUMEDOWN, + }, + { + .gpio = S5PV210_GPH3(2), + .code = KEY_VOLUMEUP, + } +}; + +static struct gpio_event_input_info herring_keypad_key_info = { + .info.func = gpio_event_input_func, + .info.no_suspend = true, + .debounce_time.tv64 = 5 * NSEC_PER_MSEC, + .type = EV_KEY, + .keymap = herring_keypad_key_map, + .keymap_size = ARRAY_SIZE(herring_keypad_key_map) +}; + +static struct gpio_event_info *herring_input_info[] = { + &herring_keypad_key_info.info, +}; + + +static struct gpio_event_platform_data herring_input_data = { + .names = { + "herring-keypad", + NULL, + }, + .info = herring_input_info, + .info_count = ARRAY_SIZE(herring_input_info), +}; + +static struct platform_device herring_input_device = { + .name = GPIO_EVENT_DEV_NAME, + .id = 0, + .dev = { + .platform_data = &herring_input_data, + }, +}; + +#ifdef CONFIG_S5P_ADC +static struct s3c_adc_mach_info s3c_adc_platform __initdata = { + /* s5pc110 support 12-bit resolution */ + .delay = 10000, + .presc = 65, + .resolution = 12, +}; +#endif + +/* in revisions before 0.9, there is a common mic bias gpio */ + +static DEFINE_SPINLOCK(mic_bias_lock); +static bool wm8994_mic_bias; +static bool jack_mic_bias; +static void set_shared_mic_bias(void) +{ + gpio_set_value(GPIO_MICBIAS_EN, wm8994_mic_bias || jack_mic_bias); +} + +static void wm8994_set_mic_bias(bool on) +{ + if (system_rev < 0x09) { + unsigned long flags; + spin_lock_irqsave(&mic_bias_lock, flags); + wm8994_mic_bias = on; + set_shared_mic_bias(); + spin_unlock_irqrestore(&mic_bias_lock, flags); + } else + gpio_set_value(GPIO_MICBIAS_EN, on); +} + +static void sec_jack_set_micbias_state(bool on) +{ + if (system_rev < 0x09) { + unsigned long flags; + spin_lock_irqsave(&mic_bias_lock, flags); + jack_mic_bias = on; + set_shared_mic_bias(); + spin_unlock_irqrestore(&mic_bias_lock, flags); + } else + gpio_set_value(GPIO_EAR_MICBIAS_EN, on); +} + +static struct wm8994_platform_data wm8994_pdata = { + .ldo = GPIO_CODEC_LDO_EN, + .ear_sel = GPIO_EAR_SEL, + .set_mic_bias = wm8994_set_mic_bias, +}; + +/* + * Guide for Camera Configuration for Crespo board + * ITU CAM CH A: LSI s5k4ecgx + */ +static DEFINE_MUTEX(s5k4ecgx_lock); +static struct regulator *cam_isp_core_regulator; +static struct regulator *cam_isp_host_regulator; +static struct regulator *cam_af_regulator; +static bool s5k4ecgx_powered_on; +static int s5k4ecgx_regulator_init(void) +{ + if (IS_ERR_OR_NULL(cam_isp_core_regulator)) { + cam_isp_core_regulator = regulator_get(NULL, "cam_isp_core"); + if (IS_ERR_OR_NULL(cam_isp_core_regulator)) { + pr_err("failed to get cam_isp_core regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_isp_host_regulator)) { + cam_isp_host_regulator = regulator_get(NULL, "cam_isp_host"); + if (IS_ERR_OR_NULL(cam_isp_host_regulator)) { + pr_err("failed to get cam_isp_host regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_af_regulator)) { + cam_af_regulator = regulator_get(NULL, "cam_af"); + if (IS_ERR_OR_NULL(cam_af_regulator)) { + pr_err("failed to get cam_af regulator"); + return -EINVAL; + } + } + pr_debug("cam_isp_core_regulator = %p\n", cam_isp_core_regulator); + pr_debug("cam_isp_host_regulator = %p\n", cam_isp_host_regulator); + pr_debug("cam_af_regulator = %p\n", cam_af_regulator); + return 0; +} + +static void s5k4ecgx_init(void) +{ + /* CAM_IO_EN - GPB(7) */ + if (gpio_request(GPIO_GPB7, "GPB7") < 0) + pr_err("failed gpio_request(GPB7) for camera control\n"); + /* CAM_MEGA_nRST - GPJ1(5) */ + if (gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1") < 0) + pr_err("failed gpio_request(GPJ1) for camera control\n"); + /* CAM_MEGA_EN - GPJ0(6) */ + if (gpio_request(GPIO_CAM_MEGA_EN, "GPJ0") < 0) + pr_err("failed gpio_request(GPJ0) for camera control\n"); + /* FLASH_EN - GPJ1(2) */ + if (gpio_request(GPIO_FLASH_EN, "GPIO_FLASH_EN") < 0) + pr_err("failed gpio_request(GPIO_FLASH_EN)\n"); + /* FLASH_EN_SET - GPJ1(0) */ + if (gpio_request(GPIO_CAM_FLASH_EN_SET, "GPIO_CAM_FLASH_EN_SET") < 0) + pr_err("failed gpio_request(GPIO_CAM_FLASH_EN_SET)\n"); +} + +static int s5k4ecgx_ldo_en(bool en) +{ + int err = 0; + int result; + + if (IS_ERR_OR_NULL(cam_isp_core_regulator) || + IS_ERR_OR_NULL(cam_isp_host_regulator) || + IS_ERR_OR_NULL(cam_af_regulator)) { + pr_err("Camera regulators not initialized\n"); + return -EINVAL; + } + + if (!en) + goto off; + + /* Turn CAM_ISP_CORE_1.2V(VDD_REG) on */ + err = regulator_enable(cam_isp_core_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + mdelay(1); + + /* Turn CAM_SENSOR_A_2.8V(VDDA) on */ + gpio_set_value(GPIO_GPB7, 1); + mdelay(1); + + /* Turn CAM_ISP_HOST_2.8V(VDDIO) on */ + err = regulator_enable(cam_isp_host_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + udelay(50); + + /* Turn CAM_AF_2.8V or 3.0V on */ + err = regulator_enable(cam_af_regulator); + if (err) { + pr_err("Failed to enable regulator cam_isp_core\n"); + goto off; + } + udelay(50); + return 0; + +off: + result = err; + err = regulator_disable(cam_af_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + err = regulator_disable(cam_isp_host_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + gpio_set_value(GPIO_GPB7, 0); + err = regulator_disable(cam_isp_core_regulator); + if (err) { + pr_err("Failed to disable regulator cam_isp_core\n"); + result = err; + } + return result; +} + +static int s5k4ecgx_power_on(void) +{ + /* LDO on */ + int err; + + /* can't do this earlier because regulators aren't available in + * early boot + */ + if (s5k4ecgx_regulator_init()) { + pr_err("Failed to initialize camera regulators\n"); + return -EINVAL; + } + + err = s5k4ecgx_ldo_en(true); + if (err) + return err; + mdelay(66); + + /* MCLK on - default is input, to save power when camera not on */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(GPIO_CAM_MCLK_AF)); + mdelay(1); + + /* CAM_MEGA_EN - GPJ1(2) LOW */ + gpio_set_value(GPIO_CAM_MEGA_EN, 1); + mdelay(1); + + /* CAM_MEGA_nRST - GPJ1(5) LOW */ + gpio_set_value(GPIO_CAM_MEGA_nRST, 1); + mdelay(1); + + return 0; +} + +static int s5k4ecgx_power_off(void) +{ + /* CAM_MEGA_nRST - GPJ1(5) LOW */ + gpio_set_value(GPIO_CAM_MEGA_nRST, 0); + udelay(60); + + /* Mclk disable - set to input function to save power */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + udelay(10); + + /* CAM_MEGA_EN - GPJ1(2) LOW */ + gpio_set_value(GPIO_CAM_MEGA_EN, 0); + udelay(10); + + s5k4ecgx_ldo_en(false); + mdelay(1); + + return 0; +} + +static int s5k4ecgx_power_en(int onoff) +{ + int err = 0; + mutex_lock(&s5k4ecgx_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != s5k4ecgx_powered_on) { + if (onoff) + err = s5k4ecgx_power_on(); + else + err = s5k4ecgx_power_off(); + if (!err) + s5k4ecgx_powered_on = onoff; + } + mutex_unlock(&s5k4ecgx_lock); + return err; +} + +#define FLASH_MOVIE_MODE_CURRENT_50_PERCENT 7 + +#define FLASH_TIME_LATCH_US 500 +#define FLASH_TIME_EN_SET_US 1 + +/* The AAT1274 uses a single wire interface to write data to its + * control registers. An incoming value is written by sending a number + * of rising edges to EN_SET. Data is 4 bits, or 1-16 pulses, and + * addresses are 17 pulses or more. Data written without an address + * controls the current to the LED via the default address 17. */ +static void aat1274_write(int value) +{ + while (value--) { + gpio_set_value(GPIO_CAM_FLASH_EN_SET, 0); + udelay(FLASH_TIME_EN_SET_US); + gpio_set_value(GPIO_CAM_FLASH_EN_SET, 1); + udelay(FLASH_TIME_EN_SET_US); + } + udelay(FLASH_TIME_LATCH_US); + /* At this point, the LED will be on */ +} + +static int aat1274_flash(int enable) +{ + /* Turn main flash on or off by asserting a value on the EN line. */ + gpio_set_value(GPIO_FLASH_EN, !!enable); + + return 0; +} + +static int aat1274_af_assist(int enable) +{ + /* Turn assist light on or off by asserting a value on the EN_SET + * line. The default illumination level of 1/7.3 at 100% is used */ + gpio_set_value(GPIO_CAM_FLASH_EN_SET, !!enable); + if (!enable) + gpio_set_value(GPIO_FLASH_EN, 0); + + return 0; +} + +static int aat1274_torch(int enable) +{ + /* Turn torch mode on or off by writing to the EN_SET line. A level + * of 1/7.3 and 50% is used (half AF assist brightness). */ + if (enable) { + aat1274_write(FLASH_MOVIE_MODE_CURRENT_50_PERCENT); + } else { + gpio_set_value(GPIO_CAM_FLASH_EN_SET, 0); + gpio_set_value(GPIO_FLASH_EN, 0); + } + + return 0; +} + +static struct s5k4ecgx_platform_data s5k4ecgx_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .flash_onoff = &aat1274_flash, + .af_assist_onoff = &aat1274_af_assist, + .torch_onoff = &aat1274_torch, +}; + +static struct i2c_board_info s5k4ecgx_i2c_info = { + I2C_BOARD_INFO("S5K4ECGX", 0x5A>>1), + .platform_data = &s5k4ecgx_plat, +}; + +static struct s3c_platform_camera s5k4ecgx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &s5k4ecgx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 1920, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, + .cam_power = s5k4ecgx_power_en, +}; + + +/* External camera module setting */ +static DEFINE_MUTEX(s5ka3dfx_lock); +static struct regulator *s5ka3dfx_vga_avdd; +static struct regulator *s5ka3dfx_vga_vddio; +static struct regulator *s5ka3dfx_cam_isp_host; +static struct regulator *s5ka3dfx_vga_dvdd; +static bool s5ka3dfx_powered_on; + +static int s5ka3dfx_request_gpio(void) +{ + int err; + + /* CAM_VGA_nSTBY - GPB(0) */ + err = gpio_request(GPIO_CAM_VGA_nSTBY, "GPB0"); + if (err) { + pr_err("Failed to request GPB0 for camera control\n"); + return -EINVAL; + } + + /* CAM_VGA_nRST - GPB(2) */ + err = gpio_request(GPIO_CAM_VGA_nRST, "GPB2"); + if (err) { + pr_err("Failed to request GPB2 for camera control\n"); + gpio_free(GPIO_CAM_VGA_nSTBY); + return -EINVAL; + } + + return 0; +} + +static int s5ka3dfx_power_init(void) +{ + if (IS_ERR_OR_NULL(s5ka3dfx_vga_avdd)) + s5ka3dfx_vga_avdd = regulator_get(NULL, "vga_avdd"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_avdd)) { + pr_err("Failed to get regulator vga_avdd\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_vddio)) + s5ka3dfx_vga_vddio = regulator_get(NULL, "vga_vddio"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_vddio)) { + pr_err("Failed to get regulator vga_vddio\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_cam_isp_host)) + s5ka3dfx_cam_isp_host = regulator_get(NULL, "cam_isp_host"); + + if (IS_ERR_OR_NULL(s5ka3dfx_cam_isp_host)) { + pr_err("Failed to get regulator cam_isp_host\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_dvdd)) + s5ka3dfx_vga_dvdd = regulator_get(NULL, "vga_dvdd"); + + if (IS_ERR_OR_NULL(s5ka3dfx_vga_dvdd)) { + pr_err("Failed to get regulator vga_dvdd\n"); + return -EINVAL; + } + + return 0; +} + +static int s5ka3dfx_power_on(void) +{ + int err = 0; + int result; + + if (s5ka3dfx_power_init()) { + pr_err("Failed to get all regulator\n"); + return -EINVAL; + } + + /* Turn VGA_AVDD_2.8V on */ + err = regulator_enable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to enable regulator vga_avdd\n"); + return -EINVAL; + } + msleep(3); + + /* Turn VGA_VDDIO_2.8V on */ + err = regulator_enable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to enable regulator vga_vddio\n"); + goto off_vga_vddio; + } + udelay(20); + + /* Turn VGA_DVDD_1.8V on */ + err = regulator_enable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to enable regulator vga_dvdd\n"); + goto off_vga_dvdd; + } + udelay(100); + + /* CAM_VGA_nSTBY HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 1); + + udelay(10); + + /* Mclk enable */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(0x02)); + udelay(430); + + /* Turn CAM_ISP_HOST_2.8V on */ + err = regulator_enable(s5ka3dfx_cam_isp_host); + if (err) { + pr_err("Failed to enable regulator cam_isp_host\n"); + goto off_cam_isp_host; + } + udelay(150); + + /* CAM_VGA_nRST HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + gpio_set_value(GPIO_CAM_VGA_nRST, 1); + mdelay(5); + + return 0; +off_cam_isp_host: + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + udelay(1); + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + udelay(1); + err = regulator_disable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to disable regulator vga_dvdd\n"); + result = err; + } +off_vga_dvdd: + err = regulator_disable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to disable regulator vga_vddio\n"); + result = err; + } +off_vga_vddio: + err = regulator_disable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to disable regulator vga_avdd\n"); + result = err; + } + + return result; +} + +static int s5ka3dfx_power_off(void) +{ + int err; + + if (!s5ka3dfx_vga_avdd || !s5ka3dfx_vga_vddio || + !s5ka3dfx_cam_isp_host || !s5ka3dfx_vga_dvdd) { + pr_err("Faild to get all regulator\n"); + return -EINVAL; + } + + /* Turn CAM_ISP_HOST_2.8V off */ + err = regulator_disable(s5ka3dfx_cam_isp_host); + if (err) { + pr_err("Failed to disable regulator cam_isp_host\n"); + return -EINVAL; + } + + /* CAM_VGA_nRST LOW */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 1); + gpio_set_value(GPIO_CAM_VGA_nRST, 0); + udelay(430); + + /* Mclk disable */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + + udelay(1); + + /* Turn VGA_VDDIO_2.8V off */ + err = regulator_disable(s5ka3dfx_vga_vddio); + if (err) { + pr_err("Failed to disable regulator vga_vddio\n"); + return -EINVAL; + } + + /* Turn VGA_DVDD_1.8V off */ + err = regulator_disable(s5ka3dfx_vga_dvdd); + if (err) { + pr_err("Failed to disable regulator vga_dvdd\n"); + return -EINVAL; + } + + /* CAM_VGA_nSTBY LOW */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + + udelay(1); + + /* Turn VGA_AVDD_2.8V off */ + err = regulator_disable(s5ka3dfx_vga_avdd); + if (err) { + pr_err("Failed to disable regulator vga_avdd\n"); + return -EINVAL; + } + + return err; +} + +static int s5ka3dfx_power_en(int onoff) +{ + int err = 0; + mutex_lock(&s5ka3dfx_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != s5ka3dfx_powered_on) { + if (onoff) + err = s5ka3dfx_power_on(); + else { + err = s5ka3dfx_power_off(); + s3c_i2c0_force_stop(); + } + if (!err) + s5ka3dfx_powered_on = onoff; + } + mutex_unlock(&s5ka3dfx_lock); + + return err; +} + +static struct s5ka3dfx_platform_data s5ka3dfx_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 0, + + .cam_power = s5ka3dfx_power_en, +}; + +static struct i2c_board_info s5ka3dfx_i2c_info = { + I2C_BOARD_INFO("S5KA3DFX", 0xc4>>1), + .platform_data = &s5ka3dfx_plat, +}; + +static struct s3c_platform_camera s5ka3dfx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &s5ka3dfx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 480, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, + .cam_power = s5ka3dfx_power_en, +}; + +/* Interface setting */ +static struct s3c_platform_fimc fimc_plat_lsi = { + .srclk_name = "mout_mpll", + .clk_name = "sclk_fimc", + .lclk_name = "fimc", + .clk_rate = 166750000, + .default_cam = CAMERA_PAR_A, + .camera = { + &s5k4ecgx, + &s5ka3dfx, + }, + .hw_ver = 0x43, +}; + +#ifdef CONFIG_VIDEO_JPEG_V2 +static struct s3c_platform_jpeg jpeg_plat __initdata = { + .max_main_width = 800, + .max_main_height = 480, + .max_thumb_width = 320, + .max_thumb_height = 240, +}; +#endif + +static struct k3g_platform_data k3g_pdata = { + .axis_map_x = 1, + .axis_map_y = 1, + .axis_map_z = 1, + .negate_x = 0, + .negate_y = 0, + .negate_z = 0, +}; + +/* I2C0 */ +static struct i2c_board_info i2c_devs0[] __initdata = { + { + I2C_BOARD_INFO("k3g", 0x69), + .platform_data = &k3g_pdata, + }, +}; + +static struct i2c_board_info i2c_devs4[] __initdata = { + { + I2C_BOARD_INFO("wm8994-samsung", (0x34>>1)), + .platform_data = &wm8994_pdata, + }, +}; + +static struct akm8973_platform_data akm8973_pdata = { + .reset_line = GPIO_MSENSE_nRST, + .reset_asserted = GPIO_LEVEL_LOW, + .gpio_data_ready_int = GPIO_MSENSE_IRQ, +}; + +static struct kr3dm_platform_data kr3dm_data = { + .gpio_acc_int = GPIO_ACC_INT, +}; + +/* I2C1 */ +static struct i2c_board_info i2c_devs1[] __initdata = { + { + I2C_BOARD_INFO("ak8973", 0x1c), + .platform_data = &akm8973_pdata, + }, + { + I2C_BOARD_INFO("kr3dm", 0x09), + .platform_data = &kr3dm_data, + }, +}; + +static void mxt224_power_on(void) +{ + gpio_direction_output(GPIO_TOUCH_EN, 1); + + mdelay(40); +} + +static void mxt224_power_off(void) +{ + gpio_direction_output(GPIO_TOUCH_EN, 0); +} + +#define MXT224_MAX_MT_FINGERS 5 + +static u8 t7_config[] = {GEN_POWERCONFIG_T7, + 64, 255, 50}; +static u8 t8_config[] = {GEN_ACQUISITIONCONFIG_T8, + 7, 0, 5, 0, 0, 0, 9, 35}; +static u8 t9_config[] = {TOUCH_MULTITOUCHSCREEN_T9, + 139, 0, 0, 19, 11, 0, 32, 25, 2, 1, 25, 3, 1, + 46, MXT224_MAX_MT_FINGERS, 5, 14, 10, 255, 3, + 255, 3, 18, 18, 10, 10, 141, 65, 143, 110, 18}; +static u8 t18_config[] = {SPT_COMCONFIG_T18, + 0, 1}; +static u8 t20_config[] = {PROCI_GRIPFACESUPPRESSION_T20, + 7, 0, 0, 0, 0, 0, 0, 80, 40, 4, 35, 10}; +static u8 t22_config[] = {PROCG_NOISESUPPRESSION_T22, + 5, 0, 0, 0, 0, 0, 0, 3, 30, 0, 0, 29, 34, 39, + 49, 58, 3}; +static u8 t28_config[] = {SPT_CTECONFIG_T28, + 1, 0, 3, 16, 63, 60}; +static u8 end_config[] = {RESERVED_T255}; + +static const u8 *mxt224_config[] = { + t7_config, + t8_config, + t9_config, + t18_config, + t20_config, + t22_config, + t28_config, + end_config, +}; + +static struct mxt224_platform_data mxt224_data = { + .max_finger_touches = MXT224_MAX_MT_FINGERS, + .gpio_read_done = GPIO_TOUCH_INT, + .config = mxt224_config, + .min_x = 0, + .max_x = 1023, + .min_y = 0, + .max_y = 1023, + .min_z = 0, + .max_z = 255, + .min_w = 0, + .max_w = 30, + .power_on = mxt224_power_on, + .power_off = mxt224_power_off, +}; + +/* I2C2 */ +static struct i2c_board_info i2c_devs2[] __initdata = { + { + I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a), + .platform_data = &mxt224_data, + .irq = IRQ_EINT_GROUP(18, 5), + }, +}; + +static void mxt224_init(void) +{ + if (!herring_is_tft_dev()) + return; + mxt224_data.max_y = 950; + t9_config[8] = 45; + t9_config[9] = 3; + t9_config[23] = 0; + t9_config[24] = 0; + t9_config[27] = 0; + t9_config[28] = 0; + t9_config[29] = 0; + t9_config[30] = 0; +} + +static ssize_t herring_virtual_keys_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, + __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":71:839:73:62" + ":" __stringify(EV_KEY) ":" + __stringify(KEY_MENU) ":183:839:73:62" + ":" __stringify(EV_KEY) ":" + __stringify(KEY_SEARCH) ":294:839:73:62" + ":" __stringify(EV_KEY) ":" + __stringify(KEY_HOME) ":406:839:73:62" + "\n"); +} + +static struct kobj_attribute herring_virtual_keys_attr = { + .attr = { + .name = "virtualkeys.mxt224_ts_input", + .mode = S_IRUGO, + }, + .show = &herring_virtual_keys_show, +}; + +static struct attribute *herring_properties_attrs[] = { + &herring_virtual_keys_attr.attr, + NULL, +}; + +static struct attribute_group herring_properties_attr_group = { + .attrs = herring_properties_attrs, +}; + +static void herring_virtual_keys_init(void) +{ + struct kobject *properties_kobj; + int ret; + + properties_kobj = kobject_create_and_add("board_properties", NULL); + if (properties_kobj) + ret = sysfs_create_group(properties_kobj, + &herring_properties_attr_group); + if (!properties_kobj || ret) + pr_err("failed to create board_properties\n"); +} + +/* I2C2 */ +static struct i2c_board_info i2c_devs10[] __initdata = { + { + I2C_BOARD_INFO(CYPRESS_TOUCHKEY_DEV_NAME, 0x20), + .platform_data = &touchkey_data, + .irq = (IRQ_EINT_GROUP22_BASE + 1), + }, +}; + +static struct i2c_board_info i2c_devs5[] __initdata = { + { + I2C_BOARD_INFO("kr3dm", 0x09), + .platform_data = &kr3dm_data, + }, +}; + +static struct i2c_board_info i2c_devs8[] __initdata = { + { + I2C_BOARD_INFO("k3g", 0x69), + .platform_data = &k3g_pdata, + .irq = -1, + }, +}; + +static void k3g_irq_init(void) +{ + i2c_devs0[0].irq = (system_rev >= 0x0A) ? IRQ_EINT(29) : -1; +} + + +static void fsa9480_usb_cb(bool attached) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + if (gadget) { + if (attached) + usb_gadget_vbus_connect(gadget); + else + usb_gadget_vbus_disconnect(gadget); + } + + set_cable_status = attached ? CABLE_TYPE_USB : CABLE_TYPE_NONE; + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static void fsa9480_charger_cb(bool attached) +{ + set_cable_status = attached ? CABLE_TYPE_AC : CABLE_TYPE_NONE; + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static struct switch_dev switch_dock = { + .name = "dock", +}; + +static void fsa9480_deskdock_cb(bool attached) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + if (attached) + switch_set_state(&switch_dock, 1); + else + switch_set_state(&switch_dock, 0); + + if (gadget) { + if (attached) + usb_gadget_vbus_connect(gadget); + else + usb_gadget_vbus_disconnect(gadget); + } + + set_cable_status = attached ? CABLE_TYPE_USB : CABLE_TYPE_NONE; + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); +} + +static void fsa9480_cardock_cb(bool attached) +{ + if (attached) + switch_set_state(&switch_dock, 2); + else + switch_set_state(&switch_dock, 0); +} + +static void fsa9480_reset_cb(void) +{ + int ret; + + /* for CarDock, DeskDock */ + ret = switch_dev_register(&switch_dock); + if (ret < 0) + pr_err("Failed to register dock switch. %d\n", ret); +} + +static struct fsa9480_platform_data fsa9480_pdata = { + .usb_cb = fsa9480_usb_cb, + .charger_cb = fsa9480_charger_cb, + .deskdock_cb = fsa9480_deskdock_cb, + .cardock_cb = fsa9480_cardock_cb, + .reset_cb = fsa9480_reset_cb, +}; + +static struct i2c_board_info i2c_devs7[] __initdata = { + { + I2C_BOARD_INFO("fsa9480", 0x4A >> 1), + .platform_data = &fsa9480_pdata, + .irq = IRQ_EINT(23), + }, +}; + +static struct i2c_board_info i2c_devs6[] __initdata = { +#ifdef CONFIG_REGULATOR_MAX8998 + { + /* The address is 0xCC used since SRAD = 0 */ + I2C_BOARD_INFO("max8998", (0xCC >> 1)), + .platform_data = &max8998_pdata, + .irq = IRQ_EINT7, + }, { + I2C_BOARD_INFO("rtc_max8998", (0x0D >> 1)), + }, +#endif +}; + +static struct pn544_i2c_platform_data pn544_pdata = { + .irq_gpio = NFC_IRQ, + .ven_gpio = NFC_EN, + .firm_gpio = NFC_FIRM, +}; + +static struct i2c_board_info i2c_devs14[] __initdata = { + { + I2C_BOARD_INFO("pn544", 0x2b), + .irq = IRQ_EINT(12), + .platform_data = &pn544_pdata, + }, +}; + +static int max17040_power_supply_register(struct device *parent, + struct power_supply *psy) +{ + herring_charger.psy_fuelgauge = psy; + return 0; +} + +static void max17040_power_supply_unregister(struct power_supply *psy) +{ + herring_charger.psy_fuelgauge = NULL; +} + +static struct max17040_platform_data max17040_pdata = { + .power_supply_register = max17040_power_supply_register, + .power_supply_unregister = max17040_power_supply_unregister, + .rcomp_value = 0xD700, +}; + +static struct i2c_board_info i2c_devs9[] __initdata = { + { + I2C_BOARD_INFO("max17040", (0x6D >> 1)), + .platform_data = &max17040_pdata, + }, +}; + +static void gp2a_gpio_init(void) +{ + int ret = gpio_request(GPIO_PS_ON, "gp2a_power_supply_on"); + if (ret) + printk(KERN_ERR "Failed to request gpio gp2a power supply.\n"); +} + +static int gp2a_power(bool on) +{ + /* this controls the power supply rail to the gp2a IC */ + gpio_direction_output(GPIO_PS_ON, on); + return 0; +} + +static int gp2a_light_adc_value(void) +{ + return s3c_adc_get_adc_data(9); +} + +static struct gp2a_platform_data gp2a_pdata = { + .power = gp2a_power, + .p_out = GPIO_PS_VOUT, + .light_adc_value = gp2a_light_adc_value, + .light_adc_max = 4095, + .light_adc_fuzz = 64, +}; + +static struct i2c_board_info i2c_devs11[] __initdata = { + { + I2C_BOARD_INFO("gp2a", (0x88 >> 1)), + .platform_data = &gp2a_pdata, + }, +}; + +static struct i2c_board_info i2c_devs12[] __initdata = { + { + I2C_BOARD_INFO("ak8973", 0x1c), + .platform_data = &akm8973_pdata, + }, +}; + +static struct resource ram_console_resource[] = { + { + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ram_console_device = { + .name = "ram_console", + .id = -1, + .num_resources = ARRAY_SIZE(ram_console_resource), + .resource = ram_console_resource, +}; + +#ifdef CONFIG_ANDROID_PMEM +static struct android_pmem_platform_data pmem_pdata = { + .name = "pmem", + .no_allocator = 1, + .cached = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_gpu1_pdata = { + .name = "pmem_gpu1", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_adsp_pdata = { + .name = "pmem_adsp", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct platform_device pmem_device = { + .name = "android_pmem", + .id = 0, + .dev = { .platform_data = &pmem_pdata }, +}; + +static struct platform_device pmem_gpu1_device = { + .name = "android_pmem", + .id = 1, + .dev = { .platform_data = &pmem_gpu1_pdata }, +}; + +static struct platform_device pmem_adsp_device = { + .name = "android_pmem", + .id = 2, + .dev = { .platform_data = &pmem_adsp_pdata }, +}; + +static void __init android_pmem_set_platdata(void) +{ + pmem_pdata.start = (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM, 0); + pmem_pdata.size = (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM, 0); + + pmem_gpu1_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_GPU1, 0); + pmem_gpu1_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_GPU1, 0); + + pmem_adsp_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_ADSP, 0); + pmem_adsp_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_ADSP, 0); +} +#endif + +struct platform_device sec_device_battery = { + .name = "sec-battery", + .id = -1, +}; + +static struct platform_device sec_device_rfkill = { + .name = "bt_rfkill", + .id = -1, +}; + +static struct platform_device sec_device_btsleep = { + .name = "bt_sleep", + .id = -1, +}; + +static struct sec_jack_zone sec_jack_zones[] = { + { + /* adc == 0, unstable zone, default to 3pole if it stays + * in this range for a half second (20ms delays, 25 samples) + */ + .adc_high = 0, + .delay_ms = 20, + .check_count = 25, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 0 < adc <= 1000, unstable zone, default to 3pole if it stays + * in this range for a second (10ms delays, 100 samples) + */ + .adc_high = 1000, + .delay_ms = 10, + .check_count = 100, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 1000 < adc <= 2000, unstable zone, default to 4pole if it + * stays in this range for a second (10ms delays, 100 samples) + */ + .adc_high = 2000, + .delay_ms = 10, + .check_count = 100, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* 2000 < adc <= 3700, 4 pole zone, default to 4pole if it + * stays in this range for 200ms (20ms delays, 10 samples) + */ + .adc_high = 3700, + .delay_ms = 20, + .check_count = 10, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* adc > 3700, unstable zone, default to 3pole if it stays + * in this range for a second (10ms delays, 100 samples) + */ + .adc_high = 0x7fffffff, + .delay_ms = 10, + .check_count = 100, + .jack_type = SEC_HEADSET_3POLE, + }, +}; + +/* To support 3-buttons earjack */ +static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = { + { + /* 0 <= adc <=110, stable zone */ + .code = KEY_MEDIA, + .adc_low = 0, + .adc_high = 110, + }, + { + /* 130 <= adc <= 365, stable zone */ + .code = KEY_PREVIOUSSONG, + .adc_low = 130, + .adc_high = 365, + }, + { + /* 385 <= adc <= 870, stable zone */ + .code = KEY_NEXTSONG, + .adc_low = 385, + .adc_high = 870, + }, +}; + +static int sec_jack_get_adc_value(void) +{ + return s3c_adc_get_adc_data(3); +} + +struct sec_jack_platform_data sec_jack_pdata = { + .set_micbias_state = sec_jack_set_micbias_state, + .get_adc_value = sec_jack_get_adc_value, + .zones = sec_jack_zones, + .num_zones = ARRAY_SIZE(sec_jack_zones), + .buttons_zones = sec_jack_buttons_zones, + .num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones), + .det_gpio = GPIO_DET_35, + .send_end_gpio = GPIO_EAR_SEND_END, +}; + +static struct platform_device sec_device_jack = { + .name = "sec_jack", + .id = 1, /* will be used also for gpio_event id */ + .dev.platform_data = &sec_jack_pdata, +}; + + +#define S3C_GPIO_SETPIN_ZERO 0 +#define S3C_GPIO_SETPIN_ONE 1 +#define S3C_GPIO_SETPIN_NONE 2 + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +static struct gpio_init_data herring_init_gpios[] = { + { + .num = S5PV210_GPB(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + + }, { + .num = S5PV210_GPB(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPC0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPC1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPD0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPD1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPE0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + + { + .num = S5PV210_GPE1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPF3(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPF3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG0(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG1(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG3(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_DET_35 - 3.5" ear jack */ + .num = S5PV210_GPH0(6), + .cfg = S3C_GPIO_SFN(GPIO_DET_35_AF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(7), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_IRQ */ + .num = S5PV210_GPH1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_EN */ + .num = S5PV210_GPH1(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_FIRM */ + .num = S5PV210_GPH1(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(7), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(5), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(6), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH3(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_UP, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(1), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(2), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_EAR_SEND_END */ + .num = S5PV210_GPH3(6), + .cfg = S3C_GPIO_SFN(GPIO_EAR_SEND_END_AF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPI(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(5), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ1(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ3(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* GPIO_EAR_ADC_SEL */ + .num = S5PV210_GPJ3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ4(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(1), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP01(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP02(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP03(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP04(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_SCL_18V - has external pull up resistor */ + .num = S5PV210_MP04(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { /* NFC_SDA_18V - has external pull up resistor */ + .num = S5PV210_MP04(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP05(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +}; + +void s3c_config_gpio_table(void) +{ + u32 i, gpio; + + for (i = 0; i < ARRAY_SIZE(herring_init_gpios); i++) { + gpio = herring_init_gpios[i].num; + if (system_rev <= 0x07 && gpio == S5PV210_GPJ3(3)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ONE); + } else if (gpio <= S5PV210_MP05(7)) { + s3c_gpio_cfgpin(gpio, herring_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, herring_init_gpios[i].pud); + + if (herring_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, herring_init_gpios[i].val); + + s3c_gpio_set_drvstrength(gpio, + herring_init_gpios[i].drv); + } + } + + if (herring_is_cdma_wimax_dev()) { + /* WiMAX_I2C_CON */ + gpio = S5PV210_GPC1(1); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_GPC1(3); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_GPC1(4); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_GPG2(0); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(1); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(3); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(4); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(5); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio = S5PV210_GPG2(6); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + /* WIMAX_EN */ + gpio = S5PV210_GPH1(0); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ZERO); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_1X); + + /* GPIO_CP_RST, CDMA modem specific setting */ + gpio = S5PV210_GPH3(7); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN); + gpio_set_value(gpio, S3C_GPIO_SETPIN_ZERO); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_MP05(2); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + + gpio = S5PV210_MP05(3); + s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + gpio_set_value(gpio, S3C_GPIO_SETPIN_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_4X); + } +} + +#define S5PV210_PS_HOLD_CONTROL_REG (S3C_VA_SYS+0xE81C) +static void herring_power_off(void) +{ + int phone_wait_cnt = 0; + + if (herring_is_cdma_wimax_dev()) { + /* confirm phone is powered-off */ + while (1) { + if (gpio_get_value(GPIO_PHONE_ACTIVE)) { + pr_info("%s: Try to Turn Phone Off by CP_RST\n", + __func__); + gpio_set_value(GPIO_CP_RST, 0); + if (phone_wait_cnt > 1) { + pr_info("%s: PHONE OFF Fail\n", + __func__); + break; + } + phone_wait_cnt++; + mdelay(100); + } else { + pr_info("%s: PHONE OFF Success\n", __func__); + break; + } + } + } + + while (1) { + /* Check reboot charging */ + if (set_cable_status) { + /* watchdog reset */ + pr_info("%s: charger connected, rebooting\n", __func__); + writel(3, S5P_INFORM6); + arch_reset('r', NULL); + pr_crit("%s: waiting for reset!\n", __func__); + while (1); + } + + /* wait for power button release */ + if (gpio_get_value(GPIO_nPOWER)) { + pr_info("%s: set PS_HOLD low\n", __func__); + + /* PS_HOLD high PS_HOLD_CONTROL, R/W, 0xE010_E81C */ + writel(readl(S5PV210_PS_HOLD_CONTROL_REG) & 0xFFFFFEFF, + S5PV210_PS_HOLD_CONTROL_REG); + + pr_crit("%s: should not reach here!\n", __func__); + } + + /* if power button is not released, wait and check TA again */ + pr_info("%s: PowerButton is not released.\n", __func__); + mdelay(1000); + } +} + +/* this table only for B4 board */ +static unsigned int herring_sleep_gpio_table[][3] = { + { S5PV210_GPA0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPG1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPG2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + /* Alive part ending and off part start*/ + { S5PV210_GPI(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /* memory part */ + { S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP04(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /* Memory part ending and off part ending */ +}; + +static unsigned int herring_cdma_wimax_sleep_gpio_table[][3] = { + { S5PV210_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX PMIC SDA*/ + { S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*Wimax eeprom switch*/ + { S5PV210_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /*WIMAX PMIC SCL*/ + { S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX EEPROM I2C LINES*/ + { S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX DBGEN*/ + { S5PV210_GPD0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX RESET_N*/ + { S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + + { S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + + { S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + + { S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + + { S5PV210_GPG0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*wimax SDIO pins*/ + { S5PV210_GPG2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPG3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_GPH1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPH1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPH2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPH3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + { S5PV210_GPH3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /* Alive part ending and off part start*/ + { S5PV210_GPI(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /* memory part */ + { S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX*/ + { S5PV210_MP04(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /*WIMAX*/ + { S5PV210_MP04(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP05(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + /*WIMAX*/ + { S5PV210_MP05(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /* Memory part ending and off part ending */ +}; + +void s3c_config_sleep_gpio_table(int array_size, unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +void s3c_config_cdma_wimax_sleep_gpio(void) +{ + s3c_gpio_cfgpin(S5PV210_GPH0(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(0), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH0(1), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(1), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH0(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(2), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH0(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(4), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(4), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(4), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(5), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(0), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(1), S3C_GPIO_PULL_DOWN); + gpio_set_value(S5PV210_GPH1(1), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(2), S3C_GPIO_PULL_UP); + gpio_set_value(S5PV210_GPH1(2), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(4), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(5), S3C_GPIO_PULL_DOWN); + gpio_set_value(S5PV210_GPH1(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(6), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(6), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(7), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(7), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH2(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(0), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH2(2), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(2), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(2), 0); + + s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH2(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH3(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(0), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH3(3), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(3), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH3(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH3(5), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(5), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH3(7), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH3(7), S3C_GPIO_PULL_UP); + gpio_set_value(S5PV210_GPH3(7), 1); + +} + +void s3c_config_gsm_sleep_gpio(void) +{ + /* setting the alive mode registers */ + s3c_gpio_cfgpin(S5PV210_GPH0(1), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH0(1), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH0(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(4), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(4), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(4), 0); + + s3c_gpio_cfgpin(S5PV210_GPH0(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH0(5), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH0(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(1), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(1), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(2), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(2), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(4), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH1(5), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH1(5), 0); + + s3c_gpio_cfgpin(S5PV210_GPH1(6), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(6), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH1(7), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH1(7), S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(S5PV210_GPH2(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH2(0), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH2(2), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(2), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(2), 0); + + s3c_gpio_cfgpin(S5PV210_GPH2(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPH2(3), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPH2(3), 0); + + s3c_gpio_cfgpin(S5PV210_GPH3(0), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(0), S3C_GPIO_PULL_UP); + + s3c_gpio_cfgpin(S5PV210_GPH3(3), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(3), S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(S5PV210_GPH3(4), S3C_GPIO_INPUT); + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_DOWN); +} + +void s3c_config_sleep_gpio(void) +{ + if (herring_is_cdma_wimax_dev()) + s3c_config_cdma_wimax_sleep_gpio(); + else + s3c_config_gsm_sleep_gpio(); +} +EXPORT_SYMBOL(s3c_config_sleep_gpio); + +static unsigned int wlan_sdio_on_table[][4] = { + {GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF, GPIO_LEVEL_NONE, + S3C_GPIO_PULL_NONE}, +}; + +static unsigned int wlan_sdio_off_table[][4] = { + {GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, +}; + +static int wlan_power_en(int onoff) +{ + if (onoff) { + s3c_gpio_cfgpin(GPIO_WLAN_HOST_WAKE, + S3C_GPIO_SFN(GPIO_WLAN_HOST_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_HOST_WAKE, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_WLAN_WAKE, + S3C_GPIO_SFN(GPIO_WLAN_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_WAKE, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_WAKE, GPIO_LEVEL_LOW); + + s3c_gpio_cfgpin(GPIO_WLAN_nRST, + S3C_GPIO_SFN(GPIO_WLAN_nRST_AF)); + s3c_gpio_setpull(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + msleep(200); + } else { + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + if (gpio_get_value(GPIO_BT_nRST) == 0) { + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + } + } + return 0; +} + +static int wlan_reset_en(int onoff) +{ + gpio_set_value(GPIO_WLAN_nRST, + onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); + return 0; +} + +static int wlan_carddetect_en(int onoff) +{ + u32 i; + u32 sdio; + + if (onoff) { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_on_table); i++) { + sdio = wlan_sdio_on_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wlan_sdio_on_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_on_table[i][3]); + if (wlan_sdio_on_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_on_table[i][2]); + } + } else { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_off_table); i++) { + sdio = wlan_sdio_off_table[i][0]; + s3c_gpio_cfgpin(sdio, + S3C_GPIO_SFN(wlan_sdio_off_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_off_table[i][3]); + if (wlan_sdio_off_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_off_table[i][2]); + } + } + udelay(5); + + sdhci_s3c_force_presence_change(&s3c_device_hsmmc3); + msleep(500); /* wait for carddetect */ + return 0; +} + +static struct resource wifi_resources[] = { + [0] = { + .name = "bcm4329_wlan_irq", + .start = IRQ_EINT(20), + .end = IRQ_EINT(20), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = { + {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)} +}; + +static void *herring_mem_prealloc(int section, unsigned long size) +{ + if (section == PREALLOC_WLAN_SEC_NUM) + return wlan_static_skb; + + if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM)) + return NULL; + + if (wifi_mem_array[section].size < size) + return NULL; + + return wifi_mem_array[section].mem_ptr; +} + +int __init herring_init_wifi_mem(void) +{ + int i; + int j; + + for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) { + wlan_static_skb[i] = dev_alloc_skb( + ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192)); + + if (!wlan_static_skb[i]) + goto err_skb_alloc; + } + + for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) { + wifi_mem_array[i].mem_ptr = + kmalloc(wifi_mem_array[i].size, GFP_KERNEL); + + if (!wifi_mem_array[i].mem_ptr) + goto err_mem_alloc; + } + return 0; + + err_mem_alloc: + pr_err("Failed to mem_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + kfree(wifi_mem_array[j].mem_ptr); + + i = WLAN_SKB_BUF_NUM; + + err_skb_alloc: + pr_err("Failed to skb_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + dev_kfree_skb(wlan_static_skb[j]); + + return -ENOMEM; +} + +/* Customized Locale table : OPTIONAL feature */ +#define WLC_CNTRY_BUF_SZ 4 +typedef struct cntry_locales_custom { + char iso_abbrev[WLC_CNTRY_BUF_SZ]; + char custom_locale[WLC_CNTRY_BUF_SZ]; + int custom_locale_rev; +} cntry_locales_custom_t; + +static cntry_locales_custom_t herring_wlan_translate_custom_table[] = { +/* Table should be filled out based on custom platform regulatory requirement */ + {"", "XY", 4}, /* universal */ + {"US", "US", 69}, /* input ISO "US" to : US regrev 69 */ + {"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */ + {"EU", "EU", 5}, /* European union countries */ + {"AT", "EU", 5}, + {"BE", "EU", 5}, + {"BG", "EU", 5}, + {"CY", "EU", 5}, + {"CZ", "EU", 5}, + {"DK", "EU", 5}, + {"EE", "EU", 5}, + {"FI", "EU", 5}, + {"FR", "EU", 5}, + {"DE", "EU", 5}, + {"GR", "EU", 5}, + {"HU", "EU", 5}, + {"IE", "EU", 5}, + {"IT", "EU", 5}, + {"LV", "EU", 5}, + {"LI", "EU", 5}, + {"LT", "EU", 5}, + {"LU", "EU", 5}, + {"MT", "EU", 5}, + {"NL", "EU", 5}, + {"PL", "EU", 5}, + {"PT", "EU", 5}, + {"RO", "EU", 5}, + {"SK", "EU", 5}, + {"SI", "EU", 5}, + {"ES", "EU", 5}, + {"SE", "EU", 5}, + {"GB", "EU", 5}, /* input ISO "GB" to : EU regrev 05 */ + {"IL", "IL", 0}, + {"CH", "CH", 0}, + {"TR", "TR", 0}, + {"NO", "NO", 0}, + {"KR", "XY", 3}, + {"AU", "XY", 3}, + {"CN", "XY", 3}, /* input ISO "CN" to : XY regrev 03 */ + {"TW", "XY", 3}, + {"AR", "XY", 3}, + {"MX", "XY", 3} +}; + +static void *herring_wlan_get_country_code(char *ccode) +{ + int size = ARRAY_SIZE(herring_wlan_translate_custom_table); + int i; + + if (!ccode) + return NULL; + + for (i = 0; i < size; i++) + if (strcmp(ccode, herring_wlan_translate_custom_table[i].iso_abbrev) == 0) + return &herring_wlan_translate_custom_table[i]; + return &herring_wlan_translate_custom_table[0]; +} + + +static struct wifi_platform_data wifi_pdata = { + .set_power = wlan_power_en, + .set_reset = wlan_reset_en, + .set_carddetect = wlan_carddetect_en, + .mem_prealloc = herring_mem_prealloc, + .get_country_code = herring_wlan_get_country_code, +}; + +static struct platform_device sec_device_wifi = { + .name = "bcm4329_wlan", + .id = 1, + .num_resources = ARRAY_SIZE(wifi_resources), + .resource = wifi_resources, + .dev = { + .platform_data = &wifi_pdata, + }, +}; + +static struct platform_device watchdog_device = { + .name = "watchdog", + .id = -1, +}; + +static struct platform_device *herring_devices[] __initdata = { + &watchdog_device, +#ifdef CONFIG_FIQ_DEBUGGER + &s5pv210_device_fiqdbg_uart2, +#endif + &s5p_device_onenand, +#ifdef CONFIG_RTC_DRV_S3C + &s5p_device_rtc, +#endif + &herring_input_device, + + &s5pv210_device_iis0, + &s3c_device_wdt, + +#ifdef CONFIG_FB_S3C + &s3c_device_fb, +#endif + +#ifdef CONFIG_VIDEO_MFC50 + &s3c_device_mfc, +#endif +#ifdef CONFIG_S5P_ADC + &s3c_device_adc, +#endif +#ifdef CONFIG_VIDEO_FIMC + &s3c_device_fimc0, + &s3c_device_fimc1, + &s3c_device_fimc2, +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + &s3c_device_jpeg, +#endif + + &s3c_device_g3d, + &s3c_device_lcd, + +#ifdef CONFIG_FB_S3C_TL2796 + &s3c_device_spi_gpio, +#endif + &sec_device_jack, + + &s3c_device_i2c0, +#if defined(CONFIG_S3C_DEV_I2C1) + &s3c_device_i2c1, +#endif + +#if defined(CONFIG_S3C_DEV_I2C2) + &s3c_device_i2c2, +#endif + &herring_i2c4_device, + &herring_i2c6_device, + &herring_i2c7_device, + &herring_i2c8_device, /* gyro sensor */ + &herring_i2c9_device, /* max1704x:fuel_guage */ + &herring_i2c11_device, /* optical sensor */ + &herring_i2c12_device, /* magnetic sensor */ + &herring_i2c14_device, /* nfc sensor */ +#if defined CONFIG_USB_S3C_OTG_HOST + &s3c_device_usb_otghcd, +#endif +#if defined CONFIG_USB_DWC_OTG + &s3c_device_usb_dwcotg, +#endif +#ifdef CONFIG_USB_GADGET + &s3c_device_usbgadget, +#endif +#ifdef CONFIG_USB_ANDROID + &s3c_device_android_usb, +#ifdef CONFIG_USB_ANDROID_MASS_STORAGE + &s3c_device_usb_mass_storage, +#endif +#ifdef CONFIG_USB_ANDROID_RNDIS + &s3c_device_rndis, +#endif +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + &s3c_device_hsmmc0, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + &s3c_device_hsmmc1, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + &s3c_device_hsmmc2, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + &s3c_device_hsmmc3, +#endif + + &sec_device_battery, + &herring_i2c10_device, + +#ifdef CONFIG_S5PV210_POWER_DOMAIN + &s5pv210_pd_audio, + &s5pv210_pd_cam, + &s5pv210_pd_tv, + &s5pv210_pd_lcd, + &s5pv210_pd_g3d, + &s5pv210_pd_mfc, +#endif + +#ifdef CONFIG_ANDROID_PMEM + &pmem_device, + &pmem_gpu1_device, + &pmem_adsp_device, +#endif + +#ifdef CONFIG_HAVE_PWM + &s3c_device_timer[0], + &s3c_device_timer[1], + &s3c_device_timer[2], + &s3c_device_timer[3], +#endif + +#ifdef CONFIG_CPU_FREQ + &s5pv210_device_cpufreq, +#endif + + &sec_device_rfkill, + &sec_device_btsleep, + &ram_console_device, + &sec_device_wifi, + &samsung_asoc_dma, +}; + +unsigned int HWREV; +EXPORT_SYMBOL(HWREV); + +static void __init herring_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s5pv210_gpiolib_init(); + s3c24xx_init_uarts(herring_uartcfgs, ARRAY_SIZE(herring_uartcfgs)); +#ifndef CONFIG_S5P_HIGH_RES_TIMERS + s5p_set_timer_source(S5P_PWM3, S5P_PWM4); +#endif + s5p_reserve_bootmem(herring_media_devs, + ARRAY_SIZE(herring_media_devs), S5P_RANGE_MFC); +#ifdef CONFIG_MTD_ONENAND + s5p_device_onenand.name = "s5pc110-onenand"; +#endif +} + +unsigned int pm_debug_scratchpad; + +static unsigned int ram_console_start; +static unsigned int ram_console_size; + +static void __init herring_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, + struct meminfo *mi) +{ + mi->bank[0].start = 0x30000000; + mi->bank[0].size = 80 * SZ_1M; + + mi->bank[1].start = 0x40000000; + mi->bank[1].size = 256 * SZ_1M; + + mi->bank[2].start = 0x50000000; + /* 1M for ram_console buffer */ + mi->bank[2].size = 127 * SZ_1M; + mi->nr_banks = 3; + + ram_console_start = mi->bank[2].start + mi->bank[2].size; + ram_console_size = SZ_1M - SZ_4K; + + pm_debug_scratchpad = ram_console_start + ram_console_size; +} + +/* this function are used to detect s5pc110 chip version temporally */ +int s5pc110_version ; + +void _hw_version_check(void) +{ + void __iomem *phy_address ; + int temp; + + phy_address = ioremap(0x40, 1); + + temp = __raw_readl(phy_address); + + if (temp == 0xE59F010C) + s5pc110_version = 0; + else + s5pc110_version = 1; + + printk(KERN_INFO "S5PC110 Hardware version : EVT%d\n", + s5pc110_version); + + iounmap(phy_address); +} + +/* + * Temporally used + * return value 0 -> EVT 0 + * value 1 -> evt 1 + */ + +int hw_version_check(void) +{ + return s5pc110_version ; +} +EXPORT_SYMBOL(hw_version_check); + +static void herring_init_gpio(void) +{ + s3c_config_gpio_table(); + s3c_config_sleep_gpio_table(ARRAY_SIZE(herring_sleep_gpio_table), + herring_sleep_gpio_table); + if (herring_is_cdma_wimax_dev()) + s3c_config_sleep_gpio_table( + ARRAY_SIZE(herring_cdma_wimax_sleep_gpio_table), + herring_cdma_wimax_sleep_gpio_table); + +} + +static void __init fsa9480_gpio_init(void) +{ + if (herring_is_cdma_wimax_dev()) { + s3c_gpio_cfgpin(GPIO_USB_HS_SEL, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_USB_HS_SEL, 1); + } else { + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_JACK_nINT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_JACK_nINT, S3C_GPIO_PULL_NONE); +} + +static void __init setup_ram_console_mem(void) +{ + ram_console_resource[0].start = ram_console_start; + ram_console_resource[0].end = ram_console_start + ram_console_size - 1; +} + +static void __init sound_init(void) +{ + u32 reg; + + reg = __raw_readl(S5P_OTHERS); + reg &= ~(0x3 << 8); + reg |= 3 << 8; + __raw_writel(reg, S5P_OTHERS); + + reg = __raw_readl(S5P_CLK_OUT); + reg &= ~(0x1f << 12); + reg |= 19 << 12; + __raw_writel(reg, S5P_CLK_OUT); + + reg = __raw_readl(S5P_CLK_OUT); + reg &= ~0x1; + reg |= 0x1; + __raw_writel(reg, S5P_CLK_OUT); + + gpio_request(GPIO_MICBIAS_EN, "micbias_enable"); +} + +static s8 accel_rotation_wimax_rev0[9] = { + 0, -1, 0, + -1, 0, 0, + 0, 0, -1, +}; + +static void __init accel_init(void) +{ + if (herring_is_cdma_wimax_rev0()) + kr3dm_data.rotation = accel_rotation_wimax_rev0; +} + +static bool console_flushed; + +static void flush_console(void) +{ + if (console_flushed) + return; + + console_flushed = true; + + printk("\n"); + pr_emerg("Restarting %s\n", linux_banner); + if (!is_console_locked()) + return; + + mdelay(50); + + local_irq_disable(); + if (!console_trylock()) + pr_emerg("flush_console: console was locked! busting!\n"); + else + pr_emerg("flush_console: console was locked!\n"); + console_unlock(); +} + +static void herring_pm_restart(char mode, const char *cmd) +{ + flush_console(); + + /* On a normal reboot, INFORM6 will contain a small integer + * reason code from the notifier hook. On a panic, it will + * contain the 0xee we set at boot. Write 0xbb to differentiate + * a watchdog-timeout-and-reboot (0xee) from a controlled reboot + * (0xbb) + */ + if (__raw_readl(S5P_INFORM6) == 0xee) + __raw_writel(0xbb, S5P_INFORM6); + + arm_machine_restart(mode, cmd); +} + +static void __init herring_machine_init(void) +{ + arm_pm_restart = herring_pm_restart; + + setup_ram_console_mem(); + platform_add_devices(herring_devices, ARRAY_SIZE(herring_devices)); + if (!herring_is_tft_dev()) + platform_device_register(&herring_i2c5_device); + + /* Find out S5PC110 chip version */ + _hw_version_check(); + + pm_power_off = herring_power_off ; + + s3c_gpio_cfgpin(GPIO_HWREV_MODE0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE0, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE1, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE1, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE2, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE2, S3C_GPIO_PULL_NONE); + HWREV = gpio_get_value(GPIO_HWREV_MODE0); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE1) << 1); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE2) << 2); + s3c_gpio_cfgpin(GPIO_HWREV_MODE3, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HWREV_MODE3, S3C_GPIO_PULL_NONE); + HWREV = HWREV | (gpio_get_value(GPIO_HWREV_MODE3) << 3); + printk(KERN_INFO "HWREV is 0x%x\n", HWREV); + + /*initialise the gpio's*/ + herring_init_gpio(); + +#ifdef CONFIG_ANDROID_PMEM + android_pmem_set_platdata(); +#endif + + /* headset/earjack detection */ + if (system_rev >= 0x09) + gpio_request(GPIO_EAR_MICBIAS_EN, "ear_micbias_enable"); + + gpio_request(GPIO_TOUCH_EN, "touch en"); + + /* i2c */ + s3c_i2c0_set_platdata(NULL); +#ifdef CONFIG_S3C_DEV_I2C1 + s3c_i2c1_set_platdata(NULL); +#endif + +#ifdef CONFIG_S3C_DEV_I2C2 + s3c_i2c2_set_platdata(NULL); +#endif + k3g_irq_init(); + set_adc_table(); + accel_init(); + /* H/W I2C lines */ + if (system_rev >= 0x05) { + /* gyro sensor */ + if (herring_is_cdma_wimax_dev() && herring_is_cdma_wimax_rev0()) + i2c_register_board_info(5, i2c_devs0, + ARRAY_SIZE(i2c_devs0)); + else + i2c_register_board_info(0, i2c_devs0, + ARRAY_SIZE(i2c_devs0)); + /* magnetic and accel sensor */ + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + } + mxt224_init(); + i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2)); + + /* wm8994 codec */ + sound_init(); + i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4)); + /* accel sensor for rev04 */ + if (system_rev == 0x04) + i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5)); + + if (herring_is_cdma_wimax_dev()) { + struct max8998_platform_data *pdata = + (struct max8998_platform_data *)&max8998_pdata; + pdata->num_regulators = + ARRAY_SIZE(herring_cdma_wimax_regulators); + pdata->regulators = herring_cdma_wimax_regulators; + } + + i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6)); + if (!herring_is_tft_dev()) { + /* Touch Key */ + touch_keypad_gpio_init(); + i2c_register_board_info(10, i2c_devs10, ARRAY_SIZE(i2c_devs10)); + } else { + herring_virtual_keys_init(); + } + /* FSA9480 */ + fsa9480_gpio_init(); + i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7)); + + /* gyro sensor for rev04 */ + if (system_rev == 0x04) + i2c_register_board_info(8, i2c_devs8, ARRAY_SIZE(i2c_devs8)); + + i2c_register_board_info(9, i2c_devs9, ARRAY_SIZE(i2c_devs9)); + /* optical sensor */ + gp2a_gpio_init(); + i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11)); + /* magnetic sensor for rev04 */ + if (system_rev == 0x04) + i2c_register_board_info(12, i2c_devs12, ARRAY_SIZE(i2c_devs12)); + + /* nfc sensor */ + i2c_register_board_info(14, i2c_devs14, ARRAY_SIZE(i2c_devs14)); + + /* max8893 wimax PMIC */ + if (herring_is_cdma_wimax_dev()) { + platform_device_register(&herring_i2c15_device); + i2c_register_board_info(15, i2c_devs15, ARRAY_SIZE(i2c_devs15)); + } + + if (!herring_is_tft_dev()) { + is_device_lcd = false; + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + s3cfb_set_platdata(&tl2796_data); + } else { + is_device_lcd = true; + switch (lcd_type) { + case 1: + spi_register_board_info(spi_board_info_hydis, + ARRAY_SIZE(spi_board_info_hydis)); + s3cfb_set_platdata(&nt35580_data); + break; + case 2: + spi_register_board_info(spi_board_info_hitachi, + ARRAY_SIZE(spi_board_info_hitachi)); + s3cfb_set_platdata(&r61408_data); + break; + default: + spi_register_board_info(spi_board_info_sony, + ARRAY_SIZE(spi_board_info_sony)); + s3cfb_set_platdata(&nt35580_data); + break; + } + } + +#if defined(CONFIG_S5P_ADC) + s3c_adc_set_platdata(&s3c_adc_platform); +#endif + +#if defined(CONFIG_PM) + s3c_pm_init(); +#endif + + s5ka3dfx_request_gpio(); + + s5k4ecgx_init(); + +#ifdef CONFIG_VIDEO_FIMC + /* fimc */ + s3c_fimc0_set_platdata(&fimc_plat_lsi); + s3c_fimc1_set_platdata(&fimc_plat_lsi); + s3c_fimc2_set_platdata(&fimc_plat_lsi); +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + s3c_jpeg_set_platdata(&jpeg_plat); +#endif + +#ifdef CONFIG_VIDEO_MFC50 + /* mfc */ + s3c_mfc_set_platdata(NULL); +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + s5pv210_default_sdhci0(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + s5pv210_default_sdhci1(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + s5pv210_default_sdhci2(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + s5pv210_default_sdhci3(); +#endif +#ifdef CONFIG_S5PV210_SETUP_SDHCI + s3c_sdhci_set_platdata(); +#endif + +#ifdef CONFIG_CPU_FREQ + s5pv210_cpufreq_set_platdata(&smdkc110_cpufreq_plat); +#endif + + regulator_has_full_constraints(); + + register_reboot_notifier(&herring_reboot_notifier); + + herring_switch_init(); + + gps_gpio_init(); + + uart_switch_init(); + + herring_init_wifi_mem(); + + if (herring_is_cdma_wimax_dev()) + platform_device_register(&s3c_device_cmc732); + + /* write something into the INFORM6 register that we can use to + * differentiate an unclear reboot from a clean reboot (which + * writes a small integer code to INFORM6). + */ + __raw_writel(0xee, S5P_INFORM6); +} + +#ifdef CONFIG_USB_SUPPORT +/* Initializes OTG Phy. */ +void otg_phy_init(void) +{ + /* USB PHY0 Enable */ + writel(readl(S5P_USB_PHY_CONTROL) | (0x1<<0), + S5P_USB_PHY_CONTROL); + writel((readl(S3C_USBOTG_PHYPWR) & ~(0x3<<3) & ~(0x1<<0)) | (0x1<<5), + S3C_USBOTG_PHYPWR); + writel((readl(S3C_USBOTG_PHYCLK) & ~(0x5<<2)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + writel((readl(S3C_USBOTG_RSTCON) & ~(0x3<<1)) | (0x1<<0), + S3C_USBOTG_RSTCON); + mdelay(1); + writel(readl(S3C_USBOTG_RSTCON) & ~(0x7<<0), + S3C_USBOTG_RSTCON); + mdelay(1); + + /* rising/falling time */ + writel(readl(S3C_USBOTG_PHYTUNE) | (0x1<<20), + S3C_USBOTG_PHYTUNE); + + /* set DC level as 0xf (24%) */ + writel(readl(S3C_USBOTG_PHYTUNE) | 0xf, S3C_USBOTG_PHYTUNE); +} +EXPORT_SYMBOL(otg_phy_init); + +/* USB Control request data struct must be located here for DMA transfer */ +struct usb_ctrlrequest usb_ctrl __attribute__((aligned(64))); + +/* OTG PHY Power Off */ +void otg_phy_off(void) +{ + writel(readl(S3C_USBOTG_PHYPWR) | (0x3<<3), + S3C_USBOTG_PHYPWR); + writel(readl(S5P_USB_PHY_CONTROL) & ~(1<<0), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(otg_phy_off); + +void usb_host_phy_init(void) +{ + struct clk *otg_clk; + + otg_clk = clk_get(NULL, "otg"); + clk_enable(otg_clk); + + if (readl(S5P_USB_PHY_CONTROL) & (0x1<<1)) + return; + + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) | (0x1<<1), + S5P_USB_PHY_CONTROL); + __raw_writel((__raw_readl(S3C_USBOTG_PHYPWR) + & ~(0x1<<7) & ~(0x1<<6)) | (0x1<<8) | (0x1<<5), + S3C_USBOTG_PHYPWR); + __raw_writel((__raw_readl(S3C_USBOTG_PHYCLK) & ~(0x1<<7)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + __raw_writel((__raw_readl(S3C_USBOTG_RSTCON)) | (0x1<<4) | (0x1<<3), + S3C_USBOTG_RSTCON); + __raw_writel(__raw_readl(S3C_USBOTG_RSTCON) & ~(0x1<<4) & ~(0x1<<3), + S3C_USBOTG_RSTCON); +} +EXPORT_SYMBOL(usb_host_phy_init); + +void usb_host_phy_off(void) +{ + __raw_writel(__raw_readl(S3C_USBOTG_PHYPWR) | (0x1<<7)|(0x1<<6), + S3C_USBOTG_PHYPWR); + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) & ~(1<<1), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(usb_host_phy_off); +#endif + +#if defined CONFIG_USB_S3C_OTG_HOST || defined CONFIG_USB_DWC_OTG + +/* Initializes OTG Phy */ +void otg_host_phy_init(void) +{ + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) + |(0x1<<0), S5P_USB_PHY_CONTROL); /*USB PHY0 Enable */ +// from galaxy tab otg host: + __raw_writel((__raw_readl(S3C_USBOTG_PHYPWR) + &~(0x3<<3)&~(0x1<<0))|(0x1<<5), S3C_USBOTG_PHYPWR); +// from galaxy s2 otg host: +// __raw_writel((__raw_readl(S3C_USBOTG_PHYPWR) +// &~(0x7<<3)&~(0x1<<0)), S3C_USBOTG_PHYPWR); + __raw_writel((__raw_readl(S3C_USBOTG_PHYCLK) + &~(0x1<<4))|(0x7<<0), S3C_USBOTG_PHYCLK); + + __raw_writel((__raw_readl(S3C_USBOTG_RSTCON) + &~(0x3<<1))|(0x1<<0), S3C_USBOTG_RSTCON); + mdelay(1); + __raw_writel((__raw_readl(S3C_USBOTG_RSTCON) + &~(0x7<<0)), S3C_USBOTG_RSTCON); + mdelay(1); + + __raw_writel((__raw_readl(S3C_UDC_OTG_GUSBCFG) + |(0x3<<8)), S3C_UDC_OTG_GUSBCFG); + +// smb136_set_otg_mode(1); + + printk("otg_host_phy_int : USBPHYCTL=0x%x,PHYPWR=0x%x,PHYCLK=0x%x,USBCFG=0x%x\n", + readl(S5P_USB_PHY_CONTROL), + readl(S3C_USBOTG_PHYPWR), + readl(S3C_USBOTG_PHYCLK), + readl(S3C_UDC_OTG_GUSBCFG) + ); +} +EXPORT_SYMBOL(otg_host_phy_init); +#endif + +MACHINE_START(HERRING, "herring") + .boot_params = S5P_PA_SDRAM + 0x100, + .fixup = herring_fixup, + .init_irq = s5pv210_init_irq, + .map_io = herring_map_io, + .init_machine = herring_machine_init, +#ifdef CONFIG_S5P_HIGH_RES_TIMERS + .timer = &s5p_systimer, +#else + .timer = &s5p_timer, +#endif +MACHINE_END + +void s3c_setup_uart_cfg_gpio(unsigned char port) +{ + switch (port) { + case 0: + s3c_gpio_cfgpin(GPIO_BT_RXD, S3C_GPIO_SFN(GPIO_BT_RXD_AF)); + s3c_gpio_setpull(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_TXD, S3C_GPIO_SFN(GPIO_BT_TXD_AF)); + s3c_gpio_setpull(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_CTS, S3C_GPIO_SFN(GPIO_BT_CTS_AF)); + s3c_gpio_setpull(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_RTS, S3C_GPIO_SFN(GPIO_BT_RTS_AF)); + s3c_gpio_setpull(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_TXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_CTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + break; + case 1: + s3c_gpio_cfgpin(GPIO_GPS_RXD, S3C_GPIO_SFN(GPIO_GPS_RXD_AF)); + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_GPS_TXD, S3C_GPIO_SFN(GPIO_GPS_TXD_AF)); + s3c_gpio_setpull(GPIO_GPS_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_CTS, S3C_GPIO_SFN(GPIO_GPS_CTS_AF)); + s3c_gpio_setpull(GPIO_GPS_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_RTS, S3C_GPIO_SFN(GPIO_GPS_RTS_AF)); + s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_NONE); + break; + case 2: + s3c_gpio_cfgpin(GPIO_AP_RXD, S3C_GPIO_SFN(GPIO_AP_RXD_AF)); + s3c_gpio_setpull(GPIO_AP_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_AP_TXD, S3C_GPIO_SFN(GPIO_AP_TXD_AF)); + s3c_gpio_setpull(GPIO_AP_TXD, S3C_GPIO_PULL_NONE); + break; + case 3: + s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(GPIO_FLM_RXD_AF)); + s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(GPIO_FLM_TXD_AF)); + s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); + break; + default: + break; + } +} +EXPORT_SYMBOL(s3c_setup_uart_cfg_gpio); diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 24febae..39f3270 100644..100755 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -25,8 +25,16 @@ #include <mach/regs-irq.h> #include <mach/regs-clock.h> +#include <mach/regs-mem.h> +#include <mach/power-domain.h> + +static struct sleep_save core_save[] = { + /* PLL Control */ + SAVE_ITEM(S5P_APLL_CON), + SAVE_ITEM(S5P_MPLL_CON), + SAVE_ITEM(S5P_EPLL_CON), + SAVE_ITEM(S5P_VPLL_CON), -static struct sleep_save s5pv210_core_save[] = { /* Clock source */ SAVE_ITEM(S5P_CLK_SRC0), SAVE_ITEM(S5P_CLK_SRC1), @@ -72,7 +80,7 @@ static struct sleep_save s5pv210_core_save[] = { /* Clock Blcok and Bus gate */ SAVE_ITEM(S5P_CLKGATE_BLOCK), - SAVE_ITEM(S5P_CLKGATE_BUS0), + SAVE_ITEM(S5P_CLKGATE_IP5), /* Clock ETC */ SAVE_ITEM(S5P_CLK_OUT), @@ -115,10 +123,6 @@ static void s5pv210_pm_prepare(void) /* ensure at least INFORM0 has the resume address */ __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); - tmp = __raw_readl(S5P_SLEEP_CFG); - tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); - __raw_writel(tmp, S5P_SLEEP_CFG); - /* WFI for SLEEP mode configuration by SYSCON */ tmp = __raw_readl(S5P_PWR_CFG); tmp &= S5P_CFG_WFI_CLEAN; @@ -130,7 +134,12 @@ static void s5pv210_pm_prepare(void) tmp |= S5P_OTHER_SYSC_INTOFF; __raw_writel(tmp, S5P_OTHERS); - s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); + __raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR)); + __raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR)); + + s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); } static int s5pv210_pm_add(struct sys_device *sysdev) @@ -153,14 +162,29 @@ arch_initcall(s5pv210_pm_drvinit); static void s5pv210_pm_resume(void) { - u32 tmp; + u32 tmp, audiodomain_on; + + tmp = __raw_readl(S5P_NORMAL_CFG); + if (tmp & S5PV210_PD_AUDIO) + audiodomain_on = 0; + else { + tmp |= S5PV210_PD_AUDIO; + __raw_writel(tmp , S5P_NORMAL_CFG); + audiodomain_on = 1; + } tmp = __raw_readl(S5P_OTHERS); tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\ S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART); __raw_writel(tmp , S5P_OTHERS); - s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); + if (audiodomain_on) { + tmp = __raw_readl(S5P_NORMAL_CFG); + tmp &= ~S5PV210_PD_AUDIO; + __raw_writel(tmp , S5P_NORMAL_CFG); + } + + s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); } static struct syscore_ops s5pv210_pm_syscore_ops = { diff --git a/arch/arm/mach-s5pv210/power-domain.c b/arch/arm/mach-s5pv210/power-domain.c new file mode 100644 index 0000000..683901c --- /dev/null +++ b/arch/arm/mach-s5pv210/power-domain.c @@ -0,0 +1,566 @@ +/* linux/arch/arm/mach-s5pv210/power-domain.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Power domain support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/mutex.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <mach/power-domain.h> + +#include <mach/regs-clock.h> +#include <plat/devs.h> + +struct s5pv210_pd_data { + struct regulator_desc desc; + struct regulator_dev *dev; + int microvolts; + unsigned startup_delay; + struct clk_should_be_running *clk_run; + int ctrlbit; +}; + +struct clk_should_be_running { + const char *clk_name; + struct device *dev; +}; +static spinlock_t pd_lock; + +static struct regulator_consumer_supply s5pv210_pd_audio_supply[] = { + REGULATOR_SUPPLY("pd", "samsung-i2s.0"), +}; + +static struct regulator_consumer_supply s5pv210_pd_cam_supply[] = { + REGULATOR_SUPPLY("pd", "s3c-fimc.0"), + REGULATOR_SUPPLY("pd", "s3c-fimc.1"), + REGULATOR_SUPPLY("pd", "s3c-fimc.2"), + REGULATOR_SUPPLY("pd", "s3c-jpg"), + REGULATOR_SUPPLY("pd", "s3c-csis"), + REGULATOR_SUPPLY("pd", "s5p-rotator"), +}; + +static struct regulator_consumer_supply s5pv210_pd_tv_supply[] = { + REGULATOR_SUPPLY("pd", "s5p-tvout"), +}; + +static struct regulator_consumer_supply s5pv210_pd_lcd_supply[] = { + REGULATOR_SUPPLY("pd", "s3cfb"), +}; + +static struct regulator_consumer_supply s5pv210_pd_g3d_supply[] = { + REGULATOR_SUPPLY("pd", "pvrsrvkm"), +}; + +static struct regulator_consumer_supply s5pv210_pd_mfc_supply[] = { + REGULATOR_SUPPLY("pd", "s3c-mfc"), +}; + +static struct regulator_init_data s5pv210_pd_audio_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_audio_supply), + .consumer_supplies = s5pv210_pd_audio_supply, +}; + +static struct regulator_init_data s5pv210_pd_cam_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_cam_supply), + .consumer_supplies = s5pv210_pd_cam_supply, +}; + +static struct regulator_init_data s5pv210_pd_tv_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_tv_supply), + .consumer_supplies = s5pv210_pd_tv_supply, +}; + +static struct regulator_init_data s5pv210_pd_lcd_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_lcd_supply), + .consumer_supplies = s5pv210_pd_lcd_supply, +}; + +static struct regulator_init_data s5pv210_pd_g3d_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_g3d_supply), + .consumer_supplies = s5pv210_pd_g3d_supply, +}; + +static struct regulator_init_data s5pv210_pd_mfc_data = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5pv210_pd_mfc_supply), + .consumer_supplies = s5pv210_pd_mfc_supply, +}; + +struct clk_should_be_running s5pv210_pd_audio_clk[] = { + { + .clk_name = "i2scdclk", + .dev = &s5pv210_device_iis0.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_cam_clk[] = { + { + .clk_name = "fimc", + .dev = &s3c_device_fimc0.dev, + }, { + .clk_name = "fimc", + .dev = &s3c_device_fimc1.dev, + }, { + .clk_name = "fimc", + .dev = &s3c_device_fimc2.dev, + }, { + .clk_name = "sclk_csis", + .dev = &s5p_device_mipi_csis0.dev, + }, { + .clk_name = "jpeg", + .dev = &s3c_device_jpeg.dev, + }, { + .clk_name = "rot", + .dev = &s5p_device_rotator.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_tv_clk[] = { + { + .clk_name = "vp", + .dev = &s5p_device_tvout.dev, + }, { + .clk_name = "mixer", + .dev = &s5p_device_tvout.dev, + }, { + .clk_name = "tvenc", + .dev = &s5p_device_tvout.dev, + }, { + .clk_name = "hdmi", + .dev = &s5p_device_tvout.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_lcd_clk[] = { + { + .clk_name = "lcd", + .dev = &s3c_device_fb.dev, + }, { + .clk_name = "dsim", + .dev = &s3c_device_fb.dev, + }, { + .clk_name = "sclk_fimg2d", + .dev = &s3c_device_fb.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_g3d_clk[] = { + { + .clk_name = "sclk", + .dev = &s3c_device_g3d.dev, + }, { + /* end of the clock array */ + }, +}; + +struct clk_should_be_running s5pv210_pd_mfc_clk[] = { + { + .clk_name = "mfc", + .dev = &s3c_device_mfc.dev, + }, { + /* end of the clock array */ + }, +}; + +static struct s5pv210_pd_config s5pv210_pd_audio_pdata = { + .supply_name = "pd_audio_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_audio_data, + .clk_run = s5pv210_pd_audio_clk, + .ctrlbit = S5PV210_PD_AUDIO, +}; + +static struct s5pv210_pd_config s5pv210_pd_cam_pdata = { + .supply_name = "pd_cam_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_cam_data, + .clk_run = s5pv210_pd_cam_clk, + .ctrlbit = S5PV210_PD_CAM, +}; + +static struct s5pv210_pd_config s5pv210_pd_tv_pdata = { + .supply_name = "pd_tv_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_tv_data, + .clk_run = s5pv210_pd_tv_clk, + .ctrlbit = S5PV210_PD_TV, +}; + +static struct s5pv210_pd_config s5pv210_pd_lcd_pdata = { + .supply_name = "pd_lcd_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_lcd_data, + .clk_run = s5pv210_pd_lcd_clk, + .ctrlbit = S5PV210_PD_LCD, +}; + +static struct s5pv210_pd_config s5pv210_pd_g3d_pdata = { + .supply_name = "pd_g3d_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_g3d_data, + .clk_run = s5pv210_pd_g3d_clk, + .ctrlbit = S5PV210_PD_G3D, +}; + +static struct s5pv210_pd_config s5pv210_pd_mfc_pdata = { + .supply_name = "pd_mfc_supply", + .microvolts = 5000000, + .init_data = &s5pv210_pd_mfc_data, + .clk_run = s5pv210_pd_mfc_clk, + .ctrlbit = S5PV210_PD_MFC, +}; + +struct platform_device s5pv210_pd_audio = { + .name = "reg-s5pv210-pd", + .id = 0, + .dev = { + .platform_data = &s5pv210_pd_audio_pdata, + }, +}; + +struct platform_device s5pv210_pd_cam = { + .name = "reg-s5pv210-pd", + .id = 1, + .dev = { + .platform_data = &s5pv210_pd_cam_pdata, + }, +}; + +struct platform_device s5pv210_pd_tv = { + .name = "reg-s5pv210-pd", + .id = 2, + .dev = { + .platform_data = &s5pv210_pd_tv_pdata, + }, +}; + +struct platform_device s5pv210_pd_lcd = { + .name = "reg-s5pv210-pd", + .id = 3, + .dev = { + .platform_data = &s5pv210_pd_lcd_pdata, + }, +}; + +struct platform_device s5pv210_pd_g3d = { + .name = "reg-s5pv210-pd", + .id = 4, + .dev = { + .platform_data = &s5pv210_pd_g3d_pdata, + }, +}; + +struct platform_device s5pv210_pd_mfc = { + .name = "reg-s5pv210-pd", + .id = 5, + .dev = { + .platform_data = &s5pv210_pd_mfc_pdata, + }, +}; + +static int s5pv210_pd_pwr_done(int ctrl) +{ + unsigned int cnt; + cnt = 1000; + + do { + if (__raw_readl(S5P_BLK_PWR_STAT) & ctrl) + return 0; + udelay(1); + } while (cnt-- > 0); + + return -ETIME; +} + +static int s5pv210_pd_pwr_off(int ctrl) +{ + unsigned int cnt; + cnt = 1000; + + do { + if (!(__raw_readl(S5P_BLK_PWR_STAT) & ctrl)) + return 0; + udelay(1); + } while (cnt-- > 0); + + return -ETIME; +} + +static int s5pv210_pd_ctrl(int ctrlbit, int enable) +{ + u32 pd_reg; + + spin_lock(&pd_lock); + pd_reg = __raw_readl(S5P_NORMAL_CFG); + if (enable) { + __raw_writel((pd_reg | ctrlbit), S5P_NORMAL_CFG); + if (s5pv210_pd_pwr_done(ctrlbit)) + goto out; + } else { + __raw_writel((pd_reg & ~(ctrlbit)), S5P_NORMAL_CFG); + if (s5pv210_pd_pwr_off(ctrlbit)) + goto out; + } + spin_unlock(&pd_lock); + return 0; +out: + spin_unlock(&pd_lock); + return -ETIME; + +} + +static int s5pv210_pd_clk_enable(struct clk_should_be_running *clk_run) +{ + struct clk *clkp; + int i; + + for (i = 0;; i++) { + if (clk_run[i].clk_name == NULL) + break; + + clkp = clk_get(clk_run[i].dev, clk_run[i].clk_name); + + if (IS_ERR(clkp)) { + printk(KERN_ERR "unable to get clock %s\n", + clk_run[i].clk_name); + } else { + clk_enable(clkp); + clk_put(clkp); + } + } + + return 0; +} + +static int s5pv210_pd_clk_disable(struct clk_should_be_running *clk_run) +{ + struct clk *clkp; + int i; + + for (i = 0;; i++) { + if (clk_run[i].clk_name == NULL) + break; + + clkp = clk_get(clk_run[i].dev, clk_run[i].clk_name); + + if (IS_ERR(clkp)) { + printk(KERN_ERR "unable to get clock %s\n", + clk_run[i].clk_name); + } else { + clk_disable(clkp); + clk_put(clkp); + } + } + + return 0; +} + +static int s5pv210_pd_is_enabled(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + return (__raw_readl(S5P_BLK_PWR_STAT) & data->ctrlbit) ? 1 : 0; +} + +static int s5pv210_pd_enable(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + int ret = 0; + + if (data->clk_run) + s5pv210_pd_clk_enable(data->clk_run); + + ret = s5pv210_pd_ctrl(data->ctrlbit, 1); + if (ret < 0) { + printk(KERN_ERR "failed to enable power domain\n"); + } + + if (data->clk_run) + s5pv210_pd_clk_disable(data->clk_run); + + return ret; +} + +static int s5pv210_pd_disable(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + int ret; + + ret = s5pv210_pd_ctrl(data->ctrlbit, 0); + if (ret < 0) { + printk(KERN_ERR "faild to disable power domain\n"); + return ret; + } + + return 0; +} + +static int s5pv210_pd_enable_time(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + return data->startup_delay; +} + +static int s5pv210_pd_get_voltage(struct regulator_dev *dev) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + return data->microvolts; +} + +static int s5pv210_pd_list_voltage(struct regulator_dev *dev, + unsigned selector) +{ + struct s5pv210_pd_data *data = rdev_get_drvdata(dev); + + if (selector != 0) + return -EINVAL; + + return data->microvolts; +} + +static struct regulator_ops s5pv210_pd_ops = { + .is_enabled = s5pv210_pd_is_enabled, + .enable = s5pv210_pd_enable, + .disable = s5pv210_pd_disable, + .enable_time = s5pv210_pd_enable_time, + .get_voltage = s5pv210_pd_get_voltage, + .list_voltage = s5pv210_pd_list_voltage, +}; + +static int __devinit reg_s5pv210_pd_probe(struct platform_device *pdev) +{ + struct s5pv210_pd_config *config = pdev->dev.platform_data; + struct s5pv210_pd_data *drvdata; + int ret; + + drvdata = kzalloc(sizeof(struct s5pv210_pd_data), GFP_KERNEL); + if (drvdata == NULL) { + dev_err(&pdev->dev, "Failed to allocate device data\n"); + ret = -ENOMEM; + goto err; + } + + drvdata->desc.name = kstrdup(config->supply_name, GFP_KERNEL); + if (drvdata->desc.name == NULL) { + dev_err(&pdev->dev, "Failed to allocate supply name\n"); + ret = -ENOMEM; + goto err; + } + + drvdata->desc.type = REGULATOR_VOLTAGE; + drvdata->desc.owner = THIS_MODULE; + drvdata->desc.ops = &s5pv210_pd_ops; + drvdata->desc.n_voltages = 1; + + drvdata->microvolts = config->microvolts; + drvdata->startup_delay = config->startup_delay; + + drvdata->clk_run = config->clk_run; + drvdata->ctrlbit = config->ctrlbit; + spin_lock_init(&pd_lock); + + drvdata->dev = regulator_register(&drvdata->desc, &pdev->dev, + config->init_data, drvdata); + if (IS_ERR(drvdata->dev)) { + ret = PTR_ERR(drvdata->dev); + dev_err(&pdev->dev, "Failed to register regulator: %d\n", ret); + goto err_name; + } + + platform_set_drvdata(pdev, drvdata); + + dev_dbg(&pdev->dev, "%s supplying %duV\n", drvdata->desc.name, + drvdata->microvolts); + + return 0; + +err_name: + kfree(drvdata->desc.name); +err: + kfree(drvdata); + return ret; +} + +static int __devexit reg_s5pv210_pd_remove(struct platform_device *pdev) +{ + struct s5pv210_pd_data *drvdata = platform_get_drvdata(pdev); + + regulator_unregister(drvdata->dev); + kfree(drvdata->desc.name); + kfree(drvdata); + + return 0; +} + +static struct platform_driver regulator_s5pv210_pd_driver = { + .probe = reg_s5pv210_pd_probe, + .remove = __devexit_p(reg_s5pv210_pd_remove), + .driver = { + .name = "reg-s5pv210-pd", + .owner = THIS_MODULE, + }, +}; + +static int __init regulator_s5pv210_pd_init(void) +{ + return platform_driver_register(®ulator_s5pv210_pd_driver); +} +subsys_initcall(regulator_s5pv210_pd_init); + +static void __exit regulator_s5pv210_pd_exit(void) +{ + platform_driver_unregister(®ulator_s5pv210_pd_driver); +} +module_exit(regulator_s5pv210_pd_exit); + +MODULE_AUTHOR("HuiSung Kang <hs1218.kang@samsung.com>"); +MODULE_DESCRIPTION("S5PV210 power domain regulator"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:reg-s5pv210-pd"); diff --git a/arch/arm/mach-s5pv210/setup-fb.c b/arch/arm/mach-s5pv210/setup-fb.c new file mode 100644 index 0000000..85adf23 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fb.c @@ -0,0 +1,226 @@ +/* linux/arch/arm/mach-s5pv210/setup-fb.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMD controller configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/types.h> +#include <plat/clock.h> +#include <plat/gpio-cfg.h> +#include <plat/fb.h> +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> +#include <linux/io.h> +#include <mach/map.h> + +struct platform_device; /* don't need the contents */ + +void s3cfb_cfg_gpio(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + } + + /* mDNIe SEL: why we shall write 0x2 ? */ + writel(0x2, S5P_MDNIE_SEL); + + /* drive strength to max */ + writel(0xffffffff, S5PV210_GPF0_BASE + 0xc); + writel(0xffffffff, S5PV210_GPF1_BASE + 0xc); + writel(0xffffffff, S5PV210_GPF2_BASE + 0xc); + writel(0x000000ff, S5PV210_GPF3_BASE + 0xc); +} + +int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk) +{ + struct clk *sclk = NULL; + struct clk *mout_mpll = NULL; + u32 rate = 0; + + sclk = clk_get(&pdev->dev, "sclk_fimd"); + if (IS_ERR(sclk)) { + dev_err(&pdev->dev, "failed to get sclk for fimd\n"); + goto err_clk1; + } + + mout_mpll = clk_get(&pdev->dev, "mout_mpll"); + if (IS_ERR(mout_mpll)) { + dev_err(&pdev->dev, "failed to get mout_mpll\n"); + goto err_clk2; + } + + clk_set_parent(sclk, mout_mpll); + + if (!rate) + rate = 166750000; + + clk_set_rate(sclk, rate); + dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate); + + clk_put(mout_mpll); + + clk_enable(sclk); + + *s3cfb_clk = sclk; + + return 0; + +err_clk2: + clk_put(sclk); + +err_clk1: + return -EINVAL; +} + +int s3cfb_clk_off(struct platform_device *pdev, struct clk **clk) +{ + clk_disable(*clk); + clk_put(*clk); + + *clk = NULL; + + return 0; +} + +void s3cfb_get_clk_name(char *clk_name) +{ + strcpy(clk_name, "sclk_fimd"); +} +#ifdef CONFIG_FB_S3C_LTE480WV +int s3cfb_backlight_onoff(struct platform_device *pdev, int onoff) +{ + int err; + + err = gpio_request(S5PV210_GPD0(3), "GPD0"); + + if (err) { + printk(KERN_ERR "failed to request GPD0 for " + "lcd backlight control\n"); + return err; + } + + if (onoff) { + gpio_direction_output(S5PV210_GPD0(3), 1); + /* 2009.12.28 by icarus : added for PWM backlight */ + s3c_gpio_cfgpin(S5PV210_GPD0(3), S5PV210_GPD_0_3_TOUT_3); + + } else { + gpio_direction_output(S5PV210_GPD0(3), 0); + } + gpio_free(S5PV210_GPD0(3)); + return 0; +} + +int s3cfb_reset_lcd(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_GPH0(6), "GPH0"); + if (err) { + printk(KERN_ERR "failed to request GPH0 for " + "lcd reset control\n"); + return err; + } + + gpio_direction_output(S5PV210_GPH0(6), 1); + mdelay(100); + + gpio_set_value(S5PV210_GPH0(6), 0); + mdelay(10); + + gpio_set_value(S5PV210_GPH0(6), 1); + mdelay(10); + + gpio_free(S5PV210_GPH0(6)); + + return 0; +} +#elif defined(CONFIG_FB_S3C_HT101HD1) +int s3cfb_backlight_on(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_GPB(2), "GPB"); + if (err) { + printk(KERN_ERR "failed to request GPB for " + "lcd backlight control\n"); + return err; + } + +#ifdef CONFIG_TYPE_PROTO3 + err = gpio_request(S5PV210_GPD0(1), "GPD0"); + if (err) { + printk(KERN_ERR "failed to request GPD0 for " + "lcd backlight control\n"); + return err; + } +#endif + + gpio_direction_output(S5PV210_GPB(2), 1); /* LED_EN (SPI1_MOSI) */ + +#ifdef CONFIG_TYPE_PROTO3 + /* LCD_PWR_EN is only for Proto3 */ + gpio_direction_output(S5PV210_GPD0(1), 1); + mdelay(10); +#endif + + gpio_free(S5PV210_GPB(2)); +#ifdef CONFIG_TYPE_PROTO3 + gpio_free(S5PV210_GPD0(1)); +#endif + + return 0; +} + +int s3cfb_reset_lcd(struct platform_device *pdev) +{ + int err; + + err = gpio_request(S5PV210_GPH0(1), "GPH0"); + if (err) { + printk(KERN_ERR "failed to request GPH0 for " + "lcd reset control\n"); + return err; + } + + gpio_direction_output(S5PV210_GPH0(1), 1); + + gpio_set_value(S5PV210_GPH0(1), 0); + + gpio_set_value(S5PV210_GPH0(1), 1); + + gpio_free(S5PV210_GPH0(1)); + + return 0; +} +#endif diff --git a/arch/arm/mach-s5pv210/setup-fimc0.c b/arch/arm/mach-s5pv210/setup-fimc0.c new file mode 100644 index 0000000..6b4b39b --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fimc0.c @@ -0,0 +1,122 @@ +/* linux/arch/arm/mach-s5pv210/setup-fimc0.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMC 0 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/gpio.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <plat/clock.h> +#include <plat/gpio-cfg.h> +#include <plat/map-s5p.h> +#include <mach/regs-gpio.h> +#include <mach/map.h> +#include <plat/regs-fimc.h> + +struct platform_device; /* don't need the contents */ + +void s3c_fimc0_cfg_gpio(struct platform_device *pdev) +{ + int i = 0; + + /* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */ + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPE0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPE0(i), S3C_GPIO_PULL_NONE); + } + /* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */ + for (i = 0; i < 3; i++) { + s3c_gpio_cfgpin(S5PV210_GPE1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPE1(i), S3C_GPIO_PULL_NONE); + } + +#if defined(CONFIG_MACH_SMDKC110) || defined(CONFIG_MACH_SMDKV210) + s3c_gpio_cfgpin(S5PV210_GPE1(4), S5PV210_GPE1_4_CAM_A_FIELD); + s3c_gpio_setpull(S5PV210_GPE1(4), S3C_GPIO_PULL_NONE); + + /* CAM B port(b0011) : DATA[0-7] */ + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPJ0(i), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PV210_GPJ0(i), S3C_GPIO_PULL_NONE); + } + /* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLCKOUT */ + for (i = 0; i < 5; i++) { + s3c_gpio_cfgpin(S5PV210_GPJ1(i), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PV210_GPJ1(i), S3C_GPIO_PULL_NONE); + } +#endif + + /* note : driver strength to max is unnecessary */ +} + +int s3c_fimc_clk_on(struct platform_device *pdev, struct clk *clk) +{ + struct clk *sclk_fimc_lclk = NULL; + struct clk *mout_fimc_lclk = NULL; + struct clk *mout_mpll = NULL; + + mout_mpll = clk_get(&pdev->dev, "mout_mpll"); + if (IS_ERR(mout_mpll)) { + dev_err(&pdev->dev, "failed to get mout_mpll\n"); + goto err_clk1; + } + + mout_fimc_lclk = clk_get(&pdev->dev, "mout_fimc_lclk"); + if (IS_ERR(mout_fimc_lclk)) { + dev_err(&pdev->dev, "failed to get mout_fimc_lclk\n"); + goto err_clk2; + } + + sclk_fimc_lclk = clk_get(&pdev->dev, "fimc"); + if (IS_ERR(sclk_fimc_lclk)) { + dev_err(&pdev->dev, "failed to get sclk_fimc_lclk\n"); + goto err_clk3; + } + + clk_set_parent(mout_fimc_lclk, mout_mpll); + clk_set_rate(sclk_fimc_lclk, 166750000); + + /* be able to handle clock on/off only with this clock */ + clk = clk_get(&pdev->dev, "fimc"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "failed to get interface clock\n"); + goto err_clk3; + } + + clk_put(mout_mpll); + clk_put(mout_fimc_lclk); + + clk_enable(clk); + + return 0; + +err_clk3: + clk_put(mout_fimc_lclk); + +err_clk2: + clk_put(mout_mpll); + +err_clk1: + return -EINVAL; +} + +int s3c_fimc_clk_off(struct platform_device *pdev, struct clk *clk) +{ + clk_disable(clk); + clk_put(clk); + + clk = NULL; + + return 0; +} diff --git a/arch/arm/mach-s5pv210/setup-fimc1.c b/arch/arm/mach-s5pv210/setup-fimc1.c new file mode 100644 index 0000000..5ec1301 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fimc1.c @@ -0,0 +1,21 @@ +/* linux/arch/arm/mach-s5pv210/setup-fimc1.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMC 1 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> + +void s3c_fimc1_cfg_gpio(struct platform_device *pdev) { } diff --git a/arch/arm/mach-s5pv210/setup-fimc2.c b/arch/arm/mach-s5pv210/setup-fimc2.c new file mode 100644 index 0000000..aaa6f6e --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fimc2.c @@ -0,0 +1,21 @@ +/* linux/arch/arm/mach-s5pv210/setup-fimc2.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base FIMC 2 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> + +void s3c_fimc2_cfg_gpio(struct platform_device *pdev) { } diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c index 0f1cc3a..39b644f 100644 --- a/arch/arm/mach-s5pv210/setup-i2c0.c +++ b/arch/arm/mach-s5pv210/setup-i2c0.c @@ -24,5 +24,5 @@ struct platform_device; /* don't need the contents */ void s3c_i2c0_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); } diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c index f61365a..834b318 100644 --- a/arch/arm/mach-s5pv210/setup-i2c1.c +++ b/arch/arm/mach-s5pv210/setup-i2c1.c @@ -24,5 +24,5 @@ struct platform_device; /* don't need the contents */ void s3c_i2c1_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); } diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c index 2f91b5c..3bdc649 100644 --- a/arch/arm/mach-s5pv210/setup-i2c2.c +++ b/arch/arm/mach-s5pv210/setup-i2c2.c @@ -24,5 +24,5 @@ struct platform_device; /* don't need the contents */ void s3c_i2c2_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); } diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index 3e3ac05..0ecc905 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -23,82 +23,125 @@ #include <plat/regs-sdhci.h> #include <plat/sdhci.h> +#include "herring.h" + void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPG0/GPG1 pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2)); + unsigned int gpio; switch (width) { + /* Channel 0 supports 4 and 8-bit bus width */ case 8: - /* GPG1[3:6] special-function 3 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3)); + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_2X); + } + + case 0: + case 1: case 4: - /* GPG0[3:6] special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2)); - default: + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG0(0); gpio <= S5PV210_GPG0(6); gpio++) { + if (gpio != S5PV210_GPG0(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_2X); + } break; + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); + } + + if (machine_is_herring()) { + s3c_gpio_cfgpin(S5PV210_GPJ2(7), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPJ2(7), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPJ2(7), 1); } - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); + if (machine_is_herring()) { + gpio_direction_output(S5PV210_GPJ2(7), 1); + s3c_gpio_setpull(S5PV210_GPJ2(7), S3C_GPIO_PULL_NONE); } } void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; - /* Set all the necessary GPG1[0:1] pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2)); - - /* Data pin GPG1[3:6] to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2)); - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); + switch (width) { + /* Channel 1 supports 4-bit bus width */ + case 0: + case 1: + case 4: + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG1(0); gpio <= S5PV210_GPG1(6); gpio++) { + if (gpio != S5PV210_GPG1(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_2X); + } + break; + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } } void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPG2[0:1] pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2)); + unsigned int gpio; switch (width) { + /* Channel 2 supports 4 and 8-bit bus width */ case 8: - /* Data pin GPG3[3:6] to special-function 3 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3)); + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_2X); + } + + case 0: + case 1: case 4: - /* Data pin GPG2[3:6] to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2)); - default: + if (machine_is_herring() && herring_is_cdma_wimax_dev()) + break; + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG2(0); gpio <= S5PV210_GPG2(6); gpio++) { + if (gpio != S5PV210_GPG2(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_2X); + } break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } } void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) { - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - - /* Set all the necessary GPG3[0:1] pins to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2)); + unsigned int gpio; - /* Data pin GPG3[3:6] to special-function 2 */ - s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2)); - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2)); + switch (width) { + /* Channel 3 supports 4-bit bus width */ + case 0: + case 1: + case 4: + /* Set all the necessary GPIO function and pull up/down */ + for (gpio = S5PV210_GPG3(0); gpio <= S5PV210_GPG3(6); gpio++) { + if (gpio != S5PV210_GPG3(2)) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + } + s3c_gpio_set_drvstrength(gpio, S3C_GPIO_DRVSTR_2X); + } + break; + default: + printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } } diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index a83b6c9..04ec6af 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -15,6 +15,7 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/irq.h> #include <linux/mmc/card.h> #include <linux/mmc/host.h> @@ -22,6 +23,13 @@ #include <plat/regs-sdhci.h> #include <plat/sdhci.h> +#include <plat/gpio-cfg.h> +#include <plat/devs.h> +#include <mach/regs-gpio.h> +#include <mach/gpio.h> + +#include "herring.h" + /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ char *s5pv210_hsmmc_clksrcs[4] = { @@ -31,33 +39,225 @@ char *s5pv210_hsmmc_clksrcs[4] = { /* [3] = NULL, - reserved */ }; +#define S3C_SDHCI_CTRL3_FCSELTX_INVERT (0) +#define S3C_SDHCI_CTRL3_FCSELTX_BASIC \ + (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2) +#define S3C_SDHCI_CTRL3_FCSELRX_INVERT (0) +#define S3C_SDHCI_CTRL3_FCSELRX_BASIC \ + (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0) + void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, struct mmc_card *card) { - u32 ctrl2, ctrl3; - - /* don't need to alter anything according to card-type */ - - writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); + u32 ctrl2; + u32 ctrl3; ctrl2 = readl(r + S3C_SDHCI_CONTROL2); ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | S3C_SDHCI_CTRL2_DFCNT_NONE | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + if (ios->clock <= (400 * 1000)) { + ctrl2 &= ~(S3C_SDHCI_CTRL2_ENFBCLKTX | + S3C_SDHCI_CTRL2_ENFBCLKRX); + ctrl3 = 0; + } else { + u32 range_start; + u32 range_end; + + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKTX | + S3C_SDHCI_CTRL2_ENFBCLKRX; + + if (card->type == MMC_TYPE_MMC) /* MMC */ + range_start = 20 * 1000 * 1000; + //else /* SD, SDIO */ + // range_start = 25 * 1000 * 1000; + + range_end = 37 * 1000 * 1000; + + if ((ios->clock > range_start) && (ios->clock < range_end)) + ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC | + S3C_SDHCI_CTRL3_FCSELRX_BASIC; + else if (machine_is_herring() && herring_is_cdma_wimax_dev() && + dev->id == 2) { + ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC; + //if(card->type & MMC_TYPE_SDIO) + ctrl3 |= S3C_SDHCI_CTRL3_FCSELRX_BASIC; + //else + // ctrl3 |= S3C_SDHCI_CTRL3_FCSELRX_INVERT; + } else + ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC | + S3C_SDHCI_CTRL3_FCSELRX_INVERT; + } + + + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} + +void s5pv210_adjust_sdhci_cfg_card(struct s3c_sdhci_platdata *pdata, + void __iomem *r, int rw) +{ + u32 ctrl2, ctrl3; + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + ctrl3 = readl(r + S3C_SDHCI_CONTROL3); + + if (rw == 0) { + pdata->rx_cfg++; + if (pdata->rx_cfg == 1) { + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKRX; + ctrl3 |= S3C_SDHCI_CTRL3_FCSELRX_BASIC; + } else if (pdata->rx_cfg == 2) { + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKRX; + ctrl3 &= ~S3C_SDHCI_CTRL3_FCSELRX_BASIC; + } else if (pdata->rx_cfg == 3) { + ctrl2 &= ~(S3C_SDHCI_CTRL2_ENFBCLKTX | + S3C_SDHCI_CTRL2_ENFBCLKRX); + pdata->rx_cfg = 0; + } + } else if (rw == 1) { + pdata->tx_cfg++; + if (pdata->tx_cfg == 1) { + if (ctrl2 & S3C_SDHCI_CTRL2_ENFBCLKRX) { + ctrl2 |= S3C_SDHCI_CTRL2_ENFBCLKTX; + ctrl3 |= S3C_SDHCI_CTRL3_FCSELTX_BASIC; + } else { + ctrl2 &= ~S3C_SDHCI_CTRL2_ENFBCLKTX; + } + } else if (pdata->tx_cfg == 2) { + ctrl2 &= ~S3C_SDHCI_CTRL2_ENFBCLKTX; + pdata->tx_cfg = 0; + } + } else { + printk(KERN_ERR "%s, unknown value rw:%d\n", __func__, rw); + return; + } writel(ctrl2, r + S3C_SDHCI_CONTROL2); writel(ctrl3, r + S3C_SDHCI_CONTROL3); } + +void universal_sdhci2_cfg_ext_cd(void) +{ + printk(KERN_DEBUG "Universal :SD Detect configuration\n"); + s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_NONE); + irq_set_irq_type(IRQ_EINT(28), IRQ_TYPE_EDGE_BOTH); +} + +static struct s3c_sdhci_platdata hsmmc0_platdata = { +#if defined(CONFIG_S5PV210_SD_CH0_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; + +#if defined(CONFIG_S3C_DEV_HSMMC2) +static struct s3c_sdhci_platdata hsmmc2_platdata = { +#if defined(CONFIG_S5PV210_SD_CH2_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; +#endif + +#if defined(CONFIG_S3C_DEV_HSMMC3) +static struct s3c_sdhci_platdata hsmmc3_platdata = { 0 }; +#endif + +static DEFINE_MUTEX(notify_lock); + +#define DEFINE_MMC_CARD_NOTIFIER(num) \ +static void (*hsmmc##num##_notify_func)(struct platform_device *, int state); \ +static int ext_cd_init_hsmmc##num(void (*notify_func)( \ + struct platform_device *, int state)) \ +{ \ + mutex_lock(¬ify_lock); \ + WARN_ON(hsmmc##num##_notify_func); \ + hsmmc##num##_notify_func = notify_func; \ + mutex_unlock(¬ify_lock); \ + return 0; \ +} \ +static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \ + struct platform_device *, int state)) \ +{ \ + mutex_lock(¬ify_lock); \ + WARN_ON(hsmmc##num##_notify_func != notify_func); \ + hsmmc##num##_notify_func = NULL; \ + mutex_unlock(¬ify_lock); \ + return 0; \ +} + +#ifdef CONFIG_S3C_DEV_HSMMC2 +DEFINE_MMC_CARD_NOTIFIER(2) +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 +DEFINE_MMC_CARD_NOTIFIER(3) +#endif + +/* + * call this when you need sd stack to recognize insertion or removal of card + * that can't be told by SDHCI regs + */ +void sdhci_s3c_force_presence_change(struct platform_device *pdev) +{ + void (*notify_func)(struct platform_device *, int state) = NULL; + mutex_lock(¬ify_lock); +#ifdef CONFIG_S3C_DEV_HSMMC2 + if (pdev == &s3c_device_hsmmc2) + notify_func = hsmmc2_notify_func; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + if (pdev == &s3c_device_hsmmc3) + notify_func = hsmmc3_notify_func; +#endif + + if (notify_func) + notify_func(pdev, 1); + else + pr_warn("%s: called for device with no notifier\n", __func__); + mutex_unlock(¬ify_lock); +} +EXPORT_SYMBOL_GPL(sdhci_s3c_force_presence_change); + +void s3c_sdhci_set_platdata(void) +{ +#if defined(CONFIG_S3C_DEV_HSMMC) + if (machine_is_herring()) { /* TODO: move to mach-herring.c */ + hsmmc0_platdata.cd_type = S3C_SDHCI_CD_PERMANENT; + } + s3c_sdhci0_set_platdata(&hsmmc0_platdata); +#endif +#if defined(CONFIG_S3C_DEV_HSMMC2) + if (machine_is_herring()) { + if (herring_is_cdma_wimax_dev()) { + hsmmc2_platdata.cd_type = S3C_SDHCI_CD_EXTERNAL; + hsmmc2_platdata.ext_cd_init = ext_cd_init_hsmmc2; + hsmmc2_platdata.ext_cd_cleanup = ext_cd_cleanup_hsmmc2; + hsmmc2_platdata.built_in = 1; + hsmmc2_platdata.must_maintain_clock = 1; + hsmmc2_platdata.enable_intr_on_resume = 1; + } else { + hsmmc2_platdata.cd_type = S3C_SDHCI_CD_GPIO; + hsmmc2_platdata.ext_cd_gpio = S5PV210_GPH3(4); + hsmmc2_platdata.ext_cd_gpio_invert = true; + universal_sdhci2_cfg_ext_cd(); + } + } + + s3c_sdhci2_set_platdata(&hsmmc2_platdata); +#endif +#if defined(CONFIG_S3C_DEV_HSMMC3) + if (machine_is_herring()) { + hsmmc3_platdata.cd_type = S3C_SDHCI_CD_EXTERNAL; + hsmmc3_platdata.ext_cd_init = ext_cd_init_hsmmc3; + hsmmc3_platdata.ext_cd_cleanup = ext_cd_cleanup_hsmmc3; + hsmmc3_platdata.built_in = 1; + } + s3c_sdhci3_set_platdata(&hsmmc3_platdata); +#endif +}; diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S index a3d6494..758c913 100644 --- a/arch/arm/mach-s5pv210/sleep.S +++ b/arch/arm/mach-s5pv210/sleep.S @@ -49,6 +49,10 @@ ENTRY(s3c_cpu_save) mov pc, r0 resume_with_mmu: + /* Invalidate TLB after mucking with MMU table. */ + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB + ldmfd sp!, { r3 - r12, pc } .ltorg diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 44c0867..6f6c1a6 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -29,6 +29,16 @@ static void __iomem *l2x0_base; static DEFINE_SPINLOCK(l2x0_lock); static uint32_t l2x0_way_mask; /* Bitmask of active ways */ static uint32_t l2x0_size; +static u32 l2x0_cache_id; +static unsigned int l2x0_sets; +static unsigned int l2x0_ways; + +static inline bool is_pl310_rev(int rev) +{ + return (l2x0_cache_id & + (L2X0_CACHE_ID_PART_MASK | L2X0_CACHE_ID_REV_MASK)) == + (L2X0_CACHE_ID_PART_L310 | rev); +} static inline void cache_wait_way(void __iomem *reg, unsigned long mask) { @@ -120,6 +130,23 @@ static void l2x0_cache_sync(void) spin_unlock_irqrestore(&l2x0_lock, flags); } +#ifdef CONFIG_PL310_ERRATA_727915 +static void l2x0_for_each_set_way(void __iomem *reg) +{ + int set; + int way; + unsigned long flags; + + for (way = 0; way < l2x0_ways; way++) { + spin_lock_irqsave(&l2x0_lock, flags); + for (set = 0; set < l2x0_sets; set++) + writel_relaxed((way << 28) | (set << 5), reg); + cache_sync(); + spin_unlock_irqrestore(&l2x0_lock, flags); + } +} +#endif + static void __l2x0_flush_all(void) { debug_writel(0x03); @@ -133,6 +160,13 @@ static void l2x0_flush_all(void) { unsigned long flags; +#ifdef CONFIG_PL310_ERRATA_727915 + if (is_pl310_rev(REV_PL310_R2P0)) { + l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_INV_LINE_IDX); + return; + } +#endif + /* clean all ways */ spin_lock_irqsave(&l2x0_lock, flags); __l2x0_flush_all(); @@ -143,11 +177,20 @@ static void l2x0_clean_all(void) { unsigned long flags; +#ifdef CONFIG_PL310_ERRATA_727915 + if (is_pl310_rev(REV_PL310_R2P0)) { + l2x0_for_each_set_way(l2x0_base + L2X0_CLEAN_LINE_IDX); + return; + } +#endif + /* clean all ways */ spin_lock_irqsave(&l2x0_lock, flags); + debug_writel(0x03); writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask); cache_sync(); + debug_writel(0x00); spin_unlock_irqrestore(&l2x0_lock, flags); } @@ -280,47 +323,46 @@ static void l2x0_disable(void) void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { __u32 aux; - __u32 cache_id; __u32 way_size = 0; - int ways; const char *type; l2x0_base = base; - cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); + l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); aux &= aux_mask; aux |= aux_val; /* Determine the number of ways */ - switch (cache_id & L2X0_CACHE_ID_PART_MASK) { + switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) { case L2X0_CACHE_ID_PART_L310: if (aux & (1 << 16)) - ways = 16; + l2x0_ways = 16; else - ways = 8; + l2x0_ways = 8; type = "L310"; break; case L2X0_CACHE_ID_PART_L210: - ways = (aux >> 13) & 0xf; + l2x0_ways = (aux >> 13) & 0xf; type = "L210"; break; default: /* Assume unknown chips have 8 ways */ - ways = 8; + l2x0_ways = 8; type = "L2x0 series"; break; } - l2x0_way_mask = (1 << ways) - 1; + l2x0_way_mask = (1 << l2x0_ways) - 1; /* * L2 cache Size = Way size * Number of ways */ way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; - way_size = 1 << (way_size + 3); - l2x0_size = ways * way_size * SZ_1K; + way_size = SZ_1K << (way_size + 3); + l2x0_size = l2x0_ways * way_size; + l2x0_sets = way_size / CACHE_LINE_SIZE; /* * Check if l2x0 controller is already enabled. @@ -349,5 +391,5 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", - ways, cache_id, aux, l2x0_size); + l2x0_ways, l2x0_cache_id, aux, l2x0_size); } diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 73b4a8b..6b5441d 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -272,6 +272,11 @@ v6_dma_clean_range: * - end - virtual end address of region */ ENTRY(v6_dma_flush_range) +#ifdef CONFIG_CACHE_FLUSH_RANGE_LIMIT + sub r2, r1, r0 + cmp r2, #CONFIG_CACHE_FLUSH_RANGE_LIMIT + bhi v6_dma_flush_dcache_all +#endif #ifdef CONFIG_DMA_CACHE_RWFO ldrb r2, [r0] @ read for ownership strb r2, [r0] @ write for ownership @@ -294,6 +299,18 @@ ENTRY(v6_dma_flush_range) mcr p15, 0, r0, c7, c10, 4 @ drain write buffer mov pc, lr +#ifdef CONFIG_CACHE_FLUSH_RANGE_LIMIT +v6_dma_flush_dcache_all: + mov r0, #0 +#ifdef HARVARD_CACHE + mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate +#else + mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate +#endif + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + mov pc, lr +#endif + /* * dma_map_area(start, size, dir) * - start - kernel virtual start address diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index e98f5c5..c2a98b8 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -94,3 +94,43 @@ config S5P_SETUP_MIPIPHY bool help Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices + +# FB part +config S5P_DEV_FB + bool + depends on FB_S3C + default y + help + Compile in platform device definitions for FIMD controller + +config S5P_HIGH_RES_TIMERS + bool "HRtimer and Dynamic Tick support" + select GENERIC_CLOCKEVENTS + select HIGH_RES_TIMERS + select HRT_RTC + select NO_HZ + default n + help + Support for HRtimer and Dynamic Tick system. + +config HRT_RTC + bool + depends on S5P_HIGH_RES_TIMERS + default y + help + RTC and System timer are used as HRT + +# MFC part +config S5P_DEV_MFC + bool + default y if CPU_FREQ + default n + help + Compile in platform device definitions for MFC + +config S5P_SETUP_MFC + bool + default n + help + Common setup code for MFC + diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index e234cc4..a9b3cb7 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -17,12 +17,17 @@ obj-y += dev-uart.o obj-y += cpu.o obj-y += clock.o obj-y += irq.o -obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o +obj-y += devs.o +obj-y += bootmem.o +obj-y += reset.o +obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o irq-eint-group.o obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += irq-pm.o +ifndef CONFIG_S5P_HIGH_RES_TIMERS obj-$(CONFIG_S5P_HRT) += s5p-time.o +endif # devices @@ -35,3 +40,22 @@ obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o obj-$(CONFIG_S5P_DEV_USB_EHCI) += dev-ehci.o obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o + +# PM support + +# PM support + +obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += irq-pm.o + +ifdef CONFIG_S5P_HIGH_RES_TIMERS +ifdef CONFIG_HRT_RTC +obj-y += hr-time-rtc.o +endif +endif + +obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o +obj-$(CONFIG_S5P_SETUP_MFC) += setup-mfc.o + + +EXTRA_CFLAGS += -Idrivers/video/samsung diff --git a/arch/arm/plat-s5p/bootmem.c b/arch/arm/plat-s5p/bootmem.c new file mode 100644 index 0000000..8a79c34 --- /dev/null +++ b/arch/arm/plat-s5p/bootmem.c @@ -0,0 +1,144 @@ +/* linux/arch/arm/plat-s5p/bootmem.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Bootmem helper functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/err.h> +#include <linux/memblock.h> +#include <linux/mm.h> +#include <linux/swap.h> +#include <asm/setup.h> +#include <linux/io.h> +#include <mach/memory.h> +#include <plat/media.h> +#include <mach/media.h> + +static struct s5p_media_device *media_devs; +static int nr_media_devs; + +static dma_addr_t media_base[NR_BANKS]; + +static struct s5p_media_device *s5p_get_media_device(int dev_id, int bank) +{ + struct s5p_media_device *mdev = NULL; + int i = 0, found = 0; + + if (dev_id < 0) + return NULL; + + while (!found && (i < nr_media_devs)) { + mdev = &media_devs[i]; + if (mdev->id == dev_id && mdev->bank == bank) + found = 1; + else + i++; + } + + if (!found) + mdev = NULL; + + return mdev; +} + +dma_addr_t s5p_get_media_memory_bank(int dev_id, int bank) +{ + struct s5p_media_device *mdev; + + mdev = s5p_get_media_device(dev_id, bank); + if (!mdev) { + printk(KERN_ERR "invalid media device\n"); + return 0; + } + + if (!mdev->paddr) { + printk(KERN_ERR "no memory for %s\n", mdev->name); + return 0; + } + + return mdev->paddr; +} +EXPORT_SYMBOL(s5p_get_media_memory_bank); + +size_t s5p_get_media_memsize_bank(int dev_id, int bank) +{ + struct s5p_media_device *mdev; + + mdev = s5p_get_media_device(dev_id, bank); + if (!mdev) { + printk(KERN_ERR "invalid media device\n"); + return 0; + } + + return mdev->memsize; +} +EXPORT_SYMBOL(s5p_get_media_memsize_bank); + +dma_addr_t s5p_get_media_membase_bank(int bank) +{ + if (bank > meminfo.nr_banks) { + printk(KERN_ERR "invalid bank.\n"); + return -EINVAL; + } + + return media_base[bank]; +} +EXPORT_SYMBOL(s5p_get_media_membase_bank); + +void s5p_reserve_bootmem(struct s5p_media_device *mdevs, + int nr_mdevs, size_t boundary) +{ + struct s5p_media_device *mdev; + u64 start, end; + int i, ret; + + media_devs = mdevs; + nr_media_devs = nr_mdevs; + + for (i = 0; i < meminfo.nr_banks; i++) + media_base[i] = meminfo.bank[i].start + meminfo.bank[i].size; + + for (i = 0; i < nr_media_devs; i++) { + mdev = &media_devs[i]; + if (mdev->memsize <= 0) + continue; + + if (!mdev->paddr) { + start = meminfo.bank[mdev->bank].start; + end = start + meminfo.bank[mdev->bank].size; + + if (boundary && (boundary < end - start)) + start = end - boundary; + + mdev->paddr = memblock_find_in_range(start, end, + mdev->memsize, PAGE_SIZE); + } + + ret = memblock_remove(mdev->paddr, mdev->memsize); + if (ret < 0) + pr_err("memblock_reserve(%x, %x) failed\n", + mdev->paddr, mdev->memsize); + + if (media_base[mdev->bank] > mdev->paddr) + media_base[mdev->bank] = mdev->paddr; + + printk(KERN_INFO "s5p: %lu bytes system memory reserved " + "for %s at 0x%08x, %d-bank base(0x%08x)\n", + (unsigned long) mdev->memsize, mdev->name, mdev->paddr, + mdev->bank, media_base[mdev->bank]); + } +} + +/* FIXME: temporary implementation to avoid compile error */ +int dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) +{ + return 0; +} + + diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 8d081d9..10037b3 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -38,6 +38,13 @@ struct clk clk_ext_xtal_mux = { struct clk clk_xusbxti = { .name = "xusbxti", .id = -1, + .rate = 24000000, +}; + +struct clk clk_xrtcxti = { + .name = "xrtcxti", + .id = -1, + .rate = 32768, }; struct clk s5p_clk_27m = { @@ -170,6 +177,8 @@ unsigned long s5p_epll_get_rate(struct clk *clk) static struct clk *s5p_clks[] __initdata = { &clk_ext_xtal_mux, + &clk_xrtcxti, + &clk_xusbxti, &clk_48m, &s5p_clk_27m, &clk_fout_apll, @@ -178,7 +187,6 @@ static struct clk *s5p_clks[] __initdata = { &clk_fout_dpll, &clk_fout_vpll, &clk_vpll, - &clk_xusbxti, }; void __init s5p_register_clocks(unsigned long xtal_freq) diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c index e3aabef..f61317c 100644 --- a/arch/arm/plat-s5p/dev-csis0.c +++ b/arch/arm/plat-s5p/dev-csis0.c @@ -11,6 +11,9 @@ #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/platform_device.h> + +#include <plat/csis.h> +#include <plat/mipi_csis.h> #include <mach/map.h> static struct resource s5p_mipi_csis0_resource[] = { @@ -32,3 +35,26 @@ struct platform_device s5p_device_mipi_csis0 = { .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource), .resource = s5p_mipi_csis0_resource, }; + +static struct s3c_platform_csis default_csis_data __initdata = { + .srclk_name = "mout_mpll", + .clk_name = "sclk_csis", + .clk_rate = 166000000, +}; + +void __init s3c_csis_set_platdata(struct s3c_platform_csis *pd) +{ + struct s3c_platform_csis *npd; + + if (!pd) + pd = &default_csis_data; + + npd = kmemdup(pd, sizeof(struct s3c_platform_csis), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + + npd->cfg_gpio = NULL; + npd->cfg_phy_global = s5p_csis_phy_enable; + + s5p_device_mipi_csis0.dev.platform_data = npd; +} diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c new file mode 100644 index 0000000..62d9f21 --- /dev/null +++ b/arch/arm/plat-s5p/dev-mfc.c @@ -0,0 +1,65 @@ +/* arch/arm/plat-s5p/dev-mfc.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Device definition for MFC device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <mach/map.h> +#include <asm/irq.h> +#include <plat/mfc.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/media.h> +#include <mach/media.h> + +static struct s3c_platform_mfc s3c_mfc_pdata = { + .buf_phy_base[0] = 0, + .buf_phy_base[1] = 0, + .buf_phy_size[0] = 0, + .buf_phy_size[1] = 0, +}; + +static struct resource s3c_mfc_resources[] = { + [0] = { + .start = S5PV210_PA_MFC, + .end = S5PV210_PA_MFC + S5PV210_SZ_MFC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MFC, + .end = IRQ_MFC, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s3c_device_mfc = { + .name = "s3c-mfc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_mfc_resources), + .resource = s3c_mfc_resources, + .dev = { + .platform_data = &s3c_mfc_pdata, + }, +}; + +void __init s3c_mfc_set_platdata(struct s3c_platform_mfc *pd) +{ + s3c_mfc_pdata.buf_phy_base[0] = + (u32)s5p_get_media_memory_bank(S5P_MDEV_MFC, 0); + s3c_mfc_pdata.buf_phy_size[0] = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_MFC, 0); + s3c_mfc_pdata.buf_phy_base[1] = + (u32)s5p_get_media_memory_bank(S5P_MDEV_MFC, 1); + s3c_mfc_pdata.buf_phy_size[1] = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_MFC, 1); +} + diff --git a/arch/arm/plat-s5p/devs.c b/arch/arm/plat-s5p/devs.c new file mode 100644 index 0000000..a5bacca --- /dev/null +++ b/arch/arm/plat-s5p/devs.c @@ -0,0 +1,713 @@ +/* linux/arch/arm/plat-s5p/devs.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base S5P platform device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <mach/hardware.h> +#include <mach/map.h> +#include <mach/dma.h> +#include <mach/adc.h> + + +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> +#include <plat/fb.h> +#include <plat/fimc.h> +#include <plat/csis.h> +#include <plat/media.h> +#include <plat/jpeg.h> +#include <mach/media.h> +#include <s3cfb.h> + +#if defined CONFIG_USB_S3C_OTG_HOST +/* USB Device (OTG hcd)*/ +static struct resource s3c_usb_otghcd_resource[] = { + [0] = { + .start = S3C_PA_OTG, + .end = S3C_PA_OTG + S3C_SZ_OTG - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_OTG, + .end = IRQ_OTG, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_usb_otghcd_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_usb_otghcd = { + .name = "s3c_otghcd", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb_otghcd_resource), + .resource = s3c_usb_otghcd_resource, + .dev = { + .dma_mask = &s3c_device_usb_otghcd_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_usb_otghcd); +#endif + +#if defined CONFIG_USB_DWC_OTG +/* USB Device (OTG hcd)*/ +static struct resource s3c_usb_dwcotg_resource[] = { + [0] = { + .start = S3C_PA_OTG, + .end = S3C_PA_OTG + S3C_SZ_OTG - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_OTG, + .end = IRQ_OTG, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_usb_dwcotg_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_usb_dwcotg = { + .name = "dwc_otg", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb_dwcotg_resource), + .resource = s3c_usb_dwcotg_resource, + .dev = { + .dma_mask = &s3c_device_usb_dwcotg_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_usb_dwcotg); +#endif + +/* RTC */ +static struct resource s5p_rtc_resource[] = { + [0] = { + .start = S3C_PA_RTC, + .end = S3C_PA_RTC + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTC_TIC, + .end = IRQ_RTC_TIC, + .flags = IORESOURCE_IRQ + } +}; + +struct platform_device s5p_device_rtc = { + .name = "s3c2410-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_rtc_resource), + .resource = s5p_rtc_resource, +}; + +#ifdef CONFIG_S5P_ADC +/* ADCTS */ +static struct resource s3c_adc_resource[] = { + [0] = { + .start = SAMSUNG_PA_ADC, + .end = SAMSUNG_PA_ADC + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PENDN, + .end = IRQ_PENDN, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_ADC, + .end = IRQ_ADC, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s3c_device_adc = { + .name = "s3c-adc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_adc_resource), + .resource = s3c_adc_resource, +}; + +void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd) +{ + struct s3c_adc_mach_info *npd; + + npd = kmalloc(sizeof(*npd), GFP_KERNEL); + if (npd) { + memcpy(npd, pd, sizeof(*npd)); + s3c_device_adc.dev.platform_data = npd; + } else { + printk(KERN_ERR "no memory for ADC platform data\n"); + } +} +#endif /* CONFIG_S5P_ADC */ + +#if defined(CONFIG_VIDEO_MFC51) || defined(CONFIG_VIDEO_MFC50) +static struct resource s5p_mfc_resources[] = { + [0] = { + .start = S5P_PA_MFC, + .end = S5P_PA_MFC + S5P_SZ_MFC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MFC, + .end = IRQ_MFC, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s5p_device_mfc = { + .name = "mfc", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_mfc_resources), + .resource = s5p_mfc_resources, +}; +#endif + +#if defined(CONFIG_S5P_DEV_FB) +static struct resource s3cfb_resource[] = { + [0] = { + .start = S5P_PA_LCD, + .end = S5P_PA_LCD + S5P_SZ_LCD - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LCD1, + .end = IRQ_LCD1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_LCD0, + .end = IRQ_LCD0, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 fb_dma_mask = 0xffffffffUL; + +struct platform_device s3c_device_fb = { + .name = "s3cfb", + .id = -1, + .num_resources = ARRAY_SIZE(s3cfb_resource), + .resource = s3cfb_resource, + .dev = { + .dma_mask = &fb_dma_mask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +static struct s3c_platform_fb default_fb_data __initdata = { +#if defined(CONFIG_CPU_S5PV210_EVT0) + .hw_ver = 0x60, +#else + .hw_ver = 0x62, +#endif + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_WORD | FB_SWAP_HWORD, +}; + +void __init s3cfb_set_platdata(struct s3c_platform_fb *pd) +{ + struct s3c_platform_fb *npd; + struct s3cfb_lcd *lcd; + phys_addr_t pmem_start; + int i, default_win, num_overlay_win; + int frame_size; + + if (!pd) + pd = &default_fb_data; + + npd = kmemdup(pd, sizeof(struct s3c_platform_fb), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else { + for (i = 0; i < npd->nr_wins; i++) + npd->nr_buffers[i] = 1; + + default_win = npd->default_win; + num_overlay_win = CONFIG_FB_S3C_NUM_OVLY_WIN; + + if (num_overlay_win >= default_win) { + printk(KERN_WARNING "%s: NUM_OVLY_WIN should be less than default \ + window number. set to 0.\n", __func__); + num_overlay_win = 0; + } + + for (i = 0; i < num_overlay_win; i++) + npd->nr_buffers[i] = CONFIG_FB_S3C_NUM_BUF_OVLY_WIN; + npd->nr_buffers[default_win] = CONFIG_FB_S3C_NR_BUFFERS; + + lcd = (struct s3cfb_lcd *)npd->lcd; + frame_size = (lcd->width * lcd->height * 4); + + s3cfb_get_clk_name(npd->clk_name); + npd->backlight_onoff = NULL; + npd->clk_on = s3cfb_clk_on; + npd->clk_off = s3cfb_clk_off; + + /* set starting physical address & size of memory region for overlay + * window */ + pmem_start = s5p_get_media_memory_bank(S5P_MDEV_FIMD, 1); + for (i = 0; i < num_overlay_win; i++) { + npd->pmem_start[i] = pmem_start; + npd->pmem_size[i] = frame_size * npd->nr_buffers[i]; + pmem_start += npd->pmem_size[i]; + } + + /* set starting physical address & size of memory region for default + * window */ + npd->pmem_start[default_win] = pmem_start; + npd->pmem_size[default_win] = frame_size * npd->nr_buffers[default_win]; + + s3c_device_fb.dev.platform_data = npd; + } +} +#endif + +#if defined(CONFIG_VIDEO_FIMC) || defined(CONFIG_CPU_FREQ) /* TODO: use existing dev */ +static struct resource s3c_fimc0_resource[] = { + [0] = { + .start = S5P_PA_FIMC0, + .end = S5P_PA_FIMC0 + S5P_SZ_FIMC0 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FIMC0, + .end = IRQ_FIMC0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_fimc0 = { + .name = "s3c-fimc", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_fimc0_resource), + .resource = s3c_fimc0_resource, +}; + +static struct s3c_platform_fimc default_fimc0_data __initdata = { + .default_cam = CAMERA_PAR_A, + .hw_ver = 0x45, +}; + +void __init s3c_fimc0_set_platdata(struct s3c_platform_fimc *pd) +{ + struct s3c_platform_fimc *npd; + + if (!pd) + pd = &default_fimc0_data; + + npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else { + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_fimc0_cfg_gpio; + + if (!npd->clk_on) + npd->clk_on = s3c_fimc_clk_on; + + if (!npd->clk_off) + npd->clk_off = s3c_fimc_clk_off; + + npd->hw_ver = 0x45; + + /* starting physical address of memory region */ + npd->pmem_start = s5p_get_media_memory_bank(S5P_MDEV_FIMC0, 1); + /* size of memory region */ + npd->pmem_size = s5p_get_media_memsize_bank(S5P_MDEV_FIMC0, 1); + + s3c_device_fimc0.dev.platform_data = npd; + } +} + +static struct resource s3c_fimc1_resource[] = { + [0] = { + .start = S5P_PA_FIMC1, + .end = S5P_PA_FIMC1 + S5P_SZ_FIMC1 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FIMC1, + .end = IRQ_FIMC1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_fimc1 = { + .name = "s3c-fimc", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_fimc1_resource), + .resource = s3c_fimc1_resource, +}; + +static struct s3c_platform_fimc default_fimc1_data __initdata = { + .default_cam = CAMERA_PAR_A, + .hw_ver = 0x50, +}; + +void __init s3c_fimc1_set_platdata(struct s3c_platform_fimc *pd) +{ + struct s3c_platform_fimc *npd; + + if (!pd) + pd = &default_fimc1_data; + + npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else { + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_fimc1_cfg_gpio; + + if (!npd->clk_on) + npd->clk_on = s3c_fimc_clk_on; + + if (!npd->clk_off) + npd->clk_off = s3c_fimc_clk_off; + + npd->hw_ver = 0x50; + + /* starting physical address of memory region */ + npd->pmem_start = s5p_get_media_memory_bank(S5P_MDEV_FIMC1, 1); + /* size of memory region */ + npd->pmem_size = s5p_get_media_memsize_bank(S5P_MDEV_FIMC1, 1); + + s3c_device_fimc1.dev.platform_data = npd; + } +} + +static struct resource s3c_fimc2_resource[] = { + [0] = { + .start = S5P_PA_FIMC2, + .end = S5P_PA_FIMC2 + S5P_SZ_FIMC2 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FIMC2, + .end = IRQ_FIMC2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_fimc2 = { + .name = "s3c-fimc", + .id = 2, + .num_resources = ARRAY_SIZE(s3c_fimc2_resource), + .resource = s3c_fimc2_resource, +}; + +static struct s3c_platform_fimc default_fimc2_data __initdata = { + .default_cam = CAMERA_PAR_A, + .hw_ver = 0x45, +}; + +void __init s3c_fimc2_set_platdata(struct s3c_platform_fimc *pd) +{ + struct s3c_platform_fimc *npd; + + if (!pd) + pd = &default_fimc2_data; + + npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else { + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_fimc2_cfg_gpio; + + if (!npd->clk_on) + npd->clk_on = s3c_fimc_clk_on; + + if (!npd->clk_off) + npd->clk_off = s3c_fimc_clk_off; + + npd->hw_ver = 0x45; + + /* starting physical address of memory region */ + npd->pmem_start = s5p_get_media_memory_bank(S5P_MDEV_FIMC2, 1); + /* size of memory region */ + npd->pmem_size = s5p_get_media_memsize_bank(S5P_MDEV_FIMC2, 1); + + s3c_device_fimc2.dev.platform_data = npd; + } +} + +static struct resource s3c_ipc_resource[] = { + [0] = { + .start = S5P_PA_IPC, + .end = S5P_PA_IPC + S5P_SZ_IPC - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device s3c_device_ipc = { + .name = "s3c-ipc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_ipc_resource), + .resource = s3c_ipc_resource, +}; +#endif + +/* JPEG controller */ +static struct s3c_platform_jpeg default_jpeg_data __initdata = { + .max_main_width = 2560, + .max_main_height = 1920, + .max_thumb_width = 0, + .max_thumb_height = 0, +}; + +void __init s3c_jpeg_set_platdata(struct s3c_platform_jpeg *pd) +{ + struct s3c_platform_jpeg *npd; + + if (!pd) + pd = &default_jpeg_data; + + npd = kmemdup(pd, sizeof(struct s3c_platform_jpeg), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else + s3c_device_jpeg.dev.platform_data = npd; +} + +static struct resource s3c_jpeg_resource[] = { + [0] = { + .start = S5PV210_PA_JPEG, + .end = S5PV210_PA_JPEG + S5PV210_SZ_JPEG - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_JPEG, + .end = IRQ_JPEG, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s3c_device_jpeg = { + .name = "s3c-jpg", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_jpeg_resource), + .resource = s3c_jpeg_resource, +}; + +/* G3D */ +struct platform_device s3c_device_g3d = { + .name = "pvrsrvkm", + .id = -1, +}; + +struct platform_device s3c_device_lcd = { + .name = "s3c_lcd", + .id = -1, +}; + +/* rotator interface */ +static struct resource s5p_rotator_resource[] = { + [0] = { + .start = S5P_PA_ROTATOR, + .end = S5P_PA_ROTATOR + S5P_SZ_ROTATOR - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_ROTATOR, + .end = IRQ_ROTATOR, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s5p_device_rotator = { + .name = "s5p-rotator", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_rotator_resource), + .resource = s5p_rotator_resource +}; + +/* TVOUT interface */ +static struct resource s5p_tvout_resources[] = { + [0] = { + .start = S5P_PA_TVENC, + .end = S5P_PA_TVENC + S5P_SZ_TVENC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S5P_PA_VP, + .end = S5P_PA_VP + S5P_SZ_VP - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = S5P_PA_MIXER, + .end = S5P_PA_MIXER + S5P_SZ_MIXER - 1, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = S5P_PA_HDMI, + .end = S5P_PA_HDMI + S5P_SZ_HDMI - 1, + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = S5P_I2C_HDMI_PHY, + .end = S5P_I2C_HDMI_PHY + S5P_I2C_HDMI_SZ_PHY - 1, + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = IRQ_MIXER, + .end = IRQ_MIXER, + .flags = IORESOURCE_IRQ, + }, + [6] = { + .start = IRQ_HDMI, + .end = IRQ_HDMI, + .flags = IORESOURCE_IRQ, + }, + [7] = { + .start = IRQ_TVENC, + .end = IRQ_TVENC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_tvout = { + .name = "s5p-tvout", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_tvout_resources), + .resource = s5p_tvout_resources, +}; + +/* CEC */ +static struct resource s5p_cec_resources[] = { + [0] = { + .start = S5P_PA_CEC, + .end = S5P_PA_CEC + S5P_SZ_CEC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CEC, + .end = IRQ_CEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_cec = { + .name = "s5p-cec", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_cec_resources), + .resource = s5p_cec_resources, +}; + +/* HPD */ +struct platform_device s5p_device_hpd = { + .name = "s5p-hpd", + .id = -1, +}; + +#ifdef CONFIG_USB_SUPPORT +#ifdef CONFIG_USB_ARCH_HAS_EHCI + /* USB Host Controlle EHCI registrations */ +static struct resource s3c_usb__ehci_resource[] = { + [0] = { + .start = S5P_PA_USB_EHCI, + .end = S5P_PA_USB_EHCI + S5P_SZ_USB_EHCI - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_UHOST, + .end = IRQ_UHOST, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_usb_ehci_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_usb_ehci = { + .name = "s5p-ehci", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb__ehci_resource), + .resource = s3c_usb__ehci_resource, + .dev = { + .dma_mask = &s3c_device_usb_ehci_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; +#endif /* CONFIG_USB_ARCH_HAS_EHCI */ + +#ifdef CONFIG_USB_ARCH_HAS_OHCI +/* USB Host Controlle OHCI registrations */ +static struct resource s3c_usb__ohci_resource[] = { + [0] = { + .start = S5P_PA_USB_OHCI, + .end = S5P_PA_USB_OHCI + S5P_SZ_USB_OHCI - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_UHOST, + .end = IRQ_UHOST, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_usb_ohci_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_usb_ohci = { + .name = "s5p-ohci", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb__ohci_resource), + .resource = s3c_usb__ohci_resource, + .dev = { + .dma_mask = &s3c_device_usb_ohci_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; +#endif /* CONFIG_USB_ARCH_HAS_EHCI */ + +/* USB Device (Gadget)*/ +static struct resource s3c_usbgadget_resource[] = { + [0] = { + .start = S3C_PA_OTG, + .end = S3C_PA_OTG + S3C_SZ_OTG - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_OTG, + .end = IRQ_OTG, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s3c_device_usbgadget = { + .name = "s3c-usbgadget", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), + .resource = s3c_usbgadget_resource, +}; +#endif + diff --git a/arch/arm/plat-s5p/hr-time-rtc.c b/arch/arm/plat-s5p/hr-time-rtc.c new file mode 100644 index 0000000..9dfc727 --- /dev/null +++ b/arch/arm/plat-s5p/hr-time-rtc.c @@ -0,0 +1,512 @@ +/* + * linux/arch/arm/plat-s5p/hr-time-rtc.c + * + * S5P Timers + * + * Copyright (c) 2006 Samsung Electronics + * + * + * S5P (and compatible) HRT support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/io.h> + +#include <asm/system.h> +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> +#include <asm/mach-types.h> +#include <mach/map.h> +#include <plat/regs-timer.h> +#include <plat/regs-rtc.h> +#include <plat/regs-systimer.h> +#include <mach/regs-irq.h> +#include <mach/regs-clock.h> +#include <mach/tick.h> + +#include <plat/clock.h> +#include <plat/cpu.h> + +static unsigned long long time_stamp; +static unsigned long long s5p_sched_timer_overflows; +static unsigned long long old_overflows; +static cycle_t last_ticks; + +/* Sched timer interrupt is not processed right after + * timer counter expired + */ +static unsigned int pending_irq; +#define USE_SYSTIMER_IRQ + +/* sched_timer_running + * 0 : sched timer stopped or not initialized + * 1 : sched timer started + */ +static unsigned int sched_timer_running; + +void __iomem *rtc_base = S5P_VA_RTC; +static struct clk *clk_event; +static struct clk *clk_sched; +static int tick_timer_mode; /* 0: oneshot, 1: autoreload */ + +#define RTC_CLOCK (32768) +#define RTC_DEFAULT_TICK ((RTC_CLOCK / HZ) - 1) +/* + * Helper functions + * s5p_systimer_read() : Read from System timer register + * s5p_systimer_write(): Write to System timer register + * + */ +static unsigned int s5p_systimer_read(unsigned int *reg_offset) +{ + return __raw_readl(reg_offset); +} + +static unsigned int s5p_systimer_write(unsigned int *reg_offset, + unsigned int value) +{ + unsigned int temp_regs; + + __raw_writel(value, reg_offset); + + if (reg_offset == S5P_SYSTIMER_TCON) { + while (!(__raw_readl(S5P_SYSTIMER_INT_CSTAT) & + S5P_SYSTIMER_INT_TCON)) + ; + temp_regs = __raw_readl(S5P_SYSTIMER_INT_CSTAT); + temp_regs |= S5P_SYSTIMER_INT_TCON; + __raw_writel(temp_regs, S5P_SYSTIMER_INT_CSTAT); + + } else if (reg_offset == S5P_SYSTIMER_ICNTB) { + while (!(__raw_readl(S5P_SYSTIMER_INT_CSTAT) & + S5P_SYSTIMER_INT_ICNTB)) + ; + temp_regs = __raw_readl(S5P_SYSTIMER_INT_CSTAT); + temp_regs |= S5P_SYSTIMER_INT_ICNTB; + __raw_writel(temp_regs, S5P_SYSTIMER_INT_CSTAT); + + } else if (reg_offset == S5P_SYSTIMER_TICNTB) { + while (!(__raw_readl(S5P_SYSTIMER_INT_CSTAT) & + S5P_SYSTIMER_INT_TICNTB)) + ; + temp_regs = __raw_readl(S5P_SYSTIMER_INT_CSTAT); + temp_regs |= S5P_SYSTIMER_INT_TICNTB; + __raw_writel(temp_regs, S5P_SYSTIMER_INT_CSTAT); + } + + return 0; +} + +unsigned int get_rtc_cnt(void) +{ + unsigned int ticcnt, current_cnt, rtccnt; + + ticcnt = __raw_readl(rtc_base + S3C2410_TICNT); + current_cnt = __raw_readl(rtc_base + S3C2410_CURTICCNT); + rtccnt = ticcnt - current_cnt; + + return rtccnt; +} + +static void s5p_tick_timer_setup(void); + +static void s5p_tick_timer_start(unsigned long load_val, + int autoreset) +{ + unsigned int tmp; + + tmp = __raw_readl(rtc_base + S3C2410_RTCCON) & + ~(S3C_RTCCON_TICEN); + __raw_writel(tmp, rtc_base + S3C2410_RTCCON); + + __raw_writel(load_val, rtc_base + S3C2410_TICNT); + + tmp |= S3C_RTCCON_TICEN; + + __raw_writel(tmp, rtc_base + S3C2410_RTCCON); +} + +static inline void s5p_tick_timer_stop(void) +{ + unsigned int tmp; + + tmp = __raw_readl(rtc_base + S3C2410_RTCCON) & + ~(S3C_RTCCON_TICEN); + + __raw_writel(tmp, rtc_base + S3C2410_RTCCON); +} + +static void s5p_sched_timer_start(unsigned long load_val, + int autoreset) +{ + unsigned long tcon; + unsigned long tcnt; + unsigned long tcfg; + + tcnt = TICK_MAX; /* default value for tcnt */ + + /* initialize system timer clock */ + tcfg = s5p_systimer_read(S5P_SYSTIMER_TCFG); + + tcfg &= ~S5P_SYSTIMER_TCLK_MASK; + tcfg |= S5P_SYSTIMER_TCLK_USB; + + s5p_systimer_write(S5P_SYSTIMER_TCFG, tcfg); + + /* TCFG must not be changed at run-time. + * If you want to change TCFG, stop timer(TCON[0] = 0) + */ + s5p_systimer_write(S5P_SYSTIMER_TCON, 0); + + /* read the current timer configuration bits */ + tcon = s5p_systimer_read(S5P_SYSTIMER_TCON); + tcfg = s5p_systimer_read(S5P_SYSTIMER_TCFG); + + tcfg &= ~S5P_SYSTIMER_TCLK_MASK; + tcfg |= S5P_SYSTIMER_TCLK_USB; + tcfg &= ~S5P_SYSTIMER_PRESCALER_MASK; + + /* check to see if timer is within 16bit range... */ + if (tcnt > TICK_MAX) { + panic("setup_timer: cannot configure timer!"); + return; + } + + s5p_systimer_write(S5P_SYSTIMER_TCFG, tcfg); + + s5p_systimer_write(S5P_SYSTIMER_TICNTB, tcnt); + +#if !defined(USE_SYSTIMER_IRQ) + /* set timer con */ + tcon = (S5P_SYSTIMER_START | S5P_SYSTIMER_AUTO_RELOAD); + s5p_systimer_write(S5P_SYSTIMER_TCON, tcon); +#else + /* set timer con */ + tcon = S5P_SYSTIMER_INT_AUTO | S5P_SYSTIMER_START | + S5P_SYSTIMER_AUTO_RELOAD; + s5p_systimer_write(S5P_SYSTIMER_TCON, tcon); + + tcon |= S5P_SYSTIMER_INT_START; + s5p_systimer_write(S5P_SYSTIMER_TCON, tcon); + + /* Interrupt Start and Enable */ + s5p_systimer_write(S5P_SYSTIMER_INT_CSTAT, + (S5P_SYSTIMER_INT_ICNTEIE | + S5P_SYSTIMER_INT_INTENABLE)); +#endif + sched_timer_running = 1; +} + +/* + * RTC tick : count down to zero, interrupt, reload + */ +static int s5p_tick_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + /* printk(KERN_INFO "%d\n", cycles); */ + if (cycles == 0) /* Should be larger than 0 */ + cycles = 1; + s5p_tick_timer_start(cycles, 0); + return 0; +} + +static void s5p_tick_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + tick_timer_mode = 1; + break; + case CLOCK_EVT_MODE_ONESHOT: + s5p_tick_timer_stop(); + tick_timer_mode = 0; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + /* Sched timer stopped */ + sched_timer_running = 0; + + /* Reset sched_clock variables after sleep/wakeup */ + last_ticks = 0; + s5p_sched_timer_overflows = 0; + old_overflows = 0; + pending_irq = 0; + break; + case CLOCK_EVT_MODE_RESUME: + s5p_tick_timer_setup(); + s5p_sched_timer_start(~0, 1); + break; + } +} + +static struct clock_event_device clockevent_tick_timer = { + .name = "S5PC110 event timer", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = s5p_tick_set_next_event, + .set_mode = s5p_tick_set_mode, +}; + +static irqreturn_t s5p_tick_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_tick_timer; + + __raw_writel(S3C_INTP_TIC, rtc_base + S3C_INTP); + /* In case of oneshot mode */ + if (tick_timer_mode == 0) + s5p_tick_timer_stop(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction s5p_tick_timer_irq = { + .name = "rtc-tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = s5p_tick_timer_interrupt, +}; + +static void s5p_init_dynamic_tick_timer(unsigned long rate) +{ + tick_timer_mode = 1; + + s5p_tick_timer_stop(); + + s5p_tick_timer_start((rate / HZ) - 1, 1); + + clockevent_tick_timer.mult = div_sc(rate, NSEC_PER_SEC, + clockevent_tick_timer.shift); + clockevent_tick_timer.max_delta_ns = + clockevent_delta2ns(-1, &clockevent_tick_timer); + clockevent_tick_timer.min_delta_ns = + clockevent_delta2ns(1, &clockevent_tick_timer); + + clockevent_tick_timer.cpumask = cpumask_of(0); + clockevents_register_device(&clockevent_tick_timer); + + printk(KERN_INFO "mult[%lu]\n", + (long unsigned int)clockevent_tick_timer.mult); + printk(KERN_INFO "max_delta_ns[%lu]\n", + (long unsigned int)clockevent_tick_timer.max_delta_ns); + printk(KERN_INFO "min_delta_ns[%lu]\n", + (long unsigned int)clockevent_tick_timer.min_delta_ns); + printk(KERN_INFO "rate[%lu]\n", + (long unsigned int)rate); + printk(KERN_INFO "HZ[%d]\n", HZ); +} + +/* + * --------------------------------------------------------------------------- + * SYSTEM TIMER ... free running 32-bit clock source and scheduler clock + * --------------------------------------------------------------------------- + */ +irqreturn_t s5p_sched_timer_interrupt(int irq, void *dev_id) +{ + unsigned int temp_cstat; + + temp_cstat = s5p_systimer_read(S5P_SYSTIMER_INT_CSTAT); + temp_cstat |= S5P_SYSTIMER_INT_INTCNT; + + s5p_systimer_write(S5P_SYSTIMER_INT_CSTAT, temp_cstat); + + if (unlikely(pending_irq)) + pending_irq = 0; + else + s5p_sched_timer_overflows++; + + return IRQ_HANDLED; +} + +struct irqaction s5p_systimer_irq = { + .name = "System timer", + .flags = IRQF_DISABLED , + .handler = s5p_sched_timer_interrupt, +}; + + +static cycle_t s5p_sched_timer_read(struct clocksource *cs) +{ + + return (cycle_t)~__raw_readl(S5P_SYSTIMER_TICNTO); +} + +struct clocksource clocksource_s5p = { + .name = "clock_source_systimer", + .rating = 300, + .read = s5p_sched_timer_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void s5p_init_clocksource(unsigned long rate) +{ + static char err[] __initdata = KERN_ERR + "%s: can't register clocksource!\n"; + + clocksource_s5p.mult + = clocksource_khz2mult(rate/1000, clocksource_s5p.shift); + + s5p_sched_timer_start(~0, 1); + + if (clocksource_register(&clocksource_s5p)) + printk(err, clocksource_s5p.name); +} + +/* + * Returns current time from boot in nsecs. It's OK for this to wrap + * around for now, as it's just a relative time stamp. + */ +unsigned long long sched_clock(void) +{ + unsigned long irq_flags; + cycle_t ticks, elapsed_ticks = 0; + unsigned long long increment = 0; + unsigned int overflow_cnt = 0; + + local_irq_save(irq_flags); + + if (likely(sched_timer_running)) { + overflow_cnt = (s5p_sched_timer_overflows - old_overflows); + ticks = s5p_sched_timer_read(&clocksource_s5p); + + if (overflow_cnt) { + increment = (overflow_cnt - 1) * + (clocksource_cyc2ns(clocksource_s5p.read(&clocksource_s5p), + clocksource_s5p.mult, clocksource_s5p.shift)); + elapsed_ticks = + (clocksource_s5p.mask - last_ticks) + ticks; + } else { + if (unlikely(last_ticks > ticks)) { + pending_irq = 1; + elapsed_ticks = + (clocksource_s5p.mask - last_ticks) + ticks; + s5p_sched_timer_overflows++; + } else { + elapsed_ticks = (ticks - last_ticks); + } + } + + time_stamp += (clocksource_cyc2ns(elapsed_ticks, + clocksource_s5p.mult, + clocksource_s5p.shift) + increment); + + old_overflows = s5p_sched_timer_overflows; + last_ticks = ticks; + } + local_irq_restore(irq_flags); + + return time_stamp; +} + +/* + * Event/Sched Timer initialization + */ +static void s5p_timer_setup(void) +{ + unsigned long rate; + unsigned int tmp; + + /* Setup event timer using XrtcXTI */ + if (clk_event == NULL) + clk_event = clk_get(NULL, "xrtcxti"); + + if (IS_ERR(clk_event)) + panic("failed to get clock for event timer"); + + rate = clk_get_rate(clk_event); + + tmp = readl(rtc_base + S3C2410_RTCCON) & + ~(S3C_RTCCON_TICEN); + + /* We only support 32768 Hz : [7:4] = 0x0 */ + writel(tmp & ~0xf0, rtc_base + S3C2410_RTCCON); + + s5p_init_dynamic_tick_timer(rate); + + /* Setup sched-timer using XusbXTI */ + if (clk_sched == NULL) + clk_sched = clk_get(NULL, "xusbxti"); + if (IS_ERR(clk_sched)) + panic("failed to get clock for sched-timer"); + rate = clk_get_rate(clk_sched); + + s5p_init_clocksource(rate); +} + +static void s5p_tick_timer_setup(void) +{ + unsigned long rate; + + rate = clk_get_rate(clk_event); + s5p_tick_timer_start((rate / HZ) - 1, 1); +} + +static void __init s5p_timer_init(void) +{ + + /* clock configuration setting and enable */ + struct clk *clk_systimer; + struct clk *clk_rtc; + + /* Initialize variables before starting each timers */ + last_ticks = 0; + s5p_sched_timer_overflows = 0; + old_overflows = 0; + time_stamp = 0; + sched_timer_running = 0; + pending_irq = 0; + + /* Setup system timer */ + clk_systimer = clk_get(NULL, "systimer"); + if (IS_ERR(clk_systimer)) + panic("failed to get clock[%s] for system timer", "systimer"); + + clk_enable(clk_systimer); + clk_put(clk_systimer); + + /* Setup rtc timer */ + clk_rtc = clk_get(NULL, "rtc"); + if (IS_ERR(clk_rtc)) + panic("failed to get clock[%s] for system timer", "rtc"); + + clk_enable(clk_rtc); + clk_put(clk_rtc); + + s5p_timer_setup(); + setup_irq(IRQ_RTC_TIC, &s5p_tick_timer_irq); +#if defined(USE_SYSTIMER_IRQ) + setup_irq(IRQ_SYSTIMER, &s5p_systimer_irq); +#endif +} + +struct sys_timer s5p_systimer = { + .init = s5p_timer_init, +}; + diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h new file mode 100644 index 0000000..23a9b527b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/csis.h @@ -0,0 +1,29 @@ +/* linux/arch/arm/plat-s5p/include/plat/csis.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Platform header file for MIPI-CSI2 driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_PLAT_CSIS_H +#define __ASM_PLAT_CSIS_H __FILE__ + +struct platform_device; + +struct s3c_platform_csis { + const char srclk_name[16]; + const char clk_name[16]; + unsigned long clk_rate; + + void (*cfg_gpio)(void); + void (*cfg_phy_global)(int on); +}; + +extern void s3c_csis_set_platdata(struct s3c_platform_csis *csis); + +#endif /* __ASM_PLAT_CSIS_H */ diff --git a/arch/arm/plat-s5p/include/plat/fb.h b/arch/arm/plat-s5p/include/plat/fb.h new file mode 100644 index 0000000..de4725b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/fb.h @@ -0,0 +1,127 @@ +/* linux/arch/arm/plat-s3c/include/plat/fb.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - FB platform data definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C_FB_H +#define __PLAT_S3C_FB_H __FILE__ + +#ifdef CONFIG_FB_S3C + +#define FB_SWAP_WORD (1 << 24) +#define FB_SWAP_HWORD (1 << 16) +#define FB_SWAP_BYTE (1 << 8) +#define FB_SWAP_BIT (1 << 0) + +struct platform_device; +struct clk; + +struct s3c_platform_fb { + int hw_ver; + char clk_name[16]; + int nr_wins; + int nr_buffers[5]; + int default_win; + int swap; + phys_addr_t pmem_start[5]; /* starting physical address of memory region */ + size_t pmem_size[5]; /* size of memory region */ + void *lcd; + void (*cfg_gpio)(struct platform_device *dev); + int (*backlight_on)(struct platform_device *dev); + int (*backlight_onoff)(struct platform_device *dev, int onoff); + int (*reset_lcd)(struct platform_device *dev); + int (*clk_on)(struct platform_device *pdev, struct clk **s3cfb_clk); + int (*clk_off)(struct platform_device *pdev, struct clk **clk); +}; + +extern void s3cfb_set_platdata(struct s3c_platform_fb *fimd); + +/* defined by architecture to configure gpio */ +extern void s3cfb_cfg_gpio(struct platform_device *pdev); +extern int s3cfb_backlight_on(struct platform_device *pdev); +extern int s3cfb_backlight_onoff(struct platform_device *pdev, int onoff); +extern int s3cfb_reset_lcd(struct platform_device *pdev); +extern int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk); +extern int s3cfb_clk_off(struct platform_device *pdev, struct clk **clk); +extern void s3cfb_get_clk_name(char *clk_name); + +#else + +#ifdef CONFIG_S3C_FB + +/** + * struct s3c_fb_pd_win - per window setup data + * @win_mode: The display parameters to initialise (not for window 0) + * @virtual_x: The virtual X size. + * @virtual_y: The virtual Y size. + */ +struct s3c_fb_pd_win { + struct fb_videomode win_mode; + + unsigned short default_bpp; + unsigned short max_bpp; + unsigned short virtual_x; + unsigned short virtual_y; +}; + +/** + * struct s3c_fb_platdata - S3C driver platform specific information + * @setup_gpio: Setup the external GPIO pins to the right state to transfer + * the data from the display system to the connected display + * device. + * @vidcon0: The base vidcon0 values to control the panel data format. + * @vidcon1: The base vidcon1 values to control the panel data output. + * @win: The setup data for each hardware window, or NULL for unused. + * @display_mode: The LCD output display mode. + * + * The platform data supplies the video driver with all the information + * it requires to work with the display(s) attached to the machine. It + * controls the initial mode, the number of display windows (0 is always + * the base framebuffer) that are initialised etc. + * + */ +struct s3c_fb_platdata { + void (*setup_gpio)(void); + + struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN]; + + u32 vidcon0; + u32 vidcon1; +}; + +/** + * s3c_fb_set_platdata() - Setup the FB device with platform data. + * @pd: The platform data to set. The data is copied from the passed structure + * so the machine data can mark the data __initdata so that any unused + * machines will end up dumping their data at runtime. + */ +extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); + +/** + * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s3c64xx_fb_gpio_setup_24bpp(void); + +/** + * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s5pc100_fb_gpio_setup_24bpp(void); + +#endif /* CONFIG_FB */ + +#endif + +#endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-s5p/include/plat/fimc.h b/arch/arm/plat-s5p/include/plat/fimc.h new file mode 100644 index 0000000..5685ed1 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/fimc.h @@ -0,0 +1,129 @@ +/* linux/arch/arm/plat-s5p/include/plat/fimc.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Platform header file for Samsung Camera Interface (FIMC) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef __ASM_PLAT_FIMC_H +#define __ASM_PLAT_FIMC_H __FILE__ + +#include <linux/videodev2.h> + +#define FIMC_SRC_MAX_W 1920 +#define FIMC_SRC_MAX_H 1280 + +struct platform_device; + +/* For exnternal camera device */ +enum fimc_cam_type { + CAM_TYPE_ITU = 0, + CAM_TYPE_MIPI = 1, +}; + +enum fimc_cam_format { + ITU_601_YCBCR422_8BIT = (1 << 31), + ITU_656_YCBCR422_8BIT = (0 << 31), + ITU_601_YCBCR422_16BIT = (1 << 29), + MIPI_CSI_YCBCR422_8BIT = 0x1e, + MIPI_CSI_RAW8 = 0x2a, + MIPI_CSI_RAW10 = 0x2b, + MIPI_CSI_RAW12 = 0x2c, + MIPI_USER_DEF_PACKET_1 = 0x30, /* User defined Byte-based packet 1 */ +}; + +enum fimc_cam_order422 { + CAM_ORDER422_8BIT_YCBYCR = (0 << 14), + CAM_ORDER422_8BIT_YCRYCB = (1 << 14), + CAM_ORDER422_8BIT_CBYCRY = (2 << 14), + CAM_ORDER422_8BIT_CRYCBY = (3 << 14), + CAM_ORDER422_16BIT_Y4CBCRCBCR = (0 << 14), + CAM_ORDER422_16BIT_Y4CRCBCRCB = (1 << 14), +}; + +enum fimc_cam_index { + CAMERA_PAR_A = 0, + CAMERA_PAR_B = 1, + CAMERA_CSI_C = 2, + CAMERA_PATTERN = 3, /* Not actual camera but test pattern */ + CAMERA_WB = 4, /* Not actual camera but write back */ +}; + +/* struct s3c_platform_camera: abstraction for input camera */ +struct s3c_platform_camera { + /* + * ITU cam A,B: 0,1 + * CSI-2 cam C: 2 + */ + enum fimc_cam_index id; + + enum fimc_cam_type type; /* ITU or MIPI */ + enum fimc_cam_format fmt; /* input format */ + enum fimc_cam_order422 order422; /* YCBCR422 order for ITU */ + u32 pixelformat; /* default fourcc */ + + int i2c_busnum; + struct i2c_board_info *info; + struct v4l2_subdev *sd; + + const char srclk_name[16]; /* source of mclk name */ + const char clk_name[16]; /* mclk name */ + u32 clk_rate; /* mclk ratio */ + struct clk *srclk; /* parent for mclk */ + struct clk *clk; /* mclk */ + int line_length; /* max length */ + int width; /* default resol */ + int height; /* default resol */ + struct v4l2_rect window; /* real cut region from source */ + + int mipi_lanes; /* MIPI data lanes */ + int mipi_settle; /* MIPI settle */ + int mipi_align; /* MIPI data align: 24/32 */ + + /* Polarity: 1 if inverted polarity used */ + int inv_pclk; + int inv_vsync; + int inv_href; + int inv_hsync; + + int initialized; + + /* Board specific power pin control */ + int (*cam_power)(int onoff); +}; + +/* For camera interface driver */ +struct s3c_platform_fimc { + const char srclk_name[16]; /* source of interface clock name */ + const char clk_name[16]; /* interface clock name */ + const char lclk_name[16]; /* interface clock name */ + u32 clk_rate; /* clockrate for interface clock */ + enum fimc_cam_index default_cam; /* index of default cam */ + struct s3c_platform_camera *camera[5]; /* FIXME */ + int hw_ver; + phys_addr_t pmem_start; /* starting physical address of memory region */ + size_t pmem_size; /* size of memory region */ + + void (*cfg_gpio)(struct platform_device *pdev); + int (*clk_on)(struct platform_device *pdev, struct clk *clk); + int (*clk_off)(struct platform_device *pdev, struct clk *clk); +}; + +extern void s3c_fimc0_set_platdata(struct s3c_platform_fimc *fimc); +extern void s3c_fimc1_set_platdata(struct s3c_platform_fimc *fimc); +extern void s3c_fimc2_set_platdata(struct s3c_platform_fimc *fimc); + +/* defined by architecture to configure gpio */ +extern void s3c_fimc0_cfg_gpio(struct platform_device *pdev); +extern void s3c_fimc1_cfg_gpio(struct platform_device *pdev); +extern void s3c_fimc2_cfg_gpio(struct platform_device *pdev); + +/* platform specific clock functions */ +extern int s3c_fimc_clk_on(struct platform_device *pdev, struct clk *clk); +extern int s3c_fimc_clk_off(struct platform_device *pdev, struct clk *clk); + +#endif /*__ASM_PLAT_FIMC_H */ diff --git a/arch/arm/plat-s5p/include/plat/irq-eint-group.h b/arch/arm/plat-s5p/include/plat/irq-eint-group.h new file mode 100644 index 0000000..430985b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irq-eint-group.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/plat-s5p/include/plat/irq-eint-group.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P Common IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S5P_IRQ_EINT_GROUP_H +#define __PLAT_S5P_IRQ_EINT_GROUP_H +void s5pv210_restore_eint_group(void); +#endif /* __PLAT_S5P_IRQ_EINT_GROUP_H */ diff --git a/arch/arm/plat-s5p/include/plat/irq-pm.h b/arch/arm/plat-s5p/include/plat/irq-pm.h new file mode 100644 index 0000000..a104998 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irq-pm.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/plat-s5p/include/plat/irq-pm.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P Common IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S5P_IRQ_PM_H +#define __PLAT_S5P_IRQ_PM_H +int s3c_irq_wake(struct irq_data *data, unsigned int state); +#endif /* __PLAT_S5P_IRQ_PM_H */ diff --git a/arch/arm/plat-s5p/include/plat/jpeg.h b/arch/arm/plat-s5p/include/plat/jpeg.h new file mode 100755 index 0000000..cf52000 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/jpeg.h @@ -0,0 +1,27 @@ +/* linux/arch/arm/plat-s5p/include/plat/jpeg.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Platform header file for JPEG device driver driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef __ASM_PLAT_JPEG_H +#define __ASM_PLAT_JPEG_H __FILE__ + +struct platform_device; + +/* For camera interface driver */ +struct s3c_platform_jpeg { + unsigned int max_main_width; + unsigned int max_main_height; + unsigned int max_thumb_width; + unsigned int max_thumb_height; +}; + +extern void s3c_jpeg_set_platdata(struct s3c_platform_jpeg *jpeg); + +#endif /*__ASM_PLAT_FIMC_H */ diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index d973d39..56b0432 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -25,6 +25,7 @@ #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) #define S5P_VA_SROMC S3C_ADDR(0x024C0000) +#define S5P_VA_AUDSS S3C_ADDR(0X01600000) #define S5P_VA_SYSTIMER S3C_ADDR(0x02500000) #define S5P_VA_L2CC S3C_ADDR(0x02600000) diff --git a/arch/arm/plat-s5p/include/plat/media.h b/arch/arm/plat-s5p/include/plat/media.h new file mode 100644 index 0000000..79761da --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/media.h @@ -0,0 +1,34 @@ +/* linux/arch/arm/plat-s5p/include/plat/media.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung Media device descriptions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _S5P_MEDIA_H +#define _S5P_MEDIA_H + +#include <linux/types.h> +#include <asm/setup.h> + +struct s5p_media_device { + u32 id; + const char *name; + u32 bank; + size_t memsize; + dma_addr_t paddr; +}; + +extern struct meminfo meminfo; +extern dma_addr_t s5p_get_media_memory_bank(int dev_id, int bank); +extern size_t s5p_get_media_memsize_bank(int dev_id, int bank); +extern dma_addr_t s5p_get_media_membase_bank(int bank); +extern void s5p_reserve_bootmem(struct s5p_media_device *mdevs, int nr_mdevs, size_t boundary); + +#endif + diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h new file mode 100644 index 0000000..bba97a9 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/mfc.h @@ -0,0 +1,24 @@ +/* arch/arm/plat-s5p/include/plat/mfc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Platform header file for MFC driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _S3C_MFC_H +#define _S3C_MFC_H + +#include <linux/types.h> + +struct s3c_platform_mfc { + dma_addr_t buf_phy_base[2]; + size_t buf_phy_size[2]; +}; + +extern void s3c_mfc_set_platdata(struct s3c_platform_mfc *pd); +#endif diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index bf28fad..9c2332f 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -94,10 +94,12 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, return result; } +#define PLL90XX_VDIV_MASK (0x1) #define PLL90XX_MDIV_MASK (0xFF) #define PLL90XX_PDIV_MASK (0x3F) #define PLL90XX_SDIV_MASK (0x7) #define PLL90XX_KDIV_MASK (0xffff) +#define PLL90XX_VDIV_SHIFT (27) #define PLL90XX_MDIV_SHIFT (16) #define PLL90XX_PDIV_SHIFT (8) #define PLL90XX_SDIV_SHIFT (0) diff --git a/arch/arm/plat-s5p/include/plat/regs-csis.h b/arch/arm/plat-s5p/include/plat/regs-csis.h new file mode 100644 index 0000000..aaab7bc --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-csis.h @@ -0,0 +1,105 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-csis.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Register definition file for MIPI-CSI2 Driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_CSIS_H +#define _REGS_CSIS_H + +#define S3C_CSISREG(x) (x) + +/************************************************************************* + * Registers + ************************************************************************/ +#define S3C_CSIS_CONTROL S3C_CSISREG(0x00) +#define S3C_CSIS_DPHYCTRL S3C_CSISREG(0x04) +#define S3C_CSIS_CONFIG S3C_CSISREG(0x08) +#define S3C_CSIS_DPHYSTS S3C_CSISREG(0x0c) +#define S3C_CSIS_INTMSK S3C_CSISREG(0x10) +#define S3C_CSIS_INTSRC S3C_CSISREG(0x14) +#define S3C_CSIS_RESOL S3C_CSISREG(0x2c) + +/************************************************************************* + * Bit Definitions + ************************************************************************/ +/* Control Register */ +#define S3C_CSIS_CONTROL_DPDN_DEFAULT (0 << 31) +#define S3C_CSIS_CONTROL_DPDN_SWAP (1 << 31) +#define S3C_CSIS_CONTROL_ALIGN_32BIT (1 << 20) +#define S3C_CSIS_CONTROL_ALIGN_24BIT (0 << 20) +#define S3C_CSIS_CONTROL_ALIGN_MASK (1 << 20) +#define S3C_CSIS_CONTROL_UPDATE_SHADOW (1 << 16) +#define S3C_CSIS_CONTROL_WCLK_PCLK (0 << 8) +#define S3C_CSIS_CONTROL_WCLK_EXTCLK (1 << 8) +#define S3C_CSIS_CONTROL_WCLK_MASK (1 << 8) +#define S3C_CSIS_CONTROL_RESET (1 << 4) +#define S3C_CSIS_CONTROL_DISABLE (0 << 0) +#define S3C_CSIS_CONTROL_ENABLE (1 << 0) + +/* D-PHY Control Register */ +#define S3C_CSIS_DPHYCTRL_HS_SETTLE_MASK (0x1f << 27) +#define S3C_CSIS_DPHYCTRL_HS_SETTLE_SHIFT (27) +#define S3C_CSIS_DPHYCTRL_DISABLE (0xf << 0) +#define S3C_CSIS_DPHYCTRL_ENABLE (0xf << 0) + +/* Configuration Register */ +#define S3C_CSIS_CONFIG_FORMAT_SHIFT (2) +#define S3C_CSIS_CONFIG_FORMAT_MASK (0x1f << 2) +#define S3C_CSIS_CONFIG_NR_LANE_1 (0 << 0) +#define S3C_CSIS_CONFIG_NR_LANE_2 (1 << 0) +#define S3C_CSIS_CONFIG_NR_LANE_MASK (1 << 0) + +/* D-PHY Status Register */ +#define S3C_CSIS_DPHYSTS_STOPSTATE_LANE1 (1 << 5) +#define S3C_CSIS_DPHYSTS_STOPSTATE_LANE0 (1 << 4) +#define S3C_CSIS_DPHYSTS_STOPSTATE_CLOCK (1 << 0) + +/* Interrupt Mask Register */ +#define S3C_CSIS_INTMSK_EVEN_BEFORE_DISABLE (0 << 31) +#define S3C_CSIS_INTMSK_EVEN_BEFORE_ENABLE (1 << 31) +#define S3C_CSIS_INTMSK_EVEN_AFTER_DISABLE (0 << 30) +#define S3C_CSIS_INTMSK_EVEN_AFTER_ENABLE (1 << 30) +#define S3C_CSIS_INTMSK_ODD_BEFORE_DISABLE (0 << 29) +#define S3C_CSIS_INTMSK_ODD_BEFORE_ENABLE (1 << 29) +#define S3C_CSIS_INTMSK_ODD_AFTER_DISABLE (0 << 28) +#define S3C_CSIS_INTMSK_ODD_AFTER_ENABLE (1 << 28) +#define S3C_CSIS_INTMSK_ERR_SOT_HS_DISABLE (0 << 12) +#define S3C_CSIS_INTMSK_ERR_SOT_HS_ENABLE (1 << 12) +#define S3C_CSIS_INTMSK_ERR_ESC_DISABLE (0 << 8) +#define S3C_CSIS_INTMSK_ERR_ESC_ENABLE (1 << 8) +#define S3C_CSIS_INTMSK_ERR_CTRL_DISABLE (0 << 4) +#define S3C_CSIS_INTMSK_ERR_CTRL_ENABLE (1 << 4) +#define S3C_CSIS_INTMSK_ERR_ECC_DISABLE (0 << 2) +#define S3C_CSIS_INTMSK_ERR_ECC_ENABLE (1 << 2) +#define S3C_CSIS_INTMSK_ERR_CRC_DISABLE (0 << 1) +#define S3C_CSIS_INTMSK_ERR_CRC_ENABLE (1 << 1) +#define S3C_CSIS_INTMSK_ERR_ID_DISABLE (0 << 0) +#define S3C_CSIS_INTMSK_ERR_ID_ENABLE (1 << 0) + +/* Interrupt Source Register */ +#define S3C_CSIS_INTSRC_EVEN_BEFORE (1 << 31) +#define S3C_CSIS_INTSRC_EVEN_AFTER (1 << 30) +#define S3C_CSIS_INTSRC_ODD_BEFORE (1 << 29) +#define S3C_CSIS_INTSRC_ODD_AFTER (1 << 28) +#define S3C_CSIS_INTSRC_ERR_SOT_HS_LANE1 (1 << 13) +#define S3C_CSIS_INTSRC_ERR_SOT_HS_LANE0 (1 << 12) +#define S3C_CSIS_INTSRC_ERR_ESC_LANE1 (1 << 9) +#define S3C_CSIS_INTSRC_ERR_ESC_LANE0 (1 << 8) +#define S3C_CSIS_INTSRC_ERR_CTRL1 (1 << 5) +#define S3C_CSIS_INTSRC_ERR_CTRL0 (1 << 4) +#define S3C_CSIS_INTSRC_ERR_ECC (1 << 2) +#define S3C_CSIS_INTSRC_ERR_CRC (1 << 1) +#define S3C_CSIS_INTSRC_ERR_ID (1 << 0) + +/* Resolution Register */ +#define S3C_CSIS_RESOL_HOR_SHIFT (16) +#define S3C_CSIS_RESOL_VER_SHIFT (0) + +#endif /* _REGS_CSIS_H */ diff --git a/arch/arm/plat-s5p/include/plat/regs-fb.h b/arch/arm/plat-s5p/include/plat/regs-fb.h new file mode 100644 index 0000000..9945ebf --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-fb.h @@ -0,0 +1,396 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-fb.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Register definition file for Samsung Display Controller (FIMD) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_FB_H +#define _REGS_FB_H + +#define S3C_LCDREG(x) (x) +#define S3C_WINCON(x) S3C_LCDREG(0x0020 + (x * 0x04)) +#define S3C_VIDOSD_A(x) S3C_LCDREG(0x0040 + (x * 0x10)) +#define S3C_VIDOSD_B(x) S3C_LCDREG(0x0044 + (x * 0x10)) +#define S3C_VIDOSD_C(x) S3C_LCDREG(0x0048 + (x * 0x10)) +#define S3C_VIDOSD_D(x) S3C_LCDREG(0x004C + (x * 0x10)) +#define S3C_VIDADDR_START0(x) S3C_LCDREG(0x00A0 + (x * 0x08)) +#define S3C_VIDADDR_START1(x) S3C_LCDREG(0x00A4 + (x * 0x08)) +#define S3C_VIDADDR_END0(x) S3C_LCDREG(0x00D0 + (x * 0x08)) +#define S3C_VIDADDR_END1(x) S3C_LCDREG(0x00D4 + (x * 0x08)) +#define S3C_VIDADDR_SIZE(x) S3C_LCDREG(0x0100 + (x * 0x04)) +#define S3C_KEYCON(x) S3C_LCDREG(0x0140 + ((x - 1) * 0x08)) +#define S3C_KEYVAL(x) S3C_LCDREG(0x0144 + ((x - 1) * 0x08)) +#define S3C_WINMAP(x) S3C_LCDREG(0x0180 + (x * 0x04)) + +/* + * Register Map +*/ +#define S3C_VIDCON0 S3C_LCDREG(0x0000) /* Video control 0 */ +#define S3C_VIDCON1 S3C_LCDREG(0x0004) /* Video control 1 */ +#define S3C_VIDCON2 S3C_LCDREG(0x0008) /* Video control 2 */ +#define S3C_PRTCON S3C_LCDREG(0x000C) /* Protect control */ + +#define S3C_VIDTCON0 S3C_LCDREG(0x0010) /* Video time control 0 */ +#define S3C_VIDTCON1 S3C_LCDREG(0x0014) /* Video time control 1 */ +#define S3C_VIDTCON2 S3C_LCDREG(0x0018) /* Video time control 2 */ + +#define S3C_WINCON0 S3C_LCDREG(0x0020) /* Window control 0 */ +#define S3C_WINCON1 S3C_LCDREG(0x0024) /* Window control 1 */ +#define S3C_WINCON2 S3C_LCDREG(0x0028) /* Window control 2 */ +#define S3C_WINCON3 S3C_LCDREG(0x002C) /* Window control 3 */ +#define S3C_WINCON4 S3C_LCDREG(0x0030) /* Window control 4 */ + +#define S3C_WINSHMAP S3C_LCDREG(0x0034) /* Window Shadow control */ + +#define S3C_VIDOSD0A S3C_LCDREG(0x0040) /* Video Window 0 position control */ +#define S3C_VIDOSD0B S3C_LCDREG(0x0044) /* Video Window 0 position control1 */ +#define S3C_VIDOSD0C S3C_LCDREG(0x0048) /* Video Window 0 position control */ + +#define S3C_VIDOSD1A S3C_LCDREG(0x0050) /* Video Window 1 position control */ +#define S3C_VIDOSD1B S3C_LCDREG(0x0054) /* Video Window 1 position control */ +#define S3C_VIDOSD1C S3C_LCDREG(0x0058) /* Video Window 1 position control */ +#define S3C_VIDOSD1D S3C_LCDREG(0x005C) /* Video Window 1 position control */ + +#define S3C_VIDOSD2A S3C_LCDREG(0x0060) /* Video Window 2 position control */ +#define S3C_VIDOSD2B S3C_LCDREG(0x0064) /* Video Window 2 position control */ +#define S3C_VIDOSD2C S3C_LCDREG(0x0068) /* Video Window 2 position control */ +#define S3C_VIDOSD2D S3C_LCDREG(0x006C) /* Video Window 2 position control */ + +#define S3C_VIDOSD3A S3C_LCDREG(0x0070) /* Video Window 3 position control */ +#define S3C_VIDOSD3B S3C_LCDREG(0x0074) /* Video Window 3 position control */ +#define S3C_VIDOSD3C S3C_LCDREG(0x0078) /* Video Window 3 position control */ + +#define S3C_VIDOSD4A S3C_LCDREG(0x0080) /* Video Window 4 position control */ +#define S3C_VIDOSD4B S3C_LCDREG(0x0084) /* Video Window 4 position control */ +#define S3C_VIDOSD4C S3C_LCDREG(0x0088) /* Video Window 4 position control */ + +#define S3C_VIDW00ADD0B0 S3C_LCDREG(0x00A0) /* Window 0 buffer start address, buffer 0 */ +#define S3C_VIDW00ADD0B1 S3C_LCDREG(0x00A4) /* Window 0 buffer start address, buffer 1 */ +#define S3C_VIDW01ADD0B0 S3C_LCDREG(0x00A8) /* Window 1 buffer start address, buffer 0 */ +#define S3C_VIDW01ADD0B1 S3C_LCDREG(0x00AC) /* Window 1 buffer start address, buffer 1 */ +#define S3C_VIDW02ADD0 S3C_LCDREG(0x00B0) /* Window 2 buffer start address, buffer 0 */ +#define S3C_VIDW03ADD0 S3C_LCDREG(0x00B8) /* Window 3 buffer start address, buffer 0 */ +#define S3C_VIDW04ADD0 S3C_LCDREG(0x00C0) /* Window 4 buffer start address, buffer 0 */ +#define S3C_VIDW00ADD1B0 S3C_LCDREG(0x00D0) /* Window 0 buffer end address, buffer 0 */ +#define S3C_VIDW00ADD1B1 S3C_LCDREG(0x00D4) /* Window 0 buffer end address, buffer 1 */ +#define S3C_VIDW01ADD1B0 S3C_LCDREG(0x00D8) /* Window 1 buffer end address, buffer 0 */ +#define S3C_VIDW01ADD1B1 S3C_LCDREG(0x00DC) /* Window 1 buffer end address, buffer 1 */ +#define S3C_VIDW02ADD1 S3C_LCDREG(0x00E0) /* Window 2 buffer end address */ +#define S3C_VIDW03ADD1 S3C_LCDREG(0x00E8) /* Window 3 buffer end address */ +#define S3C_VIDW04ADD1 S3C_LCDREG(0x00F0) /* Window 4 buffer end address */ +#define S3C_VIDW00ADD2 S3C_LCDREG(0x0100) /* Window 0 buffer size */ +#define S3C_VIDW01ADD2 S3C_LCDREG(0x0104) /* Window 1 buffer size */ +#define S3C_VIDW02ADD2 S3C_LCDREG(0x0108) /* Window 2 buffer size */ +#define S3C_VIDW03ADD2 S3C_LCDREG(0x010C) /* Window 3 buffer size */ +#define S3C_VIDW04ADD2 S3C_LCDREG(0x0110) /* Window 4 buffer size */ + +#define S3C_VP1TCON0 S3C_LCDREG(0x0118) /* VP1 interface timing control 0 */ +#define S3C_VP1TCON1 S3C_LCDREG(0x011C) /* VP1 interface timing control 1 */ + +#define S3C_VIDINTCON0 S3C_LCDREG(0x0130) /* Indicate the Video interrupt control */ +#define S3C_VIDINTCON1 S3C_LCDREG(0x0134) /* Video Interrupt Pending */ + +#define S3C_W1KEYCON0 S3C_LCDREG(0x0140) /* Color key control */ +#define S3C_W1KEYCON1 S3C_LCDREG(0x0144) /* Color key value (transparent value) */ +#define S3C_W2KEYCON0 S3C_LCDREG(0x0148) /* Color key control */ +#define S3C_W2KEYCON1 S3C_LCDREG(0x014C) /* Color key value (transparent value) */ +#define S3C_W3KEYCON0 S3C_LCDREG(0x0150) /* Color key control */ +#define S3C_W3KEYCON1 S3C_LCDREG(0x0154) /* Color key value (transparent value) */ +#define S3C_W4KEYCON0 S3C_LCDREG(0x0158) /* Color key control */ +#define S3C_W4KEYCON1 S3C_LCDREG(0x015C) /* Color key value (transparent value) */ + +#define S3C_W1KEYALPHA S3C_LCDREG(0x0160) /* Color key alpha value */ +#define S3C_W2KEYALPHA S3C_LCDREG(0x0164) /* Color key alpha value */ +#define S3C_W3KEYALPHA S3C_LCDREG(0x0168) /* Color key alpha value */ +#define S3C_W4KEYALPHA S3C_LCDREG(0x016C) /* Color key alpha value */ + +#define S3C_DITHMODE S3C_LCDREG(0x0170) /* Dithering mode */ + +#define S3C_WIN0MAP S3C_LCDREG(0x0180) /* Window color control */ +#define S3C_WIN1MAP S3C_LCDREG(0x0184) /* Window color control */ +#define S3C_WIN2MAP S3C_LCDREG(0x0188) /* Window color control */ +#define S3C_WIN3MAP S3C_LCDREG(0x018C) /* Window color control */ +#define S3C_WIN4MAP S3C_LCDREG(0x0190) /* Window color control */ + +#define S3C_WPALCON_H S3C_LCDREG(0x019C) /* Window Palette control */ +#define S3C_WPALCON_L S3C_LCDREG(0x01A0) /* Window Palette control */ + +#define S3C_VIDW0ALPHA0 S3C_LCDREG(0x0200) /* Window 0 alpha value 0 */ +#define S3C_VIDW0ALPHA1 S3C_LCDREG(0x0204) /* Window 0 alpha value 1 */ +#define S3C_VIDW1ALPHA0 S3C_LCDREG(0x0208) /* Window 1 alpha value 0 */ +#define S3C_VIDW1ALPHA1 S3C_LCDREG(0x020C) /* Window 1 alpha value 1 */ +#define S3C_VIDW2ALPHA0 S3C_LCDREG(0x0210) /* Window 2 alpha value 0 */ +#define S3C_VIDW2ALPHA1 S3C_LCDREG(0x0214) /* Window 2 alpha value 1 */ +#define S3C_VIDW3ALPHA0 S3C_LCDREG(0x0218) /* Window 3 alpha value 0 */ +#define S3C_VIDW3ALPHA1 S3C_LCDREG(0x021C) /* Window 3 alpha value 1 */ +#define S3C_VIDW4ALPHA0 S3C_LCDREG(0x0220) /* Window 4 alpha value 0 */ +#define S3C_VIDW4ALPHA1 S3C_LCDREG(0x0224) /* Window 4 alpha value 1 */ + +#define S3C_BLENDEQ1 S3C_LCDREG(0x0244) /* Window 1 blending equation control */ +#define S3C_BLENDEQ2 S3C_LCDREG(0x0248) /* Window 2 blending equation control */ +#define S3C_BLENDEQ3 S3C_LCDREG(0x024C) /* Window 3 blending equation control */ +#define S3C_BLENDEQ4 S3C_LCDREG(0x0250) /* Window 4 blending equation control */ +#define S3C_BLENDCON S3C_LCDREG(0x0260) /* Blending control */ + +/* + * Bit Definitions +*/ + +/* VIDCON0 */ +#define S3C_VIDCON0_DSI_DISABLE (0 << 30) +#define S3C_VIDCON0_DSI_ENABLE (1 << 30) +#define S3C_VIDCON0_SCAN_PROGRESSIVE (0 << 29) +#define S3C_VIDCON0_SCAN_INTERLACE (1 << 29) +#define S3C_VIDCON0_SCAN_MASK (1 << 29) +#define S3C_VIDCON0_VIDOUT_RGB (0 << 26) +#define S3C_VIDCON0_VIDOUT_ITU (1 << 26) +#define S3C_VIDCON0_VIDOUT_I80LDI0 (2 << 26) +#define S3C_VIDCON0_VIDOUT_I80LDI1 (3 << 26) +#define S3C_VIDCON0_VIDOUT_WB_RGB (4 << 26) +#define S3C_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26) +#define S3C_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26) +#define S3C_VIDCON0_VIDOUT_MASK (7 << 26) +#define S3C_VIDCON0_PNRMODE_RGB_P (0 << 17) +#define S3C_VIDCON0_PNRMODE_BGR_P (1 << 17) +#define S3C_VIDCON0_PNRMODE_RGB_S (2 << 17) +#define S3C_VIDCON0_PNRMODE_BGR_S (3 << 17) +#define S3C_VIDCON0_PNRMODE_MASK (3 << 17) +#define S3C_VIDCON0_PNRMODE_SHIFT (17) +#define S3C_VIDCON0_CLKVALUP_ALWAYS (0 << 16) +#define S3C_VIDCON0_CLKVALUP_START_FRAME (1 << 16) +#define S3C_VIDCON0_CLKVALUP_MASK (1 << 16) +#define S3C_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) +#define S3C_VIDCON0_VCLKEN_NORMAL (0 << 5) +#define S3C_VIDCON0_VCLKEN_FREERUN (1 << 5) +#define S3C_VIDCON0_VCLKEN_MASK (1 << 5) +#define S3C_VIDCON0_CLKDIR_DIRECTED (0 << 4) +#define S3C_VIDCON0_CLKDIR_DIVIDED (1 << 4) +#define S3C_VIDCON0_CLKDIR_MASK (1 << 4) +#define S3C_VIDCON0_CLKSEL_HCLK (0 << 2) +#define S3C_VIDCON0_CLKSEL_SCLK (1 << 2) +#define S3C_VIDCON0_CLKSEL_MASK (1 << 2) +#define S3C_VIDCON0_ENVID_ENABLE (1 << 1) +#define S3C_VIDCON0_ENVID_DISABLE (0 << 1) +#define S3C_VIDCON0_ENVID_F_ENABLE (1 << 0) +#define S3C_VIDCON0_ENVID_F_DISABLE (0 << 0) + +/* VIDCON1 */ +#define S3C_VIDCON1_IVCLK_FALLING_EDGE (0 << 7) +#define S3C_VIDCON1_IVCLK_RISING_EDGE (1 << 7) +#define S3C_VIDCON1_IHSYNC_NORMAL (0 << 6) +#define S3C_VIDCON1_IHSYNC_INVERT (1 << 6) +#define S3C_VIDCON1_IVSYNC_NORMAL (0 << 5) +#define S3C_VIDCON1_IVSYNC_INVERT (1 << 5) +#define S3C_VIDCON1_IVDEN_NORMAL (0 << 4) +#define S3C_VIDCON1_IVDEN_INVERT (1 << 4) + +/* VIDCON2 */ +#define S3C_VIDCON2_EN601_DISABLE (0 << 23) +#define S3C_VIDCON2_EN601_ENABLE (1 << 23) +#define S3C_VIDCON2_EN601_MASK (1 << 23) +#define S3C_VIDCON2_WB_DISABLE (0 << 15) +#define S3C_VIDCON2_WB_ENABLE (1 << 15) +#define S3C_VIDCON2_WB_MASK (1 << 15) +#define S3C_VIDCON2_TVFORMATSEL_HW (0 << 14) +#define S3C_VIDCON2_TVFORMATSEL_SW (1 << 14) +#define S3C_VIDCON2_TVFORMATSEL_MASK (1 << 14) +#define S3C_VIDCON2_TVFORMATSEL_YUV422 (1 << 12) +#define S3C_VIDCON2_TVFORMATSEL_YUV444 (2 << 12) +#define S3C_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12) +#define S3C_VIDCON2_ORGYUV_YCBCR (0 << 8) +#define S3C_VIDCON2_ORGYUV_CBCRY (1 << 8) +#define S3C_VIDCON2_ORGYUV_MASK (1 << 8) +#define S3C_VIDCON2_YUVORD_CBCR (0 << 7) +#define S3C_VIDCON2_YUVORD_CRCB (1 << 7) +#define S3C_VIDCON2_YUVORD_MASK (1 << 7) + +/* PRTCON */ +#define S3C_PRTCON_UPDATABLE (0 << 11) +#define S3C_PRTCON_PROTECT (1 << 11) + +/* VIDTCON0 */ +#define S3C_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) +#define S3C_VIDTCON0_VBPD(x) (((x) & 0xff) << 16) +#define S3C_VIDTCON0_VFPD(x) (((x) & 0xff) << 8) +#define S3C_VIDTCON0_VSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON1 */ +#define S3C_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24) +#define S3C_VIDTCON1_HBPD(x) (((x) & 0xff) << 16) +#define S3C_VIDTCON1_HFPD(x) (((x) & 0xff) << 8) +#define S3C_VIDTCON1_HSPW(x) (((x) & 0xff) << 0) + +/* VIDTCON2 */ +#define S3C_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) +#define S3C_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) + +/* Window 0~4 Control - WINCONx */ +#define S3C_WINCON_DATAPATH_DMA (0 << 22) +#define S3C_WINCON_DATAPATH_LOCAL (1 << 22) +#define S3C_WINCON_DATAPATH_MASK (1 << 22) +#define S3C_WINCON_BUFSEL_0 (0 << 20) +#define S3C_WINCON_BUFSEL_1 (1 << 20) +#define S3C_WINCON_BUFSEL_MASK (1 << 20) +#define S3C_WINCON_BUFSEL_SHIFT (20) +#define S3C_WINCON_BUFAUTO_DISABLE (0 << 19) +#define S3C_WINCON_BUFAUTO_ENABLE (1 << 19) +#define S3C_WINCON_BUFAUTO_MASK (1 << 19) +#define S3C_WINCON_BITSWP_DISABLE (0 << 18) +#define S3C_WINCON_BITSWP_ENABLE (1 << 18) +#define S3C_WINCON_BITSWP_SHIFT (18) +#define S3C_WINCON_BYTESWP_DISABLE (0 << 17) +#define S3C_WINCON_BYTESWP_ENABLE (1 << 17) +#define S3C_WINCON_BYTESWP_SHIFT (17) +#define S3C_WINCON_HAWSWP_DISABLE (0 << 16) +#define S3C_WINCON_HAWSWP_ENABLE (1 << 16) +#define S3C_WINCON_HAWSWP_SHIFT (16) +#define S3C_WINCON_WSWP_DISABLE (0 << 15) +#define S3C_WINCON_WSWP_ENABLE (1 << 15) +#define S3C_WINCON_WSWP_SHIFT (15) +#define S3C_WINCON_INRGB_RGB (0 << 13) +#define S3C_WINCON_INRGB_YUV (1 << 13) +#define S3C_WINCON_INRGB_MASK (1 << 13) +#define S3C_WINCON_BURSTLEN_16WORD (0 << 9) +#define S3C_WINCON_BURSTLEN_8WORD (1 << 9) +#define S3C_WINCON_BURSTLEN_4WORD (2 << 9) +#define S3C_WINCON_BURSTLEN_MASK (3 << 9) +#define S3C_WINCON_ALPHA_MULTI_DISABLE (0 << 7) +#define S3C_WINCON_ALPHA_MULTI_ENABLE (1 << 7) +#define S3C_WINCON_BLD_PLANE (0 << 6) +#define S3C_WINCON_BLD_PIXEL (1 << 6) +#define S3C_WINCON_BLD_MASK (1 << 6) +#define S3C_WINCON_BPPMODE_1BPP (0 << 2) +#define S3C_WINCON_BPPMODE_2BPP (1 << 2) +#define S3C_WINCON_BPPMODE_4BPP (2 << 2) +#define S3C_WINCON_BPPMODE_8BPP_PAL (3 << 2) +#define S3C_WINCON_BPPMODE_8BPP (4 << 2) +#define S3C_WINCON_BPPMODE_16BPP_565 (5 << 2) +#define S3C_WINCON_BPPMODE_16BPP_A555 (6 << 2) +#define S3C_WINCON_BPPMODE_18BPP_666 (8 << 2) +#define S3C_WINCON_BPPMODE_18BPP_A665 (9 << 2) +#define S3C_WINCON_BPPMODE_24BPP_888 (0xb << 2) +#define S3C_WINCON_BPPMODE_24BPP_A887 (0xc << 2) +#define S3C_WINCON_BPPMODE_32BPP (0xd << 2) +#define S3C_WINCON_BPPMODE_16BPP_A444 (0xe << 2) +#define S3C_WINCON_BPPMODE_15BPP_555 (0xf << 2) +#define S3C_WINCON_BPPMODE_MASK (0xf << 2) +#define S3C_WINCON_BPPMODE_SHIFT (2) +#define S3C_WINCON_ALPHA0_SEL (0 << 1) +#define S3C_WINCON_ALPHA1_SEL (1 << 1) +#define S3C_WINCON_ALPHA_SEL_MASK (1 << 1) +#define S3C_WINCON_ENWIN_DISABLE (0 << 0) +#define S3C_WINCON_ENWIN_ENABLE (1 << 0) + +/* WINCON1 special */ +#define S3C_WINCON1_VP_DISABLE (0 << 24) +#define S3C_WINCON1_VP_ENABLE (1 << 24) +#define S3C_WINCON1_LOCALSEL_FIMC1 (0 << 23) +#define S3C_WINCON1_LOCALSEL_VP (1 << 23) +#define S3C_WINCON1_LOCALSEL_MASK (1 << 23) + +/* WINSHMAP */ +#define S3C_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10) +#define S3C_WINSHMAP_CH_ENABLE(x) (1 << (x)) +#define S3C_WINSHMAP_CH_DISABLE(x) (1 << (x)) +#define S3C_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x)) +#define S3C_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x)) + + +/* VIDOSDxA, VIDOSDxB */ +#define S3C_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11) +#define S3C_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) +#define S3C_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) +#define S3C_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) + +/* VIDOSD0C, VIDOSDxD */ +#define S3C_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) + +/* VIDOSDxC (1~4) */ +#define S3C_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20) +#define S3C_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16) +#define S3C_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12) +#define S3C_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8) +#define S3C_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4) +#define S3C_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0) +#define S3C_VIDOSD_ALPHA0_SHIFT (12) +#define S3C_VIDOSD_ALPHA1_SHIFT (0) + +/* Start Address */ +#define S3C_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24) +#define S3C_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0) + +/* End Address */ +#define S3C_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0) + +/* Buffer Size */ +#define S3C_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) +#define S3C_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) + +/* WIN Color Map */ +#define S3C_WINMAP_COLOR(x) ((x) & 0xffffff) + +/* VIDINTCON0 */ +#define S3C_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19) +#define S3C_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19) +#define S3C_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18) +#define S3C_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18) +#define S3C_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17) +#define S3C_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17) +#define S3C_VIDINTCON0_FRAMESEL0_BACK (0 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_FRONT (3 << 15) +#define S3C_VIDINTCON0_FRAMESEL0_MASK (3 << 15) +#define S3C_VIDINTCON0_FRAMESEL1_NONE (0 << 13) +#define S3C_VIDINTCON0_FRAMESEL1_BACK (1 << 13) +#define S3C_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13) +#define S3C_VIDINTCON0_FRAMESEL1_FRONT (3 << 13) +#define S3C_VIDINTCON0_INTFRMEN_DISABLE (0 << 12) +#define S3C_VIDINTCON0_INTFRMEN_ENABLE (1 << 12) +#define S3C_VIDINTCON0_FIFOSEL_WIN4 (1 << 11) +#define S3C_VIDINTCON0_FIFOSEL_WIN3 (1 << 10) +#define S3C_VIDINTCON0_FIFOSEL_WIN2 (1 << 9) +#define S3C_VIDINTCON0_FIFOSEL_WIN1 (1 << 6) +#define S3C_VIDINTCON0_FIFOSEL_WIN0 (1 << 5) +#define S3C_VIDINTCON0_FIFOSEL_ALL (0x73 << 5) +#define S3C_VIDINTCON0_FIFOSEL_MASK (0x73 << 5) +#define S3C_VIDINTCON0_FIFOLEVEL_25 (0 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_50 (1 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_75 (2 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_FULL (4 << 2) +#define S3C_VIDINTCON0_FIFOLEVEL_MASK (7 << 2) +#define S3C_VIDINTCON0_INTFIFO_DISABLE (0 << 1) +#define S3C_VIDINTCON0_INTFIFO_ENABLE (1 << 1) +#define S3C_VIDINTCON0_INT_DISABLE (0 << 0) +#define S3C_VIDINTCON0_INT_ENABLE (1 << 0) +#define S3C_VIDINTCON0_INT_MASK (1 << 0) + +/* VIDINTCON1 */ +#define S3C_VIDINTCON1_INTVPPEND (1 << 5) +#define S3C_VIDINTCON1_INTI80PEND (1 << 2) +#define S3C_VIDINTCON1_INTFRMPEND (1 << 1) +#define S3C_VIDINTCON1_INTFIFOPEND (1 << 0) + +/* WINMAP */ +#define S3C_WINMAP_ENABLE (1 << 24) + +/* WxKEYCON0 (1~4) */ +#define S3C_KEYCON0_KEYBLEN_DISABLE (0 << 26) +#define S3C_KEYCON0_KEYBLEN_ENABLE (1 << 26) +#define S3C_KEYCON0_KEY_DISABLE (0 << 25) +#define S3C_KEYCON0_KEY_ENABLE (1 << 25) +#define S3C_KEYCON0_DIRCON_MATCH_FG (0 << 24) +#define S3C_KEYCON0_DIRCON_MATCH_BG (1 << 24) +#define S3C_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0) + +/* WxKEYCON1 (1~4) */ +#define S3C_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0) + +#endif /* _REGS_FB_H */ diff --git a/arch/arm/plat-s5p/include/plat/regs-fimc.h b/arch/arm/plat-s5p/include/plat/regs-fimc.h new file mode 100644 index 0000000..26cd622 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-fimc.h @@ -0,0 +1,446 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-fimc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Register definition file for Samsung Camera Interface (FIMC) driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_REGS_FIMC_H +#define __ASM_PLAT_REGS_FIMC_H __FILE__ + +/* + * Register part +*/ +#define S3C_CIOYSA(__x) (0x18 + (__x) * 4) +#define S3C_CIOCBSA(__x) (0x28 + (__x) * 4) +#define S3C_CIOCRSA(__x) (0x38 + (__x) * 4) + +#define S3C_CISRCFMT (0x00) /* Input source format */ +#define S3C_CIWDOFST (0x04) /* Window offset */ +#define S3C_CIGCTRL (0x08) /* Global control */ +#define S3C_CIWDOFST2 (0x14) /* Window offset 2 */ +#define S3C_CIOYSA1 (0x18) /* Y 1st frame start address for output DMA */ +#define S3C_CIOYSA2 (0x1c) /* Y 2nd frame start address for output DMA */ +#define S3C_CIOYSA3 (0x20) /* Y 3rd frame start address for output DMA */ +#define S3C_CIOYSA4 (0x24) /* Y 4th frame start address for output DMA */ +#define S3C_CIOCBSA1 (0x28) /* Cb 1st frame start address for output DMA */ +#define S3C_CIOCBSA2 (0x2c) /* Cb 2nd frame start address for output DMA */ +#define S3C_CIOCBSA3 (0x30) /* Cb 3rd frame start address for output DMA */ +#define S3C_CIOCBSA4 (0x34) /* Cb 4th frame start address for output DMA */ +#define S3C_CIOCRSA1 (0x38) /* Cr 1st frame start address for output DMA */ +#define S3C_CIOCRSA2 (0x3c) /* Cr 2nd frame start address for output DMA */ +#define S3C_CIOCRSA3 (0x40) /* Cr 3rd frame start address for output DMA */ +#define S3C_CIOCRSA4 (0x44) /* Cr 4th frame start address for output DMA */ +#define S3C_CITRGFMT (0x48) /* Target image format */ +#define S3C_CIOCTRL (0x4c) /* Output DMA control */ +#define S3C_CISCPRERATIO (0x50) /* Pre-scaler control 1 */ +#define S3C_CISCPREDST (0x54) /* Pre-scaler control 2 */ +#define S3C_CISCCTRL (0x58) /* Main scaler control */ +#define S3C_CITAREA (0x5c) /* Target area */ +#define S3C_CISTATUS (0x64) /* Status */ +#define S3C_CIIMGCPT (0xc0) /* Image capture enable command */ +#define S3C_CICPTSEQ (0xc4) /* Capture sequence */ +#define S3C_CIIMGEFF (0xd0) /* Image effects */ +#define S3C_CIIYSA0 (0xd4) /* Y frame start address for input DMA */ +#define S3C_CIICBSA0 (0xd8) /* Cb frame start address for input DMA */ +#define S3C_CIICRSA0 (0xdc) /* Cr frame start address for input DMA */ +#define S3C_CIILINESKIP_Y (0xec) /* Input DMA Y Line Skip */ +#define S3C_CIILINESKIP_CB (0xf0) /* Input DMA Cb Line Skip */ +#define S3C_CIILINESKIP_CR (0xf4) /* Input DMA Cr Line Skip */ +#define S3C_CIREAL_ISIZE (0xf8) /* Real input DMA image size */ +#define S3C_MSCTRL (0xfc) /* Input DMA control */ +#define S3C_CIOYOFF (0x168) /* Output DMA Y offset */ +#define S3C_CIOCBOFF (0x16c) /* Output DMA CB offset */ +#define S3C_CIOCROFF (0x170) /* Output DMA CR offset */ +#define S3C_CIIYOFF (0x174) /* Input DMA Y offset */ +#define S3C_CIICBOFF (0x178) /* Input DMA CB offset */ +#define S3C_CIICROFF (0x17c) /* Input DMA CR offset */ +#define S3C_ORGISIZE (0x180) /* Input DMA original image size */ +#define S3C_ORGOSIZE (0x184) /* Output DMA original image size */ +#define S3C_CIEXTEN (0x188) /* Real output DMA image size */ +#define S3C_CIDMAPARAM (0x18c) /* DMA parameter */ +#define S3C_CSIIMGFMT (0x194) /* MIPI CSI image format */ +#define S3C_MISC_FIMC (0x198) /* FIMC Clock Source Select */ + +/* + * Macro part +*/ +#define S3C_CISRCFMT_SOURCEHSIZE(x) ((x) << 16) +#define S3C_CISRCFMT_SOURCEVSIZE(x) ((x) << 0) + +#define S3C_CIWDOFST_WINHOROFST(x) ((x) << 16) +#define S3C_CIWDOFST_WINVEROFST(x) ((x) << 0) + +#define S3C_CIWDOFST2_WINHOROFST2(x) ((x) << 16) +#define S3C_CIWDOFST2_WINVEROFST2(x) ((x) << 0) + +#define S3C_CITRGFMT_TARGETHSIZE(x) (((x) & 0x1fff) << 16) +#define S3C_CITRGFMT_TARGETVSIZE(x) (((x) & 0x1fff) << 0) + +#define S3C_CISCPRERATIO_SHFACTOR(x) ((x) << 28) +#define S3C_CISCPRERATIO_PREHORRATIO(x) ((x) << 16) +#define S3C_CISCPRERATIO_PREVERRATIO(x) ((x) << 0) + +#define S3C_CISCPREDST_PREDSTWIDTH(x) ((x) << 16) +#define S3C_CISCPREDST_PREDSTHEIGHT(x) ((x) << 0) + +#define S3C_CISCCTRL_MAINHORRATIO(x) ((x) << 16) +#define S3C_CISCCTRL_MAINVERRATIO(x) ((x) << 0) + +#define S3C_CITAREA_TARGET_AREA(x) ((x) << 0) + +#define S3C_CISTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) +#define S3C_CISTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1) +#define S3C_CISTATUS_GET_LAST_CAPTURE_END(x) (((x) >> 16) & 0x1) +#define S3C_CISTATUS_GET_LCD_STATUS(x) (((x) >> 9) & 0x1) +#define S3C_CISTATUS_GET_ENVID_STATUS(x) ((x) & 0x1) + +#define S3C_CIIMGEFF_FIN(x) ((x & 0x7) << 26) +#define S3C_CIIMGEFF_PAT_CB(x) ((x) << 13) +#define S3C_CIIMGEFF_PAT_CR(x) ((x) << 0) + +#define S3C_CIILINESKIP(x) (((x) & 0xf) << 24) + +#define S3C_CIREAL_ISIZE_HEIGHT(x) ((x) << 16) +#define S3C_CIREAL_ISIZE_WIDTH(x) ((x) << 0) + +#define S3C_MSCTRL_SUCCESSIVE_COUNT(x) ((x) << 24) +#define S3C_MSCTRL_GET_INDMA_STATUS(x) ((x) & 0x1) + +#define S3C_CIOYOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIOYOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIOCBOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIOCBOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIOCROFF_VERTICAL(x) ((x) << 16) +#define S3C_CIOCROFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIIYOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIIYOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIICBOFF_VERTICAL(x) ((x) << 16) +#define S3C_CIICBOFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIICROFF_VERTICAL(x) ((x) << 16) +#define S3C_CIICROFF_HORIZONTAL(x) ((x) << 0) + +#define S3C_ORGISIZE_VERTICAL(x) ((x) << 16) +#define S3C_ORGISIZE_HORIZONTAL(x) ((x) << 0) + +#define S3C_ORGOSIZE_VERTICAL(x) ((x) << 16) +#define S3C_ORGOSIZE_HORIZONTAL(x) ((x) << 0) + +#define S3C_CIEXTEN_TARGETH_EXT(x) (((x) & 0x2000) << 26) +#define S3C_CIEXTEN_TARGETV_EXT(x) (((x) & 0x2000) << 24) +#define S3C_CIEXTEN_MAINHORRATIO_EXT(x) (((x) & 0x3F) << 10) +#define S3C_CIEXTEN_MAINVERRATIO_EXT(x) ((x) & 0x3F) + +/* + * Bit definition part +*/ +/* Source format register */ +#define S3C_CISRCFMT_ITU601_8BIT (1 << 31) +#define S3C_CISRCFMT_ITU656_8BIT (0 << 31) +#define S3C_CISRCFMT_ITU601_16BIT (1 << 29) +#define S3C_CISRCFMT_ORDER422_YCBYCR (0 << 14) +#define S3C_CISRCFMT_ORDER422_YCRYCB (1 << 14) +#define S3C_CISRCFMT_ORDER422_CBYCRY (2 << 14) +#define S3C_CISRCFMT_ORDER422_CRYCBY (3 << 14) +#define S3C_CISRCFMT_ORDER422_Y4CBCRCBCR (0 << 14) /* ITU601 16bit only */ +#define S3C_CISRCFMT_ORDER422_Y4CRCBCRCB (1 << 14) /* ITU601 16bit only */ + +/* Window offset register */ +#define S3C_CIWDOFST_WINOFSEN (1 << 31) +#define S3C_CIWDOFST_CLROVFIY (1 << 30) +#define S3C_CIWDOFST_CLROVRLB (1 << 29) +#define S3C_CIWDOFST_WINHOROFST_MASK (0x7ff << 16) +#define S3C_CIWDOFST_CLROVFICB (1 << 15) +#define S3C_CIWDOFST_CLROVFICR (1 << 14) +#define S3C_CIWDOFST_WINVEROFST_MASK (0xfff << 0) + +/* Global control register */ +#define S3C_CIGCTRL_SWRST (1 << 31) +#define S3C_CIGCTRL_CAMRST_A (1 << 30) +#define S3C_CIGCTRL_SELCAM_ITU_B (0 << 29) +#define S3C_CIGCTRL_SELCAM_ITU_A (1 << 29) +#define S3C_CIGCTRL_SELCAM_ITU_MASK (1 << 29) +#define S3C_CIGCTRL_TESTPATTERN_NORMAL (0 << 27) +#define S3C_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) +#define S3C_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) +#define S3C_CIGCTRL_TESTPATTERN_VER_INC (3 << 27) +#define S3C_CIGCTRL_TESTPATTERN_MASK (3 << 27) +#define S3C_CIGCTRL_TESTPATTERN_SHIFT (27) +#define S3C_CIGCTRL_INVPOLPCLK (1 << 26) +#define S3C_CIGCTRL_INVPOLVSYNC (1 << 25) +#define S3C_CIGCTRL_INVPOLHREF (1 << 24) +#define S3C_CIGCTRL_IRQ_OVFEN (1 << 22) +#define S3C_CIGCTRL_HREF_MASK (1 << 21) +#define S3C_CIGCTRL_IRQ_EDGE (0 << 20) +#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20) +#define S3C_CIGCTRL_IRQ_CLR (1 << 19) +#define S3C_CIGCTRL_IRQ_DISABLE (0 << 16) +#define S3C_CIGCTRL_IRQ_ENABLE (1 << 16) +#define S3C_CIGCTRL_SHADOW_DISABLE (1 << 12) +#define S3C_CIGCTRL_CAM_JPEG (1 << 8) +#define S3C_CIGCTRL_SELCAM_MIPI_B (0 << 7) +#define S3C_CIGCTRL_SELCAM_MIPI_A (1 << 7) +#define S3C_CIGCTRL_SELCAM_MIPI_MASK (1 << 7) +#define S3C_CIGCTRL_SELWB_CAMIF_CAMERA (0 << 6) +#define S3C_CIGCTRL_SELWB_CAMIF_WRITEBACK (1 << 6) +#define S3C_CIGCTRL_SELWB_CAMIF_MASK (1 << 6) +#define S3C_CIGCTRL_CSC_ITU601 (0 << 5) +#define S3C_CIGCTRL_CSC_ITU709 (1 << 5) +#define S3C_CIGCTRL_CSC_MASK (1 << 5) +#define S3C_CIGCTRL_INVPOLHSYNC (1 << 4) +#define S3C_CIGCTRL_SELCAM_FIMC_ITU (0 << 3) +#define S3C_CIGCTRL_SELCAM_FIMC_MIPI (1 << 3) +#define S3C_CIGCTRL_SELCAM_FIMC_MASK (1 << 3) +#define S3C_CIGCTRL_PROGRESSIVE (0 << 0) +#define S3C_CIGCTRL_INTERLACE (1 << 0) + +/* Window offset2 register */ +#define S3C_CIWDOFST_WINHOROFST2_MASK (0xfff << 16) +#define S3C_CIWDOFST_WINVEROFST2_MASK (0xfff << 16) + +/* Target format register */ +#define S3C_CITRGFMT_INROT90_CLOCKWISE (1 << 31) +#define S3C_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) +#define S3C_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) +#define S3C_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE (2 << 29) +#define S3C_CITRGFMT_OUTFORMAT_RGB (3 << 29) +#define S3C_CITRGFMT_OUTFORMAT_MASK (3 << 29) +#define S3C_CITRGFMT_FLIP_SHIFT (14) +#define S3C_CITRGFMT_FLIP_NORMAL (0 << 14) +#define S3C_CITRGFMT_FLIP_X_MIRROR (1 << 14) +#define S3C_CITRGFMT_FLIP_Y_MIRROR (2 << 14) +#define S3C_CITRGFMT_FLIP_180 (3 << 14) +#define S3C_CITRGFMT_FLIP_MASK (3 << 14) +#define S3C_CITRGFMT_OUTROT90_CLOCKWISE (1 << 13) +#define S3C_CITRGFMT_TARGETV_MASK (0x1fff << 0) +#define S3C_CITRGFMT_TARGETH_MASK (0x1fff << 16) + +/* Output DMA control register */ +#define S3C_CIOCTRL_WEAVE_OUT (1 << 31) +#define S3C_CIOCTRL_WEAVE_MASK (1 << 31) +#define S3C_CIOCTRL_ORDER2P_LSB_CBCR (0 << 24) +#define S3C_CIOCTRL_ORDER2P_LSB_CRCB (1 << 24) +#define S3C_CIOCTRL_ORDER2P_MSB_CRCB (2 << 24) +#define S3C_CIOCTRL_ORDER2P_MSB_CBCR (3 << 24) +#define S3C_CIOCTRL_ORDER2P_SHIFT (24) +#define S3C_CIOCTRL_ORDER2P_MASK (3 << 24) +#define S3C_CIOCTRL_YCBCR_3PLANE (0 << 3) +#define S3C_CIOCTRL_YCBCR_2PLANE (1 << 3) +#define S3C_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) +#define S3C_CIOCTRL_LASTIRQ_ENABLE (1 << 2) +#define S3C_CIOCTRL_ORDER422_YCBYCR (0 << 0) +#define S3C_CIOCTRL_ORDER422_YCRYCB (1 << 0) +#define S3C_CIOCTRL_ORDER422_CBYCRY (2 << 0) +#define S3C_CIOCTRL_ORDER422_CRYCBY (3 << 0) +#define S3C_CIOCTRL_ORDER422_MASK (3 << 0) + +/* Main scaler control register */ +#define S3C_CISCCTRL_SCALERBYPASS (1 << 31) +#define S3C_CISCCTRL_SCALEUP_H (1 << 30) +#define S3C_CISCCTRL_SCALEUP_V (1 << 29) +#define S3C_CISCCTRL_CSCR2Y_NARROW (0 << 28) +#define S3C_CISCCTRL_CSCR2Y_WIDE (1 << 28) +#define S3C_CISCCTRL_CSCY2R_NARROW (0 << 27) +#define S3C_CISCCTRL_CSCY2R_WIDE (1 << 27) +#define S3C_CISCCTRL_LCDPATHEN_FIFO (1 << 26) +#define S3C_CISCCTRL_PROGRESSIVE (0 << 25) +#define S3C_CISCCTRL_INTERLACE (1 << 25) +#define S3C_CISCCTRL_SCAN_MASK (1 << 25) +#define S3C_CISCCTRL_SCALERSTART (1 << 15) +#define S3C_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) +#define S3C_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) +#define S3C_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) +#define S3C_CISCCTRL_INRGB_FMT_RGB_MASK (3 << 13) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) +#define S3C_CISCCTRL_OUTRGB_FMT_RGB_MASK (3 << 11) +#define S3C_CISCCTRL_EXTRGB_NORMAL (0 << 10) +#define S3C_CISCCTRL_EXTRGB_EXTENSION (1 << 10) +#define S3C_CISCCTRL_ONE2ONE (1 << 9) +#define S3C_CISCCTRL_MAIN_V_RATIO_MASK (0x1ff << 0) +#define S3C_CISCCTRL_MAIN_H_RATIO_MASK (0x1ff << 16) + +/* Status register */ +#define S3C_CISTATUS_OVFIY (1 << 31) +#define S3C_CISTATUS_OVFICB (1 << 30) +#define S3C_CISTATUS_OVFICR (1 << 29) +#define S3C_CISTATUS_VSYNC (1 << 28) +#define S3C_CISTATUS_WINOFSTEN (1 << 25) +#define S3C_CISTATUS_IMGCPTEN (1 << 22) +#define S3C_CISTATUS_IMGCPTENSC (1 << 21) +#define S3C_CISTATUS_VSYNC_A (1 << 20) +#define S3C_CISTATUS_VSYNC_B (1 << 19) +#define S3C_CISTATUS_OVRLB (1 << 18) +#define S3C_CISTATUS_FRAMEEND (1 << 17) +#define S3C_CISTATUS_LASTCAPTUREEND (1 << 16) +#define S3C_CISTATUS_VVALID_A (1 << 15) +#define S3C_CISTATUS_VVALID_B (1 << 14) + +/* Image capture enable register */ +#define S3C_CIIMGCPT_IMGCPTEN (1 << 31) +#define S3C_CIIMGCPT_IMGCPTEN_SC (1 << 30) +#define S3C_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) +#define S3C_CIIMGCPT_CPT_FRMOD_EN (0 << 18) +#define S3C_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) + +/* Image effects register */ +#define S3C_CIIMGEFF_IE_DISABLE (0 << 30) +#define S3C_CIIMGEFF_IE_ENABLE (1 << 30) +#define S3C_CIIMGEFF_IE_SC_BEFORE (0 << 29) +#define S3C_CIIMGEFF_IE_SC_AFTER (1 << 29) +#define S3C_CIIMGEFF_FIN_BYPASS (0 << 26) +#define S3C_CIIMGEFF_FIN_ARBITRARY (1 << 26) +#define S3C_CIIMGEFF_FIN_NEGATIVE (2 << 26) +#define S3C_CIIMGEFF_FIN_ARTFREEZE (3 << 26) +#define S3C_CIIMGEFF_FIN_EMBOSSING (4 << 26) +#define S3C_CIIMGEFF_FIN_SILHOUETTE (5 << 26) +#define S3C_CIIMGEFF_FIN_MASK (7 << 26) +#define S3C_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0)) + +/* Real input DMA size register */ +#define S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31) +#define S3C_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30) +#define S3C_CIREAL_ISIZE_HEIGHT_MASK (0x3FFF << 16) +#define S3C_CIREAL_ISIZE_WIDTH_MASK (0x3FFF << 0) + +/* Input DMA control register */ +#define S3C_MSCTRL_FIELD_MASK (1 << 31) +#define S3C_MSCTRL_FIELD_WEAVE (1 << 31) +#define S3C_MSCTRL_FIELD_NORMAL (0 << 31) +#define S3C_MSCTRL_BURST_CNT (24) +#define S3C_MSCTRL_BURST_CNT_MASK (0xf << 24) +#define S3C_MSCTRL_ORDER2P_LSB_CBCR (0 << 16) +#define S3C_MSCTRL_ORDER2P_LSB_CRCB (1 << 16) +#define S3C_MSCTRL_ORDER2P_MSB_CRCB (2 << 16) +#define S3C_MSCTRL_ORDER2P_MSB_CBCR (3 << 16) +#define S3C_MSCTRL_ORDER2P_SHIFT (16) +#define S3C_MSCTRL_ORDER2P_SHIFT_MASK (0x3 << 16) +#define S3C_MSCTRL_C_INT_IN_3PLANE (0 << 15) +#define S3C_MSCTRL_C_INT_IN_2PLANE (1 << 15) +#define S3C_MSCTRL_FLIP_SHIFT (13) +#define S3C_MSCTRL_FLIP_NORMAL (0 << 13) +#define S3C_MSCTRL_FLIP_X_MIRROR (1 << 13) +#define S3C_MSCTRL_FLIP_Y_MIRROR (2 << 13) +#define S3C_MSCTRL_FLIP_180 (3 << 13) +#define S3C_MSCTRL_FLIP_MASK (3 << 13) +#define S3C_MSCTRL_ORDER422_CRYCBY (0 << 4) +#define S3C_MSCTRL_ORDER422_YCRYCB (1 << 4) +#define S3C_MSCTRL_ORDER422_CBYCRY (2 << 4) +#define S3C_MSCTRL_ORDER422_YCBYCR (3 << 4) +#define S3C_MSCTRL_INPUT_EXTCAM (0 << 3) +#define S3C_MSCTRL_INPUT_MEMORY (1 << 3) +#define S3C_MSCTRL_INPUT_MASK (1 << 3) +#define S3C_MSCTRL_INFORMAT_YCBCR420 (0 << 1) +#define S3C_MSCTRL_INFORMAT_YCBCR422 (1 << 1) +#define S3C_MSCTRL_INFORMAT_YCBCR422_1PLANE (2 << 1) +#define S3C_MSCTRL_INFORMAT_RGB (3 << 1) +#define S3C_MSCTRL_ENVID (1 << 0) + +/* DMA parameter register */ +#define S3C_CIDMAPARAM_R_MODE_LINEAR (0 << 29) +#define S3C_CIDMAPARAM_R_MODE_CONFTILE (1 << 29) +#define S3C_CIDMAPARAM_R_MODE_16X16 (2 << 29) +#define S3C_CIDMAPARAM_R_MODE_64X32 (3 << 29) +#define S3C_CIDMAPARAM_R_MODE_MASK (3 << 29) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_64 (0 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_128 (1 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_256 (2 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_512 (3 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24) +#define S3C_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_1 (0 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_2 (1 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_4 (2 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_8 (3 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20) +#define S3C_CIDMAPARAM_R_TILE_VSIZE_32 (5 << 20) +#define S3C_CIDMAPARAM_W_MODE_LINEAR (0 << 13) +#define S3C_CIDMAPARAM_W_MODE_CONFTILE (1 << 13) +#define S3C_CIDMAPARAM_W_MODE_16X16 (2 << 13) +#define S3C_CIDMAPARAM_W_MODE_64X32 (3 << 13) +#define S3C_CIDMAPARAM_W_MODE_MASK (3 << 13) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_64 (0 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_128 (1 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_256 (2 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_512 (3 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8) +#define S3C_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4) +#define S3C_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4) + +/* Gathering Extension register */ +#define S3C_CIEXTEN_TARGETH_EXT_MASK (1 << 26) +#define S3C_CIEXTEN_TARGETV_EXT_MASK (1 << 24) +#define S3C_CIEXTEN_MAINHORRATIO_EXT_MASK (0x3F << 10) +#define S3C_CIEXTEN_MAINVERRATIO_EXT_MASK (0x3F) +#define S3C_CIEXTEN_YUV444_OUT (1 << 22) + +/* FIMC Clock Source Select register */ +#define S3C_CLKSRC_HCLK (0 << 1) +#define S3C_CLKSRC_HCLK_MASK (1 << 1) +#define S3C_CLKSRC_SCLK (1 << 1) + +/* FIMC GPIO */ +#define S5PV210_GPE0_0_CAM_A_PCLK (0x2 << 0) +#define S5PV210_GPE0_0_GPIO_INT8_0 (0xf << 0) + +#define S5PV210_GPE0_1_CAM_A_VSYNC (0x2 << 4) +#define S5PV210_GPE0_1_GPIO_INT8_1 (0xf << 4) + +#define S5PV210_GPE0_2_CAM_A_HREF (0x2 << 8) +#define S5PV210_GPE0_2_GPIO_INT8_2 (0xf << 8) + +#define S5PV210_GPE0_3_CAM_A_DATA_0 (0x2 << 12) +#define S5PV210_GPE0_3_GPIO_INT8_3 (0xf << 12) + +#define S5PV210_GPE0_4_CAM_A_DATA_1 (0x2 << 16) +#define S5PV210_GPE0_4_GPIO_INT8_4 (0xf << 16) + +#define S5PV210_GPE0_5_CAM_A_DATA_2 (0x2 << 20) +#define S5PV210_GPE0_5_GPIO_INT8_5 (0xf << 20) + +#define S5PV210_GPE0_6_CAM_A_DATA_3 (0x2 << 24) +#define S5PV210_GPE0_6_GPIO_INT8_6 (0xf << 24) + +#define S5PV210_GPE0_7_CAM_A_DATA_4 (0x2 << 28) +#define S5PV210_GPE0_7_GPIO_INT8_7 (0xf << 28) + +#define S5PV210_GPE1_0_CAM_A_DATA_5 (0x2 << 0) +#define S5PV210_GPE1_1_CAM_A_DATA_6 (0x2 << 4) +#define S5PV210_GPE1_2_CAM_A_DATA_7 (0x2 << 8) +#define S5PV210_GPE1_3_CAM_A_CLKOUT (0x2 << 12) +#define S5PV210_GPE1_4_CAM_A_FIELD (0x2 << 16) + +#define S5PV210_GPJ0_0_CAM_B_DATA_0 (0x3 << 0) +#define S5PV210_GPJ0_1_CAM_B_DATA_1 (0x3 << 4) +#define S5PV210_GPJ0_2_CAM_B_DATA_2 (0x3 << 8) +#define S5PV210_GPJ0_3_CAM_B_DATA_3 (0x3 << 12) +#define S5PV210_GPJ0_4_CAM_B_DATA_4 (0x3 << 16) +#define S5PV210_GPJ0_5_CAM_B_DATA_5 (0x3 << 20) +#define S5PV210_GPJ0_6_CAM_B_DATA_6 (0x3 << 24) +#define S5PV210_GPJ0_7_CAM_B_DATA_7 (0x3 << 28) + +#define S5PV210_GPJ1_0_CAM_B_PCLK (0x3 << 0) +#define S5PV210_GPJ1_1_CAM_B_VSYNC (0x3 << 4) +#define S5PV210_GPJ1_2_CAM_B_HREF (0x3 << 8) +#define S5PV210_GPJ1_3_CAM_B_FIELD (0x3 << 12) +#define S5PV210_GPJ1_4_CAM_B_CLKOUT (0x3 << 16) + +#endif /* __ASM_PLAT_REGS_FIMC_H */ diff --git a/arch/arm/plat-s5p/include/plat/regs-iis.h b/arch/arm/plat-s5p/include/plat/regs-iis.h new file mode 100644 index 0000000..db94a13 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-iis.h @@ -0,0 +1,147 @@ +/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h + * + * Copyright 2007 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2412 IIS register definition +*/ + +#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H +#define __ASM_ARCH_REGS_S3C2412_IIS_H + +#define S3C2412_IISCON (0x00) +#define S3C2412_IISMOD (0x04) +#define S3C2412_IISFIC (0x08) +#define S3C2412_IISPSR (0x0C) +#define S3C2412_IISTXD (0x10) +#define S3C2412_IISRXD (0x14) +#define S5P_IISFICS (0x18) +#define S5P_IISTXDS (0x1C) +#define S5P_IISAHB (0x20) +#define S5P_IISSTR (0x24) +#define S5P_IISSIZE (0x28) +#define S5P_IISTRNCNT (0x2C) +#define S5P_IISADDR0 (0x30) +#define S5P_IISADDR1 (0x34) +#define S5P_IISADDR2 (0x38) +#define S5P_IISADDR3 (0x3C) + +#define S5P_IISCON_FTXSURSTAT (1 << 24) +#define S5P_IISCON_FTXSURINTEN (1 << 23) +#define S5P_IISCON_TXSDMAPAUSE (1 << 20) +#define S5P_IISCON_TXSDMACTIVE (1 << 18) +#define S5P_IISCON_FTXURSTATUS (1 << 17) +#define S5P_IISCON_FTXURINTEN (1 << 16) + +#define S3C2412_IISCON_LRINDEX (1 << 11) +#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10) +#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9) +#define S3C2412_IISCON_TXFIFO_FULL (1 << 8) +#define S3C2412_IISCON_RXFIFO_FULL (1 << 7) +#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6) +#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5) +#define S3C2412_IISCON_TXCH_PAUSE (1 << 4) +#define S3C2412_IISCON_RXCH_PAUSE (1 << 3) +#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2) +#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1) +#define S3C2412_IISCON_IIS_ACTIVE (1 << 0) + +#define S3C64XX_IISMOD_OPPCLK (3<<30) + +#define S5P_IISMOD_TXSLP (1<<28) +#define S5P_IISMOD_BLCPMASK (3<<24) +#define S5P_IISMOD_BLCSMASK (3<<26) + +#define S3C64XX_IISMOD_BLC_16BIT (0 << 13) +#define S3C64XX_IISMOD_BLC_8BIT (1 << 13) +#define S3C64XX_IISMOD_BLC_24BIT (2 << 13) +#define S3C64XX_IISMOD_BLC_MASK (3 << 13) + +#define S3C64XX_IISMOD_IMSMASK (3 << 10) +#define S3C64XX_IISMOD_IMS_PCLK (0 << 10) +#define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10) +#define S3C64XX_CLKSRC_I2SEXT (3 << 10) +#define S3C64XX_CDCLKSRC_EXT (5 << 10) + +#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10) +#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10) +#define S3C2412_IISMOD_SLAVE (2 << 10) +#define S3C2412_IISMOD_MASTER_MASK (3 << 10) +#define S3C2412_IISMOD_MODE_TXONLY (0 << 8) +#define S3C2412_IISMOD_MODE_RXONLY (1 << 8) +#define S3C2412_IISMOD_MODE_TXRX (2 << 8) +#define S3C2412_IISMOD_MODE_MASK (3 << 8) +#define S3C2412_IISMOD_LR_LLOW (0 << 7) +#define S3C2412_IISMOD_LR_RLOW (1 << 7) +#define S3C2412_IISMOD_SDF_IIS (0 << 5) +#define S3C2412_IISMOD_SDF_MSB (1 << 5) +#define S3C2412_IISMOD_SDF_LSB (2 << 5) +#define S3C2412_IISMOD_SDF_MASK (3 << 5) +#define S3C2412_IISMOD_RCLK_256FS (0 << 3) +#define S3C2412_IISMOD_RCLK_512FS (1 << 3) +#define S3C2412_IISMOD_RCLK_384FS (2 << 3) +#define S3C2412_IISMOD_RCLK_768FS (3 << 3) +#define S3C2412_IISMOD_RCLK_MASK (3 << 3) +#define S3C2412_IISMOD_BCLK_32FS (0 << 1) +#define S3C2412_IISMOD_BCLK_48FS (1 << 1) +#define S3C2412_IISMOD_BCLK_16FS (2 << 1) +#define S3C2412_IISMOD_BCLK_24FS (3 << 1) +#define S3C2412_IISMOD_BCLK_MASK (3 << 1) +#define S3C2412_IISMOD_8BIT (1 << 0) + +#define S3C64XX_IISMOD_CDCLKCON (1 << 12) + +#define S3C2412_IISPSR_PSREN (1 << 15) + +#define S3C2412_IISFIC_TXFLUSH (1 << 15) +#define S3C2412_IISFIC_RXFLUSH (1 << 7) +#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf) +#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf) + +#define S5P_IISAHB_INTENLVL3 (1<<27) +#define S5P_IISAHB_INTENLVL2 (1<<26) +#define S5P_IISAHB_INTENLVL1 (1<<25) +#define S5P_IISAHB_INTENLVL0 (1<<24) +#define S5P_IISAHB_LVL3INT (1<<23) +#define S5P_IISAHB_LVL2INT (1<<22) +#define S5P_IISAHB_LVL1INT (1<<21) +#define S5P_IISAHB_LVL0INT (1<<20) +#define S5P_IISAHB_CLRLVL3 (1<<19) +#define S5P_IISAHB_CLRLVL2 (1<<18) +#define S5P_IISAHB_CLRLVL1 (1<<17) +#define S5P_IISAHB_CLRLVL0 (1<<16) +#define S5P_IISAHB_DMARLD (1<<5) +#define S5P_IISAHB_DISRLDINT (1<<3) +#define S5P_IISAHB_DMAEND (1<<2) +#define S5P_IISAHB_DMACLR (1<<1) +#define S5P_IISAHB_DMAEN (1<<0) + +#define S5P_IISSIZE_SHIFT (16) +#define S5P_IISSIZE_TRNMSK (0xffff) +#define S5P_IISTRNCNT_MASK (0xffffff) + +#define S5P_IISADDR_MASK (0x3fffff) +#define S5P_IISADDR_SHIFT (10) +#define S5P_IISADDR_ENSTOP (1<<0) + +/* clock sources */ +#define S3C_IISMOD_IMSMASK (3<<10) +#define S3C_IISMOD_MSTPCLK (0<<10) +#define S3C_IISMOD_MSTCLKAUDIO (1<<10) +#define S3C_IISMOD_SLVPCLK (2<<10) +#define S3C_IISMOD_SLVI2SCLK (3<<10) + +#define S3C_CLKSRC_PCLK S3C_IISMOD_MSTPCLK +#define S3C_CLKSRC_CLKAUDIO S3C_IISMOD_MSTCLKAUDIO +#define S3C_CLKSRC_SLVPCLK S3C_IISMOD_SLVPCLK +#define S3C_CLKSRC_I2SEXT S3C_IISMOD_SLVI2SCLK +#define S3C_CDCLKSRC_INT (4<<10) +#define S3C_CDCLKSRC_EXT (5<<10) + + +#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */ + diff --git a/arch/arm/plat-s5p/include/plat/regs-ipc.h b/arch/arm/plat-s5p/include/plat/regs-ipc.h new file mode 100644 index 0000000..4d1172a --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-ipc.h @@ -0,0 +1,147 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-ipc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Register definition file for IPC driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_IPC_H +#define _REGS_IPC_H + +#define S3C_IPCREG(x) (x) + +#define IPC_2D_ENABLE 0x10000 +#define IPC_HOR_SCALING_ENABLE 0x8000 + +/************************************************************************* + * Registers + ************************************************************************/ +#define S3C_IPC_ENABLE S3C_IPCREG(0x00) +#define S3C_IPC_SRESET S3C_IPCREG(0x04) +#define S3C_IPC_SHADOW_UPDATE S3C_IPCREG(0x08) +#define S3C_IPC_FIELD_ID S3C_IPCREG(0x0c) +#define S3C_IPC_MODE S3C_IPCREG(0x10) +#define S3C_IPC_PEL_RATE_CTRL S3C_IPCREG(0x1C) +#define S3C_IPC_ENDIAN_MODE S3C_IPCREG(0x3C) +#define S3C_IPC_SRC_WIDTH S3C_IPCREG(0x4C) +#define S3C_IPC_SRC_HEIGHT S3C_IPCREG(0x50) +#define S3C_IPC_DST_WIDTH S3C_IPCREG(0x5C) +#define S3C_IPC_DST_HEIGHT S3C_IPCREG(0x60) +#define S3C_IPC_H_RATIO S3C_IPCREG(0x64) +#define S3C_IPC_V_RATIO S3C_IPCREG(0x68) + +#define S3C_IPC_POLY8_Y0_LL S3C_IPCREG(0x6C) +#define S3C_IPC_POLY8_Y0_LH S3C_IPCREG(0x70) +#define S3C_IPC_POLY8_Y0_HL S3C_IPCREG(0x74) +#define S3C_IPC_POLY8_Y0_HH S3C_IPCREG(0x78) +#define S3C_IPC_POLY8_Y1_LL S3C_IPCREG(0x7C) +#define S3C_IPC_POLY8_Y1_LH S3C_IPCREG(0x80) +#define S3C_IPC_POLY8_Y1_HL S3C_IPCREG(0x84) +#define S3C_IPC_POLY8_Y1_HH S3C_IPCREG(0x88) +#define S3C_IPC_POLY8_Y2_LL S3C_IPCREG(0x8C) +#define S3C_IPC_POLY8_Y2_LH S3C_IPCREG(0x90) +#define S3C_IPC_POLY8_Y2_HL S3C_IPCREG(0x94) +#define S3C_IPC_POLY8_Y2_HH S3C_IPCREG(0x98) +#define S3C_IPC_POLY8_Y3_LL S3C_IPCREG(0x9C) +#define S3C_IPC_POLY8_Y3_LH S3C_IPCREG(0xA0) +#define S3C_IPC_POLY8_Y3_HL S3C_IPCREG(0xA4) +#define S3C_IPC_POLY8_Y3_HH S3C_IPCREG(0xA8) +#define S3C_IPC_POLY4_Y0_LL S3C_IPCREG(0xEC) +#define S3C_IPC_POLY4_Y0_LH S3C_IPCREG(0xF0) +#define S3C_IPC_POLY4_Y0_HL S3C_IPCREG(0xF4) +#define S3C_IPC_POLY4_Y0_HH S3C_IPCREG(0xF8) +#define S3C_IPC_POLY4_Y1_LL S3C_IPCREG(0xFC) +#define S3C_IPC_POLY4_Y1_LH S3C_IPCREG(0x100) +#define S3C_IPC_POLY4_Y1_HL S3C_IPCREG(0x104) +#define S3C_IPC_POLY4_Y1_HH S3C_IPCREG(0x108) +#define S3C_IPC_POLY4_Y2_LL S3C_IPCREG(0x10C) +#define S3C_IPC_POLY4_Y2_LH S3C_IPCREG(0x110) +#define S3C_IPC_POLY4_Y2_HL S3C_IPCREG(0x114) +#define S3C_IPC_POLY4_Y2_HH S3C_IPCREG(0x118) +#define S3C_IPC_POLY4_Y3_LL S3C_IPCREG(0x11C) +#define S3C_IPC_POLY4_Y3_LH S3C_IPCREG(0x120) +#define S3C_IPC_POLY4_Y3_HL S3C_IPCREG(0x124) +#define S3C_IPC_POLY4_Y3_HH S3C_IPCREG(0x128) +#define S3C_IPC_POLY4_C0_LL S3C_IPCREG(0x12C) +#define S3C_IPC_POLY4_C0_LH S3C_IPCREG(0x130) +#define S3C_IPC_POLY4_C0_HL S3C_IPCREG(0x134) +#define S3C_IPC_POLY4_C0_HH S3C_IPCREG(0x138) +#define S3C_IPC_POLY4_C1_LL S3C_IPCREG(0x13C) +#define S3C_IPC_POLY4_C1_LH S3C_IPCREG(0x140) +#define S3C_IPC_POLY4_C1_HL S3C_IPCREG(0x144) +#define S3C_IPC_POLY4_C1_HH S3C_IPCREG(0x148) +#define S3C_IPC_BYPASS S3C_IPCREG(0x200) +#define S3C_IPC_PP_SATURATION S3C_IPCREG(0x20C) +#define S3C_IPC_PP_SHARPNESS S3C_IPCREG(0x210) +#define S3C_IPC_PP_LINE_EQ0 S3C_IPCREG(0x218) +#define S3C_IPC_PP_LINE_EQ1 S3C_IPCREG(0x21C) +#define S3C_IPC_PP_LINE_EQ2 S3C_IPCREG(0x220) +#define S3C_IPC_PP_LINE_EQ3 S3C_IPCREG(0x224) +#define S3C_IPC_PP_LINE_EQ4 S3C_IPCREG(0x228) +#define S3C_IPC_PP_LINE_EQ5 S3C_IPCREG(0x22C) +#define S3C_IPC_PP_LINE_EQ6 S3C_IPCREG(0x230) +#define S3C_IPC_PP_LINE_EQ7 S3C_IPCREG(0x234) +#define S3C_IPC_PP_BRIGHT_OFFSET S3C_IPCREG(0x238) +#define S3C_IPC_VERSION_INFO S3C_IPCREG(0x3FC) + +/* Bit Definitions + ************************************************************************/ +/* ENABLE/DISABLE CONTROL */ +#define S3C_IPC_ON (1 << 0) +#define S3C_IPC_OFF (0 << 0) + +/* SOFTWARE RESET */ +#define S3C_IPC_SRESET_ENABLE (1 << 0) +#define S3C_IPC_SRESET_MASK (1 << 0) + +/* SHADOW UPDATE ENABLE CONTROL */ +#define S3C_IPC_SHADOW_UPDATE_ENABLE (1 << 0) +#define S3C_IPC_SHADOW_UPDATE_DISABLE (0 << 0) + +/* OPERATION MODE CONTROL */ +#define S3C_IPC_2D_ENABLE (1 << 0) +#define S3C_IPC_2D_DISABLE (0 << 0) +#define S3C_IPC_2D_MASK (1 << 1) + +/* VERTICAL SCALER PIXEL RATE CONTROL */ +#define S3C_IPC_PEL_RATE_SET (0 << 0) + +/* HORIZONTAL ZOOM RATIO */ +#define S3C_IPC_H_RATIO_MASK (0x7fff << 0) +#define S3C_IPC_V_RATIO_MASK (0x7fff << 0) + +/* POST PROCESSING IMAGE BYPASS MODE CONTROL */ +#define S3C_IPC_PP_BYPASS_ENABLE (0 << 0) +#define S3C_IPC_PP_BYPASS_DISABLE (1 << 0) +#define S3C_IPC_PP_BYPASS_MASK (1 << 0) + +/* BRIGHTNESS AND CONTRAST CONTROL */ +#define S3C_IPC_PP_LINE_CONTRAST_MASK (0xff << 0) +#define S3C_IPC_PP_LINE_BRIGTHNESS_MASK (0xffff << 8) + +/*************************************************************************/ +/* Macro part */ +/*************************************************************************/ +#define S3C_IPC_FIELD_ID_SELECTION(x) ((x) << 6) +#define S3C_IPC_FIELD_ID_AUTO_TOGGLING(x) ((x) << 2) +#define S3C_IPC_2D_CTRL(x) ((x) << 1) +#define S3C_IPC_SRC_WIDTH_SET(x) ((x) & 0x7ff << 0) +#define S3C_IPC_SRC_HEIGHT_SET(x) ((x) & 0x3ff << 0) +#define S3C_IPC_DST_WIDTH_SET(x) ((x) & 0x7ff << 0) +#define S3C_IPC_DST_HEIGHT_SET(x) ((x) & 0x3ff << 0) +#define S3C_IPC_PP_SATURATION_SET(x) ((x) & 0xff << 0) +#define S3C_IPC_PP_TH_HNOISE_SET(x) ((x) & 0xff << 8) +#define S3C_IPC_PP_SHARPNESS_SET(x) ((x) & 0x3 << 8) +#define S3C_IPC_PP_BRIGHT_OFFSET_SET(x) ((x) & 0x1ff << 8) +#define S3C_IPC_PP_LINE_CONTRAST(x)\ + (((x) & S3C_IPC_PP_LINE_CONTRAST_MASK) << 0) +#define S3C_IPC_PP_LINE_BRIGHT(x)\ + (((x) & S3C_IPC_PP_LINE_BRIGTHNESS_MASK) << 8) + +#endif /* _REGS_IPC_H */ + diff --git a/arch/arm/plat-s5p/include/plat/regs-mfc.h b/arch/arm/plat-s5p/include/plat/regs-mfc.h new file mode 100644 index 0000000..1cecb53 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-mfc.h @@ -0,0 +1,256 @@ +/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h + * + * Register definition file for Samsung MFC V5.0 Interface (FIMV) driver + * + * Jaeryul Oh, Copyright (c) 2009 Samsung Electronics + * http://www.samsungsemi.com/ + * + * history: + * 2009.09.14 : Delete MFC v4.0 codes & rewrite defintion (Key-Young, Park) + * 2009.10.08 - Apply 9/30 firmware(Key Young, Park) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _REGS_FIMV_H +#define _REGS_FIMV_H + +#if defined(CONFIG_CPU_S5PV210) +#define MFC_REG(x) (x) +#define MFC_START_ADDR MFC_REG(0x0000) +#define MFC_END_ADDR MFC_REG(0xe008 + 4) +#define MFC_REG_SIZE (MFC_END_ADDR - MFC_START_ADDR) +#define MFC_REG_COUNT ((MFC_END_ADDR - MFC_START_ADDR) / 4) + +/*====================================================================================================*/ +/* MFC Core Control Register */ +/*====================================================================================================*/ +#define MFC_SW_RESET MFC_REG(0x0000) /* MFC Software Reset Register */ +#define MFC_RISC_HOST_INT MFC_REG(0x0008) /* RISC to HOST Interrupt Reigser */ + +#define MFC_HOST2RISC_COMMAND MFC_REG(0x0030) /* HOST to RISC Command Register */ +#define MFC_HOST2RISC_ARG1 MFC_REG(0x0034) /* first argument register */ +#define MFC_HOST2RISC_ARG2 MFC_REG(0x0038) /* second argument register */ +#define MFC_HOST2RISC_ARG3 MFC_REG(0x003c) /* third argument register */ +#define MFC_HOST2RISC_ARG4 MFC_REG(0x0040) /* fourth argument register */ + +#define MFC_RISC2HOST_COMMAND MFC_REG(0x0044) /* RISC to HOST Command Register */ +#define MFC_RISC2HOST_ARG1 MFC_REG(0x0048) /* first argument register */ +#define MFC_RISC2HOST_ARG2 MFC_REG(0x004c) /* second argument register */ +#define MFC_RISC2HOST_ARG3 MFC_REG(0x0050) /* third argument register */ +#define MFC_RISC2HOST_ARG4 MFC_REG(0x0054) /* fourth argument register */ + +#define MFC_FW_VERSION MFC_REG(0x0058) /* firmware version register */ +#define MFC_FW_STATUS MFC_REG(0x0080) /* 0: Not ready, 1: Ready */ + + +/*====================================================================================================*/ +/* Memory Controller Register */ +/*====================================================================================================*/ +#define MFC_MC_DRAMBASE_ADDR_A MFC_REG(0x0508) /* Port A DRAM base address */ +#define MFC_MC_DRAMBASE_ADDR_B MFC_REG(0x050c) /* Port B DRAM base address */ +#define MFC_MC_STATUS MFC_REG(0x0510) /* Bus arbiter's status */ + + +/*====================================================================================================*/ +/* Common Address Control */ +/*====================================================================================================*/ +/*----------------------------------------------------------------------------------------------------*/ +/* H264 Decoder Buffer Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_H264DEC_VERT_NB_MV MFC_REG(0x068c) /* Base:35, vertical neighbor motion vector */ +#define MFC_H264DEC_NB_IP MFC_REG(0x0690) /* Base:36, neighbor pixels for intra pred */ +#define MFC_H264DEC_LUMA MFC_REG(0x0700) /* Base:64, Luma0 ~ Luma31 */ +#define MFC_H264DEC_CHROMA MFC_REG(0x0600) /* Base:0, Chroma0 ~ Chroma31 */ +#define MFC_H264DEC_MV MFC_REG(0x0780) /* Base:96, Mv0 ~ Mv31 */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Other Decoder Buffer Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_NB_DCAC MFC_REG(0x068c) /* Base:35, neighbor AC/DC coeff. buffer */ +#define MFC_UPNB_MV MFC_REG(0x0690) /* Base:36, upper neighbor motion vector buffer */ +#define MFC_SUB_ANCHOR_MV MFC_REG(0x0694) /* Base:37, subseq. anchor motion vector buffer */ +#define MFC_OVERLAP_TRANSFORM MFC_REG(0x0698) /* Base:38, overlap transform line buffer */ +#define MFC_STX_PARSER MFC_REG(0x06A8) /* Base:42, syntax parser addr */ +#define MFC_DEC_LUMA MFC_REG(0x0700) /* Base:64, Luma0 ~ Luma5 */ +#define MFC_DEC_CHROMA MFC_REG(0x0600) /* Base:0, Chroma0 ~ Chroma5 */ +#define MFC_BITPLANE1 MFC_REG(0x06A4) /* Base:41, bitplane1 addr */ +#define MFC_BITPLANE2 MFC_REG(0x06A0) /* Base:40, bitplane2 addr */ +#define MFC_BITPLANE3 MFC_REG(0x069C) /* Base:39, bitplane3 addr */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Encoder Buffer Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_UPPER_MV_ADDR MFC_REG(0x0600) /* Base:0, upper motion vector addr */ +#define MFC_DIRECT_COLZERO_FLAG_ADDR MFC_REG(0x0610) /* Base:4, direct cozero flag addr */ +#define MFC_UPPER_INTRA_MD_ADDR MFC_REG(0x0608) /* Base:2, upper intra MD addr */ +#define MFC_UPPER_INTRA_PRED_ADDR MFC_REG(0x0740) /* Base:80, upper intra PRED addr */ +#define MFC_NBOR_INFO_MPENC_ADDR MFC_REG(0x0604) /* Base:1, entropy engine's AC/DC coeff. */ +#define MFC_ACDC_COEF_BASE_ADDR MFC_REG(0x0604) /* Base:1, entropy engine's AC/DC coeff. */ +#define MFC_ENC_DPB_Y0_ADDR MFC_REG(0x061C) /* Base:7, ref0 Luma addr */ +#define MFC_ENC_DPB_C0_ADDR MFC_REG(0x0700) /* Base:64, ref0 Chroma addr */ +#define MFC_ENC_DPB_Y1_ADDR MFC_REG(0x0620) /* Base:8, ref1 Luma addr */ +#define MFC_ENC_DPB_C1_ADDR MFC_REG(0x0704) /* Base:65, ref1 Chroma addr */ +#define MFC_ENC_DPB_Y2_ADDR MFC_REG(0x0710) /* Base:68, ref2 Luma addr */ +#define MFC_ENC_DPB_C2_ADDR MFC_REG(0x0708) /* Base:66, ref2 Chroma addr */ +#define MFC_ENC_DPB_Y3_ADDR MFC_REG(0x0714) /* Base:69, ref3 Luma addr */ +#define MFC_ENC_DPB_C3_ADDR MFC_REG(0x070c) /* Base:67, ref3 Chroma addr */ + + +/*====================================================================================================*/ +/* Channel & Stream Interface Register */ +/*====================================================================================================*/ +#define MFC_HSIZE_PX MFC_REG(0x0818) /* frame width at encoder */ +#define MFC_VSIZE_PX MFC_REG(0x081c) /* frame height at encoder */ +#define MFC_PROFILE MFC_REG(0x0830) /* profile register */ +#define MFC_PICTURE_STRUCT MFC_REG(0x083c) /* picture field/frame flag */ +#define MFC_LF_CONTROL MFC_REG(0x0848) /* loop filter control */ +#define MFC_LF_ALPHA_OFF MFC_REG(0x084c) /* H.264 loop filter alpha offset */ +#define MFC_LF_BETA_OFF MFC_REG(0x0850) /* H.264 loop filter beta offset */ +#define MFC_QP_OFFSET MFC_REG(0x0c30) /* QP information offset from the DPB address */ +#define MFC_QP_OUT_EN MFC_REG(0x0c34) /* QP infomration enable at decoder */ + + +/*====================================================================================================*/ +/* Channel & Stream Interface Register */ +/*====================================================================================================*/ +#define MFC_SI_RTN_CHID MFC_REG(0x2000) /* Return CH instance ID register */ +#define MFC_SI_CH0_INST_ID MFC_REG(0x2040) /* CH0 instance ID and control register */ +#define MFC_SI_CH1_INST_ID MFC_REG(0x2080) /* CH1 instance ID and control register */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Decoder Channel and Stream Interface Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_SI_VER_RESOL MFC_REG(0x2004) /* vertical resolution of decoder */ +#define MFC_SI_HOR_RESOL MFC_REG(0x2008) /* horizontal resolution of decoder */ +#define MFC_SI_MIN_NUM_DPB MFC_REG(0x200c) /* number of frames in the decoded pic */ +#define MFC_SI_DISPLAY_Y_ADR MFC_REG(0x2010) /* luma address of displayed pic */ +#define MFC_SI_DISPLAY_C_ADR MFC_REG(0x2014) /* chroma address of displayed pic */ +#define MFC_SI_DEC_FRM_SIZE MFC_REG(0x2018) /* consumed number of bytes to decode a frame */ +#define MFC_SI_DISPLAY_STATUS MFC_REG(0x201c) /* status of displayed picture */ +#define MFC_SI_FRAME_TYPE MFC_REG(0x2020) /* frame type such as skip/I/P/B */ +#define MFC_SI_DECODE_Y_ADR MFC_REG(0x2024) /* luma address of decoded pic */ +#define MFC_SI_DECODE_C_ADR MFC_REG(0x2028) /* chroma address of decoded pic */ +#define MFC_SI_DECODE_STATUS MFC_REG(0x202c) /* status of decoded picture */ + +#define MFC_SI_CH0_ES_ADDR MFC_REG(0x2044) /* start addr of stream buf */ +#define MFC_SI_CH0_ES_DEC_UNIT_SIZE MFC_REG(0x2048) /* size of stream buf */ +#define MFC_SI_CH0_DESC_ADDR MFC_REG(0x204c) /* addr of descriptor buf */ +#define MFC_SI_CH0_FIMV1_VRESOL MFC_REG(0x2050) /* horizontal resolution */ +#define MFC_SI_CH0_FIMV1_HRESOL MFC_REG(0x2054) /* vertical resolution */ +#define MFC_SI_CH0_CPB_SIZE MFC_REG(0x2058) /* max size of coded pic. buf */ +#define MFC_SI_CH0_DESC_SIZE MFC_REG(0x205c) /* max size of descriptor buf */ +#define MFC_SI_CH0_RELEASE_BUFFER MFC_REG(0x2060) /* specifices the availability of each DPB */ +#define MFC_SI_CH0_HOST_WR_ADR MFC_REG(0x2064) /* start addr of shared memory */ +#define MFC_SI_CH0_DPB_CONFIG_CTRL MFC_REG(0x2068) /* DPB configuarion control */ +#define MFC_SI_CH0_CMD_SEQ_NUM MFC_REG(0x206c) /* Command sequence number from the host */ + +#define MFC_SI_CH1_ES_ADDR MFC_REG(0x2084) /* start addr of stream buf */ +#define MFC_SI_CH1_ES_DEC_UNIT_SIZE MFC_REG(0x2088) /* size of stream buf */ +#define MFC_SI_CH1_DESC_ADDR MFC_REG(0x208c) /* addr of descriptor buf */ +#define MFC_SI_CH1_FIMV1_VRESOL MFC_REG(0x2090) /* horizontal resolution */ +#define MFC_SI_CH1_FIMV1_HRESOL MFC_REG(0x2094) /* vertical resolution */ +#define MFC_SI_CH1_CPB_SIZE MFC_REG(0x2098) /* max size of coded pic. buf */ +#define MFC_SI_CH1_DESC_SIZE MFC_REG(0x209c) /* max size of descriptor buf */ +#define MFC_SI_CH1_RELEASE_BUFFER MFC_REG(0x20a0) /* specifices the availability of each DPB */ +#define MFC_SI_CH1_HOST_WR_ADR MFC_REG(0x20a4) /* start addr of shared memory */ +#define MFC_SI_CH1_DPB_CONFIG_CTRL MFC_REG(0x20a8) /* DPB configuarion control */ +#define MFC_SI_CH1_CMD_SEQ_NUM MFC_REG(0x20ac) /* Command sequence number from the host */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Encoder Channel and Stream Interface Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_CRC_LUMA0 MFC_REG(0x2030) /* luma crc data per frame(or top field) */ +#define MFC_CRC_CHROMA0 MFC_REG(0x2034) /* chroma crc data per frame(or top field) */ +#define MFC_CRC_LUMA1 MFC_REG(0x2038) /* luma crc data per bottom field */ +#define MFC_CRC_CHROMA1 MFC_REG(0x203c) /* chroma crc data per bottom field */ + +#define MFC_SI_ENC_STREAM_SIZE MFC_REG(0x2004) /* stream size */ +#define MFC_SI_ENC_PICTURE_CNT MFC_REG(0x2008) /* picture count */ +#define MFC_SI_WRITE_POINTER MFC_REG(0x200c) /* stream buffer write pointer */ +#define MFC_SI_ENC_SLICE_TYPE MFC_REG(0x2010) /* slice type(I/P/B/IDR) */ +#define MFC_SI_ENCODED_Y_ADDR MFC_REG(0x2014) /* address of the encoded luminance picture */ +#define MFC_SI_ENCODED_C_ADDR MFC_REG(0x2018) /* address of the encoded chroma address */ + +#define MFC_SI_CH0_SB_U_ADDR MFC_REG(0x2044) /* addr of upper stream buf */ +#define MFC_SI_CH0_SB_L_ADDR MFC_REG(0x2048) /* addr of lower stream buf */ +#define MFC_SI_CH0_BUFFER_SIZE MFC_REG(0x204c) /* size of stream buf */ +#define MFC_SI_CH0_CURRENT_Y_ADDR MFC_REG(0x2050) /* current Luma addr */ +#define MFC_SI_CH0_CURRENT_C_ADDR MFC_REG(0x2054) /* current Chroma addr */ +#define MFC_SI_CH0_ENC_PARA MFC_REG(0x2058) /* frame insertion control register */ + +#define MFC_SI_CH1_SB_U_ADDR MFC_REG(0x2084) /* addr of upper stream buf */ +#define MFC_SI_CH1_SB_L_ADDR MFC_REG(0x2088) /* addr of lower stream buf */ +#define MFC_SI_CH1_BUFFER_SIZE MFC_REG(0x208c) /* size of stream buf */ +#define MFC_SI_CH1_CURRENT_Y_ADDR MFC_REG(0x2090) /* current Luma addr */ +#define MFC_SI_CH1_CURRENT_C_ADDR MFC_REG(0x2094) /* current Chroma addr */ +#define MFC_SI_CH1_ENC_PARA MFC_REG(0x2098) /* frame insertion control register */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Encoded Data Formatter Unit Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_STR_BF_U_FULL MFC_REG(0xc004) /* upper stream buf full status */ +#define MFC_STR_BF_U_EMPTY MFC_REG(0xc008) /* upper stream buf empty status */ +#define MFC_STR_BF_L_FULL MFC_REG(0xc00c) /* lower stream buf full status */ +#define MFC_STR_BF_L_EMPTY MFC_REG(0xc010) /* lower stream buf empty status */ +#define MFC_STR_BF_STATUS MFC_REG(0xc018) /* stream buf interrupt status */ +#define MFC_EDFU_SF_EPB_ON_CTRL MFC_REG(0xc054) /* EDFU stream control */ +#define MFC_EDFU_SF_BUF_CTRL MFC_REG(0xc058) /* EDFU buffer control */ +#define MFC_STR_BF_MODE_CTRL MFC_REG(0xc05c) /* stream buffer mode control */ + + +/*====================================================================================================*/ +/* Encoding Registers */ +/*====================================================================================================*/ +/*----------------------------------------------------------------------------------------------------*/ +/* Common Encoder Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_RC_CONTROL_CONFIG MFC_REG(0x00a0) /* Rate Control Configuration */ +#define MFC_ENC_PIC_TYPE_CTRL MFC_REG(0xc504) /* pic type level control */ +#define MFC_ENC_B_RECON_WRITE_ON MFC_REG(0xc508) /* B frame recon data write cotrl */ +#define MFC_ENC_MSLICE_CTRL MFC_REG(0xc50c) /* multi slice control */ +#define MFC_ENC_MSLICE_MB MFC_REG(0xc510) /* MB number in the one slice */ +#define MFC_ENC_MSLICE_BYTE MFC_REG(0xc514) /* byte count number for one slice */ +#define MFC_ENC_CIR_CTRL MFC_REG(0xc518) /* number of intra refresh MB */ +#define MFC_ENC_MAP_FOR_CUR MFC_REG(0xc51c) /* linear or 64x32 tiled mode */ +#define MFC_ENC_PADDING_CTRL MFC_REG(0xc520) /* padding control */ +#define MFC_ENC_INT_MASK MFC_REG(0xc528) /* interrupt mask */ +#define MFC_ENC_COMMON_INTRA_BIAS MFC_REG(0xc528) /* intra mode bias register */ +#define MFC_ENC_COMMON_BI_DIRECT_BIAS MFC_REG(0xc528) /* bi-directional mode bias register */ + +/*----------------------------------------------------------------------------------------------------*/ +/* Rate Control Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_RC_CONFIG MFC_REG(0xc5a0) /* RC config */ +#define MFC_RC_FRAME_RATE MFC_REG(0xc5a4) /* frame rate */ +#define MFC_RC_BIT_RATE MFC_REG(0xc5a8) /* bit rate */ +#define MFC_RC_QBOUND MFC_REG(0xc5ac) /* max/min QP */ +#define MFC_RC_RPARA MFC_REG(0xc5b0) /* rate control reaction coeff. */ +#define MFC_RC_MB_CTRL MFC_REG(0xc5b4) /* MB adaptive scaling */ + +/*----------------------------------------------------------------------------------------------------*/ +/* H.264 Encoder Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_H264_ENC_ENTRP_MODE MFC_REG(0xd004) /* CAVLC or CABAC */ +#define MFC_H264_ENC_NUM_OF_REF MFC_REG(0xd010) /* number of reference for P/B */ +#define MFC_H264_ENC_MDINTER_WEIGHT MFC_REG(0xd01c) /* inter weighted parameter */ +#define MFC_H264_ENC_MDINTRA_WEIGHT MFC_REG(0xd020) /* intra weighted parameter */ +#define MFC_H264_ENC_TRANS_8X8_FLAG MFC_REG(0xd034) /* 8x8 transform flag in PPS & high profile */ + +/*----------------------------------------------------------------------------------------------------*/ +/* MPEG4 Encoder Register */ +/*----------------------------------------------------------------------------------------------------*/ +#define MFC_MPEG4_ENC_QUART_PXL MFC_REG(0xe008) /* quarter pel interpolation control */ + + +/*====================================================================================================*/ +/* Etc Registers */ +/*====================================================================================================*/ +#define MFC_NUM_MASTER MFC_REG(0x0b14) /* Number of master port */ + +//#define MFC_SI_DEC_FRM_SIZE MFC_REG(0x2018) +#endif /* CONFIG_CPU_S5PC1xx */ + +#endif diff --git a/arch/arm/plat-s5p/include/plat/regs-systimer.h b/arch/arm/plat-s5p/include/plat/regs-systimer.h new file mode 100644 index 0000000..7091c40 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-systimer.h @@ -0,0 +1,77 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-systimer.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P System Timer Driver Header information + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_REGS_SYSTIMER_H +#define __ASM_PLAT_REGS_SYSTIMER_H __FILE__ + +#define S5P_SYSTIMERREG(x) (S5P_VA_SYSTIMER + (x)) + +#define S5P_SYSTIMER_TCFG S5P_SYSTIMERREG(0x00) +#define S5P_SYSTIMER_TCON S5P_SYSTIMERREG(0x04) +#define S5P_SYSTIMER_TICNTB S5P_SYSTIMERREG(0x08) +#define S5P_SYSTIMER_TICNTO S5P_SYSTIMERREG(0x0c) +#define S5P_SYSTIMER_TFCNTB S5P_SYSTIMERREG(0x10) +#define S5P_SYSTIMER_ICNTB S5P_SYSTIMERREG(0x18) +#define S5P_SYSTIMER_ICNTO S5P_SYSTIMERREG(0x1c) +#define S5P_SYSTIMER_INT_CSTAT S5P_SYSTIMERREG(0x20) + +/* Value for TCFG */ + +#define S5P_SYSTIMER_SWRST (1<<16) + +#define S5P_SYSTIMER_DIV_GEN (0<<15) +#define S5P_SYSTIMER_DIV_RTC (1<<15) + +#define S5P_SYSTIMER_TICK_INT (0<<14) +#define S5P_SYSTIMER_TICK_FRA (1<<14) + +#define S5P_SYSTIMER_TCLK_MASK (3<<12) +#define S5P_SYSTIMER_TCLK_XXTI (0<<12) +#define S5P_SYSTIMER_TCLK_RTC (1<<12) +#define S5P_SYSTIMER_TCLK_USB (2<<12) +#define S5P_SYSTIMER_TCLK_PCLK (3<<12) + +#define S5P_SYSTIMER_DIV_MASK (7<<8) +#define S5P_SYSTIMER_DIV_1 (0<<8) +#define S5P_SYSTIMER_DIV_2 (1<<8) +#define S5P_SYSTIMER_DIV_4 (2<<8) +#define S5P_SYSTIMER_DIV_8 (3<<8) +#define S5P_SYSTIMER_DIV_16 (4<<8) + +#define S5P_SYSTIMER_TARGET_HZ 200 +#define S5P_SYSTIMER_PRESCALER 5 +#define S5P_SYSTIMER_PRESCALER_MASK (0x3f<<0) + +/* value for TCON */ + +#define S5P_SYSTIMER_INT_AUTO (1<<5) +#define S5P_SYSTIMER_INT_IMM (1<<4) +#define S5P_SYSTIMER_INT_START (1<<3) +#define S5P_SYSTIMER_AUTO_RELOAD (1<<2) +#define S5P_SYSTIMER_IMM_UPDATE (1<<1) +#define S5P_SYSTIMER_START (1<<0) + +/* Value for INT_CSTAT */ + +#define S5P_SYSTIMER_INT_TWIE (1<<10) +#define S5P_SYSTIMER_INT_IWIE (1<<9) +#define S5P_SYSTIMER_INT_TFWIE (1<<8) +#define S5P_SYSTIMER_INT_TIWIE (1<<7) +#define S5P_SYSTIMER_INT_ICNTEIE (1<<6) +#define S5P_SYSTIMER_INT_TCON (1<<5) +#define S5P_SYSTIMER_INT_ICNTB (1<<4) +#define S5P_SYSTIMER_INT_TFCNTB (1<<3) +#define S5P_SYSTIMER_INT_TICNTB (1<<2) +#define S5P_SYSTIMER_INT_INTCNT (1<<1) +#define S5P_SYSTIMER_INT_INTENABLE (1<<0) + +#endif /* __ASM_PLAT_REGS_SYSTIMER_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5p-otghost.h b/arch/arm/plat-s5p/include/plat/s5p-otghost.h new file mode 100644 index 0000000..a466c93 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p-otghost.h @@ -0,0 +1,56 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5p-otghost.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Platform header file for Samsung OTG Host driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef _PLAT_S5P_OTGHOST_H +#define _PLAT_S5P_OTGHOST_H __FILE__ + +#include <linux/wakelock.h> + +/*#define CONFIG_USB_S3C_OTG_HOST_HANDLING_CLOCK*/ +#define CONFIG_USB_S3C_OTG_HOST_DTGDRVVBUS + +union port_flags_t { + /** raw register data */ + u32 d32; + /** register bits */ + struct { + unsigned port_connect_status_change:1; + unsigned port_connect_status:1; + unsigned port_reset_change:1; + unsigned port_enable_change:1; + unsigned port_suspend_change:1; + unsigned port_over_current_change:1; + unsigned reserved:26; + } b; +}; + +struct sec_otghost_data { + bool clk_usage; + void (*set_pwr_cb)(int on); + int host_notify; + int sec_whlist_table_num; +}; + +struct sec_otghost { + spinlock_t lock; + + bool ch_halt; + bool is_hs; + union port_flags_t port_flag; + struct wake_lock wake_lock; + + struct work_struct work; + struct workqueue_struct *wq; + + struct sec_otghost_data *otg_data; +}; + +#endif /*_PLAT_S5P_OTGHOST_H */ diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h index f307f34..9e0a095 100644 --- a/arch/arm/plat-s5p/include/plat/system-reset.h +++ b/arch/arm/plat-s5p/include/plat/system-reset.h @@ -12,20 +12,6 @@ * published by the Free Software Foundation. */ -#include <plat/watchdog-reset.h> +extern void (*s5p_reset_hook)(void); -void (*s5p_reset_hook)(void); - -static void arch_reset(char mode, const char *cmd) -{ - /* SWRESET support in s5p_reset_hook() */ - - if (s5p_reset_hook) - s5p_reset_hook(); - - /* Perform reset using Watchdog reset - * if there is no s5p_reset_hook() - */ - - arch_wdt_reset(); -} +void arch_reset(char mode, const char *cmd); diff --git a/arch/arm/plat-s5p/irq-eint-group.c b/arch/arm/plat-s5p/irq-eint-group.c new file mode 100644 index 0000000..0fe4d5a --- /dev/null +++ b/arch/arm/plat-s5p/irq-eint-group.c @@ -0,0 +1,605 @@ +/* linux/arch/arm/mach-s5pv210/irq-eint-group.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - IRQ EINT Group support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <plat/regs-irqtype.h> + +#include <mach/map.h> +#include <plat/cpu.h> + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> +#include <plat/irq-eint-group.h> +#include <mach/regs-gpio.h> + +#define S5PV210_EINT_MAX_SOURCES 8 + +static DEFINE_SPINLOCK(eint_group_lock); + +struct s5pv210_eint_group_t { + int sources; + int base; + void __iomem *cont_reg; + void __iomem *mask_reg; + void __iomem *pend_reg; + int mask_ofs; + int pend_ofs; + unsigned int int_con; + unsigned int int_mask; + + /* start offset in control register for each source */ + int cont_map[S5PV210_EINT_MAX_SOURCES]; +}; + +static struct s5pv210_eint_group_t eint_groups[] = { + [0] = { + .sources = 0, + .base = 0, + .cont_reg = 0x0, + .mask_reg = 0x0, + .pend_reg = 0x0, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + -1, -1, -1, -1, -1, -1, -1, -1, + }, + }, + [1] = { + .sources = IRQ_EINT_GROUP1_NR, + .base = IRQ_EINT_GROUP1_BASE, + .cont_reg = S5PV210_GPA0_INT_CON, + .mask_reg = S5PV210_GPA0_INT_MASK, + .pend_reg = S5PV210_GPA0_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [2] = { + .sources = IRQ_EINT_GROUP2_NR, + .base = IRQ_EINT_GROUP2_BASE, + .cont_reg = S5PV210_GPA1_INT_CON, + .mask_reg = S5PV210_GPA1_INT_MASK, + .pend_reg = S5PV210_GPA1_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, -1, -1, -1, -1, + }, + }, + [3] = { + .sources = IRQ_EINT_GROUP3_NR, + .base = IRQ_EINT_GROUP3_BASE, + .cont_reg = S5PV210_GPB_INT_CON, + .mask_reg = S5PV210_GPB_INT_MASK, + .pend_reg = S5PV210_GPB_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [4] = { + .sources = IRQ_EINT_GROUP4_NR, + .base = IRQ_EINT_GROUP4_BASE, + .cont_reg = S5PV210_GPC0_INT_CON, + .mask_reg = S5PV210_GPC0_INT_MASK, + .pend_reg = S5PV210_GPC0_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, -1, -1, -1, + }, + }, + [5] = { + .sources = IRQ_EINT_GROUP5_NR, + .base = IRQ_EINT_GROUP5_BASE, + .cont_reg = S5PV210_GPC1_INT_CON, + .mask_reg = S5PV210_GPC1_INT_MASK, + .pend_reg = S5PV210_GPC1_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, -1, -1, -1, + }, + }, + [6] = { + .sources = IRQ_EINT_GROUP6_NR, + .base = IRQ_EINT_GROUP6_BASE, + .cont_reg = S5PV210_GPD0_INT_CON, + .mask_reg = S5PV210_GPD0_INT_MASK, + .pend_reg = S5PV210_GPD0_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, -1, -1, -1, -1, + }, + }, + [7] = { + .sources = IRQ_EINT_GROUP7_NR, + .base = IRQ_EINT_GROUP7_BASE, + .cont_reg = S5PV210_GPD1_INT_CON, + .mask_reg = S5PV210_GPD1_INT_MASK, + .pend_reg = S5PV210_GPD1_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, -1, -1, + }, + }, + [8] = { + .sources = IRQ_EINT_GROUP8_NR, + .base = IRQ_EINT_GROUP8_BASE, + .cont_reg = S5PV210_GPE0_INT_CON, + .mask_reg = S5PV210_GPE0_INT_MASK, + .pend_reg = S5PV210_GPE0_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [9] = { + .sources = IRQ_EINT_GROUP9_NR, + .base = IRQ_EINT_GROUP9_BASE, + .cont_reg = S5PV210_GPE1_INT_CON, + .mask_reg = S5PV210_GPE1_INT_MASK, + .pend_reg = S5PV210_GPE1_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, -1, -1, -1, + }, + }, + [10] = { + .sources = IRQ_EINT_GROUP10_NR, + .base = IRQ_EINT_GROUP10_BASE, + .cont_reg = S5PV210_GPF0_INT_CON, + .mask_reg = S5PV210_GPF0_INT_MASK, + .pend_reg = S5PV210_GPF0_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [11] = { + .sources = IRQ_EINT_GROUP11_NR, + .base = IRQ_EINT_GROUP11_BASE, + .cont_reg = S5PV210_GPF1_INT_CON, + .mask_reg = S5PV210_GPF1_INT_MASK, + .pend_reg = S5PV210_GPF1_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [12] = { + .sources = IRQ_EINT_GROUP12_NR, + .base = IRQ_EINT_GROUP12_BASE, + .cont_reg = S5PV210_GPF2_INT_CON, + .mask_reg = S5PV210_GPF2_INT_MASK, + .pend_reg = S5PV210_GPF2_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [13] = { + .sources = IRQ_EINT_GROUP13_NR, + .base = IRQ_EINT_GROUP13_BASE, + .cont_reg = S5PV210_GPF3_INT_CON, + .mask_reg = S5PV210_GPF3_INT_MASK, + .pend_reg = S5PV210_GPF3_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, -1, -1, + }, + }, + [14] = { + .sources = IRQ_EINT_GROUP14_NR, + .base = IRQ_EINT_GROUP14_BASE, + .cont_reg = S5PV210_GPG0_INT_CON, + .mask_reg = S5PV210_GPG0_INT_MASK, + .pend_reg = S5PV210_GPG0_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, -1, + }, + }, + [15] = { + .sources = IRQ_EINT_GROUP15_NR, + .base = IRQ_EINT_GROUP15_BASE, + .cont_reg = S5PV210_GPG1_INT_CON, + .mask_reg = S5PV210_GPG1_INT_MASK, + .pend_reg = S5PV210_GPG1_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, -1, + }, + }, + [16] = { + .sources = IRQ_EINT_GROUP16_NR, + .base = IRQ_EINT_GROUP16_BASE, + .cont_reg = S5PV210_GPG2_INT_CON, + .mask_reg = S5PV210_GPG2_INT_MASK, + .pend_reg = S5PV210_GPG2_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, -1, + }, + }, + [17] = { + .sources = IRQ_EINT_GROUP17_NR, + .base = IRQ_EINT_GROUP17_BASE, + .cont_reg = S5PV210_GPG3_INT_CON, + .mask_reg = S5PV210_GPG3_INT_MASK, + .pend_reg = S5PV210_GPG3_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, -1, + }, + }, + [18] = { + .sources = IRQ_EINT_GROUP18_NR, + .base = IRQ_EINT_GROUP18_BASE, + .cont_reg = S5PV210_GPJ0_INT_CON, + .mask_reg = S5PV210_GPJ0_INT_MASK, + .pend_reg = S5PV210_GPJ0_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [19] = { + .sources = IRQ_EINT_GROUP19_NR, + .base = IRQ_EINT_GROUP19_BASE, + .cont_reg = S5PV210_GPJ1_INT_CON, + .mask_reg = S5PV210_GPJ1_INT_MASK, + .pend_reg = S5PV210_GPJ1_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, -1, -1, + }, + }, + [20] = { + .sources = IRQ_EINT_GROUP20_NR, + .base = IRQ_EINT_GROUP20_BASE, + .cont_reg = S5PV210_GPJ2_INT_CON, + .mask_reg = S5PV210_GPJ2_INT_MASK, + .pend_reg = S5PV210_GPJ2_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [21] = { + .sources = IRQ_EINT_GROUP21_NR, + .base = IRQ_EINT_GROUP21_BASE, + .cont_reg = S5PV210_GPJ3_INT_CON, + .mask_reg = S5PV210_GPJ3_INT_MASK, + .pend_reg = S5PV210_GPJ3_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, 20, 24, 28, + }, + }, + [22] = { + .sources = IRQ_EINT_GROUP22_NR, + .base = IRQ_EINT_GROUP22_BASE, + .cont_reg = S5PV210_GPJ4_INT_CON, + .mask_reg = S5PV210_GPJ4_INT_MASK, + .pend_reg = S5PV210_GPJ4_INT_PEND, + .mask_ofs = 0, + .pend_ofs = 0, + .int_con = 0x0, + .int_mask = 0xff, + .cont_map = { + 0, 4, 8, 12, 16, -1, -1, -1, + }, + }, +}; + +#define S5PV210_EINT_GROUPS (sizeof(eint_groups) / sizeof(eint_groups[0])) + +static int to_group_number(unsigned int irq) +{ + int grp, found; + + for (grp = 1; grp < S5PV210_EINT_GROUPS; grp++) { + if (irq >= eint_groups[grp].base + eint_groups[grp].sources) + continue; + else { + found = 1; + break; + } + } + + if (!found) { + printk(KERN_ERR "failed to find out the eint group number\n"); + grp = 0; + } + + return grp; +} + +static inline int to_irq_number(int grp, unsigned int irq) +{ + return irq - eint_groups[grp].base; +} + +static inline int to_bit_offset(int grp, unsigned int irq) +{ + int offset; + + offset = eint_groups[grp].cont_map[to_irq_number(grp, irq)]; + + if (offset == -1) { + printk(KERN_ERR "invalid bit offset\n"); + offset = 0; + } + + return offset; +} + +static inline void s5pv210_irq_eint_group_mask(struct irq_data *d) +{ + struct s5pv210_eint_group_t *group; + unsigned long flags; + int grp; + + grp = to_group_number(d->irq); + group = &eint_groups[grp]; + spin_lock_irqsave(&eint_group_lock, flags); + eint_groups[grp].int_mask |= + (1 << (group->mask_ofs + to_irq_number(grp, d->irq))); + + writel(eint_groups[grp].int_mask, group->mask_reg); + spin_unlock_irqrestore(&eint_group_lock, flags); +} + +static inline void s5pv210_irq_eint_group_ack(struct irq_data *d) +{ + struct s5pv210_eint_group_t *group; + unsigned long flags; + int grp; + u32 pend; + + grp = to_group_number(d->irq); + group = &eint_groups[grp]; + + spin_lock_irqsave(&eint_group_lock, flags); + pend = (1 << (group->pend_ofs + to_irq_number(grp, d->irq))); + + writel(pend, group->pend_reg); + spin_unlock_irqrestore(&eint_group_lock, flags); +} + +static void s5pv210_irq_eint_group_unmask(struct irq_data *d) +{ + struct s5pv210_eint_group_t *group; + unsigned long flags; + int grp; + + grp = to_group_number(d->irq); + group = &eint_groups[grp]; + + /* for level triggered interrupts, masking doesn't prevent + * the interrupt from becoming pending again. by the time + * the handler (either irq or thread) can do its thing to clear + * the interrupt, it's too late because it could be pending + * already. we have to ack it here, after the handler runs, + * or else we get a false interrupt. + */ + if (irqd_is_level_type(d)) + s5pv210_irq_eint_group_ack(d); + + spin_lock_irqsave(&eint_group_lock, flags); + eint_groups[grp].int_mask &= + ~(1 << (group->mask_ofs + to_irq_number(grp, d->irq))); + + writel(eint_groups[grp].int_mask, group->mask_reg); + spin_unlock_irqrestore(&eint_group_lock, flags); +} + +static void s5pv210_irq_eint_group_maskack(struct irq_data *d) +{ + /* compiler should in-line these */ + s5pv210_irq_eint_group_mask(d); + s5pv210_irq_eint_group_ack(d); +} + +static int s5pv210_irq_eint_group_set_type(struct irq_data *d, + unsigned int type) +{ + struct s5pv210_eint_group_t *group; + unsigned long flags; + int grp, shift; + u32 mask, newvalue = 0; + + grp = to_group_number(d->irq); + group = &eint_groups[grp]; + + switch (type) { + case IRQ_TYPE_NONE: + printk(KERN_WARNING "No edge setting!\n"); + break; + + case IRQ_TYPE_EDGE_RISING: + newvalue = S5P_IRQ_TYPE_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_FALLING: + newvalue = S5P_IRQ_TYPE_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_BOTH: + newvalue = S5P_IRQ_TYPE_EDGE_BOTH; + break; + + case IRQ_TYPE_LEVEL_LOW: + newvalue = S5P_IRQ_TYPE_LEVEL_LOW; + break; + + case IRQ_TYPE_LEVEL_HIGH: + newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; + break; + + default: + printk(KERN_ERR "No such irq type %d", type); + return -1; + } + + shift = to_bit_offset(grp, d->irq); + mask = 0x7 << shift; + + spin_lock_irqsave(&eint_group_lock, flags); + eint_groups[grp].int_con &= ~mask; + eint_groups[grp].int_con |= newvalue << shift; + writel(eint_groups[grp].int_con, group->cont_reg); + spin_unlock_irqrestore(&eint_group_lock, flags); + + return 0; +} + +static struct irq_chip s5pv210_irq_eint_group = { + .name = "s5pv210-eint-group", + .irq_mask = s5pv210_irq_eint_group_mask, + .irq_unmask = s5pv210_irq_eint_group_unmask, + .irq_mask_ack = s5pv210_irq_eint_group_maskack, + .irq_ack = s5pv210_irq_eint_group_ack, + .irq_set_type = s5pv210_irq_eint_group_set_type, +}; + +/* + * s5p_irq_demux_eint_group +*/ +static inline void s5pv210_irq_demux_eint_group(unsigned int irq, + struct irq_desc *desc) +{ + struct s5pv210_eint_group_t *group; + u32 status, newirq; + int grp, src; + + for (grp = 1; grp < S5PV210_EINT_GROUPS; grp++) { + group = &eint_groups[grp]; + status = __raw_readl(group->pend_reg); + + status &= ~eint_groups[grp].int_mask; + status >>= group->pend_ofs; + status &= 0xff; /* MAX IRQ in a group is 8 */ + + if (!status) + continue; + + for (src = 0; src < S5PV210_EINT_MAX_SOURCES; src++) { + if (status & 1) { + newirq = group->base + src; + generic_handle_irq(newirq); + } + + status >>= 1; + } + } +} + +void s5pv210_restore_eint_group(void) +{ + struct s5pv210_eint_group_t *group; + unsigned long flags; + int grp; + + spin_lock_irqsave(&eint_group_lock, flags); + for (grp = 1; grp < S5PV210_EINT_GROUPS; grp++) { + group = &eint_groups[grp]; + writel(eint_groups[grp].int_con, group->cont_reg); + writel(eint_groups[grp].int_mask, group->mask_reg); + } + spin_unlock_irqrestore(&eint_group_lock, flags); +} + +int __init s5pv210_init_irq_eint_group(void) +{ + int irq; + + for (irq = IRQ_EINT_GROUP_BASE; irq < NR_IRQS; irq++) { + irq_set_chip(irq, &s5pv210_irq_eint_group); + irq_set_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + irq_set_chained_handler(IRQ_GPIOINT, s5pv210_irq_demux_eint_group); + + return 0; +} + +arch_initcall(s5pv210_init_irq_eint_group); diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index b5bb774..8380951 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c @@ -37,21 +37,31 @@ static inline void s5p_irq_eint_mask(struct irq_data *data) __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); } +static inline void s5p_irq_eint_ack(struct irq_data *data) +{ + __raw_writel(eint_irq_to_bit(data->irq), + S5P_EINT_PEND(EINT_REG_NR(data->irq))); +} + static void s5p_irq_eint_unmask(struct irq_data *data) { u32 mask; + /* for level triggered interrupts, masking doesn't prevent + * the interrupt from becoming pending again. by the time + * the handler (either irq or thread) can do its thing to clear + * the interrupt, it's too late because it could be pending + * already. we have to ack it here, after the handler runs, + * or else we get a false interrupt. + */ + if (irqd_is_level_type(data)) + s5p_irq_eint_ack(data); + mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); mask &= ~(eint_irq_to_bit(data->irq)); __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); } -static inline void s5p_irq_eint_ack(struct irq_data *data) -{ - __raw_writel(eint_irq_to_bit(data->irq), - S5P_EINT_PEND(EINT_REG_NR(data->irq))); -} - static void s5p_irq_eint_maskack(struct irq_data *data) { /* compiler should in-line these */ @@ -65,6 +75,7 @@ static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type) int shift; u32 ctrl, mask; u32 newvalue = 0; + struct irq_desc *desc = irq_to_desc(data->irq); switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -115,6 +126,11 @@ static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type) else printk(KERN_ERR "No such irq number %d", offs); + if (type & IRQ_TYPE_EDGE_BOTH) + desc->handle_irq = handle_edge_irq; + else + desc->handle_irq = handle_level_irq; + return 0; } diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c index 327acb3..d957398 100644 --- a/arch/arm/plat-s5p/irq-pm.c +++ b/arch/arm/plat-s5p/irq-pm.c @@ -21,6 +21,7 @@ #include <plat/irqs.h> #include <plat/pm.h> #include <mach/map.h> +#include <plat/irq-pm.h> #include <mach/regs-gpio.h> #include <mach/regs-irq.h> @@ -41,17 +42,49 @@ int s3c_irq_wake(struct irq_data *data, unsigned int state) unsigned long irqbit; switch (data->irq) { - case IRQ_RTC_TIC: case IRQ_RTC_ALARM: - irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM); - if (!state) - s3c_irqwake_intmask |= irqbit; - else - s3c_irqwake_intmask &= ~irqbit; + irqbit = 1 << 1; + break; + case IRQ_RTC_TIC: + irqbit = 1 << 2; + break; + case IRQ_ADC: + irqbit = 1 << 3; + break; + case IRQ_ADC1: + irqbit = 1 << 4; + break; + case IRQ_KEYPAD: + irqbit = 1 << 5; + break; + case IRQ_HSMMC0: + irqbit = 1 << 9; + break; + case IRQ_HSMMC1: + irqbit = 1 << 10; + break; + case IRQ_HSMMC2: + irqbit = 1 << 11; + break; + case IRQ_HSMMC3: + irqbit = 1 << 12; + break; + case IRQ_I2S0: + irqbit = 1 << 13; + break; + case IRQ_SYSTIMER: + irqbit = 1 << 14; + break; + case IRQ_CEC: + irqbit = 1 << 15; break; default: return -ENOENT; } + if (!state) + s3c_irqwake_intmask |= irqbit; + else + s3c_irqwake_intmask &= ~irqbit; return 0; } @@ -61,19 +94,19 @@ static struct sleep_save eint_save[] = { SAVE_ITEM(S5P_EINT_CON(2)), SAVE_ITEM(S5P_EINT_CON(3)), - SAVE_ITEM(S5P_EINT_FLTCON(0)), - SAVE_ITEM(S5P_EINT_FLTCON(1)), - SAVE_ITEM(S5P_EINT_FLTCON(2)), - SAVE_ITEM(S5P_EINT_FLTCON(3)), - SAVE_ITEM(S5P_EINT_FLTCON(4)), - SAVE_ITEM(S5P_EINT_FLTCON(5)), - SAVE_ITEM(S5P_EINT_FLTCON(6)), - SAVE_ITEM(S5P_EINT_FLTCON(7)), - SAVE_ITEM(S5P_EINT_MASK(0)), SAVE_ITEM(S5P_EINT_MASK(1)), SAVE_ITEM(S5P_EINT_MASK(2)), SAVE_ITEM(S5P_EINT_MASK(3)), + + SAVE_ITEM(S5P_EINT_FLTCON(0,0)), + SAVE_ITEM(S5P_EINT_FLTCON(0,1)), + SAVE_ITEM(S5P_EINT_FLTCON(1,0)), + SAVE_ITEM(S5P_EINT_FLTCON(1,1)), + SAVE_ITEM(S5P_EINT_FLTCON(2,0)), + SAVE_ITEM(S5P_EINT_FLTCON(2,1)), + SAVE_ITEM(S5P_EINT_FLTCON(3,0)), + SAVE_ITEM(S5P_EINT_FLTCON(3,1)), }; int s3c24xx_irq_suspend(void) diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c index a97c089..c4b561c 100644 --- a/arch/arm/plat-s5p/irq.c +++ b/arch/arm/plat-s5p/irq.c @@ -24,6 +24,23 @@ #include <plat/cpu.h> #include <plat/irq-vic-timer.h> #include <plat/irq-uart.h> +#include <plat/irq-pm.h> + +/* Wakeup source */ +static int wakeup_source[] = { + IRQ_RTC_ALARM, + IRQ_RTC_TIC, + IRQ_ADC, + IRQ_ADC1, + IRQ_KEYPAD, + IRQ_HSMMC0, + IRQ_HSMMC1, + IRQ_HSMMC2, + IRQ_HSMMC3, + IRQ_I2S0, + IRQ_SYSTIMER, + IRQ_CEC +}; /* * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] @@ -56,9 +73,10 @@ static struct s3c_uart_irq uart_irqs[] = { void __init s5p_init_irq(u32 *vic, u32 num_vic) { -#ifdef CONFIG_ARM_VIC + struct irq_chip *chip; int irq; +#ifdef CONFIG_ARM_VIC /* initialize the VICs */ for (irq = 0; irq < num_vic; irq++) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); @@ -67,4 +85,10 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) s3c_init_vic_timer_irq(5, IRQ_TIMER0); s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); + + /* Register wakeup source. */ + for (irq = 0; irq < ARRAY_SIZE(wakeup_source); irq++) { + chip = irq_get_chip(wakeup_source[irq]); + chip->irq_set_wake = s3c_irq_wake; + } } diff --git a/arch/arm/plat-s5p/reset.c b/arch/arm/plat-s5p/reset.c new file mode 100644 index 0000000..96dfdab --- /dev/null +++ b/arch/arm/plat-s5p/reset.c @@ -0,0 +1,33 @@ +/* linux/arch/arm/plat-s5p/include/plat/system-reset.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h + * + * S5P - System define for arch_reset() + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <plat/system-reset.h> +#include <plat/watchdog-reset.h> + + +void (*s5p_reset_hook)(void); + +void arch_reset(char mode, const char *cmd) +{ + /* SWRESET support in s5p_reset_hook() */ + + if (s5p_reset_hook) + s5p_reset_hook(); + + /* Perform reset using Watchdog reset + * if there is no s5p_reset_hook() + */ + + arch_wdt_reset(); +} diff --git a/arch/arm/plat-s5p/setup-mfc.c b/arch/arm/plat-s5p/setup-mfc.c new file mode 100644 index 0000000..2bb3f06 --- /dev/null +++ b/arch/arm/plat-s5p/setup-mfc.c @@ -0,0 +1,17 @@ +/* arch/arm/plat-s5pv2xx/setup-mfc.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * MFC configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 53eb15b..c4bc9cb 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -12,7 +12,9 @@ obj- := # Objects we always build independent of SoC choice obj-y += init.o +ifndef CONFIG_S5P_HIGH_RES_TIMERS obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o +endif obj-y += clock.o obj-y += pwm-clock.o obj-y += gpio.o diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 7728928..a3101e5 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -95,10 +95,19 @@ static int dev_is_platform_device(struct device *dev) /* Clock API calls */ +static int nullstrcmp(const char *a, const char *b) +{ + if (!a) + return b ? -1 : 0; + if (!b) + return 1; + + return strcmp(a, b); +} + struct clk *clk_get(struct device *dev, const char *id) { - struct clk *p; - struct clk *clk = ERR_PTR(-ENOENT); + struct clk *clk; int idno; if (dev == NULL || !dev_is_platform_device(dev)) @@ -108,65 +117,96 @@ struct clk *clk_get(struct device *dev, const char *id) spin_lock(&clocks_lock); - list_for_each_entry(p, &clocks, list) { - if (p->id == idno && - strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } + list_for_each_entry(clk, &clocks, list) + if (!nullstrcmp(id, clk->name) && clk->dev == dev) + goto found_it; - /* check for the case where a device was supplied, but the - * clock that was being searched for is not device specific */ + list_for_each_entry(clk, &clocks, list) + if (clk->id == idno && nullstrcmp(id, clk->name) == 0) + goto found_it; - if (IS_ERR(clk)) { - list_for_each_entry(p, &clocks, list) { - if (p->id == -1 && strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - } + list_for_each_entry(clk, &clocks, list) + if (clk->id == -1 && !nullstrcmp(id, clk->name) && + clk->dev == NULL) + goto found_it; + clk = ERR_PTR(-ENOENT); + pr_warning("%s: could not find clock %s for dev %pS (%s)\n", + __func__, id, dev, dev ? dev_name(dev) : ""); + spin_unlock(&clocks_lock); + return clk; +found_it: + pr_debug("%s(%p, %s) found %s %d %pS\n", + __func__, dev, id, clk->name, clk->id, clk->dev); + if (!try_module_get(clk->owner)) + clk = ERR_PTR(-ENOENT); spin_unlock(&clocks_lock); return clk; } void clk_put(struct clk *clk) { + pr_debug("%s on %s %d %pS", __func__, clk->name, clk->id, clk->dev); module_put(clk->owner); } -int clk_enable(struct clk *clk) +void _clk_enable(struct clk *clk) { - if (IS_ERR(clk) || clk == NULL) - return -EINVAL; + if (!clk || IS_ERR(clk)) + return; - clk_enable(clk->parent); + if ((clk->usage++) > 0) + return; - spin_lock(&clocks_lock); + _clk_enable(clk->parent); + pr_debug("%s update hardware clock %s %d %pS\n", + __func__, clk->name, clk->id, clk->dev); + (clk->enable)(clk, 1); +} - if ((clk->usage++) == 0) - (clk->enable)(clk, 1); +int clk_enable(struct clk *clk) +{ + if (WARN_ON_ONCE(IS_ERR(clk) || clk == NULL)) { + pr_debug("%s request on invalid clock\n", __func__); + return -EINVAL; + } + pr_debug("%s request on %s %d %pS\n", + __func__, clk->name, clk->id, clk->dev); + spin_lock(&clocks_lock); + _clk_enable(clk); spin_unlock(&clocks_lock); + return 0; } -void clk_disable(struct clk *clk) +void _clk_disable(struct clk *clk) { - if (IS_ERR(clk) || clk == NULL) + if (!clk || IS_ERR(clk)) + return; + + if ((--clk->usage) > 0) return; - spin_lock(&clocks_lock); + pr_debug("%s update hardware clock %s %d %pS\n", + __func__, clk->name, clk->id, clk->dev); + (clk->enable)(clk, 0); + _clk_disable(clk->parent); +} - if ((--clk->usage) == 0) - (clk->enable)(clk, 0); +void clk_disable(struct clk *clk) +{ + if (IS_ERR(clk) || clk == NULL) { + pr_debug("%s request on invalid clock\n", __func__); + return; + } + pr_debug("%s request on %s %d %pS\n", + __func__, clk->name, clk->id, clk->dev); + + spin_lock(&clocks_lock); + _clk_disable(clk); spin_unlock(&clocks_lock); - clk_disable(clk->parent); } @@ -352,6 +392,25 @@ int s3c24xx_register_clock(struct clk *clk) BUG_ON(clk->list.prev != clk->list.next); spin_lock(&clocks_lock); + if (clk->enable != clk_null_enable) { + struct clk *c; + list_for_each_entry(c, &clocks, list) { + if (c->enable == clk->enable && + c->ctrlbit & clk->ctrlbit) { + pr_warning("%s: new clock %s, id %d, dev %p " + "uses same enable bit as " + "%s, id %d, dev %p\n", __func__, + clk->name, clk->id, clk->dev, + c->name, c->id, c->dev); + } + if (!nullstrcmp(c->name, clk->name) && + c->id == clk->id && c->dev == clk->dev) { + pr_warning("%s: duplicate clock id: " + "%s, id %d, dev %p\n", __func__, + clk->name, clk->id, clk->dev); + } + } + } list_add(&clk->list, &clocks); spin_unlock(&clocks_lock); @@ -462,18 +521,35 @@ static int clk_debugfs_register_one(struct clk *c) struct clk *pa = c->parent; char s[255]; char *p = s; + int i; p += sprintf(p, "%s", c->name); if (c->id >= 0) - sprintf(p, ":%d", c->id); + p += sprintf(p, ":%d", c->id); - d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); - if (!d) - return -ENOMEM; + for (i = 1; i < 16; i++) { + d = debugfs_create_dir(s, clk_debugfs_root); + if (d) + break; + sprintf(p, " copy %d", i); + } + if (!d) { + pr_warning("%s: failed to register %s\n", __func__, s); + return 0; + } c->dent = d; + if (pa) { + d = debugfs_create_symlink("parent", + c->dent, pa->dent->d_name.name); + if (!d) { + err = -ENOMEM; + goto err_out; + } + } + d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage); if (!d) { err = -ENOMEM; diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c index db7a65c..9296bd8 100644 --- a/arch/arm/plat-samsung/dev-hsmmc.c +++ b/arch/arm/plat-samsung/dev-hsmmc.c @@ -76,4 +76,10 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) set->host_caps |= pd->host_caps; if (pd->clk_type) set->clk_type = pd->clk_type; + if (pd->built_in) + set->built_in = pd->built_in; + if (pd->must_maintain_clock) + set->must_maintain_clock = pd->must_maintain_clock; + if (pd->enable_intr_on_resume) + set->enable_intr_on_resume = pd->enable_intr_on_resume; } diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c index 2497321..4e7b100 100644 --- a/arch/arm/plat-samsung/dev-hsmmc1.c +++ b/arch/arm/plat-samsung/dev-hsmmc1.c @@ -76,4 +76,10 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) set->host_caps |= pd->host_caps; if (pd->clk_type) set->clk_type = pd->clk_type; + if (pd->built_in) + set->built_in = pd->built_in; + if (pd->must_maintain_clock) + set->must_maintain_clock = pd->must_maintain_clock; + if (pd->enable_intr_on_resume) + set->enable_intr_on_resume = pd->enable_intr_on_resume; } diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c index f60aedb..ef2e8c6 100644 --- a/arch/arm/plat-samsung/dev-hsmmc2.c +++ b/arch/arm/plat-samsung/dev-hsmmc2.c @@ -77,4 +77,10 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) set->host_caps |= pd->host_caps; if (pd->clk_type) set->clk_type = pd->clk_type; + if (pd->built_in) + set->built_in = pd->built_in; + if (pd->must_maintain_clock) + set->must_maintain_clock = pd->must_maintain_clock; + if (pd->enable_intr_on_resume) + set->enable_intr_on_resume = pd->enable_intr_on_resume; } diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c index ede776f..da729c5 100644 --- a/arch/arm/plat-samsung/dev-hsmmc3.c +++ b/arch/arm/plat-samsung/dev-hsmmc3.c @@ -80,4 +80,10 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) set->host_caps |= pd->host_caps; if (pd->clk_type) set->clk_type = pd->clk_type; + if (pd->built_in) + set->built_in = pd->built_in; + if (pd->must_maintain_clock) + set->must_maintain_clock = pd->must_maintain_clock; + if (pd->enable_intr_on_resume) + set->enable_intr_on_resume = pd->enable_intr_on_resume; } diff --git a/arch/arm/plat-samsung/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c index 3a601c1..0aa46b1 100644 --- a/arch/arm/plat-samsung/dev-i2c0.c +++ b/arch/arm/plat-samsung/dev-i2c0.c @@ -15,6 +15,8 @@ #include <linux/kernel.h> #include <linux/string.h> #include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/irqs.h> #include <mach/map.h> @@ -24,6 +26,8 @@ #include <plat/devs.h> #include <plat/cpu.h> +#include <asm/io.h> + static struct resource s3c_i2c_resource[] = { [0] = { .start = S3C_PA_IIC, @@ -39,11 +43,7 @@ static struct resource s3c_i2c_resource[] = { struct platform_device s3c_device_i2c0 = { .name = "s3c2410-i2c", -#ifdef CONFIG_S3C_DEV_I2C1 .id = 0, -#else - .id = -1, -#endif .num_resources = ARRAY_SIZE(s3c_i2c_resource), .resource = s3c_i2c_resource, }; @@ -51,8 +51,8 @@ struct platform_device s3c_device_i2c0 = { static struct s3c2410_platform_i2c default_i2c_data0 __initdata = { .flags = 0, .slave_addr = 0x10, - .frequency = 100*1000, - .sda_delay = 100, + .frequency = 400*1000, + .sda_delay = S3C2410_IICLC_SDA_DELAY15 | S3C2410_IICLC_FILTER_ON, }; void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) @@ -70,3 +70,31 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) s3c_device_i2c0.dev.platform_data = npd; } + +void s3c_i2c0_force_stop() +{ + void __iomem *regs; + struct clk *clk; + unsigned long iicstat; + + regs = ioremap(S3C_PA_IIC, SZ_4K); + if(regs == NULL) { + printk(KERN_ERR "%s, cannot request IO\n", __func__); + return; + } + + clk = clk_get(&s3c_device_i2c0.dev, "i2c"); + if(clk == NULL || IS_ERR(clk)) { + printk(KERN_ERR "%s, cannot get cloock\n", __func__); + return; + } + + clk_enable(clk); + iicstat = readl(regs + S3C2410_IICSTAT); + writel(iicstat & ~S3C2410_IICSTAT_TXRXEN, regs + S3C2410_IICSTAT); + clk_disable(clk); + + iounmap(regs); +} +EXPORT_SYMBOL(s3c_i2c0_force_stop); + diff --git a/arch/arm/plat-samsung/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c index 858ee2a..3a1a85f 100644 --- a/arch/arm/plat-samsung/dev-i2c1.c +++ b/arch/arm/plat-samsung/dev-i2c1.c @@ -15,6 +15,8 @@ #include <linux/kernel.h> #include <linux/string.h> #include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/irqs.h> #include <mach/map.h> @@ -24,6 +26,8 @@ #include <plat/devs.h> #include <plat/cpu.h> +#include <asm/io.h> + static struct resource s3c_i2c_resource[] = { [0] = { .start = S3C_PA_IIC1, @@ -48,8 +52,8 @@ static struct s3c2410_platform_i2c default_i2c_data1 __initdata = { .flags = 0, .bus_num = 1, .slave_addr = 0x10, - .frequency = 100*1000, - .sda_delay = 100, + .frequency = 400*1000, + .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, }; void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) @@ -67,3 +71,32 @@ void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) s3c_device_i2c1.dev.platform_data = npd; } + +void s3c_i2c1_force_stop() +{ + struct resource *ioarea; + void __iomem *regs; + struct clk *clk; + unsigned long iicstat; + + regs = ioremap(S3C_PA_IIC1, SZ_4K); + if(regs == NULL) { + printk(KERN_ERR "%s, cannot request IO\n", __func__); + return; + } + + clk = clk_get(&s3c_device_i2c1.dev, "i2c"); + if(clk == NULL || IS_ERR(clk)) { + printk(KERN_ERR "%s, cannot get cloock\n", __func__); + return; + } + + clk_enable(clk); + iicstat = readl(regs + S3C2410_IICSTAT); + writel(iicstat & ~S3C2410_IICSTAT_TXRXEN, regs + S3C2410_IICSTAT); + clk_disable(clk); + + iounmap(regs); +} +EXPORT_SYMBOL(s3c_i2c1_force_stop); + diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c index ff4ba69..d9b5fb6 100644 --- a/arch/arm/plat-samsung/dev-i2c2.c +++ b/arch/arm/plat-samsung/dev-i2c2.c @@ -1,12 +1,11 @@ /* linux/arch/arm/plat-s3c/dev-i2c2.c * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ + * Copyright 2008-2009 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ * * S3C series device definition for i2c device 2 * - * Based on plat-samsung/dev-i2c0.c - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -16,6 +15,8 @@ #include <linux/kernel.h> #include <linux/string.h> #include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/irqs.h> #include <mach/map.h> @@ -25,6 +26,8 @@ #include <plat/devs.h> #include <plat/cpu.h> +#include <asm/io.h> + static struct resource s3c_i2c_resource[] = { [0] = { .start = S3C_PA_IIC2, @@ -49,8 +52,8 @@ static struct s3c2410_platform_i2c default_i2c_data2 __initdata = { .flags = 0, .bus_num = 2, .slave_addr = 0x10, - .frequency = 100*1000, - .sda_delay = 100, + .frequency = 400*1000, + .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, }; void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) @@ -68,3 +71,31 @@ void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) s3c_device_i2c2.dev.platform_data = npd; } + +void s3c_i2c2_force_stop() +{ + void __iomem *regs; + struct clk *clk; + unsigned long iicstat; + + regs = ioremap(S3C_PA_IIC2, SZ_4K); + if(regs == NULL) { + printk(KERN_ERR "%s, cannot request IO\n", __func__); + return; + } + + clk = clk_get(&s3c_device_i2c2.dev, "i2c"); + if(clk == NULL || IS_ERR(clk)) { + printk(KERN_ERR "%s, cannot get cloock\n", __func__); + return; + } + + clk_enable(clk); + iicstat = readl(regs + S3C2410_IICSTAT); + writel(iicstat & ~S3C2410_IICSTAT_TXRXEN, regs + S3C2410_IICSTAT); + clk_disable(clk); + + iounmap(regs); +} +EXPORT_SYMBOL(s3c_i2c2_force_stop); + diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c index 5928105..6db1f63 100644 --- a/arch/arm/plat-samsung/dev-uart.c +++ b/arch/arm/plat-samsung/dev-uart.c @@ -19,19 +19,19 @@ /* uart devices */ -static struct platform_device s3c24xx_uart_device0 = { +struct platform_device s3c24xx_uart_device0 = { .id = 0, }; -static struct platform_device s3c24xx_uart_device1 = { +struct platform_device s3c24xx_uart_device1 = { .id = 1, }; -static struct platform_device s3c24xx_uart_device2 = { +struct platform_device s3c24xx_uart_device2 = { .id = 2, }; -static struct platform_device s3c24xx_uart_device3 = { +struct platform_device s3c24xx_uart_device3 = { .id = 3, }; diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c index 1c0b040..a899173 100644 --- a/arch/arm/plat-samsung/gpio-config.c +++ b/arch/arm/plat-samsung/gpio-config.c @@ -130,6 +130,27 @@ s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin) } EXPORT_SYMBOL(s3c_gpio_getpull); +int s3c_gpio_setpin(unsigned int pin, s3c_gpio_pull_t level) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned long flags; + int offset, ret; + + if (!chip) + return -EINVAL; + + offset = pin - chip->chip.base; + + local_irq_save(flags); + //ret = s3c_gpio_do_setpin(chip, offset, level); + ret = (chip->config->set_pin)(chip, offset, level); + local_irq_restore(flags); + + return ret; +} + +EXPORT_SYMBOL(s3c_gpio_setpin); + #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 983c578..0533827 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -46,6 +46,7 @@ struct clk { unsigned long ctrlbit; struct clk_ops *ops; + struct device *dev; int (*enable)(struct clk *, int enable); #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) struct dentry *dent; /* For visible tree hierarchy */ diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index c0a5741..8865194 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -66,7 +66,11 @@ extern void s3c24xx_init_uartdevs(char *name, /* timer for 2410/2440 */ struct sys_timer; +#if defined(CONFIG_S5P_HIGH_RES_TIMERS) +extern struct sys_timer s5p_systimer; +#else extern struct sys_timer s3c24xx_timer; +#endif extern struct syscore_ops s3c2410_pm_syscore_ops; extern struct syscore_ops s3c2412_pm_syscore_ops; diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index e3b31c2..9a918d0 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -30,6 +30,16 @@ extern struct s3c24xx_uart_resources s5p_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; +extern struct platform_device s3c24xx_uart_device0; +extern struct platform_device s3c24xx_uart_device1; +extern struct platform_device s3c24xx_uart_device2; +extern struct platform_device s3c24xx_uart_device3; + +extern struct platform_device s5pv210_device_fiqdbg_uart0; +extern struct platform_device s5pv210_device_fiqdbg_uart1; +extern struct platform_device s5pv210_device_fiqdbg_uart2; +extern struct platform_device s5pv210_device_fiqdbg_uart3; + extern struct platform_device s3c_device_timer[]; extern struct platform_device s3c64xx_device_iis0; @@ -49,6 +59,15 @@ extern struct platform_device s3c64xx_device_ac97; extern struct platform_device s3c_device_ts; extern struct platform_device s3c_device_fb; + +extern struct platform_device s3c_device_fimc0; +extern struct platform_device s3c_device_fimc1; +extern struct platform_device s3c_device_fimc2; +extern struct platform_device s3c_device_ipc; +extern struct platform_device s3c_device_mfc; +extern struct platform_device s3c_device_jpeg; +extern struct platform_device s3c_device_g3d; + extern struct platform_device s3c_device_ohci; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; @@ -91,7 +110,19 @@ extern struct platform_device s5p_device_onenand; extern struct platform_device s3c_device_usbgadget; extern struct platform_device s3c_device_usb_hsudc; +extern struct platform_device s3c_device_android_usb; +extern struct platform_device s3c_device_usb_mass_storage; +extern struct platform_device s3c_device_rndis; extern struct platform_device s3c_device_usb_hsotg; +#if defined CONFIG_USB_S3C_OTG_HOST +extern struct platform_device s3c_device_usb_otghcd; +#endif +#if defined CONFIG_USB_DWC_OTG +extern struct platform_device s3c_device_usb_dwcotg; +#endif +extern struct platform_device s5p_device_rotator; +extern struct platform_device s5p_device_tvout; +extern struct platform_device s5p_device_g3d; extern struct platform_device s5pv210_device_ac97; extern struct platform_device s5pv210_device_pcm0; @@ -142,9 +173,17 @@ extern struct platform_device s5p_device_mipi_csis1; extern struct platform_device s5p_device_ehci; extern struct platform_device exynos4_device_sysmmu; +extern struct platform_device s5p_device_rtc; +extern struct platform_device s3c_device_adc; /* s3c2440 specific devices */ +extern struct platform_device s5pv210_device_pdma0; +extern struct platform_device s5pv210_device_pdma1; +extern struct platform_device s5pv210_device_mdma; + +extern struct platform_device s5pv210_device_cpufreq; + #ifdef CONFIG_CPU_S3C2440 extern struct platform_device s3c_device_camif; @@ -164,4 +203,6 @@ extern struct platform_device s3c_device_ac97; extern void *s3c_set_platdata(void *pd, size_t pdsize, struct platform_device *pdev); +void __init s3c_usb_set_serial(void); + #endif /* __PLAT_DEVS_H */ diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h index 8c273b7..459bdc8 100644 --- a/arch/arm/plat-samsung/include/plat/dma.h +++ b/arch/arm/plat-samsung/include/plat/dma.h @@ -18,7 +18,9 @@ enum s3c2410_dma_buffresult { enum s3c2410_dmasrc { S3C2410_DMASRC_HW, /* source is memory */ - S3C2410_DMASRC_MEM /* source is hardware */ + S3C2410_DMASRC_MEM, /* source is hardware */ + S3C_DMA_MEM2MEM, + S3C_DMA_MEM2MEM_SET, }; /* enum s3c2410_chan_op diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 3ad8386..33cc2ca 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -48,6 +48,12 @@ static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip, return chip->config->get_pull(chip, off); } +static inline int s3c_gpio_do_setpin(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t level) +{ + return (chip->config->set_pin)(chip, off, level); +} + /** * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. * @chip: The gpio chip that is being configured. diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 1762dcb..60b7460 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -56,11 +56,16 @@ struct s3c_gpio_cfg { int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, s3c_gpio_pull_t pull); + int (*set_pin)(struct s3c_gpio_chip *chip, unsigned offs, + s3c_gpio_pull_t level); + unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, unsigned config); }; +extern int s3c_gpio_setpin(unsigned int pin, s3c_gpio_pull_t level); + #define S3C_GPIO_SPECIAL_MARK (0xfffffff0) #define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x)) diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 8cad4cf..0ce5225 100644..100755 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -69,7 +69,7 @@ struct s3c_gpio_chip { int group; spinlock_t lock; #ifdef CONFIG_PM - u32 pm_save[4]; + u32 pm_save[7]; #endif }; diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h index 1543da8..aec3471 100644 --- a/arch/arm/plat-samsung/include/plat/iic.h +++ b/arch/arm/plat-samsung/include/plat/iic.h @@ -71,4 +71,8 @@ extern void s3c_i2c5_cfg_gpio(struct platform_device *dev); extern void s3c_i2c6_cfg_gpio(struct platform_device *dev); extern void s3c_i2c7_cfg_gpio(struct platform_device *dev); +extern void s3c_i2c0_force_stop(void); +extern void s3c_i2c1_force_stop(void); +extern void s3c_i2c2_force_stop(void); + #endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/plat-samsung/include/plat/map-base.h index 3ffac4d..da2414c 100644 --- a/arch/arm/plat-samsung/include/plat/map-base.h +++ b/arch/arm/plat-samsung/include/plat/map-base.h @@ -14,7 +14,7 @@ #ifndef __ASM_PLAT_MAP_H #define __ASM_PLAT_MAP_H __FILE__ -/* Fit all our registers in at 0xF6000000 upwards, trying to use as +/* Fit all our registers in at 0xFC000000 upwards, trying to use as * little of the VA space as possible so vmalloc and friends have a * better chance of getting memory. * @@ -22,7 +22,7 @@ * an single MOVS instruction (ie, only 8 bits of set data) */ -#define S3C_ADDR_BASE 0xF6000000 +#define S3C_ADDR_BASE (0xFC000000) #ifndef __ASSEMBLY__ #define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) @@ -35,6 +35,8 @@ #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_OTG S3C_ADDR(0x00E00000) /* OTG */ +#define S3C_VA_OTGSFR S3C_ADDR(0x00F00000) /* OTG PHY */ #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ /* This is used for the CPU specific mappings that may be needed, so that diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 7fb6f6b..b85132d 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -43,6 +43,7 @@ extern unsigned long s3c_irqwake_eintallow; extern void (*pm_cpu_prep)(void); extern void (*pm_cpu_sleep)(void); +extern void (*pm_cpu_restore)(void); /* Flags for PM Control */ @@ -128,7 +129,7 @@ extern void s3c_pm_dbg(const char *msg, ...); #define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) #else -#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) +#define S3C_PMDBG(fmt...) pr_debug(fmt) #endif #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK diff --git a/arch/arm/plat-samsung/include/plat/regs-otg.h b/arch/arm/plat-samsung/include/plat/regs-otg.h new file mode 100644 index 0000000..dccdb26 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-otg.h @@ -0,0 +1,262 @@ +/* arch/arm/plat-samsung/include/plat/regs-otg.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * Kyoungil Kim <ki0351.kim@samsung.com> + * + * This include file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. +*/ + +#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H +#define __ASM_ARCH_REGS_USB_OTG_HS_H + +/* USB2.0 OTG Controller register */ +#define S3C_USBOTG_PHYREG(x) ((x) + S3C_VA_OTGSFR) +#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0) +#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4) +#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8) +#define S3C_USBOTG_PHYTUNE S3C_USBOTG_PHYREG(0x24) + +/* USB2.0 OTG Controller register */ +#define S3C_USBOTGREG(x) ((x) + S3C_VA_OTG) +/*============================================================================================== */ + /* Core Global Registers */ +#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) /* OTG Control & Status */ +#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) /* OTG Interrupt */ +#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) /* Core AHB Configuration */ +#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) /* Core USB Configuration */ +#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) /* Core Reset */ +#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) /* Core Interrupt */ +#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) /* Core Interrupt Mask */ +#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) /* Receive Status Debug Read/Status Read */ +#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) /* Receive Status Debug Pop/Status Pop */ +#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) /* Receive FIFO Size */ +#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) /* Non-Periodic Transmit FIFO Size */ +#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) /* Non-Periodic Transmit FIFO/Queue Status */ + +#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) /* Host Periodic Transmit FIFO Size */ +#define S3C_UDC_OTG_DIEPTXF(n) S3C_USBOTGREG(0x104 + (n-1)*0x4)/* Device IN EP Transmit FIFO Size Register */ + +/*============================================================================================== */ +/* Host Mode Registers */ +/*------------------------------------------------ */ +/* Host Global Registers */ +#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) /* Host Configuration */ +#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) /* Host Frame Interval */ +#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) /* Host Frame Number/Frame Time Remaining */ +#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) /* Host Periodic Transmit FIFO/Queue Status */ +#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) /* Host All Channels Interrupt */ +#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) /* Host All Channels Interrupt Mask */ + +/*------------------------------------------------ */ +/* Host Port Control & Status Registers */ +#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) /* Host Port Control & Status */ + +/*------------------------------------------------ */ +/* Host Channel-Specific Registers */ +#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) /* Host Channel-0 Characteristics */ +#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) /* Host Channel-0 Split Control */ +#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) /* Host Channel-0 Interrupt */ +#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) /* Host Channel-0 Interrupt Mask */ +#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) /* Host Channel-0 Transfer Size */ +#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) /* Host Channel-0 DMA Address */ + + +/*============================================================================================== */ +/* Device Mode Registers */ +/*------------------------------------------------ */ +/* Device Global Registers */ +#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) /* Device Configuration */ +#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) /* Device Control */ +#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) /* Device Status */ +#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) /* Device IN Endpoint Common Interrupt Mask */ +#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) /* Device OUT Endpoint Common Interrupt Mask */ +#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) /* Device All Endpoints Interrupt */ +#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) /* Device All Endpoints Interrupt Mask */ +#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) /* Device IN Token Sequence Learning Queue Read 1 */ +#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) /* Device IN Token Sequence Learning Queue Read 2 */ +#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) /* Device VBUS Discharge Time */ +#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) /* Device VBUS Pulsing Time */ +#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) /* Device IN Token Sequence Learning Queue Read 3 */ +#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) /* Device IN Token Sequence Learning Queue Read 4 */ + +/*------------------------------------------------ */ +/* Device Logical IN Endpoint-Specific Registers */ +#define S3C_UDC_OTG_DIEPCTL(n) S3C_USBOTGREG(0x900 + n*0x20) /* Device IN Endpoint n Control */ +#define S3C_UDC_OTG_DIEPINT(n) S3C_USBOTGREG(0x908 + n*0x20) /* Device IN Endpoint n Interrupt */ +#define S3C_UDC_OTG_DIEPTSIZ(n) S3C_USBOTGREG(0x910 + n*0x20) /* Device IN Endpoint n Transfer Size */ +#define S3C_UDC_OTG_DIEPDMA(n) S3C_USBOTGREG(0x914 + n*0x20) /* Device IN Endpoint n DMA Address */ + +/*------------------------------------------------ */ +/* Device Logical OUT Endpoint-Specific Registers */ +#define S3C_UDC_OTG_DOEPCTL(n) S3C_USBOTGREG(0xB00 + n*0x20) /* Device OUT Endpoint n Control */ +#define S3C_UDC_OTG_DOEPINT(n) S3C_USBOTGREG(0xB08 + n*0x20) /* Device OUT Endpoint n Interrupt */ +#define S3C_UDC_OTG_DOEPTSIZ(n) S3C_USBOTGREG(0xB10 + n*0x20) /* Device OUT Endpoint n Transfer Size */ +#define S3C_UDC_OTG_DOEPDMA(n) S3C_USBOTGREG(0xB14 + n*0x20) /* Device OUT Endpoint n DMA Address */ + +/*------------------------------------------------ */ +/* Endpoint FIFO address */ +#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000) +#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000) +#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000) +#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000) +#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000) +#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000) +#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000) +#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000) +#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000) +#define S3C_UDC_OTG_EP9_FIFO S3C_USBOTGREG(0xA000) +#define S3C_UDC_OTG_EP10_FIFO S3C_USBOTGREG(0xB000) +#define S3C_UDC_OTG_EP11_FIFO S3C_USBOTGREG(0xC000) +#define S3C_UDC_OTG_EP12_FIFO S3C_USBOTGREG(0xD000) +#define S3C_UDC_OTG_EP13_FIFO S3C_USBOTGREG(0xE000) +#define S3C_UDC_OTG_EP14_FIFO S3C_USBOTGREG(0xF000) +#define S3C_UDC_OTG_EP15_FIFO S3C_USBOTGREG(0x10000) + +/*===================================================================== */ +/*definitions related to CSR setting */ + +/* S3C_UDC_OTG_GOTGCTL */ +#define B_SESSION_VALID (0x1<<19) +#define A_SESSION_VALID (0x1<<18) +#define SESSION_REQ (0x1<<1) +/* S3C_UDC_OTG_GAHBCFG */ +#define PTXFE_HALF (0<<8) +#define PTXFE_ZERO (1<<8) +#define NPTXFE_HALF (0<<7) +#define NPTXFE_ZERO (1<<7) +#define MODE_SLAVE (0<<5) +#define MODE_DMA (1<<5) +#define BURST_SINGLE (0<<1) +#define BURST_INCR (1<<1) +#define BURST_INCR4 (3<<1) +#define BURST_INCR8 (5<<1) +#define BURST_INCR16 (7<<1) +#define GBL_INT_UNMASK (1<<0) +#define GBL_INT_MASK (0<<0) + +/* S3C_UDC_OTG_GRSTCTL */ +#define AHB_MASTER_IDLE (1u<<31) +#define HCLK_SOFT_RESET (0x1<<1) +#define CORE_SOFT_RESET (0x1<<0) + +/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */ +#define INT_RESUME (1u<<31) +#define INT_DISCONN (0x1<<29) +#define INT_CONN_ID_STS_CNG (0x1<<28) +#define INT_OUT_EP (0x1<<19) +#define INT_IN_EP (0x1<<18) +#define INT_ENUMDONE (0x1<<13) +#define INT_RESET (0x1<<12) +#define INT_SUSPEND (0x1<<11) +#define INT_EARLY_SUSPEND (0x1<<10) +#define INT_NP_TX_FIFO_EMPTY (0x1<<5) +#define INT_RX_FIFO_NOT_EMPTY (0x1<<4) +#define INT_SOF (0x1<<3) +#define INT_DEV_MODE (0x0<<0) +#define INT_HOST_MODE (0x1<<1) +#define INT_GOUTNakEff (0x01<<7) +#define INT_GINNakEff (0x01<<6) + +#define FULL_SPEED_CONTROL_PKT_SIZE 8 +#define FULL_SPEED_BULK_PKT_SIZE 64 + +#define HIGH_SPEED_CONTROL_PKT_SIZE 64 +#define HIGH_SPEED_BULK_PKT_SIZE 512 + +#define RX_FIFO_SIZE (4096>>2) +#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE +#define NPTX_FIFO_SIZE (4096>>2) +#define PTX_FIFO_SIZE (1024>>1) + +/* Enumeration speed */ +#define USB_HIGH_30_60MHZ (0x0<<1) +#define USB_FULL_30_60MHZ (0x1<<1) +#define USB_LOW_6MHZ (0x2<<1) +#define USB_FULL_48MHZ (0x3<<1) + +/* S3C_UDC_OTG_GRXSTSP STATUS */ +#define OUT_PKT_RECEIVED (0x2<<17) +#define OUT_TRANSFER_COMPLELTED (0x3<<17) +#define SETUP_TRANSACTION_COMPLETED (0x4<<17) +#define SETUP_PKT_RECEIVED (0x6<<17) +#define GLOBAL_OUT_NAK (0x1<<17) + +/* S3C_UDC_OTG_DCTL device control register */ +#define NORMAL_OPERATION (0x1<<0) +#define SOFT_DISCONNECT (0x1<<1) +#define TEST_CONTROL_MASK (0x7<<4) +#define TEST_J_MODE (0x1<<4) +#define TEST_K_MODE (0x2<<4) +#define TEST_SE0_NAK_MODE (0x3<<4) +#define TEST_PACKET_MODE (0x4<<4) +#define TEST_FORCE_ENABLE_MODE (0x5<<4) +#define REMOTE_WAKEUP (0x1<<0) + +/* S3C_UDC_OTG_DSTS device status register */ +#define SOFFN_MASK (0x3fff << 8) +#define SOFFN_SHIFT (8) +#define USB_SUSPEND (0x1<<0) + +/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */ +#define DAINT_OUT_BIT (16) +#define DAINT_MASK (0xFFFF) + +/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */ +#define DEPCTL_EPENA (0x1<<31) +#define DEPCTL_EPDIS (0x1<<30) +#define DEPCTL_SETD1PID (0x1<<29) +#define DEPCTL_SET_ODD_FRM (0x1<<29) +#define DEPCTL_SETD0PID (0x1<<28) +#define DEPCTL_SET_EVEN_FRM (0x1<<28) +#define DEPCTL_SNAK (0x1<<27) +#define DEPCTL_CNAK (0x1<<26) +#define DEPCTL_STALL (0x1<<21) +#define DEPCTL_TYPE_BIT (18) +#define DEPCTL_TXFNUM_BIT (22) +#define DEPCTL_TXFNUM_MASK (0xF<<22) +#define DEPCTL_TYPE_MASK (0x3<<18) +#define DEPCTL_CTRL_TYPE (0x0<<18) +#define DEPCTL_ISO_TYPE (0x1<<18) +#define DEPCTL_BULK_TYPE (0x2<<18) +#define DEPCTL_INTR_TYPE (0x3<<18) +#define DEPCTL_USBACTEP (0x1<<15) +#define DEPCTL_NEXT_EP_BIT (11) +#define DEPCTL_MPS_BIT (0) +#define DEPCTL_MPS_MASK (0x7FF) + +#define DEPCTL0_MPS_64 (0x0<<0) +#define DEPCTL0_MPS_32 (0x1<<0) +#define DEPCTL0_MPS_16 (0x2<<0) +#define DEPCTL0_MPS_8 (0x3<<0) +#define DEPCTL_MPS_BULK_512 (512<<0) +#define DEPCTL_MPS_INT_MPS_16 (16<<0) + +#define DIEPCTL0_NEXT_EP_BIT (11) + +/* S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register */ + +/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */ +/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ +#define BACK2BACK_SETUP_RECEIVED (0x1<<6) +#define INTKNEPMIS (0x1<<5) +#define INTKN_TXFEMP (0x1<<4) +#define NON_ISO_IN_EP_TIMEOUT (0x1<<3) +#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3) +#define AHB_ERROR (0x1<<2) +#define EPDISBLD (0x1<<1) +#define TRANSFER_DONE (0x1<<0) + +/*DIEPTSIZ0 / DOEPTSIZ0 */ + +/* DEPTSIZ common bit */ +#define DEPTSIZ_PKT_CNT_BIT (19) +#define DEPTSIZ_XFER_SIZE_BIT (0) + +#define DEPTSIZ_SETUP_PKCNT_1 (1<<29) +#define DEPTSIZ_SETUP_PKCNT_2 (2<<29) +#define DEPTSIZ_SETUP_PKCNT_3 (3<<29) + +#endif diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h index 30b7cc1..b8daf4b 100644 --- a/arch/arm/plat-samsung/include/plat/regs-rtc.h +++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h @@ -28,6 +28,22 @@ #define S3C64XX_RTCCON_TICMSK (0xF<<7) #define S3C64XX_RTCCON_TICSHT (7) +#if defined(CONFIG_CPU_S5PC100) || defined(CONFIG_CPU_S5PV210) +#define S3C_MAX_CNT 32768 +#define S3C_RTCCON_TICEN (1<<8) +#define S3C_RTC_TICNT S3C2410_RTCREG(0x40) +#else +#define S3C_INTP_ALM (1<<1) +#define S3C_MAX_CNT 128 +#define S3C_RTCCON_TICEN (1<<7) +#define S3C_RTC_TICNT S3C2410_RTCREG(0x44) +#endif + +/* Common Reg for samsung AP*/ +#define S3C_INTP S3C2410_RTCREG(0x30) +#define S3C_INTP_ALM (1<<1) +#define S3C_INTP_TIC (1<<0) + #define S3C2410_TICNT S3C2410_RTCREG(0x44) #define S3C2410_TICNT_ENABLE (1<<7) @@ -63,6 +79,6 @@ #define S3C2410_RTCDAY S3C2410_RTCREG(0x80) #define S3C2410_RTCMON S3C2410_RTCREG(0x84) #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) - +#define S3C2410_CURTICCNT S3C2410_RTCREG(0x90) #endif /* __ASM_ARCH_REGS_RTC_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h index e34049a..a9d956d 100644 --- a/arch/arm/plat-samsung/include/plat/regs-sdhci.h +++ b/arch/arm/plat-samsung/include/plat/regs-sdhci.h @@ -83,5 +83,5 @@ #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) #define S3C64XX_SDHCI_CONTROL4_BUSY (1) - +#define SDHCI_S3C_CTRL_8BITBUS (1 << 5) #endif /* __PLAT_S3C_SDHCI_REGS_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index 116edfe..48a91dd 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -53,6 +53,8 @@ #define S3C2410_UERSTAT (0x14) #define S3C2410_UFSTAT (0x18) #define S3C2410_UMSTAT (0x1C) +#define S3C2410_UDIVSLOT (0x2C) +#define S3C2410_UINTMSK (0x38) #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) @@ -194,6 +196,11 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 +/* S5V210 interrupt registers. */ +#define S5P_UINTP 0x30 +#define S5P_UINTSP 0x34 +#define S5P_UINTM 0x38 + /* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) #define S5PV210_UCON_PCLK (0<<10) @@ -259,7 +266,11 @@ struct s3c2410_uartcfg { unsigned char hwport; /* hardware port number */ unsigned char unused; unsigned short flags; +#if !defined(CONFIG_CPU_S5PV210) upf_t uart_flags; /* default uart flags */ +#else + unsigned long uart_flags; /* default uart flags */ +#endif unsigned int has_fracval; @@ -269,6 +280,8 @@ struct s3c2410_uartcfg { struct s3c24xx_uart_clksrc *clocks; unsigned int clocks_size; + + void (*wake_peer)(struct uart_port *); }; /* s3c24xx_uart_devs diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h index 8107442..333e381 100644 --- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h +++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h @@ -84,6 +84,14 @@ enum dma_ch { DMACH_SLIMBUS4_TX, DMACH_SLIMBUS5_RX, DMACH_SLIMBUS5_TX, + DMACH_MTOM_0, + DMACH_MTOM_1, + DMACH_MTOM_2, + DMACH_MTOM_3, + DMACH_MTOM_4, + DMACH_MTOM_5, + DMACH_MTOM_6, + DMACH_MTOM_7, /* END Marker, also used to denote a reserved channel */ DMACH_MAX, }; diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 058e096..0c386fc 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -84,6 +84,15 @@ struct s3c_sdhci_platdata { void __iomem *regbase, struct mmc_ios *ios, struct mmc_card *card); + void (*adjust_cfg_card)(struct s3c_sdhci_platdata *pdata, void __iomem *regbase, int rw); + int rx_cfg; + int tx_cfg; + + /* add to deal with non-removable device */ + int built_in; + + int must_maintain_clock; + int enable_intr_on_resume; }; /** @@ -94,6 +103,7 @@ struct s3c_sdhci_platdata { * The call will copy the platform data, so the board definitions can * make the structure itself __initdata. */ +extern void s3c_sdhci_set_platdata(void); extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd); @@ -289,9 +299,10 @@ static inline void s5pc100_default_sdhci2(void) { } extern char *s5pv210_hsmmc_clksrcs[4]; extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); +extern void s5pv210_adjust_sdhci_cfg_card(struct s3c_sdhci_platdata *pdata, void __iomem *r, int rw); static inline void s5pv210_default_sdhci0(void) { @@ -299,6 +310,7 @@ static inline void s5pv210_default_sdhci0(void) s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; + s3c_hsmmc0_def_platdata.adjust_cfg_card = s5pv210_adjust_sdhci_cfg_card; #endif } @@ -308,6 +320,7 @@ static inline void s5pv210_default_sdhci1(void) s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; + s3c_hsmmc1_def_platdata.adjust_cfg_card = s5pv210_adjust_sdhci_cfg_card; #endif } @@ -317,6 +330,7 @@ static inline void s5pv210_default_sdhci2(void) s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; + s3c_hsmmc2_def_platdata.adjust_cfg_card = s5pv210_adjust_sdhci_cfg_card; #endif } @@ -326,6 +340,7 @@ static inline void s5pv210_default_sdhci3(void) s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; + s3c_hsmmc3_def_platdata.adjust_cfg_card = s5pv210_adjust_sdhci_cfg_card; #endif } @@ -390,4 +405,6 @@ static inline void exynos4_default_sdhci3(void) { } #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ +extern void sdhci_s3c_force_presence_change(struct platform_device *pdev); + #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h index 54b762a..632e1ed 100644 --- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h +++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h @@ -13,24 +13,18 @@ #include <plat/regs-watchdog.h> #include <mach/map.h> +#include <linux/kernel.h> #include <linux/clk.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> static inline void arch_wdt_reset(void) { - struct clk *wdtclk; - printk("arch_reset: attempting watchdog reset\n"); __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - wdtclk = clk_get(NULL, "watchdog"); - if (!IS_ERR(wdtclk)) { - clk_enable(wdtclk); - } else - printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); - /* put initial values into count and data */ __raw_writel(0x80, S3C2410_WTCNT); __raw_writel(0x80, S3C2410_WTDAT); diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 9652820..f7dccb0 100644..100755 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -27,6 +27,9 @@ #define OFFS_CON (0x00) #define OFFS_DAT (0x04) #define OFFS_UP (0x08) +#define OFFS_DRV (0x0C) +#define OFFS_CONPDN (0x10) +#define OFFS_PUDPDN (0x14) static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip) { @@ -198,6 +201,9 @@ static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); + chip->pm_save[4] = __raw_readl(chip->base + OFFS_DRV); + chip->pm_save[5] = __raw_readl(chip->base + OFFS_CONPDN); + chip->pm_save[6] = __raw_readl(chip->base + OFFS_PUDPDN); if (chip->chip.ngpio > 8) chip->pm_save[0] = __raw_readl(chip->base - 4); @@ -284,6 +290,9 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) __raw_writel(chip->pm_save[2], base + OFFS_DAT); __raw_writel(chip->pm_save[3], base + OFFS_UP); + __raw_writel(chip->pm_save[4], base + OFFS_DRV); + __raw_writel(chip->pm_save[5], base + OFFS_CONPDN); + __raw_writel(chip->pm_save[6], base + OFFS_PUDPDN); if (chip->chip.ngpio > 8) { S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n", diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 5c0a440..b351133 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -26,15 +26,87 @@ #include <plat/regs-serial.h> #include <mach/regs-clock.h> #include <mach/regs-irq.h> +#include <asm/fiq_glue.h> #include <asm/irq.h> #include <plat/pm.h> +#include <plat/irq-eint-group.h> #include <mach/pm-core.h> /* for external use */ unsigned long s3c_pm_flags; +/* ---------------------------------------------- */ +extern unsigned int pm_debug_scratchpad; +#include <linux/slab.h> +#include <linux/debugfs.h> +#include <linux/uaccess.h> +#include <linux/module.h> + +#define PMSTATS_MAGIC "*PM*DEBUG*STATS*" + +struct pmstats { + char magic[16]; + unsigned sleep_count; + unsigned wake_count; + unsigned sleep_freq; + unsigned wake_freq; +}; + +static struct pmstats *pmstats; +static struct pmstats *pmstats_last; + +static ssize_t pmstats_read(struct file *file, char __user *buf, + size_t len, loff_t *offset) +{ + if (*offset != 0) + return 0; + if (len > 4096) + len = 4096; + + if (copy_to_user(buf, file->private_data, len)) + return -EFAULT; + + *offset += len; + return len; +} + +static int pmstats_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static const struct file_operations pmstats_ops = { + .owner = THIS_MODULE, + .read = pmstats_read, + .open = pmstats_open, +}; + +void __init pmstats_init(void) +{ + pr_info("pmstats at %08x\n", pm_debug_scratchpad); + if (pm_debug_scratchpad) + pmstats = ioremap(pm_debug_scratchpad, 4096); + else + pmstats = kzalloc(4096, GFP_ATOMIC); + + if (!memcmp(pmstats->magic, PMSTATS_MAGIC, 16)) { + pmstats_last = kzalloc(4096, GFP_ATOMIC); + if (pmstats_last) + memcpy(pmstats_last, pmstats, 4096); + } + + memset(pmstats, 0, 4096); + memcpy(pmstats->magic, PMSTATS_MAGIC, 16); + + debugfs_create_file("pmstats", 0444, NULL, pmstats, &pmstats_ops); + if (pmstats_last) + debugfs_create_file("pmstats_last", 0444, NULL, pmstats_last, &pmstats_ops); +} +/* ---------------------------------------------- */ + /* Debug code: * * This code supports debug output to the low level UARTs for use on @@ -185,12 +257,8 @@ void s3c_pm_do_save(struct sleep_save *ptr, int count) void s3c_pm_do_restore(struct sleep_save *ptr, int count) { - for (; count > 0; count--, ptr++) { - printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", - ptr->reg, ptr->val, __raw_readl(ptr->reg)); - + for (; count > 0; count--, ptr++) __raw_writel(ptr->val, ptr->reg); - } } /** @@ -232,6 +300,7 @@ static void __maybe_unused s3c_pm_show_resume_irqs(int start, void (*pm_cpu_prep)(void); void (*pm_cpu_sleep)(void); +void (*pm_cpu_restore)(void); #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) @@ -271,6 +340,7 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_save_uarts(); s3c_pm_save_core(); + /* set the irq configuration for wake */ s3c_pm_configure_extint(); @@ -290,6 +360,9 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_check_store(); + /* clear wakeup_stat register for next wakeup reason */ + __raw_writel(__raw_readl(S5P_WAKEUP_STAT), S5P_WAKEUP_STAT); + /* send the cpu to sleep... */ s3c_pm_arch_stop_clocks(); @@ -298,20 +371,31 @@ static int s3c_pm_enter(suspend_state_t state) * we resume as it saves its own register state and restores it * during the resume. */ + pmstats->sleep_count++; + pmstats->sleep_freq = __raw_readl(S5P_CLK_DIV0); s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET); + pmstats->wake_count++; + pmstats->wake_freq = __raw_readl(S5P_CLK_DIV0); /* restore the cpu state using the kernel's cpu init code. */ cpu_init(); - /* restore the system state */ + fiq_glue_resume(); + local_fiq_enable(); s3c_pm_restore_core(); s3c_pm_restore_uarts(); s3c_pm_restore_gpios(); + s5pv210_restore_eint_group(); s3c_pm_debug_init(); + /* restore the system state */ + + if (pm_cpu_restore) + pm_cpu_restore(); + /* check what irq (if any) restored the system */ s3c_pm_arch_show_resume_irqs(); @@ -359,6 +443,7 @@ static const struct platform_suspend_ops s3c_pm_ops = { int __init s3c_pm_init(void) { printk("S3C Power Management, Copyright 2004 Simtec Electronics\n"); + pmstats_init(); suspend_set_ops(&s3c_pm_ops); return 0; diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c index f37457c..84723bd 100644 --- a/arch/arm/plat-samsung/pwm.c +++ b/arch/arm/plat-samsung/pwm.c @@ -44,6 +44,7 @@ struct pwm_device { #define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) static struct clk *clk_scaler[2]; +static DEFINE_SPINLOCK(pwm_spin_lock); static inline int pwm_is_tdiv(struct pwm_device *pwm) { @@ -108,15 +109,21 @@ int pwm_enable(struct pwm_device *pwm) unsigned long flags; unsigned long tcon; - local_irq_save(flags); + spin_lock_irqsave(&pwm_spin_lock, flags); - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_start(pwm); - __raw_writel(tcon, S3C2410_TCON); + if (!pwm->running) { + clk_enable(pwm->clk); + clk_enable(pwm->clk_div); - local_irq_restore(flags); + tcon = __raw_readl(S3C2410_TCON); + tcon |= pwm_tcon_start(pwm); + __raw_writel(tcon, S3C2410_TCON); + + pwm->running = 1; + } + + spin_unlock_irqrestore(&pwm_spin_lock, flags); - pwm->running = 1; return 0; } @@ -127,15 +134,20 @@ void pwm_disable(struct pwm_device *pwm) unsigned long flags; unsigned long tcon; - local_irq_save(flags); + spin_lock_irqsave(&pwm_spin_lock, flags); - tcon = __raw_readl(S3C2410_TCON); - tcon &= ~pwm_tcon_start(pwm); - __raw_writel(tcon, S3C2410_TCON); + if (pwm->running) { + tcon = __raw_readl(S3C2410_TCON); + tcon &= ~pwm_tcon_start(pwm); + __raw_writel(tcon, S3C2410_TCON); - local_irq_restore(flags); + clk_disable(pwm->clk); + clk_disable(pwm->clk_div); - pwm->running = 0; + pwm->running = 0; + } + + spin_unlock_irqrestore(&pwm_spin_lock, flags); } EXPORT_SYMBOL(pwm_disable); @@ -185,6 +197,9 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) /* The TCMP and TCNT can be read without a lock, they're not * shared between the timers. */ + clk_enable(pwm->clk); + clk_enable(pwm->clk_div); + tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id)); tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id)); @@ -227,7 +242,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) /* Update the PWM register block. */ - local_irq_save(flags); + spin_lock_irqsave(&pwm_spin_lock, flags); __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id)); __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id)); @@ -240,9 +255,13 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) tcon &= ~pwm_tcon_manulupdate(pwm); __raw_writel(tcon, S3C2410_TCON); - local_irq_restore(flags); + spin_unlock_irqrestore(&pwm_spin_lock, flags); + + clk_disable(pwm->clk); + clk_disable(pwm->clk_div); return 0; + } EXPORT_SYMBOL(pwm_config); @@ -299,14 +318,13 @@ static int s3c_pwm_probe(struct platform_device *pdev) goto err_clk_tin; } - local_irq_save(flags); + spin_lock_irqsave(&pwm_spin_lock, flags); tcon = __raw_readl(S3C2410_TCON); tcon |= pwm_tcon_invert(pwm); __raw_writel(tcon, S3C2410_TCON); - local_irq_restore(flags); - + spin_unlock_irqrestore(&pwm_spin_lock, flags); ret = pwm_register(pwm); if (ret) { diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c index f85638c..3b88d8f 100644 --- a/arch/arm/plat-samsung/s3c-pl330.c +++ b/arch/arm/plat-samsung/s3c-pl330.c @@ -747,8 +747,11 @@ int s3c2410_dma_request(enum dma_ch id, dmac = ch->dmac; + clk_enable(dmac->clk); + ch->pl330_chan_id = pl330_request_channel(dmac->pi); if (!ch->pl330_chan_id) { + clk_disable(dmac->clk); chan_release(ch); ret = -EBUSY; goto req_exit; @@ -860,7 +863,7 @@ int s3c2410_dma_free(enum dma_ch id, struct s3c2410_dma_client *client) pl330_release_channel(ch->pl330_chan_id); ch->pl330_chan_id = NULL; - + clk_disable(ch->dmac->clk); chan_release(ch); free_exit: @@ -986,6 +989,18 @@ int s3c2410_dma_devconfig(enum dma_ch id, enum s3c2410_dmasrc source, ch->rqcfg.src_inc = 1; ch->rqcfg.dst_inc = 0; break; + case S3C_DMA_MEM2MEM: + ch->req[0].rqtype = MEMTOMEM; + ch->req[1].rqtype = MEMTOMEM; + ch->rqcfg.src_inc = 1; + ch->rqcfg.dst_inc = 1; + break; + case S3C_DMA_MEM2MEM_SET: + ch->req[0].rqtype = MEMTOMEM; + ch->req[1].rqtype = MEMTOMEM; + ch->rqcfg.src_inc = 0; + ch->rqcfg.dst_inc = 1; + break; default: ret = -EINVAL; goto devcfg_exit; @@ -1131,6 +1146,7 @@ static int pl330_probe(struct platform_device *pdev) pl330_info->pcfg.data_bus_width / 8, pl330_info->pcfg.num_chan, pl330_info->pcfg.num_peri, pl330_info->pcfg.num_events); + clk_disable(s3c_pl330_dmac->clk); return 0; probe_err8: @@ -1156,7 +1172,7 @@ probe_err1: static int pl330_remove(struct platform_device *pdev) { struct s3c_pl330_dmac *dmac, *d; - struct s3c_pl330_chan *ch; + struct s3c_pl330_chan *ch, *cht; unsigned long flags; int del, found; @@ -1180,7 +1196,7 @@ static int pl330_remove(struct platform_device *pdev) dmac = d; /* Remove all Channels that are managed only by this DMAC */ - list_for_each_entry(ch, &chan_list, node) { + list_for_each_entry_safe(ch, cht, &chan_list, node) { /* Only channels that are handled by this DMAC */ if (iface_of_dmac(dmac, ch->id)) @@ -1205,7 +1221,6 @@ static int pl330_remove(struct platform_device *pdev) } /* Disable operation clock */ - clk_disable(dmac->clk); clk_put(dmac->clk); /* Remove the DMAC */ diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c index 2231d80..a16a57b 100644 --- a/arch/arm/plat-samsung/time.c +++ b/arch/arm/plat-samsung/time.c @@ -132,7 +132,9 @@ static unsigned long s3c2410_gettimeoffset (void) static irqreturn_t s3c2410_timer_interrupt(int irq, void *dev_id) { +#ifndef CONFIG_GENERIC_CLOCKEVENTS timer_tick(); +#endif return IRQ_HANDLED; } diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 4fa9903..c1a9784 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -10,7 +10,7 @@ * * Basic entry code, called from the kernel's undefined instruction trap. * r0 = faulted instruction - * r5 = faulted PC+4 + * r2 = faulted PC+4 * r9 = successful return * r10 = thread_info structure * lr = failure return @@ -26,6 +26,7 @@ ENTRY(do_vfp) str r11, [r10, #TI_PREEMPT] #endif enable_irq + str r2, [sp, #S_PC] @ update regs->ARM_pc for Thumb 2 case ldr r4, .LCvfp ldr r11, [r10, #TI_CPU] @ CPU number add r10, r10, #TI_VFPSTATE @ r10 = workspace diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 9897dcf..404538a 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -77,15 +77,12 @@ ENTRY(vfp_support_entry) bne look_for_VFP_exceptions @ VFP is already enabled DBGSTR1 "enable %x", r10 - ldr r3, last_VFP_context_address + ldr r3, vfp_current_hw_state_address orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set - ldr r4, [r3, r11, lsl #2] @ last_VFP_context pointer + ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled - cmp r4, r10 - beq check_for_exception @ we are returning to the same - @ process, so the registers are - @ still there. In this case, we do - @ not want to drop a pending exception. + cmp r4, r10 @ this thread owns the hw context? + beq vfp_hw_state_valid VFPFMXR FPEXC, r5 @ enable VFP, disable any pending @ exceptions, so we can get at the @@ -116,7 +113,7 @@ ENTRY(vfp_support_entry) no_old_VFP_process: DBGSTR1 "load state %p", r10 - str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer + str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer @ Load the saved state back into the VFP VFPFLDMIA r10, r5 @ reload the working registers while @ FPEXC is in a safe state @@ -132,7 +129,8 @@ no_old_VFP_process: #endif VFPFMXR FPSCR, r5 @ restore status -check_for_exception: +@ The context stored in the VFP hardware is up to date with this thread +vfp_hw_state_valid: tst r1, #FPEXC_EX bne process_exception @ might as well handle the pending @ exception before retrying branch @@ -207,8 +205,8 @@ ENTRY(vfp_save_state) ENDPROC(vfp_save_state) .align -last_VFP_context_address: - .word last_VFP_context +vfp_current_hw_state_address: + .word vfp_current_hw_state .macro tbl_branch, base, tmp, shift #ifdef CONFIG_THUMB2_KERNEL diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index f25e7ec..78829fa 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -33,7 +33,13 @@ void vfp_support_entry(void); void vfp_null_entry(void); void (*vfp_vector)(void) = vfp_null_entry; -union vfp_state *last_VFP_context[NR_CPUS]; + +/* + * The pointer to the vfpstate structure of the thread which currently + * owns the context held in the VFP hardware, or NULL if the hardware + * context is invalid. + */ +union vfp_state *vfp_current_hw_state[NR_CPUS]; /* * Dual-use variable. @@ -57,12 +63,12 @@ static void vfp_thread_flush(struct thread_info *thread) /* * Disable VFP to ensure we initialize it first. We must ensure - * that the modification of last_VFP_context[] and hardware disable + * that the modification of vfp_current_hw_state[] and hardware disable * are done for the same CPU and without preemption. */ cpu = get_cpu(); - if (last_VFP_context[cpu] == vfp) - last_VFP_context[cpu] = NULL; + if (vfp_current_hw_state[cpu] == vfp) + vfp_current_hw_state[cpu] = NULL; fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); put_cpu(); } @@ -73,8 +79,8 @@ static void vfp_thread_exit(struct thread_info *thread) union vfp_state *vfp = &thread->vfpstate; unsigned int cpu = get_cpu(); - if (last_VFP_context[cpu] == vfp) - last_VFP_context[cpu] = NULL; + if (vfp_current_hw_state[cpu] == vfp) + vfp_current_hw_state[cpu] = NULL; put_cpu(); } @@ -129,9 +135,9 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) * case the thread migrates to a different CPU. The * restoring is done lazily. */ - if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) { - vfp_save_state(last_VFP_context[cpu], fpexc); - last_VFP_context[cpu]->hard.cpu = cpu; + if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) { + vfp_save_state(vfp_current_hw_state[cpu], fpexc); + vfp_current_hw_state[cpu]->hard.cpu = cpu; } /* * Thread migration, just force the reloading of the @@ -139,7 +145,7 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) * contain stale data. */ if (thread->vfpstate.hard.cpu != cpu) - last_VFP_context[cpu] = NULL; + vfp_current_hw_state[cpu] = NULL; #endif /* @@ -412,10 +418,16 @@ static int vfp_pm_suspend(void) /* disable, just in case */ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); + } else if (vfp_current_hw_state[ti->cpu]) { +#ifndef CONFIG_SMP + fmxr(FPEXC, fpexc | FPEXC_EN); + vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc); + fmxr(FPEXC, fpexc); +#endif } /* clear any information we had about last context state */ - memset(last_VFP_context, 0, sizeof(last_VFP_context)); + vfp_current_hw_state[ti->cpu] = NULL; return 0; } @@ -451,7 +463,7 @@ void vfp_sync_hwstate(struct thread_info *thread) * If the thread we're interested in is the current owner of the * hardware VFP state, then we need to save its state. */ - if (last_VFP_context[cpu] == &thread->vfpstate) { + if (vfp_current_hw_state[cpu] == &thread->vfpstate) { u32 fpexc = fmrx(FPEXC); /* @@ -473,7 +485,7 @@ void vfp_flush_hwstate(struct thread_info *thread) * If the thread we're interested in is the current owner of the * hardware VFP state, then we need to save its state. */ - if (last_VFP_context[cpu] == &thread->vfpstate) { + if (vfp_current_hw_state[cpu] == &thread->vfpstate) { u32 fpexc = fmrx(FPEXC); fmxr(FPEXC, fpexc & ~FPEXC_EN); @@ -482,7 +494,7 @@ void vfp_flush_hwstate(struct thread_info *thread) * Set the context to NULL to force a reload the next time * the thread uses the VFP. */ - last_VFP_context[cpu] = NULL; + vfp_current_hw_state[cpu] = NULL; } #ifdef CONFIG_SMP @@ -514,7 +526,7 @@ static int vfp_hotplug(struct notifier_block *b, unsigned long action, { if (action == CPU_DYING || action == CPU_DYING_FROZEN) { unsigned int cpu = (long)hcpu; - last_VFP_context[cpu] = NULL; + vfp_current_hw_state[cpu] = NULL; } else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) vfp_enable(NULL); return NOTIFY_OK; diff --git a/arch/x86/include/asm/idle.h b/arch/x86/include/asm/idle.h index f49253d7..f1e4268 100644 --- a/arch/x86/include/asm/idle.h +++ b/arch/x86/include/asm/idle.h @@ -1,13 +1,6 @@ #ifndef _ASM_X86_IDLE_H #define _ASM_X86_IDLE_H -#define IDLE_START 1 -#define IDLE_END 2 - -struct notifier_block; -void idle_notifier_register(struct notifier_block *n); -void idle_notifier_unregister(struct notifier_block *n); - #ifdef CONFIG_X86_64 void enter_idle(void); void exit_idle(void); diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index b01898d..eeb5004 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -56,31 +56,17 @@ asmlinkage extern void ret_from_fork(void); DEFINE_PER_CPU(unsigned long, old_rsp); static DEFINE_PER_CPU(unsigned char, is_idle); -static ATOMIC_NOTIFIER_HEAD(idle_notifier); - -void idle_notifier_register(struct notifier_block *n) -{ - atomic_notifier_chain_register(&idle_notifier, n); -} -EXPORT_SYMBOL_GPL(idle_notifier_register); - -void idle_notifier_unregister(struct notifier_block *n) -{ - atomic_notifier_chain_unregister(&idle_notifier, n); -} -EXPORT_SYMBOL_GPL(idle_notifier_unregister); - void enter_idle(void) { percpu_write(is_idle, 1); - atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); + idle_notifier_call_chain(IDLE_START); } static void __exit_idle(void) { if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) return; - atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); + idle_notifier_call_chain(IDLE_END); } /* Called from interrupts to signify idle end */ |