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-rw-r--r--sound/soc/Kconfig2
-rw-r--r--sound/soc/codecs/Kconfig3
-rw-r--r--sound/soc/codecs/Kconfig.voodoo60
-rw-r--r--sound/soc/codecs/Makefile13
-rw-r--r--sound/soc/codecs/wm8994.h265
-rw-r--r--sound/soc/codecs/wm8994_def.h9147
-rwxr-xr-xsound/soc/codecs/wm8994_herring.c3988
-rwxr-xr-xsound/soc/codecs/wm8994_samsung.c3219
-rwxr-xr-xsound/soc/codecs/wm8994_samsung.h207
-rw-r--r--sound/soc/codecs/wm8994_voodoo.c1872
-rw-r--r--sound/soc/codecs/wm8994_voodoo.h67
-rw-r--r--sound/soc/samsung/Kconfig20
-rw-r--r--sound/soc/samsung/Makefile7
-rw-r--r--sound/soc/samsung/dma.c25
-rw-r--r--sound/soc/samsung/dma.h2
-rw-r--r--sound/soc/samsung/herring-wm8994.c358
-rw-r--r--sound/soc/samsung/i2s.c65
-rw-r--r--sound/soc/samsung/s3c-dma-wrapper.c267
-rw-r--r--sound/soc/samsung/s3c-dma.c478
-rw-r--r--sound/soc/samsung/s3c-dma.h33
-rw-r--r--sound/soc/samsung/s3c-idma.c533
-rw-r--r--sound/soc/samsung/s3c-idma.h37
-rw-r--r--sound/soc/samsung/s5p-i2s_sec.c355
-rw-r--r--sound/soc/samsung/s5pc1xx-i2s.c1152
-rw-r--r--sound/soc/samsung/s5pc1xx-i2s.h124
25 files changed, 22146 insertions, 153 deletions
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 8224db5..fbcd4f9 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -58,6 +58,8 @@ source "sound/soc/sh/Kconfig"
source "sound/soc/tegra/Kconfig"
source "sound/soc/txx9/Kconfig"
+source "sound/soc/codecs/Kconfig.voodoo"
+
# Supported codecs
source "sound/soc/codecs/Kconfig"
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 98175a0..abfd23b 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -356,6 +356,9 @@ config SND_SOC_WM8993
config SND_SOC_WM8994
tristate
+config SND_SOC_WM8994_SAMSUNG
+ tristate
+
config SND_SOC_WM8995
tristate
diff --git a/sound/soc/codecs/Kconfig.voodoo b/sound/soc/codecs/Kconfig.voodoo
new file mode 100644
index 0000000..6672bed
--- /dev/null
+++ b/sound/soc/codecs/Kconfig.voodoo
@@ -0,0 +1,60 @@
+menuconfig SND_VOODOO
+ bool "Voodoo sound driver"
+ depends on SND_UNIVERSAL_WM8994 || SND_S3C24XX_SOC || SND_SOC_WM8994_P3 || SND_SOC_SAMSUNG_HERRING_WM8994
+ default y
+ help
+ With this option enabled, the kernel compile an additionnal driver
+ that extend the existing sound driver
+
+config SND_VOODOO_HP_LEVEL_CONTROL
+ bool "Add headphone amplifier level control"
+ depends on SND_VOODOO
+ default y
+ help
+ Adds a control allowing to adjust the analog gain of the headphone
+ amplifier
+
+config SND_VOODOO_HP_LEVEL
+ int "default level at boot 0-62"
+ depends on SND_VOODOO_HP_LEVEL_CONTROL
+ default 54 if MACH_HERRING=y || M110S=y
+ default 47
+ range 0 62
+ help
+ Default headphone amplifier level. Take care not setting it to high,
+ it would introduce hiss for people not using the control app
+
+config SND_VOODOO_RECORD_PRESETS
+ bool "Microphone recording presets"
+ depends on SND_VOODOO
+ default y
+ help
+ Recording presets with Dynamic Range Compression auto-gain
+ on microphone:
+ - Original
+ - High sensitivity
+ - Balanced (recommanded, default)
+ - Loud environment - concert
+
+config SND_VOODOO_FM
+ bool "FM radio: frequency response and levels optimizations"
+ depends on SND_VOODOO && ARIES_EUR
+ default n
+ help
+ Adds a control to enable or disable the high-pass filter on FM radio
+
+config SND_VOODOO_MODULE
+ tristate "Build also as module (incomplete)"
+ depends on SND_VOODOO && m && n
+ default n
+ help
+ requires additionnal source
+
+config SND_VOODOO_DEVELOPMENT
+ bool "Codec development tools (unsafe)"
+ depends on SND_VOODOO
+ default n
+ help
+ Allow to codec dump registers and load register-address/value batchs
+ Powerful but also dangerous tool
+
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index fd85584..fa6ba22 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -73,8 +73,14 @@ snd-soc-wm8988-objs := wm8988.o
snd-soc-wm8990-objs := wm8990.o
snd-soc-wm8991-objs := wm8991.o
snd-soc-wm8993-objs := wm8993.o
-snd-soc-wm8994-objs := wm8994.o wm8994-tables.o wm8958-dsp2.o
snd-soc-wm8995-objs := wm8995.o
+ifeq ($(CONFIG_SND_VOODOO),y)
+snd-soc-wm8994-objs := wm8994_samsung.o wm8994_herring.o wm8994_voodoo.o
+snd-soc-wm8994-samsung-objs := wm8994_samsung.o wm8994_herring.o wm8994_voodoo.o
+else
+snd-soc-wm8994-objs := wm8994.o wm8994-tables.o wm8958-dsp2.o
+snd-soc-wm8994-samsung-objs := wm8994_samsung.o wm8994_herring.o
+endif
snd-soc-wm9081-objs := wm9081.o
snd-soc-wm9705-objs := wm9705.o
snd-soc-wm9712-objs := wm9712.o
@@ -166,6 +172,7 @@ obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
obj-$(CONFIG_SND_SOC_WM8991) += snd-soc-wm8991.o
obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o
obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o
+obj-$(CONFIG_SND_SOC_WM8994_SAMSUNG) += snd-soc-wm8994-samsung.o
obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o
obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o
obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o
@@ -179,3 +186,7 @@ obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o
obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o
obj-$(CONFIG_SND_SOC_WM9090) += snd-soc-wm9090.o
+
+ifeq ($(CONFIG_SND_VOODOO_MODULE),m)
+obj-$(CONFIG_SND_VOODOO_MODULE) += voodoo-sound-tegrak-module/
+endif
diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h
index 0a1db04..13257dc 100644
--- a/sound/soc/codecs/wm8994.h
+++ b/sound/soc/codecs/wm8994.h
@@ -1,145 +1,120 @@
-/*
- * wm8994.h -- WM8994 Soc Audio driver
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _WM8994_H
-#define _WM8994_H
-
-#include <sound/soc.h>
-#include <linux/firmware.h>
-
-#include "wm_hubs.h"
-
-/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
-#define WM8994_SYSCLK_MCLK1 1
-#define WM8994_SYSCLK_MCLK2 2
-#define WM8994_SYSCLK_FLL1 3
-#define WM8994_SYSCLK_FLL2 4
-
-/* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */
-#define WM8994_SYSCLK_OPCLK 5
-
-#define WM8994_FLL1 1
-#define WM8994_FLL2 2
-
-#define WM8994_FLL_SRC_MCLK1 1
-#define WM8994_FLL_SRC_MCLK2 2
-#define WM8994_FLL_SRC_LRCLK 3
-#define WM8994_FLL_SRC_BCLK 4
-
-typedef void (*wm8958_micdet_cb)(u16 status, void *data);
-
-int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
- int micbias, int det, int shrt);
-int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
- wm8958_micdet_cb cb, void *cb_data);
-
-#define WM8994_CACHE_SIZE 1570
-
-struct wm8994_access_mask {
- unsigned short readable; /* Mask of readable bits */
- unsigned short writable; /* Mask of writable bits */
-};
-
-extern const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE];
-extern const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE];
-
-int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
- struct snd_kcontrol *kcontrol, int event);
-
-void wm8958_dsp2_init(struct snd_soc_codec *codec);
-
-struct wm8994_micdet {
- struct snd_soc_jack *jack;
- int det;
- int shrt;
-};
-
-/* codec private data */
-struct wm8994_fll_config {
- int src;
- int in;
- int out;
-};
-
-#define WM8994_NUM_DRC 3
-#define WM8994_NUM_EQ 3
-
-struct wm8994_priv {
- struct wm_hubs_data hubs;
- enum snd_soc_control_type control_type;
- void *control_data;
- struct snd_soc_codec *codec;
- int sysclk[2];
- int sysclk_rate[2];
- int mclk[2];
- int aifclk[2];
- struct wm8994_fll_config fll[2], fll_suspend[2];
-
- int dac_rates[2];
- int lrclk_shared[2];
-
- int mbc_ena[3];
- int hpf1_ena[3];
- int hpf2_ena[3];
- int vss_ena[3];
- int enh_eq_ena[3];
-
- /* Platform dependant DRC configuration */
- const char **drc_texts;
- int drc_cfg[WM8994_NUM_DRC];
- struct soc_enum drc_enum;
-
- /* Platform dependant ReTune mobile configuration */
- int num_retune_mobile_texts;
- const char **retune_mobile_texts;
- int retune_mobile_cfg[WM8994_NUM_EQ];
- struct soc_enum retune_mobile_enum;
-
- /* Platform dependant MBC configuration */
- int mbc_cfg;
- const char **mbc_texts;
- struct soc_enum mbc_enum;
-
- /* Platform dependant VSS configuration */
- int vss_cfg;
- const char **vss_texts;
- struct soc_enum vss_enum;
-
- /* Platform dependant VSS HPF configuration */
- int vss_hpf_cfg;
- const char **vss_hpf_texts;
- struct soc_enum vss_hpf_enum;
-
- /* Platform dependant enhanced EQ configuration */
- int enh_eq_cfg;
- const char **enh_eq_texts;
- struct soc_enum enh_eq_enum;
-
- struct wm8994_micdet micdet[2];
-
- wm8958_micdet_cb jack_cb;
- void *jack_cb_data;
- int micdet_irq;
-
- int revision;
- struct wm8994_pdata *pdata;
-
- unsigned int aif1clk_enable:1;
- unsigned int aif2clk_enable:1;
-
- unsigned int aif1clk_disable:1;
- unsigned int aif2clk_disable:1;
-
- int dsp_active;
- const struct firmware *cur_fw;
- const struct firmware *mbc;
- const struct firmware *mbc_vss;
- const struct firmware *enh_eq;
-};
-
-#endif
+/*
+ * wm8994.h -- WM8994 Soc Audio driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8994_H
+#define _WM8994_H
+
+#include <sound/soc.h>
+
+extern struct snd_soc_codec_device soc_codec_dev_wm8994;
+// We don't use array - DW Shim.
+//extern struct snd_soc_dai wm8994_dai[];
+
+/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
+#define WM8994_SYSCLK_MCLK1 1
+#define WM8994_SYSCLK_MCLK2 2
+#define WM8994_SYSCLK_FLL1 3
+#define WM8994_SYSCLK_FLL2 4
+
+#define WM8994_FLL1 1
+#define WM8994_FLL2 2
+
+//-----------------------------------------------------------
+// Added belows codes by Samsung Electronics.
+
+#include "wm8994_def.h"
+
+extern struct snd_soc_dai wm8994_dai;
+
+#define WM8994_SYSCLK_MCLK 1
+#define WM8994_SYSCLK_FLL 2
+
+#define AUDIO_COMMON_DEBUG 0
+//#define WM8994_REGISTER_DUMP
+#if defined CONFIG_SND_SOC_WM8994_PCM
+#define ATTACH_ADDITINAL_PCM_DRIVER // for VT call.
+#endif
+//------------------------------------------------
+// Definitions of enum type
+//------------------------------------------------
+enum audio_path { OFF, RCV, SPK, HP, BT, SPK_HP};
+enum mic_path { MAIN, SUB, MIC_OFF};
+enum fmradio_audio_path { FMR_OFF, FMR_SPK, FMR_HP, FMR_SPK_MIX, FMR_HP_MIX, FMR_SPK_HP_MIX};
+enum call_state { DISCONNECT, CONNECT};
+enum power_state { CODEC_OFF, CODEC_ON };
+enum mic_state { MIC_NO_USE, MIC_USE};
+
+typedef void (*select_route)(struct snd_soc_codec *);
+typedef void (*select_mic_route)(struct snd_soc_codec *);
+
+struct wm8994_setup_data {
+ int i2c_bus;
+ unsigned short i2c_address;
+};
+
+struct wm8994_priv {
+ //u16 reg_cache[WM8994_REGISTER_COUNT];
+ struct snd_soc_codec codec;
+ int master;
+ int sysclk_source;
+ unsigned int mclk_rate;
+ unsigned int sysclk_rate;
+ unsigned int fs;
+ unsigned int bclk;
+ unsigned int hw_version; // For wolfson H/W version. 1 = Rev B, 3 = Rev D
+ enum audio_path cur_path;
+ enum mic_path rec_path;
+ enum fmradio_audio_path fmradio_path;
+ enum call_state call_state;
+ enum power_state power_state;
+ enum mic_state mic_state;
+ select_route *universal_playback_path;
+ select_route *universal_voicecall_path;
+ select_mic_route *universal_mic_path;
+ int testmode_config_flag; // for testmode.
+};
+
+#if AUDIO_COMMON_DEBUG
+#define DEBUG_LOG(format,...)\
+ printk ("[ "SUBJECT " (%s,%d) ] " format "\n", __func__, __LINE__, ## __VA_ARGS__);
+#else
+#define DEBUG_LOG(format,...)
+#endif
+
+#define DEBUG_LOG_ERR(format,...)\
+ printk (KERN_ERR "[ "SUBJECT " (%s,%d) ] " format "\n", __func__, __LINE__, ## __VA_ARGS__);
+
+// Definitions of function prototype.
+inline unsigned int wm8994_read(struct snd_soc_codec *codec,unsigned int reg);
+int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value);
+int audio_init(void);
+int audio_power(int en);
+void audio_ctrl_mic_bias_gpio(int enable);
+void wm8994_set_off(struct snd_soc_codec *codec);
+void wm8994_disable_playback_path(struct snd_soc_codec *codec, enum audio_path path);
+void wm8994_disable_fmradio_path(struct snd_soc_codec *codec, enum fmradio_audio_path path);
+void wm8994_disable_rec_path(struct snd_soc_codec *codec,enum mic_path rec_path);
+void wm8994_record_main_mic( struct snd_soc_codec *codec);
+void wm8994_record_headset_mic( struct snd_soc_codec *codec);
+void wm8994_set_playback_receiver(struct snd_soc_codec *codec);
+void wm8994_set_playback_headset(struct snd_soc_codec *codec);
+void wm8994_set_playback_speaker(struct snd_soc_codec *codec);
+void wm8994_set_playback_speaker_headset(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_receiver(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_headset(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_speaker(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_bluetooth(struct snd_soc_codec *codec);
+void wm8994_set_fmradio_headset(struct snd_soc_codec *codec);
+void wm8994_set_fmradio_speaker(struct snd_soc_codec *codec);
+void wm8994_set_fmradio_headset_mix(struct snd_soc_codec *codec);
+void wm8994_set_fmradio_speaker_mix(struct snd_soc_codec *codec);
+void wm8994_set_fmradio_speaker_headset_mix(struct snd_soc_codec *codec);
+#if defined WM8994_REGISTER_DUMP
+void wm8994_register_dump(struct snd_soc_codec *codec);
+#endif
+#endif
diff --git a/sound/soc/codecs/wm8994_def.h b/sound/soc/codecs/wm8994_def.h
new file mode 100644
index 0000000..a375950
--- /dev/null
+++ b/sound/soc/codecs/wm8994_def.h
@@ -0,0 +1,9147 @@
+/*
+ * wm8994_def.h -- WM8994 ALSA Soc Audio driver
+ *
+ * Copyright 2010 Samsung Electronics.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Note :
+ * Definitions of WM8994 Register names and values.
+ */
+
+/*
+ * Register values.
+ */
+#define WM8994_SOFTWARE_RESET 0x00
+#define WM8994_POWER_MANAGEMENT_1 0x01
+#define WM8994_POWER_MANAGEMENT_2 0x02
+#define WM8994_POWER_MANAGEMENT_3 0x03
+#define WM8994_POWER_MANAGEMENT_4 0x04
+#define WM8994_POWER_MANAGEMENT_5 0x05
+#define WM8994_POWER_MANAGEMENT_6 0x06
+#define WM8994_INPUT_MIXER_1 0x15
+#define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18
+#define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19
+#define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
+#define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
+#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
+#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
+#define WM8994_LINE_OUTPUTS_VOLUME 0x1E
+#define WM8994_HPOUT2_VOLUME 0x1F
+#define WM8994_LEFT_OPGA_VOLUME 0x20
+#define WM8994_RIGHT_OPGA_VOLUME 0x21
+#define WM8994_SPKMIXL_ATTENUATION 0x22
+#define WM8994_SPKMIXR_ATTENUATION 0x23
+#define WM8994_SPKOUT_MIXERS 0x24
+#define WM8994_CLASSD 0x25
+#define WM8994_SPEAKER_VOLUME_LEFT 0x26
+#define WM8994_SPEAKER_VOLUME_RIGHT 0x27
+#define WM8994_INPUT_MIXER_2 0x28
+#define WM8994_INPUT_MIXER_3 0x29
+#define WM8994_INPUT_MIXER_4 0x2A
+#define WM8994_INPUT_MIXER_5 0x2B
+#define WM8994_INPUT_MIXER_6 0x2C
+#define WM8994_OUTPUT_MIXER_1 0x2D
+#define WM8994_OUTPUT_MIXER_2 0x2E
+#define WM8994_OUTPUT_MIXER_3 0x2F
+#define WM8994_OUTPUT_MIXER_4 0x30
+#define WM8994_OUTPUT_MIXER_5 0x31
+#define WM8994_OUTPUT_MIXER_6 0x32
+#define WM8994_HPOUT2_MIXER 0x33
+#define WM8994_LINE_MIXER_1 0x34
+#define WM8994_LINE_MIXER_2 0x35
+#define WM8994_SPEAKER_MIXER 0x36
+#define WM8994_ADDITIONAL_CONTROL 0x37
+#define WM8994_ANTIPOP_1 0x38
+#define WM8994_ANTIPOP_2 0x39
+#define WM8994_MICBIAS 0x3A
+#define WM8994_LDO_1 0x3B
+#define WM8994_LDO_2 0x3C
+#define WM8994_CHARGE_PUMP_1 0x4C
+#define WM8994_CLASS_W_1 0x51
+#define WM8994_DC_SERVO_1 0x54
+#define WM8994_DC_SERVO_2 0x55
+#define WM8994_DC_SERVO_4 0x57
+#define WM8994_DC_SERVO_READBACK 0x58
+#define WM8994_DC_SERVO_ANA_1 0x5B
+#define WM8994_DC_SERVO_ANA_2 0x5C
+#define WM8994_ANALOGUE_HP_1 0x60
+#define WM8958_MIC_DETECT_1 0xD0
+#define WM8958_MIC_DETECT_2 0xD1
+#define WM8958_MIC_DETECT_3 0xD2
+#define WM8994_CHIP_REVISION 0x100
+#define WM8994_CONTROL_INTERFACE 0x101
+#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110
+#define WM8994_WRITE_SEQUENCER_CTRL_2 0x111
+#define WM8994_AIF1_CLOCKING_1 0x200
+#define WM8994_AIF1_CLOCKING_2 0x201
+#define WM8994_AIF2_CLOCKING_1 0x204
+#define WM8994_AIF2_CLOCKING_2 0x205
+#define WM8994_CLOCKING_1 0x208
+#define WM8994_CLOCKING_2 0x209
+#define WM8994_AIF1_RATE 0x210
+#define WM8994_AIF2_RATE 0x211
+#define WM8994_RATE_STATUS 0x212
+#define WM8994_FLL1_CONTROL_1 0x220
+#define WM8994_FLL1_CONTROL_2 0x221
+#define WM8994_FLL1_CONTROL_3 0x222
+#define WM8994_FLL1_CONTROL_4 0x223
+#define WM8994_FLL1_CONTROL_5 0x224
+#define WM8994_FLL2_CONTROL_1 0x240
+#define WM8994_FLL2_CONTROL_2 0x241
+#define WM8994_FLL2_CONTROL_3 0x242
+#define WM8994_FLL2_CONTROL_4 0x243
+#define WM8994_FLL2_CONTROL_5 0x244
+#define WM8994_AIF1_CONTROL_1 0x300
+#define WM8994_AIF1_CONTROL_2 0x301
+#define WM8994_AIF1_MASTER_SLAVE 0x302
+#define WM8994_AIF1_BCLK 0x303
+#define WM8994_AIF1ADC_LRCLK 0x304
+#define WM8994_AIF1DAC_LRCLK 0x305
+#define WM8994_AIF1DAC_DATA 0x306
+#define WM8994_AIF1ADC_DATA 0x307
+#define WM8994_AIF2_CONTROL_1 0x310
+#define WM8994_AIF2_CONTROL_2 0x311
+#define WM8994_AIF2_MASTER_SLAVE 0x312
+#define WM8994_AIF2_BCLK 0x313
+#define WM8994_AIF2ADC_LRCLK 0x314
+#define WM8994_AIF2DAC_LRCLK 0x315
+#define WM8994_AIF2DAC_DATA 0x316
+#define WM8994_AIF2ADC_DATA 0x317
+#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400
+#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401
+#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402
+#define WM8994_AIF1_DAC1_RIGHT_VOLUME 0x403
+#define WM8994_AIF1_ADC2_LEFT_VOLUME 0x404
+#define WM8994_AIF1_ADC2_RIGHT_VOLUME 0x405
+#define WM8994_AIF1_DAC2_LEFT_VOLUME 0x406
+#define WM8994_AIF1_DAC2_RIGHT_VOLUME 0x407
+#define WM8994_AIF1_ADC1_FILTERS 0x410
+#define WM8994_AIF1_ADC2_FILTERS 0x411
+#define WM8994_AIF1_DAC1_FILTERS_1 0x420
+#define WM8994_AIF1_DAC1_FILTERS_2 0x421
+#define WM8994_AIF1_DAC2_FILTERS_1 0x422
+#define WM8994_AIF1_DAC2_FILTERS_2 0x423
+#define WM8994_AIF1_DRC1_1 0x440
+#define WM8994_AIF1_DRC1_2 0x441
+#define WM8994_AIF1_DRC1_3 0x442
+#define WM8994_AIF1_DRC1_4 0x443
+#define WM8994_AIF1_DRC1_5 0x444
+#define WM8994_AIF1_DRC2_1 0x450
+#define WM8994_AIF1_DRC2_2 0x451
+#define WM8994_AIF1_DRC2_3 0x452
+#define WM8994_AIF1_DRC2_4 0x453
+#define WM8994_AIF1_DRC2_5 0x454
+#define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480
+#define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481
+#define WM8994_AIF1_DAC1_EQ_BAND_1_A 0x482
+#define WM8994_AIF1_DAC1_EQ_BAND_1_B 0x483
+#define WM8994_AIF1_DAC1_EQ_BAND_1_PG 0x484
+#define WM8994_AIF1_DAC1_EQ_BAND_2_A 0x485
+#define WM8994_AIF1_DAC1_EQ_BAND_2_B 0x486
+#define WM8994_AIF1_DAC1_EQ_BAND_2_C 0x487
+#define WM8994_AIF1_DAC1_EQ_BAND_2_PG 0x488
+#define WM8994_AIF1_DAC1_EQ_BAND_3_A 0x489
+#define WM8994_AIF1_DAC1_EQ_BAND_3_B 0x48A
+#define WM8994_AIF1_DAC1_EQ_BAND_3_C 0x48B
+#define WM8994_AIF1_DAC1_EQ_BAND_3_PG 0x48C
+#define WM8994_AIF1_DAC1_EQ_BAND_4_A 0x48D
+#define WM8994_AIF1_DAC1_EQ_BAND_4_B 0x48E
+#define WM8994_AIF1_DAC1_EQ_BAND_4_C 0x48F
+#define WM8994_AIF1_DAC1_EQ_BAND_4_PG 0x490
+#define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491
+#define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492
+#define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493
+#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0
+#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1
+#define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2
+#define WM8994_AIF1_DAC2_EQ_BAND_1_B 0x4A3
+#define WM8994_AIF1_DAC2_EQ_BAND_1_PG 0x4A4
+#define WM8994_AIF1_DAC2_EQ_BAND_2_A 0x4A5
+#define WM8994_AIF1_DAC2_EQ_BAND_2_B 0x4A6
+#define WM8994_AIF1_DAC2_EQ_BAND_2_C 0x4A7
+#define WM8994_AIF1_DAC2_EQ_BAND_2_PG 0x4A8
+#define WM8994_AIF1_DAC2_EQ_BAND_3_A 0x4A9
+#define WM8994_AIF1_DAC2_EQ_BAND_3_B 0x4AA
+#define WM8994_AIF1_DAC2_EQ_BAND_3_C 0x4AB
+#define WM8994_AIF1_DAC2_EQ_BAND_3_PG 0x4AC
+#define WM8994_AIF1_DAC2_EQ_BAND_4_A 0x4AD
+#define WM8994_AIF1_DAC2_EQ_BAND_4_B 0x4AE
+#define WM8994_AIF1_DAC2_EQ_BAND_4_C 0x4AF
+#define WM8994_AIF1_DAC2_EQ_BAND_4_PG 0x4B0
+#define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1
+#define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2
+#define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
+#define WM8994_AIF2_ADC_LEFT_VOLUME 0x500
+#define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501
+#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
+#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
+#define WM8994_AIF2_ADC_FILTERS 0x510
+#define WM8994_AIF2_DAC_FILTERS_1 0x520
+#define WM8994_AIF2_DAC_FILTERS_2 0x521
+#define WM8994_AIF2_DRC_1 0x540
+#define WM8994_AIF2_DRC_2 0x541
+#define WM8994_AIF2_DRC_3 0x542
+#define WM8994_AIF2_DRC_4 0x543
+#define WM8994_AIF2_DRC_5 0x544
+#define WM8994_AIF2_EQ_GAINS_1 0x580
+#define WM8994_AIF2_EQ_GAINS_2 0x581
+#define WM8994_AIF2_EQ_BAND_1_A 0x582
+#define WM8994_AIF2_EQ_BAND_1_B 0x583
+#define WM8994_AIF2_EQ_BAND_1_PG 0x584
+#define WM8994_AIF2_EQ_BAND_2_A 0x585
+#define WM8994_AIF2_EQ_BAND_2_B 0x586
+#define WM8994_AIF2_EQ_BAND_2_C 0x587
+#define WM8994_AIF2_EQ_BAND_2_PG 0x588
+#define WM8994_AIF2_EQ_BAND_3_A 0x589
+#define WM8994_AIF2_EQ_BAND_3_B 0x58A
+#define WM8994_AIF2_EQ_BAND_3_C 0x58B
+#define WM8994_AIF2_EQ_BAND_3_PG 0x58C
+#define WM8994_AIF2_EQ_BAND_4_A 0x58D
+#define WM8994_AIF2_EQ_BAND_4_B 0x58E
+#define WM8994_AIF2_EQ_BAND_4_C 0x58F
+#define WM8994_AIF2_EQ_BAND_4_PG 0x590
+#define WM8994_AIF2_EQ_BAND_5_A 0x591
+#define WM8994_AIF2_EQ_BAND_5_B 0x592
+#define WM8994_AIF2_EQ_BAND_5_PG 0x593
+#define WM8994_DAC1_MIXER_VOLUMES 0x600
+#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
+#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
+#define WM8994_DAC2_MIXER_VOLUMES 0x603
+#define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604
+#define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605
+#define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606
+#define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607
+#define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608
+#define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609
+#define WM8994_DAC1_LEFT_VOLUME 0x610
+#define WM8994_DAC1_RIGHT_VOLUME 0x611
+#define WM8994_DAC2_LEFT_VOLUME 0x612
+#define WM8994_DAC2_RIGHT_VOLUME 0x613
+#define WM8994_DAC_SOFTMUTE 0x614
+#define WM8994_OVERSAMPLING 0x620
+#define WM8994_SIDETONE 0x621
+#define WM8994_GPIO_1 0x700
+#define WM8994_GPIO_2 0x701
+#define WM8994_GPIO_3 0x702
+#define WM8994_GPIO_4 0x703
+#define WM8994_GPIO_5 0x704
+#define WM8994_GPIO_6 0x705
+#define WM8994_GPIO_7 0x706
+#define WM8994_GPIO_8 0x707
+#define WM8994_GPIO_9 0x708
+#define WM8994_GPIO_10 0x709
+#define WM8994_GPIO_11 0x70A
+#define WM8994_DIGITAL_PULLS 0x720
+#define WM8994_INTERRUPT_STATUS_1 0x730
+#define WM8994_INTERRUPT_STATUS_2 0x731
+#define WM8994_INTERRUPT_STATUS_1_MASK 0x738
+#define WM8994_INTERRUPT_STATUS_2_MASK 0x739
+#define WM8994_INTERRUPT_CONTROL 0x740
+#define WM8994_IRQ_DEBOUNCE 0x748
+#define WM8994_IRQ_POLARITY 0x749
+#define WM8958_DSP2_EXECCONTROL 0xA0D
+#define WM8994_WRITE_SEQUENCER_0 0x3000
+#define WM8994_WRITE_SEQUENCER_1 0x3001
+#define WM8994_WRITE_SEQUENCER_2 0x3002
+#define WM8994_WRITE_SEQUENCER_3 0x3003
+#define WM8994_WRITE_SEQUENCER_4 0x3004
+#define WM8994_WRITE_SEQUENCER_5 0x3005
+#define WM8994_WRITE_SEQUENCER_6 0x3006
+#define WM8994_WRITE_SEQUENCER_7 0x3007
+#define WM8994_WRITE_SEQUENCER_8 0x3008
+#define WM8994_WRITE_SEQUENCER_9 0x3009
+#define WM8994_WRITE_SEQUENCER_10 0x300A
+#define WM8994_WRITE_SEQUENCER_11 0x300B
+#define WM8994_WRITE_SEQUENCER_12 0x300C
+#define WM8994_WRITE_SEQUENCER_13 0x300D
+#define WM8994_WRITE_SEQUENCER_14 0x300E
+#define WM8994_WRITE_SEQUENCER_15 0x300F
+#define WM8994_WRITE_SEQUENCER_16 0x3010
+#define WM8994_WRITE_SEQUENCER_17 0x3011
+#define WM8994_WRITE_SEQUENCER_18 0x3012
+#define WM8994_WRITE_SEQUENCER_19 0x3013
+#define WM8994_WRITE_SEQUENCER_20 0x3014
+#define WM8994_WRITE_SEQUENCER_21 0x3015
+#define WM8994_WRITE_SEQUENCER_22 0x3016
+#define WM8994_WRITE_SEQUENCER_23 0x3017
+#define WM8994_WRITE_SEQUENCER_24 0x3018
+#define WM8994_WRITE_SEQUENCER_25 0x3019
+#define WM8994_WRITE_SEQUENCER_26 0x301A
+#define WM8994_WRITE_SEQUENCER_27 0x301B
+#define WM8994_WRITE_SEQUENCER_28 0x301C
+#define WM8994_WRITE_SEQUENCER_29 0x301D
+#define WM8994_WRITE_SEQUENCER_30 0x301E
+#define WM8994_WRITE_SEQUENCER_31 0x301F
+#define WM8994_WRITE_SEQUENCER_32 0x3020
+#define WM8994_WRITE_SEQUENCER_33 0x3021
+#define WM8994_WRITE_SEQUENCER_34 0x3022
+#define WM8994_WRITE_SEQUENCER_35 0x3023
+#define WM8994_WRITE_SEQUENCER_36 0x3024
+#define WM8994_WRITE_SEQUENCER_37 0x3025
+#define WM8994_WRITE_SEQUENCER_38 0x3026
+#define WM8994_WRITE_SEQUENCER_39 0x3027
+#define WM8994_WRITE_SEQUENCER_40 0x3028
+#define WM8994_WRITE_SEQUENCER_41 0x3029
+#define WM8994_WRITE_SEQUENCER_42 0x302A
+#define WM8994_WRITE_SEQUENCER_43 0x302B
+#define WM8994_WRITE_SEQUENCER_44 0x302C
+#define WM8994_WRITE_SEQUENCER_45 0x302D
+#define WM8994_WRITE_SEQUENCER_46 0x302E
+#define WM8994_WRITE_SEQUENCER_47 0x302F
+#define WM8994_WRITE_SEQUENCER_48 0x3030
+#define WM8994_WRITE_SEQUENCER_49 0x3031
+#define WM8994_WRITE_SEQUENCER_50 0x3032
+#define WM8994_WRITE_SEQUENCER_51 0x3033
+#define WM8994_WRITE_SEQUENCER_52 0x3034
+#define WM8994_WRITE_SEQUENCER_53 0x3035
+#define WM8994_WRITE_SEQUENCER_54 0x3036
+#define WM8994_WRITE_SEQUENCER_55 0x3037
+#define WM8994_WRITE_SEQUENCER_56 0x3038
+#define WM8994_WRITE_SEQUENCER_57 0x3039
+#define WM8994_WRITE_SEQUENCER_58 0x303A
+#define WM8994_WRITE_SEQUENCER_59 0x303B
+#define WM8994_WRITE_SEQUENCER_60 0x303C
+#define WM8994_WRITE_SEQUENCER_61 0x303D
+#define WM8994_WRITE_SEQUENCER_62 0x303E
+#define WM8994_WRITE_SEQUENCER_63 0x303F
+#define WM8994_WRITE_SEQUENCER_64 0x3040
+#define WM8994_WRITE_SEQUENCER_65 0x3041
+#define WM8994_WRITE_SEQUENCER_66 0x3042
+#define WM8994_WRITE_SEQUENCER_67 0x3043
+#define WM8994_WRITE_SEQUENCER_68 0x3044
+#define WM8994_WRITE_SEQUENCER_69 0x3045
+#define WM8994_WRITE_SEQUENCER_70 0x3046
+#define WM8994_WRITE_SEQUENCER_71 0x3047
+#define WM8994_WRITE_SEQUENCER_72 0x3048
+#define WM8994_WRITE_SEQUENCER_73 0x3049
+#define WM8994_WRITE_SEQUENCER_74 0x304A
+#define WM8994_WRITE_SEQUENCER_75 0x304B
+#define WM8994_WRITE_SEQUENCER_76 0x304C
+#define WM8994_WRITE_SEQUENCER_77 0x304D
+#define WM8994_WRITE_SEQUENCER_78 0x304E
+#define WM8994_WRITE_SEQUENCER_79 0x304F
+#define WM8994_WRITE_SEQUENCER_80 0x3050
+#define WM8994_WRITE_SEQUENCER_81 0x3051
+#define WM8994_WRITE_SEQUENCER_82 0x3052
+#define WM8994_WRITE_SEQUENCER_83 0x3053
+#define WM8994_WRITE_SEQUENCER_84 0x3054
+#define WM8994_WRITE_SEQUENCER_85 0x3055
+#define WM8994_WRITE_SEQUENCER_86 0x3056
+#define WM8994_WRITE_SEQUENCER_87 0x3057
+#define WM8994_WRITE_SEQUENCER_88 0x3058
+#define WM8994_WRITE_SEQUENCER_89 0x3059
+#define WM8994_WRITE_SEQUENCER_90 0x305A
+#define WM8994_WRITE_SEQUENCER_91 0x305B
+#define WM8994_WRITE_SEQUENCER_92 0x305C
+#define WM8994_WRITE_SEQUENCER_93 0x305D
+#define WM8994_WRITE_SEQUENCER_94 0x305E
+#define WM8994_WRITE_SEQUENCER_95 0x305F
+#define WM8994_WRITE_SEQUENCER_96 0x3060
+#define WM8994_WRITE_SEQUENCER_97 0x3061
+#define WM8994_WRITE_SEQUENCER_98 0x3062
+#define WM8994_WRITE_SEQUENCER_99 0x3063
+#define WM8994_WRITE_SEQUENCER_100 0x3064
+#define WM8994_WRITE_SEQUENCER_101 0x3065
+#define WM8994_WRITE_SEQUENCER_102 0x3066
+#define WM8994_WRITE_SEQUENCER_103 0x3067
+#define WM8994_WRITE_SEQUENCER_104 0x3068
+#define WM8994_WRITE_SEQUENCER_105 0x3069
+#define WM8994_WRITE_SEQUENCER_106 0x306A
+#define WM8994_WRITE_SEQUENCER_107 0x306B
+#define WM8994_WRITE_SEQUENCER_108 0x306C
+#define WM8994_WRITE_SEQUENCER_109 0x306D
+#define WM8994_WRITE_SEQUENCER_110 0x306E
+#define WM8994_WRITE_SEQUENCER_111 0x306F
+#define WM8994_WRITE_SEQUENCER_112 0x3070
+#define WM8994_WRITE_SEQUENCER_113 0x3071
+#define WM8994_WRITE_SEQUENCER_114 0x3072
+#define WM8994_WRITE_SEQUENCER_115 0x3073
+#define WM8994_WRITE_SEQUENCER_116 0x3074
+#define WM8994_WRITE_SEQUENCER_117 0x3075
+#define WM8994_WRITE_SEQUENCER_118 0x3076
+#define WM8994_WRITE_SEQUENCER_119 0x3077
+#define WM8994_WRITE_SEQUENCER_120 0x3078
+#define WM8994_WRITE_SEQUENCER_121 0x3079
+#define WM8994_WRITE_SEQUENCER_122 0x307A
+#define WM8994_WRITE_SEQUENCER_123 0x307B
+#define WM8994_WRITE_SEQUENCER_124 0x307C
+#define WM8994_WRITE_SEQUENCER_125 0x307D
+#define WM8994_WRITE_SEQUENCER_126 0x307E
+#define WM8994_WRITE_SEQUENCER_127 0x307F
+#define WM8994_WRITE_SEQUENCER_128 0x3080
+#define WM8994_WRITE_SEQUENCER_129 0x3081
+#define WM8994_WRITE_SEQUENCER_130 0x3082
+#define WM8994_WRITE_SEQUENCER_131 0x3083
+#define WM8994_WRITE_SEQUENCER_132 0x3084
+#define WM8994_WRITE_SEQUENCER_133 0x3085
+#define WM8994_WRITE_SEQUENCER_134 0x3086
+#define WM8994_WRITE_SEQUENCER_135 0x3087
+#define WM8994_WRITE_SEQUENCER_136 0x3088
+#define WM8994_WRITE_SEQUENCER_137 0x3089
+#define WM8994_WRITE_SEQUENCER_138 0x308A
+#define WM8994_WRITE_SEQUENCER_139 0x308B
+#define WM8994_WRITE_SEQUENCER_140 0x308C
+#define WM8994_WRITE_SEQUENCER_141 0x308D
+#define WM8994_WRITE_SEQUENCER_142 0x308E
+#define WM8994_WRITE_SEQUENCER_143 0x308F
+#define WM8994_WRITE_SEQUENCER_144 0x3090
+#define WM8994_WRITE_SEQUENCER_145 0x3091
+#define WM8994_WRITE_SEQUENCER_146 0x3092
+#define WM8994_WRITE_SEQUENCER_147 0x3093
+#define WM8994_WRITE_SEQUENCER_148 0x3094
+#define WM8994_WRITE_SEQUENCER_149 0x3095
+#define WM8994_WRITE_SEQUENCER_150 0x3096
+#define WM8994_WRITE_SEQUENCER_151 0x3097
+#define WM8994_WRITE_SEQUENCER_152 0x3098
+#define WM8994_WRITE_SEQUENCER_153 0x3099
+#define WM8994_WRITE_SEQUENCER_154 0x309A
+#define WM8994_WRITE_SEQUENCER_155 0x309B
+#define WM8994_WRITE_SEQUENCER_156 0x309C
+#define WM8994_WRITE_SEQUENCER_157 0x309D
+#define WM8994_WRITE_SEQUENCER_158 0x309E
+#define WM8994_WRITE_SEQUENCER_159 0x309F
+#define WM8994_WRITE_SEQUENCER_160 0x30A0
+#define WM8994_WRITE_SEQUENCER_161 0x30A1
+#define WM8994_WRITE_SEQUENCER_162 0x30A2
+#define WM8994_WRITE_SEQUENCER_163 0x30A3
+#define WM8994_WRITE_SEQUENCER_164 0x30A4
+#define WM8994_WRITE_SEQUENCER_165 0x30A5
+#define WM8994_WRITE_SEQUENCER_166 0x30A6
+#define WM8994_WRITE_SEQUENCER_167 0x30A7
+#define WM8994_WRITE_SEQUENCER_168 0x30A8
+#define WM8994_WRITE_SEQUENCER_169 0x30A9
+#define WM8994_WRITE_SEQUENCER_170 0x30AA
+#define WM8994_WRITE_SEQUENCER_171 0x30AB
+#define WM8994_WRITE_SEQUENCER_172 0x30AC
+#define WM8994_WRITE_SEQUENCER_173 0x30AD
+#define WM8994_WRITE_SEQUENCER_174 0x30AE
+#define WM8994_WRITE_SEQUENCER_175 0x30AF
+#define WM8994_WRITE_SEQUENCER_176 0x30B0
+#define WM8994_WRITE_SEQUENCER_177 0x30B1
+#define WM8994_WRITE_SEQUENCER_178 0x30B2
+#define WM8994_WRITE_SEQUENCER_179 0x30B3
+#define WM8994_WRITE_SEQUENCER_180 0x30B4
+#define WM8994_WRITE_SEQUENCER_181 0x30B5
+#define WM8994_WRITE_SEQUENCER_182 0x30B6
+#define WM8994_WRITE_SEQUENCER_183 0x30B7
+#define WM8994_WRITE_SEQUENCER_184 0x30B8
+#define WM8994_WRITE_SEQUENCER_185 0x30B9
+#define WM8994_WRITE_SEQUENCER_186 0x30BA
+#define WM8994_WRITE_SEQUENCER_187 0x30BB
+#define WM8994_WRITE_SEQUENCER_188 0x30BC
+#define WM8994_WRITE_SEQUENCER_189 0x30BD
+#define WM8994_WRITE_SEQUENCER_190 0x30BE
+#define WM8994_WRITE_SEQUENCER_191 0x30BF
+#define WM8994_WRITE_SEQUENCER_192 0x30C0
+#define WM8994_WRITE_SEQUENCER_193 0x30C1
+#define WM8994_WRITE_SEQUENCER_194 0x30C2
+#define WM8994_WRITE_SEQUENCER_195 0x30C3
+#define WM8994_WRITE_SEQUENCER_196 0x30C4
+#define WM8994_WRITE_SEQUENCER_197 0x30C5
+#define WM8994_WRITE_SEQUENCER_198 0x30C6
+#define WM8994_WRITE_SEQUENCER_199 0x30C7
+#define WM8994_WRITE_SEQUENCER_200 0x30C8
+#define WM8994_WRITE_SEQUENCER_201 0x30C9
+#define WM8994_WRITE_SEQUENCER_202 0x30CA
+#define WM8994_WRITE_SEQUENCER_203 0x30CB
+#define WM8994_WRITE_SEQUENCER_204 0x30CC
+#define WM8994_WRITE_SEQUENCER_205 0x30CD
+#define WM8994_WRITE_SEQUENCER_206 0x30CE
+#define WM8994_WRITE_SEQUENCER_207 0x30CF
+#define WM8994_WRITE_SEQUENCER_208 0x30D0
+#define WM8994_WRITE_SEQUENCER_209 0x30D1
+#define WM8994_WRITE_SEQUENCER_210 0x30D2
+#define WM8994_WRITE_SEQUENCER_211 0x30D3
+#define WM8994_WRITE_SEQUENCER_212 0x30D4
+#define WM8994_WRITE_SEQUENCER_213 0x30D5
+#define WM8994_WRITE_SEQUENCER_214 0x30D6
+#define WM8994_WRITE_SEQUENCER_215 0x30D7
+#define WM8994_WRITE_SEQUENCER_216 0x30D8
+#define WM8994_WRITE_SEQUENCER_217 0x30D9
+#define WM8994_WRITE_SEQUENCER_218 0x30DA
+#define WM8994_WRITE_SEQUENCER_219 0x30DB
+#define WM8994_WRITE_SEQUENCER_220 0x30DC
+#define WM8994_WRITE_SEQUENCER_221 0x30DD
+#define WM8994_WRITE_SEQUENCER_222 0x30DE
+#define WM8994_WRITE_SEQUENCER_223 0x30DF
+#define WM8994_WRITE_SEQUENCER_224 0x30E0
+#define WM8994_WRITE_SEQUENCER_225 0x30E1
+#define WM8994_WRITE_SEQUENCER_226 0x30E2
+#define WM8994_WRITE_SEQUENCER_227 0x30E3
+#define WM8994_WRITE_SEQUENCER_228 0x30E4
+#define WM8994_WRITE_SEQUENCER_229 0x30E5
+#define WM8994_WRITE_SEQUENCER_230 0x30E6
+#define WM8994_WRITE_SEQUENCER_231 0x30E7
+#define WM8994_WRITE_SEQUENCER_232 0x30E8
+#define WM8994_WRITE_SEQUENCER_233 0x30E9
+#define WM8994_WRITE_SEQUENCER_234 0x30EA
+#define WM8994_WRITE_SEQUENCER_235 0x30EB
+#define WM8994_WRITE_SEQUENCER_236 0x30EC
+#define WM8994_WRITE_SEQUENCER_237 0x30ED
+#define WM8994_WRITE_SEQUENCER_238 0x30EE
+#define WM8994_WRITE_SEQUENCER_239 0x30EF
+#define WM8994_WRITE_SEQUENCER_240 0x30F0
+#define WM8994_WRITE_SEQUENCER_241 0x30F1
+#define WM8994_WRITE_SEQUENCER_242 0x30F2
+#define WM8994_WRITE_SEQUENCER_243 0x30F3
+#define WM8994_WRITE_SEQUENCER_244 0x30F4
+#define WM8994_WRITE_SEQUENCER_245 0x30F5
+#define WM8994_WRITE_SEQUENCER_246 0x30F6
+#define WM8994_WRITE_SEQUENCER_247 0x30F7
+#define WM8994_WRITE_SEQUENCER_248 0x30F8
+#define WM8994_WRITE_SEQUENCER_249 0x30F9
+#define WM8994_WRITE_SEQUENCER_250 0x30FA
+#define WM8994_WRITE_SEQUENCER_251 0x30FB
+#define WM8994_WRITE_SEQUENCER_252 0x30FC
+#define WM8994_WRITE_SEQUENCER_253 0x30FD
+#define WM8994_WRITE_SEQUENCER_254 0x30FE
+#define WM8994_WRITE_SEQUENCER_255 0x30FF
+#define WM8994_WRITE_SEQUENCER_256 0x3100
+#define WM8994_WRITE_SEQUENCER_257 0x3101
+#define WM8994_WRITE_SEQUENCER_258 0x3102
+#define WM8994_WRITE_SEQUENCER_259 0x3103
+#define WM8994_WRITE_SEQUENCER_260 0x3104
+#define WM8994_WRITE_SEQUENCER_261 0x3105
+#define WM8994_WRITE_SEQUENCER_262 0x3106
+#define WM8994_WRITE_SEQUENCER_263 0x3107
+#define WM8994_WRITE_SEQUENCER_264 0x3108
+#define WM8994_WRITE_SEQUENCER_265 0x3109
+#define WM8994_WRITE_SEQUENCER_266 0x310A
+#define WM8994_WRITE_SEQUENCER_267 0x310B
+#define WM8994_WRITE_SEQUENCER_268 0x310C
+#define WM8994_WRITE_SEQUENCER_269 0x310D
+#define WM8994_WRITE_SEQUENCER_270 0x310E
+#define WM8994_WRITE_SEQUENCER_271 0x310F
+#define WM8994_WRITE_SEQUENCER_272 0x3110
+#define WM8994_WRITE_SEQUENCER_273 0x3111
+#define WM8994_WRITE_SEQUENCER_274 0x3112
+#define WM8994_WRITE_SEQUENCER_275 0x3113
+#define WM8994_WRITE_SEQUENCER_276 0x3114
+#define WM8994_WRITE_SEQUENCER_277 0x3115
+#define WM8994_WRITE_SEQUENCER_278 0x3116
+#define WM8994_WRITE_SEQUENCER_279 0x3117
+#define WM8994_WRITE_SEQUENCER_280 0x3118
+#define WM8994_WRITE_SEQUENCER_281 0x3119
+#define WM8994_WRITE_SEQUENCER_282 0x311A
+#define WM8994_WRITE_SEQUENCER_283 0x311B
+#define WM8994_WRITE_SEQUENCER_284 0x311C
+#define WM8994_WRITE_SEQUENCER_285 0x311D
+#define WM8994_WRITE_SEQUENCER_286 0x311E
+#define WM8994_WRITE_SEQUENCER_287 0x311F
+#define WM8994_WRITE_SEQUENCER_288 0x3120
+#define WM8994_WRITE_SEQUENCER_289 0x3121
+#define WM8994_WRITE_SEQUENCER_290 0x3122
+#define WM8994_WRITE_SEQUENCER_291 0x3123
+#define WM8994_WRITE_SEQUENCER_292 0x3124
+#define WM8994_WRITE_SEQUENCER_293 0x3125
+#define WM8994_WRITE_SEQUENCER_294 0x3126
+#define WM8994_WRITE_SEQUENCER_295 0x3127
+#define WM8994_WRITE_SEQUENCER_296 0x3128
+#define WM8994_WRITE_SEQUENCER_297 0x3129
+#define WM8994_WRITE_SEQUENCER_298 0x312A
+#define WM8994_WRITE_SEQUENCER_299 0x312B
+#define WM8994_WRITE_SEQUENCER_300 0x312C
+#define WM8994_WRITE_SEQUENCER_301 0x312D
+#define WM8994_WRITE_SEQUENCER_302 0x312E
+#define WM8994_WRITE_SEQUENCER_303 0x312F
+#define WM8994_WRITE_SEQUENCER_304 0x3130
+#define WM8994_WRITE_SEQUENCER_305 0x3131
+#define WM8994_WRITE_SEQUENCER_306 0x3132
+#define WM8994_WRITE_SEQUENCER_307 0x3133
+#define WM8994_WRITE_SEQUENCER_308 0x3134
+#define WM8994_WRITE_SEQUENCER_309 0x3135
+#define WM8994_WRITE_SEQUENCER_310 0x3136
+#define WM8994_WRITE_SEQUENCER_311 0x3137
+#define WM8994_WRITE_SEQUENCER_312 0x3138
+#define WM8994_WRITE_SEQUENCER_313 0x3139
+#define WM8994_WRITE_SEQUENCER_314 0x313A
+#define WM8994_WRITE_SEQUENCER_315 0x313B
+#define WM8994_WRITE_SEQUENCER_316 0x313C
+#define WM8994_WRITE_SEQUENCER_317 0x313D
+#define WM8994_WRITE_SEQUENCER_318 0x313E
+#define WM8994_WRITE_SEQUENCER_319 0x313F
+#define WM8994_WRITE_SEQUENCER_320 0x3140
+#define WM8994_WRITE_SEQUENCER_321 0x3141
+#define WM8994_WRITE_SEQUENCER_322 0x3142
+#define WM8994_WRITE_SEQUENCER_323 0x3143
+#define WM8994_WRITE_SEQUENCER_324 0x3144
+#define WM8994_WRITE_SEQUENCER_325 0x3145
+#define WM8994_WRITE_SEQUENCER_326 0x3146
+#define WM8994_WRITE_SEQUENCER_327 0x3147
+#define WM8994_WRITE_SEQUENCER_328 0x3148
+#define WM8994_WRITE_SEQUENCER_329 0x3149
+#define WM8994_WRITE_SEQUENCER_330 0x314A
+#define WM8994_WRITE_SEQUENCER_331 0x314B
+#define WM8994_WRITE_SEQUENCER_332 0x314C
+#define WM8994_WRITE_SEQUENCER_333 0x314D
+#define WM8994_WRITE_SEQUENCER_334 0x314E
+#define WM8994_WRITE_SEQUENCER_335 0x314F
+#define WM8994_WRITE_SEQUENCER_336 0x3150
+#define WM8994_WRITE_SEQUENCER_337 0x3151
+#define WM8994_WRITE_SEQUENCER_338 0x3152
+#define WM8994_WRITE_SEQUENCER_339 0x3153
+#define WM8994_WRITE_SEQUENCER_340 0x3154
+#define WM8994_WRITE_SEQUENCER_341 0x3155
+#define WM8994_WRITE_SEQUENCER_342 0x3156
+#define WM8994_WRITE_SEQUENCER_343 0x3157
+#define WM8994_WRITE_SEQUENCER_344 0x3158
+#define WM8994_WRITE_SEQUENCER_345 0x3159
+#define WM8994_WRITE_SEQUENCER_346 0x315A
+#define WM8994_WRITE_SEQUENCER_347 0x315B
+#define WM8994_WRITE_SEQUENCER_348 0x315C
+#define WM8994_WRITE_SEQUENCER_349 0x315D
+#define WM8994_WRITE_SEQUENCER_350 0x315E
+#define WM8994_WRITE_SEQUENCER_351 0x315F
+#define WM8994_WRITE_SEQUENCER_352 0x3160
+#define WM8994_WRITE_SEQUENCER_353 0x3161
+#define WM8994_WRITE_SEQUENCER_354 0x3162
+#define WM8994_WRITE_SEQUENCER_355 0x3163
+#define WM8994_WRITE_SEQUENCER_356 0x3164
+#define WM8994_WRITE_SEQUENCER_357 0x3165
+#define WM8994_WRITE_SEQUENCER_358 0x3166
+#define WM8994_WRITE_SEQUENCER_359 0x3167
+#define WM8994_WRITE_SEQUENCER_360 0x3168
+#define WM8994_WRITE_SEQUENCER_361 0x3169
+#define WM8994_WRITE_SEQUENCER_362 0x316A
+#define WM8994_WRITE_SEQUENCER_363 0x316B
+#define WM8994_WRITE_SEQUENCER_364 0x316C
+#define WM8994_WRITE_SEQUENCER_365 0x316D
+#define WM8994_WRITE_SEQUENCER_366 0x316E
+#define WM8994_WRITE_SEQUENCER_367 0x316F
+#define WM8994_WRITE_SEQUENCER_368 0x3170
+#define WM8994_WRITE_SEQUENCER_369 0x3171
+#define WM8994_WRITE_SEQUENCER_370 0x3172
+#define WM8994_WRITE_SEQUENCER_371 0x3173
+#define WM8994_WRITE_SEQUENCER_372 0x3174
+#define WM8994_WRITE_SEQUENCER_373 0x3175
+#define WM8994_WRITE_SEQUENCER_374 0x3176
+#define WM8994_WRITE_SEQUENCER_375 0x3177
+#define WM8994_WRITE_SEQUENCER_376 0x3178
+#define WM8994_WRITE_SEQUENCER_377 0x3179
+#define WM8994_WRITE_SEQUENCER_378 0x317A
+#define WM8994_WRITE_SEQUENCER_379 0x317B
+#define WM8994_WRITE_SEQUENCER_380 0x317C
+#define WM8994_WRITE_SEQUENCER_381 0x317D
+#define WM8994_WRITE_SEQUENCER_382 0x317E
+#define WM8994_WRITE_SEQUENCER_383 0x317F
+#define WM8994_WRITE_SEQUENCER_384 0x3180
+#define WM8994_WRITE_SEQUENCER_385 0x3181
+#define WM8994_WRITE_SEQUENCER_386 0x3182
+#define WM8994_WRITE_SEQUENCER_387 0x3183
+#define WM8994_WRITE_SEQUENCER_388 0x3184
+#define WM8994_WRITE_SEQUENCER_389 0x3185
+#define WM8994_WRITE_SEQUENCER_390 0x3186
+#define WM8994_WRITE_SEQUENCER_391 0x3187
+#define WM8994_WRITE_SEQUENCER_392 0x3188
+#define WM8994_WRITE_SEQUENCER_393 0x3189
+#define WM8994_WRITE_SEQUENCER_394 0x318A
+#define WM8994_WRITE_SEQUENCER_395 0x318B
+#define WM8994_WRITE_SEQUENCER_396 0x318C
+#define WM8994_WRITE_SEQUENCER_397 0x318D
+#define WM8994_WRITE_SEQUENCER_398 0x318E
+#define WM8994_WRITE_SEQUENCER_399 0x318F
+#define WM8994_WRITE_SEQUENCER_400 0x3190
+#define WM8994_WRITE_SEQUENCER_401 0x3191
+#define WM8994_WRITE_SEQUENCER_402 0x3192
+#define WM8994_WRITE_SEQUENCER_403 0x3193
+#define WM8994_WRITE_SEQUENCER_404 0x3194
+#define WM8994_WRITE_SEQUENCER_405 0x3195
+#define WM8994_WRITE_SEQUENCER_406 0x3196
+#define WM8994_WRITE_SEQUENCER_407 0x3197
+#define WM8994_WRITE_SEQUENCER_408 0x3198
+#define WM8994_WRITE_SEQUENCER_409 0x3199
+#define WM8994_WRITE_SEQUENCER_410 0x319A
+#define WM8994_WRITE_SEQUENCER_411 0x319B
+#define WM8994_WRITE_SEQUENCER_412 0x319C
+#define WM8994_WRITE_SEQUENCER_413 0x319D
+#define WM8994_WRITE_SEQUENCER_414 0x319E
+#define WM8994_WRITE_SEQUENCER_415 0x319F
+#define WM8994_WRITE_SEQUENCER_416 0x31A0
+#define WM8994_WRITE_SEQUENCER_417 0x31A1
+#define WM8994_WRITE_SEQUENCER_418 0x31A2
+#define WM8994_WRITE_SEQUENCER_419 0x31A3
+#define WM8994_WRITE_SEQUENCER_420 0x31A4
+#define WM8994_WRITE_SEQUENCER_421 0x31A5
+#define WM8994_WRITE_SEQUENCER_422 0x31A6
+#define WM8994_WRITE_SEQUENCER_423 0x31A7
+#define WM8994_WRITE_SEQUENCER_424 0x31A8
+#define WM8994_WRITE_SEQUENCER_425 0x31A9
+#define WM8994_WRITE_SEQUENCER_426 0x31AA
+#define WM8994_WRITE_SEQUENCER_427 0x31AB
+#define WM8994_WRITE_SEQUENCER_428 0x31AC
+#define WM8994_WRITE_SEQUENCER_429 0x31AD
+#define WM8994_WRITE_SEQUENCER_430 0x31AE
+#define WM8994_WRITE_SEQUENCER_431 0x31AF
+#define WM8994_WRITE_SEQUENCER_432 0x31B0
+#define WM8994_WRITE_SEQUENCER_433 0x31B1
+#define WM8994_WRITE_SEQUENCER_434 0x31B2
+#define WM8994_WRITE_SEQUENCER_435 0x31B3
+#define WM8994_WRITE_SEQUENCER_436 0x31B4
+#define WM8994_WRITE_SEQUENCER_437 0x31B5
+#define WM8994_WRITE_SEQUENCER_438 0x31B6
+#define WM8994_WRITE_SEQUENCER_439 0x31B7
+#define WM8994_WRITE_SEQUENCER_440 0x31B8
+#define WM8994_WRITE_SEQUENCER_441 0x31B9
+#define WM8994_WRITE_SEQUENCER_442 0x31BA
+#define WM8994_WRITE_SEQUENCER_443 0x31BB
+#define WM8994_WRITE_SEQUENCER_444 0x31BC
+#define WM8994_WRITE_SEQUENCER_445 0x31BD
+#define WM8994_WRITE_SEQUENCER_446 0x31BE
+#define WM8994_WRITE_SEQUENCER_447 0x31BF
+#define WM8994_WRITE_SEQUENCER_448 0x31C0
+#define WM8994_WRITE_SEQUENCER_449 0x31C1
+#define WM8994_WRITE_SEQUENCER_450 0x31C2
+#define WM8994_WRITE_SEQUENCER_451 0x31C3
+#define WM8994_WRITE_SEQUENCER_452 0x31C4
+#define WM8994_WRITE_SEQUENCER_453 0x31C5
+#define WM8994_WRITE_SEQUENCER_454 0x31C6
+#define WM8994_WRITE_SEQUENCER_455 0x31C7
+#define WM8994_WRITE_SEQUENCER_456 0x31C8
+#define WM8994_WRITE_SEQUENCER_457 0x31C9
+#define WM8994_WRITE_SEQUENCER_458 0x31CA
+#define WM8994_WRITE_SEQUENCER_459 0x31CB
+#define WM8994_WRITE_SEQUENCER_460 0x31CC
+#define WM8994_WRITE_SEQUENCER_461 0x31CD
+#define WM8994_WRITE_SEQUENCER_462 0x31CE
+#define WM8994_WRITE_SEQUENCER_463 0x31CF
+#define WM8994_WRITE_SEQUENCER_464 0x31D0
+#define WM8994_WRITE_SEQUENCER_465 0x31D1
+#define WM8994_WRITE_SEQUENCER_466 0x31D2
+#define WM8994_WRITE_SEQUENCER_467 0x31D3
+#define WM8994_WRITE_SEQUENCER_468 0x31D4
+#define WM8994_WRITE_SEQUENCER_469 0x31D5
+#define WM8994_WRITE_SEQUENCER_470 0x31D6
+#define WM8994_WRITE_SEQUENCER_471 0x31D7
+#define WM8994_WRITE_SEQUENCER_472 0x31D8
+#define WM8994_WRITE_SEQUENCER_473 0x31D9
+#define WM8994_WRITE_SEQUENCER_474 0x31DA
+#define WM8994_WRITE_SEQUENCER_475 0x31DB
+#define WM8994_WRITE_SEQUENCER_476 0x31DC
+#define WM8994_WRITE_SEQUENCER_477 0x31DD
+#define WM8994_WRITE_SEQUENCER_478 0x31DE
+#define WM8994_WRITE_SEQUENCER_479 0x31DF
+#define WM8994_WRITE_SEQUENCER_480 0x31E0
+#define WM8994_WRITE_SEQUENCER_481 0x31E1
+#define WM8994_WRITE_SEQUENCER_482 0x31E2
+#define WM8994_WRITE_SEQUENCER_483 0x31E3
+#define WM8994_WRITE_SEQUENCER_484 0x31E4
+#define WM8994_WRITE_SEQUENCER_485 0x31E5
+#define WM8994_WRITE_SEQUENCER_486 0x31E6
+#define WM8994_WRITE_SEQUENCER_487 0x31E7
+#define WM8994_WRITE_SEQUENCER_488 0x31E8
+#define WM8994_WRITE_SEQUENCER_489 0x31E9
+#define WM8994_WRITE_SEQUENCER_490 0x31EA
+#define WM8994_WRITE_SEQUENCER_491 0x31EB
+#define WM8994_WRITE_SEQUENCER_492 0x31EC
+#define WM8994_WRITE_SEQUENCER_493 0x31ED
+#define WM8994_WRITE_SEQUENCER_494 0x31EE
+#define WM8994_WRITE_SEQUENCER_495 0x31EF
+#define WM8994_WRITE_SEQUENCER_496 0x31F0
+#define WM8994_WRITE_SEQUENCER_497 0x31F1
+#define WM8994_WRITE_SEQUENCER_498 0x31F2
+#define WM8994_WRITE_SEQUENCER_499 0x31F3
+#define WM8994_WRITE_SEQUENCER_500 0x31F4
+#define WM8994_WRITE_SEQUENCER_501 0x31F5
+#define WM8994_WRITE_SEQUENCER_502 0x31F6
+#define WM8994_WRITE_SEQUENCER_503 0x31F7
+#define WM8994_WRITE_SEQUENCER_504 0x31F8
+#define WM8994_WRITE_SEQUENCER_505 0x31F9
+#define WM8994_WRITE_SEQUENCER_506 0x31FA
+#define WM8994_WRITE_SEQUENCER_507 0x31FB
+#define WM8994_WRITE_SEQUENCER_508 0x31FC
+#define WM8994_WRITE_SEQUENCER_509 0x31FD
+#define WM8994_WRITE_SEQUENCER_510 0x31FE
+#define WM8994_WRITE_SEQUENCER_511 0x31FF
+
+#define WM8994_REGISTER_COUNT 736
+#define WM8994_MAX_REGISTER 0x31FF
+
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Software Reset
+ */
+#define WM8994_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
+#define WM8994_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
+#define WM8994_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
+
+/*
+ * R1 (0x01) - Power Management (1)
+ */
+#define WM8994_SPKOUTR_ENA 0x2000 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTR_ENA_MASK 0x2000 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTR_ENA_SHIFT 13 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */
+#define WM8994_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */
+#define WM8994_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */
+#define WM8994_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */
+#define WM8994_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */
+#define WM8994_HPOUT2_ENA 0x0800 /* HPOUT2_ENA */
+#define WM8994_HPOUT2_ENA_MASK 0x0800 /* HPOUT2_ENA */
+#define WM8994_HPOUT2_ENA_SHIFT 11 /* HPOUT2_ENA */
+#define WM8994_HPOUT2_ENA_WIDTH 1 /* HPOUT2_ENA */
+#define WM8994_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
+#define WM8994_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
+#define WM8994_MICB2_ENA 0x0020 /* MICB2_ENA */
+#define WM8994_MICB2_ENA_MASK 0x0020 /* MICB2_ENA */
+#define WM8994_MICB2_ENA_SHIFT 5 /* MICB2_ENA */
+#define WM8994_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
+#define WM8994_MICB1_ENA 0x0010 /* MICB1_ENA */
+#define WM8994_MICB1_ENA_MASK 0x0010 /* MICB1_ENA */
+#define WM8994_MICB1_ENA_SHIFT 4 /* MICB1_ENA */
+#define WM8994_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
+#define WM8994_VMID_SEL_NORMAL 0x0002
+#define WM8994_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
+#define WM8994_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
+#define WM8994_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
+#define WM8994_BIAS_ENA 0x0001 /* BIAS_ENA */
+#define WM8994_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
+#define WM8994_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
+#define WM8994_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
+
+/*
+ * R2 (0x02) - Power Management (2)
+ */
+#define WM8994_TSHUT_ENA 0x4000 /* TSHUT_ENA */
+#define WM8994_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
+#define WM8994_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
+#define WM8994_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
+#define WM8994_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
+#define WM8994_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
+#define WM8994_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
+#define WM8994_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
+#define WM8994_OPCLK_ENA 0x0800 /* OPCLK_ENA */
+#define WM8994_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
+#define WM8994_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
+#define WM8994_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
+#define WM8994_MIXINL_ENA 0x0200 /* MIXINL_ENA */
+#define WM8994_MIXINL_ENA_MASK 0x0200 /* MIXINL_ENA */
+#define WM8994_MIXINL_ENA_SHIFT 9 /* MIXINL_ENA */
+#define WM8994_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */
+#define WM8994_MIXINR_ENA 0x0100 /* MIXINR_ENA */
+#define WM8994_MIXINR_ENA_MASK 0x0100 /* MIXINR_ENA */
+#define WM8994_MIXINR_ENA_SHIFT 8 /* MIXINR_ENA */
+#define WM8994_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */
+#define WM8994_IN2L_ENA 0x0080 /* IN2L_ENA */
+#define WM8994_IN2L_ENA_MASK 0x0080 /* IN2L_ENA */
+#define WM8994_IN2L_ENA_SHIFT 7 /* IN2L_ENA */
+#define WM8994_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
+#define WM8994_IN1L_ENA 0x0040 /* IN1L_ENA */
+#define WM8994_IN1L_ENA_MASK 0x0040 /* IN1L_ENA */
+#define WM8994_IN1L_ENA_SHIFT 6 /* IN1L_ENA */
+#define WM8994_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
+#define WM8994_IN2R_ENA 0x0020 /* IN2R_ENA */
+#define WM8994_IN2R_ENA_MASK 0x0020 /* IN2R_ENA */
+#define WM8994_IN2R_ENA_SHIFT 5 /* IN2R_ENA */
+#define WM8994_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
+#define WM8994_IN1R_ENA 0x0010 /* IN1R_ENA */
+#define WM8994_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */
+#define WM8994_IN1R_ENA_SHIFT 4 /* IN1R_ENA */
+#define WM8994_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
+
+/*
+ * R3 (0x03) - Power Management (3)
+ */
+#define WM8994_LINEOUT1N_ENA 0x2000 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1N_ENA_MASK 0x2000 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1N_ENA_SHIFT 13 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1N_ENA_WIDTH 1 /* LINEOUT1N_ENA */
+#define WM8994_LINEOUT1P_ENA 0x1000 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT1P_ENA_MASK 0x1000 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT1P_ENA_SHIFT 12 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT1P_ENA_WIDTH 1 /* LINEOUT1P_ENA */
+#define WM8994_LINEOUT2N_ENA 0x0800 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2N_ENA_MASK 0x0800 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2N_ENA_SHIFT 11 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2N_ENA_WIDTH 1 /* LINEOUT2N_ENA */
+#define WM8994_LINEOUT2P_ENA 0x0400 /* LINEOUT2P_ENA */
+#define WM8994_LINEOUT2P_ENA_MASK 0x0400 /* LINEOUT2P_ENA */
+#define WM8994_LINEOUT2P_ENA_SHIFT 10 /* LINEOUT2P_ENA */
+#define WM8994_LINEOUT2P_ENA_WIDTH 1 /* LINEOUT2P_ENA */
+#define WM8994_SPKRVOL_ENA 0x0200 /* SPKRVOL_ENA */
+#define WM8994_SPKRVOL_ENA_MASK 0x0200 /* SPKRVOL_ENA */
+#define WM8994_SPKRVOL_ENA_SHIFT 9 /* SPKRVOL_ENA */
+#define WM8994_SPKRVOL_ENA_WIDTH 1 /* SPKRVOL_ENA */
+#define WM8994_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */
+#define WM8994_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */
+#define WM8994_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */
+#define WM8994_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA 0x0080 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA_MASK 0x0080 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA_SHIFT 7 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTLVOL_ENA_WIDTH 1 /* MIXOUTLVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA 0x0040 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA_MASK 0x0040 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA_SHIFT 6 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTRVOL_ENA_WIDTH 1 /* MIXOUTRVOL_ENA */
+#define WM8994_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */
+#define WM8994_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */
+#define WM8994_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */
+#define WM8994_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */
+#define WM8994_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */
+
+/*
+ * R4 (0x04) - Power Management (4)
+ */
+#define WM8994_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */
+#define WM8994_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */
+#define WM8994_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */
+#define WM8994_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */
+#define WM8994_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */
+#define WM8994_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */
+#define WM8994_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */
+#define WM8994_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */
+#define WM8994_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */
+#define WM8994_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */
+#define WM8994_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */
+#define WM8994_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */
+#define WM8994_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
+#define WM8994_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
+#define WM8994_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
+#define WM8994_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
+#define WM8994_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
+#define WM8994_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
+#define WM8994_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
+#define WM8994_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
+#define WM8994_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
+#define WM8994_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
+#define WM8994_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
+#define WM8994_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
+#define WM8994_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
+#define WM8994_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
+#define WM8994_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
+#define WM8994_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
+#define WM8994_ADCL_ENA 0x0002 /* ADCL_ENA */
+#define WM8994_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
+#define WM8994_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
+#define WM8994_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
+#define WM8994_ADCR_ENA 0x0001 /* ADCR_ENA */
+#define WM8994_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
+#define WM8994_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
+#define WM8994_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
+
+/*
+ * R5 (0x05) - Power Management (5)
+ */
+#define WM8994_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */
+#define WM8994_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */
+#define WM8994_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */
+#define WM8994_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */
+#define WM8994_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */
+#define WM8994_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */
+#define WM8994_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */
+#define WM8994_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */
+#define WM8994_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */
+#define WM8994_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */
+#define WM8994_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */
+#define WM8994_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */
+#define WM8994_DAC2L_ENA 0x0008 /* DAC2L_ENA */
+#define WM8994_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
+#define WM8994_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
+#define WM8994_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
+#define WM8994_DAC2R_ENA 0x0004 /* DAC2R_ENA */
+#define WM8994_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
+#define WM8994_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
+#define WM8994_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
+#define WM8994_DAC1L_ENA 0x0002 /* DAC1L_ENA */
+#define WM8994_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
+#define WM8994_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
+#define WM8994_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
+#define WM8994_DAC1R_ENA 0x0001 /* DAC1R_ENA */
+#define WM8994_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
+#define WM8994_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
+#define WM8994_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
+
+/*
+ * R6 (0x06) - Power Management (6)
+ */
+#define WM8994_AIF3_TRIS 0x0020 /* AIF3_TRIS */
+#define WM8994_AIF3_TRIS_MASK 0x0020 /* AIF3_TRIS */
+#define WM8994_AIF3_TRIS_SHIFT 5 /* AIF3_TRIS */
+#define WM8994_AIF3_TRIS_WIDTH 1 /* AIF3_TRIS */
+#define WM8994_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8994_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8994_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */
+#define WM8994_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */
+#define WM8994_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */
+
+/*
+ * R21 (0x15) - Input Mixer (1)
+ */
+#define WM8994_INPUTS_CLAMP 0x0040 /* INPUTS_CLAMP */
+#define WM8994_INPUTS_CLAMP_MASK 0x0040 /* INPUTS_CLAMP */
+#define WM8994_INPUTS_CLAMP_SHIFT 6 /* INPUTS_CLAMP */
+#define WM8994_INPUTS_CLAMP_WIDTH 1 /* INPUTS_CLAMP */
+
+/*
+ * R24 (0x18) - Left Line Input 1&2 Volume
+ */
+#define WM8994_IN1L_VU 0x0100 /* IN1_VU */
+#define WM8994_IN1L_VU_MASK 0x0100 /* IN1_VU */
+#define WM8994_IN1L_VU_SHIFT 8 /* IN1_VU */
+#define WM8994_IN1L_VU_WIDTH 1 /* IN1_VU */
+#define WM8994_IN1L_MUTE 0x0080 /* IN1L_MUTE */
+#define WM8994_IN1L_MUTE_MASK 0x0080 /* IN1L_MUTE */
+#define WM8994_IN1L_MUTE_SHIFT 7 /* IN1L_MUTE */
+#define WM8994_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
+#define WM8994_IN1L_ZC 0x0040 /* IN1L_ZC */
+#define WM8994_IN1L_ZC_MASK 0x0040 /* IN1L_ZC */
+#define WM8994_IN1L_ZC_SHIFT 6 /* IN1L_ZC */
+#define WM8994_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
+#define WM8994_IN1L_VOL_30dB 0x001F
+#define WM8994_IN1L_VOL_25_5dB 0x001C
+#define WM8994_IN1L_VOL_21dB 0x0019
+#define WM8994_IN1L_VOL_16_5dB 0x0016
+#define WM8994_IN1L_VOL_12dB 0x0013
+#define WM8994_IN1L_VOL_7_5dB 0x0010
+#define WM8994_IN1L_VOL_3dB 0x000D
+#define WM8994_IN1L_VOL_n1_5dB 0x000A
+#define WM8994_IN1L_VOL_n6dB 0x0007
+#define WM8994_IN1L_VOL_n10_5dB 0x0004
+#define WM8994_IN1L_VOL_n13_5dB 0x0002
+#define WM8994_IN1L_VOL_n16_5dB 0x0000
+#define WM8994_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
+#define WM8994_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
+#define WM8994_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
+
+/*
+ * R25 (0x19) - Left Line Input 3&4 Volume
+ */
+#define WM8994_IN2L_VU 0x0100 /* IN2_VU */
+#define WM8994_IN2L_VU_MASK 0x0100 /* IN2_VU */
+#define WM8994_IN2L_VU_SHIFT 8 /* IN2_VU */
+#define WM8994_IN2L_VU_WIDTH 1 /* IN2_VU */
+#define WM8994_IN2L_MUTE 0x0080 /* IN2L_MUTE */
+#define WM8994_IN2L_MUTE_MASK 0x0080 /* IN2L_MUTE */
+#define WM8994_IN2L_MUTE_SHIFT 7 /* IN2L_MUTE */
+#define WM8994_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
+#define WM8994_IN2L_ZC 0x0040 /* IN2L_ZC */
+#define WM8994_IN2L_ZC_MASK 0x0040 /* IN2L_ZC */
+#define WM8994_IN2L_ZC_SHIFT 6 /* IN2L_ZC */
+#define WM8994_IN2L_ZC_WIDTH 1 /* IN2L_ZC */
+#define WM8994_IN2L_VOL_30dB 0x001F
+#define WM8994_IN2L_VOL_25_5dB 0x001C
+#define WM8994_IN2L_VOL_21dB 0x0019
+#define WM8994_IN2L_VOL_16_5dB 0x0016
+#define WM8994_IN2L_VOL_12dB 0x0013
+#define WM8994_IN2L_VOL_7_5dB 0x0010
+#define WM8994_IN2L_VOL_3dB 0x000D
+#define WM8994_IN2L_VOL_n1_5dB 0x000A
+#define WM8994_IN2L_VOL_n6dB 0x0007
+#define WM8994_IN2L_VOL_n10_5dB 0x0004
+#define WM8994_IN2L_VOL_n13_5dB 0x0002
+#define WM8994_IN2L_VOL_n16_5dB 0x0000
+#define WM8994_IN2L_VOL_MASK 0x001F /* IN2L_VOL - [4:0] */
+#define WM8994_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [4:0] */
+#define WM8994_IN2L_VOL_WIDTH 5 /* IN2L_VOL - [4:0] */
+
+/*
+ * R26 (0x1A) - Right Line Input 1&2 Volume
+ */
+#define WM8994_IN1R_VU 0x0100 /* IN1_VU */
+#define WM8994_IN1R_VU_MASK 0x0100 /* IN1_VU */
+#define WM8994_IN1R_VU_SHIFT 8 /* IN1_VU */
+#define WM8994_IN1R_VU_WIDTH 1 /* IN1_VU */
+#define WM8994_IN1R_MUTE 0x0080 /* IN1R_MUTE */
+#define WM8994_IN1R_MUTE_MASK 0x0080 /* IN1R_MUTE */
+#define WM8994_IN1R_MUTE_SHIFT 7 /* IN1R_MUTE */
+#define WM8994_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
+#define WM8994_IN1R_ZC 0x0040 /* IN1R_ZC */
+#define WM8994_IN1R_ZC_MASK 0x0040 /* IN1R_ZC */
+#define WM8994_IN1R_ZC_SHIFT 6 /* IN1R_ZC */
+#define WM8994_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
+#define WM8994_IN1R_VOL_30dB 0x001F
+#define WM8994_IN1R_VOL_25_5dB 0x001C
+#define WM8994_IN1R_VOL_21dB 0x0019
+#define WM8994_IN1R_VOL_16_5dB 0x0016
+#define WM8994_IN1R_VOL_12dB 0x0013
+#define WM8994_IN1R_VOL_7_5dB 0x0010
+#define WM8994_IN1R_VOL_3dB 0x000D
+#define WM8994_IN1R_VOL_n1_5dB 0x000A
+#define WM8994_IN1R_VOL_n6dB 0x0007
+#define WM8994_IN1R_VOL_n10_5dB 0x0004
+#define WM8994_IN1R_VOL_n13_5dB 0x0002
+#define WM8994_IN1R_VOL_n16_5dB 0x0000
+#define WM8994_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
+#define WM8994_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
+#define WM8994_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
+
+/*
+ * R27 (0x1B) - Right Line Input 3&4 Volume
+ */
+#define WM8994_IN2R_VU 0x0100 /* IN2_VU */
+#define WM8994_IN2R_VU_MASK 0x0100 /* IN2_VU */
+#define WM8994_IN2R_VU_SHIFT 8 /* IN2_VU */
+#define WM8994_IN2R_VU_WIDTH 1 /* IN2_VU */
+#define WM8994_IN2R_MUTE 0x0080 /* IN2R_MUTE */
+#define WM8994_IN2R_MUTE_MASK 0x0080 /* IN2R_MUTE */
+#define WM8994_IN2R_MUTE_SHIFT 7 /* IN2R_MUTE */
+#define WM8994_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
+#define WM8994_IN2R_ZC 0x0040 /* IN2R_ZC */
+#define WM8994_IN2R_ZC_MASK 0x0040 /* IN2R_ZC */
+#define WM8994_IN2R_ZC_SHIFT 6 /* IN2R_ZC */
+#define WM8994_IN2R_ZC_WIDTH 1 /* IN2R_ZC */
+#define WM8994_IN2R_VOL_30dB 0x001F
+#define WM8994_IN2R_VOL_25_5dB 0x001C
+#define WM8994_IN2R_VOL_21dB 0x0019
+#define WM8994_IN2R_VOL_16_5dB 0x0016
+#define WM8994_IN2R_VOL_12dB 0x0013
+#define WM8994_IN2R_VOL_7_5dB 0x0010
+#define WM8994_IN2R_VOL_3dB 0x000D
+#define WM8994_IN2R_VOL_n1_5dB 0x000A
+#define WM8994_IN2R_VOL_n6dB 0x0007
+#define WM8994_IN2R_VOL_n10_5dB 0x0004
+#define WM8994_IN2R_VOL_n13_5dB 0x0002
+#define WM8994_IN2R_VOL_n16_5dB 0x0000
+#define WM8994_IN2R_VOL_MASK 0x001F /* IN2R_VOL - [4:0] */
+#define WM8994_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [4:0] */
+#define WM8994_IN2R_VOL_WIDTH 5 /* IN2R_VOL - [4:0] */
+
+/*
+ * R28 (0x1C) - Left Output Volume
+ */
+#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
+#define WM8994_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
+#define WM8994_HPOUT1L_MUTE_N 0x0040 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_MUTE_N_MASK 0x0040 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_MUTE_N_SHIFT 6 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_MUTE_N_WIDTH 1 /* HPOUT1L_MUTE_N */
+#define WM8994_HPOUT1L_VOL_6dB 0x003F
+#define WM8994_HPOUT1L_VOL_n10dB 0x002F
+#define WM8994_HPOUT1L_VOL_n26dB 0x001F
+#define WM8994_HPOUT1L_VOL_n42dB 0x000F
+#define WM8994_HPOUT1L_VOL_n57dB 0x0000
+#define WM8994_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */
+#define WM8994_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */
+#define WM8994_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */
+
+/*
+ * R29 (0x1D) - Right Output Volume
+ */
+#define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */
+#define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */
+#define WM8994_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
+#define WM8994_HPOUT1R_MUTE_N 0x0040 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_MUTE_N_MASK 0x0040 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_MUTE_N_SHIFT 6 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_MUTE_N_WIDTH 1 /* HPOUT1R_MUTE_N */
+#define WM8994_HPOUT1R_VOL_6dB 0x003F
+#define WM8994_HPOUT1R_VOL_n10dB 0x002F
+#define WM8994_HPOUT1R_VOL_n26dB 0x001F
+#define WM8994_HPOUT1R_VOL_n42dB 0x000F
+#define WM8994_HPOUT1R_VOL_n57dB 0x0000
+#define WM8994_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */
+#define WM8994_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */
+#define WM8994_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */
+
+/*
+ * R30 (0x1E) - Line Outputs Volume
+ */
+#define WM8994_LINEOUT1N_MUTE 0x0040 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1N_MUTE_MASK 0x0040 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1N_MUTE_SHIFT 6 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1N_MUTE_WIDTH 1 /* LINEOUT1N_MUTE */
+#define WM8994_LINEOUT1P_MUTE 0x0020 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1P_MUTE_MASK 0x0020 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1P_MUTE_SHIFT 5 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1P_MUTE_WIDTH 1 /* LINEOUT1P_MUTE */
+#define WM8994_LINEOUT1_VOL 0x0010 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT1_VOL_MASK 0x0010 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT1_VOL_SHIFT 4 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT1_VOL_WIDTH 1 /* LINEOUT1_VOL */
+#define WM8994_LINEOUT2N_MUTE 0x0004 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2N_MUTE_MASK 0x0004 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2N_MUTE_SHIFT 2 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2N_MUTE_WIDTH 1 /* LINEOUT2N_MUTE */
+#define WM8994_LINEOUT2P_MUTE 0x0002 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2P_MUTE_MASK 0x0002 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2P_MUTE_SHIFT 1 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2P_MUTE_WIDTH 1 /* LINEOUT2P_MUTE */
+#define WM8994_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */
+#define WM8994_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */
+#define WM8994_LINEOUT2_VOL_SHIFT 0 /* LINEOUT2_VOL */
+#define WM8994_LINEOUT2_VOL_WIDTH 1 /* LINEOUT2_VOL */
+
+/*
+ * R31 (0x1F) - HPOUT2 Volume
+ */
+#define WM8994_HPOUT2_MUTE 0x0020 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_MUTE_MASK 0x0020 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_MUTE_SHIFT 5 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_MUTE_WIDTH 1 /* HPOUT2_MUTE */
+#define WM8994_HPOUT2_VOL 0x0010 /* HPOUT2_VOL */
+#define WM8994_HPOUT2_VOL_MASK 0x0010 /* HPOUT2_VOL */
+#define WM8994_HPOUT2_VOL_SHIFT 4 /* HPOUT2_VOL */
+#define WM8994_HPOUT2_VOL_WIDTH 1 /* HPOUT2_VOL */
+
+/*
+ * R32 (0x20) - Left OPGA Volume
+ */
+#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */
+#define WM8994_MIXOUTL_ZC 0x0080 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_ZC_MASK 0x0080 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_ZC_SHIFT 7 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_ZC_WIDTH 1 /* MIXOUTL_ZC */
+#define WM8994_MIXOUTL_MUTE_N 0x0040 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_MUTE_N_MASK 0x0040 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_MUTE_N_SHIFT 6 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_MUTE_N_WIDTH 1 /* MIXOUTL_MUTE_N */
+#define WM8994_MIXOUTL_VOL_MASK 0x003F /* MIXOUTL_VOL - [5:0] */
+#define WM8994_MIXOUTL_VOL_SHIFT 0 /* MIXOUTL_VOL - [5:0] */
+#define WM8994_MIXOUTL_VOL_WIDTH 6 /* MIXOUTL_VOL - [5:0] */
+
+/*
+ * R33 (0x21) - Right OPGA Volume
+ */
+#define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */
+#define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */
+#define WM8994_MIXOUTR_ZC 0x0080 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_ZC_MASK 0x0080 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_ZC_SHIFT 7 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_ZC_WIDTH 1 /* MIXOUTR_ZC */
+#define WM8994_MIXOUTR_MUTE_N 0x0040 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_MUTE_N_MASK 0x0040 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_MUTE_N_SHIFT 6 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_MUTE_N_WIDTH 1 /* MIXOUTR_MUTE_N */
+#define WM8994_MIXOUTR_VOL_MASK 0x003F /* MIXOUTR_VOL - [5:0] */
+#define WM8994_MIXOUTR_VOL_SHIFT 0 /* MIXOUTR_VOL - [5:0] */
+#define WM8994_MIXOUTR_VOL_WIDTH 6 /* MIXOUTR_VOL - [5:0] */
+
+/*
+ * R34 (0x22) - SPKMIXL Attenuation
+ */
+#define WM8994_DAC2L_SPKMIXL_VOL 0x0040 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_DAC2L_SPKMIXL_VOL_MASK 0x0040 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_DAC2L_SPKMIXL_VOL_SHIFT 6 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_DAC2L_SPKMIXL_VOL_WIDTH 1 /* DAC2L_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL 0x0020 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL_MASK 0x0020 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL_SHIFT 5 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL 0x0010 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL_MASK 0x0010 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL_SHIFT 4 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_IN1LP_SPKMIXL_VOL_WIDTH 1 /* IN1LP_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL 0x0008 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL_MASK 0x0008 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT 3 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH 1 /* MIXOUTL_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL 0x0004 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL_MASK 0x0004 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL_SHIFT 2 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_DAC1L_SPKMIXL_VOL_WIDTH 1 /* DAC1L_SPKMIXL_VOL */
+#define WM8994_SPKMIXL_VOL_MASK 0x0003 /* SPKMIXL_VOL - [1:0] */
+#define WM8994_SPKMIXL_VOL_SHIFT 0 /* SPKMIXL_VOL - [1:0] */
+#define WM8994_SPKMIXL_VOL_WIDTH 2 /* SPKMIXL_VOL - [1:0] */
+
+/*
+ * R35 (0x23) - SPKMIXR Attenuation
+ */
+#define WM8994_SPKOUT_CLASSAB 0x0100 /* SPKOUT_CLASSAB */
+#define WM8994_SPKOUT_CLASSAB_MASK 0x0100 /* SPKOUT_CLASSAB */
+#define WM8994_SPKOUT_CLASSAB_SHIFT 8 /* SPKOUT_CLASSAB */
+#define WM8994_SPKOUT_CLASSAB_WIDTH 1 /* SPKOUT_CLASSAB */
+#define WM8994_DAC2R_SPKMIXR_VOL 0x0040 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_DAC2R_SPKMIXR_VOL_MASK 0x0040 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_DAC2R_SPKMIXR_VOL_SHIFT 6 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_DAC2R_SPKMIXR_VOL_WIDTH 1 /* DAC2R_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL 0x0020 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL_MASK 0x0020 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL_SHIFT 5 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL 0x0010 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL_MASK 0x0010 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL_SHIFT 4 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_IN1RP_SPKMIXR_VOL_WIDTH 1 /* IN1RP_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL 0x0008 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL_MASK 0x0008 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT 3 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH 1 /* MIXOUTR_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL 0x0004 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL_MASK 0x0004 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL_SHIFT 2 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_DAC1R_SPKMIXR_VOL_WIDTH 1 /* DAC1R_SPKMIXR_VOL */
+#define WM8994_SPKMIXR_VOL_MASK 0x0003 /* SPKMIXR_VOL - [1:0] */
+#define WM8994_SPKMIXR_VOL_SHIFT 0 /* SPKMIXR_VOL - [1:0] */
+#define WM8994_SPKMIXR_VOL_WIDTH 2 /* SPKMIXR_VOL - [1:0] */
+
+/*
+ * R36 (0x24) - SPKOUT Mixers
+ */
+#define WM8994_IN2LP_TO_SPKOUTL 0x0020 /* IN2LP_TO_SPKOUTL */
+#define WM8994_IN2LP_TO_SPKOUTL_MASK 0x0020 /* IN2LP_TO_SPKOUTL */
+#define WM8994_IN2LP_TO_SPKOUTL_SHIFT 5 /* IN2LP_TO_SPKOUTL */
+#define WM8994_IN2LP_TO_SPKOUTL_WIDTH 1 /* IN2LP_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL 0x0008 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL_MASK 0x0008 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT 3 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH 1 /* SPKMIXR_TO_SPKOUTL */
+#define WM8994_IN2LP_TO_SPKOUTR 0x0004 /* IN2LP_TO_SPKOUTR */
+#define WM8994_IN2LP_TO_SPKOUTR_MASK 0x0004 /* IN2LP_TO_SPKOUTR */
+#define WM8994_IN2LP_TO_SPKOUTR_SHIFT 2 /* IN2LP_TO_SPKOUTR */
+#define WM8994_IN2LP_TO_SPKOUTR_WIDTH 1 /* IN2LP_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR 0x0002 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR_MASK 0x0002 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT 1 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH 1 /* SPKMIXL_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT 0 /* SPKMIXR_TO_SPKOUTR */
+#define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH 1 /* SPKMIXR_TO_SPKOUTR */
+
+/*
+ * R37 (0x25) - ClassD
+ */
+#define WM8994_CLASSD_DEFAULT 0x0140 /* Default Setting - [8:6] */
+#define WM8994_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */
+#define WM8994_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */
+#define WM8994_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */
+#define WM8994_SPKOUTR_BOOST_MASK 0x0007 /* SPKOUTR_BOOST - [2:0] */
+#define WM8994_SPKOUTR_BOOST_SHIFT 0 /* SPKOUTR_BOOST - [2:0] */
+#define WM8994_SPKOUTR_BOOST_WIDTH 3 /* SPKOUTR_BOOST - [2:0] */
+
+/*
+ * R38 (0x26) - Speaker Volume Left
+ */
+#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
+#define WM8994_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */
+#define WM8994_SPKOUTL_MUTE_N 0x0040 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_MUTE_N_MASK 0x0040 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_MUTE_N_SHIFT 6 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_MUTE_N_WIDTH 1 /* SPKOUTL_MUTE_N */
+#define WM8994_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */
+#define WM8994_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */
+#define WM8994_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */
+
+/*
+ * R39 (0x27) - Speaker Volume Right
+ */
+#define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */
+#define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
+#define WM8994_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */
+#define WM8994_SPKOUTR_MUTE_N 0x0040 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_MUTE_N_MASK 0x0040 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_MUTE_N_SHIFT 6 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_MUTE_N_WIDTH 1 /* SPKOUTR_MUTE_N */
+#define WM8994_SPKOUTR_VOL_MASK 0x003F /* SPKOUTR_VOL - [5:0] */
+#define WM8994_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [5:0] */
+#define WM8994_SPKOUTR_VOL_WIDTH 6 /* SPKOUTR_VOL - [5:0] */
+
+/*
+ * R40 (0x28) - Input Mixer (2)
+ */
+#define WM8994_IN2LP_TO_IN2L 0x0080 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LP_TO_IN2L_MASK 0x0080 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LP_TO_IN2L_SHIFT 7 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LP_TO_IN2L_WIDTH 1 /* IN2LP_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L 0x0040 /* IN2LN_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L_MASK 0x0040 /* IN2LN_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L_SHIFT 6 /* IN2LN_TO_IN2L */
+#define WM8994_IN2LN_TO_IN2L_WIDTH 1 /* IN2LN_TO_IN2L */
+#define WM8994_IN1LP_TO_IN1L 0x0020 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LP_TO_IN1L_MASK 0x0020 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LP_TO_IN1L_SHIFT 5 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LP_TO_IN1L_WIDTH 1 /* IN1LP_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L 0x0010 /* IN1LN_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L_MASK 0x0010 /* IN1LN_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L_SHIFT 4 /* IN1LN_TO_IN1L */
+#define WM8994_IN1LN_TO_IN1L_WIDTH 1 /* IN1LN_TO_IN1L */
+#define WM8994_IN2RP_TO_IN2R 0x0008 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RP_TO_IN2R_MASK 0x0008 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RP_TO_IN2R_SHIFT 3 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RP_TO_IN2R_WIDTH 1 /* IN2RP_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R 0x0004 /* IN2RN_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R_MASK 0x0004 /* IN2RN_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R_SHIFT 2 /* IN2RN_TO_IN2R */
+#define WM8994_IN2RN_TO_IN2R_WIDTH 1 /* IN2RN_TO_IN2R */
+#define WM8994_IN1RP_TO_IN1R 0x0002 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RP_TO_IN1R_MASK 0x0002 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RP_TO_IN1R_SHIFT 1 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RP_TO_IN1R_WIDTH 1 /* IN1RP_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R_SHIFT 0 /* IN1RN_TO_IN1R */
+#define WM8994_IN1RN_TO_IN1R_WIDTH 1 /* IN1RN_TO_IN1R */
+
+/*
+ * R41 (0x29) - Input Mixer (3)
+ */
+#define WM8994_IN2L_TO_MIXINL 0x0100 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_TO_MIXINL_MASK 0x0100 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_TO_MIXINL_SHIFT 8 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */
+#define WM8994_IN2L_MIXINL_VOL 0x0080 /* IN2L_MIXINL_VOL */
+#define WM8994_IN2L_MIXINL_VOL_MASK 0x0080 /* IN2L_MIXINL_VOL */
+#define WM8994_IN2L_MIXINL_VOL_SHIFT 7 /* IN2L_MIXINL_VOL */
+#define WM8994_IN2L_MIXINL_VOL_WIDTH 1 /* IN2L_MIXINL_VOL */
+#define WM8994_IN1L_TO_MIXINL 0x0020 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_TO_MIXINL_MASK 0x0020 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_TO_MIXINL_SHIFT 5 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_TO_MIXINL_WIDTH 1 /* IN1L_TO_MIXINL */
+#define WM8994_IN1L_MIXINL_VOL 0x0010 /* IN1L_MIXINL_VOL */
+#define WM8994_IN1L_MIXINL_VOL_MASK 0x0010 /* IN1L_MIXINL_VOL */
+#define WM8994_IN1L_MIXINL_VOL_SHIFT 4 /* IN1L_MIXINL_VOL */
+#define WM8994_IN1L_MIXINL_VOL_WIDTH 1 /* IN1L_MIXINL_VOL */
+#define WM8994_MIXOUTL_MIXINL_VOL_MASK 0x0007 /* MIXOUTL_MIXINL_VOL - [2:0] */
+#define WM8994_MIXOUTL_MIXINL_VOL_SHIFT 0 /* MIXOUTL_MIXINL_VOL - [2:0] */
+#define WM8994_MIXOUTL_MIXINL_VOL_WIDTH 3 /* MIXOUTL_MIXINL_VOL - [2:0] */
+
+/*
+ * R42 (0x2A) - Input Mixer (4)
+ */
+#define WM8994_IN2R_TO_MIXINR 0x0100 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_TO_MIXINR_MASK 0x0100 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_TO_MIXINR_SHIFT 8 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */
+#define WM8994_IN2R_MIXINR_VOL 0x0080 /* IN2R_MIXINR_VOL */
+#define WM8994_IN2R_MIXINR_VOL_MASK 0x0080 /* IN2R_MIXINR_VOL */
+#define WM8994_IN2R_MIXINR_VOL_SHIFT 7 /* IN2R_MIXINR_VOL */
+#define WM8994_IN2R_MIXINR_VOL_WIDTH 1 /* IN2R_MIXINR_VOL */
+#define WM8994_IN1R_TO_MIXINR 0x0020 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_TO_MIXINR_MASK 0x0020 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_TO_MIXINR_SHIFT 5 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_TO_MIXINR_WIDTH 1 /* IN1R_TO_MIXINR */
+#define WM8994_IN1R_MIXINR_VOL 0x0010 /* IN1R_MIXINR_VOL */
+#define WM8994_IN1R_MIXINR_VOL_MASK 0x0010 /* IN1R_MIXINR_VOL */
+#define WM8994_IN1R_MIXINR_VOL_SHIFT 4 /* IN1R_MIXINR_VOL */
+#define WM8994_IN1R_MIXINR_VOL_WIDTH 1 /* IN1R_MIXINR_VOL */
+#define WM8994_MIXOUTR_MIXINR_VOL_MASK 0x0007 /* MIXOUTR_MIXINR_VOL - [2:0] */
+#define WM8994_MIXOUTR_MIXINR_VOL_SHIFT 0 /* MIXOUTR_MIXINR_VOL - [2:0] */
+#define WM8994_MIXOUTR_MIXINR_VOL_WIDTH 3 /* MIXOUTR_MIXINR_VOL - [2:0] */
+
+/*
+ * R43 (0x2B) - Input Mixer (5)
+ */
+#define WM8994_IN1LP_MIXINL_VOL_MASK 0x01C0 /* IN1LP_MIXINL_VOL - [8:6] */
+#define WM8994_IN1LP_MIXINL_VOL_SHIFT 6 /* IN1LP_MIXINL_VOL - [8:6] */
+#define WM8994_IN1LP_MIXINL_VOL_WIDTH 3 /* IN1LP_MIXINL_VOL - [8:6] */
+#define WM8994_IN2LP_MIXINL_VOL_MASK 0x0007 /* IN2LP_MIXINL_VOL - [2:0] */
+#define WM8994_IN2LP_MIXINL_VOL_SHIFT 0 /* IN2LP_MIXINL_VOL - [2:0] */
+#define WM8994_IN2LP_MIXINL_VOL_WIDTH 3 /* IN2LP_MIXINL_VOL - [2:0] */
+
+/*
+ * R44 (0x2C) - Input Mixer (6)
+ */
+#define WM8994_IN1RP_MIXINR_VOL_MASK 0x01C0 /* IN1RP_MIXINR_VOL - [8:6] */
+#define WM8994_IN1RP_MIXINR_VOL_SHIFT 6 /* IN1RP_MIXINR_VOL - [8:6] */
+#define WM8994_IN1RP_MIXINR_VOL_WIDTH 3 /* IN1RP_MIXINR_VOL - [8:6] */
+#define WM8994_IN2LP_MIXINR_VOL_MASK 0x0007 /* IN2LP_MIXINR_VOL - [2:0] */
+#define WM8994_IN2LP_MIXINR_VOL_SHIFT 0 /* IN2LP_MIXINR_VOL - [2:0] */
+#define WM8994_IN2LP_MIXINR_VOL_WIDTH 3 /* IN2LP_MIXINR_VOL - [2:0] */
+
+/*
+ * R45 (0x2D) - Output Mixer (1)
+ */
+#define WM8994_DAC1L_TO_HPOUT1L 0x0100 /* DAC1L_TO_HPOUT1L */
+#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 /* DAC1L_TO_HPOUT1L */
+#define WM8994_DAC1L_TO_HPOUT1L_SHIFT 8 /* DAC1L_TO_HPOUT1L */
+#define WM8994_DAC1L_TO_HPOUT1L_WIDTH 1 /* DAC1L_TO_HPOUT1L */
+#define WM8994_MIXINR_TO_MIXOUTL 0x0080 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINR_TO_MIXOUTL_MASK 0x0080 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINR_TO_MIXOUTL_SHIFT 7 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINR_TO_MIXOUTL_WIDTH 1 /* MIXINR_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL 0x0040 /* MIXINL_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL_MASK 0x0040 /* MIXINL_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL_SHIFT 6 /* MIXINL_TO_MIXOUTL */
+#define WM8994_MIXINL_TO_MIXOUTL_WIDTH 1 /* MIXINL_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL 0x0020 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL_MASK 0x0020 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL_SHIFT 5 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2RN_TO_MIXOUTL_WIDTH 1 /* IN2RN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL 0x0010 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL_MASK 0x0010 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL_SHIFT 4 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN2LN_TO_MIXOUTL_WIDTH 1 /* IN2LN_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL 0x0008 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL_MASK 0x0008 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL_SHIFT 3 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1R_TO_MIXOUTL_WIDTH 1 /* IN1R_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL 0x0004 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL_MASK 0x0004 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL_SHIFT 2 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN1L_TO_MIXOUTL_WIDTH 1 /* IN1L_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL 0x0002 /* IN2LP_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL_MASK 0x0002 /* IN2LP_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL_SHIFT 1 /* IN2LP_TO_MIXOUTL */
+#define WM8994_IN2LP_TO_MIXOUTL_WIDTH 1 /* IN2LP_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL 0x0001 /* DAC1L_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL_MASK 0x0001 /* DAC1L_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL_SHIFT 0 /* DAC1L_TO_MIXOUTL */
+#define WM8994_DAC1L_TO_MIXOUTL_WIDTH 1 /* DAC1L_TO_MIXOUTL */
+
+/*
+ * R46 (0x2E) - Output Mixer (2)
+ */
+#define WM8994_DAC1R_TO_HPOUT1R 0x0100 /* DAC1R_TO_HPOUT1R */
+#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 /* DAC1R_TO_HPOUT1R */
+#define WM8994_DAC1R_TO_HPOUT1R_SHIFT 8 /* DAC1R_TO_HPOUT1R */
+#define WM8994_DAC1R_TO_HPOUT1R_WIDTH 1 /* DAC1R_TO_HPOUT1R */
+#define WM8994_MIXINL_TO_MIXOUTR 0x0080 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINL_TO_MIXOUTR_MASK 0x0080 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINL_TO_MIXOUTR_SHIFT 7 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINL_TO_MIXOUTR_WIDTH 1 /* MIXINL_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR 0x0040 /* MIXINR_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR_MASK 0x0040 /* MIXINR_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR_SHIFT 6 /* MIXINR_TO_MIXOUTR */
+#define WM8994_MIXINR_TO_MIXOUTR_WIDTH 1 /* MIXINR_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR 0x0020 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR_MASK 0x0020 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR_SHIFT 5 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2LN_TO_MIXOUTR_WIDTH 1 /* IN2LN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR 0x0010 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR_MASK 0x0010 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR_SHIFT 4 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN2RN_TO_MIXOUTR_WIDTH 1 /* IN2RN_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR 0x0008 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR_MASK 0x0008 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR_SHIFT 3 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1L_TO_MIXOUTR_WIDTH 1 /* IN1L_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR 0x0004 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR_MASK 0x0004 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR_SHIFT 2 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN1R_TO_MIXOUTR_WIDTH 1 /* IN1R_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR 0x0002 /* IN2RP_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR_MASK 0x0002 /* IN2RP_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR_SHIFT 1 /* IN2RP_TO_MIXOUTR */
+#define WM8994_IN2RP_TO_MIXOUTR_WIDTH 1 /* IN2RP_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR 0x0001 /* DAC1R_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR_MASK 0x0001 /* DAC1R_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR_SHIFT 0 /* DAC1R_TO_MIXOUTR */
+#define WM8994_DAC1R_TO_MIXOUTR_WIDTH 1 /* DAC1R_TO_MIXOUTR */
+
+/*
+ * R47 (0x2F) - Output Mixer (3)
+ */
+#define WM8994_IN2LP_MIXOUTL_VOL_MASK 0x0E00 /* IN2LP_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2LP_MIXOUTL_VOL_SHIFT 9 /* IN2LP_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2LP_MIXOUTL_VOL_WIDTH 3 /* IN2LP_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2LN_MIXOUTL_VOL_MASK 0x01C0 /* IN2LN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTL_VOL_SHIFT 6 /* IN2LN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTL_VOL_WIDTH 3 /* IN2LN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN1R_MIXOUTL_VOL_MASK 0x0038 /* IN1R_MIXOUTL_VOL - [5:3] */
+#define WM8994_IN1R_MIXOUTL_VOL_SHIFT 3 /* IN1R_MIXOUTL_VOL - [5:3] */
+#define WM8994_IN1R_MIXOUTL_VOL_WIDTH 3 /* IN1R_MIXOUTL_VOL - [5:3] */
+#define WM8994_IN1L_MIXOUTL_VOL_MASK 0x0007 /* IN1L_MIXOUTL_VOL - [2:0] */
+#define WM8994_IN1L_MIXOUTL_VOL_SHIFT 0 /* IN1L_MIXOUTL_VOL - [2:0] */
+#define WM8994_IN1L_MIXOUTL_VOL_WIDTH 3 /* IN1L_MIXOUTL_VOL - [2:0] */
+
+/*
+ * R48 (0x30) - Output Mixer (4)
+ */
+#define WM8994_IN2RP_MIXOUTR_VOL_MASK 0x0E00 /* IN2RP_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2RP_MIXOUTR_VOL_SHIFT 9 /* IN2RP_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2RP_MIXOUTR_VOL_WIDTH 3 /* IN2RP_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2RN_MIXOUTR_VOL_MASK 0x01C0 /* IN2RN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTR_VOL_SHIFT 6 /* IN2RN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTR_VOL_WIDTH 3 /* IN2RN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN1L_MIXOUTR_VOL_MASK 0x0038 /* IN1L_MIXOUTR_VOL - [5:3] */
+#define WM8994_IN1L_MIXOUTR_VOL_SHIFT 3 /* IN1L_MIXOUTR_VOL - [5:3] */
+#define WM8994_IN1L_MIXOUTR_VOL_WIDTH 3 /* IN1L_MIXOUTR_VOL - [5:3] */
+#define WM8994_IN1R_MIXOUTR_VOL_MASK 0x0007 /* IN1R_MIXOUTR_VOL - [2:0] */
+#define WM8994_IN1R_MIXOUTR_VOL_SHIFT 0 /* IN1R_MIXOUTR_VOL - [2:0] */
+#define WM8994_IN1R_MIXOUTR_VOL_WIDTH 3 /* IN1R_MIXOUTR_VOL - [2:0] */
+
+/*
+ * R49 (0x31) - Output Mixer (5)
+ */
+#define WM8994_DACL_MIXOUTL_VOL_MASK 0x0E00 /* DACL_MIXOUTL_VOL - [11:9] */
+#define WM8994_DACL_MIXOUTL_VOL_SHIFT 9 /* DACL_MIXOUTL_VOL - [11:9] */
+#define WM8994_DACL_MIXOUTL_VOL_WIDTH 3 /* DACL_MIXOUTL_VOL - [11:9] */
+#define WM8994_IN2RN_MIXOUTL_VOL_MASK 0x01C0 /* IN2RN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTL_VOL_SHIFT 6 /* IN2RN_MIXOUTL_VOL - [8:6] */
+#define WM8994_IN2RN_MIXOUTL_VOL_WIDTH 3 /* IN2RN_MIXOUTL_VOL - [8:6] */
+#define WM8994_MIXINR_MIXOUTL_VOL_MASK 0x0038 /* MIXINR_MIXOUTL_VOL - [5:3] */
+#define WM8994_MIXINR_MIXOUTL_VOL_SHIFT 3 /* MIXINR_MIXOUTL_VOL - [5:3] */
+#define WM8994_MIXINR_MIXOUTL_VOL_WIDTH 3 /* MIXINR_MIXOUTL_VOL - [5:3] */
+#define WM8994_MIXINL_MIXOUTL_VOL_MASK 0x0007 /* MIXINL_MIXOUTL_VOL - [2:0] */
+#define WM8994_MIXINL_MIXOUTL_VOL_SHIFT 0 /* MIXINL_MIXOUTL_VOL - [2:0] */
+#define WM8994_MIXINL_MIXOUTL_VOL_WIDTH 3 /* MIXINL_MIXOUTL_VOL - [2:0] */
+
+/*
+ * R50 (0x32) - Output Mixer (6)
+ */
+#define WM8994_DACR_MIXOUTR_VOL_MASK 0x0E00 /* DACR_MIXOUTR_VOL - [11:9] */
+#define WM8994_DACR_MIXOUTR_VOL_SHIFT 9 /* DACR_MIXOUTR_VOL - [11:9] */
+#define WM8994_DACR_MIXOUTR_VOL_WIDTH 3 /* DACR_MIXOUTR_VOL - [11:9] */
+#define WM8994_IN2LN_MIXOUTR_VOL_MASK 0x01C0 /* IN2LN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTR_VOL_SHIFT 6 /* IN2LN_MIXOUTR_VOL - [8:6] */
+#define WM8994_IN2LN_MIXOUTR_VOL_WIDTH 3 /* IN2LN_MIXOUTR_VOL - [8:6] */
+#define WM8994_MIXINL_MIXOUTR_VOL_MASK 0x0038 /* MIXINL_MIXOUTR_VOL - [5:3] */
+#define WM8994_MIXINL_MIXOUTR_VOL_SHIFT 3 /* MIXINL_MIXOUTR_VOL - [5:3] */
+#define WM8994_MIXINL_MIXOUTR_VOL_WIDTH 3 /* MIXINL_MIXOUTR_VOL - [5:3] */
+#define WM8994_MIXINR_MIXOUTR_VOL_MASK 0x0007 /* MIXINR_MIXOUTR_VOL - [2:0] */
+#define WM8994_MIXINR_MIXOUTR_VOL_SHIFT 0 /* MIXINR_MIXOUTR_VOL - [2:0] */
+#define WM8994_MIXINR_MIXOUTR_VOL_WIDTH 3 /* MIXINR_MIXOUTR_VOL - [2:0] */
+
+/*
+ * R51 (0x33) - HPOUT2 Mixer
+ */
+#define WM8994_IN2LRP_TO_HPOUT2 0x0020 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_IN2LRP_TO_HPOUT2_MASK 0x0020 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_IN2LRP_TO_HPOUT2_SHIFT 5 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_IN2LRP_TO_HPOUT2_WIDTH 1 /* IN2LRP_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT 4 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTLVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT 3 /* MIXOUTRVOL_TO_HPOUT2 */
+#define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTRVOL_TO_HPOUT2 */
+
+/*
+ * R52 (0x34) - Line Mixer (1)
+ */
+#define WM8994_MIXOUTL_TO_LINEOUT1N 0x0040 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTL_TO_LINEOUT1N_MASK 0x0040 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT 6 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH 1 /* MIXOUTL_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N 0x0020 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N_MASK 0x0020 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT 5 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH 1 /* MIXOUTR_TO_LINEOUT1N */
+#define WM8994_LINEOUT1_MODE 0x0010 /* LINEOUT1_MODE */
+#define WM8994_LINEOUT1_MODE_MASK 0x0010 /* LINEOUT1_MODE */
+#define WM8994_LINEOUT1_MODE_SHIFT 4 /* LINEOUT1_MODE */
+#define WM8994_LINEOUT1_MODE_WIDTH 1 /* LINEOUT1_MODE */
+#define WM8994_IN1R_TO_LINEOUT1P 0x0004 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1R_TO_LINEOUT1P_MASK 0x0004 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1R_TO_LINEOUT1P_SHIFT 2 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1R_TO_LINEOUT1P_WIDTH 1 /* IN1R_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P 0x0002 /* IN1L_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P_MASK 0x0002 /* IN1L_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P_SHIFT 1 /* IN1L_TO_LINEOUT1P */
+#define WM8994_IN1L_TO_LINEOUT1P_WIDTH 1 /* IN1L_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT 0 /* MIXOUTL_TO_LINEOUT1P */
+#define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH 1 /* MIXOUTL_TO_LINEOUT1P */
+
+/*
+ * R53 (0x35) - Line Mixer (2)
+ */
+#define WM8994_MIXOUTR_TO_LINEOUT2N 0x0040 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTR_TO_LINEOUT2N_MASK 0x0040 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT 6 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH 1 /* MIXOUTR_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N 0x0020 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N_MASK 0x0020 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT 5 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH 1 /* MIXOUTL_TO_LINEOUT2N */
+#define WM8994_LINEOUT2_MODE 0x0010 /* LINEOUT2_MODE */
+#define WM8994_LINEOUT2_MODE_MASK 0x0010 /* LINEOUT2_MODE */
+#define WM8994_LINEOUT2_MODE_SHIFT 4 /* LINEOUT2_MODE */
+#define WM8994_LINEOUT2_MODE_WIDTH 1 /* LINEOUT2_MODE */
+#define WM8994_IN1L_TO_LINEOUT2P 0x0004 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1L_TO_LINEOUT2P_MASK 0x0004 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1L_TO_LINEOUT2P_SHIFT 2 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1L_TO_LINEOUT2P_WIDTH 1 /* IN1L_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P 0x0002 /* IN1R_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P_MASK 0x0002 /* IN1R_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P_SHIFT 1 /* IN1R_TO_LINEOUT2P */
+#define WM8994_IN1R_TO_LINEOUT2P_WIDTH 1 /* IN1R_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT 0 /* MIXOUTR_TO_LINEOUT2P */
+#define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH 1 /* MIXOUTR_TO_LINEOUT2P */
+
+/*
+ * R54 (0x36) - Speaker Mixer
+ */
+#define WM8994_DAC2L_TO_SPKMIXL 0x0200 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2L_TO_SPKMIXL_MASK 0x0200 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2L_TO_SPKMIXL_SHIFT 9 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2L_TO_SPKMIXL_WIDTH 1 /* DAC2L_TO_SPKMIXL */
+#define WM8994_DAC2R_TO_SPKMIXR 0x0100 /* DAC2R_TO_SPKMIXR */
+#define WM8994_DAC2R_TO_SPKMIXR_MASK 0x0100 /* DAC2R_TO_SPKMIXR */
+#define WM8994_DAC2R_TO_SPKMIXR_SHIFT 8 /* DAC2R_TO_SPKMIXR */
+#define WM8994_DAC2R_TO_SPKMIXR_WIDTH 1 /* DAC2R_TO_SPKMIXR */
+#define WM8994_MIXINL_TO_SPKMIXL 0x0080 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINL_TO_SPKMIXL_MASK 0x0080 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINL_TO_SPKMIXL_SHIFT 7 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */
+#define WM8994_MIXINR_TO_SPKMIXR 0x0040 /* MIXINR_TO_SPKMIXR */
+#define WM8994_MIXINR_TO_SPKMIXR_MASK 0x0040 /* MIXINR_TO_SPKMIXR */
+#define WM8994_MIXINR_TO_SPKMIXR_SHIFT 6 /* MIXINR_TO_SPKMIXR */
+#define WM8994_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */
+#define WM8994_IN1LP_TO_SPKMIXL 0x0020 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1LP_TO_SPKMIXL_MASK 0x0020 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1LP_TO_SPKMIXL_SHIFT 5 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1LP_TO_SPKMIXL_WIDTH 1 /* IN1LP_TO_SPKMIXL */
+#define WM8994_IN1RP_TO_SPKMIXR 0x0010 /* IN1RP_TO_SPKMIXR */
+#define WM8994_IN1RP_TO_SPKMIXR_MASK 0x0010 /* IN1RP_TO_SPKMIXR */
+#define WM8994_IN1RP_TO_SPKMIXR_SHIFT 4 /* IN1RP_TO_SPKMIXR */
+#define WM8994_IN1RP_TO_SPKMIXR_WIDTH 1 /* IN1RP_TO_SPKMIXR */
+#define WM8994_MIXOUTL_TO_SPKMIXL 0x0008 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTL_TO_SPKMIXL_MASK 0x0008 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT 3 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH 1 /* MIXOUTL_TO_SPKMIXL */
+#define WM8994_MIXOUTR_TO_SPKMIXR 0x0004 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_MIXOUTR_TO_SPKMIXR_MASK 0x0004 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT 2 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH 1 /* MIXOUTR_TO_SPKMIXR */
+#define WM8994_DAC1L_TO_SPKMIXL 0x0002 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1L_TO_SPKMIXL_MASK 0x0002 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1L_TO_SPKMIXL_SHIFT 1 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1L_TO_SPKMIXL_WIDTH 1 /* DAC1L_TO_SPKMIXL */
+#define WM8994_DAC1R_TO_SPKMIXR 0x0001 /* DAC1R_TO_SPKMIXR */
+#define WM8994_DAC1R_TO_SPKMIXR_MASK 0x0001 /* DAC1R_TO_SPKMIXR */
+#define WM8994_DAC1R_TO_SPKMIXR_SHIFT 0 /* DAC1R_TO_SPKMIXR */
+#define WM8994_DAC1R_TO_SPKMIXR_WIDTH 1 /* DAC1R_TO_SPKMIXR */
+
+/*
+ * R55 (0x37) - Additional Control
+ */
+#define WM8994_LINEOUT1_FB 0x0080 /* LINEOUT1_FB */
+#define WM8994_LINEOUT1_FB_MASK 0x0080 /* LINEOUT1_FB */
+#define WM8994_LINEOUT1_FB_SHIFT 7 /* LINEOUT1_FB */
+#define WM8994_LINEOUT1_FB_WIDTH 1 /* LINEOUT1_FB */
+#define WM8994_LINEOUT2_FB 0x0040 /* LINEOUT2_FB */
+#define WM8994_LINEOUT2_FB_MASK 0x0040 /* LINEOUT2_FB */
+#define WM8994_LINEOUT2_FB_SHIFT 6 /* LINEOUT2_FB */
+#define WM8994_LINEOUT2_FB_WIDTH 1 /* LINEOUT2_FB */
+#define WM8994_VROI 0x0001 /* VROI */
+#define WM8994_VROI_MASK 0x0001 /* VROI */
+#define WM8994_VROI_SHIFT 0 /* VROI */
+#define WM8994_VROI_WIDTH 1 /* VROI */
+
+/*
+ * R56 (0x38) - AntiPOP (1)
+ */
+#define WM8994_LINEOUT_VMID_BUF_ENA 0x0080 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_LINEOUT_VMID_BUF_ENA_MASK 0x0080 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT 7 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH 1 /* LINEOUT_VMID_BUF_ENA */
+#define WM8994_HPOUT2_IN_ENA 0x0040 /* HPOUT2_IN_ENA */
+#define WM8994_HPOUT2_IN_ENA_MASK 0x0040 /* HPOUT2_IN_ENA */
+#define WM8994_HPOUT2_IN_ENA_SHIFT 6 /* HPOUT2_IN_ENA */
+#define WM8994_HPOUT2_IN_ENA_WIDTH 1 /* HPOUT2_IN_ENA */
+#define WM8994_LINEOUT1_DISCH 0x0020 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT1_DISCH_MASK 0x0020 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT1_DISCH_SHIFT 5 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT1_DISCH_WIDTH 1 /* LINEOUT1_DISCH */
+#define WM8994_LINEOUT2_DISCH 0x0010 /* LINEOUT2_DISCH */
+#define WM8994_LINEOUT2_DISCH_MASK 0x0010 /* LINEOUT2_DISCH */
+#define WM8994_LINEOUT2_DISCH_SHIFT 4 /* LINEOUT2_DISCH */
+#define WM8994_LINEOUT2_DISCH_WIDTH 1 /* LINEOUT2_DISCH */
+
+/*
+ * R57 (0x39) - AntiPOP (2)
+ */
+#define WM8994_VMID_RAMP_MASK 0x0060 /* VMID_RAMP - [6:5] */
+#define WM8994_VMID_RAMP_SHIFT 5 /* VMID_RAMP - [6:5] */
+#define WM8994_VMID_RAMP_WIDTH 2 /* VMID_RAMP - [6:5] */
+#define WM8994_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */
+#define WM8994_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */
+#define WM8994_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */
+#define WM8994_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
+#define WM8994_STARTUP_BIAS_ENA 0x0004 /* STARTUP_BIAS_ENA */
+#define WM8994_STARTUP_BIAS_ENA_MASK 0x0004 /* STARTUP_BIAS_ENA */
+#define WM8994_STARTUP_BIAS_ENA_SHIFT 2 /* STARTUP_BIAS_ENA */
+#define WM8994_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
+#define WM8994_BIAS_SRC 0x0002 /* BIAS_SRC */
+#define WM8994_BIAS_SRC_MASK 0x0002 /* BIAS_SRC */
+#define WM8994_BIAS_SRC_SHIFT 1 /* BIAS_SRC */
+#define WM8994_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
+#define WM8994_VMID_DISCH 0x0001 /* VMID_DISCH */
+#define WM8994_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */
+#define WM8994_VMID_DISCH_SHIFT 0 /* VMID_DISCH */
+#define WM8994_VMID_DISCH_WIDTH 1 /* VMID_DISCH */
+
+/*
+ * R58 (0x3A) - MICBIAS
+ */
+#define WM8994_MICD_SCTHR_MASK 0x00C0 /* MICD_SCTHR - [7:6] */
+#define WM8994_MICD_SCTHR_SHIFT 6 /* MICD_SCTHR - [7:6] */
+#define WM8994_MICD_SCTHR_WIDTH 2 /* MICD_SCTHR - [7:6] */
+#define WM8994_MICD_THR_MASK 0x0038 /* MICD_THR - [5:3] */
+#define WM8994_MICD_THR_SHIFT 3 /* MICD_THR - [5:3] */
+#define WM8994_MICD_THR_WIDTH 3 /* MICD_THR - [5:3] */
+#define WM8994_MICD_ENA 0x0004 /* MICD_ENA */
+#define WM8994_MICD_ENA_MASK 0x0004 /* MICD_ENA */
+#define WM8994_MICD_ENA_SHIFT 2 /* MICD_ENA */
+#define WM8994_MICD_ENA_WIDTH 1 /* MICD_ENA */
+#define WM8994_MICB2_LVL 0x0002 /* MICB2_LVL */
+#define WM8994_MICB2_LVL_MASK 0x0002 /* MICB2_LVL */
+#define WM8994_MICB2_LVL_SHIFT 1 /* MICB2_LVL */
+#define WM8994_MICB2_LVL_WIDTH 1 /* MICB2_LVL */
+#define WM8994_MICB1_LVL 0x0001 /* MICB1_LVL */
+#define WM8994_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */
+#define WM8994_MICB1_LVL_SHIFT 0 /* MICB1_LVL */
+#define WM8994_MICB1_LVL_WIDTH 1 /* MICB1_LVL */
+
+/*
+ * R59 (0x3B) - LDO 1
+ */
+#define WM8994_LDO1_VSEL_MASK 0x000E /* LDO1_VSEL - [3:1] */
+#define WM8994_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [3:1] */
+#define WM8994_LDO1_VSEL_WIDTH 3 /* LDO1_VSEL - [3:1] */
+#define WM8994_LDO1_DISCH 0x0001 /* LDO1_DISCH */
+#define WM8994_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
+#define WM8994_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
+#define WM8994_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
+
+/*
+ * R60 (0x3C) - LDO 2
+ */
+#define WM8994_LDO2_VSEL_MASK 0x0006 /* LDO2_VSEL - [2:1] */
+#define WM8994_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [2:1] */
+#define WM8994_LDO2_VSEL_WIDTH 2 /* LDO2_VSEL - [2:1] */
+#define WM8994_LDO2_DISCH 0x0001 /* LDO2_DISCH */
+#define WM8994_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
+#define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
+#define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
+
+/*
+ * R76 (0x4C) - Charge Pump (1)
+ */
+#define WM8994_CP_ENA 0x8000 /* CP_ENA */
+#define WM8994_CP_ENA_MASK 0x8000 /* CP_ENA */
+#define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */
+#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */
+#define WM8994_CP_ENA_DEFAULT 0x1F25
+
+/*
+ * R81 (0x51) - Class W (1)
+ */
+#define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8994_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */
+#define WM8994_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
+#define WM8994_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
+#define WM8994_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */
+#define WM8994_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
+
+/*
+ * R84 (0x54) - DC Servo (1)
+ */
+#define WM8994_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
+#define WM8994_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
+#define WM8994_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
+#define WM8994_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
+#define WM8994_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
+#define WM8994_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
+#define WM8994_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
+#define WM8994_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
+#define WM8994_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
+#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
+#define WM8994_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
+#define WM8994_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
+
+/*
+ * R85 (0x55) - DC Servo (2)
+ */
+#define WM8994_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */
+#define WM8994_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */
+#define WM8994_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */
+#define WM8994_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8994_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
+#define WM8994_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
+
+/*
+ * R87 (0x57) - DC Servo (4)
+ */
+#define WM8994_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8994_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8994_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
+#define WM8994_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8994_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
+#define WM8994_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
+
+/*
+ * R88 (0x58) - DC Servo Readback
+ */
+#define WM8994_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */
+#define WM8994_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */
+#define WM8994_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */
+#define WM8994_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */
+#define WM8994_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */
+#define WM8994_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */
+#define WM8994_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */
+#define WM8994_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */
+#define WM8994_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */
+
+/*
+ * R91 (0x5B) - DC Servo ANA (1)
+ */
+#define WM8994_DCS_IDAC_VAL_1_MASK 0x00FF /* DCS_IDAC_VAL_1 - [7:0] */
+#define WM8994_DCS_IDAC_VAL_1_SHIFT 0 /* DCS_IDAC_VAL_1 - [7:0] */
+#define WM8994_DCS_IDAC_VAL_1_WIDTH 8 /* DCS_IDAC_VAL_1 - [7:0] */
+
+/*
+ * R92 (0x5C) - DC Servo ANA (2)
+ */
+#define WM8994_DCS_IDAC_VAL_0_MASK 0x00FF /* DCS_IDAC_VAL_0 - [7:0] */
+#define WM8994_DCS_IDAC_VAL_0_SHIFT 0 /* DCS_IDAC_VAL_0 - [7:0] */
+#define WM8994_DCS_IDAC_VAL_0_WIDTH 8 /* DCS_IDAC_VAL_0 - [7:0] */
+
+/*
+ * R96 (0x60) - Analogue HP (1)
+ */
+#define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
+#define WM8994_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
+#define WM8994_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
+#define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
+#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
+
+/*
+ * R257 (0x101) - Control Interface
+ */
+#define WM8994_REG_SYNC 0x8000 /* REG_SYNC */
+#define WM8994_REG_SYNC_MASK 0x8000 /* REG_SYNC */
+#define WM8994_REG_SYNC_SHIFT 15 /* REG_SYNC */
+#define WM8994_REG_SYNC_WIDTH 1 /* REG_SYNC */
+#define WM8994_SPI_CONTRD 0x0040 /* SPI_CONTRD */
+#define WM8994_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */
+#define WM8994_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */
+#define WM8994_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
+#define WM8994_SPI_4WIRE 0x0020 /* SPI_4WIRE */
+#define WM8994_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */
+#define WM8994_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */
+#define WM8994_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
+#define WM8994_SPI_CFG 0x0010 /* SPI_CFG */
+#define WM8994_SPI_CFG_MASK 0x0010 /* SPI_CFG */
+#define WM8994_SPI_CFG_SHIFT 4 /* SPI_CFG */
+#define WM8994_SPI_CFG_WIDTH 1 /* SPI_CFG */
+#define WM8994_AUTO_INC 0x0004 /* AUTO_INC */
+#define WM8994_AUTO_INC_MASK 0x0004 /* AUTO_INC */
+#define WM8994_AUTO_INC_SHIFT 2 /* AUTO_INC */
+#define WM8994_AUTO_INC_WIDTH 1 /* AUTO_INC */
+
+/*
+ * R272 (0x110) - Write Sequencer Ctrl (1)
+ */
+#define WM8994_WSEQ_ENA 0x8000 /* WSEQ_ENA */
+#define WM8994_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
+#define WM8994_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
+#define WM8994_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
+#define WM8994_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
+#define WM8994_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
+#define WM8994_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
+#define WM8994_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
+#define WM8994_WSEQ_START 0x0100 /* WSEQ_START */
+#define WM8994_WSEQ_START_MASK 0x0100 /* WSEQ_START */
+#define WM8994_WSEQ_START_SHIFT 8 /* WSEQ_START */
+#define WM8994_WSEQ_START_WIDTH 1 /* WSEQ_START */
+#define WM8994_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
+#define WM8994_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
+#define WM8994_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
+
+/*
+ * R273 (0x111) - Write Sequencer Ctrl (2)
+ */
+#define WM8994_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
+#define WM8994_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
+#define WM8994_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
+#define WM8994_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
+#define WM8994_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8994_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
+#define WM8994_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
+
+/*
+ * R512 (0x200) - AIF1 Clocking (1)
+ */
+#define WM8994_AIF1CLK_SRC_FLL1 0x0010
+#define WM8994_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */
+#define WM8994_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */
+#define WM8994_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */
+#define WM8994_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */
+#define WM8994_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */
+#define WM8994_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */
+#define WM8994_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */
+#define WM8994_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */
+
+/*
+ * R513 (0x201) - AIF1 Clocking (2)
+ */
+#define WM8994_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */
+#define WM8994_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */
+#define WM8994_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */
+#define WM8994_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */
+#define WM8994_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */
+#define WM8994_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */
+
+/*
+ * R516 (0x204) - AIF2 Clocking (1)
+ */
+#define WM8994_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */
+#define WM8994_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */
+#define WM8994_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */
+#define WM8994_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */
+#define WM8994_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */
+#define WM8994_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */
+#define WM8994_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */
+#define WM8994_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */
+#define WM8994_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */
+
+/*
+ * R517 (0x205) - AIF2 Clocking (2)
+ */
+#define WM8994_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */
+#define WM8994_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */
+#define WM8994_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */
+#define WM8994_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */
+#define WM8994_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */
+#define WM8994_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */
+
+/*
+ * R520 (0x208) - Clocking (1)
+ */
+#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */
+#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
+#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
+#define WM8994_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
+#define WM8994_DSP_FS1CLK_ENA 0x0008 /* DSP_FS1CLK_ENA */
+#define WM8994_DSP_FS1CLK_ENA_MASK 0x0008 /* DSP_FS1CLK_ENA */
+#define WM8994_DSP_FS1CLK_ENA_SHIFT 3 /* DSP_FS1CLK_ENA */
+#define WM8994_DSP_FS1CLK_ENA_WIDTH 1 /* DSP_FS1CLK_ENA */
+#define WM8994_DSP_FS2CLK_ENA 0x0004 /* DSP_FS2CLK_ENA */
+#define WM8994_DSP_FS2CLK_ENA_MASK 0x0004 /* DSP_FS2CLK_ENA */
+#define WM8994_DSP_FS2CLK_ENA_SHIFT 2 /* DSP_FS2CLK_ENA */
+#define WM8994_DSP_FS2CLK_ENA_WIDTH 1 /* DSP_FS2CLK_ENA */
+#define WM8994_DSP_FSINTCLK_ENA 0x0002 /* DSP_FSINTCLK_ENA */
+#define WM8994_DSP_FSINTCLK_ENA_MASK 0x0002 /* DSP_FSINTCLK_ENA */
+#define WM8994_DSP_FSINTCLK_ENA_SHIFT 1 /* DSP_FSINTCLK_ENA */
+#define WM8994_DSP_FSINTCLK_ENA_WIDTH 1 /* DSP_FSINTCLK_ENA */
+#define WM8994_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */
+#define WM8994_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */
+#define WM8994_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */
+#define WM8994_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
+
+/*
+ * R521 (0x209) - Clocking (2)
+ */
+#define WM8994_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
+#define WM8994_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
+#define WM8994_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
+#define WM8994_DBCLK_DIV_MASK 0x0070 /* DBCLK_DIV - [6:4] */
+#define WM8994_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [6:4] */
+#define WM8994_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [6:4] */
+#define WM8994_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
+#define WM8994_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
+#define WM8994_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
+
+/*
+ * R528 (0x210) - AIF1 Rate
+ */
+#define WM8994_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */
+#define WM8994_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */
+#define WM8994_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */
+#define WM8994_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */
+#define WM8994_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */
+#define WM8994_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */
+
+/*
+ * R529 (0x211) - AIF2 Rate
+ */
+#define WM8994_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */
+#define WM8994_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */
+#define WM8994_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */
+#define WM8994_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */
+#define WM8994_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */
+#define WM8994_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */
+
+/*
+ * R530 (0x212) - Rate Status
+ */
+#define WM8994_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */
+#define WM8994_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */
+#define WM8994_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */
+
+/*
+ * R544 (0x220) - FLL1 Control (1)
+ */
+#define WM8994_FLL1_FRACN_ENA 0x0004 /* FLL1_FRACN_ENA */
+#define WM8994_FLL1_FRACN_ENA_MASK 0x0004 /* FLL1_FRACN_ENA */
+#define WM8994_FLL1_FRACN_ENA_SHIFT 2 /* FLL1_FRACN_ENA */
+#define WM8994_FLL1_FRACN_ENA_WIDTH 1 /* FLL1_FRACN_ENA */
+#define WM8994_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */
+#define WM8994_FLL1_ENA 0x0001 /* FLL1_ENA */
+#define WM8994_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
+#define WM8994_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
+#define WM8994_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
+
+/*
+ * R545 (0x221) - FLL1 Control (2)
+ */
+#define WM8994_FLL1_OUTDIV_8 0x0700
+#define WM8994_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
+#define WM8994_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
+#define WM8994_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
+#define WM8994_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */
+#define WM8994_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */
+#define WM8994_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */
+#define WM8994_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
+#define WM8994_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
+#define WM8994_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
+
+/*
+ * R546 (0x222) - FLL1 Control (3)
+ */
+#define WM8994_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */
+#define WM8994_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */
+#define WM8994_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */
+
+/*
+ * R547 (0x223) - FLL1 Control (4)
+ */
+#define WM8994_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */
+#define WM8994_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */
+#define WM8994_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */
+#define WM8994_FLL1_GAIN_MASK 0x000F /* FLL1_GAIN - [3:0] */
+#define WM8994_FLL1_GAIN_SHIFT 0 /* FLL1_GAIN - [3:0] */
+#define WM8994_FLL1_GAIN_WIDTH 4 /* FLL1_GAIN - [3:0] */
+
+/*
+ * R548 (0x224) - FLL1 Control (5)
+ */
+#define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */
+#define WM8994_FLL1_CLK_REF_DIV_MASK 0x0018 /* FLL1_CLK_REF_DIV - [4:3] */
+#define WM8994_FLL1_CLK_REF_DIV_SHIFT 3 /* FLL1_CLK_REF_DIV - [4:3] */
+#define WM8994_FLL1_CLK_REF_DIV_WIDTH 2 /* FLL1_CLK_REF_DIV - [4:3] */
+#define WM8994_FLL1_CLK_REF_SRC_MASK 0x0003 /* FLL1_CLK_REF_SRC - [1:0] */
+#define WM8994_FLL1_CLK_REF_SRC_SHIFT 0 /* FLL1_CLK_REF_SRC - [1:0] */
+#define WM8994_FLL1_CLK_REF_SRC_WIDTH 2 /* FLL1_CLK_REF_SRC - [1:0] */
+
+/*
+ * R576 (0x240) - FLL2 Control (1)
+ */
+#define WM8994_FLL2_FRACN_ENA 0x0004 /* FLL2_FRACN_ENA */
+#define WM8994_FLL2_FRACN_ENA_MASK 0x0004 /* FLL2_FRACN_ENA */
+#define WM8994_FLL2_FRACN_ENA_SHIFT 2 /* FLL2_FRACN_ENA */
+#define WM8994_FLL2_FRACN_ENA_WIDTH 1 /* FLL2_FRACN_ENA */
+#define WM8994_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */
+#define WM8994_FLL2_ENA 0x0001 /* FLL2_ENA */
+#define WM8994_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
+#define WM8994_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
+#define WM8994_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
+
+/*
+ * R577 (0x241) - FLL2 Control (2)
+ */
+#define WM8994_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
+#define WM8994_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
+#define WM8994_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
+#define WM8994_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */
+#define WM8994_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */
+#define WM8994_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */
+#define WM8994_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
+#define WM8994_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
+#define WM8994_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
+
+/*
+ * R578 (0x242) - FLL2 Control (3)
+ */
+#define WM8994_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */
+#define WM8994_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */
+#define WM8994_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */
+
+/*
+ * R579 (0x243) - FLL2 Control (4)
+ */
+#define WM8994_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */
+#define WM8994_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */
+#define WM8994_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */
+#define WM8994_FLL2_GAIN_MASK 0x000F /* FLL2_GAIN - [3:0] */
+#define WM8994_FLL2_GAIN_SHIFT 0 /* FLL2_GAIN - [3:0] */
+#define WM8994_FLL2_GAIN_WIDTH 4 /* FLL2_GAIN - [3:0] */
+
+/*
+ * R580 (0x244) - FLL2 Control (5)
+ */
+#define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
+#define WM8994_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */
+#define WM8994_FLL2_CLK_REF_DIV_MASK 0x0018 /* FLL2_CLK_REF_DIV - [4:3] */
+#define WM8994_FLL2_CLK_REF_DIV_SHIFT 3 /* FLL2_CLK_REF_DIV - [4:3] */
+#define WM8994_FLL2_CLK_REF_DIV_WIDTH 2 /* FLL2_CLK_REF_DIV - [4:3] */
+#define WM8994_FLL2_CLK_REF_SRC_MASK 0x0003 /* FLL2_CLK_REF_SRC - [1:0] */
+#define WM8994_FLL2_CLK_REF_SRC_SHIFT 0 /* FLL2_CLK_REF_SRC - [1:0] */
+#define WM8994_FLL2_CLK_REF_SRC_WIDTH 2 /* FLL2_CLK_REF_SRC - [1:0] */
+
+/*
+ * R768 (0x300) - AIF1 Control (1)
+ */
+#define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */
+#define WM8994_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */
+#define WM8994_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */
+#define WM8994_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */
+#define WM8994_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */
+#define WM8994_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */
+#define WM8994_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
+#define WM8994_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
+#define WM8994_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */
+#define WM8994_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */
+#define WM8994_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */
+#define WM8994_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */
+#define WM8994_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */
+#define WM8994_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */
+
+/*
+ * R769 (0x301) - AIF1 Control (2)
+ */
+#define WM8994_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */
+#define WM8994_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */
+#define WM8994_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */
+#define WM8994_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */
+#define WM8994_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */
+#define WM8994_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */
+#define WM8994_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */
+#define WM8994_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */
+#define WM8994_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */
+#define WM8994_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */
+#define WM8994_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */
+#define WM8994_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */
+#define WM8994_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */
+#define WM8994_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */
+#define WM8994_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */
+#define WM8994_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */
+
+/*
+ * R770 (0x302) - AIF1 Master/Slave
+ */
+#define WM8994_AIF1_TRI 0x8000 /* AIF1_TRI */
+#define WM8994_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */
+#define WM8994_AIF1_TRI_SHIFT 15 /* AIF1_TRI */
+#define WM8994_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
+#define WM8994_AIF1_MSTR 0x4000 /* AIF1_MSTR */
+#define WM8994_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */
+#define WM8994_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */
+#define WM8994_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */
+#define WM8994_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */
+#define WM8994_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */
+
+/*
+ * R771 (0x303) - AIF1 BCLK
+ */
+#define WM8994_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */
+#define WM8994_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */
+#define WM8994_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */
+
+/*
+ * R772 (0x304) - AIF1ADC LRCLK
+ */
+#define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */
+#define WM8994_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */
+#define WM8994_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */
+#define WM8994_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */
+
+/*
+ * R773 (0x305) - AIF1DAC LRCLK
+ */
+#define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */
+#define WM8994_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */
+#define WM8994_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */
+#define WM8994_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */
+
+/*
+ * R774 (0x306) - AIF1DAC Data
+ */
+#define WM8994_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */
+#define WM8994_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */
+
+/*
+ * R775 (0x307) - AIF1ADC Data
+ */
+#define WM8994_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */
+#define WM8994_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */
+
+/*
+ * R784 (0x310) - AIF2 Control (1)
+ */
+#define WM8994_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */
+#define WM8994_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */
+#define WM8994_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */
+#define WM8994_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */
+#define WM8994_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
+#define WM8994_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */
+#define WM8994_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */
+#define WM8994_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */
+#define WM8994_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */
+#define WM8994_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */
+#define WM8994_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */
+#define WM8994_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */
+
+/*
+ * R785 (0x311) - AIF2 Control (2)
+ */
+#define WM8994_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */
+#define WM8994_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */
+#define WM8994_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */
+#define WM8994_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */
+#define WM8994_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */
+#define WM8994_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */
+#define WM8994_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */
+#define WM8994_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */
+#define WM8994_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */
+#define WM8994_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */
+#define WM8994_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */
+#define WM8994_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */
+#define WM8994_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */
+#define WM8994_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */
+#define WM8994_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */
+#define WM8994_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */
+#define WM8994_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */
+#define WM8994_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */
+
+/*
+ * R786 (0x312) - AIF2 Master/Slave
+ */
+#define WM8994_AIF2_TRI 0x8000 /* AIF2_TRI */
+#define WM8994_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */
+#define WM8994_AIF2_TRI_SHIFT 15 /* AIF2_TRI */
+#define WM8994_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
+#define WM8994_AIF2_MSTR 0x4000 /* AIF2_MSTR */
+#define WM8994_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */
+#define WM8994_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */
+#define WM8994_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */
+#define WM8994_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */
+#define WM8994_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */
+
+/*
+ * R787 (0x313) - AIF2 BCLK
+ */
+#define WM8994_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */
+#define WM8994_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */
+#define WM8994_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */
+
+/*
+ * R788 (0x314) - AIF2ADC LRCLK
+ */
+#define WM8994_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */
+#define WM8994_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */
+#define WM8994_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */
+#define WM8994_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */
+
+/*
+ * R789 (0x315) - AIF2DAC LRCLK
+ */
+#define WM8994_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */
+#define WM8994_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */
+#define WM8994_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */
+#define WM8994_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */
+
+/*
+ * R790 (0x316) - AIF2DAC Data
+ */
+#define WM8994_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */
+#define WM8994_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */
+
+/*
+ * R791 (0x317) - AIF2ADC Data
+ */
+#define WM8994_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */
+#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
+
+/*
+ * R1024 (0x400) - AIF1 ADC1 Left Volume
+ */
+#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */
+#define WM8994_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */
+#define WM8994_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */
+
+/*
+ * R1025 (0x401) - AIF1 ADC1 Right Volume
+ */
+#define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
+#define WM8994_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */
+#define WM8994_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */
+#define WM8994_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */
+
+/*
+ * R1026 (0x402) - AIF1 DAC1 Left Volume
+ */
+#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */
+#define WM8994_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */
+#define WM8994_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */
+
+/*
+ * R1027 (0x403) - AIF1 DAC1 Right Volume
+ */
+#define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
+#define WM8994_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */
+#define WM8994_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */
+#define WM8994_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */
+
+/*
+ * R1028 (0x404) - AIF1 ADC2 Left Volume
+ */
+#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */
+#define WM8994_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */
+#define WM8994_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */
+
+/*
+ * R1029 (0x405) - AIF1 ADC2 Right Volume
+ */
+#define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
+#define WM8994_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */
+#define WM8994_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */
+#define WM8994_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */
+
+/*
+ * R1030 (0x406) - AIF1 DAC2 Left Volume
+ */
+#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */
+#define WM8994_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */
+#define WM8994_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */
+
+/*
+ * R1031 (0x407) - AIF1 DAC2 Right Volume
+ */
+#define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
+#define WM8994_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */
+#define WM8994_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */
+#define WM8994_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */
+
+/*
+ * R1040 (0x410) - AIF1 ADC1 Filters
+ */
+#define WM8994_AIF1ADC1_HPF_CUT_MASK 0x6000 /* AIF1ADC1_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC1_HPF_CUT_SHIFT 13 /* AIF1ADC1_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC1_HPF_CUT_WIDTH 2 /* AIF1ADC1_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */
+#define WM8994_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */
+#define WM8994_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */
+#define WM8994_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */
+#define WM8994_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */
+
+/*
+ * R1041 (0x411) - AIF1 ADC2 Filters
+ */
+#define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */
+#define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
+#define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */
+#define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */
+#define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */
+#define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
+
+/*
+ * R1056 (0x420) - AIF1 DAC1 Filters (1)
+ */
+ #define WM8994_AIF1DAC1_UNMUTE 0x0000 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */
+#define WM8994_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */
+#define WM8994_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */
+#define WM8994_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */
+#define WM8994_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */
+#define WM8994_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */
+
+/*
+ * R1057 (0x421) - AIF1 DAC1 Filters (2)
+ */
+#define WM8994_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */
+#define WM8994_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */
+#define WM8994_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */
+#define WM8994_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */
+
+/*
+ * R1058 (0x422) - AIF1 DAC2 Filters (1)
+ */
+ #define WM8994_AIF1DAC2_UNMUTE 0x0000 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */
+#define WM8994_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */
+#define WM8994_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */
+#define WM8994_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */
+#define WM8994_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */
+#define WM8994_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */
+
+/*
+ * R1059 (0x423) - AIF1 DAC2 Filters (2)
+ */
+#define WM8994_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */
+#define WM8994_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */
+#define WM8994_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */
+#define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */
+#define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
+
+/*
+ * R1088 (0x440) - AIF1 DRC1 (1)
+ */
+#define WM8994_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */
+#define WM8994_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */
+#define WM8994_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */
+#define WM8994_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */
+#define WM8994_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */
+#define WM8994_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */
+
+/*
+ * R1089 (0x441) - AIF1 DRC1 (2)
+ */
+#define WM8994_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */
+#define WM8994_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */
+#define WM8994_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */
+#define WM8994_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */
+#define WM8994_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */
+#define WM8994_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */
+#define WM8994_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */
+
+/*
+ * R1090 (0x442) - AIF1 DRC1 (3)
+ */
+#define WM8994_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8994_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8994_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */
+#define WM8994_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */
+
+/*
+ * R1091 (0x443) - AIF1 DRC1 (4)
+ */
+#define WM8994_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */
+
+/*
+ * R1092 (0x444) - AIF1 DRC1 (5)
+ */
+#define WM8994_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */
+
+/*
+ * R1104 (0x450) - AIF1 DRC2 (1)
+ */
+#define WM8994_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */
+#define WM8994_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */
+#define WM8994_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */
+#define WM8994_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */
+#define WM8994_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */
+#define WM8994_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */
+#define WM8994_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */
+#define WM8994_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */
+
+/*
+ * R1105 (0x451) - AIF1 DRC2 (2)
+ */
+#define WM8994_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */
+#define WM8994_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */
+#define WM8994_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */
+#define WM8994_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */
+#define WM8994_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */
+#define WM8994_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */
+#define WM8994_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */
+#define WM8994_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */
+#define WM8994_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */
+
+/*
+ * R1106 (0x452) - AIF1 DRC2 (3)
+ */
+#define WM8994_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */
+#define WM8994_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */
+#define WM8994_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8994_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8994_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */
+#define WM8994_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */
+#define WM8994_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */
+#define WM8994_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */
+#define WM8994_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */
+
+/*
+ * R1107 (0x453) - AIF1 DRC2 (4)
+ */
+#define WM8994_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */
+#define WM8994_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */
+
+/*
+ * R1108 (0x454) - AIF1 DRC2 (5)
+ */
+#define WM8994_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
+#define WM8994_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */
+#define WM8994_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */
+
+/*
+ * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
+ */
+#define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */
+#define WM8994_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */
+#define WM8994_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */
+#define WM8994_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */
+
+/*
+ * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
+ */
+#define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
+ */
+#define WM8994_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */
+
+/*
+ * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
+ */
+#define WM8994_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */
+
+/*
+ * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */
+
+/*
+ * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
+ */
+#define WM8994_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */
+
+/*
+ * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
+ */
+#define WM8994_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */
+
+/*
+ * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
+ */
+#define WM8994_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */
+
+/*
+ * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */
+
+/*
+ * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
+ */
+#define WM8994_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */
+
+/*
+ * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
+ */
+#define WM8994_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */
+
+/*
+ * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
+ */
+#define WM8994_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */
+
+/*
+ * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */
+
+/*
+ * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
+ */
+#define WM8994_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */
+
+/*
+ * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
+ */
+#define WM8994_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */
+
+/*
+ * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
+ */
+#define WM8994_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */
+
+/*
+ * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */
+
+/*
+ * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
+ */
+#define WM8994_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */
+
+/*
+ * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
+ */
+#define WM8994_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */
+
+/*
+ * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
+ */
+#define WM8994_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */
+
+/*
+ * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
+ */
+#define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */
+#define WM8994_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */
+#define WM8994_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */
+#define WM8994_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */
+
+/*
+ * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
+ */
+#define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
+ */
+#define WM8994_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */
+
+/*
+ * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
+ */
+#define WM8994_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */
+
+/*
+ * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */
+
+/*
+ * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
+ */
+#define WM8994_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */
+
+/*
+ * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
+ */
+#define WM8994_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */
+
+/*
+ * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
+ */
+#define WM8994_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */
+
+/*
+ * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */
+
+/*
+ * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
+ */
+#define WM8994_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */
+
+/*
+ * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
+ */
+#define WM8994_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */
+
+/*
+ * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
+ */
+#define WM8994_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */
+
+/*
+ * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */
+
+/*
+ * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
+ */
+#define WM8994_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */
+
+/*
+ * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
+ */
+#define WM8994_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */
+
+/*
+ * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
+ */
+#define WM8994_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */
+
+/*
+ * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */
+
+/*
+ * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
+ */
+#define WM8994_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */
+
+/*
+ * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
+ */
+#define WM8994_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */
+
+/*
+ * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
+ */
+#define WM8994_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */
+#define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */
+
+/*
+ * R1280 (0x500) - AIF2 ADC Left Volume
+ */
+#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
+#define WM8994_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */
+#define WM8994_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */
+#define WM8994_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */
+
+/*
+ * R1281 (0x501) - AIF2 ADC Right Volume
+ */
+#define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
+#define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
+#define WM8994_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */
+#define WM8994_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */
+#define WM8994_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */
+
+/*
+ * R1282 (0x502) - AIF2 DAC Left Volume
+ */
+#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
+#define WM8994_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */
+#define WM8994_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */
+#define WM8994_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */
+
+/*
+ * R1283 (0x503) - AIF2 DAC Right Volume
+ */
+#define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
+#define WM8994_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */
+#define WM8994_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */
+#define WM8994_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */
+
+/*
+ * R1296 (0x510) - AIF2 ADC Filters
+ */
+#define WM8994_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */
+#define WM8994_AIF2ADC_HPF_CUT_MASK 0x6000 /* AIF2ADC_HPF_CUT - [14:13] */
+#define WM8994_AIF2ADC_HPF_CUT_SHIFT 13 /* AIF2ADC_HPF_CUT - [14:13] */
+#define WM8994_AIF2ADC_HPF_CUT_WIDTH 2 /* AIF2ADC_HPF_CUT - [14:13] */
+#define WM8994_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */
+#define WM8994_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */
+#define WM8994_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */
+#define WM8994_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */
+#define WM8994_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */
+
+/*
+ * R1312 (0x520) - AIF2 DAC Filters (1)
+ */
+#define WM8994_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */
+#define WM8994_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */
+#define WM8994_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */
+#define WM8994_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */
+#define WM8994_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */
+#define WM8994_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */
+
+/*
+ * R1313 (0x521) - AIF2 DAC Filters (2)
+ */
+#define WM8994_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8994_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8994_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */
+#define WM8994_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */
+#define WM8994_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */
+#define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */
+#define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
+
+/*
+ * R1344 (0x540) - AIF2 DRC (1)
+ */
+#define WM8994_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */
+#define WM8994_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8994_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8994_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */
+#define WM8994_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */
+#define WM8994_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */
+#define WM8994_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */
+#define WM8994_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */
+#define WM8994_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */
+#define WM8994_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */
+#define WM8994_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */
+
+/*
+ * R1345 (0x541) - AIF2 DRC (2)
+ */
+#define WM8994_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */
+#define WM8994_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */
+#define WM8994_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */
+#define WM8994_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */
+#define WM8994_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */
+#define WM8994_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */
+#define WM8994_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8994_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8994_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */
+#define WM8994_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */
+#define WM8994_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */
+#define WM8994_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */
+
+/*
+ * R1346 (0x542) - AIF2 DRC (3)
+ */
+#define WM8994_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8994_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8994_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */
+#define WM8994_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8994_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8994_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */
+#define WM8994_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */
+#define WM8994_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */
+#define WM8994_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */
+#define WM8994_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8994_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8994_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */
+#define WM8994_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8994_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8994_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */
+#define WM8994_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */
+#define WM8994_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */
+#define WM8994_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */
+
+/*
+ * R1347 (0x543) - AIF2 DRC (4)
+ */
+#define WM8994_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8994_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8994_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */
+#define WM8994_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */
+
+/*
+ * R1348 (0x544) - AIF2 DRC (5)
+ */
+#define WM8994_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8994_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8994_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */
+#define WM8994_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */
+#define WM8994_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */
+
+/*
+ * R1408 (0x580) - AIF2 EQ Gains (1)
+ */
+#define WM8994_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
+#define WM8994_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */
+#define WM8994_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */
+#define WM8994_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */
+#define WM8994_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */
+
+/*
+ * R1409 (0x581) - AIF2 EQ Gains (2)
+ */
+#define WM8994_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
+#define WM8994_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+#define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
+
+/*
+ * R1410 (0x582) - AIF2 EQ Band 1 A
+ */
+#define WM8994_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */
+
+/*
+ * R1411 (0x583) - AIF2 EQ Band 1 B
+ */
+#define WM8994_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */
+
+/*
+ * R1412 (0x584) - AIF2 EQ Band 1 PG
+ */
+#define WM8994_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */
+
+/*
+ * R1413 (0x585) - AIF2 EQ Band 2 A
+ */
+#define WM8994_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */
+
+/*
+ * R1414 (0x586) - AIF2 EQ Band 2 B
+ */
+#define WM8994_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */
+
+/*
+ * R1415 (0x587) - AIF2 EQ Band 2 C
+ */
+#define WM8994_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */
+
+/*
+ * R1416 (0x588) - AIF2 EQ Band 2 PG
+ */
+#define WM8994_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */
+
+/*
+ * R1417 (0x589) - AIF2 EQ Band 3 A
+ */
+#define WM8994_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */
+
+/*
+ * R1418 (0x58A) - AIF2 EQ Band 3 B
+ */
+#define WM8994_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */
+
+/*
+ * R1419 (0x58B) - AIF2 EQ Band 3 C
+ */
+#define WM8994_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */
+
+/*
+ * R1420 (0x58C) - AIF2 EQ Band 3 PG
+ */
+#define WM8994_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */
+
+/*
+ * R1421 (0x58D) - AIF2 EQ Band 4 A
+ */
+#define WM8994_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */
+
+/*
+ * R1422 (0x58E) - AIF2 EQ Band 4 B
+ */
+#define WM8994_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */
+
+/*
+ * R1423 (0x58F) - AIF2 EQ Band 4 C
+ */
+#define WM8994_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */
+
+/*
+ * R1424 (0x590) - AIF2 EQ Band 4 PG
+ */
+#define WM8994_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */
+
+/*
+ * R1425 (0x591) - AIF2 EQ Band 5 A
+ */
+#define WM8994_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */
+
+/*
+ * R1426 (0x592) - AIF2 EQ Band 5 B
+ */
+#define WM8994_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */
+
+/*
+ * R1427 (0x593) - AIF2 EQ Band 5 PG
+ */
+#define WM8994_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */
+#define WM8994_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */
+
+/*
+ * R1536 (0x600) - DAC1 Mixer Volumes
+ */
+#define WM8994_ADC2_DAC1_VOL_MASK 0x01E0 /* ADC2_DAC1_VOL - [8:5] */
+#define WM8994_ADC2_DAC1_VOL_SHIFT 5 /* ADC2_DAC1_VOL - [8:5] */
+#define WM8994_ADC2_DAC1_VOL_WIDTH 4 /* ADC2_DAC1_VOL - [8:5] */
+#define WM8994_ADC1_DAC1_VOL_MASK 0x000F /* ADC1_DAC1_VOL - [3:0] */
+#define WM8994_ADC1_DAC1_VOL_SHIFT 0 /* ADC1_DAC1_VOL - [3:0] */
+#define WM8994_ADC1_DAC1_VOL_WIDTH 4 /* ADC1_DAC1_VOL - [3:0] */
+
+/*
+ * R1537 (0x601) - DAC1 Left Mixer Routing
+ */
+#define WM8994_ADC2_TO_DAC1L 0x0020 /* ADC2_TO_DAC1L */
+#define WM8994_ADC2_TO_DAC1L_MASK 0x0020 /* ADC2_TO_DAC1L */
+#define WM8994_ADC2_TO_DAC1L_SHIFT 5 /* ADC2_TO_DAC1L */
+#define WM8994_ADC2_TO_DAC1L_WIDTH 1 /* ADC2_TO_DAC1L */
+#define WM8994_ADC1_TO_DAC1L 0x0010 /* ADC1_TO_DAC1L */
+#define WM8994_ADC1_TO_DAC1L_MASK 0x0010 /* ADC1_TO_DAC1L */
+#define WM8994_ADC1_TO_DAC1L_SHIFT 4 /* ADC1_TO_DAC1L */
+#define WM8994_ADC1_TO_DAC1L_WIDTH 1 /* ADC1_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */
+#define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */
+
+/*
+ * R1538 (0x602) - DAC1 Right Mixer Routing
+ */
+#define WM8994_ADC2_TO_DAC1R 0x0020 /* ADC2_TO_DAC1R */
+#define WM8994_ADC2_TO_DAC1R_MASK 0x0020 /* ADC2_TO_DAC1R */
+#define WM8994_ADC2_TO_DAC1R_SHIFT 5 /* ADC2_TO_DAC1R */
+#define WM8994_ADC2_TO_DAC1R_WIDTH 1 /* ADC2_TO_DAC1R */
+#define WM8994_ADC1_TO_DAC1R 0x0010 /* ADC1_TO_DAC1R */
+#define WM8994_ADC1_TO_DAC1R_MASK 0x0010 /* ADC1_TO_DAC1R */
+#define WM8994_ADC1_TO_DAC1R_SHIFT 4 /* ADC1_TO_DAC1R */
+#define WM8994_ADC1_TO_DAC1R_WIDTH 1 /* ADC1_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */
+#define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */
+
+/*
+ * R1539 (0x603) - DAC2 Mixer Volumes
+ */
+#define WM8994_ADC2_DAC2_VOL_MASK 0x01E0 /* ADC2_DAC2_VOL - [8:5] */
+#define WM8994_ADC2_DAC2_VOL_SHIFT 5 /* ADC2_DAC2_VOL - [8:5] */
+#define WM8994_ADC2_DAC2_VOL_WIDTH 4 /* ADC2_DAC2_VOL - [8:5] */
+#define WM8994_ADC1_DAC2_VOL_MASK 0x000F /* ADC1_DAC2_VOL - [3:0] */
+#define WM8994_ADC1_DAC2_VOL_SHIFT 0 /* ADC1_DAC2_VOL - [3:0] */
+#define WM8994_ADC1_DAC2_VOL_WIDTH 4 /* ADC1_DAC2_VOL - [3:0] */
+
+/*
+ * R1540 (0x604) - DAC2 Left Mixer Routing
+ */
+#define WM8994_ADC2_TO_DAC2L 0x0020 /* ADC2_TO_DAC2L */
+#define WM8994_ADC2_TO_DAC2L_MASK 0x0020 /* ADC2_TO_DAC2L */
+#define WM8994_ADC2_TO_DAC2L_SHIFT 5 /* ADC2_TO_DAC2L */
+#define WM8994_ADC2_TO_DAC2L_WIDTH 1 /* ADC2_TO_DAC2L */
+#define WM8994_ADC1_TO_DAC2L 0x0010 /* ADC1_TO_DAC2L */
+#define WM8994_ADC1_TO_DAC2L_MASK 0x0010 /* ADC1_TO_DAC2L */
+#define WM8994_ADC1_TO_DAC2L_SHIFT 4 /* ADC1_TO_DAC2L */
+#define WM8994_ADC1_TO_DAC2L_WIDTH 1 /* ADC1_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */
+#define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */
+
+/*
+ * R1541 (0x605) - DAC2 Right Mixer Routing
+ */
+#define WM8994_ADC2_TO_DAC2R 0x0020 /* ADC2_TO_DAC2R */
+#define WM8994_ADC2_TO_DAC2R_MASK 0x0020 /* ADC2_TO_DAC2R */
+#define WM8994_ADC2_TO_DAC2R_SHIFT 5 /* ADC2_TO_DAC2R */
+#define WM8994_ADC2_TO_DAC2R_WIDTH 1 /* ADC2_TO_DAC2R */
+#define WM8994_ADC1_TO_DAC2R 0x0010 /* ADC1_TO_DAC2R */
+#define WM8994_ADC1_TO_DAC2R_MASK 0x0010 /* ADC1_TO_DAC2R */
+#define WM8994_ADC1_TO_DAC2R_SHIFT 4 /* ADC1_TO_DAC2R */
+#define WM8994_ADC1_TO_DAC2R_WIDTH 1 /* ADC1_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */
+#define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */
+
+/*
+ * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
+ */
+#define WM8994_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */
+#define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */
+
+/*
+ * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
+ */
+#define WM8994_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */
+#define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */
+
+/*
+ * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
+ */
+#define WM8994_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */
+#define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */
+
+/*
+ * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
+ */
+#define WM8994_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */
+#define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */
+
+/*
+ * R1552 (0x610) - DAC1 Left Volume
+ */
+#define WM8994_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
+#define WM8994_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
+#define WM8994_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
+#define WM8994_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
+#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */
+#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */
+#define WM8994_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
+#define WM8994_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
+#define WM8994_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
+
+/*
+ * R1553 (0x611) - DAC1 Right Volume
+ */
+#define WM8994_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
+#define WM8994_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
+#define WM8994_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
+#define WM8994_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
+#define WM8994_DAC1_VU 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */
+#define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */
+#define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */
+#define WM8994_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
+#define WM8994_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
+#define WM8994_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
+
+/*
+ * R1554 (0x612) - DAC2 Left Volume
+ */
+#define WM8994_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
+#define WM8994_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
+#define WM8994_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
+#define WM8994_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
+#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */
+#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */
+#define WM8994_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
+#define WM8994_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
+#define WM8994_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
+
+/*
+ * R1555 (0x613) - DAC2 Right Volume
+ */
+#define WM8994_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
+#define WM8994_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
+#define WM8994_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
+#define WM8994_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
+#define WM8994_DAC2_VU 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */
+#define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */
+#define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */
+#define WM8994_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
+#define WM8994_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
+#define WM8994_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
+
+/*
+ * R1556 (0x614) - DAC Softmute
+ */
+#define WM8994_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
+#define WM8994_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
+#define WM8994_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
+#define WM8994_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
+#define WM8994_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
+
+/*
+ * R1568 (0x620) - Oversampling
+ */
+#define WM8994_ADC_OSR128 0x0002 /* ADC_OSR128 */
+#define WM8994_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
+#define WM8994_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
+#define WM8994_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
+#define WM8994_DAC_OSR128 0x0001 /* DAC_OSR128 */
+#define WM8994_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
+#define WM8994_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
+#define WM8994_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
+
+/*
+ * R1569 (0x621) - Sidetone
+ */
+#define WM8994_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
+#define WM8994_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
+#define WM8994_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
+#define WM8994_ST_HPF 0x0040 /* ST_HPF */
+#define WM8994_ST_HPF_MASK 0x0040 /* ST_HPF */
+#define WM8994_ST_HPF_SHIFT 6 /* ST_HPF */
+#define WM8994_ST_HPF_WIDTH 1 /* ST_HPF */
+#define WM8994_ST2_SEL 0x0002 /* ST2_SEL */
+#define WM8994_ST2_SEL_MASK 0x0002 /* ST2_SEL */
+#define WM8994_ST2_SEL_SHIFT 1 /* ST2_SEL */
+#define WM8994_ST2_SEL_WIDTH 1 /* ST2_SEL */
+#define WM8994_ST1_SEL 0x0001 /* ST1_SEL */
+#define WM8994_ST1_SEL_MASK 0x0001 /* ST1_SEL */
+#define WM8994_ST1_SEL_SHIFT 0 /* ST1_SEL */
+#define WM8994_ST1_SEL_WIDTH 1 /* ST1_SEL */
+
+/*
+ * R1792 (0x700) - GPIO 1
+ */
+#define WM8994_GP1_DIR 0x8000 /* GP1_DIR */
+#define WM8994_GP1_DIR_MASK 0x8000 /* GP1_DIR */
+#define WM8994_GP1_DIR_SHIFT 15 /* GP1_DIR */
+#define WM8994_GP1_DIR_WIDTH 1 /* GP1_DIR */
+#define WM8994_GP1_PU 0x4000 /* GP1_PU */
+#define WM8994_GP1_PU_MASK 0x4000 /* GP1_PU */
+#define WM8994_GP1_PU_SHIFT 14 /* GP1_PU */
+#define WM8994_GP1_PU_WIDTH 1 /* GP1_PU */
+#define WM8994_GP1_PD 0x2000 /* GP1_PD */
+#define WM8994_GP1_PD_MASK 0x2000 /* GP1_PD */
+#define WM8994_GP1_PD_SHIFT 13 /* GP1_PD */
+#define WM8994_GP1_PD_WIDTH 1 /* GP1_PD */
+#define WM8994_GP1_POL 0x0400 /* GP1_POL */
+#define WM8994_GP1_POL_MASK 0x0400 /* GP1_POL */
+#define WM8994_GP1_POL_SHIFT 10 /* GP1_POL */
+#define WM8994_GP1_POL_WIDTH 1 /* GP1_POL */
+#define WM8994_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
+#define WM8994_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
+#define WM8994_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
+#define WM8994_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
+#define WM8994_GP1_DB 0x0100 /* GP1_DB */
+#define WM8994_GP1_DB_MASK 0x0100 /* GP1_DB */
+#define WM8994_GP1_DB_SHIFT 8 /* GP1_DB */
+#define WM8994_GP1_DB_WIDTH 1 /* GP1_DB */
+#define WM8994_GP1_LVL 0x0040 /* GP1_LVL */
+#define WM8994_GP1_LVL_MASK 0x0040 /* GP1_LVL */
+#define WM8994_GP1_LVL_SHIFT 6 /* GP1_LVL */
+#define WM8994_GP1_LVL_WIDTH 1 /* GP1_LVL */
+#define WM8994_GP1_FN_LOGIC_INOUT 0x0001
+#define WM8994_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */
+#define WM8994_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */
+#define WM8994_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */
+
+/*
+ * R1793 (0x701) - GPIO 2
+ */
+#define WM8994_GP2_PU 0x4000 /* GP2_PU */
+#define WM8994_GP2_PU_MASK 0x4000 /* GP2_PU */
+#define WM8994_GP2_PU_SHIFT 14 /* GP2_PU */
+#define WM8994_GP2_PU_WIDTH 1 /* GP2_PU */
+#define WM8994_GP2_PD 0x2000 /* GP2_PD */
+#define WM8994_GP2_PD_MASK 0x2000 /* GP2_PD */
+#define WM8994_GP2_PD_SHIFT 13 /* GP2_PD */
+#define WM8994_GP2_PD_WIDTH 1 /* GP2_PD */
+#define WM8994_GP2_POL 0x0400 /* GP2_POL */
+#define WM8994_GP2_POL_MASK 0x0400 /* GP2_POL */
+#define WM8994_GP2_POL_SHIFT 10 /* GP2_POL */
+#define WM8994_GP2_POL_WIDTH 1 /* GP2_POL */
+#define WM8994_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
+#define WM8994_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
+#define WM8994_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
+#define WM8994_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
+#define WM8994_GP2_LVL 0x0040 /* GP2_LVL */
+#define WM8994_GP2_LVL_MASK 0x0040 /* GP2_LVL */
+#define WM8994_GP2_LVL_SHIFT 6 /* GP2_LVL */
+#define WM8994_GP2_LVL_WIDTH 1 /* GP2_LVL */
+#define WM8994_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */
+#define WM8994_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */
+#define WM8994_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */
+
+/*
+ * R1794 (0x702) - GPIO 3
+ */
+#define WM8994_GP3_DIR 0x8000 /* GP3_DIR */
+#define WM8994_GP3_DIR_MASK 0x8000 /* GP3_DIR */
+#define WM8994_GP3_DIR_SHIFT 15 /* GP3_DIR */
+#define WM8994_GP3_DIR_WIDTH 1 /* GP3_DIR */
+#define WM8994_GP3_PU 0x4000 /* GP3_PU */
+#define WM8994_GP3_PU_MASK 0x4000 /* GP3_PU */
+#define WM8994_GP3_PU_SHIFT 14 /* GP3_PU */
+#define WM8994_GP3_PU_WIDTH 1 /* GP3_PU */
+#define WM8994_GP3_PD 0x2000 /* GP3_PD */
+#define WM8994_GP3_PD_MASK 0x2000 /* GP3_PD */
+#define WM8994_GP3_PD_SHIFT 13 /* GP3_PD */
+#define WM8994_GP3_PD_WIDTH 1 /* GP3_PD */
+#define WM8994_GP3_POL 0x0400 /* GP3_POL */
+#define WM8994_GP3_POL_MASK 0x0400 /* GP3_POL */
+#define WM8994_GP3_POL_SHIFT 10 /* GP3_POL */
+#define WM8994_GP3_POL_WIDTH 1 /* GP3_POL */
+#define WM8994_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
+#define WM8994_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
+#define WM8994_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
+#define WM8994_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
+#define WM8994_GP3_DB 0x0100 /* GP3_DB */
+#define WM8994_GP3_DB_MASK 0x0100 /* GP3_DB */
+#define WM8994_GP3_DB_SHIFT 8 /* GP3_DB */
+#define WM8994_GP3_DB_WIDTH 1 /* GP3_DB */
+#define WM8994_GP3_LVL 0x0040 /* GP3_LVL */
+#define WM8994_GP3_LVL_MASK 0x0040 /* GP3_LVL */
+#define WM8994_GP3_LVL_SHIFT 6 /* GP3_LVL */
+#define WM8994_GP3_LVL_WIDTH 1 /* GP3_LVL */
+#define WM8994_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */
+#define WM8994_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */
+#define WM8994_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */
+
+/*
+ * R1795 (0x703) - GPIO 4
+ */
+#define WM8994_GP4_DIR 0x8000 /* GP4_DIR */
+#define WM8994_GP4_DIR_MASK 0x8000 /* GP4_DIR */
+#define WM8994_GP4_DIR_SHIFT 15 /* GP4_DIR */
+#define WM8994_GP4_DIR_WIDTH 1 /* GP4_DIR */
+#define WM8994_GP4_PU 0x4000 /* GP4_PU */
+#define WM8994_GP4_PU_MASK 0x4000 /* GP4_PU */
+#define WM8994_GP4_PU_SHIFT 14 /* GP4_PU */
+#define WM8994_GP4_PU_WIDTH 1 /* GP4_PU */
+#define WM8994_GP4_PD 0x2000 /* GP4_PD */
+#define WM8994_GP4_PD_MASK 0x2000 /* GP4_PD */
+#define WM8994_GP4_PD_SHIFT 13 /* GP4_PD */
+#define WM8994_GP4_PD_WIDTH 1 /* GP4_PD */
+#define WM8994_GP4_POL 0x0400 /* GP4_POL */
+#define WM8994_GP4_POL_MASK 0x0400 /* GP4_POL */
+#define WM8994_GP4_POL_SHIFT 10 /* GP4_POL */
+#define WM8994_GP4_POL_WIDTH 1 /* GP4_POL */
+#define WM8994_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
+#define WM8994_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
+#define WM8994_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
+#define WM8994_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
+#define WM8994_GP4_DB 0x0100 /* GP4_DB */
+#define WM8994_GP4_DB_MASK 0x0100 /* GP4_DB */
+#define WM8994_GP4_DB_SHIFT 8 /* GP4_DB */
+#define WM8994_GP4_DB_WIDTH 1 /* GP4_DB */
+#define WM8994_GP4_LVL 0x0040 /* GP4_LVL */
+#define WM8994_GP4_LVL_MASK 0x0040 /* GP4_LVL */
+#define WM8994_GP4_LVL_SHIFT 6 /* GP4_LVL */
+#define WM8994_GP4_LVL_WIDTH 1 /* GP4_LVL */
+#define WM8994_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */
+#define WM8994_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */
+#define WM8994_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */
+
+/*
+ * R1796 (0x704) - GPIO 5
+ */
+#define WM8994_GP5_DIR 0x8000 /* GP5_DIR */
+#define WM8994_GP5_DIR_MASK 0x8000 /* GP5_DIR */
+#define WM8994_GP5_DIR_SHIFT 15 /* GP5_DIR */
+#define WM8994_GP5_DIR_WIDTH 1 /* GP5_DIR */
+#define WM8994_GP5_PU 0x4000 /* GP5_PU */
+#define WM8994_GP5_PU_MASK 0x4000 /* GP5_PU */
+#define WM8994_GP5_PU_SHIFT 14 /* GP5_PU */
+#define WM8994_GP5_PU_WIDTH 1 /* GP5_PU */
+#define WM8994_GP5_PD 0x2000 /* GP5_PD */
+#define WM8994_GP5_PD_MASK 0x2000 /* GP5_PD */
+#define WM8994_GP5_PD_SHIFT 13 /* GP5_PD */
+#define WM8994_GP5_PD_WIDTH 1 /* GP5_PD */
+#define WM8994_GP5_POL 0x0400 /* GP5_POL */
+#define WM8994_GP5_POL_MASK 0x0400 /* GP5_POL */
+#define WM8994_GP5_POL_SHIFT 10 /* GP5_POL */
+#define WM8994_GP5_POL_WIDTH 1 /* GP5_POL */
+#define WM8994_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
+#define WM8994_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
+#define WM8994_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
+#define WM8994_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
+#define WM8994_GP5_DB 0x0100 /* GP5_DB */
+#define WM8994_GP5_DB_MASK 0x0100 /* GP5_DB */
+#define WM8994_GP5_DB_SHIFT 8 /* GP5_DB */
+#define WM8994_GP5_DB_WIDTH 1 /* GP5_DB */
+#define WM8994_GP5_LVL 0x0040 /* GP5_LVL */
+#define WM8994_GP5_LVL_MASK 0x0040 /* GP5_LVL */
+#define WM8994_GP5_LVL_SHIFT 6 /* GP5_LVL */
+#define WM8994_GP5_LVL_WIDTH 1 /* GP5_LVL */
+#define WM8994_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */
+#define WM8994_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */
+#define WM8994_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */
+
+/*
+ * R1797 (0x705) - GPIO 6
+ */
+#define WM8994_GP6_DIR 0x8000 /* GP6_DIR */
+#define WM8994_GP6_DIR_MASK 0x8000 /* GP6_DIR */
+#define WM8994_GP6_DIR_SHIFT 15 /* GP6_DIR */
+#define WM8994_GP6_DIR_WIDTH 1 /* GP6_DIR */
+#define WM8994_GP6_PU 0x4000 /* GP6_PU */
+#define WM8994_GP6_PU_MASK 0x4000 /* GP6_PU */
+#define WM8994_GP6_PU_SHIFT 14 /* GP6_PU */
+#define WM8994_GP6_PU_WIDTH 1 /* GP6_PU */
+#define WM8994_GP6_PD 0x2000 /* GP6_PD */
+#define WM8994_GP6_PD_MASK 0x2000 /* GP6_PD */
+#define WM8994_GP6_PD_SHIFT 13 /* GP6_PD */
+#define WM8994_GP6_PD_WIDTH 1 /* GP6_PD */
+#define WM8994_GP6_POL 0x0400 /* GP6_POL */
+#define WM8994_GP6_POL_MASK 0x0400 /* GP6_POL */
+#define WM8994_GP6_POL_SHIFT 10 /* GP6_POL */
+#define WM8994_GP6_POL_WIDTH 1 /* GP6_POL */
+#define WM8994_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */
+#define WM8994_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */
+#define WM8994_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */
+#define WM8994_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
+#define WM8994_GP6_DB 0x0100 /* GP6_DB */
+#define WM8994_GP6_DB_MASK 0x0100 /* GP6_DB */
+#define WM8994_GP6_DB_SHIFT 8 /* GP6_DB */
+#define WM8994_GP6_DB_WIDTH 1 /* GP6_DB */
+#define WM8994_GP6_LVL 0x0040 /* GP6_LVL */
+#define WM8994_GP6_LVL_MASK 0x0040 /* GP6_LVL */
+#define WM8994_GP6_LVL_SHIFT 6 /* GP6_LVL */
+#define WM8994_GP6_LVL_WIDTH 1 /* GP6_LVL */
+#define WM8994_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */
+#define WM8994_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */
+#define WM8994_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */
+
+/*
+ * R1798 (0x706) - GPIO 7
+ */
+#define WM8994_GP7_DIR 0x8000 /* GP7_DIR */
+#define WM8994_GP7_DIR_MASK 0x8000 /* GP7_DIR */
+#define WM8994_GP7_DIR_SHIFT 15 /* GP7_DIR */
+#define WM8994_GP7_DIR_WIDTH 1 /* GP7_DIR */
+#define WM8994_GP7_PU 0x4000 /* GP7_PU */
+#define WM8994_GP7_PU_MASK 0x4000 /* GP7_PU */
+#define WM8994_GP7_PU_SHIFT 14 /* GP7_PU */
+#define WM8994_GP7_PU_WIDTH 1 /* GP7_PU */
+#define WM8994_GP7_PD 0x2000 /* GP7_PD */
+#define WM8994_GP7_PD_MASK 0x2000 /* GP7_PD */
+#define WM8994_GP7_PD_SHIFT 13 /* GP7_PD */
+#define WM8994_GP7_PD_WIDTH 1 /* GP7_PD */
+#define WM8994_GP7_POL 0x0400 /* GP7_POL */
+#define WM8994_GP7_POL_MASK 0x0400 /* GP7_POL */
+#define WM8994_GP7_POL_SHIFT 10 /* GP7_POL */
+#define WM8994_GP7_POL_WIDTH 1 /* GP7_POL */
+#define WM8994_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */
+#define WM8994_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */
+#define WM8994_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */
+#define WM8994_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */
+#define WM8994_GP7_DB 0x0100 /* GP7_DB */
+#define WM8994_GP7_DB_MASK 0x0100 /* GP7_DB */
+#define WM8994_GP7_DB_SHIFT 8 /* GP7_DB */
+#define WM8994_GP7_DB_WIDTH 1 /* GP7_DB */
+#define WM8994_GP7_LVL 0x0040 /* GP7_LVL */
+#define WM8994_GP7_LVL_MASK 0x0040 /* GP7_LVL */
+#define WM8994_GP7_LVL_SHIFT 6 /* GP7_LVL */
+#define WM8994_GP7_LVL_WIDTH 1 /* GP7_LVL */
+#define WM8994_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */
+#define WM8994_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */
+#define WM8994_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */
+
+/*
+ * R1799 (0x707) - GPIO 8
+ */
+#define WM8994_GP8_DIR 0x8000 /* GP8_DIR */
+#define WM8994_GP8_DIR_MASK 0x8000 /* GP8_DIR */
+#define WM8994_GP8_DIR_SHIFT 15 /* GP8_DIR */
+#define WM8994_GP8_DIR_WIDTH 1 /* GP8_DIR */
+#define WM8994_GP8_PU 0x4000 /* GP8_PU */
+#define WM8994_GP8_PU_MASK 0x4000 /* GP8_PU */
+#define WM8994_GP8_PU_SHIFT 14 /* GP8_PU */
+#define WM8994_GP8_PU_WIDTH 1 /* GP8_PU */
+#define WM8994_GP8_PD 0x2000 /* GP8_PD */
+#define WM8994_GP8_PD_MASK 0x2000 /* GP8_PD */
+#define WM8994_GP8_PD_SHIFT 13 /* GP8_PD */
+#define WM8994_GP8_PD_WIDTH 1 /* GP8_PD */
+#define WM8994_GP8_POL 0x0400 /* GP8_POL */
+#define WM8994_GP8_POL_MASK 0x0400 /* GP8_POL */
+#define WM8994_GP8_POL_SHIFT 10 /* GP8_POL */
+#define WM8994_GP8_POL_WIDTH 1 /* GP8_POL */
+#define WM8994_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */
+#define WM8994_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */
+#define WM8994_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */
+#define WM8994_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */
+#define WM8994_GP8_DB 0x0100 /* GP8_DB */
+#define WM8994_GP8_DB_MASK 0x0100 /* GP8_DB */
+#define WM8994_GP8_DB_SHIFT 8 /* GP8_DB */
+#define WM8994_GP8_DB_WIDTH 1 /* GP8_DB */
+#define WM8994_GP8_LVL 0x0040 /* GP8_LVL */
+#define WM8994_GP8_LVL_MASK 0x0040 /* GP8_LVL */
+#define WM8994_GP8_LVL_SHIFT 6 /* GP8_LVL */
+#define WM8994_GP8_LVL_WIDTH 1 /* GP8_LVL */
+#define WM8994_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */
+#define WM8994_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */
+#define WM8994_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */
+
+/*
+ * R1800 (0x708) - GPIO 9
+ */
+#define WM8994_GP9_DIR 0x8000 /* GP9_DIR */
+#define WM8994_GP9_DIR_MASK 0x8000 /* GP9_DIR */
+#define WM8994_GP9_DIR_SHIFT 15 /* GP9_DIR */
+#define WM8994_GP9_DIR_WIDTH 1 /* GP9_DIR */
+#define WM8994_GP9_PU 0x4000 /* GP9_PU */
+#define WM8994_GP9_PU_MASK 0x4000 /* GP9_PU */
+#define WM8994_GP9_PU_SHIFT 14 /* GP9_PU */
+#define WM8994_GP9_PU_WIDTH 1 /* GP9_PU */
+#define WM8994_GP9_PD 0x2000 /* GP9_PD */
+#define WM8994_GP9_PD_MASK 0x2000 /* GP9_PD */
+#define WM8994_GP9_PD_SHIFT 13 /* GP9_PD */
+#define WM8994_GP9_PD_WIDTH 1 /* GP9_PD */
+#define WM8994_GP9_POL 0x0400 /* GP9_POL */
+#define WM8994_GP9_POL_MASK 0x0400 /* GP9_POL */
+#define WM8994_GP9_POL_SHIFT 10 /* GP9_POL */
+#define WM8994_GP9_POL_WIDTH 1 /* GP9_POL */
+#define WM8994_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */
+#define WM8994_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */
+#define WM8994_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */
+#define WM8994_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */
+#define WM8994_GP9_DB 0x0100 /* GP9_DB */
+#define WM8994_GP9_DB_MASK 0x0100 /* GP9_DB */
+#define WM8994_GP9_DB_SHIFT 8 /* GP9_DB */
+#define WM8994_GP9_DB_WIDTH 1 /* GP9_DB */
+#define WM8994_GP9_LVL 0x0040 /* GP9_LVL */
+#define WM8994_GP9_LVL_MASK 0x0040 /* GP9_LVL */
+#define WM8994_GP9_LVL_SHIFT 6 /* GP9_LVL */
+#define WM8994_GP9_LVL_WIDTH 1 /* GP9_LVL */
+#define WM8994_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */
+#define WM8994_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */
+#define WM8994_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */
+
+/*
+ * R1801 (0x709) - GPIO 10
+ */
+#define WM8994_GP10_DIR 0x8000 /* GP10_DIR */
+#define WM8994_GP10_DIR_MASK 0x8000 /* GP10_DIR */
+#define WM8994_GP10_DIR_SHIFT 15 /* GP10_DIR */
+#define WM8994_GP10_DIR_WIDTH 1 /* GP10_DIR */
+#define WM8994_GP10_PU 0x4000 /* GP10_PU */
+#define WM8994_GP10_PU_MASK 0x4000 /* GP10_PU */
+#define WM8994_GP10_PU_SHIFT 14 /* GP10_PU */
+#define WM8994_GP10_PU_WIDTH 1 /* GP10_PU */
+#define WM8994_GP10_PD 0x2000 /* GP10_PD */
+#define WM8994_GP10_PD_MASK 0x2000 /* GP10_PD */
+#define WM8994_GP10_PD_SHIFT 13 /* GP10_PD */
+#define WM8994_GP10_PD_WIDTH 1 /* GP10_PD */
+#define WM8994_GP10_POL 0x0400 /* GP10_POL */
+#define WM8994_GP10_POL_MASK 0x0400 /* GP10_POL */
+#define WM8994_GP10_POL_SHIFT 10 /* GP10_POL */
+#define WM8994_GP10_POL_WIDTH 1 /* GP10_POL */
+#define WM8994_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */
+#define WM8994_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */
+#define WM8994_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */
+#define WM8994_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */
+#define WM8994_GP10_DB 0x0100 /* GP10_DB */
+#define WM8994_GP10_DB_MASK 0x0100 /* GP10_DB */
+#define WM8994_GP10_DB_SHIFT 8 /* GP10_DB */
+#define WM8994_GP10_DB_WIDTH 1 /* GP10_DB */
+#define WM8994_GP10_LVL 0x0040 /* GP10_LVL */
+#define WM8994_GP10_LVL_MASK 0x0040 /* GP10_LVL */
+#define WM8994_GP10_LVL_SHIFT 6 /* GP10_LVL */
+#define WM8994_GP10_LVL_WIDTH 1 /* GP10_LVL */
+#define WM8994_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */
+#define WM8994_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */
+#define WM8994_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */
+
+/*
+ * R1802 (0x70A) - GPIO 11
+ */
+#define WM8994_GP11_DIR 0x8000 /* GP11_DIR */
+#define WM8994_GP11_DIR_MASK 0x8000 /* GP11_DIR */
+#define WM8994_GP11_DIR_SHIFT 15 /* GP11_DIR */
+#define WM8994_GP11_DIR_WIDTH 1 /* GP11_DIR */
+#define WM8994_GP11_PU 0x4000 /* GP11_PU */
+#define WM8994_GP11_PU_MASK 0x4000 /* GP11_PU */
+#define WM8994_GP11_PU_SHIFT 14 /* GP11_PU */
+#define WM8994_GP11_PU_WIDTH 1 /* GP11_PU */
+#define WM8994_GP11_PD 0x2000 /* GP11_PD */
+#define WM8994_GP11_PD_MASK 0x2000 /* GP11_PD */
+#define WM8994_GP11_PD_SHIFT 13 /* GP11_PD */
+#define WM8994_GP11_PD_WIDTH 1 /* GP11_PD */
+#define WM8994_GP11_POL 0x0400 /* GP11_POL */
+#define WM8994_GP11_POL_MASK 0x0400 /* GP11_POL */
+#define WM8994_GP11_POL_SHIFT 10 /* GP11_POL */
+#define WM8994_GP11_POL_WIDTH 1 /* GP11_POL */
+#define WM8994_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */
+#define WM8994_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */
+#define WM8994_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */
+#define WM8994_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */
+#define WM8994_GP11_DB 0x0100 /* GP11_DB */
+#define WM8994_GP11_DB_MASK 0x0100 /* GP11_DB */
+#define WM8994_GP11_DB_SHIFT 8 /* GP11_DB */
+#define WM8994_GP11_DB_WIDTH 1 /* GP11_DB */
+#define WM8994_GP11_LVL 0x0040 /* GP11_LVL */
+#define WM8994_GP11_LVL_MASK 0x0040 /* GP11_LVL */
+#define WM8994_GP11_LVL_SHIFT 6 /* GP11_LVL */
+#define WM8994_GP11_LVL_WIDTH 1 /* GP11_LVL */
+#define WM8994_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */
+#define WM8994_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */
+#define WM8994_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */
+
+/*
+ * R1824 (0x720) - Digital Pulls
+ */
+#define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PU_MASK 0x0800 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PU_SHIFT 11 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PU_WIDTH 1 /* DMICDAT2_PU */
+#define WM8994_DMICDAT2_PD 0x0400 /* DMICDAT2_PD */
+#define WM8994_DMICDAT2_PD_MASK 0x0400 /* DMICDAT2_PD */
+#define WM8994_DMICDAT2_PD_SHIFT 10 /* DMICDAT2_PD */
+#define WM8994_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
+#define WM8994_DMICDAT1_PU 0x0200 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PU_MASK 0x0200 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PU_SHIFT 9 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PU_WIDTH 1 /* DMICDAT1_PU */
+#define WM8994_DMICDAT1_PD 0x0100 /* DMICDAT1_PD */
+#define WM8994_DMICDAT1_PD_MASK 0x0100 /* DMICDAT1_PD */
+#define WM8994_DMICDAT1_PD_SHIFT 8 /* DMICDAT1_PD */
+#define WM8994_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
+#define WM8994_MCLK1_PU 0x0080 /* MCLK1_PU */
+#define WM8994_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
+#define WM8994_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
+#define WM8994_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
+#define WM8994_MCLK1_PD 0x0040 /* MCLK1_PD */
+#define WM8994_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
+#define WM8994_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
+#define WM8994_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
+#define WM8994_DACDAT1_PU 0x0020 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
+#define WM8994_DACDAT1_PD 0x0010 /* DACDAT1_PD */
+#define WM8994_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
+#define WM8994_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
+#define WM8994_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
+#define WM8994_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
+#define WM8994_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
+#define WM8994_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
+#define WM8994_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
+#define WM8994_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
+#define WM8994_BCLK1_PU 0x0002 /* BCLK1_PU */
+#define WM8994_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
+#define WM8994_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
+#define WM8994_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
+#define WM8994_BCLK1_PD 0x0001 /* BCLK1_PD */
+#define WM8994_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
+#define WM8994_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
+#define WM8994_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
+
+/*
+ * R1840 (0x730) - Interrupt Status 1
+ */
+#define WM8994_GP11_EINT 0x0400 /* GP11_EINT */
+#define WM8994_GP11_EINT_MASK 0x0400 /* GP11_EINT */
+#define WM8994_GP11_EINT_SHIFT 10 /* GP11_EINT */
+#define WM8994_GP11_EINT_WIDTH 1 /* GP11_EINT */
+#define WM8994_GP10_EINT 0x0200 /* GP10_EINT */
+#define WM8994_GP10_EINT_MASK 0x0200 /* GP10_EINT */
+#define WM8994_GP10_EINT_SHIFT 9 /* GP10_EINT */
+#define WM8994_GP10_EINT_WIDTH 1 /* GP10_EINT */
+#define WM8994_GP9_EINT 0x0100 /* GP9_EINT */
+#define WM8994_GP9_EINT_MASK 0x0100 /* GP9_EINT */
+#define WM8994_GP9_EINT_SHIFT 8 /* GP9_EINT */
+#define WM8994_GP9_EINT_WIDTH 1 /* GP9_EINT */
+#define WM8994_GP8_EINT 0x0080 /* GP8_EINT */
+#define WM8994_GP8_EINT_MASK 0x0080 /* GP8_EINT */
+#define WM8994_GP8_EINT_SHIFT 7 /* GP8_EINT */
+#define WM8994_GP8_EINT_WIDTH 1 /* GP8_EINT */
+#define WM8994_GP7_EINT 0x0040 /* GP7_EINT */
+#define WM8994_GP7_EINT_MASK 0x0040 /* GP7_EINT */
+#define WM8994_GP7_EINT_SHIFT 6 /* GP7_EINT */
+#define WM8994_GP7_EINT_WIDTH 1 /* GP7_EINT */
+#define WM8994_GP6_EINT 0x0020 /* GP6_EINT */
+#define WM8994_GP6_EINT_MASK 0x0020 /* GP6_EINT */
+#define WM8994_GP6_EINT_SHIFT 5 /* GP6_EINT */
+#define WM8994_GP6_EINT_WIDTH 1 /* GP6_EINT */
+#define WM8994_GP5_EINT 0x0010 /* GP5_EINT */
+#define WM8994_GP5_EINT_MASK 0x0010 /* GP5_EINT */
+#define WM8994_GP5_EINT_SHIFT 4 /* GP5_EINT */
+#define WM8994_GP5_EINT_WIDTH 1 /* GP5_EINT */
+#define WM8994_GP4_EINT 0x0008 /* GP4_EINT */
+#define WM8994_GP4_EINT_MASK 0x0008 /* GP4_EINT */
+#define WM8994_GP4_EINT_SHIFT 3 /* GP4_EINT */
+#define WM8994_GP4_EINT_WIDTH 1 /* GP4_EINT */
+#define WM8994_GP3_EINT 0x0004 /* GP3_EINT */
+#define WM8994_GP3_EINT_MASK 0x0004 /* GP3_EINT */
+#define WM8994_GP3_EINT_SHIFT 2 /* GP3_EINT */
+#define WM8994_GP3_EINT_WIDTH 1 /* GP3_EINT */
+#define WM8994_GP2_EINT 0x0002 /* GP2_EINT */
+#define WM8994_GP2_EINT_MASK 0x0002 /* GP2_EINT */
+#define WM8994_GP2_EINT_SHIFT 1 /* GP2_EINT */
+#define WM8994_GP2_EINT_WIDTH 1 /* GP2_EINT */
+#define WM8994_GP1_EINT 0x0001 /* GP1_EINT */
+#define WM8994_GP1_EINT_MASK 0x0001 /* GP1_EINT */
+#define WM8994_GP1_EINT_SHIFT 0 /* GP1_EINT */
+#define WM8994_GP1_EINT_WIDTH 1 /* GP1_EINT */
+
+/*
+ * R1841 (0x731) - Interrupt Status 2
+ */
+#define WM8994_WSEQ_DONE_EINT 0x2000 /* WSEQ_DONE_EINT */
+#define WM8994_WSEQ_DONE_EINT_MASK 0x2000 /* WSEQ_DONE_EINT */
+#define WM8994_WSEQ_DONE_EINT_SHIFT 13 /* WSEQ_DONE_EINT */
+#define WM8994_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
+#define WM8994_FIFOS_ERR_EINT 0x1000 /* FIFOS_ERR_EINT */
+#define WM8994_FIFOS_ERR_EINT_MASK 0x1000 /* FIFOS_ERR_EINT */
+#define WM8994_FIFOS_ERR_EINT_SHIFT 12 /* FIFOS_ERR_EINT */
+#define WM8994_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
+#define WM8994_DRC3_ACTDET_EINT 0x0800 /* DRC3_ACTDET_EINT */
+#define WM8994_DRC3_ACTDET_EINT_MASK 0x0800 /* DRC3_ACTDET_EINT */
+#define WM8994_DRC3_ACTDET_EINT_SHIFT 11 /* DRC3_ACTDET_EINT */
+#define WM8994_DRC3_ACTDET_EINT_WIDTH 1 /* DRC3_ACTDET_EINT */
+#define WM8994_DRC2_ACTDET_EINT 0x0400 /* DRC2_ACTDET_EINT */
+#define WM8994_DRC2_ACTDET_EINT_MASK 0x0400 /* DRC2_ACTDET_EINT */
+#define WM8994_DRC2_ACTDET_EINT_SHIFT 10 /* DRC2_ACTDET_EINT */
+#define WM8994_DRC2_ACTDET_EINT_WIDTH 1 /* DRC2_ACTDET_EINT */
+#define WM8994_DRC1_ACTDET_EINT 0x0200 /* DRC1_ACTDET_EINT */
+#define WM8994_DRC1_ACTDET_EINT_MASK 0x0200 /* DRC1_ACTDET_EINT */
+#define WM8994_DRC1_ACTDET_EINT_SHIFT 9 /* DRC1_ACTDET_EINT */
+#define WM8994_DRC1_ACTDET_EINT_WIDTH 1 /* DRC1_ACTDET_EINT */
+#define WM8994_SRC2_LOCK_EINT 0x0100 /* SRC2_LOCK_EINT */
+#define WM8994_SRC2_LOCK_EINT_MASK 0x0100 /* SRC2_LOCK_EINT */
+#define WM8994_SRC2_LOCK_EINT_SHIFT 8 /* SRC2_LOCK_EINT */
+#define WM8994_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT 0x0080 /* SRC1_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT_MASK 0x0080 /* SRC1_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT_SHIFT 7 /* SRC1_LOCK_EINT */
+#define WM8994_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT 0x0040 /* FLL2_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT_MASK 0x0040 /* FLL2_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT_SHIFT 6 /* FLL2_LOCK_EINT */
+#define WM8994_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT 0x0020 /* FLL1_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT_MASK 0x0020 /* FLL1_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT_SHIFT 5 /* FLL1_LOCK_EINT */
+#define WM8994_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
+#define WM8994_MIC2_SHRT_EINT 0x0010 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_SHRT_EINT_MASK 0x0010 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_SHRT_EINT_SHIFT 4 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_SHRT_EINT_WIDTH 1 /* MIC2_SHRT_EINT */
+#define WM8994_MIC2_DET_EINT 0x0008 /* MIC2_DET_EINT */
+#define WM8994_MIC2_DET_EINT_MASK 0x0008 /* MIC2_DET_EINT */
+#define WM8994_MIC2_DET_EINT_SHIFT 3 /* MIC2_DET_EINT */
+#define WM8994_MIC2_DET_EINT_WIDTH 1 /* MIC2_DET_EINT */
+#define WM8994_MIC1_SHRT_EINT 0x0004 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_SHRT_EINT_MASK 0x0004 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_SHRT_EINT_SHIFT 2 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_SHRT_EINT_WIDTH 1 /* MIC1_SHRT_EINT */
+#define WM8994_MIC1_DET_EINT 0x0002 /* MIC1_DET_EINT */
+#define WM8994_MIC1_DET_EINT_MASK 0x0002 /* MIC1_DET_EINT */
+#define WM8994_MIC1_DET_EINT_SHIFT 1 /* MIC1_DET_EINT */
+#define WM8994_MIC1_DET_EINT_WIDTH 1 /* MIC1_DET_EINT */
+#define WM8994_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */
+#define WM8994_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */
+#define WM8994_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */
+#define WM8994_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */
+
+/*
+ * R1848 (0x738) - Interrupt Status 1 Mask
+ */
+#define WM8994_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
+#define WM8994_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
+#define WM8994_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
+#define WM8994_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
+#define WM8994_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
+#define WM8994_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
+#define WM8994_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
+#define WM8994_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
+#define WM8994_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
+#define WM8994_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
+#define WM8994_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
+#define WM8994_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
+#define WM8994_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
+#define WM8994_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
+#define WM8994_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
+#define WM8994_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
+#define WM8994_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
+#define WM8994_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
+#define WM8994_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
+#define WM8994_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
+#define WM8994_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
+#define WM8994_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
+#define WM8994_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
+#define WM8994_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
+#define WM8994_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
+#define WM8994_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
+#define WM8994_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
+#define WM8994_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
+#define WM8994_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
+#define WM8994_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
+#define WM8994_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
+#define WM8994_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
+#define WM8994_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
+#define WM8994_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
+#define WM8994_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
+#define WM8994_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
+#define WM8994_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
+#define WM8994_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
+#define WM8994_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
+#define WM8994_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
+#define WM8994_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
+#define WM8994_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
+#define WM8994_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
+#define WM8994_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
+
+/*
+ * R1849 (0x739) - Interrupt Status 2 Mask
+ */
+#define WM8994_IM_WSEQ_DONE_EINT 0x2000 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_WSEQ_DONE_EINT_MASK 0x2000 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_WSEQ_DONE_EINT_SHIFT 13 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT 0x1000 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT_MASK 0x1000 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT_SHIFT 12 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
+#define WM8994_IM_DRC3_ACTDET_EINT 0x0800 /* IM_DRC3_ACTDET_EINT */
+#define WM8994_IM_DRC3_ACTDET_EINT_MASK 0x0800 /* IM_DRC3_ACTDET_EINT */
+#define WM8994_IM_DRC3_ACTDET_EINT_SHIFT 11 /* IM_DRC3_ACTDET_EINT */
+#define WM8994_IM_DRC3_ACTDET_EINT_WIDTH 1 /* IM_DRC3_ACTDET_EINT */
+#define WM8994_IM_DRC2_ACTDET_EINT 0x0400 /* IM_DRC2_ACTDET_EINT */
+#define WM8994_IM_DRC2_ACTDET_EINT_MASK 0x0400 /* IM_DRC2_ACTDET_EINT */
+#define WM8994_IM_DRC2_ACTDET_EINT_SHIFT 10 /* IM_DRC2_ACTDET_EINT */
+#define WM8994_IM_DRC2_ACTDET_EINT_WIDTH 1 /* IM_DRC2_ACTDET_EINT */
+#define WM8994_IM_DRC1_ACTDET_EINT 0x0200 /* IM_DRC1_ACTDET_EINT */
+#define WM8994_IM_DRC1_ACTDET_EINT_MASK 0x0200 /* IM_DRC1_ACTDET_EINT */
+#define WM8994_IM_DRC1_ACTDET_EINT_SHIFT 9 /* IM_DRC1_ACTDET_EINT */
+#define WM8994_IM_DRC1_ACTDET_EINT_WIDTH 1 /* IM_DRC1_ACTDET_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT 0x0100 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT_MASK 0x0100 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT_SHIFT 8 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT 0x0080 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT_MASK 0x0080 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT_SHIFT 7 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT 0x0040 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT_MASK 0x0040 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT_SHIFT 6 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT 0x0020 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT_MASK 0x0020 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT_SHIFT 5 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT 0x0010 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT_MASK 0x0010 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT_SHIFT 4 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_SHRT_EINT_WIDTH 1 /* IM_MIC2_SHRT_EINT */
+#define WM8994_IM_MIC2_DET_EINT 0x0008 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC2_DET_EINT_MASK 0x0008 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC2_DET_EINT_SHIFT 3 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC2_DET_EINT_WIDTH 1 /* IM_MIC2_DET_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT 0x0004 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT_MASK 0x0004 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT_SHIFT 2 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_SHRT_EINT_WIDTH 1 /* IM_MIC1_SHRT_EINT */
+#define WM8994_IM_MIC1_DET_EINT 0x0002 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_MIC1_DET_EINT_MASK 0x0002 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_MIC1_DET_EINT_SHIFT 1 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_MIC1_DET_EINT_WIDTH 1 /* IM_MIC1_DET_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */
+#define WM8994_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */
+
+/*
+ * R1856 (0x740) - Interrupt Control
+ */
+#define WM8994_IRQ_POL 0x0001 /* IRQ_POL */
+#define WM8994_IRQ_POL_MASK 0x0001 /* IRQ_POL */
+#define WM8994_IRQ_POL_SHIFT 0 /* IRQ_POL */
+#define WM8994_IRQ_POL_WIDTH 1 /* IRQ_POL */
+
+/*
+ * R1864 (0x748) - IRQ Debounce
+ */
+#define WM8994_MIC2_SHRT_DB 0x0010 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_SHRT_DB_MASK 0x0010 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_SHRT_DB_SHIFT 4 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_SHRT_DB_WIDTH 1 /* MIC2_SHRT_DB */
+#define WM8994_MIC2_DET_DB 0x0008 /* MIC2_DET_DB */
+#define WM8994_MIC2_DET_DB_MASK 0x0008 /* MIC2_DET_DB */
+#define WM8994_MIC2_DET_DB_SHIFT 3 /* MIC2_DET_DB */
+#define WM8994_MIC2_DET_DB_WIDTH 1 /* MIC2_DET_DB */
+#define WM8994_MIC1_SHRT_DB 0x0004 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_SHRT_DB_MASK 0x0004 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_SHRT_DB_SHIFT 2 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_SHRT_DB_WIDTH 1 /* MIC1_SHRT_DB */
+#define WM8994_MIC1_DET_DB 0x0002 /* MIC1_DET_DB */
+#define WM8994_MIC1_DET_DB_MASK 0x0002 /* MIC1_DET_DB */
+#define WM8994_MIC1_DET_DB_SHIFT 1 /* MIC1_DET_DB */
+#define WM8994_MIC1_DET_DB_WIDTH 1 /* MIC1_DET_DB */
+#define WM8994_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */
+#define WM8994_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */
+#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */
+#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */
+
+/*
+ * R1865 (0x749) - IRQ Polarity
+ */
+#define WM8994_WSEQ_DONE_POL 0x2000 /* WSEQ_DONE_POL */
+#define WM8994_WSEQ_DONE_POL_MASK 0x2000 /* WSEQ_DONE_POL */
+#define WM8994_WSEQ_DONE_POL_SHIFT 13 /* WSEQ_DONE_POL */
+#define WM8994_WSEQ_DONE_POL_WIDTH 1 /* WSEQ_DONE_POL */
+#define WM8994_FIFOS_ERR_POL 0x1000 /* FIFOS_ERR_POL */
+#define WM8994_FIFOS_ERR_POL_MASK 0x1000 /* FIFOS_ERR_POL */
+#define WM8994_FIFOS_ERR_POL_SHIFT 12 /* FIFOS_ERR_POL */
+#define WM8994_FIFOS_ERR_POL_WIDTH 1 /* FIFOS_ERR_POL */
+#define WM8994_DRC3_ACTDET_POL 0x0800 /* DRC3_ACTDET_POL */
+#define WM8994_DRC3_ACTDET_POL_MASK 0x0800 /* DRC3_ACTDET_POL */
+#define WM8994_DRC3_ACTDET_POL_SHIFT 11 /* DRC3_ACTDET_POL */
+#define WM8994_DRC3_ACTDET_POL_WIDTH 1 /* DRC3_ACTDET_POL */
+#define WM8994_DRC2_ACTDET_POL 0x0400 /* DRC2_ACTDET_POL */
+#define WM8994_DRC2_ACTDET_POL_MASK 0x0400 /* DRC2_ACTDET_POL */
+#define WM8994_DRC2_ACTDET_POL_SHIFT 10 /* DRC2_ACTDET_POL */
+#define WM8994_DRC2_ACTDET_POL_WIDTH 1 /* DRC2_ACTDET_POL */
+#define WM8994_DRC1_ACTDET_POL 0x0200 /* DRC1_ACTDET_POL */
+#define WM8994_DRC1_ACTDET_POL_MASK 0x0200 /* DRC1_ACTDET_POL */
+#define WM8994_DRC1_ACTDET_POL_SHIFT 9 /* DRC1_ACTDET_POL */
+#define WM8994_DRC1_ACTDET_POL_WIDTH 1 /* DRC1_ACTDET_POL */
+#define WM8994_SRC2_LOCK_POL 0x0100 /* SRC2_LOCK_POL */
+#define WM8994_SRC2_LOCK_POL_MASK 0x0100 /* SRC2_LOCK_POL */
+#define WM8994_SRC2_LOCK_POL_SHIFT 8 /* SRC2_LOCK_POL */
+#define WM8994_SRC2_LOCK_POL_WIDTH 1 /* SRC2_LOCK_POL */
+#define WM8994_SRC1_LOCK_POL 0x0080 /* SRC1_LOCK_POL */
+#define WM8994_SRC1_LOCK_POL_MASK 0x0080 /* SRC1_LOCK_POL */
+#define WM8994_SRC1_LOCK_POL_SHIFT 7 /* SRC1_LOCK_POL */
+#define WM8994_SRC1_LOCK_POL_WIDTH 1 /* SRC1_LOCK_POL */
+#define WM8994_FLL2_LOCK_POL 0x0040 /* FLL2_LOCK_POL */
+#define WM8994_FLL2_LOCK_POL_MASK 0x0040 /* FLL2_LOCK_POL */
+#define WM8994_FLL2_LOCK_POL_SHIFT 6 /* FLL2_LOCK_POL */
+#define WM8994_FLL2_LOCK_POL_WIDTH 1 /* FLL2_LOCK_POL */
+#define WM8994_FLL1_LOCK_POL 0x0020 /* FLL1_LOCK_POL */
+#define WM8994_FLL1_LOCK_POL_MASK 0x0020 /* FLL1_LOCK_POL */
+#define WM8994_FLL1_LOCK_POL_SHIFT 5 /* FLL1_LOCK_POL */
+#define WM8994_FLL1_LOCK_POL_WIDTH 1 /* FLL1_LOCK_POL */
+#define WM8994_MIC2_SHRT_POL 0x0010 /* MIC2_SHRT_POL */
+#define WM8994_MIC2_SHRT_POL_MASK 0x0010 /* MIC2_SHRT_POL */
+#define WM8994_MIC2_SHRT_POL_SHIFT 4 /* MIC2_SHRT_POL */
+#define WM8994_MIC2_SHRT_POL_WIDTH 1 /* MIC2_SHRT_POL */
+#define WM8994_MIC2_DET_POL 0x0008 /* MIC2_DET_POL */
+#define WM8994_MIC2_DET_POL_MASK 0x0008 /* MIC2_DET_POL */
+#define WM8994_MIC2_DET_POL_SHIFT 3 /* MIC2_DET_POL */
+#define WM8994_MIC2_DET_POL_WIDTH 1 /* MIC2_DET_POL */
+#define WM8994_MIC1_SHRT_POL 0x0004 /* MIC1_SHRT_POL */
+#define WM8994_MIC1_SHRT_POL_MASK 0x0004 /* MIC1_SHRT_POL */
+#define WM8994_MIC1_SHRT_POL_SHIFT 2 /* MIC1_SHRT_POL */
+#define WM8994_MIC1_SHRT_POL_WIDTH 1 /* MIC1_SHRT_POL */
+#define WM8994_MIC1_DET_POL 0x0002 /* MIC1_DET_POL */
+#define WM8994_MIC1_DET_POL_MASK 0x0002 /* MIC1_DET_POL */
+#define WM8994_MIC1_DET_POL_SHIFT 1 /* MIC1_DET_POL */
+#define WM8994_MIC1_DET_POL_WIDTH 1 /* MIC1_DET_POL */
+#define WM8994_TEMP_SHUT_POL 0x0001 /* TEMP_SHUT_POL */
+#define WM8994_TEMP_SHUT_POL_MASK 0x0001 /* TEMP_SHUT_POL */
+#define WM8994_TEMP_SHUT_POL_SHIFT 0 /* TEMP_SHUT_POL */
+#define WM8994_TEMP_SHUT_POL_WIDTH 1 /* TEMP_SHUT_POL */
+
+/*
+ * R12288 (0x3000) - Write Sequencer 0
+ */
+#define WM8994_WSEQ_ADDR0_MASK 0x3FFF /* WSEQ_ADDR0 - [13:0] */
+#define WM8994_WSEQ_ADDR0_SHIFT 0 /* WSEQ_ADDR0 - [13:0] */
+#define WM8994_WSEQ_ADDR0_WIDTH 14 /* WSEQ_ADDR0 - [13:0] */
+
+/*
+ * R12289 (0x3001) - Write Sequencer 1
+ */
+#define WM8994_WSEQ_DATA0_MASK 0x00FF /* WSEQ_DATA0 - [7:0] */
+#define WM8994_WSEQ_DATA0_SHIFT 0 /* WSEQ_DATA0 - [7:0] */
+#define WM8994_WSEQ_DATA0_WIDTH 8 /* WSEQ_DATA0 - [7:0] */
+
+/*
+ * R12290 (0x3002) - Write Sequencer 2
+ */
+#define WM8994_WSEQ_DATA_WIDTH0_MASK 0x0700 /* WSEQ_DATA_WIDTH0 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH0_SHIFT 8 /* WSEQ_DATA_WIDTH0 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH0_WIDTH 3 /* WSEQ_DATA_WIDTH0 - [10:8] */
+#define WM8994_WSEQ_DATA_START0_MASK 0x000F /* WSEQ_DATA_START0 - [3:0] */
+#define WM8994_WSEQ_DATA_START0_SHIFT 0 /* WSEQ_DATA_START0 - [3:0] */
+#define WM8994_WSEQ_DATA_START0_WIDTH 4 /* WSEQ_DATA_START0 - [3:0] */
+
+/*
+ * R12291 (0x3003) - Write Sequencer 3
+ */
+#define WM8994_WSEQ_EOS0 0x0100 /* WSEQ_EOS0 */
+#define WM8994_WSEQ_EOS0_MASK 0x0100 /* WSEQ_EOS0 */
+#define WM8994_WSEQ_EOS0_SHIFT 8 /* WSEQ_EOS0 */
+#define WM8994_WSEQ_EOS0_WIDTH 1 /* WSEQ_EOS0 */
+#define WM8994_WSEQ_DELAY0_MASK 0x000F /* WSEQ_DELAY0 - [3:0] */
+#define WM8994_WSEQ_DELAY0_SHIFT 0 /* WSEQ_DELAY0 - [3:0] */
+#define WM8994_WSEQ_DELAY0_WIDTH 4 /* WSEQ_DELAY0 - [3:0] */
+
+/*
+ * R12292 (0x3004) - Write Sequencer 4
+ */
+#define WM8994_WSEQ_ADDR1_MASK 0x3FFF /* WSEQ_ADDR1 - [13:0] */
+#define WM8994_WSEQ_ADDR1_SHIFT 0 /* WSEQ_ADDR1 - [13:0] */
+#define WM8994_WSEQ_ADDR1_WIDTH 14 /* WSEQ_ADDR1 - [13:0] */
+
+/*
+ * R12293 (0x3005) - Write Sequencer 5
+ */
+#define WM8994_WSEQ_DATA1_MASK 0x00FF /* WSEQ_DATA1 - [7:0] */
+#define WM8994_WSEQ_DATA1_SHIFT 0 /* WSEQ_DATA1 - [7:0] */
+#define WM8994_WSEQ_DATA1_WIDTH 8 /* WSEQ_DATA1 - [7:0] */
+
+/*
+ * R12294 (0x3006) - Write Sequencer 6
+ */
+#define WM8994_WSEQ_DATA_WIDTH1_MASK 0x0700 /* WSEQ_DATA_WIDTH1 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH1_SHIFT 8 /* WSEQ_DATA_WIDTH1 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH1_WIDTH 3 /* WSEQ_DATA_WIDTH1 - [10:8] */
+#define WM8994_WSEQ_DATA_START1_MASK 0x000F /* WSEQ_DATA_START1 - [3:0] */
+#define WM8994_WSEQ_DATA_START1_SHIFT 0 /* WSEQ_DATA_START1 - [3:0] */
+#define WM8994_WSEQ_DATA_START1_WIDTH 4 /* WSEQ_DATA_START1 - [3:0] */
+
+/*
+ * R12295 (0x3007) - Write Sequencer 7
+ */
+#define WM8994_WSEQ_EOS1 0x0100 /* WSEQ_EOS1 */
+#define WM8994_WSEQ_EOS1_MASK 0x0100 /* WSEQ_EOS1 */
+#define WM8994_WSEQ_EOS1_SHIFT 8 /* WSEQ_EOS1 */
+#define WM8994_WSEQ_EOS1_WIDTH 1 /* WSEQ_EOS1 */
+#define WM8994_WSEQ_DELAY1_MASK 0x000F /* WSEQ_DELAY1 - [3:0] */
+#define WM8994_WSEQ_DELAY1_SHIFT 0 /* WSEQ_DELAY1 - [3:0] */
+#define WM8994_WSEQ_DELAY1_WIDTH 4 /* WSEQ_DELAY1 - [3:0] */
+
+/*
+ * R12296 (0x3008) - Write Sequencer 8
+ */
+#define WM8994_WSEQ_ADDR2_MASK 0x3FFF /* WSEQ_ADDR2 - [13:0] */
+#define WM8994_WSEQ_ADDR2_SHIFT 0 /* WSEQ_ADDR2 - [13:0] */
+#define WM8994_WSEQ_ADDR2_WIDTH 14 /* WSEQ_ADDR2 - [13:0] */
+
+/*
+ * R12297 (0x3009) - Write Sequencer 9
+ */
+#define WM8994_WSEQ_DATA2_MASK 0x00FF /* WSEQ_DATA2 - [7:0] */
+#define WM8994_WSEQ_DATA2_SHIFT 0 /* WSEQ_DATA2 - [7:0] */
+#define WM8994_WSEQ_DATA2_WIDTH 8 /* WSEQ_DATA2 - [7:0] */
+
+/*
+ * R12298 (0x300A) - Write Sequencer 10
+ */
+#define WM8994_WSEQ_DATA_WIDTH2_MASK 0x0700 /* WSEQ_DATA_WIDTH2 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH2_SHIFT 8 /* WSEQ_DATA_WIDTH2 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH2_WIDTH 3 /* WSEQ_DATA_WIDTH2 - [10:8] */
+#define WM8994_WSEQ_DATA_START2_MASK 0x000F /* WSEQ_DATA_START2 - [3:0] */
+#define WM8994_WSEQ_DATA_START2_SHIFT 0 /* WSEQ_DATA_START2 - [3:0] */
+#define WM8994_WSEQ_DATA_START2_WIDTH 4 /* WSEQ_DATA_START2 - [3:0] */
+
+/*
+ * R12299 (0x300B) - Write Sequencer 11
+ */
+#define WM8994_WSEQ_EOS2 0x0100 /* WSEQ_EOS2 */
+#define WM8994_WSEQ_EOS2_MASK 0x0100 /* WSEQ_EOS2 */
+#define WM8994_WSEQ_EOS2_SHIFT 8 /* WSEQ_EOS2 */
+#define WM8994_WSEQ_EOS2_WIDTH 1 /* WSEQ_EOS2 */
+#define WM8994_WSEQ_DELAY2_MASK 0x000F /* WSEQ_DELAY2 - [3:0] */
+#define WM8994_WSEQ_DELAY2_SHIFT 0 /* WSEQ_DELAY2 - [3:0] */
+#define WM8994_WSEQ_DELAY2_WIDTH 4 /* WSEQ_DELAY2 - [3:0] */
+
+/*
+ * R12300 (0x300C) - Write Sequencer 12
+ */
+#define WM8994_WSEQ_ADDR3_MASK 0x3FFF /* WSEQ_ADDR3 - [13:0] */
+#define WM8994_WSEQ_ADDR3_SHIFT 0 /* WSEQ_ADDR3 - [13:0] */
+#define WM8994_WSEQ_ADDR3_WIDTH 14 /* WSEQ_ADDR3 - [13:0] */
+
+/*
+ * R12301 (0x300D) - Write Sequencer 13
+ */
+#define WM8994_WSEQ_DATA3_MASK 0x00FF /* WSEQ_DATA3 - [7:0] */
+#define WM8994_WSEQ_DATA3_SHIFT 0 /* WSEQ_DATA3 - [7:0] */
+#define WM8994_WSEQ_DATA3_WIDTH 8 /* WSEQ_DATA3 - [7:0] */
+
+/*
+ * R12302 (0x300E) - Write Sequencer 14
+ */
+#define WM8994_WSEQ_DATA_WIDTH3_MASK 0x0700 /* WSEQ_DATA_WIDTH3 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH3_SHIFT 8 /* WSEQ_DATA_WIDTH3 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH3_WIDTH 3 /* WSEQ_DATA_WIDTH3 - [10:8] */
+#define WM8994_WSEQ_DATA_START3_MASK 0x000F /* WSEQ_DATA_START3 - [3:0] */
+#define WM8994_WSEQ_DATA_START3_SHIFT 0 /* WSEQ_DATA_START3 - [3:0] */
+#define WM8994_WSEQ_DATA_START3_WIDTH 4 /* WSEQ_DATA_START3 - [3:0] */
+
+/*
+ * R12303 (0x300F) - Write Sequencer 15
+ */
+#define WM8994_WSEQ_EOS3 0x0100 /* WSEQ_EOS3 */
+#define WM8994_WSEQ_EOS3_MASK 0x0100 /* WSEQ_EOS3 */
+#define WM8994_WSEQ_EOS3_SHIFT 8 /* WSEQ_EOS3 */
+#define WM8994_WSEQ_EOS3_WIDTH 1 /* WSEQ_EOS3 */
+#define WM8994_WSEQ_DELAY3_MASK 0x000F /* WSEQ_DELAY3 - [3:0] */
+#define WM8994_WSEQ_DELAY3_SHIFT 0 /* WSEQ_DELAY3 - [3:0] */
+#define WM8994_WSEQ_DELAY3_WIDTH 4 /* WSEQ_DELAY3 - [3:0] */
+
+/*
+ * R12304 (0x3010) - Write Sequencer 16
+ */
+#define WM8994_WSEQ_ADDR4_MASK 0x3FFF /* WSEQ_ADDR4 - [13:0] */
+#define WM8994_WSEQ_ADDR4_SHIFT 0 /* WSEQ_ADDR4 - [13:0] */
+#define WM8994_WSEQ_ADDR4_WIDTH 14 /* WSEQ_ADDR4 - [13:0] */
+
+/*
+ * R12305 (0x3011) - Write Sequencer 17
+ */
+#define WM8994_WSEQ_DATA4_MASK 0x00FF /* WSEQ_DATA4 - [7:0] */
+#define WM8994_WSEQ_DATA4_SHIFT 0 /* WSEQ_DATA4 - [7:0] */
+#define WM8994_WSEQ_DATA4_WIDTH 8 /* WSEQ_DATA4 - [7:0] */
+
+/*
+ * R12306 (0x3012) - Write Sequencer 18
+ */
+#define WM8994_WSEQ_DATA_WIDTH4_MASK 0x0700 /* WSEQ_DATA_WIDTH4 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH4_SHIFT 8 /* WSEQ_DATA_WIDTH4 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH4_WIDTH 3 /* WSEQ_DATA_WIDTH4 - [10:8] */
+#define WM8994_WSEQ_DATA_START4_MASK 0x000F /* WSEQ_DATA_START4 - [3:0] */
+#define WM8994_WSEQ_DATA_START4_SHIFT 0 /* WSEQ_DATA_START4 - [3:0] */
+#define WM8994_WSEQ_DATA_START4_WIDTH 4 /* WSEQ_DATA_START4 - [3:0] */
+
+/*
+ * R12307 (0x3013) - Write Sequencer 19
+ */
+#define WM8994_WSEQ_EOS4 0x0100 /* WSEQ_EOS4 */
+#define WM8994_WSEQ_EOS4_MASK 0x0100 /* WSEQ_EOS4 */
+#define WM8994_WSEQ_EOS4_SHIFT 8 /* WSEQ_EOS4 */
+#define WM8994_WSEQ_EOS4_WIDTH 1 /* WSEQ_EOS4 */
+#define WM8994_WSEQ_DELAY4_MASK 0x000F /* WSEQ_DELAY4 - [3:0] */
+#define WM8994_WSEQ_DELAY4_SHIFT 0 /* WSEQ_DELAY4 - [3:0] */
+#define WM8994_WSEQ_DELAY4_WIDTH 4 /* WSEQ_DELAY4 - [3:0] */
+
+/*
+ * R12308 (0x3014) - Write Sequencer 20
+ */
+#define WM8994_WSEQ_ADDR5_MASK 0x3FFF /* WSEQ_ADDR5 - [13:0] */
+#define WM8994_WSEQ_ADDR5_SHIFT 0 /* WSEQ_ADDR5 - [13:0] */
+#define WM8994_WSEQ_ADDR5_WIDTH 14 /* WSEQ_ADDR5 - [13:0] */
+
+/*
+ * R12309 (0x3015) - Write Sequencer 21
+ */
+#define WM8994_WSEQ_DATA5_MASK 0x00FF /* WSEQ_DATA5 - [7:0] */
+#define WM8994_WSEQ_DATA5_SHIFT 0 /* WSEQ_DATA5 - [7:0] */
+#define WM8994_WSEQ_DATA5_WIDTH 8 /* WSEQ_DATA5 - [7:0] */
+
+/*
+ * R12310 (0x3016) - Write Sequencer 22
+ */
+#define WM8994_WSEQ_DATA_WIDTH5_MASK 0x0700 /* WSEQ_DATA_WIDTH5 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH5_SHIFT 8 /* WSEQ_DATA_WIDTH5 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH5_WIDTH 3 /* WSEQ_DATA_WIDTH5 - [10:8] */
+#define WM8994_WSEQ_DATA_START5_MASK 0x000F /* WSEQ_DATA_START5 - [3:0] */
+#define WM8994_WSEQ_DATA_START5_SHIFT 0 /* WSEQ_DATA_START5 - [3:0] */
+#define WM8994_WSEQ_DATA_START5_WIDTH 4 /* WSEQ_DATA_START5 - [3:0] */
+
+/*
+ * R12311 (0x3017) - Write Sequencer 23
+ */
+#define WM8994_WSEQ_EOS5 0x0100 /* WSEQ_EOS5 */
+#define WM8994_WSEQ_EOS5_MASK 0x0100 /* WSEQ_EOS5 */
+#define WM8994_WSEQ_EOS5_SHIFT 8 /* WSEQ_EOS5 */
+#define WM8994_WSEQ_EOS5_WIDTH 1 /* WSEQ_EOS5 */
+#define WM8994_WSEQ_DELAY5_MASK 0x000F /* WSEQ_DELAY5 - [3:0] */
+#define WM8994_WSEQ_DELAY5_SHIFT 0 /* WSEQ_DELAY5 - [3:0] */
+#define WM8994_WSEQ_DELAY5_WIDTH 4 /* WSEQ_DELAY5 - [3:0] */
+
+/*
+ * R12312 (0x3018) - Write Sequencer 24
+ */
+#define WM8994_WSEQ_ADDR6_MASK 0x3FFF /* WSEQ_ADDR6 - [13:0] */
+#define WM8994_WSEQ_ADDR6_SHIFT 0 /* WSEQ_ADDR6 - [13:0] */
+#define WM8994_WSEQ_ADDR6_WIDTH 14 /* WSEQ_ADDR6 - [13:0] */
+
+/*
+ * R12313 (0x3019) - Write Sequencer 25
+ */
+#define WM8994_WSEQ_DATA6_MASK 0x00FF /* WSEQ_DATA6 - [7:0] */
+#define WM8994_WSEQ_DATA6_SHIFT 0 /* WSEQ_DATA6 - [7:0] */
+#define WM8994_WSEQ_DATA6_WIDTH 8 /* WSEQ_DATA6 - [7:0] */
+
+/*
+ * R12314 (0x301A) - Write Sequencer 26
+ */
+#define WM8994_WSEQ_DATA_WIDTH6_MASK 0x0700 /* WSEQ_DATA_WIDTH6 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH6_SHIFT 8 /* WSEQ_DATA_WIDTH6 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH6_WIDTH 3 /* WSEQ_DATA_WIDTH6 - [10:8] */
+#define WM8994_WSEQ_DATA_START6_MASK 0x000F /* WSEQ_DATA_START6 - [3:0] */
+#define WM8994_WSEQ_DATA_START6_SHIFT 0 /* WSEQ_DATA_START6 - [3:0] */
+#define WM8994_WSEQ_DATA_START6_WIDTH 4 /* WSEQ_DATA_START6 - [3:0] */
+
+/*
+ * R12315 (0x301B) - Write Sequencer 27
+ */
+#define WM8994_WSEQ_EOS6 0x0100 /* WSEQ_EOS6 */
+#define WM8994_WSEQ_EOS6_MASK 0x0100 /* WSEQ_EOS6 */
+#define WM8994_WSEQ_EOS6_SHIFT 8 /* WSEQ_EOS6 */
+#define WM8994_WSEQ_EOS6_WIDTH 1 /* WSEQ_EOS6 */
+#define WM8994_WSEQ_DELAY6_MASK 0x000F /* WSEQ_DELAY6 - [3:0] */
+#define WM8994_WSEQ_DELAY6_SHIFT 0 /* WSEQ_DELAY6 - [3:0] */
+#define WM8994_WSEQ_DELAY6_WIDTH 4 /* WSEQ_DELAY6 - [3:0] */
+
+/*
+ * R12316 (0x301C) - Write Sequencer 28
+ */
+#define WM8994_WSEQ_ADDR7_MASK 0x3FFF /* WSEQ_ADDR7 - [13:0] */
+#define WM8994_WSEQ_ADDR7_SHIFT 0 /* WSEQ_ADDR7 - [13:0] */
+#define WM8994_WSEQ_ADDR7_WIDTH 14 /* WSEQ_ADDR7 - [13:0] */
+
+/*
+ * R12317 (0x301D) - Write Sequencer 29
+ */
+#define WM8994_WSEQ_DATA7_MASK 0x00FF /* WSEQ_DATA7 - [7:0] */
+#define WM8994_WSEQ_DATA7_SHIFT 0 /* WSEQ_DATA7 - [7:0] */
+#define WM8994_WSEQ_DATA7_WIDTH 8 /* WSEQ_DATA7 - [7:0] */
+
+/*
+ * R12318 (0x301E) - Write Sequencer 30
+ */
+#define WM8994_WSEQ_DATA_WIDTH7_MASK 0x0700 /* WSEQ_DATA_WIDTH7 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH7_SHIFT 8 /* WSEQ_DATA_WIDTH7 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH7_WIDTH 3 /* WSEQ_DATA_WIDTH7 - [10:8] */
+#define WM8994_WSEQ_DATA_START7_MASK 0x000F /* WSEQ_DATA_START7 - [3:0] */
+#define WM8994_WSEQ_DATA_START7_SHIFT 0 /* WSEQ_DATA_START7 - [3:0] */
+#define WM8994_WSEQ_DATA_START7_WIDTH 4 /* WSEQ_DATA_START7 - [3:0] */
+
+/*
+ * R12319 (0x301F) - Write Sequencer 31
+ */
+#define WM8994_WSEQ_EOS7 0x0100 /* WSEQ_EOS7 */
+#define WM8994_WSEQ_EOS7_MASK 0x0100 /* WSEQ_EOS7 */
+#define WM8994_WSEQ_EOS7_SHIFT 8 /* WSEQ_EOS7 */
+#define WM8994_WSEQ_EOS7_WIDTH 1 /* WSEQ_EOS7 */
+#define WM8994_WSEQ_DELAY7_MASK 0x000F /* WSEQ_DELAY7 - [3:0] */
+#define WM8994_WSEQ_DELAY7_SHIFT 0 /* WSEQ_DELAY7 - [3:0] */
+#define WM8994_WSEQ_DELAY7_WIDTH 4 /* WSEQ_DELAY7 - [3:0] */
+
+/*
+ * R12320 (0x3020) - Write Sequencer 32
+ */
+#define WM8994_WSEQ_ADDR8_MASK 0x3FFF /* WSEQ_ADDR8 - [13:0] */
+#define WM8994_WSEQ_ADDR8_SHIFT 0 /* WSEQ_ADDR8 - [13:0] */
+#define WM8994_WSEQ_ADDR8_WIDTH 14 /* WSEQ_ADDR8 - [13:0] */
+
+/*
+ * R12321 (0x3021) - Write Sequencer 33
+ */
+#define WM8994_WSEQ_DATA8_MASK 0x00FF /* WSEQ_DATA8 - [7:0] */
+#define WM8994_WSEQ_DATA8_SHIFT 0 /* WSEQ_DATA8 - [7:0] */
+#define WM8994_WSEQ_DATA8_WIDTH 8 /* WSEQ_DATA8 - [7:0] */
+
+/*
+ * R12322 (0x3022) - Write Sequencer 34
+ */
+#define WM8994_WSEQ_DATA_WIDTH8_MASK 0x0700 /* WSEQ_DATA_WIDTH8 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH8_SHIFT 8 /* WSEQ_DATA_WIDTH8 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH8_WIDTH 3 /* WSEQ_DATA_WIDTH8 - [10:8] */
+#define WM8994_WSEQ_DATA_START8_MASK 0x000F /* WSEQ_DATA_START8 - [3:0] */
+#define WM8994_WSEQ_DATA_START8_SHIFT 0 /* WSEQ_DATA_START8 - [3:0] */
+#define WM8994_WSEQ_DATA_START8_WIDTH 4 /* WSEQ_DATA_START8 - [3:0] */
+
+/*
+ * R12323 (0x3023) - Write Sequencer 35
+ */
+#define WM8994_WSEQ_EOS8 0x0100 /* WSEQ_EOS8 */
+#define WM8994_WSEQ_EOS8_MASK 0x0100 /* WSEQ_EOS8 */
+#define WM8994_WSEQ_EOS8_SHIFT 8 /* WSEQ_EOS8 */
+#define WM8994_WSEQ_EOS8_WIDTH 1 /* WSEQ_EOS8 */
+#define WM8994_WSEQ_DELAY8_MASK 0x000F /* WSEQ_DELAY8 - [3:0] */
+#define WM8994_WSEQ_DELAY8_SHIFT 0 /* WSEQ_DELAY8 - [3:0] */
+#define WM8994_WSEQ_DELAY8_WIDTH 4 /* WSEQ_DELAY8 - [3:0] */
+
+/*
+ * R12324 (0x3024) - Write Sequencer 36
+ */
+#define WM8994_WSEQ_ADDR9_MASK 0x3FFF /* WSEQ_ADDR9 - [13:0] */
+#define WM8994_WSEQ_ADDR9_SHIFT 0 /* WSEQ_ADDR9 - [13:0] */
+#define WM8994_WSEQ_ADDR9_WIDTH 14 /* WSEQ_ADDR9 - [13:0] */
+
+/*
+ * R12325 (0x3025) - Write Sequencer 37
+ */
+#define WM8994_WSEQ_DATA9_MASK 0x00FF /* WSEQ_DATA9 - [7:0] */
+#define WM8994_WSEQ_DATA9_SHIFT 0 /* WSEQ_DATA9 - [7:0] */
+#define WM8994_WSEQ_DATA9_WIDTH 8 /* WSEQ_DATA9 - [7:0] */
+
+/*
+ * R12326 (0x3026) - Write Sequencer 38
+ */
+#define WM8994_WSEQ_DATA_WIDTH9_MASK 0x0700 /* WSEQ_DATA_WIDTH9 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH9_SHIFT 8 /* WSEQ_DATA_WIDTH9 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH9_WIDTH 3 /* WSEQ_DATA_WIDTH9 - [10:8] */
+#define WM8994_WSEQ_DATA_START9_MASK 0x000F /* WSEQ_DATA_START9 - [3:0] */
+#define WM8994_WSEQ_DATA_START9_SHIFT 0 /* WSEQ_DATA_START9 - [3:0] */
+#define WM8994_WSEQ_DATA_START9_WIDTH 4 /* WSEQ_DATA_START9 - [3:0] */
+
+/*
+ * R12327 (0x3027) - Write Sequencer 39
+ */
+#define WM8994_WSEQ_EOS9 0x0100 /* WSEQ_EOS9 */
+#define WM8994_WSEQ_EOS9_MASK 0x0100 /* WSEQ_EOS9 */
+#define WM8994_WSEQ_EOS9_SHIFT 8 /* WSEQ_EOS9 */
+#define WM8994_WSEQ_EOS9_WIDTH 1 /* WSEQ_EOS9 */
+#define WM8994_WSEQ_DELAY9_MASK 0x000F /* WSEQ_DELAY9 - [3:0] */
+#define WM8994_WSEQ_DELAY9_SHIFT 0 /* WSEQ_DELAY9 - [3:0] */
+#define WM8994_WSEQ_DELAY9_WIDTH 4 /* WSEQ_DELAY9 - [3:0] */
+
+/*
+ * R12328 (0x3028) - Write Sequencer 40
+ */
+#define WM8994_WSEQ_ADDR10_MASK 0x3FFF /* WSEQ_ADDR10 - [13:0] */
+#define WM8994_WSEQ_ADDR10_SHIFT 0 /* WSEQ_ADDR10 - [13:0] */
+#define WM8994_WSEQ_ADDR10_WIDTH 14 /* WSEQ_ADDR10 - [13:0] */
+
+/*
+ * R12329 (0x3029) - Write Sequencer 41
+ */
+#define WM8994_WSEQ_DATA10_MASK 0x00FF /* WSEQ_DATA10 - [7:0] */
+#define WM8994_WSEQ_DATA10_SHIFT 0 /* WSEQ_DATA10 - [7:0] */
+#define WM8994_WSEQ_DATA10_WIDTH 8 /* WSEQ_DATA10 - [7:0] */
+
+/*
+ * R12330 (0x302A) - Write Sequencer 42
+ */
+#define WM8994_WSEQ_DATA_WIDTH10_MASK 0x0700 /* WSEQ_DATA_WIDTH10 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH10_SHIFT 8 /* WSEQ_DATA_WIDTH10 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH10_WIDTH 3 /* WSEQ_DATA_WIDTH10 - [10:8] */
+#define WM8994_WSEQ_DATA_START10_MASK 0x000F /* WSEQ_DATA_START10 - [3:0] */
+#define WM8994_WSEQ_DATA_START10_SHIFT 0 /* WSEQ_DATA_START10 - [3:0] */
+#define WM8994_WSEQ_DATA_START10_WIDTH 4 /* WSEQ_DATA_START10 - [3:0] */
+
+/*
+ * R12331 (0x302B) - Write Sequencer 43
+ */
+#define WM8994_WSEQ_EOS10 0x0100 /* WSEQ_EOS10 */
+#define WM8994_WSEQ_EOS10_MASK 0x0100 /* WSEQ_EOS10 */
+#define WM8994_WSEQ_EOS10_SHIFT 8 /* WSEQ_EOS10 */
+#define WM8994_WSEQ_EOS10_WIDTH 1 /* WSEQ_EOS10 */
+#define WM8994_WSEQ_DELAY10_MASK 0x000F /* WSEQ_DELAY10 - [3:0] */
+#define WM8994_WSEQ_DELAY10_SHIFT 0 /* WSEQ_DELAY10 - [3:0] */
+#define WM8994_WSEQ_DELAY10_WIDTH 4 /* WSEQ_DELAY10 - [3:0] */
+
+/*
+ * R12332 (0x302C) - Write Sequencer 44
+ */
+#define WM8994_WSEQ_ADDR11_MASK 0x3FFF /* WSEQ_ADDR11 - [13:0] */
+#define WM8994_WSEQ_ADDR11_SHIFT 0 /* WSEQ_ADDR11 - [13:0] */
+#define WM8994_WSEQ_ADDR11_WIDTH 14 /* WSEQ_ADDR11 - [13:0] */
+
+/*
+ * R12333 (0x302D) - Write Sequencer 45
+ */
+#define WM8994_WSEQ_DATA11_MASK 0x00FF /* WSEQ_DATA11 - [7:0] */
+#define WM8994_WSEQ_DATA11_SHIFT 0 /* WSEQ_DATA11 - [7:0] */
+#define WM8994_WSEQ_DATA11_WIDTH 8 /* WSEQ_DATA11 - [7:0] */
+
+/*
+ * R12334 (0x302E) - Write Sequencer 46
+ */
+#define WM8994_WSEQ_DATA_WIDTH11_MASK 0x0700 /* WSEQ_DATA_WIDTH11 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH11_SHIFT 8 /* WSEQ_DATA_WIDTH11 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH11_WIDTH 3 /* WSEQ_DATA_WIDTH11 - [10:8] */
+#define WM8994_WSEQ_DATA_START11_MASK 0x000F /* WSEQ_DATA_START11 - [3:0] */
+#define WM8994_WSEQ_DATA_START11_SHIFT 0 /* WSEQ_DATA_START11 - [3:0] */
+#define WM8994_WSEQ_DATA_START11_WIDTH 4 /* WSEQ_DATA_START11 - [3:0] */
+
+/*
+ * R12335 (0x302F) - Write Sequencer 47
+ */
+#define WM8994_WSEQ_EOS11 0x0100 /* WSEQ_EOS11 */
+#define WM8994_WSEQ_EOS11_MASK 0x0100 /* WSEQ_EOS11 */
+#define WM8994_WSEQ_EOS11_SHIFT 8 /* WSEQ_EOS11 */
+#define WM8994_WSEQ_EOS11_WIDTH 1 /* WSEQ_EOS11 */
+#define WM8994_WSEQ_DELAY11_MASK 0x000F /* WSEQ_DELAY11 - [3:0] */
+#define WM8994_WSEQ_DELAY11_SHIFT 0 /* WSEQ_DELAY11 - [3:0] */
+#define WM8994_WSEQ_DELAY11_WIDTH 4 /* WSEQ_DELAY11 - [3:0] */
+
+/*
+ * R12336 (0x3030) - Write Sequencer 48
+ */
+#define WM8994_WSEQ_ADDR12_MASK 0x3FFF /* WSEQ_ADDR12 - [13:0] */
+#define WM8994_WSEQ_ADDR12_SHIFT 0 /* WSEQ_ADDR12 - [13:0] */
+#define WM8994_WSEQ_ADDR12_WIDTH 14 /* WSEQ_ADDR12 - [13:0] */
+
+/*
+ * R12337 (0x3031) - Write Sequencer 49
+ */
+#define WM8994_WSEQ_DATA12_MASK 0x00FF /* WSEQ_DATA12 - [7:0] */
+#define WM8994_WSEQ_DATA12_SHIFT 0 /* WSEQ_DATA12 - [7:0] */
+#define WM8994_WSEQ_DATA12_WIDTH 8 /* WSEQ_DATA12 - [7:0] */
+
+/*
+ * R12338 (0x3032) - Write Sequencer 50
+ */
+#define WM8994_WSEQ_DATA_WIDTH12_MASK 0x0700 /* WSEQ_DATA_WIDTH12 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH12_SHIFT 8 /* WSEQ_DATA_WIDTH12 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH12_WIDTH 3 /* WSEQ_DATA_WIDTH12 - [10:8] */
+#define WM8994_WSEQ_DATA_START12_MASK 0x000F /* WSEQ_DATA_START12 - [3:0] */
+#define WM8994_WSEQ_DATA_START12_SHIFT 0 /* WSEQ_DATA_START12 - [3:0] */
+#define WM8994_WSEQ_DATA_START12_WIDTH 4 /* WSEQ_DATA_START12 - [3:0] */
+
+/*
+ * R12339 (0x3033) - Write Sequencer 51
+ */
+#define WM8994_WSEQ_EOS12 0x0100 /* WSEQ_EOS12 */
+#define WM8994_WSEQ_EOS12_MASK 0x0100 /* WSEQ_EOS12 */
+#define WM8994_WSEQ_EOS12_SHIFT 8 /* WSEQ_EOS12 */
+#define WM8994_WSEQ_EOS12_WIDTH 1 /* WSEQ_EOS12 */
+#define WM8994_WSEQ_DELAY12_MASK 0x000F /* WSEQ_DELAY12 - [3:0] */
+#define WM8994_WSEQ_DELAY12_SHIFT 0 /* WSEQ_DELAY12 - [3:0] */
+#define WM8994_WSEQ_DELAY12_WIDTH 4 /* WSEQ_DELAY12 - [3:0] */
+
+/*
+ * R12340 (0x3034) - Write Sequencer 52
+ */
+#define WM8994_WSEQ_ADDR13_MASK 0x3FFF /* WSEQ_ADDR13 - [13:0] */
+#define WM8994_WSEQ_ADDR13_SHIFT 0 /* WSEQ_ADDR13 - [13:0] */
+#define WM8994_WSEQ_ADDR13_WIDTH 14 /* WSEQ_ADDR13 - [13:0] */
+
+/*
+ * R12341 (0x3035) - Write Sequencer 53
+ */
+#define WM8994_WSEQ_DATA13_MASK 0x00FF /* WSEQ_DATA13 - [7:0] */
+#define WM8994_WSEQ_DATA13_SHIFT 0 /* WSEQ_DATA13 - [7:0] */
+#define WM8994_WSEQ_DATA13_WIDTH 8 /* WSEQ_DATA13 - [7:0] */
+
+/*
+ * R12342 (0x3036) - Write Sequencer 54
+ */
+#define WM8994_WSEQ_DATA_WIDTH13_MASK 0x0700 /* WSEQ_DATA_WIDTH13 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH13_SHIFT 8 /* WSEQ_DATA_WIDTH13 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH13_WIDTH 3 /* WSEQ_DATA_WIDTH13 - [10:8] */
+#define WM8994_WSEQ_DATA_START13_MASK 0x000F /* WSEQ_DATA_START13 - [3:0] */
+#define WM8994_WSEQ_DATA_START13_SHIFT 0 /* WSEQ_DATA_START13 - [3:0] */
+#define WM8994_WSEQ_DATA_START13_WIDTH 4 /* WSEQ_DATA_START13 - [3:0] */
+
+/*
+ * R12343 (0x3037) - Write Sequencer 55
+ */
+#define WM8994_WSEQ_EOS13 0x0100 /* WSEQ_EOS13 */
+#define WM8994_WSEQ_EOS13_MASK 0x0100 /* WSEQ_EOS13 */
+#define WM8994_WSEQ_EOS13_SHIFT 8 /* WSEQ_EOS13 */
+#define WM8994_WSEQ_EOS13_WIDTH 1 /* WSEQ_EOS13 */
+#define WM8994_WSEQ_DELAY13_MASK 0x000F /* WSEQ_DELAY13 - [3:0] */
+#define WM8994_WSEQ_DELAY13_SHIFT 0 /* WSEQ_DELAY13 - [3:0] */
+#define WM8994_WSEQ_DELAY13_WIDTH 4 /* WSEQ_DELAY13 - [3:0] */
+
+/*
+ * R12344 (0x3038) - Write Sequencer 56
+ */
+#define WM8994_WSEQ_ADDR14_MASK 0x3FFF /* WSEQ_ADDR14 - [13:0] */
+#define WM8994_WSEQ_ADDR14_SHIFT 0 /* WSEQ_ADDR14 - [13:0] */
+#define WM8994_WSEQ_ADDR14_WIDTH 14 /* WSEQ_ADDR14 - [13:0] */
+
+/*
+ * R12345 (0x3039) - Write Sequencer 57
+ */
+#define WM8994_WSEQ_DATA14_MASK 0x00FF /* WSEQ_DATA14 - [7:0] */
+#define WM8994_WSEQ_DATA14_SHIFT 0 /* WSEQ_DATA14 - [7:0] */
+#define WM8994_WSEQ_DATA14_WIDTH 8 /* WSEQ_DATA14 - [7:0] */
+
+/*
+ * R12346 (0x303A) - Write Sequencer 58
+ */
+#define WM8994_WSEQ_DATA_WIDTH14_MASK 0x0700 /* WSEQ_DATA_WIDTH14 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH14_SHIFT 8 /* WSEQ_DATA_WIDTH14 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH14_WIDTH 3 /* WSEQ_DATA_WIDTH14 - [10:8] */
+#define WM8994_WSEQ_DATA_START14_MASK 0x000F /* WSEQ_DATA_START14 - [3:0] */
+#define WM8994_WSEQ_DATA_START14_SHIFT 0 /* WSEQ_DATA_START14 - [3:0] */
+#define WM8994_WSEQ_DATA_START14_WIDTH 4 /* WSEQ_DATA_START14 - [3:0] */
+
+/*
+ * R12347 (0x303B) - Write Sequencer 59
+ */
+#define WM8994_WSEQ_EOS14 0x0100 /* WSEQ_EOS14 */
+#define WM8994_WSEQ_EOS14_MASK 0x0100 /* WSEQ_EOS14 */
+#define WM8994_WSEQ_EOS14_SHIFT 8 /* WSEQ_EOS14 */
+#define WM8994_WSEQ_EOS14_WIDTH 1 /* WSEQ_EOS14 */
+#define WM8994_WSEQ_DELAY14_MASK 0x000F /* WSEQ_DELAY14 - [3:0] */
+#define WM8994_WSEQ_DELAY14_SHIFT 0 /* WSEQ_DELAY14 - [3:0] */
+#define WM8994_WSEQ_DELAY14_WIDTH 4 /* WSEQ_DELAY14 - [3:0] */
+
+/*
+ * R12348 (0x303C) - Write Sequencer 60
+ */
+#define WM8994_WSEQ_ADDR15_MASK 0x3FFF /* WSEQ_ADDR15 - [13:0] */
+#define WM8994_WSEQ_ADDR15_SHIFT 0 /* WSEQ_ADDR15 - [13:0] */
+#define WM8994_WSEQ_ADDR15_WIDTH 14 /* WSEQ_ADDR15 - [13:0] */
+
+/*
+ * R12349 (0x303D) - Write Sequencer 61
+ */
+#define WM8994_WSEQ_DATA15_MASK 0x00FF /* WSEQ_DATA15 - [7:0] */
+#define WM8994_WSEQ_DATA15_SHIFT 0 /* WSEQ_DATA15 - [7:0] */
+#define WM8994_WSEQ_DATA15_WIDTH 8 /* WSEQ_DATA15 - [7:0] */
+
+/*
+ * R12350 (0x303E) - Write Sequencer 62
+ */
+#define WM8994_WSEQ_DATA_WIDTH15_MASK 0x0700 /* WSEQ_DATA_WIDTH15 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH15_SHIFT 8 /* WSEQ_DATA_WIDTH15 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH15_WIDTH 3 /* WSEQ_DATA_WIDTH15 - [10:8] */
+#define WM8994_WSEQ_DATA_START15_MASK 0x000F /* WSEQ_DATA_START15 - [3:0] */
+#define WM8994_WSEQ_DATA_START15_SHIFT 0 /* WSEQ_DATA_START15 - [3:0] */
+#define WM8994_WSEQ_DATA_START15_WIDTH 4 /* WSEQ_DATA_START15 - [3:0] */
+
+/*
+ * R12351 (0x303F) - Write Sequencer 63
+ */
+#define WM8994_WSEQ_EOS15 0x0100 /* WSEQ_EOS15 */
+#define WM8994_WSEQ_EOS15_MASK 0x0100 /* WSEQ_EOS15 */
+#define WM8994_WSEQ_EOS15_SHIFT 8 /* WSEQ_EOS15 */
+#define WM8994_WSEQ_EOS15_WIDTH 1 /* WSEQ_EOS15 */
+#define WM8994_WSEQ_DELAY15_MASK 0x000F /* WSEQ_DELAY15 - [3:0] */
+#define WM8994_WSEQ_DELAY15_SHIFT 0 /* WSEQ_DELAY15 - [3:0] */
+#define WM8994_WSEQ_DELAY15_WIDTH 4 /* WSEQ_DELAY15 - [3:0] */
+
+/*
+ * R12352 (0x3040) - Write Sequencer 64
+ */
+#define WM8994_WSEQ_ADDR16_MASK 0x3FFF /* WSEQ_ADDR16 - [13:0] */
+#define WM8994_WSEQ_ADDR16_SHIFT 0 /* WSEQ_ADDR16 - [13:0] */
+#define WM8994_WSEQ_ADDR16_WIDTH 14 /* WSEQ_ADDR16 - [13:0] */
+
+/*
+ * R12353 (0x3041) - Write Sequencer 65
+ */
+#define WM8994_WSEQ_DATA16_MASK 0x00FF /* WSEQ_DATA16 - [7:0] */
+#define WM8994_WSEQ_DATA16_SHIFT 0 /* WSEQ_DATA16 - [7:0] */
+#define WM8994_WSEQ_DATA16_WIDTH 8 /* WSEQ_DATA16 - [7:0] */
+
+/*
+ * R12354 (0x3042) - Write Sequencer 66
+ */
+#define WM8994_WSEQ_DATA_WIDTH16_MASK 0x0700 /* WSEQ_DATA_WIDTH16 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH16_SHIFT 8 /* WSEQ_DATA_WIDTH16 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH16_WIDTH 3 /* WSEQ_DATA_WIDTH16 - [10:8] */
+#define WM8994_WSEQ_DATA_START16_MASK 0x000F /* WSEQ_DATA_START16 - [3:0] */
+#define WM8994_WSEQ_DATA_START16_SHIFT 0 /* WSEQ_DATA_START16 - [3:0] */
+#define WM8994_WSEQ_DATA_START16_WIDTH 4 /* WSEQ_DATA_START16 - [3:0] */
+
+/*
+ * R12355 (0x3043) - Write Sequencer 67
+ */
+#define WM8994_WSEQ_EOS16 0x0100 /* WSEQ_EOS16 */
+#define WM8994_WSEQ_EOS16_MASK 0x0100 /* WSEQ_EOS16 */
+#define WM8994_WSEQ_EOS16_SHIFT 8 /* WSEQ_EOS16 */
+#define WM8994_WSEQ_EOS16_WIDTH 1 /* WSEQ_EOS16 */
+#define WM8994_WSEQ_DELAY16_MASK 0x000F /* WSEQ_DELAY16 - [3:0] */
+#define WM8994_WSEQ_DELAY16_SHIFT 0 /* WSEQ_DELAY16 - [3:0] */
+#define WM8994_WSEQ_DELAY16_WIDTH 4 /* WSEQ_DELAY16 - [3:0] */
+
+/*
+ * R12356 (0x3044) - Write Sequencer 68
+ */
+#define WM8994_WSEQ_ADDR17_MASK 0x3FFF /* WSEQ_ADDR17 - [13:0] */
+#define WM8994_WSEQ_ADDR17_SHIFT 0 /* WSEQ_ADDR17 - [13:0] */
+#define WM8994_WSEQ_ADDR17_WIDTH 14 /* WSEQ_ADDR17 - [13:0] */
+
+/*
+ * R12357 (0x3045) - Write Sequencer 69
+ */
+#define WM8994_WSEQ_DATA17_MASK 0x00FF /* WSEQ_DATA17 - [7:0] */
+#define WM8994_WSEQ_DATA17_SHIFT 0 /* WSEQ_DATA17 - [7:0] */
+#define WM8994_WSEQ_DATA17_WIDTH 8 /* WSEQ_DATA17 - [7:0] */
+
+/*
+ * R12358 (0x3046) - Write Sequencer 70
+ */
+#define WM8994_WSEQ_DATA_WIDTH17_MASK 0x0700 /* WSEQ_DATA_WIDTH17 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH17_SHIFT 8 /* WSEQ_DATA_WIDTH17 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH17_WIDTH 3 /* WSEQ_DATA_WIDTH17 - [10:8] */
+#define WM8994_WSEQ_DATA_START17_MASK 0x000F /* WSEQ_DATA_START17 - [3:0] */
+#define WM8994_WSEQ_DATA_START17_SHIFT 0 /* WSEQ_DATA_START17 - [3:0] */
+#define WM8994_WSEQ_DATA_START17_WIDTH 4 /* WSEQ_DATA_START17 - [3:0] */
+
+/*
+ * R12359 (0x3047) - Write Sequencer 71
+ */
+#define WM8994_WSEQ_EOS17 0x0100 /* WSEQ_EOS17 */
+#define WM8994_WSEQ_EOS17_MASK 0x0100 /* WSEQ_EOS17 */
+#define WM8994_WSEQ_EOS17_SHIFT 8 /* WSEQ_EOS17 */
+#define WM8994_WSEQ_EOS17_WIDTH 1 /* WSEQ_EOS17 */
+#define WM8994_WSEQ_DELAY17_MASK 0x000F /* WSEQ_DELAY17 - [3:0] */
+#define WM8994_WSEQ_DELAY17_SHIFT 0 /* WSEQ_DELAY17 - [3:0] */
+#define WM8994_WSEQ_DELAY17_WIDTH 4 /* WSEQ_DELAY17 - [3:0] */
+
+/*
+ * R12360 (0x3048) - Write Sequencer 72
+ */
+#define WM8994_WSEQ_ADDR18_MASK 0x3FFF /* WSEQ_ADDR18 - [13:0] */
+#define WM8994_WSEQ_ADDR18_SHIFT 0 /* WSEQ_ADDR18 - [13:0] */
+#define WM8994_WSEQ_ADDR18_WIDTH 14 /* WSEQ_ADDR18 - [13:0] */
+
+/*
+ * R12361 (0x3049) - Write Sequencer 73
+ */
+#define WM8994_WSEQ_DATA18_MASK 0x00FF /* WSEQ_DATA18 - [7:0] */
+#define WM8994_WSEQ_DATA18_SHIFT 0 /* WSEQ_DATA18 - [7:0] */
+#define WM8994_WSEQ_DATA18_WIDTH 8 /* WSEQ_DATA18 - [7:0] */
+
+/*
+ * R12362 (0x304A) - Write Sequencer 74
+ */
+#define WM8994_WSEQ_DATA_WIDTH18_MASK 0x0700 /* WSEQ_DATA_WIDTH18 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH18_SHIFT 8 /* WSEQ_DATA_WIDTH18 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH18_WIDTH 3 /* WSEQ_DATA_WIDTH18 - [10:8] */
+#define WM8994_WSEQ_DATA_START18_MASK 0x000F /* WSEQ_DATA_START18 - [3:0] */
+#define WM8994_WSEQ_DATA_START18_SHIFT 0 /* WSEQ_DATA_START18 - [3:0] */
+#define WM8994_WSEQ_DATA_START18_WIDTH 4 /* WSEQ_DATA_START18 - [3:0] */
+
+/*
+ * R12363 (0x304B) - Write Sequencer 75
+ */
+#define WM8994_WSEQ_EOS18 0x0100 /* WSEQ_EOS18 */
+#define WM8994_WSEQ_EOS18_MASK 0x0100 /* WSEQ_EOS18 */
+#define WM8994_WSEQ_EOS18_SHIFT 8 /* WSEQ_EOS18 */
+#define WM8994_WSEQ_EOS18_WIDTH 1 /* WSEQ_EOS18 */
+#define WM8994_WSEQ_DELAY18_MASK 0x000F /* WSEQ_DELAY18 - [3:0] */
+#define WM8994_WSEQ_DELAY18_SHIFT 0 /* WSEQ_DELAY18 - [3:0] */
+#define WM8994_WSEQ_DELAY18_WIDTH 4 /* WSEQ_DELAY18 - [3:0] */
+
+/*
+ * R12364 (0x304C) - Write Sequencer 76
+ */
+#define WM8994_WSEQ_ADDR19_MASK 0x3FFF /* WSEQ_ADDR19 - [13:0] */
+#define WM8994_WSEQ_ADDR19_SHIFT 0 /* WSEQ_ADDR19 - [13:0] */
+#define WM8994_WSEQ_ADDR19_WIDTH 14 /* WSEQ_ADDR19 - [13:0] */
+
+/*
+ * R12365 (0x304D) - Write Sequencer 77
+ */
+#define WM8994_WSEQ_DATA19_MASK 0x00FF /* WSEQ_DATA19 - [7:0] */
+#define WM8994_WSEQ_DATA19_SHIFT 0 /* WSEQ_DATA19 - [7:0] */
+#define WM8994_WSEQ_DATA19_WIDTH 8 /* WSEQ_DATA19 - [7:0] */
+
+/*
+ * R12366 (0x304E) - Write Sequencer 78
+ */
+#define WM8994_WSEQ_DATA_WIDTH19_MASK 0x0700 /* WSEQ_DATA_WIDTH19 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH19_SHIFT 8 /* WSEQ_DATA_WIDTH19 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH19_WIDTH 3 /* WSEQ_DATA_WIDTH19 - [10:8] */
+#define WM8994_WSEQ_DATA_START19_MASK 0x000F /* WSEQ_DATA_START19 - [3:0] */
+#define WM8994_WSEQ_DATA_START19_SHIFT 0 /* WSEQ_DATA_START19 - [3:0] */
+#define WM8994_WSEQ_DATA_START19_WIDTH 4 /* WSEQ_DATA_START19 - [3:0] */
+
+/*
+ * R12367 (0x304F) - Write Sequencer 79
+ */
+#define WM8994_WSEQ_EOS19 0x0100 /* WSEQ_EOS19 */
+#define WM8994_WSEQ_EOS19_MASK 0x0100 /* WSEQ_EOS19 */
+#define WM8994_WSEQ_EOS19_SHIFT 8 /* WSEQ_EOS19 */
+#define WM8994_WSEQ_EOS19_WIDTH 1 /* WSEQ_EOS19 */
+#define WM8994_WSEQ_DELAY19_MASK 0x000F /* WSEQ_DELAY19 - [3:0] */
+#define WM8994_WSEQ_DELAY19_SHIFT 0 /* WSEQ_DELAY19 - [3:0] */
+#define WM8994_WSEQ_DELAY19_WIDTH 4 /* WSEQ_DELAY19 - [3:0] */
+
+/*
+ * R12368 (0x3050) - Write Sequencer 80
+ */
+#define WM8994_WSEQ_ADDR20_MASK 0x3FFF /* WSEQ_ADDR20 - [13:0] */
+#define WM8994_WSEQ_ADDR20_SHIFT 0 /* WSEQ_ADDR20 - [13:0] */
+#define WM8994_WSEQ_ADDR20_WIDTH 14 /* WSEQ_ADDR20 - [13:0] */
+
+/*
+ * R12369 (0x3051) - Write Sequencer 81
+ */
+#define WM8994_WSEQ_DATA20_MASK 0x00FF /* WSEQ_DATA20 - [7:0] */
+#define WM8994_WSEQ_DATA20_SHIFT 0 /* WSEQ_DATA20 - [7:0] */
+#define WM8994_WSEQ_DATA20_WIDTH 8 /* WSEQ_DATA20 - [7:0] */
+
+/*
+ * R12370 (0x3052) - Write Sequencer 82
+ */
+#define WM8994_WSEQ_DATA_WIDTH20_MASK 0x0700 /* WSEQ_DATA_WIDTH20 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH20_SHIFT 8 /* WSEQ_DATA_WIDTH20 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH20_WIDTH 3 /* WSEQ_DATA_WIDTH20 - [10:8] */
+#define WM8994_WSEQ_DATA_START20_MASK 0x000F /* WSEQ_DATA_START20 - [3:0] */
+#define WM8994_WSEQ_DATA_START20_SHIFT 0 /* WSEQ_DATA_START20 - [3:0] */
+#define WM8994_WSEQ_DATA_START20_WIDTH 4 /* WSEQ_DATA_START20 - [3:0] */
+
+/*
+ * R12371 (0x3053) - Write Sequencer 83
+ */
+#define WM8994_WSEQ_EOS20 0x0100 /* WSEQ_EOS20 */
+#define WM8994_WSEQ_EOS20_MASK 0x0100 /* WSEQ_EOS20 */
+#define WM8994_WSEQ_EOS20_SHIFT 8 /* WSEQ_EOS20 */
+#define WM8994_WSEQ_EOS20_WIDTH 1 /* WSEQ_EOS20 */
+#define WM8994_WSEQ_DELAY20_MASK 0x000F /* WSEQ_DELAY20 - [3:0] */
+#define WM8994_WSEQ_DELAY20_SHIFT 0 /* WSEQ_DELAY20 - [3:0] */
+#define WM8994_WSEQ_DELAY20_WIDTH 4 /* WSEQ_DELAY20 - [3:0] */
+
+/*
+ * R12372 (0x3054) - Write Sequencer 84
+ */
+#define WM8994_WSEQ_ADDR21_MASK 0x3FFF /* WSEQ_ADDR21 - [13:0] */
+#define WM8994_WSEQ_ADDR21_SHIFT 0 /* WSEQ_ADDR21 - [13:0] */
+#define WM8994_WSEQ_ADDR21_WIDTH 14 /* WSEQ_ADDR21 - [13:0] */
+
+/*
+ * R12373 (0x3055) - Write Sequencer 85
+ */
+#define WM8994_WSEQ_DATA21_MASK 0x00FF /* WSEQ_DATA21 - [7:0] */
+#define WM8994_WSEQ_DATA21_SHIFT 0 /* WSEQ_DATA21 - [7:0] */
+#define WM8994_WSEQ_DATA21_WIDTH 8 /* WSEQ_DATA21 - [7:0] */
+
+/*
+ * R12374 (0x3056) - Write Sequencer 86
+ */
+#define WM8994_WSEQ_DATA_WIDTH21_MASK 0x0700 /* WSEQ_DATA_WIDTH21 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH21_SHIFT 8 /* WSEQ_DATA_WIDTH21 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH21_WIDTH 3 /* WSEQ_DATA_WIDTH21 - [10:8] */
+#define WM8994_WSEQ_DATA_START21_MASK 0x000F /* WSEQ_DATA_START21 - [3:0] */
+#define WM8994_WSEQ_DATA_START21_SHIFT 0 /* WSEQ_DATA_START21 - [3:0] */
+#define WM8994_WSEQ_DATA_START21_WIDTH 4 /* WSEQ_DATA_START21 - [3:0] */
+
+/*
+ * R12375 (0x3057) - Write Sequencer 87
+ */
+#define WM8994_WSEQ_EOS21 0x0100 /* WSEQ_EOS21 */
+#define WM8994_WSEQ_EOS21_MASK 0x0100 /* WSEQ_EOS21 */
+#define WM8994_WSEQ_EOS21_SHIFT 8 /* WSEQ_EOS21 */
+#define WM8994_WSEQ_EOS21_WIDTH 1 /* WSEQ_EOS21 */
+#define WM8994_WSEQ_DELAY21_MASK 0x000F /* WSEQ_DELAY21 - [3:0] */
+#define WM8994_WSEQ_DELAY21_SHIFT 0 /* WSEQ_DELAY21 - [3:0] */
+#define WM8994_WSEQ_DELAY21_WIDTH 4 /* WSEQ_DELAY21 - [3:0] */
+
+/*
+ * R12376 (0x3058) - Write Sequencer 88
+ */
+#define WM8994_WSEQ_ADDR22_MASK 0x3FFF /* WSEQ_ADDR22 - [13:0] */
+#define WM8994_WSEQ_ADDR22_SHIFT 0 /* WSEQ_ADDR22 - [13:0] */
+#define WM8994_WSEQ_ADDR22_WIDTH 14 /* WSEQ_ADDR22 - [13:0] */
+
+/*
+ * R12377 (0x3059) - Write Sequencer 89
+ */
+#define WM8994_WSEQ_DATA22_MASK 0x00FF /* WSEQ_DATA22 - [7:0] */
+#define WM8994_WSEQ_DATA22_SHIFT 0 /* WSEQ_DATA22 - [7:0] */
+#define WM8994_WSEQ_DATA22_WIDTH 8 /* WSEQ_DATA22 - [7:0] */
+
+/*
+ * R12378 (0x305A) - Write Sequencer 90
+ */
+#define WM8994_WSEQ_DATA_WIDTH22_MASK 0x0700 /* WSEQ_DATA_WIDTH22 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH22_SHIFT 8 /* WSEQ_DATA_WIDTH22 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH22_WIDTH 3 /* WSEQ_DATA_WIDTH22 - [10:8] */
+#define WM8994_WSEQ_DATA_START22_MASK 0x000F /* WSEQ_DATA_START22 - [3:0] */
+#define WM8994_WSEQ_DATA_START22_SHIFT 0 /* WSEQ_DATA_START22 - [3:0] */
+#define WM8994_WSEQ_DATA_START22_WIDTH 4 /* WSEQ_DATA_START22 - [3:0] */
+
+/*
+ * R12379 (0x305B) - Write Sequencer 91
+ */
+#define WM8994_WSEQ_EOS22 0x0100 /* WSEQ_EOS22 */
+#define WM8994_WSEQ_EOS22_MASK 0x0100 /* WSEQ_EOS22 */
+#define WM8994_WSEQ_EOS22_SHIFT 8 /* WSEQ_EOS22 */
+#define WM8994_WSEQ_EOS22_WIDTH 1 /* WSEQ_EOS22 */
+#define WM8994_WSEQ_DELAY22_MASK 0x000F /* WSEQ_DELAY22 - [3:0] */
+#define WM8994_WSEQ_DELAY22_SHIFT 0 /* WSEQ_DELAY22 - [3:0] */
+#define WM8994_WSEQ_DELAY22_WIDTH 4 /* WSEQ_DELAY22 - [3:0] */
+
+/*
+ * R12380 (0x305C) - Write Sequencer 92
+ */
+#define WM8994_WSEQ_ADDR23_MASK 0x3FFF /* WSEQ_ADDR23 - [13:0] */
+#define WM8994_WSEQ_ADDR23_SHIFT 0 /* WSEQ_ADDR23 - [13:0] */
+#define WM8994_WSEQ_ADDR23_WIDTH 14 /* WSEQ_ADDR23 - [13:0] */
+
+/*
+ * R12381 (0x305D) - Write Sequencer 93
+ */
+#define WM8994_WSEQ_DATA23_MASK 0x00FF /* WSEQ_DATA23 - [7:0] */
+#define WM8994_WSEQ_DATA23_SHIFT 0 /* WSEQ_DATA23 - [7:0] */
+#define WM8994_WSEQ_DATA23_WIDTH 8 /* WSEQ_DATA23 - [7:0] */
+
+/*
+ * R12382 (0x305E) - Write Sequencer 94
+ */
+#define WM8994_WSEQ_DATA_WIDTH23_MASK 0x0700 /* WSEQ_DATA_WIDTH23 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH23_SHIFT 8 /* WSEQ_DATA_WIDTH23 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH23_WIDTH 3 /* WSEQ_DATA_WIDTH23 - [10:8] */
+#define WM8994_WSEQ_DATA_START23_MASK 0x000F /* WSEQ_DATA_START23 - [3:0] */
+#define WM8994_WSEQ_DATA_START23_SHIFT 0 /* WSEQ_DATA_START23 - [3:0] */
+#define WM8994_WSEQ_DATA_START23_WIDTH 4 /* WSEQ_DATA_START23 - [3:0] */
+
+/*
+ * R12383 (0x305F) - Write Sequencer 95
+ */
+#define WM8994_WSEQ_EOS23 0x0100 /* WSEQ_EOS23 */
+#define WM8994_WSEQ_EOS23_MASK 0x0100 /* WSEQ_EOS23 */
+#define WM8994_WSEQ_EOS23_SHIFT 8 /* WSEQ_EOS23 */
+#define WM8994_WSEQ_EOS23_WIDTH 1 /* WSEQ_EOS23 */
+#define WM8994_WSEQ_DELAY23_MASK 0x000F /* WSEQ_DELAY23 - [3:0] */
+#define WM8994_WSEQ_DELAY23_SHIFT 0 /* WSEQ_DELAY23 - [3:0] */
+#define WM8994_WSEQ_DELAY23_WIDTH 4 /* WSEQ_DELAY23 - [3:0] */
+
+/*
+ * R12384 (0x3060) - Write Sequencer 96
+ */
+#define WM8994_WSEQ_ADDR24_MASK 0x3FFF /* WSEQ_ADDR24 - [13:0] */
+#define WM8994_WSEQ_ADDR24_SHIFT 0 /* WSEQ_ADDR24 - [13:0] */
+#define WM8994_WSEQ_ADDR24_WIDTH 14 /* WSEQ_ADDR24 - [13:0] */
+
+/*
+ * R12385 (0x3061) - Write Sequencer 97
+ */
+#define WM8994_WSEQ_DATA24_MASK 0x00FF /* WSEQ_DATA24 - [7:0] */
+#define WM8994_WSEQ_DATA24_SHIFT 0 /* WSEQ_DATA24 - [7:0] */
+#define WM8994_WSEQ_DATA24_WIDTH 8 /* WSEQ_DATA24 - [7:0] */
+
+/*
+ * R12386 (0x3062) - Write Sequencer 98
+ */
+#define WM8994_WSEQ_DATA_WIDTH24_MASK 0x0700 /* WSEQ_DATA_WIDTH24 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH24_SHIFT 8 /* WSEQ_DATA_WIDTH24 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH24_WIDTH 3 /* WSEQ_DATA_WIDTH24 - [10:8] */
+#define WM8994_WSEQ_DATA_START24_MASK 0x000F /* WSEQ_DATA_START24 - [3:0] */
+#define WM8994_WSEQ_DATA_START24_SHIFT 0 /* WSEQ_DATA_START24 - [3:0] */
+#define WM8994_WSEQ_DATA_START24_WIDTH 4 /* WSEQ_DATA_START24 - [3:0] */
+
+/*
+ * R12387 (0x3063) - Write Sequencer 99
+ */
+#define WM8994_WSEQ_EOS24 0x0100 /* WSEQ_EOS24 */
+#define WM8994_WSEQ_EOS24_MASK 0x0100 /* WSEQ_EOS24 */
+#define WM8994_WSEQ_EOS24_SHIFT 8 /* WSEQ_EOS24 */
+#define WM8994_WSEQ_EOS24_WIDTH 1 /* WSEQ_EOS24 */
+#define WM8994_WSEQ_DELAY24_MASK 0x000F /* WSEQ_DELAY24 - [3:0] */
+#define WM8994_WSEQ_DELAY24_SHIFT 0 /* WSEQ_DELAY24 - [3:0] */
+#define WM8994_WSEQ_DELAY24_WIDTH 4 /* WSEQ_DELAY24 - [3:0] */
+
+/*
+ * R12388 (0x3064) - Write Sequencer 100
+ */
+#define WM8994_WSEQ_ADDR25_MASK 0x3FFF /* WSEQ_ADDR25 - [13:0] */
+#define WM8994_WSEQ_ADDR25_SHIFT 0 /* WSEQ_ADDR25 - [13:0] */
+#define WM8994_WSEQ_ADDR25_WIDTH 14 /* WSEQ_ADDR25 - [13:0] */
+
+/*
+ * R12389 (0x3065) - Write Sequencer 101
+ */
+#define WM8994_WSEQ_DATA25_MASK 0x00FF /* WSEQ_DATA25 - [7:0] */
+#define WM8994_WSEQ_DATA25_SHIFT 0 /* WSEQ_DATA25 - [7:0] */
+#define WM8994_WSEQ_DATA25_WIDTH 8 /* WSEQ_DATA25 - [7:0] */
+
+/*
+ * R12390 (0x3066) - Write Sequencer 102
+ */
+#define WM8994_WSEQ_DATA_WIDTH25_MASK 0x0700 /* WSEQ_DATA_WIDTH25 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH25_SHIFT 8 /* WSEQ_DATA_WIDTH25 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH25_WIDTH 3 /* WSEQ_DATA_WIDTH25 - [10:8] */
+#define WM8994_WSEQ_DATA_START25_MASK 0x000F /* WSEQ_DATA_START25 - [3:0] */
+#define WM8994_WSEQ_DATA_START25_SHIFT 0 /* WSEQ_DATA_START25 - [3:0] */
+#define WM8994_WSEQ_DATA_START25_WIDTH 4 /* WSEQ_DATA_START25 - [3:0] */
+
+/*
+ * R12391 (0x3067) - Write Sequencer 103
+ */
+#define WM8994_WSEQ_EOS25 0x0100 /* WSEQ_EOS25 */
+#define WM8994_WSEQ_EOS25_MASK 0x0100 /* WSEQ_EOS25 */
+#define WM8994_WSEQ_EOS25_SHIFT 8 /* WSEQ_EOS25 */
+#define WM8994_WSEQ_EOS25_WIDTH 1 /* WSEQ_EOS25 */
+#define WM8994_WSEQ_DELAY25_MASK 0x000F /* WSEQ_DELAY25 - [3:0] */
+#define WM8994_WSEQ_DELAY25_SHIFT 0 /* WSEQ_DELAY25 - [3:0] */
+#define WM8994_WSEQ_DELAY25_WIDTH 4 /* WSEQ_DELAY25 - [3:0] */
+
+/*
+ * R12392 (0x3068) - Write Sequencer 104
+ */
+#define WM8994_WSEQ_ADDR26_MASK 0x3FFF /* WSEQ_ADDR26 - [13:0] */
+#define WM8994_WSEQ_ADDR26_SHIFT 0 /* WSEQ_ADDR26 - [13:0] */
+#define WM8994_WSEQ_ADDR26_WIDTH 14 /* WSEQ_ADDR26 - [13:0] */
+
+/*
+ * R12393 (0x3069) - Write Sequencer 105
+ */
+#define WM8994_WSEQ_DATA26_MASK 0x00FF /* WSEQ_DATA26 - [7:0] */
+#define WM8994_WSEQ_DATA26_SHIFT 0 /* WSEQ_DATA26 - [7:0] */
+#define WM8994_WSEQ_DATA26_WIDTH 8 /* WSEQ_DATA26 - [7:0] */
+
+/*
+ * R12394 (0x306A) - Write Sequencer 106
+ */
+#define WM8994_WSEQ_DATA_WIDTH26_MASK 0x0700 /* WSEQ_DATA_WIDTH26 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH26_SHIFT 8 /* WSEQ_DATA_WIDTH26 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH26_WIDTH 3 /* WSEQ_DATA_WIDTH26 - [10:8] */
+#define WM8994_WSEQ_DATA_START26_MASK 0x000F /* WSEQ_DATA_START26 - [3:0] */
+#define WM8994_WSEQ_DATA_START26_SHIFT 0 /* WSEQ_DATA_START26 - [3:0] */
+#define WM8994_WSEQ_DATA_START26_WIDTH 4 /* WSEQ_DATA_START26 - [3:0] */
+
+/*
+ * R12395 (0x306B) - Write Sequencer 107
+ */
+#define WM8994_WSEQ_EOS26 0x0100 /* WSEQ_EOS26 */
+#define WM8994_WSEQ_EOS26_MASK 0x0100 /* WSEQ_EOS26 */
+#define WM8994_WSEQ_EOS26_SHIFT 8 /* WSEQ_EOS26 */
+#define WM8994_WSEQ_EOS26_WIDTH 1 /* WSEQ_EOS26 */
+#define WM8994_WSEQ_DELAY26_MASK 0x000F /* WSEQ_DELAY26 - [3:0] */
+#define WM8994_WSEQ_DELAY26_SHIFT 0 /* WSEQ_DELAY26 - [3:0] */
+#define WM8994_WSEQ_DELAY26_WIDTH 4 /* WSEQ_DELAY26 - [3:0] */
+
+/*
+ * R12396 (0x306C) - Write Sequencer 108
+ */
+#define WM8994_WSEQ_ADDR27_MASK 0x3FFF /* WSEQ_ADDR27 - [13:0] */
+#define WM8994_WSEQ_ADDR27_SHIFT 0 /* WSEQ_ADDR27 - [13:0] */
+#define WM8994_WSEQ_ADDR27_WIDTH 14 /* WSEQ_ADDR27 - [13:0] */
+
+/*
+ * R12397 (0x306D) - Write Sequencer 109
+ */
+#define WM8994_WSEQ_DATA27_MASK 0x00FF /* WSEQ_DATA27 - [7:0] */
+#define WM8994_WSEQ_DATA27_SHIFT 0 /* WSEQ_DATA27 - [7:0] */
+#define WM8994_WSEQ_DATA27_WIDTH 8 /* WSEQ_DATA27 - [7:0] */
+
+/*
+ * R12398 (0x306E) - Write Sequencer 110
+ */
+#define WM8994_WSEQ_DATA_WIDTH27_MASK 0x0700 /* WSEQ_DATA_WIDTH27 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH27_SHIFT 8 /* WSEQ_DATA_WIDTH27 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH27_WIDTH 3 /* WSEQ_DATA_WIDTH27 - [10:8] */
+#define WM8994_WSEQ_DATA_START27_MASK 0x000F /* WSEQ_DATA_START27 - [3:0] */
+#define WM8994_WSEQ_DATA_START27_SHIFT 0 /* WSEQ_DATA_START27 - [3:0] */
+#define WM8994_WSEQ_DATA_START27_WIDTH 4 /* WSEQ_DATA_START27 - [3:0] */
+
+/*
+ * R12399 (0x306F) - Write Sequencer 111
+ */
+#define WM8994_WSEQ_EOS27 0x0100 /* WSEQ_EOS27 */
+#define WM8994_WSEQ_EOS27_MASK 0x0100 /* WSEQ_EOS27 */
+#define WM8994_WSEQ_EOS27_SHIFT 8 /* WSEQ_EOS27 */
+#define WM8994_WSEQ_EOS27_WIDTH 1 /* WSEQ_EOS27 */
+#define WM8994_WSEQ_DELAY27_MASK 0x000F /* WSEQ_DELAY27 - [3:0] */
+#define WM8994_WSEQ_DELAY27_SHIFT 0 /* WSEQ_DELAY27 - [3:0] */
+#define WM8994_WSEQ_DELAY27_WIDTH 4 /* WSEQ_DELAY27 - [3:0] */
+
+/*
+ * R12400 (0x3070) - Write Sequencer 112
+ */
+#define WM8994_WSEQ_ADDR28_MASK 0x3FFF /* WSEQ_ADDR28 - [13:0] */
+#define WM8994_WSEQ_ADDR28_SHIFT 0 /* WSEQ_ADDR28 - [13:0] */
+#define WM8994_WSEQ_ADDR28_WIDTH 14 /* WSEQ_ADDR28 - [13:0] */
+
+/*
+ * R12401 (0x3071) - Write Sequencer 113
+ */
+#define WM8994_WSEQ_DATA28_MASK 0x00FF /* WSEQ_DATA28 - [7:0] */
+#define WM8994_WSEQ_DATA28_SHIFT 0 /* WSEQ_DATA28 - [7:0] */
+#define WM8994_WSEQ_DATA28_WIDTH 8 /* WSEQ_DATA28 - [7:0] */
+
+/*
+ * R12402 (0x3072) - Write Sequencer 114
+ */
+#define WM8994_WSEQ_DATA_WIDTH28_MASK 0x0700 /* WSEQ_DATA_WIDTH28 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH28_SHIFT 8 /* WSEQ_DATA_WIDTH28 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH28_WIDTH 3 /* WSEQ_DATA_WIDTH28 - [10:8] */
+#define WM8994_WSEQ_DATA_START28_MASK 0x000F /* WSEQ_DATA_START28 - [3:0] */
+#define WM8994_WSEQ_DATA_START28_SHIFT 0 /* WSEQ_DATA_START28 - [3:0] */
+#define WM8994_WSEQ_DATA_START28_WIDTH 4 /* WSEQ_DATA_START28 - [3:0] */
+
+/*
+ * R12403 (0x3073) - Write Sequencer 115
+ */
+#define WM8994_WSEQ_EOS28 0x0100 /* WSEQ_EOS28 */
+#define WM8994_WSEQ_EOS28_MASK 0x0100 /* WSEQ_EOS28 */
+#define WM8994_WSEQ_EOS28_SHIFT 8 /* WSEQ_EOS28 */
+#define WM8994_WSEQ_EOS28_WIDTH 1 /* WSEQ_EOS28 */
+#define WM8994_WSEQ_DELAY28_MASK 0x000F /* WSEQ_DELAY28 - [3:0] */
+#define WM8994_WSEQ_DELAY28_SHIFT 0 /* WSEQ_DELAY28 - [3:0] */
+#define WM8994_WSEQ_DELAY28_WIDTH 4 /* WSEQ_DELAY28 - [3:0] */
+
+/*
+ * R12404 (0x3074) - Write Sequencer 116
+ */
+#define WM8994_WSEQ_ADDR29_MASK 0x3FFF /* WSEQ_ADDR29 - [13:0] */
+#define WM8994_WSEQ_ADDR29_SHIFT 0 /* WSEQ_ADDR29 - [13:0] */
+#define WM8994_WSEQ_ADDR29_WIDTH 14 /* WSEQ_ADDR29 - [13:0] */
+
+/*
+ * R12405 (0x3075) - Write Sequencer 117
+ */
+#define WM8994_WSEQ_DATA29_MASK 0x00FF /* WSEQ_DATA29 - [7:0] */
+#define WM8994_WSEQ_DATA29_SHIFT 0 /* WSEQ_DATA29 - [7:0] */
+#define WM8994_WSEQ_DATA29_WIDTH 8 /* WSEQ_DATA29 - [7:0] */
+
+/*
+ * R12406 (0x3076) - Write Sequencer 118
+ */
+#define WM8994_WSEQ_DATA_WIDTH29_MASK 0x0700 /* WSEQ_DATA_WIDTH29 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH29_SHIFT 8 /* WSEQ_DATA_WIDTH29 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH29_WIDTH 3 /* WSEQ_DATA_WIDTH29 - [10:8] */
+#define WM8994_WSEQ_DATA_START29_MASK 0x000F /* WSEQ_DATA_START29 - [3:0] */
+#define WM8994_WSEQ_DATA_START29_SHIFT 0 /* WSEQ_DATA_START29 - [3:0] */
+#define WM8994_WSEQ_DATA_START29_WIDTH 4 /* WSEQ_DATA_START29 - [3:0] */
+
+/*
+ * R12407 (0x3077) - Write Sequencer 119
+ */
+#define WM8994_WSEQ_EOS29 0x0100 /* WSEQ_EOS29 */
+#define WM8994_WSEQ_EOS29_MASK 0x0100 /* WSEQ_EOS29 */
+#define WM8994_WSEQ_EOS29_SHIFT 8 /* WSEQ_EOS29 */
+#define WM8994_WSEQ_EOS29_WIDTH 1 /* WSEQ_EOS29 */
+#define WM8994_WSEQ_DELAY29_MASK 0x000F /* WSEQ_DELAY29 - [3:0] */
+#define WM8994_WSEQ_DELAY29_SHIFT 0 /* WSEQ_DELAY29 - [3:0] */
+#define WM8994_WSEQ_DELAY29_WIDTH 4 /* WSEQ_DELAY29 - [3:0] */
+
+/*
+ * R12408 (0x3078) - Write Sequencer 120
+ */
+#define WM8994_WSEQ_ADDR30_MASK 0x3FFF /* WSEQ_ADDR30 - [13:0] */
+#define WM8994_WSEQ_ADDR30_SHIFT 0 /* WSEQ_ADDR30 - [13:0] */
+#define WM8994_WSEQ_ADDR30_WIDTH 14 /* WSEQ_ADDR30 - [13:0] */
+
+/*
+ * R12409 (0x3079) - Write Sequencer 121
+ */
+#define WM8994_WSEQ_DATA30_MASK 0x00FF /* WSEQ_DATA30 - [7:0] */
+#define WM8994_WSEQ_DATA30_SHIFT 0 /* WSEQ_DATA30 - [7:0] */
+#define WM8994_WSEQ_DATA30_WIDTH 8 /* WSEQ_DATA30 - [7:0] */
+
+/*
+ * R12410 (0x307A) - Write Sequencer 122
+ */
+#define WM8994_WSEQ_DATA_WIDTH30_MASK 0x0700 /* WSEQ_DATA_WIDTH30 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH30_SHIFT 8 /* WSEQ_DATA_WIDTH30 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH30_WIDTH 3 /* WSEQ_DATA_WIDTH30 - [10:8] */
+#define WM8994_WSEQ_DATA_START30_MASK 0x000F /* WSEQ_DATA_START30 - [3:0] */
+#define WM8994_WSEQ_DATA_START30_SHIFT 0 /* WSEQ_DATA_START30 - [3:0] */
+#define WM8994_WSEQ_DATA_START30_WIDTH 4 /* WSEQ_DATA_START30 - [3:0] */
+
+/*
+ * R12411 (0x307B) - Write Sequencer 123
+ */
+#define WM8994_WSEQ_EOS30 0x0100 /* WSEQ_EOS30 */
+#define WM8994_WSEQ_EOS30_MASK 0x0100 /* WSEQ_EOS30 */
+#define WM8994_WSEQ_EOS30_SHIFT 8 /* WSEQ_EOS30 */
+#define WM8994_WSEQ_EOS30_WIDTH 1 /* WSEQ_EOS30 */
+#define WM8994_WSEQ_DELAY30_MASK 0x000F /* WSEQ_DELAY30 - [3:0] */
+#define WM8994_WSEQ_DELAY30_SHIFT 0 /* WSEQ_DELAY30 - [3:0] */
+#define WM8994_WSEQ_DELAY30_WIDTH 4 /* WSEQ_DELAY30 - [3:0] */
+
+/*
+ * R12412 (0x307C) - Write Sequencer 124
+ */
+#define WM8994_WSEQ_ADDR31_MASK 0x3FFF /* WSEQ_ADDR31 - [13:0] */
+#define WM8994_WSEQ_ADDR31_SHIFT 0 /* WSEQ_ADDR31 - [13:0] */
+#define WM8994_WSEQ_ADDR31_WIDTH 14 /* WSEQ_ADDR31 - [13:0] */
+
+/*
+ * R12413 (0x307D) - Write Sequencer 125
+ */
+#define WM8994_WSEQ_DATA31_MASK 0x00FF /* WSEQ_DATA31 - [7:0] */
+#define WM8994_WSEQ_DATA31_SHIFT 0 /* WSEQ_DATA31 - [7:0] */
+#define WM8994_WSEQ_DATA31_WIDTH 8 /* WSEQ_DATA31 - [7:0] */
+
+/*
+ * R12414 (0x307E) - Write Sequencer 126
+ */
+#define WM8994_WSEQ_DATA_WIDTH31_MASK 0x0700 /* WSEQ_DATA_WIDTH31 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH31_SHIFT 8 /* WSEQ_DATA_WIDTH31 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH31_WIDTH 3 /* WSEQ_DATA_WIDTH31 - [10:8] */
+#define WM8994_WSEQ_DATA_START31_MASK 0x000F /* WSEQ_DATA_START31 - [3:0] */
+#define WM8994_WSEQ_DATA_START31_SHIFT 0 /* WSEQ_DATA_START31 - [3:0] */
+#define WM8994_WSEQ_DATA_START31_WIDTH 4 /* WSEQ_DATA_START31 - [3:0] */
+
+/*
+ * R12415 (0x307F) - Write Sequencer 127
+ */
+#define WM8994_WSEQ_EOS31 0x0100 /* WSEQ_EOS31 */
+#define WM8994_WSEQ_EOS31_MASK 0x0100 /* WSEQ_EOS31 */
+#define WM8994_WSEQ_EOS31_SHIFT 8 /* WSEQ_EOS31 */
+#define WM8994_WSEQ_EOS31_WIDTH 1 /* WSEQ_EOS31 */
+#define WM8994_WSEQ_DELAY31_MASK 0x000F /* WSEQ_DELAY31 - [3:0] */
+#define WM8994_WSEQ_DELAY31_SHIFT 0 /* WSEQ_DELAY31 - [3:0] */
+#define WM8994_WSEQ_DELAY31_WIDTH 4 /* WSEQ_DELAY31 - [3:0] */
+
+/*
+ * R12416 (0x3080) - Write Sequencer 128
+ */
+#define WM8994_WSEQ_ADDR32_MASK 0x3FFF /* WSEQ_ADDR32 - [13:0] */
+#define WM8994_WSEQ_ADDR32_SHIFT 0 /* WSEQ_ADDR32 - [13:0] */
+#define WM8994_WSEQ_ADDR32_WIDTH 14 /* WSEQ_ADDR32 - [13:0] */
+
+/*
+ * R12417 (0x3081) - Write Sequencer 129
+ */
+#define WM8994_WSEQ_DATA32_MASK 0x00FF /* WSEQ_DATA32 - [7:0] */
+#define WM8994_WSEQ_DATA32_SHIFT 0 /* WSEQ_DATA32 - [7:0] */
+#define WM8994_WSEQ_DATA32_WIDTH 8 /* WSEQ_DATA32 - [7:0] */
+
+/*
+ * R12418 (0x3082) - Write Sequencer 130
+ */
+#define WM8994_WSEQ_DATA_WIDTH32_MASK 0x0700 /* WSEQ_DATA_WIDTH32 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH32_SHIFT 8 /* WSEQ_DATA_WIDTH32 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH32_WIDTH 3 /* WSEQ_DATA_WIDTH32 - [10:8] */
+#define WM8994_WSEQ_DATA_START32_MASK 0x000F /* WSEQ_DATA_START32 - [3:0] */
+#define WM8994_WSEQ_DATA_START32_SHIFT 0 /* WSEQ_DATA_START32 - [3:0] */
+#define WM8994_WSEQ_DATA_START32_WIDTH 4 /* WSEQ_DATA_START32 - [3:0] */
+
+/*
+ * R12419 (0x3083) - Write Sequencer 131
+ */
+#define WM8994_WSEQ_EOS32 0x0100 /* WSEQ_EOS32 */
+#define WM8994_WSEQ_EOS32_MASK 0x0100 /* WSEQ_EOS32 */
+#define WM8994_WSEQ_EOS32_SHIFT 8 /* WSEQ_EOS32 */
+#define WM8994_WSEQ_EOS32_WIDTH 1 /* WSEQ_EOS32 */
+#define WM8994_WSEQ_DELAY32_MASK 0x000F /* WSEQ_DELAY32 - [3:0] */
+#define WM8994_WSEQ_DELAY32_SHIFT 0 /* WSEQ_DELAY32 - [3:0] */
+#define WM8994_WSEQ_DELAY32_WIDTH 4 /* WSEQ_DELAY32 - [3:0] */
+
+/*
+ * R12420 (0x3084) - Write Sequencer 132
+ */
+#define WM8994_WSEQ_ADDR33_MASK 0x3FFF /* WSEQ_ADDR33 - [13:0] */
+#define WM8994_WSEQ_ADDR33_SHIFT 0 /* WSEQ_ADDR33 - [13:0] */
+#define WM8994_WSEQ_ADDR33_WIDTH 14 /* WSEQ_ADDR33 - [13:0] */
+
+/*
+ * R12421 (0x3085) - Write Sequencer 133
+ */
+#define WM8994_WSEQ_DATA33_MASK 0x00FF /* WSEQ_DATA33 - [7:0] */
+#define WM8994_WSEQ_DATA33_SHIFT 0 /* WSEQ_DATA33 - [7:0] */
+#define WM8994_WSEQ_DATA33_WIDTH 8 /* WSEQ_DATA33 - [7:0] */
+
+/*
+ * R12422 (0x3086) - Write Sequencer 134
+ */
+#define WM8994_WSEQ_DATA_WIDTH33_MASK 0x0700 /* WSEQ_DATA_WIDTH33 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH33_SHIFT 8 /* WSEQ_DATA_WIDTH33 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH33_WIDTH 3 /* WSEQ_DATA_WIDTH33 - [10:8] */
+#define WM8994_WSEQ_DATA_START33_MASK 0x000F /* WSEQ_DATA_START33 - [3:0] */
+#define WM8994_WSEQ_DATA_START33_SHIFT 0 /* WSEQ_DATA_START33 - [3:0] */
+#define WM8994_WSEQ_DATA_START33_WIDTH 4 /* WSEQ_DATA_START33 - [3:0] */
+
+/*
+ * R12423 (0x3087) - Write Sequencer 135
+ */
+#define WM8994_WSEQ_EOS33 0x0100 /* WSEQ_EOS33 */
+#define WM8994_WSEQ_EOS33_MASK 0x0100 /* WSEQ_EOS33 */
+#define WM8994_WSEQ_EOS33_SHIFT 8 /* WSEQ_EOS33 */
+#define WM8994_WSEQ_EOS33_WIDTH 1 /* WSEQ_EOS33 */
+#define WM8994_WSEQ_DELAY33_MASK 0x000F /* WSEQ_DELAY33 - [3:0] */
+#define WM8994_WSEQ_DELAY33_SHIFT 0 /* WSEQ_DELAY33 - [3:0] */
+#define WM8994_WSEQ_DELAY33_WIDTH 4 /* WSEQ_DELAY33 - [3:0] */
+
+/*
+ * R12424 (0x3088) - Write Sequencer 136
+ */
+#define WM8994_WSEQ_ADDR34_MASK 0x3FFF /* WSEQ_ADDR34 - [13:0] */
+#define WM8994_WSEQ_ADDR34_SHIFT 0 /* WSEQ_ADDR34 - [13:0] */
+#define WM8994_WSEQ_ADDR34_WIDTH 14 /* WSEQ_ADDR34 - [13:0] */
+
+/*
+ * R12425 (0x3089) - Write Sequencer 137
+ */
+#define WM8994_WSEQ_DATA34_MASK 0x00FF /* WSEQ_DATA34 - [7:0] */
+#define WM8994_WSEQ_DATA34_SHIFT 0 /* WSEQ_DATA34 - [7:0] */
+#define WM8994_WSEQ_DATA34_WIDTH 8 /* WSEQ_DATA34 - [7:0] */
+
+/*
+ * R12426 (0x308A) - Write Sequencer 138
+ */
+#define WM8994_WSEQ_DATA_WIDTH34_MASK 0x0700 /* WSEQ_DATA_WIDTH34 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH34_SHIFT 8 /* WSEQ_DATA_WIDTH34 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH34_WIDTH 3 /* WSEQ_DATA_WIDTH34 - [10:8] */
+#define WM8994_WSEQ_DATA_START34_MASK 0x000F /* WSEQ_DATA_START34 - [3:0] */
+#define WM8994_WSEQ_DATA_START34_SHIFT 0 /* WSEQ_DATA_START34 - [3:0] */
+#define WM8994_WSEQ_DATA_START34_WIDTH 4 /* WSEQ_DATA_START34 - [3:0] */
+
+/*
+ * R12427 (0x308B) - Write Sequencer 139
+ */
+#define WM8994_WSEQ_EOS34 0x0100 /* WSEQ_EOS34 */
+#define WM8994_WSEQ_EOS34_MASK 0x0100 /* WSEQ_EOS34 */
+#define WM8994_WSEQ_EOS34_SHIFT 8 /* WSEQ_EOS34 */
+#define WM8994_WSEQ_EOS34_WIDTH 1 /* WSEQ_EOS34 */
+#define WM8994_WSEQ_DELAY34_MASK 0x000F /* WSEQ_DELAY34 - [3:0] */
+#define WM8994_WSEQ_DELAY34_SHIFT 0 /* WSEQ_DELAY34 - [3:0] */
+#define WM8994_WSEQ_DELAY34_WIDTH 4 /* WSEQ_DELAY34 - [3:0] */
+
+/*
+ * R12428 (0x308C) - Write Sequencer 140
+ */
+#define WM8994_WSEQ_ADDR35_MASK 0x3FFF /* WSEQ_ADDR35 - [13:0] */
+#define WM8994_WSEQ_ADDR35_SHIFT 0 /* WSEQ_ADDR35 - [13:0] */
+#define WM8994_WSEQ_ADDR35_WIDTH 14 /* WSEQ_ADDR35 - [13:0] */
+
+/*
+ * R12429 (0x308D) - Write Sequencer 141
+ */
+#define WM8994_WSEQ_DATA35_MASK 0x00FF /* WSEQ_DATA35 - [7:0] */
+#define WM8994_WSEQ_DATA35_SHIFT 0 /* WSEQ_DATA35 - [7:0] */
+#define WM8994_WSEQ_DATA35_WIDTH 8 /* WSEQ_DATA35 - [7:0] */
+
+/*
+ * R12430 (0x308E) - Write Sequencer 142
+ */
+#define WM8994_WSEQ_DATA_WIDTH35_MASK 0x0700 /* WSEQ_DATA_WIDTH35 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH35_SHIFT 8 /* WSEQ_DATA_WIDTH35 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH35_WIDTH 3 /* WSEQ_DATA_WIDTH35 - [10:8] */
+#define WM8994_WSEQ_DATA_START35_MASK 0x000F /* WSEQ_DATA_START35 - [3:0] */
+#define WM8994_WSEQ_DATA_START35_SHIFT 0 /* WSEQ_DATA_START35 - [3:0] */
+#define WM8994_WSEQ_DATA_START35_WIDTH 4 /* WSEQ_DATA_START35 - [3:0] */
+
+/*
+ * R12431 (0x308F) - Write Sequencer 143
+ */
+#define WM8994_WSEQ_EOS35 0x0100 /* WSEQ_EOS35 */
+#define WM8994_WSEQ_EOS35_MASK 0x0100 /* WSEQ_EOS35 */
+#define WM8994_WSEQ_EOS35_SHIFT 8 /* WSEQ_EOS35 */
+#define WM8994_WSEQ_EOS35_WIDTH 1 /* WSEQ_EOS35 */
+#define WM8994_WSEQ_DELAY35_MASK 0x000F /* WSEQ_DELAY35 - [3:0] */
+#define WM8994_WSEQ_DELAY35_SHIFT 0 /* WSEQ_DELAY35 - [3:0] */
+#define WM8994_WSEQ_DELAY35_WIDTH 4 /* WSEQ_DELAY35 - [3:0] */
+
+/*
+ * R12432 (0x3090) - Write Sequencer 144
+ */
+#define WM8994_WSEQ_ADDR36_MASK 0x3FFF /* WSEQ_ADDR36 - [13:0] */
+#define WM8994_WSEQ_ADDR36_SHIFT 0 /* WSEQ_ADDR36 - [13:0] */
+#define WM8994_WSEQ_ADDR36_WIDTH 14 /* WSEQ_ADDR36 - [13:0] */
+
+/*
+ * R12433 (0x3091) - Write Sequencer 145
+ */
+#define WM8994_WSEQ_DATA36_MASK 0x00FF /* WSEQ_DATA36 - [7:0] */
+#define WM8994_WSEQ_DATA36_SHIFT 0 /* WSEQ_DATA36 - [7:0] */
+#define WM8994_WSEQ_DATA36_WIDTH 8 /* WSEQ_DATA36 - [7:0] */
+
+/*
+ * R12434 (0x3092) - Write Sequencer 146
+ */
+#define WM8994_WSEQ_DATA_WIDTH36_MASK 0x0700 /* WSEQ_DATA_WIDTH36 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH36_SHIFT 8 /* WSEQ_DATA_WIDTH36 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH36_WIDTH 3 /* WSEQ_DATA_WIDTH36 - [10:8] */
+#define WM8994_WSEQ_DATA_START36_MASK 0x000F /* WSEQ_DATA_START36 - [3:0] */
+#define WM8994_WSEQ_DATA_START36_SHIFT 0 /* WSEQ_DATA_START36 - [3:0] */
+#define WM8994_WSEQ_DATA_START36_WIDTH 4 /* WSEQ_DATA_START36 - [3:0] */
+
+/*
+ * R12435 (0x3093) - Write Sequencer 147
+ */
+#define WM8994_WSEQ_EOS36 0x0100 /* WSEQ_EOS36 */
+#define WM8994_WSEQ_EOS36_MASK 0x0100 /* WSEQ_EOS36 */
+#define WM8994_WSEQ_EOS36_SHIFT 8 /* WSEQ_EOS36 */
+#define WM8994_WSEQ_EOS36_WIDTH 1 /* WSEQ_EOS36 */
+#define WM8994_WSEQ_DELAY36_MASK 0x000F /* WSEQ_DELAY36 - [3:0] */
+#define WM8994_WSEQ_DELAY36_SHIFT 0 /* WSEQ_DELAY36 - [3:0] */
+#define WM8994_WSEQ_DELAY36_WIDTH 4 /* WSEQ_DELAY36 - [3:0] */
+
+/*
+ * R12436 (0x3094) - Write Sequencer 148
+ */
+#define WM8994_WSEQ_ADDR37_MASK 0x3FFF /* WSEQ_ADDR37 - [13:0] */
+#define WM8994_WSEQ_ADDR37_SHIFT 0 /* WSEQ_ADDR37 - [13:0] */
+#define WM8994_WSEQ_ADDR37_WIDTH 14 /* WSEQ_ADDR37 - [13:0] */
+
+/*
+ * R12437 (0x3095) - Write Sequencer 149
+ */
+#define WM8994_WSEQ_DATA37_MASK 0x00FF /* WSEQ_DATA37 - [7:0] */
+#define WM8994_WSEQ_DATA37_SHIFT 0 /* WSEQ_DATA37 - [7:0] */
+#define WM8994_WSEQ_DATA37_WIDTH 8 /* WSEQ_DATA37 - [7:0] */
+
+/*
+ * R12438 (0x3096) - Write Sequencer 150
+ */
+#define WM8994_WSEQ_DATA_WIDTH37_MASK 0x0700 /* WSEQ_DATA_WIDTH37 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH37_SHIFT 8 /* WSEQ_DATA_WIDTH37 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH37_WIDTH 3 /* WSEQ_DATA_WIDTH37 - [10:8] */
+#define WM8994_WSEQ_DATA_START37_MASK 0x000F /* WSEQ_DATA_START37 - [3:0] */
+#define WM8994_WSEQ_DATA_START37_SHIFT 0 /* WSEQ_DATA_START37 - [3:0] */
+#define WM8994_WSEQ_DATA_START37_WIDTH 4 /* WSEQ_DATA_START37 - [3:0] */
+
+/*
+ * R12439 (0x3097) - Write Sequencer 151
+ */
+#define WM8994_WSEQ_EOS37 0x0100 /* WSEQ_EOS37 */
+#define WM8994_WSEQ_EOS37_MASK 0x0100 /* WSEQ_EOS37 */
+#define WM8994_WSEQ_EOS37_SHIFT 8 /* WSEQ_EOS37 */
+#define WM8994_WSEQ_EOS37_WIDTH 1 /* WSEQ_EOS37 */
+#define WM8994_WSEQ_DELAY37_MASK 0x000F /* WSEQ_DELAY37 - [3:0] */
+#define WM8994_WSEQ_DELAY37_SHIFT 0 /* WSEQ_DELAY37 - [3:0] */
+#define WM8994_WSEQ_DELAY37_WIDTH 4 /* WSEQ_DELAY37 - [3:0] */
+
+/*
+ * R12440 (0x3098) - Write Sequencer 152
+ */
+#define WM8994_WSEQ_ADDR38_MASK 0x3FFF /* WSEQ_ADDR38 - [13:0] */
+#define WM8994_WSEQ_ADDR38_SHIFT 0 /* WSEQ_ADDR38 - [13:0] */
+#define WM8994_WSEQ_ADDR38_WIDTH 14 /* WSEQ_ADDR38 - [13:0] */
+
+/*
+ * R12441 (0x3099) - Write Sequencer 153
+ */
+#define WM8994_WSEQ_DATA38_MASK 0x00FF /* WSEQ_DATA38 - [7:0] */
+#define WM8994_WSEQ_DATA38_SHIFT 0 /* WSEQ_DATA38 - [7:0] */
+#define WM8994_WSEQ_DATA38_WIDTH 8 /* WSEQ_DATA38 - [7:0] */
+
+/*
+ * R12442 (0x309A) - Write Sequencer 154
+ */
+#define WM8994_WSEQ_DATA_WIDTH38_MASK 0x0700 /* WSEQ_DATA_WIDTH38 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH38_SHIFT 8 /* WSEQ_DATA_WIDTH38 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH38_WIDTH 3 /* WSEQ_DATA_WIDTH38 - [10:8] */
+#define WM8994_WSEQ_DATA_START38_MASK 0x000F /* WSEQ_DATA_START38 - [3:0] */
+#define WM8994_WSEQ_DATA_START38_SHIFT 0 /* WSEQ_DATA_START38 - [3:0] */
+#define WM8994_WSEQ_DATA_START38_WIDTH 4 /* WSEQ_DATA_START38 - [3:0] */
+
+/*
+ * R12443 (0x309B) - Write Sequencer 155
+ */
+#define WM8994_WSEQ_EOS38 0x0100 /* WSEQ_EOS38 */
+#define WM8994_WSEQ_EOS38_MASK 0x0100 /* WSEQ_EOS38 */
+#define WM8994_WSEQ_EOS38_SHIFT 8 /* WSEQ_EOS38 */
+#define WM8994_WSEQ_EOS38_WIDTH 1 /* WSEQ_EOS38 */
+#define WM8994_WSEQ_DELAY38_MASK 0x000F /* WSEQ_DELAY38 - [3:0] */
+#define WM8994_WSEQ_DELAY38_SHIFT 0 /* WSEQ_DELAY38 - [3:0] */
+#define WM8994_WSEQ_DELAY38_WIDTH 4 /* WSEQ_DELAY38 - [3:0] */
+
+/*
+ * R12444 (0x309C) - Write Sequencer 156
+ */
+#define WM8994_WSEQ_ADDR39_MASK 0x3FFF /* WSEQ_ADDR39 - [13:0] */
+#define WM8994_WSEQ_ADDR39_SHIFT 0 /* WSEQ_ADDR39 - [13:0] */
+#define WM8994_WSEQ_ADDR39_WIDTH 14 /* WSEQ_ADDR39 - [13:0] */
+
+/*
+ * R12445 (0x309D) - Write Sequencer 157
+ */
+#define WM8994_WSEQ_DATA39_MASK 0x00FF /* WSEQ_DATA39 - [7:0] */
+#define WM8994_WSEQ_DATA39_SHIFT 0 /* WSEQ_DATA39 - [7:0] */
+#define WM8994_WSEQ_DATA39_WIDTH 8 /* WSEQ_DATA39 - [7:0] */
+
+/*
+ * R12446 (0x309E) - Write Sequencer 158
+ */
+#define WM8994_WSEQ_DATA_WIDTH39_MASK 0x0700 /* WSEQ_DATA_WIDTH39 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH39_SHIFT 8 /* WSEQ_DATA_WIDTH39 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH39_WIDTH 3 /* WSEQ_DATA_WIDTH39 - [10:8] */
+#define WM8994_WSEQ_DATA_START39_MASK 0x000F /* WSEQ_DATA_START39 - [3:0] */
+#define WM8994_WSEQ_DATA_START39_SHIFT 0 /* WSEQ_DATA_START39 - [3:0] */
+#define WM8994_WSEQ_DATA_START39_WIDTH 4 /* WSEQ_DATA_START39 - [3:0] */
+
+/*
+ * R12447 (0x309F) - Write Sequencer 159
+ */
+#define WM8994_WSEQ_EOS39 0x0100 /* WSEQ_EOS39 */
+#define WM8994_WSEQ_EOS39_MASK 0x0100 /* WSEQ_EOS39 */
+#define WM8994_WSEQ_EOS39_SHIFT 8 /* WSEQ_EOS39 */
+#define WM8994_WSEQ_EOS39_WIDTH 1 /* WSEQ_EOS39 */
+#define WM8994_WSEQ_DELAY39_MASK 0x000F /* WSEQ_DELAY39 - [3:0] */
+#define WM8994_WSEQ_DELAY39_SHIFT 0 /* WSEQ_DELAY39 - [3:0] */
+#define WM8994_WSEQ_DELAY39_WIDTH 4 /* WSEQ_DELAY39 - [3:0] */
+
+/*
+ * R12448 (0x30A0) - Write Sequencer 160
+ */
+#define WM8994_WSEQ_ADDR40_MASK 0x3FFF /* WSEQ_ADDR40 - [13:0] */
+#define WM8994_WSEQ_ADDR40_SHIFT 0 /* WSEQ_ADDR40 - [13:0] */
+#define WM8994_WSEQ_ADDR40_WIDTH 14 /* WSEQ_ADDR40 - [13:0] */
+
+/*
+ * R12449 (0x30A1) - Write Sequencer 161
+ */
+#define WM8994_WSEQ_DATA40_MASK 0x00FF /* WSEQ_DATA40 - [7:0] */
+#define WM8994_WSEQ_DATA40_SHIFT 0 /* WSEQ_DATA40 - [7:0] */
+#define WM8994_WSEQ_DATA40_WIDTH 8 /* WSEQ_DATA40 - [7:0] */
+
+/*
+ * R12450 (0x30A2) - Write Sequencer 162
+ */
+#define WM8994_WSEQ_DATA_WIDTH40_MASK 0x0700 /* WSEQ_DATA_WIDTH40 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH40_SHIFT 8 /* WSEQ_DATA_WIDTH40 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH40_WIDTH 3 /* WSEQ_DATA_WIDTH40 - [10:8] */
+#define WM8994_WSEQ_DATA_START40_MASK 0x000F /* WSEQ_DATA_START40 - [3:0] */
+#define WM8994_WSEQ_DATA_START40_SHIFT 0 /* WSEQ_DATA_START40 - [3:0] */
+#define WM8994_WSEQ_DATA_START40_WIDTH 4 /* WSEQ_DATA_START40 - [3:0] */
+
+/*
+ * R12451 (0x30A3) - Write Sequencer 163
+ */
+#define WM8994_WSEQ_EOS40 0x0100 /* WSEQ_EOS40 */
+#define WM8994_WSEQ_EOS40_MASK 0x0100 /* WSEQ_EOS40 */
+#define WM8994_WSEQ_EOS40_SHIFT 8 /* WSEQ_EOS40 */
+#define WM8994_WSEQ_EOS40_WIDTH 1 /* WSEQ_EOS40 */
+#define WM8994_WSEQ_DELAY40_MASK 0x000F /* WSEQ_DELAY40 - [3:0] */
+#define WM8994_WSEQ_DELAY40_SHIFT 0 /* WSEQ_DELAY40 - [3:0] */
+#define WM8994_WSEQ_DELAY40_WIDTH 4 /* WSEQ_DELAY40 - [3:0] */
+
+/*
+ * R12452 (0x30A4) - Write Sequencer 164
+ */
+#define WM8994_WSEQ_ADDR41_MASK 0x3FFF /* WSEQ_ADDR41 - [13:0] */
+#define WM8994_WSEQ_ADDR41_SHIFT 0 /* WSEQ_ADDR41 - [13:0] */
+#define WM8994_WSEQ_ADDR41_WIDTH 14 /* WSEQ_ADDR41 - [13:0] */
+
+/*
+ * R12453 (0x30A5) - Write Sequencer 165
+ */
+#define WM8994_WSEQ_DATA41_MASK 0x00FF /* WSEQ_DATA41 - [7:0] */
+#define WM8994_WSEQ_DATA41_SHIFT 0 /* WSEQ_DATA41 - [7:0] */
+#define WM8994_WSEQ_DATA41_WIDTH 8 /* WSEQ_DATA41 - [7:0] */
+
+/*
+ * R12454 (0x30A6) - Write Sequencer 166
+ */
+#define WM8994_WSEQ_DATA_WIDTH41_MASK 0x0700 /* WSEQ_DATA_WIDTH41 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH41_SHIFT 8 /* WSEQ_DATA_WIDTH41 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH41_WIDTH 3 /* WSEQ_DATA_WIDTH41 - [10:8] */
+#define WM8994_WSEQ_DATA_START41_MASK 0x000F /* WSEQ_DATA_START41 - [3:0] */
+#define WM8994_WSEQ_DATA_START41_SHIFT 0 /* WSEQ_DATA_START41 - [3:0] */
+#define WM8994_WSEQ_DATA_START41_WIDTH 4 /* WSEQ_DATA_START41 - [3:0] */
+
+/*
+ * R12455 (0x30A7) - Write Sequencer 167
+ */
+#define WM8994_WSEQ_EOS41 0x0100 /* WSEQ_EOS41 */
+#define WM8994_WSEQ_EOS41_MASK 0x0100 /* WSEQ_EOS41 */
+#define WM8994_WSEQ_EOS41_SHIFT 8 /* WSEQ_EOS41 */
+#define WM8994_WSEQ_EOS41_WIDTH 1 /* WSEQ_EOS41 */
+#define WM8994_WSEQ_DELAY41_MASK 0x000F /* WSEQ_DELAY41 - [3:0] */
+#define WM8994_WSEQ_DELAY41_SHIFT 0 /* WSEQ_DELAY41 - [3:0] */
+#define WM8994_WSEQ_DELAY41_WIDTH 4 /* WSEQ_DELAY41 - [3:0] */
+
+/*
+ * R12456 (0x30A8) - Write Sequencer 168
+ */
+#define WM8994_WSEQ_ADDR42_MASK 0x3FFF /* WSEQ_ADDR42 - [13:0] */
+#define WM8994_WSEQ_ADDR42_SHIFT 0 /* WSEQ_ADDR42 - [13:0] */
+#define WM8994_WSEQ_ADDR42_WIDTH 14 /* WSEQ_ADDR42 - [13:0] */
+
+/*
+ * R12457 (0x30A9) - Write Sequencer 169
+ */
+#define WM8994_WSEQ_DATA42_MASK 0x00FF /* WSEQ_DATA42 - [7:0] */
+#define WM8994_WSEQ_DATA42_SHIFT 0 /* WSEQ_DATA42 - [7:0] */
+#define WM8994_WSEQ_DATA42_WIDTH 8 /* WSEQ_DATA42 - [7:0] */
+
+/*
+ * R12458 (0x30AA) - Write Sequencer 170
+ */
+#define WM8994_WSEQ_DATA_WIDTH42_MASK 0x0700 /* WSEQ_DATA_WIDTH42 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH42_SHIFT 8 /* WSEQ_DATA_WIDTH42 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH42_WIDTH 3 /* WSEQ_DATA_WIDTH42 - [10:8] */
+#define WM8994_WSEQ_DATA_START42_MASK 0x000F /* WSEQ_DATA_START42 - [3:0] */
+#define WM8994_WSEQ_DATA_START42_SHIFT 0 /* WSEQ_DATA_START42 - [3:0] */
+#define WM8994_WSEQ_DATA_START42_WIDTH 4 /* WSEQ_DATA_START42 - [3:0] */
+
+/*
+ * R12459 (0x30AB) - Write Sequencer 171
+ */
+#define WM8994_WSEQ_EOS42 0x0100 /* WSEQ_EOS42 */
+#define WM8994_WSEQ_EOS42_MASK 0x0100 /* WSEQ_EOS42 */
+#define WM8994_WSEQ_EOS42_SHIFT 8 /* WSEQ_EOS42 */
+#define WM8994_WSEQ_EOS42_WIDTH 1 /* WSEQ_EOS42 */
+#define WM8994_WSEQ_DELAY42_MASK 0x000F /* WSEQ_DELAY42 - [3:0] */
+#define WM8994_WSEQ_DELAY42_SHIFT 0 /* WSEQ_DELAY42 - [3:0] */
+#define WM8994_WSEQ_DELAY42_WIDTH 4 /* WSEQ_DELAY42 - [3:0] */
+
+/*
+ * R12460 (0x30AC) - Write Sequencer 172
+ */
+#define WM8994_WSEQ_ADDR43_MASK 0x3FFF /* WSEQ_ADDR43 - [13:0] */
+#define WM8994_WSEQ_ADDR43_SHIFT 0 /* WSEQ_ADDR43 - [13:0] */
+#define WM8994_WSEQ_ADDR43_WIDTH 14 /* WSEQ_ADDR43 - [13:0] */
+
+/*
+ * R12461 (0x30AD) - Write Sequencer 173
+ */
+#define WM8994_WSEQ_DATA43_MASK 0x00FF /* WSEQ_DATA43 - [7:0] */
+#define WM8994_WSEQ_DATA43_SHIFT 0 /* WSEQ_DATA43 - [7:0] */
+#define WM8994_WSEQ_DATA43_WIDTH 8 /* WSEQ_DATA43 - [7:0] */
+
+/*
+ * R12462 (0x30AE) - Write Sequencer 174
+ */
+#define WM8994_WSEQ_DATA_WIDTH43_MASK 0x0700 /* WSEQ_DATA_WIDTH43 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH43_SHIFT 8 /* WSEQ_DATA_WIDTH43 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH43_WIDTH 3 /* WSEQ_DATA_WIDTH43 - [10:8] */
+#define WM8994_WSEQ_DATA_START43_MASK 0x000F /* WSEQ_DATA_START43 - [3:0] */
+#define WM8994_WSEQ_DATA_START43_SHIFT 0 /* WSEQ_DATA_START43 - [3:0] */
+#define WM8994_WSEQ_DATA_START43_WIDTH 4 /* WSEQ_DATA_START43 - [3:0] */
+
+/*
+ * R12463 (0x30AF) - Write Sequencer 175
+ */
+#define WM8994_WSEQ_EOS43 0x0100 /* WSEQ_EOS43 */
+#define WM8994_WSEQ_EOS43_MASK 0x0100 /* WSEQ_EOS43 */
+#define WM8994_WSEQ_EOS43_SHIFT 8 /* WSEQ_EOS43 */
+#define WM8994_WSEQ_EOS43_WIDTH 1 /* WSEQ_EOS43 */
+#define WM8994_WSEQ_DELAY43_MASK 0x000F /* WSEQ_DELAY43 - [3:0] */
+#define WM8994_WSEQ_DELAY43_SHIFT 0 /* WSEQ_DELAY43 - [3:0] */
+#define WM8994_WSEQ_DELAY43_WIDTH 4 /* WSEQ_DELAY43 - [3:0] */
+
+/*
+ * R12464 (0x30B0) - Write Sequencer 176
+ */
+#define WM8994_WSEQ_ADDR44_MASK 0x3FFF /* WSEQ_ADDR44 - [13:0] */
+#define WM8994_WSEQ_ADDR44_SHIFT 0 /* WSEQ_ADDR44 - [13:0] */
+#define WM8994_WSEQ_ADDR44_WIDTH 14 /* WSEQ_ADDR44 - [13:0] */
+
+/*
+ * R12465 (0x30B1) - Write Sequencer 177
+ */
+#define WM8994_WSEQ_DATA44_MASK 0x00FF /* WSEQ_DATA44 - [7:0] */
+#define WM8994_WSEQ_DATA44_SHIFT 0 /* WSEQ_DATA44 - [7:0] */
+#define WM8994_WSEQ_DATA44_WIDTH 8 /* WSEQ_DATA44 - [7:0] */
+
+/*
+ * R12466 (0x30B2) - Write Sequencer 178
+ */
+#define WM8994_WSEQ_DATA_WIDTH44_MASK 0x0700 /* WSEQ_DATA_WIDTH44 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH44_SHIFT 8 /* WSEQ_DATA_WIDTH44 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH44_WIDTH 3 /* WSEQ_DATA_WIDTH44 - [10:8] */
+#define WM8994_WSEQ_DATA_START44_MASK 0x000F /* WSEQ_DATA_START44 - [3:0] */
+#define WM8994_WSEQ_DATA_START44_SHIFT 0 /* WSEQ_DATA_START44 - [3:0] */
+#define WM8994_WSEQ_DATA_START44_WIDTH 4 /* WSEQ_DATA_START44 - [3:0] */
+
+/*
+ * R12467 (0x30B3) - Write Sequencer 179
+ */
+#define WM8994_WSEQ_EOS44 0x0100 /* WSEQ_EOS44 */
+#define WM8994_WSEQ_EOS44_MASK 0x0100 /* WSEQ_EOS44 */
+#define WM8994_WSEQ_EOS44_SHIFT 8 /* WSEQ_EOS44 */
+#define WM8994_WSEQ_EOS44_WIDTH 1 /* WSEQ_EOS44 */
+#define WM8994_WSEQ_DELAY44_MASK 0x000F /* WSEQ_DELAY44 - [3:0] */
+#define WM8994_WSEQ_DELAY44_SHIFT 0 /* WSEQ_DELAY44 - [3:0] */
+#define WM8994_WSEQ_DELAY44_WIDTH 4 /* WSEQ_DELAY44 - [3:0] */
+
+/*
+ * R12468 (0x30B4) - Write Sequencer 180
+ */
+#define WM8994_WSEQ_ADDR45_MASK 0x3FFF /* WSEQ_ADDR45 - [13:0] */
+#define WM8994_WSEQ_ADDR45_SHIFT 0 /* WSEQ_ADDR45 - [13:0] */
+#define WM8994_WSEQ_ADDR45_WIDTH 14 /* WSEQ_ADDR45 - [13:0] */
+
+/*
+ * R12469 (0x30B5) - Write Sequencer 181
+ */
+#define WM8994_WSEQ_DATA45_MASK 0x00FF /* WSEQ_DATA45 - [7:0] */
+#define WM8994_WSEQ_DATA45_SHIFT 0 /* WSEQ_DATA45 - [7:0] */
+#define WM8994_WSEQ_DATA45_WIDTH 8 /* WSEQ_DATA45 - [7:0] */
+
+/*
+ * R12470 (0x30B6) - Write Sequencer 182
+ */
+#define WM8994_WSEQ_DATA_WIDTH45_MASK 0x0700 /* WSEQ_DATA_WIDTH45 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH45_SHIFT 8 /* WSEQ_DATA_WIDTH45 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH45_WIDTH 3 /* WSEQ_DATA_WIDTH45 - [10:8] */
+#define WM8994_WSEQ_DATA_START45_MASK 0x000F /* WSEQ_DATA_START45 - [3:0] */
+#define WM8994_WSEQ_DATA_START45_SHIFT 0 /* WSEQ_DATA_START45 - [3:0] */
+#define WM8994_WSEQ_DATA_START45_WIDTH 4 /* WSEQ_DATA_START45 - [3:0] */
+
+/*
+ * R12471 (0x30B7) - Write Sequencer 183
+ */
+#define WM8994_WSEQ_EOS45 0x0100 /* WSEQ_EOS45 */
+#define WM8994_WSEQ_EOS45_MASK 0x0100 /* WSEQ_EOS45 */
+#define WM8994_WSEQ_EOS45_SHIFT 8 /* WSEQ_EOS45 */
+#define WM8994_WSEQ_EOS45_WIDTH 1 /* WSEQ_EOS45 */
+#define WM8994_WSEQ_DELAY45_MASK 0x000F /* WSEQ_DELAY45 - [3:0] */
+#define WM8994_WSEQ_DELAY45_SHIFT 0 /* WSEQ_DELAY45 - [3:0] */
+#define WM8994_WSEQ_DELAY45_WIDTH 4 /* WSEQ_DELAY45 - [3:0] */
+
+/*
+ * R12472 (0x30B8) - Write Sequencer 184
+ */
+#define WM8994_WSEQ_ADDR46_MASK 0x3FFF /* WSEQ_ADDR46 - [13:0] */
+#define WM8994_WSEQ_ADDR46_SHIFT 0 /* WSEQ_ADDR46 - [13:0] */
+#define WM8994_WSEQ_ADDR46_WIDTH 14 /* WSEQ_ADDR46 - [13:0] */
+
+/*
+ * R12473 (0x30B9) - Write Sequencer 185
+ */
+#define WM8994_WSEQ_DATA46_MASK 0x00FF /* WSEQ_DATA46 - [7:0] */
+#define WM8994_WSEQ_DATA46_SHIFT 0 /* WSEQ_DATA46 - [7:0] */
+#define WM8994_WSEQ_DATA46_WIDTH 8 /* WSEQ_DATA46 - [7:0] */
+
+/*
+ * R12474 (0x30BA) - Write Sequencer 186
+ */
+#define WM8994_WSEQ_DATA_WIDTH46_MASK 0x0700 /* WSEQ_DATA_WIDTH46 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH46_SHIFT 8 /* WSEQ_DATA_WIDTH46 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH46_WIDTH 3 /* WSEQ_DATA_WIDTH46 - [10:8] */
+#define WM8994_WSEQ_DATA_START46_MASK 0x000F /* WSEQ_DATA_START46 - [3:0] */
+#define WM8994_WSEQ_DATA_START46_SHIFT 0 /* WSEQ_DATA_START46 - [3:0] */
+#define WM8994_WSEQ_DATA_START46_WIDTH 4 /* WSEQ_DATA_START46 - [3:0] */
+
+/*
+ * R12475 (0x30BB) - Write Sequencer 187
+ */
+#define WM8994_WSEQ_EOS46 0x0100 /* WSEQ_EOS46 */
+#define WM8994_WSEQ_EOS46_MASK 0x0100 /* WSEQ_EOS46 */
+#define WM8994_WSEQ_EOS46_SHIFT 8 /* WSEQ_EOS46 */
+#define WM8994_WSEQ_EOS46_WIDTH 1 /* WSEQ_EOS46 */
+#define WM8994_WSEQ_DELAY46_MASK 0x000F /* WSEQ_DELAY46 - [3:0] */
+#define WM8994_WSEQ_DELAY46_SHIFT 0 /* WSEQ_DELAY46 - [3:0] */
+#define WM8994_WSEQ_DELAY46_WIDTH 4 /* WSEQ_DELAY46 - [3:0] */
+
+/*
+ * R12476 (0x30BC) - Write Sequencer 188
+ */
+#define WM8994_WSEQ_ADDR47_MASK 0x3FFF /* WSEQ_ADDR47 - [13:0] */
+#define WM8994_WSEQ_ADDR47_SHIFT 0 /* WSEQ_ADDR47 - [13:0] */
+#define WM8994_WSEQ_ADDR47_WIDTH 14 /* WSEQ_ADDR47 - [13:0] */
+
+/*
+ * R12477 (0x30BD) - Write Sequencer 189
+ */
+#define WM8994_WSEQ_DATA47_MASK 0x00FF /* WSEQ_DATA47 - [7:0] */
+#define WM8994_WSEQ_DATA47_SHIFT 0 /* WSEQ_DATA47 - [7:0] */
+#define WM8994_WSEQ_DATA47_WIDTH 8 /* WSEQ_DATA47 - [7:0] */
+
+/*
+ * R12478 (0x30BE) - Write Sequencer 190
+ */
+#define WM8994_WSEQ_DATA_WIDTH47_MASK 0x0700 /* WSEQ_DATA_WIDTH47 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH47_SHIFT 8 /* WSEQ_DATA_WIDTH47 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH47_WIDTH 3 /* WSEQ_DATA_WIDTH47 - [10:8] */
+#define WM8994_WSEQ_DATA_START47_MASK 0x000F /* WSEQ_DATA_START47 - [3:0] */
+#define WM8994_WSEQ_DATA_START47_SHIFT 0 /* WSEQ_DATA_START47 - [3:0] */
+#define WM8994_WSEQ_DATA_START47_WIDTH 4 /* WSEQ_DATA_START47 - [3:0] */
+
+/*
+ * R12479 (0x30BF) - Write Sequencer 191
+ */
+#define WM8994_WSEQ_EOS47 0x0100 /* WSEQ_EOS47 */
+#define WM8994_WSEQ_EOS47_MASK 0x0100 /* WSEQ_EOS47 */
+#define WM8994_WSEQ_EOS47_SHIFT 8 /* WSEQ_EOS47 */
+#define WM8994_WSEQ_EOS47_WIDTH 1 /* WSEQ_EOS47 */
+#define WM8994_WSEQ_DELAY47_MASK 0x000F /* WSEQ_DELAY47 - [3:0] */
+#define WM8994_WSEQ_DELAY47_SHIFT 0 /* WSEQ_DELAY47 - [3:0] */
+#define WM8994_WSEQ_DELAY47_WIDTH 4 /* WSEQ_DELAY47 - [3:0] */
+
+/*
+ * R12480 (0x30C0) - Write Sequencer 192
+ */
+#define WM8994_WSEQ_ADDR48_MASK 0x3FFF /* WSEQ_ADDR48 - [13:0] */
+#define WM8994_WSEQ_ADDR48_SHIFT 0 /* WSEQ_ADDR48 - [13:0] */
+#define WM8994_WSEQ_ADDR48_WIDTH 14 /* WSEQ_ADDR48 - [13:0] */
+
+/*
+ * R12481 (0x30C1) - Write Sequencer 193
+ */
+#define WM8994_WSEQ_DATA48_MASK 0x00FF /* WSEQ_DATA48 - [7:0] */
+#define WM8994_WSEQ_DATA48_SHIFT 0 /* WSEQ_DATA48 - [7:0] */
+#define WM8994_WSEQ_DATA48_WIDTH 8 /* WSEQ_DATA48 - [7:0] */
+
+/*
+ * R12482 (0x30C2) - Write Sequencer 194
+ */
+#define WM8994_WSEQ_DATA_WIDTH48_MASK 0x0700 /* WSEQ_DATA_WIDTH48 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH48_SHIFT 8 /* WSEQ_DATA_WIDTH48 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH48_WIDTH 3 /* WSEQ_DATA_WIDTH48 - [10:8] */
+#define WM8994_WSEQ_DATA_START48_MASK 0x000F /* WSEQ_DATA_START48 - [3:0] */
+#define WM8994_WSEQ_DATA_START48_SHIFT 0 /* WSEQ_DATA_START48 - [3:0] */
+#define WM8994_WSEQ_DATA_START48_WIDTH 4 /* WSEQ_DATA_START48 - [3:0] */
+
+/*
+ * R12483 (0x30C3) - Write Sequencer 195
+ */
+#define WM8994_WSEQ_EOS48 0x0100 /* WSEQ_EOS48 */
+#define WM8994_WSEQ_EOS48_MASK 0x0100 /* WSEQ_EOS48 */
+#define WM8994_WSEQ_EOS48_SHIFT 8 /* WSEQ_EOS48 */
+#define WM8994_WSEQ_EOS48_WIDTH 1 /* WSEQ_EOS48 */
+#define WM8994_WSEQ_DELAY48_MASK 0x000F /* WSEQ_DELAY48 - [3:0] */
+#define WM8994_WSEQ_DELAY48_SHIFT 0 /* WSEQ_DELAY48 - [3:0] */
+#define WM8994_WSEQ_DELAY48_WIDTH 4 /* WSEQ_DELAY48 - [3:0] */
+
+/*
+ * R12484 (0x30C4) - Write Sequencer 196
+ */
+#define WM8994_WSEQ_ADDR49_MASK 0x3FFF /* WSEQ_ADDR49 - [13:0] */
+#define WM8994_WSEQ_ADDR49_SHIFT 0 /* WSEQ_ADDR49 - [13:0] */
+#define WM8994_WSEQ_ADDR49_WIDTH 14 /* WSEQ_ADDR49 - [13:0] */
+
+/*
+ * R12485 (0x30C5) - Write Sequencer 197
+ */
+#define WM8994_WSEQ_DATA49_MASK 0x00FF /* WSEQ_DATA49 - [7:0] */
+#define WM8994_WSEQ_DATA49_SHIFT 0 /* WSEQ_DATA49 - [7:0] */
+#define WM8994_WSEQ_DATA49_WIDTH 8 /* WSEQ_DATA49 - [7:0] */
+
+/*
+ * R12486 (0x30C6) - Write Sequencer 198
+ */
+#define WM8994_WSEQ_DATA_WIDTH49_MASK 0x0700 /* WSEQ_DATA_WIDTH49 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH49_SHIFT 8 /* WSEQ_DATA_WIDTH49 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH49_WIDTH 3 /* WSEQ_DATA_WIDTH49 - [10:8] */
+#define WM8994_WSEQ_DATA_START49_MASK 0x000F /* WSEQ_DATA_START49 - [3:0] */
+#define WM8994_WSEQ_DATA_START49_SHIFT 0 /* WSEQ_DATA_START49 - [3:0] */
+#define WM8994_WSEQ_DATA_START49_WIDTH 4 /* WSEQ_DATA_START49 - [3:0] */
+
+/*
+ * R12487 (0x30C7) - Write Sequencer 199
+ */
+#define WM8994_WSEQ_EOS49 0x0100 /* WSEQ_EOS49 */
+#define WM8994_WSEQ_EOS49_MASK 0x0100 /* WSEQ_EOS49 */
+#define WM8994_WSEQ_EOS49_SHIFT 8 /* WSEQ_EOS49 */
+#define WM8994_WSEQ_EOS49_WIDTH 1 /* WSEQ_EOS49 */
+#define WM8994_WSEQ_DELAY49_MASK 0x000F /* WSEQ_DELAY49 - [3:0] */
+#define WM8994_WSEQ_DELAY49_SHIFT 0 /* WSEQ_DELAY49 - [3:0] */
+#define WM8994_WSEQ_DELAY49_WIDTH 4 /* WSEQ_DELAY49 - [3:0] */
+
+/*
+ * R12488 (0x30C8) - Write Sequencer 200
+ */
+#define WM8994_WSEQ_ADDR50_MASK 0x3FFF /* WSEQ_ADDR50 - [13:0] */
+#define WM8994_WSEQ_ADDR50_SHIFT 0 /* WSEQ_ADDR50 - [13:0] */
+#define WM8994_WSEQ_ADDR50_WIDTH 14 /* WSEQ_ADDR50 - [13:0] */
+
+/*
+ * R12489 (0x30C9) - Write Sequencer 201
+ */
+#define WM8994_WSEQ_DATA50_MASK 0x00FF /* WSEQ_DATA50 - [7:0] */
+#define WM8994_WSEQ_DATA50_SHIFT 0 /* WSEQ_DATA50 - [7:0] */
+#define WM8994_WSEQ_DATA50_WIDTH 8 /* WSEQ_DATA50 - [7:0] */
+
+/*
+ * R12490 (0x30CA) - Write Sequencer 202
+ */
+#define WM8994_WSEQ_DATA_WIDTH50_MASK 0x0700 /* WSEQ_DATA_WIDTH50 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH50_SHIFT 8 /* WSEQ_DATA_WIDTH50 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH50_WIDTH 3 /* WSEQ_DATA_WIDTH50 - [10:8] */
+#define WM8994_WSEQ_DATA_START50_MASK 0x000F /* WSEQ_DATA_START50 - [3:0] */
+#define WM8994_WSEQ_DATA_START50_SHIFT 0 /* WSEQ_DATA_START50 - [3:0] */
+#define WM8994_WSEQ_DATA_START50_WIDTH 4 /* WSEQ_DATA_START50 - [3:0] */
+
+/*
+ * R12491 (0x30CB) - Write Sequencer 203
+ */
+#define WM8994_WSEQ_EOS50 0x0100 /* WSEQ_EOS50 */
+#define WM8994_WSEQ_EOS50_MASK 0x0100 /* WSEQ_EOS50 */
+#define WM8994_WSEQ_EOS50_SHIFT 8 /* WSEQ_EOS50 */
+#define WM8994_WSEQ_EOS50_WIDTH 1 /* WSEQ_EOS50 */
+#define WM8994_WSEQ_DELAY50_MASK 0x000F /* WSEQ_DELAY50 - [3:0] */
+#define WM8994_WSEQ_DELAY50_SHIFT 0 /* WSEQ_DELAY50 - [3:0] */
+#define WM8994_WSEQ_DELAY50_WIDTH 4 /* WSEQ_DELAY50 - [3:0] */
+
+/*
+ * R12492 (0x30CC) - Write Sequencer 204
+ */
+#define WM8994_WSEQ_ADDR51_MASK 0x3FFF /* WSEQ_ADDR51 - [13:0] */
+#define WM8994_WSEQ_ADDR51_SHIFT 0 /* WSEQ_ADDR51 - [13:0] */
+#define WM8994_WSEQ_ADDR51_WIDTH 14 /* WSEQ_ADDR51 - [13:0] */
+
+/*
+ * R12493 (0x30CD) - Write Sequencer 205
+ */
+#define WM8994_WSEQ_DATA51_MASK 0x00FF /* WSEQ_DATA51 - [7:0] */
+#define WM8994_WSEQ_DATA51_SHIFT 0 /* WSEQ_DATA51 - [7:0] */
+#define WM8994_WSEQ_DATA51_WIDTH 8 /* WSEQ_DATA51 - [7:0] */
+
+/*
+ * R12494 (0x30CE) - Write Sequencer 206
+ */
+#define WM8994_WSEQ_DATA_WIDTH51_MASK 0x0700 /* WSEQ_DATA_WIDTH51 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH51_SHIFT 8 /* WSEQ_DATA_WIDTH51 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH51_WIDTH 3 /* WSEQ_DATA_WIDTH51 - [10:8] */
+#define WM8994_WSEQ_DATA_START51_MASK 0x000F /* WSEQ_DATA_START51 - [3:0] */
+#define WM8994_WSEQ_DATA_START51_SHIFT 0 /* WSEQ_DATA_START51 - [3:0] */
+#define WM8994_WSEQ_DATA_START51_WIDTH 4 /* WSEQ_DATA_START51 - [3:0] */
+
+/*
+ * R12495 (0x30CF) - Write Sequencer 207
+ */
+#define WM8994_WSEQ_EOS51 0x0100 /* WSEQ_EOS51 */
+#define WM8994_WSEQ_EOS51_MASK 0x0100 /* WSEQ_EOS51 */
+#define WM8994_WSEQ_EOS51_SHIFT 8 /* WSEQ_EOS51 */
+#define WM8994_WSEQ_EOS51_WIDTH 1 /* WSEQ_EOS51 */
+#define WM8994_WSEQ_DELAY51_MASK 0x000F /* WSEQ_DELAY51 - [3:0] */
+#define WM8994_WSEQ_DELAY51_SHIFT 0 /* WSEQ_DELAY51 - [3:0] */
+#define WM8994_WSEQ_DELAY51_WIDTH 4 /* WSEQ_DELAY51 - [3:0] */
+
+/*
+ * R12496 (0x30D0) - Write Sequencer 208
+ */
+#define WM8994_WSEQ_ADDR52_MASK 0x3FFF /* WSEQ_ADDR52 - [13:0] */
+#define WM8994_WSEQ_ADDR52_SHIFT 0 /* WSEQ_ADDR52 - [13:0] */
+#define WM8994_WSEQ_ADDR52_WIDTH 14 /* WSEQ_ADDR52 - [13:0] */
+
+/*
+ * R12497 (0x30D1) - Write Sequencer 209
+ */
+#define WM8994_WSEQ_DATA52_MASK 0x00FF /* WSEQ_DATA52 - [7:0] */
+#define WM8994_WSEQ_DATA52_SHIFT 0 /* WSEQ_DATA52 - [7:0] */
+#define WM8994_WSEQ_DATA52_WIDTH 8 /* WSEQ_DATA52 - [7:0] */
+
+/*
+ * R12498 (0x30D2) - Write Sequencer 210
+ */
+#define WM8994_WSEQ_DATA_WIDTH52_MASK 0x0700 /* WSEQ_DATA_WIDTH52 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH52_SHIFT 8 /* WSEQ_DATA_WIDTH52 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH52_WIDTH 3 /* WSEQ_DATA_WIDTH52 - [10:8] */
+#define WM8994_WSEQ_DATA_START52_MASK 0x000F /* WSEQ_DATA_START52 - [3:0] */
+#define WM8994_WSEQ_DATA_START52_SHIFT 0 /* WSEQ_DATA_START52 - [3:0] */
+#define WM8994_WSEQ_DATA_START52_WIDTH 4 /* WSEQ_DATA_START52 - [3:0] */
+
+/*
+ * R12499 (0x30D3) - Write Sequencer 211
+ */
+#define WM8994_WSEQ_EOS52 0x0100 /* WSEQ_EOS52 */
+#define WM8994_WSEQ_EOS52_MASK 0x0100 /* WSEQ_EOS52 */
+#define WM8994_WSEQ_EOS52_SHIFT 8 /* WSEQ_EOS52 */
+#define WM8994_WSEQ_EOS52_WIDTH 1 /* WSEQ_EOS52 */
+#define WM8994_WSEQ_DELAY52_MASK 0x000F /* WSEQ_DELAY52 - [3:0] */
+#define WM8994_WSEQ_DELAY52_SHIFT 0 /* WSEQ_DELAY52 - [3:0] */
+#define WM8994_WSEQ_DELAY52_WIDTH 4 /* WSEQ_DELAY52 - [3:0] */
+
+/*
+ * R12500 (0x30D4) - Write Sequencer 212
+ */
+#define WM8994_WSEQ_ADDR53_MASK 0x3FFF /* WSEQ_ADDR53 - [13:0] */
+#define WM8994_WSEQ_ADDR53_SHIFT 0 /* WSEQ_ADDR53 - [13:0] */
+#define WM8994_WSEQ_ADDR53_WIDTH 14 /* WSEQ_ADDR53 - [13:0] */
+
+/*
+ * R12501 (0x30D5) - Write Sequencer 213
+ */
+#define WM8994_WSEQ_DATA53_MASK 0x00FF /* WSEQ_DATA53 - [7:0] */
+#define WM8994_WSEQ_DATA53_SHIFT 0 /* WSEQ_DATA53 - [7:0] */
+#define WM8994_WSEQ_DATA53_WIDTH 8 /* WSEQ_DATA53 - [7:0] */
+
+/*
+ * R12502 (0x30D6) - Write Sequencer 214
+ */
+#define WM8994_WSEQ_DATA_WIDTH53_MASK 0x0700 /* WSEQ_DATA_WIDTH53 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH53_SHIFT 8 /* WSEQ_DATA_WIDTH53 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH53_WIDTH 3 /* WSEQ_DATA_WIDTH53 - [10:8] */
+#define WM8994_WSEQ_DATA_START53_MASK 0x000F /* WSEQ_DATA_START53 - [3:0] */
+#define WM8994_WSEQ_DATA_START53_SHIFT 0 /* WSEQ_DATA_START53 - [3:0] */
+#define WM8994_WSEQ_DATA_START53_WIDTH 4 /* WSEQ_DATA_START53 - [3:0] */
+
+/*
+ * R12503 (0x30D7) - Write Sequencer 215
+ */
+#define WM8994_WSEQ_EOS53 0x0100 /* WSEQ_EOS53 */
+#define WM8994_WSEQ_EOS53_MASK 0x0100 /* WSEQ_EOS53 */
+#define WM8994_WSEQ_EOS53_SHIFT 8 /* WSEQ_EOS53 */
+#define WM8994_WSEQ_EOS53_WIDTH 1 /* WSEQ_EOS53 */
+#define WM8994_WSEQ_DELAY53_MASK 0x000F /* WSEQ_DELAY53 - [3:0] */
+#define WM8994_WSEQ_DELAY53_SHIFT 0 /* WSEQ_DELAY53 - [3:0] */
+#define WM8994_WSEQ_DELAY53_WIDTH 4 /* WSEQ_DELAY53 - [3:0] */
+
+/*
+ * R12504 (0x30D8) - Write Sequencer 216
+ */
+#define WM8994_WSEQ_ADDR54_MASK 0x3FFF /* WSEQ_ADDR54 - [13:0] */
+#define WM8994_WSEQ_ADDR54_SHIFT 0 /* WSEQ_ADDR54 - [13:0] */
+#define WM8994_WSEQ_ADDR54_WIDTH 14 /* WSEQ_ADDR54 - [13:0] */
+
+/*
+ * R12505 (0x30D9) - Write Sequencer 217
+ */
+#define WM8994_WSEQ_DATA54_MASK 0x00FF /* WSEQ_DATA54 - [7:0] */
+#define WM8994_WSEQ_DATA54_SHIFT 0 /* WSEQ_DATA54 - [7:0] */
+#define WM8994_WSEQ_DATA54_WIDTH 8 /* WSEQ_DATA54 - [7:0] */
+
+/*
+ * R12506 (0x30DA) - Write Sequencer 218
+ */
+#define WM8994_WSEQ_DATA_WIDTH54_MASK 0x0700 /* WSEQ_DATA_WIDTH54 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH54_SHIFT 8 /* WSEQ_DATA_WIDTH54 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH54_WIDTH 3 /* WSEQ_DATA_WIDTH54 - [10:8] */
+#define WM8994_WSEQ_DATA_START54_MASK 0x000F /* WSEQ_DATA_START54 - [3:0] */
+#define WM8994_WSEQ_DATA_START54_SHIFT 0 /* WSEQ_DATA_START54 - [3:0] */
+#define WM8994_WSEQ_DATA_START54_WIDTH 4 /* WSEQ_DATA_START54 - [3:0] */
+
+/*
+ * R12507 (0x30DB) - Write Sequencer 219
+ */
+#define WM8994_WSEQ_EOS54 0x0100 /* WSEQ_EOS54 */
+#define WM8994_WSEQ_EOS54_MASK 0x0100 /* WSEQ_EOS54 */
+#define WM8994_WSEQ_EOS54_SHIFT 8 /* WSEQ_EOS54 */
+#define WM8994_WSEQ_EOS54_WIDTH 1 /* WSEQ_EOS54 */
+#define WM8994_WSEQ_DELAY54_MASK 0x000F /* WSEQ_DELAY54 - [3:0] */
+#define WM8994_WSEQ_DELAY54_SHIFT 0 /* WSEQ_DELAY54 - [3:0] */
+#define WM8994_WSEQ_DELAY54_WIDTH 4 /* WSEQ_DELAY54 - [3:0] */
+
+/*
+ * R12508 (0x30DC) - Write Sequencer 220
+ */
+#define WM8994_WSEQ_ADDR55_MASK 0x3FFF /* WSEQ_ADDR55 - [13:0] */
+#define WM8994_WSEQ_ADDR55_SHIFT 0 /* WSEQ_ADDR55 - [13:0] */
+#define WM8994_WSEQ_ADDR55_WIDTH 14 /* WSEQ_ADDR55 - [13:0] */
+
+/*
+ * R12509 (0x30DD) - Write Sequencer 221
+ */
+#define WM8994_WSEQ_DATA55_MASK 0x00FF /* WSEQ_DATA55 - [7:0] */
+#define WM8994_WSEQ_DATA55_SHIFT 0 /* WSEQ_DATA55 - [7:0] */
+#define WM8994_WSEQ_DATA55_WIDTH 8 /* WSEQ_DATA55 - [7:0] */
+
+/*
+ * R12510 (0x30DE) - Write Sequencer 222
+ */
+#define WM8994_WSEQ_DATA_WIDTH55_MASK 0x0700 /* WSEQ_DATA_WIDTH55 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH55_SHIFT 8 /* WSEQ_DATA_WIDTH55 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH55_WIDTH 3 /* WSEQ_DATA_WIDTH55 - [10:8] */
+#define WM8994_WSEQ_DATA_START55_MASK 0x000F /* WSEQ_DATA_START55 - [3:0] */
+#define WM8994_WSEQ_DATA_START55_SHIFT 0 /* WSEQ_DATA_START55 - [3:0] */
+#define WM8994_WSEQ_DATA_START55_WIDTH 4 /* WSEQ_DATA_START55 - [3:0] */
+
+/*
+ * R12511 (0x30DF) - Write Sequencer 223
+ */
+#define WM8994_WSEQ_EOS55 0x0100 /* WSEQ_EOS55 */
+#define WM8994_WSEQ_EOS55_MASK 0x0100 /* WSEQ_EOS55 */
+#define WM8994_WSEQ_EOS55_SHIFT 8 /* WSEQ_EOS55 */
+#define WM8994_WSEQ_EOS55_WIDTH 1 /* WSEQ_EOS55 */
+#define WM8994_WSEQ_DELAY55_MASK 0x000F /* WSEQ_DELAY55 - [3:0] */
+#define WM8994_WSEQ_DELAY55_SHIFT 0 /* WSEQ_DELAY55 - [3:0] */
+#define WM8994_WSEQ_DELAY55_WIDTH 4 /* WSEQ_DELAY55 - [3:0] */
+
+/*
+ * R12512 (0x30E0) - Write Sequencer 224
+ */
+#define WM8994_WSEQ_ADDR56_MASK 0x3FFF /* WSEQ_ADDR56 - [13:0] */
+#define WM8994_WSEQ_ADDR56_SHIFT 0 /* WSEQ_ADDR56 - [13:0] */
+#define WM8994_WSEQ_ADDR56_WIDTH 14 /* WSEQ_ADDR56 - [13:0] */
+
+/*
+ * R12513 (0x30E1) - Write Sequencer 225
+ */
+#define WM8994_WSEQ_DATA56_MASK 0x00FF /* WSEQ_DATA56 - [7:0] */
+#define WM8994_WSEQ_DATA56_SHIFT 0 /* WSEQ_DATA56 - [7:0] */
+#define WM8994_WSEQ_DATA56_WIDTH 8 /* WSEQ_DATA56 - [7:0] */
+
+/*
+ * R12514 (0x30E2) - Write Sequencer 226
+ */
+#define WM8994_WSEQ_DATA_WIDTH56_MASK 0x0700 /* WSEQ_DATA_WIDTH56 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH56_SHIFT 8 /* WSEQ_DATA_WIDTH56 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH56_WIDTH 3 /* WSEQ_DATA_WIDTH56 - [10:8] */
+#define WM8994_WSEQ_DATA_START56_MASK 0x000F /* WSEQ_DATA_START56 - [3:0] */
+#define WM8994_WSEQ_DATA_START56_SHIFT 0 /* WSEQ_DATA_START56 - [3:0] */
+#define WM8994_WSEQ_DATA_START56_WIDTH 4 /* WSEQ_DATA_START56 - [3:0] */
+
+/*
+ * R12515 (0x30E3) - Write Sequencer 227
+ */
+#define WM8994_WSEQ_EOS56 0x0100 /* WSEQ_EOS56 */
+#define WM8994_WSEQ_EOS56_MASK 0x0100 /* WSEQ_EOS56 */
+#define WM8994_WSEQ_EOS56_SHIFT 8 /* WSEQ_EOS56 */
+#define WM8994_WSEQ_EOS56_WIDTH 1 /* WSEQ_EOS56 */
+#define WM8994_WSEQ_DELAY56_MASK 0x000F /* WSEQ_DELAY56 - [3:0] */
+#define WM8994_WSEQ_DELAY56_SHIFT 0 /* WSEQ_DELAY56 - [3:0] */
+#define WM8994_WSEQ_DELAY56_WIDTH 4 /* WSEQ_DELAY56 - [3:0] */
+
+/*
+ * R12516 (0x30E4) - Write Sequencer 228
+ */
+#define WM8994_WSEQ_ADDR57_MASK 0x3FFF /* WSEQ_ADDR57 - [13:0] */
+#define WM8994_WSEQ_ADDR57_SHIFT 0 /* WSEQ_ADDR57 - [13:0] */
+#define WM8994_WSEQ_ADDR57_WIDTH 14 /* WSEQ_ADDR57 - [13:0] */
+
+/*
+ * R12517 (0x30E5) - Write Sequencer 229
+ */
+#define WM8994_WSEQ_DATA57_MASK 0x00FF /* WSEQ_DATA57 - [7:0] */
+#define WM8994_WSEQ_DATA57_SHIFT 0 /* WSEQ_DATA57 - [7:0] */
+#define WM8994_WSEQ_DATA57_WIDTH 8 /* WSEQ_DATA57 - [7:0] */
+
+/*
+ * R12518 (0x30E6) - Write Sequencer 230
+ */
+#define WM8994_WSEQ_DATA_WIDTH57_MASK 0x0700 /* WSEQ_DATA_WIDTH57 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH57_SHIFT 8 /* WSEQ_DATA_WIDTH57 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH57_WIDTH 3 /* WSEQ_DATA_WIDTH57 - [10:8] */
+#define WM8994_WSEQ_DATA_START57_MASK 0x000F /* WSEQ_DATA_START57 - [3:0] */
+#define WM8994_WSEQ_DATA_START57_SHIFT 0 /* WSEQ_DATA_START57 - [3:0] */
+#define WM8994_WSEQ_DATA_START57_WIDTH 4 /* WSEQ_DATA_START57 - [3:0] */
+
+/*
+ * R12519 (0x30E7) - Write Sequencer 231
+ */
+#define WM8994_WSEQ_EOS57 0x0100 /* WSEQ_EOS57 */
+#define WM8994_WSEQ_EOS57_MASK 0x0100 /* WSEQ_EOS57 */
+#define WM8994_WSEQ_EOS57_SHIFT 8 /* WSEQ_EOS57 */
+#define WM8994_WSEQ_EOS57_WIDTH 1 /* WSEQ_EOS57 */
+#define WM8994_WSEQ_DELAY57_MASK 0x000F /* WSEQ_DELAY57 - [3:0] */
+#define WM8994_WSEQ_DELAY57_SHIFT 0 /* WSEQ_DELAY57 - [3:0] */
+#define WM8994_WSEQ_DELAY57_WIDTH 4 /* WSEQ_DELAY57 - [3:0] */
+
+/*
+ * R12520 (0x30E8) - Write Sequencer 232
+ */
+#define WM8994_WSEQ_ADDR58_MASK 0x3FFF /* WSEQ_ADDR58 - [13:0] */
+#define WM8994_WSEQ_ADDR58_SHIFT 0 /* WSEQ_ADDR58 - [13:0] */
+#define WM8994_WSEQ_ADDR58_WIDTH 14 /* WSEQ_ADDR58 - [13:0] */
+
+/*
+ * R12521 (0x30E9) - Write Sequencer 233
+ */
+#define WM8994_WSEQ_DATA58_MASK 0x00FF /* WSEQ_DATA58 - [7:0] */
+#define WM8994_WSEQ_DATA58_SHIFT 0 /* WSEQ_DATA58 - [7:0] */
+#define WM8994_WSEQ_DATA58_WIDTH 8 /* WSEQ_DATA58 - [7:0] */
+
+/*
+ * R12522 (0x30EA) - Write Sequencer 234
+ */
+#define WM8994_WSEQ_DATA_WIDTH58_MASK 0x0700 /* WSEQ_DATA_WIDTH58 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH58_SHIFT 8 /* WSEQ_DATA_WIDTH58 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH58_WIDTH 3 /* WSEQ_DATA_WIDTH58 - [10:8] */
+#define WM8994_WSEQ_DATA_START58_MASK 0x000F /* WSEQ_DATA_START58 - [3:0] */
+#define WM8994_WSEQ_DATA_START58_SHIFT 0 /* WSEQ_DATA_START58 - [3:0] */
+#define WM8994_WSEQ_DATA_START58_WIDTH 4 /* WSEQ_DATA_START58 - [3:0] */
+
+/*
+ * R12523 (0x30EB) - Write Sequencer 235
+ */
+#define WM8994_WSEQ_EOS58 0x0100 /* WSEQ_EOS58 */
+#define WM8994_WSEQ_EOS58_MASK 0x0100 /* WSEQ_EOS58 */
+#define WM8994_WSEQ_EOS58_SHIFT 8 /* WSEQ_EOS58 */
+#define WM8994_WSEQ_EOS58_WIDTH 1 /* WSEQ_EOS58 */
+#define WM8994_WSEQ_DELAY58_MASK 0x000F /* WSEQ_DELAY58 - [3:0] */
+#define WM8994_WSEQ_DELAY58_SHIFT 0 /* WSEQ_DELAY58 - [3:0] */
+#define WM8994_WSEQ_DELAY58_WIDTH 4 /* WSEQ_DELAY58 - [3:0] */
+
+/*
+ * R12524 (0x30EC) - Write Sequencer 236
+ */
+#define WM8994_WSEQ_ADDR59_MASK 0x3FFF /* WSEQ_ADDR59 - [13:0] */
+#define WM8994_WSEQ_ADDR59_SHIFT 0 /* WSEQ_ADDR59 - [13:0] */
+#define WM8994_WSEQ_ADDR59_WIDTH 14 /* WSEQ_ADDR59 - [13:0] */
+
+/*
+ * R12525 (0x30ED) - Write Sequencer 237
+ */
+#define WM8994_WSEQ_DATA59_MASK 0x00FF /* WSEQ_DATA59 - [7:0] */
+#define WM8994_WSEQ_DATA59_SHIFT 0 /* WSEQ_DATA59 - [7:0] */
+#define WM8994_WSEQ_DATA59_WIDTH 8 /* WSEQ_DATA59 - [7:0] */
+
+/*
+ * R12526 (0x30EE) - Write Sequencer 238
+ */
+#define WM8994_WSEQ_DATA_WIDTH59_MASK 0x0700 /* WSEQ_DATA_WIDTH59 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH59_SHIFT 8 /* WSEQ_DATA_WIDTH59 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH59_WIDTH 3 /* WSEQ_DATA_WIDTH59 - [10:8] */
+#define WM8994_WSEQ_DATA_START59_MASK 0x000F /* WSEQ_DATA_START59 - [3:0] */
+#define WM8994_WSEQ_DATA_START59_SHIFT 0 /* WSEQ_DATA_START59 - [3:0] */
+#define WM8994_WSEQ_DATA_START59_WIDTH 4 /* WSEQ_DATA_START59 - [3:0] */
+
+/*
+ * R12527 (0x30EF) - Write Sequencer 239
+ */
+#define WM8994_WSEQ_EOS59 0x0100 /* WSEQ_EOS59 */
+#define WM8994_WSEQ_EOS59_MASK 0x0100 /* WSEQ_EOS59 */
+#define WM8994_WSEQ_EOS59_SHIFT 8 /* WSEQ_EOS59 */
+#define WM8994_WSEQ_EOS59_WIDTH 1 /* WSEQ_EOS59 */
+#define WM8994_WSEQ_DELAY59_MASK 0x000F /* WSEQ_DELAY59 - [3:0] */
+#define WM8994_WSEQ_DELAY59_SHIFT 0 /* WSEQ_DELAY59 - [3:0] */
+#define WM8994_WSEQ_DELAY59_WIDTH 4 /* WSEQ_DELAY59 - [3:0] */
+
+/*
+ * R12528 (0x30F0) - Write Sequencer 240
+ */
+#define WM8994_WSEQ_ADDR60_MASK 0x3FFF /* WSEQ_ADDR60 - [13:0] */
+#define WM8994_WSEQ_ADDR60_SHIFT 0 /* WSEQ_ADDR60 - [13:0] */
+#define WM8994_WSEQ_ADDR60_WIDTH 14 /* WSEQ_ADDR60 - [13:0] */
+
+/*
+ * R12529 (0x30F1) - Write Sequencer 241
+ */
+#define WM8994_WSEQ_DATA60_MASK 0x00FF /* WSEQ_DATA60 - [7:0] */
+#define WM8994_WSEQ_DATA60_SHIFT 0 /* WSEQ_DATA60 - [7:0] */
+#define WM8994_WSEQ_DATA60_WIDTH 8 /* WSEQ_DATA60 - [7:0] */
+
+/*
+ * R12530 (0x30F2) - Write Sequencer 242
+ */
+#define WM8994_WSEQ_DATA_WIDTH60_MASK 0x0700 /* WSEQ_DATA_WIDTH60 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH60_SHIFT 8 /* WSEQ_DATA_WIDTH60 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH60_WIDTH 3 /* WSEQ_DATA_WIDTH60 - [10:8] */
+#define WM8994_WSEQ_DATA_START60_MASK 0x000F /* WSEQ_DATA_START60 - [3:0] */
+#define WM8994_WSEQ_DATA_START60_SHIFT 0 /* WSEQ_DATA_START60 - [3:0] */
+#define WM8994_WSEQ_DATA_START60_WIDTH 4 /* WSEQ_DATA_START60 - [3:0] */
+
+/*
+ * R12531 (0x30F3) - Write Sequencer 243
+ */
+#define WM8994_WSEQ_EOS60 0x0100 /* WSEQ_EOS60 */
+#define WM8994_WSEQ_EOS60_MASK 0x0100 /* WSEQ_EOS60 */
+#define WM8994_WSEQ_EOS60_SHIFT 8 /* WSEQ_EOS60 */
+#define WM8994_WSEQ_EOS60_WIDTH 1 /* WSEQ_EOS60 */
+#define WM8994_WSEQ_DELAY60_MASK 0x000F /* WSEQ_DELAY60 - [3:0] */
+#define WM8994_WSEQ_DELAY60_SHIFT 0 /* WSEQ_DELAY60 - [3:0] */
+#define WM8994_WSEQ_DELAY60_WIDTH 4 /* WSEQ_DELAY60 - [3:0] */
+
+/*
+ * R12532 (0x30F4) - Write Sequencer 244
+ */
+#define WM8994_WSEQ_ADDR61_MASK 0x3FFF /* WSEQ_ADDR61 - [13:0] */
+#define WM8994_WSEQ_ADDR61_SHIFT 0 /* WSEQ_ADDR61 - [13:0] */
+#define WM8994_WSEQ_ADDR61_WIDTH 14 /* WSEQ_ADDR61 - [13:0] */
+
+/*
+ * R12533 (0x30F5) - Write Sequencer 245
+ */
+#define WM8994_WSEQ_DATA61_MASK 0x00FF /* WSEQ_DATA61 - [7:0] */
+#define WM8994_WSEQ_DATA61_SHIFT 0 /* WSEQ_DATA61 - [7:0] */
+#define WM8994_WSEQ_DATA61_WIDTH 8 /* WSEQ_DATA61 - [7:0] */
+
+/*
+ * R12534 (0x30F6) - Write Sequencer 246
+ */
+#define WM8994_WSEQ_DATA_WIDTH61_MASK 0x0700 /* WSEQ_DATA_WIDTH61 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH61_SHIFT 8 /* WSEQ_DATA_WIDTH61 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH61_WIDTH 3 /* WSEQ_DATA_WIDTH61 - [10:8] */
+#define WM8994_WSEQ_DATA_START61_MASK 0x000F /* WSEQ_DATA_START61 - [3:0] */
+#define WM8994_WSEQ_DATA_START61_SHIFT 0 /* WSEQ_DATA_START61 - [3:0] */
+#define WM8994_WSEQ_DATA_START61_WIDTH 4 /* WSEQ_DATA_START61 - [3:0] */
+
+/*
+ * R12535 (0x30F7) - Write Sequencer 247
+ */
+#define WM8994_WSEQ_EOS61 0x0100 /* WSEQ_EOS61 */
+#define WM8994_WSEQ_EOS61_MASK 0x0100 /* WSEQ_EOS61 */
+#define WM8994_WSEQ_EOS61_SHIFT 8 /* WSEQ_EOS61 */
+#define WM8994_WSEQ_EOS61_WIDTH 1 /* WSEQ_EOS61 */
+#define WM8994_WSEQ_DELAY61_MASK 0x000F /* WSEQ_DELAY61 - [3:0] */
+#define WM8994_WSEQ_DELAY61_SHIFT 0 /* WSEQ_DELAY61 - [3:0] */
+#define WM8994_WSEQ_DELAY61_WIDTH 4 /* WSEQ_DELAY61 - [3:0] */
+
+/*
+ * R12536 (0x30F8) - Write Sequencer 248
+ */
+#define WM8994_WSEQ_ADDR62_MASK 0x3FFF /* WSEQ_ADDR62 - [13:0] */
+#define WM8994_WSEQ_ADDR62_SHIFT 0 /* WSEQ_ADDR62 - [13:0] */
+#define WM8994_WSEQ_ADDR62_WIDTH 14 /* WSEQ_ADDR62 - [13:0] */
+
+/*
+ * R12537 (0x30F9) - Write Sequencer 249
+ */
+#define WM8994_WSEQ_DATA62_MASK 0x00FF /* WSEQ_DATA62 - [7:0] */
+#define WM8994_WSEQ_DATA62_SHIFT 0 /* WSEQ_DATA62 - [7:0] */
+#define WM8994_WSEQ_DATA62_WIDTH 8 /* WSEQ_DATA62 - [7:0] */
+
+/*
+ * R12538 (0x30FA) - Write Sequencer 250
+ */
+#define WM8994_WSEQ_DATA_WIDTH62_MASK 0x0700 /* WSEQ_DATA_WIDTH62 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH62_SHIFT 8 /* WSEQ_DATA_WIDTH62 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH62_WIDTH 3 /* WSEQ_DATA_WIDTH62 - [10:8] */
+#define WM8994_WSEQ_DATA_START62_MASK 0x000F /* WSEQ_DATA_START62 - [3:0] */
+#define WM8994_WSEQ_DATA_START62_SHIFT 0 /* WSEQ_DATA_START62 - [3:0] */
+#define WM8994_WSEQ_DATA_START62_WIDTH 4 /* WSEQ_DATA_START62 - [3:0] */
+
+/*
+ * R12539 (0x30FB) - Write Sequencer 251
+ */
+#define WM8994_WSEQ_EOS62 0x0100 /* WSEQ_EOS62 */
+#define WM8994_WSEQ_EOS62_MASK 0x0100 /* WSEQ_EOS62 */
+#define WM8994_WSEQ_EOS62_SHIFT 8 /* WSEQ_EOS62 */
+#define WM8994_WSEQ_EOS62_WIDTH 1 /* WSEQ_EOS62 */
+#define WM8994_WSEQ_DELAY62_MASK 0x000F /* WSEQ_DELAY62 - [3:0] */
+#define WM8994_WSEQ_DELAY62_SHIFT 0 /* WSEQ_DELAY62 - [3:0] */
+#define WM8994_WSEQ_DELAY62_WIDTH 4 /* WSEQ_DELAY62 - [3:0] */
+
+/*
+ * R12540 (0x30FC) - Write Sequencer 252
+ */
+#define WM8994_WSEQ_ADDR63_MASK 0x3FFF /* WSEQ_ADDR63 - [13:0] */
+#define WM8994_WSEQ_ADDR63_SHIFT 0 /* WSEQ_ADDR63 - [13:0] */
+#define WM8994_WSEQ_ADDR63_WIDTH 14 /* WSEQ_ADDR63 - [13:0] */
+
+/*
+ * R12541 (0x30FD) - Write Sequencer 253
+ */
+#define WM8994_WSEQ_DATA63_MASK 0x00FF /* WSEQ_DATA63 - [7:0] */
+#define WM8994_WSEQ_DATA63_SHIFT 0 /* WSEQ_DATA63 - [7:0] */
+#define WM8994_WSEQ_DATA63_WIDTH 8 /* WSEQ_DATA63 - [7:0] */
+
+/*
+ * R12542 (0x30FE) - Write Sequencer 254
+ */
+#define WM8994_WSEQ_DATA_WIDTH63_MASK 0x0700 /* WSEQ_DATA_WIDTH63 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH63_SHIFT 8 /* WSEQ_DATA_WIDTH63 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH63_WIDTH 3 /* WSEQ_DATA_WIDTH63 - [10:8] */
+#define WM8994_WSEQ_DATA_START63_MASK 0x000F /* WSEQ_DATA_START63 - [3:0] */
+#define WM8994_WSEQ_DATA_START63_SHIFT 0 /* WSEQ_DATA_START63 - [3:0] */
+#define WM8994_WSEQ_DATA_START63_WIDTH 4 /* WSEQ_DATA_START63 - [3:0] */
+
+/*
+ * R12543 (0x30FF) - Write Sequencer 255
+ */
+#define WM8994_WSEQ_EOS63 0x0100 /* WSEQ_EOS63 */
+#define WM8994_WSEQ_EOS63_MASK 0x0100 /* WSEQ_EOS63 */
+#define WM8994_WSEQ_EOS63_SHIFT 8 /* WSEQ_EOS63 */
+#define WM8994_WSEQ_EOS63_WIDTH 1 /* WSEQ_EOS63 */
+#define WM8994_WSEQ_DELAY63_MASK 0x000F /* WSEQ_DELAY63 - [3:0] */
+#define WM8994_WSEQ_DELAY63_SHIFT 0 /* WSEQ_DELAY63 - [3:0] */
+#define WM8994_WSEQ_DELAY63_WIDTH 4 /* WSEQ_DELAY63 - [3:0] */
+
+/*
+ * R12544 (0x3100) - Write Sequencer 256
+ */
+#define WM8994_WSEQ_ADDR64_MASK 0x3FFF /* WSEQ_ADDR64 - [13:0] */
+#define WM8994_WSEQ_ADDR64_SHIFT 0 /* WSEQ_ADDR64 - [13:0] */
+#define WM8994_WSEQ_ADDR64_WIDTH 14 /* WSEQ_ADDR64 - [13:0] */
+
+/*
+ * R12545 (0x3101) - Write Sequencer 257
+ */
+#define WM8994_WSEQ_DATA64_MASK 0x00FF /* WSEQ_DATA64 - [7:0] */
+#define WM8994_WSEQ_DATA64_SHIFT 0 /* WSEQ_DATA64 - [7:0] */
+#define WM8994_WSEQ_DATA64_WIDTH 8 /* WSEQ_DATA64 - [7:0] */
+
+/*
+ * R12546 (0x3102) - Write Sequencer 258
+ */
+#define WM8994_WSEQ_DATA_WIDTH64_MASK 0x0700 /* WSEQ_DATA_WIDTH64 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH64_SHIFT 8 /* WSEQ_DATA_WIDTH64 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH64_WIDTH 3 /* WSEQ_DATA_WIDTH64 - [10:8] */
+#define WM8994_WSEQ_DATA_START64_MASK 0x000F /* WSEQ_DATA_START64 - [3:0] */
+#define WM8994_WSEQ_DATA_START64_SHIFT 0 /* WSEQ_DATA_START64 - [3:0] */
+#define WM8994_WSEQ_DATA_START64_WIDTH 4 /* WSEQ_DATA_START64 - [3:0] */
+
+/*
+ * R12547 (0x3103) - Write Sequencer 259
+ */
+#define WM8994_WSEQ_EOS64 0x0100 /* WSEQ_EOS64 */
+#define WM8994_WSEQ_EOS64_MASK 0x0100 /* WSEQ_EOS64 */
+#define WM8994_WSEQ_EOS64_SHIFT 8 /* WSEQ_EOS64 */
+#define WM8994_WSEQ_EOS64_WIDTH 1 /* WSEQ_EOS64 */
+#define WM8994_WSEQ_DELAY64_MASK 0x000F /* WSEQ_DELAY64 - [3:0] */
+#define WM8994_WSEQ_DELAY64_SHIFT 0 /* WSEQ_DELAY64 - [3:0] */
+#define WM8994_WSEQ_DELAY64_WIDTH 4 /* WSEQ_DELAY64 - [3:0] */
+
+/*
+ * R12548 (0x3104) - Write Sequencer 260
+ */
+#define WM8994_WSEQ_ADDR65_MASK 0x3FFF /* WSEQ_ADDR65 - [13:0] */
+#define WM8994_WSEQ_ADDR65_SHIFT 0 /* WSEQ_ADDR65 - [13:0] */
+#define WM8994_WSEQ_ADDR65_WIDTH 14 /* WSEQ_ADDR65 - [13:0] */
+
+/*
+ * R12549 (0x3105) - Write Sequencer 261
+ */
+#define WM8994_WSEQ_DATA65_MASK 0x00FF /* WSEQ_DATA65 - [7:0] */
+#define WM8994_WSEQ_DATA65_SHIFT 0 /* WSEQ_DATA65 - [7:0] */
+#define WM8994_WSEQ_DATA65_WIDTH 8 /* WSEQ_DATA65 - [7:0] */
+
+/*
+ * R12550 (0x3106) - Write Sequencer 262
+ */
+#define WM8994_WSEQ_DATA_WIDTH65_MASK 0x0700 /* WSEQ_DATA_WIDTH65 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH65_SHIFT 8 /* WSEQ_DATA_WIDTH65 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH65_WIDTH 3 /* WSEQ_DATA_WIDTH65 - [10:8] */
+#define WM8994_WSEQ_DATA_START65_MASK 0x000F /* WSEQ_DATA_START65 - [3:0] */
+#define WM8994_WSEQ_DATA_START65_SHIFT 0 /* WSEQ_DATA_START65 - [3:0] */
+#define WM8994_WSEQ_DATA_START65_WIDTH 4 /* WSEQ_DATA_START65 - [3:0] */
+
+/*
+ * R12551 (0x3107) - Write Sequencer 263
+ */
+#define WM8994_WSEQ_EOS65 0x0100 /* WSEQ_EOS65 */
+#define WM8994_WSEQ_EOS65_MASK 0x0100 /* WSEQ_EOS65 */
+#define WM8994_WSEQ_EOS65_SHIFT 8 /* WSEQ_EOS65 */
+#define WM8994_WSEQ_EOS65_WIDTH 1 /* WSEQ_EOS65 */
+#define WM8994_WSEQ_DELAY65_MASK 0x000F /* WSEQ_DELAY65 - [3:0] */
+#define WM8994_WSEQ_DELAY65_SHIFT 0 /* WSEQ_DELAY65 - [3:0] */
+#define WM8994_WSEQ_DELAY65_WIDTH 4 /* WSEQ_DELAY65 - [3:0] */
+
+/*
+ * R12552 (0x3108) - Write Sequencer 264
+ */
+#define WM8994_WSEQ_ADDR66_MASK 0x3FFF /* WSEQ_ADDR66 - [13:0] */
+#define WM8994_WSEQ_ADDR66_SHIFT 0 /* WSEQ_ADDR66 - [13:0] */
+#define WM8994_WSEQ_ADDR66_WIDTH 14 /* WSEQ_ADDR66 - [13:0] */
+
+/*
+ * R12553 (0x3109) - Write Sequencer 265
+ */
+#define WM8994_WSEQ_DATA66_MASK 0x00FF /* WSEQ_DATA66 - [7:0] */
+#define WM8994_WSEQ_DATA66_SHIFT 0 /* WSEQ_DATA66 - [7:0] */
+#define WM8994_WSEQ_DATA66_WIDTH 8 /* WSEQ_DATA66 - [7:0] */
+
+/*
+ * R12554 (0x310A) - Write Sequencer 266
+ */
+#define WM8994_WSEQ_DATA_WIDTH66_MASK 0x0700 /* WSEQ_DATA_WIDTH66 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH66_SHIFT 8 /* WSEQ_DATA_WIDTH66 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH66_WIDTH 3 /* WSEQ_DATA_WIDTH66 - [10:8] */
+#define WM8994_WSEQ_DATA_START66_MASK 0x000F /* WSEQ_DATA_START66 - [3:0] */
+#define WM8994_WSEQ_DATA_START66_SHIFT 0 /* WSEQ_DATA_START66 - [3:0] */
+#define WM8994_WSEQ_DATA_START66_WIDTH 4 /* WSEQ_DATA_START66 - [3:0] */
+
+/*
+ * R12555 (0x310B) - Write Sequencer 267
+ */
+#define WM8994_WSEQ_EOS66 0x0100 /* WSEQ_EOS66 */
+#define WM8994_WSEQ_EOS66_MASK 0x0100 /* WSEQ_EOS66 */
+#define WM8994_WSEQ_EOS66_SHIFT 8 /* WSEQ_EOS66 */
+#define WM8994_WSEQ_EOS66_WIDTH 1 /* WSEQ_EOS66 */
+#define WM8994_WSEQ_DELAY66_MASK 0x000F /* WSEQ_DELAY66 - [3:0] */
+#define WM8994_WSEQ_DELAY66_SHIFT 0 /* WSEQ_DELAY66 - [3:0] */
+#define WM8994_WSEQ_DELAY66_WIDTH 4 /* WSEQ_DELAY66 - [3:0] */
+
+/*
+ * R12556 (0x310C) - Write Sequencer 268
+ */
+#define WM8994_WSEQ_ADDR67_MASK 0x3FFF /* WSEQ_ADDR67 - [13:0] */
+#define WM8994_WSEQ_ADDR67_SHIFT 0 /* WSEQ_ADDR67 - [13:0] */
+#define WM8994_WSEQ_ADDR67_WIDTH 14 /* WSEQ_ADDR67 - [13:0] */
+
+/*
+ * R12557 (0x310D) - Write Sequencer 269
+ */
+#define WM8994_WSEQ_DATA67_MASK 0x00FF /* WSEQ_DATA67 - [7:0] */
+#define WM8994_WSEQ_DATA67_SHIFT 0 /* WSEQ_DATA67 - [7:0] */
+#define WM8994_WSEQ_DATA67_WIDTH 8 /* WSEQ_DATA67 - [7:0] */
+
+/*
+ * R12558 (0x310E) - Write Sequencer 270
+ */
+#define WM8994_WSEQ_DATA_WIDTH67_MASK 0x0700 /* WSEQ_DATA_WIDTH67 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH67_SHIFT 8 /* WSEQ_DATA_WIDTH67 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH67_WIDTH 3 /* WSEQ_DATA_WIDTH67 - [10:8] */
+#define WM8994_WSEQ_DATA_START67_MASK 0x000F /* WSEQ_DATA_START67 - [3:0] */
+#define WM8994_WSEQ_DATA_START67_SHIFT 0 /* WSEQ_DATA_START67 - [3:0] */
+#define WM8994_WSEQ_DATA_START67_WIDTH 4 /* WSEQ_DATA_START67 - [3:0] */
+
+/*
+ * R12559 (0x310F) - Write Sequencer 271
+ */
+#define WM8994_WSEQ_EOS67 0x0100 /* WSEQ_EOS67 */
+#define WM8994_WSEQ_EOS67_MASK 0x0100 /* WSEQ_EOS67 */
+#define WM8994_WSEQ_EOS67_SHIFT 8 /* WSEQ_EOS67 */
+#define WM8994_WSEQ_EOS67_WIDTH 1 /* WSEQ_EOS67 */
+#define WM8994_WSEQ_DELAY67_MASK 0x000F /* WSEQ_DELAY67 - [3:0] */
+#define WM8994_WSEQ_DELAY67_SHIFT 0 /* WSEQ_DELAY67 - [3:0] */
+#define WM8994_WSEQ_DELAY67_WIDTH 4 /* WSEQ_DELAY67 - [3:0] */
+
+/*
+ * R12560 (0x3110) - Write Sequencer 272
+ */
+#define WM8994_WSEQ_ADDR68_MASK 0x3FFF /* WSEQ_ADDR68 - [13:0] */
+#define WM8994_WSEQ_ADDR68_SHIFT 0 /* WSEQ_ADDR68 - [13:0] */
+#define WM8994_WSEQ_ADDR68_WIDTH 14 /* WSEQ_ADDR68 - [13:0] */
+
+/*
+ * R12561 (0x3111) - Write Sequencer 273
+ */
+#define WM8994_WSEQ_DATA68_MASK 0x00FF /* WSEQ_DATA68 - [7:0] */
+#define WM8994_WSEQ_DATA68_SHIFT 0 /* WSEQ_DATA68 - [7:0] */
+#define WM8994_WSEQ_DATA68_WIDTH 8 /* WSEQ_DATA68 - [7:0] */
+
+/*
+ * R12562 (0x3112) - Write Sequencer 274
+ */
+#define WM8994_WSEQ_DATA_WIDTH68_MASK 0x0700 /* WSEQ_DATA_WIDTH68 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH68_SHIFT 8 /* WSEQ_DATA_WIDTH68 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH68_WIDTH 3 /* WSEQ_DATA_WIDTH68 - [10:8] */
+#define WM8994_WSEQ_DATA_START68_MASK 0x000F /* WSEQ_DATA_START68 - [3:0] */
+#define WM8994_WSEQ_DATA_START68_SHIFT 0 /* WSEQ_DATA_START68 - [3:0] */
+#define WM8994_WSEQ_DATA_START68_WIDTH 4 /* WSEQ_DATA_START68 - [3:0] */
+
+/*
+ * R12563 (0x3113) - Write Sequencer 275
+ */
+#define WM8994_WSEQ_EOS68 0x0100 /* WSEQ_EOS68 */
+#define WM8994_WSEQ_EOS68_MASK 0x0100 /* WSEQ_EOS68 */
+#define WM8994_WSEQ_EOS68_SHIFT 8 /* WSEQ_EOS68 */
+#define WM8994_WSEQ_EOS68_WIDTH 1 /* WSEQ_EOS68 */
+#define WM8994_WSEQ_DELAY68_MASK 0x000F /* WSEQ_DELAY68 - [3:0] */
+#define WM8994_WSEQ_DELAY68_SHIFT 0 /* WSEQ_DELAY68 - [3:0] */
+#define WM8994_WSEQ_DELAY68_WIDTH 4 /* WSEQ_DELAY68 - [3:0] */
+
+/*
+ * R12564 (0x3114) - Write Sequencer 276
+ */
+#define WM8994_WSEQ_ADDR69_MASK 0x3FFF /* WSEQ_ADDR69 - [13:0] */
+#define WM8994_WSEQ_ADDR69_SHIFT 0 /* WSEQ_ADDR69 - [13:0] */
+#define WM8994_WSEQ_ADDR69_WIDTH 14 /* WSEQ_ADDR69 - [13:0] */
+
+/*
+ * R12565 (0x3115) - Write Sequencer 277
+ */
+#define WM8994_WSEQ_DATA69_MASK 0x00FF /* WSEQ_DATA69 - [7:0] */
+#define WM8994_WSEQ_DATA69_SHIFT 0 /* WSEQ_DATA69 - [7:0] */
+#define WM8994_WSEQ_DATA69_WIDTH 8 /* WSEQ_DATA69 - [7:0] */
+
+/*
+ * R12566 (0x3116) - Write Sequencer 278
+ */
+#define WM8994_WSEQ_DATA_WIDTH69_MASK 0x0700 /* WSEQ_DATA_WIDTH69 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH69_SHIFT 8 /* WSEQ_DATA_WIDTH69 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH69_WIDTH 3 /* WSEQ_DATA_WIDTH69 - [10:8] */
+#define WM8994_WSEQ_DATA_START69_MASK 0x000F /* WSEQ_DATA_START69 - [3:0] */
+#define WM8994_WSEQ_DATA_START69_SHIFT 0 /* WSEQ_DATA_START69 - [3:0] */
+#define WM8994_WSEQ_DATA_START69_WIDTH 4 /* WSEQ_DATA_START69 - [3:0] */
+
+/*
+ * R12567 (0x3117) - Write Sequencer 279
+ */
+#define WM8994_WSEQ_EOS69 0x0100 /* WSEQ_EOS69 */
+#define WM8994_WSEQ_EOS69_MASK 0x0100 /* WSEQ_EOS69 */
+#define WM8994_WSEQ_EOS69_SHIFT 8 /* WSEQ_EOS69 */
+#define WM8994_WSEQ_EOS69_WIDTH 1 /* WSEQ_EOS69 */
+#define WM8994_WSEQ_DELAY69_MASK 0x000F /* WSEQ_DELAY69 - [3:0] */
+#define WM8994_WSEQ_DELAY69_SHIFT 0 /* WSEQ_DELAY69 - [3:0] */
+#define WM8994_WSEQ_DELAY69_WIDTH 4 /* WSEQ_DELAY69 - [3:0] */
+
+/*
+ * R12568 (0x3118) - Write Sequencer 280
+ */
+#define WM8994_WSEQ_ADDR70_MASK 0x3FFF /* WSEQ_ADDR70 - [13:0] */
+#define WM8994_WSEQ_ADDR70_SHIFT 0 /* WSEQ_ADDR70 - [13:0] */
+#define WM8994_WSEQ_ADDR70_WIDTH 14 /* WSEQ_ADDR70 - [13:0] */
+
+/*
+ * R12569 (0x3119) - Write Sequencer 281
+ */
+#define WM8994_WSEQ_DATA70_MASK 0x00FF /* WSEQ_DATA70 - [7:0] */
+#define WM8994_WSEQ_DATA70_SHIFT 0 /* WSEQ_DATA70 - [7:0] */
+#define WM8994_WSEQ_DATA70_WIDTH 8 /* WSEQ_DATA70 - [7:0] */
+
+/*
+ * R12570 (0x311A) - Write Sequencer 282
+ */
+#define WM8994_WSEQ_DATA_WIDTH70_MASK 0x0700 /* WSEQ_DATA_WIDTH70 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH70_SHIFT 8 /* WSEQ_DATA_WIDTH70 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH70_WIDTH 3 /* WSEQ_DATA_WIDTH70 - [10:8] */
+#define WM8994_WSEQ_DATA_START70_MASK 0x000F /* WSEQ_DATA_START70 - [3:0] */
+#define WM8994_WSEQ_DATA_START70_SHIFT 0 /* WSEQ_DATA_START70 - [3:0] */
+#define WM8994_WSEQ_DATA_START70_WIDTH 4 /* WSEQ_DATA_START70 - [3:0] */
+
+/*
+ * R12571 (0x311B) - Write Sequencer 283
+ */
+#define WM8994_WSEQ_EOS70 0x0100 /* WSEQ_EOS70 */
+#define WM8994_WSEQ_EOS70_MASK 0x0100 /* WSEQ_EOS70 */
+#define WM8994_WSEQ_EOS70_SHIFT 8 /* WSEQ_EOS70 */
+#define WM8994_WSEQ_EOS70_WIDTH 1 /* WSEQ_EOS70 */
+#define WM8994_WSEQ_DELAY70_MASK 0x000F /* WSEQ_DELAY70 - [3:0] */
+#define WM8994_WSEQ_DELAY70_SHIFT 0 /* WSEQ_DELAY70 - [3:0] */
+#define WM8994_WSEQ_DELAY70_WIDTH 4 /* WSEQ_DELAY70 - [3:0] */
+
+/*
+ * R12572 (0x311C) - Write Sequencer 284
+ */
+#define WM8994_WSEQ_ADDR71_MASK 0x3FFF /* WSEQ_ADDR71 - [13:0] */
+#define WM8994_WSEQ_ADDR71_SHIFT 0 /* WSEQ_ADDR71 - [13:0] */
+#define WM8994_WSEQ_ADDR71_WIDTH 14 /* WSEQ_ADDR71 - [13:0] */
+
+/*
+ * R12573 (0x311D) - Write Sequencer 285
+ */
+#define WM8994_WSEQ_DATA71_MASK 0x00FF /* WSEQ_DATA71 - [7:0] */
+#define WM8994_WSEQ_DATA71_SHIFT 0 /* WSEQ_DATA71 - [7:0] */
+#define WM8994_WSEQ_DATA71_WIDTH 8 /* WSEQ_DATA71 - [7:0] */
+
+/*
+ * R12574 (0x311E) - Write Sequencer 286
+ */
+#define WM8994_WSEQ_DATA_WIDTH71_MASK 0x0700 /* WSEQ_DATA_WIDTH71 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH71_SHIFT 8 /* WSEQ_DATA_WIDTH71 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH71_WIDTH 3 /* WSEQ_DATA_WIDTH71 - [10:8] */
+#define WM8994_WSEQ_DATA_START71_MASK 0x000F /* WSEQ_DATA_START71 - [3:0] */
+#define WM8994_WSEQ_DATA_START71_SHIFT 0 /* WSEQ_DATA_START71 - [3:0] */
+#define WM8994_WSEQ_DATA_START71_WIDTH 4 /* WSEQ_DATA_START71 - [3:0] */
+
+/*
+ * R12575 (0x311F) - Write Sequencer 287
+ */
+#define WM8994_WSEQ_EOS71 0x0100 /* WSEQ_EOS71 */
+#define WM8994_WSEQ_EOS71_MASK 0x0100 /* WSEQ_EOS71 */
+#define WM8994_WSEQ_EOS71_SHIFT 8 /* WSEQ_EOS71 */
+#define WM8994_WSEQ_EOS71_WIDTH 1 /* WSEQ_EOS71 */
+#define WM8994_WSEQ_DELAY71_MASK 0x000F /* WSEQ_DELAY71 - [3:0] */
+#define WM8994_WSEQ_DELAY71_SHIFT 0 /* WSEQ_DELAY71 - [3:0] */
+#define WM8994_WSEQ_DELAY71_WIDTH 4 /* WSEQ_DELAY71 - [3:0] */
+
+/*
+ * R12576 (0x3120) - Write Sequencer 288
+ */
+#define WM8994_WSEQ_ADDR72_MASK 0x3FFF /* WSEQ_ADDR72 - [13:0] */
+#define WM8994_WSEQ_ADDR72_SHIFT 0 /* WSEQ_ADDR72 - [13:0] */
+#define WM8994_WSEQ_ADDR72_WIDTH 14 /* WSEQ_ADDR72 - [13:0] */
+
+/*
+ * R12577 (0x3121) - Write Sequencer 289
+ */
+#define WM8994_WSEQ_DATA72_MASK 0x00FF /* WSEQ_DATA72 - [7:0] */
+#define WM8994_WSEQ_DATA72_SHIFT 0 /* WSEQ_DATA72 - [7:0] */
+#define WM8994_WSEQ_DATA72_WIDTH 8 /* WSEQ_DATA72 - [7:0] */
+
+/*
+ * R12578 (0x3122) - Write Sequencer 290
+ */
+#define WM8994_WSEQ_DATA_WIDTH72_MASK 0x0700 /* WSEQ_DATA_WIDTH72 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH72_SHIFT 8 /* WSEQ_DATA_WIDTH72 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH72_WIDTH 3 /* WSEQ_DATA_WIDTH72 - [10:8] */
+#define WM8994_WSEQ_DATA_START72_MASK 0x000F /* WSEQ_DATA_START72 - [3:0] */
+#define WM8994_WSEQ_DATA_START72_SHIFT 0 /* WSEQ_DATA_START72 - [3:0] */
+#define WM8994_WSEQ_DATA_START72_WIDTH 4 /* WSEQ_DATA_START72 - [3:0] */
+
+/*
+ * R12579 (0x3123) - Write Sequencer 291
+ */
+#define WM8994_WSEQ_EOS72 0x0100 /* WSEQ_EOS72 */
+#define WM8994_WSEQ_EOS72_MASK 0x0100 /* WSEQ_EOS72 */
+#define WM8994_WSEQ_EOS72_SHIFT 8 /* WSEQ_EOS72 */
+#define WM8994_WSEQ_EOS72_WIDTH 1 /* WSEQ_EOS72 */
+#define WM8994_WSEQ_DELAY72_MASK 0x000F /* WSEQ_DELAY72 - [3:0] */
+#define WM8994_WSEQ_DELAY72_SHIFT 0 /* WSEQ_DELAY72 - [3:0] */
+#define WM8994_WSEQ_DELAY72_WIDTH 4 /* WSEQ_DELAY72 - [3:0] */
+
+/*
+ * R12580 (0x3124) - Write Sequencer 292
+ */
+#define WM8994_WSEQ_ADDR73_MASK 0x3FFF /* WSEQ_ADDR73 - [13:0] */
+#define WM8994_WSEQ_ADDR73_SHIFT 0 /* WSEQ_ADDR73 - [13:0] */
+#define WM8994_WSEQ_ADDR73_WIDTH 14 /* WSEQ_ADDR73 - [13:0] */
+
+/*
+ * R12581 (0x3125) - Write Sequencer 293
+ */
+#define WM8994_WSEQ_DATA73_MASK 0x00FF /* WSEQ_DATA73 - [7:0] */
+#define WM8994_WSEQ_DATA73_SHIFT 0 /* WSEQ_DATA73 - [7:0] */
+#define WM8994_WSEQ_DATA73_WIDTH 8 /* WSEQ_DATA73 - [7:0] */
+
+/*
+ * R12582 (0x3126) - Write Sequencer 294
+ */
+#define WM8994_WSEQ_DATA_WIDTH73_MASK 0x0700 /* WSEQ_DATA_WIDTH73 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH73_SHIFT 8 /* WSEQ_DATA_WIDTH73 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH73_WIDTH 3 /* WSEQ_DATA_WIDTH73 - [10:8] */
+#define WM8994_WSEQ_DATA_START73_MASK 0x000F /* WSEQ_DATA_START73 - [3:0] */
+#define WM8994_WSEQ_DATA_START73_SHIFT 0 /* WSEQ_DATA_START73 - [3:0] */
+#define WM8994_WSEQ_DATA_START73_WIDTH 4 /* WSEQ_DATA_START73 - [3:0] */
+
+/*
+ * R12583 (0x3127) - Write Sequencer 295
+ */
+#define WM8994_WSEQ_EOS73 0x0100 /* WSEQ_EOS73 */
+#define WM8994_WSEQ_EOS73_MASK 0x0100 /* WSEQ_EOS73 */
+#define WM8994_WSEQ_EOS73_SHIFT 8 /* WSEQ_EOS73 */
+#define WM8994_WSEQ_EOS73_WIDTH 1 /* WSEQ_EOS73 */
+#define WM8994_WSEQ_DELAY73_MASK 0x000F /* WSEQ_DELAY73 - [3:0] */
+#define WM8994_WSEQ_DELAY73_SHIFT 0 /* WSEQ_DELAY73 - [3:0] */
+#define WM8994_WSEQ_DELAY73_WIDTH 4 /* WSEQ_DELAY73 - [3:0] */
+
+/*
+ * R12584 (0x3128) - Write Sequencer 296
+ */
+#define WM8994_WSEQ_ADDR74_MASK 0x3FFF /* WSEQ_ADDR74 - [13:0] */
+#define WM8994_WSEQ_ADDR74_SHIFT 0 /* WSEQ_ADDR74 - [13:0] */
+#define WM8994_WSEQ_ADDR74_WIDTH 14 /* WSEQ_ADDR74 - [13:0] */
+
+/*
+ * R12585 (0x3129) - Write Sequencer 297
+ */
+#define WM8994_WSEQ_DATA74_MASK 0x00FF /* WSEQ_DATA74 - [7:0] */
+#define WM8994_WSEQ_DATA74_SHIFT 0 /* WSEQ_DATA74 - [7:0] */
+#define WM8994_WSEQ_DATA74_WIDTH 8 /* WSEQ_DATA74 - [7:0] */
+
+/*
+ * R12586 (0x312A) - Write Sequencer 298
+ */
+#define WM8994_WSEQ_DATA_WIDTH74_MASK 0x0700 /* WSEQ_DATA_WIDTH74 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH74_SHIFT 8 /* WSEQ_DATA_WIDTH74 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH74_WIDTH 3 /* WSEQ_DATA_WIDTH74 - [10:8] */
+#define WM8994_WSEQ_DATA_START74_MASK 0x000F /* WSEQ_DATA_START74 - [3:0] */
+#define WM8994_WSEQ_DATA_START74_SHIFT 0 /* WSEQ_DATA_START74 - [3:0] */
+#define WM8994_WSEQ_DATA_START74_WIDTH 4 /* WSEQ_DATA_START74 - [3:0] */
+
+/*
+ * R12587 (0x312B) - Write Sequencer 299
+ */
+#define WM8994_WSEQ_EOS74 0x0100 /* WSEQ_EOS74 */
+#define WM8994_WSEQ_EOS74_MASK 0x0100 /* WSEQ_EOS74 */
+#define WM8994_WSEQ_EOS74_SHIFT 8 /* WSEQ_EOS74 */
+#define WM8994_WSEQ_EOS74_WIDTH 1 /* WSEQ_EOS74 */
+#define WM8994_WSEQ_DELAY74_MASK 0x000F /* WSEQ_DELAY74 - [3:0] */
+#define WM8994_WSEQ_DELAY74_SHIFT 0 /* WSEQ_DELAY74 - [3:0] */
+#define WM8994_WSEQ_DELAY74_WIDTH 4 /* WSEQ_DELAY74 - [3:0] */
+
+/*
+ * R12588 (0x312C) - Write Sequencer 300
+ */
+#define WM8994_WSEQ_ADDR75_MASK 0x3FFF /* WSEQ_ADDR75 - [13:0] */
+#define WM8994_WSEQ_ADDR75_SHIFT 0 /* WSEQ_ADDR75 - [13:0] */
+#define WM8994_WSEQ_ADDR75_WIDTH 14 /* WSEQ_ADDR75 - [13:0] */
+
+/*
+ * R12589 (0x312D) - Write Sequencer 301
+ */
+#define WM8994_WSEQ_DATA75_MASK 0x00FF /* WSEQ_DATA75 - [7:0] */
+#define WM8994_WSEQ_DATA75_SHIFT 0 /* WSEQ_DATA75 - [7:0] */
+#define WM8994_WSEQ_DATA75_WIDTH 8 /* WSEQ_DATA75 - [7:0] */
+
+/*
+ * R12590 (0x312E) - Write Sequencer 302
+ */
+#define WM8994_WSEQ_DATA_WIDTH75_MASK 0x0700 /* WSEQ_DATA_WIDTH75 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH75_SHIFT 8 /* WSEQ_DATA_WIDTH75 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH75_WIDTH 3 /* WSEQ_DATA_WIDTH75 - [10:8] */
+#define WM8994_WSEQ_DATA_START75_MASK 0x000F /* WSEQ_DATA_START75 - [3:0] */
+#define WM8994_WSEQ_DATA_START75_SHIFT 0 /* WSEQ_DATA_START75 - [3:0] */
+#define WM8994_WSEQ_DATA_START75_WIDTH 4 /* WSEQ_DATA_START75 - [3:0] */
+
+/*
+ * R12591 (0x312F) - Write Sequencer 303
+ */
+#define WM8994_WSEQ_EOS75 0x0100 /* WSEQ_EOS75 */
+#define WM8994_WSEQ_EOS75_MASK 0x0100 /* WSEQ_EOS75 */
+#define WM8994_WSEQ_EOS75_SHIFT 8 /* WSEQ_EOS75 */
+#define WM8994_WSEQ_EOS75_WIDTH 1 /* WSEQ_EOS75 */
+#define WM8994_WSEQ_DELAY75_MASK 0x000F /* WSEQ_DELAY75 - [3:0] */
+#define WM8994_WSEQ_DELAY75_SHIFT 0 /* WSEQ_DELAY75 - [3:0] */
+#define WM8994_WSEQ_DELAY75_WIDTH 4 /* WSEQ_DELAY75 - [3:0] */
+
+/*
+ * R12592 (0x3130) - Write Sequencer 304
+ */
+#define WM8994_WSEQ_ADDR76_MASK 0x3FFF /* WSEQ_ADDR76 - [13:0] */
+#define WM8994_WSEQ_ADDR76_SHIFT 0 /* WSEQ_ADDR76 - [13:0] */
+#define WM8994_WSEQ_ADDR76_WIDTH 14 /* WSEQ_ADDR76 - [13:0] */
+
+/*
+ * R12593 (0x3131) - Write Sequencer 305
+ */
+#define WM8994_WSEQ_DATA76_MASK 0x00FF /* WSEQ_DATA76 - [7:0] */
+#define WM8994_WSEQ_DATA76_SHIFT 0 /* WSEQ_DATA76 - [7:0] */
+#define WM8994_WSEQ_DATA76_WIDTH 8 /* WSEQ_DATA76 - [7:0] */
+
+/*
+ * R12594 (0x3132) - Write Sequencer 306
+ */
+#define WM8994_WSEQ_DATA_WIDTH76_MASK 0x0700 /* WSEQ_DATA_WIDTH76 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH76_SHIFT 8 /* WSEQ_DATA_WIDTH76 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH76_WIDTH 3 /* WSEQ_DATA_WIDTH76 - [10:8] */
+#define WM8994_WSEQ_DATA_START76_MASK 0x000F /* WSEQ_DATA_START76 - [3:0] */
+#define WM8994_WSEQ_DATA_START76_SHIFT 0 /* WSEQ_DATA_START76 - [3:0] */
+#define WM8994_WSEQ_DATA_START76_WIDTH 4 /* WSEQ_DATA_START76 - [3:0] */
+
+/*
+ * R12595 (0x3133) - Write Sequencer 307
+ */
+#define WM8994_WSEQ_EOS76 0x0100 /* WSEQ_EOS76 */
+#define WM8994_WSEQ_EOS76_MASK 0x0100 /* WSEQ_EOS76 */
+#define WM8994_WSEQ_EOS76_SHIFT 8 /* WSEQ_EOS76 */
+#define WM8994_WSEQ_EOS76_WIDTH 1 /* WSEQ_EOS76 */
+#define WM8994_WSEQ_DELAY76_MASK 0x000F /* WSEQ_DELAY76 - [3:0] */
+#define WM8994_WSEQ_DELAY76_SHIFT 0 /* WSEQ_DELAY76 - [3:0] */
+#define WM8994_WSEQ_DELAY76_WIDTH 4 /* WSEQ_DELAY76 - [3:0] */
+
+/*
+ * R12596 (0x3134) - Write Sequencer 308
+ */
+#define WM8994_WSEQ_ADDR77_MASK 0x3FFF /* WSEQ_ADDR77 - [13:0] */
+#define WM8994_WSEQ_ADDR77_SHIFT 0 /* WSEQ_ADDR77 - [13:0] */
+#define WM8994_WSEQ_ADDR77_WIDTH 14 /* WSEQ_ADDR77 - [13:0] */
+
+/*
+ * R12597 (0x3135) - Write Sequencer 309
+ */
+#define WM8994_WSEQ_DATA77_MASK 0x00FF /* WSEQ_DATA77 - [7:0] */
+#define WM8994_WSEQ_DATA77_SHIFT 0 /* WSEQ_DATA77 - [7:0] */
+#define WM8994_WSEQ_DATA77_WIDTH 8 /* WSEQ_DATA77 - [7:0] */
+
+/*
+ * R12598 (0x3136) - Write Sequencer 310
+ */
+#define WM8994_WSEQ_DATA_WIDTH77_MASK 0x0700 /* WSEQ_DATA_WIDTH77 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH77_SHIFT 8 /* WSEQ_DATA_WIDTH77 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH77_WIDTH 3 /* WSEQ_DATA_WIDTH77 - [10:8] */
+#define WM8994_WSEQ_DATA_START77_MASK 0x000F /* WSEQ_DATA_START77 - [3:0] */
+#define WM8994_WSEQ_DATA_START77_SHIFT 0 /* WSEQ_DATA_START77 - [3:0] */
+#define WM8994_WSEQ_DATA_START77_WIDTH 4 /* WSEQ_DATA_START77 - [3:0] */
+
+/*
+ * R12599 (0x3137) - Write Sequencer 311
+ */
+#define WM8994_WSEQ_EOS77 0x0100 /* WSEQ_EOS77 */
+#define WM8994_WSEQ_EOS77_MASK 0x0100 /* WSEQ_EOS77 */
+#define WM8994_WSEQ_EOS77_SHIFT 8 /* WSEQ_EOS77 */
+#define WM8994_WSEQ_EOS77_WIDTH 1 /* WSEQ_EOS77 */
+#define WM8994_WSEQ_DELAY77_MASK 0x000F /* WSEQ_DELAY77 - [3:0] */
+#define WM8994_WSEQ_DELAY77_SHIFT 0 /* WSEQ_DELAY77 - [3:0] */
+#define WM8994_WSEQ_DELAY77_WIDTH 4 /* WSEQ_DELAY77 - [3:0] */
+
+/*
+ * R12600 (0x3138) - Write Sequencer 312
+ */
+#define WM8994_WSEQ_ADDR78_MASK 0x3FFF /* WSEQ_ADDR78 - [13:0] */
+#define WM8994_WSEQ_ADDR78_SHIFT 0 /* WSEQ_ADDR78 - [13:0] */
+#define WM8994_WSEQ_ADDR78_WIDTH 14 /* WSEQ_ADDR78 - [13:0] */
+
+/*
+ * R12601 (0x3139) - Write Sequencer 313
+ */
+#define WM8994_WSEQ_DATA78_MASK 0x00FF /* WSEQ_DATA78 - [7:0] */
+#define WM8994_WSEQ_DATA78_SHIFT 0 /* WSEQ_DATA78 - [7:0] */
+#define WM8994_WSEQ_DATA78_WIDTH 8 /* WSEQ_DATA78 - [7:0] */
+
+/*
+ * R12602 (0x313A) - Write Sequencer 314
+ */
+#define WM8994_WSEQ_DATA_WIDTH78_MASK 0x0700 /* WSEQ_DATA_WIDTH78 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH78_SHIFT 8 /* WSEQ_DATA_WIDTH78 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH78_WIDTH 3 /* WSEQ_DATA_WIDTH78 - [10:8] */
+#define WM8994_WSEQ_DATA_START78_MASK 0x000F /* WSEQ_DATA_START78 - [3:0] */
+#define WM8994_WSEQ_DATA_START78_SHIFT 0 /* WSEQ_DATA_START78 - [3:0] */
+#define WM8994_WSEQ_DATA_START78_WIDTH 4 /* WSEQ_DATA_START78 - [3:0] */
+
+/*
+ * R12603 (0x313B) - Write Sequencer 315
+ */
+#define WM8994_WSEQ_EOS78 0x0100 /* WSEQ_EOS78 */
+#define WM8994_WSEQ_EOS78_MASK 0x0100 /* WSEQ_EOS78 */
+#define WM8994_WSEQ_EOS78_SHIFT 8 /* WSEQ_EOS78 */
+#define WM8994_WSEQ_EOS78_WIDTH 1 /* WSEQ_EOS78 */
+#define WM8994_WSEQ_DELAY78_MASK 0x000F /* WSEQ_DELAY78 - [3:0] */
+#define WM8994_WSEQ_DELAY78_SHIFT 0 /* WSEQ_DELAY78 - [3:0] */
+#define WM8994_WSEQ_DELAY78_WIDTH 4 /* WSEQ_DELAY78 - [3:0] */
+
+/*
+ * R12604 (0x313C) - Write Sequencer 316
+ */
+#define WM8994_WSEQ_ADDR79_MASK 0x3FFF /* WSEQ_ADDR79 - [13:0] */
+#define WM8994_WSEQ_ADDR79_SHIFT 0 /* WSEQ_ADDR79 - [13:0] */
+#define WM8994_WSEQ_ADDR79_WIDTH 14 /* WSEQ_ADDR79 - [13:0] */
+
+/*
+ * R12605 (0x313D) - Write Sequencer 317
+ */
+#define WM8994_WSEQ_DATA79_MASK 0x00FF /* WSEQ_DATA79 - [7:0] */
+#define WM8994_WSEQ_DATA79_SHIFT 0 /* WSEQ_DATA79 - [7:0] */
+#define WM8994_WSEQ_DATA79_WIDTH 8 /* WSEQ_DATA79 - [7:0] */
+
+/*
+ * R12606 (0x313E) - Write Sequencer 318
+ */
+#define WM8994_WSEQ_DATA_WIDTH79_MASK 0x0700 /* WSEQ_DATA_WIDTH79 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH79_SHIFT 8 /* WSEQ_DATA_WIDTH79 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH79_WIDTH 3 /* WSEQ_DATA_WIDTH79 - [10:8] */
+#define WM8994_WSEQ_DATA_START79_MASK 0x000F /* WSEQ_DATA_START79 - [3:0] */
+#define WM8994_WSEQ_DATA_START79_SHIFT 0 /* WSEQ_DATA_START79 - [3:0] */
+#define WM8994_WSEQ_DATA_START79_WIDTH 4 /* WSEQ_DATA_START79 - [3:0] */
+
+/*
+ * R12607 (0x313F) - Write Sequencer 319
+ */
+#define WM8994_WSEQ_EOS79 0x0100 /* WSEQ_EOS79 */
+#define WM8994_WSEQ_EOS79_MASK 0x0100 /* WSEQ_EOS79 */
+#define WM8994_WSEQ_EOS79_SHIFT 8 /* WSEQ_EOS79 */
+#define WM8994_WSEQ_EOS79_WIDTH 1 /* WSEQ_EOS79 */
+#define WM8994_WSEQ_DELAY79_MASK 0x000F /* WSEQ_DELAY79 - [3:0] */
+#define WM8994_WSEQ_DELAY79_SHIFT 0 /* WSEQ_DELAY79 - [3:0] */
+#define WM8994_WSEQ_DELAY79_WIDTH 4 /* WSEQ_DELAY79 - [3:0] */
+
+/*
+ * R12608 (0x3140) - Write Sequencer 320
+ */
+#define WM8994_WSEQ_ADDR80_MASK 0x3FFF /* WSEQ_ADDR80 - [13:0] */
+#define WM8994_WSEQ_ADDR80_SHIFT 0 /* WSEQ_ADDR80 - [13:0] */
+#define WM8994_WSEQ_ADDR80_WIDTH 14 /* WSEQ_ADDR80 - [13:0] */
+
+/*
+ * R12609 (0x3141) - Write Sequencer 321
+ */
+#define WM8994_WSEQ_DATA80_MASK 0x00FF /* WSEQ_DATA80 - [7:0] */
+#define WM8994_WSEQ_DATA80_SHIFT 0 /* WSEQ_DATA80 - [7:0] */
+#define WM8994_WSEQ_DATA80_WIDTH 8 /* WSEQ_DATA80 - [7:0] */
+
+/*
+ * R12610 (0x3142) - Write Sequencer 322
+ */
+#define WM8994_WSEQ_DATA_WIDTH80_MASK 0x0700 /* WSEQ_DATA_WIDTH80 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH80_SHIFT 8 /* WSEQ_DATA_WIDTH80 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH80_WIDTH 3 /* WSEQ_DATA_WIDTH80 - [10:8] */
+#define WM8994_WSEQ_DATA_START80_MASK 0x000F /* WSEQ_DATA_START80 - [3:0] */
+#define WM8994_WSEQ_DATA_START80_SHIFT 0 /* WSEQ_DATA_START80 - [3:0] */
+#define WM8994_WSEQ_DATA_START80_WIDTH 4 /* WSEQ_DATA_START80 - [3:0] */
+
+/*
+ * R12611 (0x3143) - Write Sequencer 323
+ */
+#define WM8994_WSEQ_EOS80 0x0100 /* WSEQ_EOS80 */
+#define WM8994_WSEQ_EOS80_MASK 0x0100 /* WSEQ_EOS80 */
+#define WM8994_WSEQ_EOS80_SHIFT 8 /* WSEQ_EOS80 */
+#define WM8994_WSEQ_EOS80_WIDTH 1 /* WSEQ_EOS80 */
+#define WM8994_WSEQ_DELAY80_MASK 0x000F /* WSEQ_DELAY80 - [3:0] */
+#define WM8994_WSEQ_DELAY80_SHIFT 0 /* WSEQ_DELAY80 - [3:0] */
+#define WM8994_WSEQ_DELAY80_WIDTH 4 /* WSEQ_DELAY80 - [3:0] */
+
+/*
+ * R12612 (0x3144) - Write Sequencer 324
+ */
+#define WM8994_WSEQ_ADDR81_MASK 0x3FFF /* WSEQ_ADDR81 - [13:0] */
+#define WM8994_WSEQ_ADDR81_SHIFT 0 /* WSEQ_ADDR81 - [13:0] */
+#define WM8994_WSEQ_ADDR81_WIDTH 14 /* WSEQ_ADDR81 - [13:0] */
+
+/*
+ * R12613 (0x3145) - Write Sequencer 325
+ */
+#define WM8994_WSEQ_DATA81_MASK 0x00FF /* WSEQ_DATA81 - [7:0] */
+#define WM8994_WSEQ_DATA81_SHIFT 0 /* WSEQ_DATA81 - [7:0] */
+#define WM8994_WSEQ_DATA81_WIDTH 8 /* WSEQ_DATA81 - [7:0] */
+
+/*
+ * R12614 (0x3146) - Write Sequencer 326
+ */
+#define WM8994_WSEQ_DATA_WIDTH81_MASK 0x0700 /* WSEQ_DATA_WIDTH81 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH81_SHIFT 8 /* WSEQ_DATA_WIDTH81 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH81_WIDTH 3 /* WSEQ_DATA_WIDTH81 - [10:8] */
+#define WM8994_WSEQ_DATA_START81_MASK 0x000F /* WSEQ_DATA_START81 - [3:0] */
+#define WM8994_WSEQ_DATA_START81_SHIFT 0 /* WSEQ_DATA_START81 - [3:0] */
+#define WM8994_WSEQ_DATA_START81_WIDTH 4 /* WSEQ_DATA_START81 - [3:0] */
+
+/*
+ * R12615 (0x3147) - Write Sequencer 327
+ */
+#define WM8994_WSEQ_EOS81 0x0100 /* WSEQ_EOS81 */
+#define WM8994_WSEQ_EOS81_MASK 0x0100 /* WSEQ_EOS81 */
+#define WM8994_WSEQ_EOS81_SHIFT 8 /* WSEQ_EOS81 */
+#define WM8994_WSEQ_EOS81_WIDTH 1 /* WSEQ_EOS81 */
+#define WM8994_WSEQ_DELAY81_MASK 0x000F /* WSEQ_DELAY81 - [3:0] */
+#define WM8994_WSEQ_DELAY81_SHIFT 0 /* WSEQ_DELAY81 - [3:0] */
+#define WM8994_WSEQ_DELAY81_WIDTH 4 /* WSEQ_DELAY81 - [3:0] */
+
+/*
+ * R12616 (0x3148) - Write Sequencer 328
+ */
+#define WM8994_WSEQ_ADDR82_MASK 0x3FFF /* WSEQ_ADDR82 - [13:0] */
+#define WM8994_WSEQ_ADDR82_SHIFT 0 /* WSEQ_ADDR82 - [13:0] */
+#define WM8994_WSEQ_ADDR82_WIDTH 14 /* WSEQ_ADDR82 - [13:0] */
+
+/*
+ * R12617 (0x3149) - Write Sequencer 329
+ */
+#define WM8994_WSEQ_DATA82_MASK 0x00FF /* WSEQ_DATA82 - [7:0] */
+#define WM8994_WSEQ_DATA82_SHIFT 0 /* WSEQ_DATA82 - [7:0] */
+#define WM8994_WSEQ_DATA82_WIDTH 8 /* WSEQ_DATA82 - [7:0] */
+
+/*
+ * R12618 (0x314A) - Write Sequencer 330
+ */
+#define WM8994_WSEQ_DATA_WIDTH82_MASK 0x0700 /* WSEQ_DATA_WIDTH82 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH82_SHIFT 8 /* WSEQ_DATA_WIDTH82 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH82_WIDTH 3 /* WSEQ_DATA_WIDTH82 - [10:8] */
+#define WM8994_WSEQ_DATA_START82_MASK 0x000F /* WSEQ_DATA_START82 - [3:0] */
+#define WM8994_WSEQ_DATA_START82_SHIFT 0 /* WSEQ_DATA_START82 - [3:0] */
+#define WM8994_WSEQ_DATA_START82_WIDTH 4 /* WSEQ_DATA_START82 - [3:0] */
+
+/*
+ * R12619 (0x314B) - Write Sequencer 331
+ */
+#define WM8994_WSEQ_EOS82 0x0100 /* WSEQ_EOS82 */
+#define WM8994_WSEQ_EOS82_MASK 0x0100 /* WSEQ_EOS82 */
+#define WM8994_WSEQ_EOS82_SHIFT 8 /* WSEQ_EOS82 */
+#define WM8994_WSEQ_EOS82_WIDTH 1 /* WSEQ_EOS82 */
+#define WM8994_WSEQ_DELAY82_MASK 0x000F /* WSEQ_DELAY82 - [3:0] */
+#define WM8994_WSEQ_DELAY82_SHIFT 0 /* WSEQ_DELAY82 - [3:0] */
+#define WM8994_WSEQ_DELAY82_WIDTH 4 /* WSEQ_DELAY82 - [3:0] */
+
+/*
+ * R12620 (0x314C) - Write Sequencer 332
+ */
+#define WM8994_WSEQ_ADDR83_MASK 0x3FFF /* WSEQ_ADDR83 - [13:0] */
+#define WM8994_WSEQ_ADDR83_SHIFT 0 /* WSEQ_ADDR83 - [13:0] */
+#define WM8994_WSEQ_ADDR83_WIDTH 14 /* WSEQ_ADDR83 - [13:0] */
+
+/*
+ * R12621 (0x314D) - Write Sequencer 333
+ */
+#define WM8994_WSEQ_DATA83_MASK 0x00FF /* WSEQ_DATA83 - [7:0] */
+#define WM8994_WSEQ_DATA83_SHIFT 0 /* WSEQ_DATA83 - [7:0] */
+#define WM8994_WSEQ_DATA83_WIDTH 8 /* WSEQ_DATA83 - [7:0] */
+
+/*
+ * R12622 (0x314E) - Write Sequencer 334
+ */
+#define WM8994_WSEQ_DATA_WIDTH83_MASK 0x0700 /* WSEQ_DATA_WIDTH83 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH83_SHIFT 8 /* WSEQ_DATA_WIDTH83 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH83_WIDTH 3 /* WSEQ_DATA_WIDTH83 - [10:8] */
+#define WM8994_WSEQ_DATA_START83_MASK 0x000F /* WSEQ_DATA_START83 - [3:0] */
+#define WM8994_WSEQ_DATA_START83_SHIFT 0 /* WSEQ_DATA_START83 - [3:0] */
+#define WM8994_WSEQ_DATA_START83_WIDTH 4 /* WSEQ_DATA_START83 - [3:0] */
+
+/*
+ * R12623 (0x314F) - Write Sequencer 335
+ */
+#define WM8994_WSEQ_EOS83 0x0100 /* WSEQ_EOS83 */
+#define WM8994_WSEQ_EOS83_MASK 0x0100 /* WSEQ_EOS83 */
+#define WM8994_WSEQ_EOS83_SHIFT 8 /* WSEQ_EOS83 */
+#define WM8994_WSEQ_EOS83_WIDTH 1 /* WSEQ_EOS83 */
+#define WM8994_WSEQ_DELAY83_MASK 0x000F /* WSEQ_DELAY83 - [3:0] */
+#define WM8994_WSEQ_DELAY83_SHIFT 0 /* WSEQ_DELAY83 - [3:0] */
+#define WM8994_WSEQ_DELAY83_WIDTH 4 /* WSEQ_DELAY83 - [3:0] */
+
+/*
+ * R12624 (0x3150) - Write Sequencer 336
+ */
+#define WM8994_WSEQ_ADDR84_MASK 0x3FFF /* WSEQ_ADDR84 - [13:0] */
+#define WM8994_WSEQ_ADDR84_SHIFT 0 /* WSEQ_ADDR84 - [13:0] */
+#define WM8994_WSEQ_ADDR84_WIDTH 14 /* WSEQ_ADDR84 - [13:0] */
+
+/*
+ * R12625 (0x3151) - Write Sequencer 337
+ */
+#define WM8994_WSEQ_DATA84_MASK 0x00FF /* WSEQ_DATA84 - [7:0] */
+#define WM8994_WSEQ_DATA84_SHIFT 0 /* WSEQ_DATA84 - [7:0] */
+#define WM8994_WSEQ_DATA84_WIDTH 8 /* WSEQ_DATA84 - [7:0] */
+
+/*
+ * R12626 (0x3152) - Write Sequencer 338
+ */
+#define WM8994_WSEQ_DATA_WIDTH84_MASK 0x0700 /* WSEQ_DATA_WIDTH84 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH84_SHIFT 8 /* WSEQ_DATA_WIDTH84 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH84_WIDTH 3 /* WSEQ_DATA_WIDTH84 - [10:8] */
+#define WM8994_WSEQ_DATA_START84_MASK 0x000F /* WSEQ_DATA_START84 - [3:0] */
+#define WM8994_WSEQ_DATA_START84_SHIFT 0 /* WSEQ_DATA_START84 - [3:0] */
+#define WM8994_WSEQ_DATA_START84_WIDTH 4 /* WSEQ_DATA_START84 - [3:0] */
+
+/*
+ * R12627 (0x3153) - Write Sequencer 339
+ */
+#define WM8994_WSEQ_EOS84 0x0100 /* WSEQ_EOS84 */
+#define WM8994_WSEQ_EOS84_MASK 0x0100 /* WSEQ_EOS84 */
+#define WM8994_WSEQ_EOS84_SHIFT 8 /* WSEQ_EOS84 */
+#define WM8994_WSEQ_EOS84_WIDTH 1 /* WSEQ_EOS84 */
+#define WM8994_WSEQ_DELAY84_MASK 0x000F /* WSEQ_DELAY84 - [3:0] */
+#define WM8994_WSEQ_DELAY84_SHIFT 0 /* WSEQ_DELAY84 - [3:0] */
+#define WM8994_WSEQ_DELAY84_WIDTH 4 /* WSEQ_DELAY84 - [3:0] */
+
+/*
+ * R12628 (0x3154) - Write Sequencer 340
+ */
+#define WM8994_WSEQ_ADDR85_MASK 0x3FFF /* WSEQ_ADDR85 - [13:0] */
+#define WM8994_WSEQ_ADDR85_SHIFT 0 /* WSEQ_ADDR85 - [13:0] */
+#define WM8994_WSEQ_ADDR85_WIDTH 14 /* WSEQ_ADDR85 - [13:0] */
+
+/*
+ * R12629 (0x3155) - Write Sequencer 341
+ */
+#define WM8994_WSEQ_DATA85_MASK 0x00FF /* WSEQ_DATA85 - [7:0] */
+#define WM8994_WSEQ_DATA85_SHIFT 0 /* WSEQ_DATA85 - [7:0] */
+#define WM8994_WSEQ_DATA85_WIDTH 8 /* WSEQ_DATA85 - [7:0] */
+
+/*
+ * R12630 (0x3156) - Write Sequencer 342
+ */
+#define WM8994_WSEQ_DATA_WIDTH85_MASK 0x0700 /* WSEQ_DATA_WIDTH85 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH85_SHIFT 8 /* WSEQ_DATA_WIDTH85 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH85_WIDTH 3 /* WSEQ_DATA_WIDTH85 - [10:8] */
+#define WM8994_WSEQ_DATA_START85_MASK 0x000F /* WSEQ_DATA_START85 - [3:0] */
+#define WM8994_WSEQ_DATA_START85_SHIFT 0 /* WSEQ_DATA_START85 - [3:0] */
+#define WM8994_WSEQ_DATA_START85_WIDTH 4 /* WSEQ_DATA_START85 - [3:0] */
+
+/*
+ * R12631 (0x3157) - Write Sequencer 343
+ */
+#define WM8994_WSEQ_EOS85 0x0100 /* WSEQ_EOS85 */
+#define WM8994_WSEQ_EOS85_MASK 0x0100 /* WSEQ_EOS85 */
+#define WM8994_WSEQ_EOS85_SHIFT 8 /* WSEQ_EOS85 */
+#define WM8994_WSEQ_EOS85_WIDTH 1 /* WSEQ_EOS85 */
+#define WM8994_WSEQ_DELAY85_MASK 0x000F /* WSEQ_DELAY85 - [3:0] */
+#define WM8994_WSEQ_DELAY85_SHIFT 0 /* WSEQ_DELAY85 - [3:0] */
+#define WM8994_WSEQ_DELAY85_WIDTH 4 /* WSEQ_DELAY85 - [3:0] */
+
+/*
+ * R12632 (0x3158) - Write Sequencer 344
+ */
+#define WM8994_WSEQ_ADDR86_MASK 0x3FFF /* WSEQ_ADDR86 - [13:0] */
+#define WM8994_WSEQ_ADDR86_SHIFT 0 /* WSEQ_ADDR86 - [13:0] */
+#define WM8994_WSEQ_ADDR86_WIDTH 14 /* WSEQ_ADDR86 - [13:0] */
+
+/*
+ * R12633 (0x3159) - Write Sequencer 345
+ */
+#define WM8994_WSEQ_DATA86_MASK 0x00FF /* WSEQ_DATA86 - [7:0] */
+#define WM8994_WSEQ_DATA86_SHIFT 0 /* WSEQ_DATA86 - [7:0] */
+#define WM8994_WSEQ_DATA86_WIDTH 8 /* WSEQ_DATA86 - [7:0] */
+
+/*
+ * R12634 (0x315A) - Write Sequencer 346
+ */
+#define WM8994_WSEQ_DATA_WIDTH86_MASK 0x0700 /* WSEQ_DATA_WIDTH86 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH86_SHIFT 8 /* WSEQ_DATA_WIDTH86 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH86_WIDTH 3 /* WSEQ_DATA_WIDTH86 - [10:8] */
+#define WM8994_WSEQ_DATA_START86_MASK 0x000F /* WSEQ_DATA_START86 - [3:0] */
+#define WM8994_WSEQ_DATA_START86_SHIFT 0 /* WSEQ_DATA_START86 - [3:0] */
+#define WM8994_WSEQ_DATA_START86_WIDTH 4 /* WSEQ_DATA_START86 - [3:0] */
+
+/*
+ * R12635 (0x315B) - Write Sequencer 347
+ */
+#define WM8994_WSEQ_EOS86 0x0100 /* WSEQ_EOS86 */
+#define WM8994_WSEQ_EOS86_MASK 0x0100 /* WSEQ_EOS86 */
+#define WM8994_WSEQ_EOS86_SHIFT 8 /* WSEQ_EOS86 */
+#define WM8994_WSEQ_EOS86_WIDTH 1 /* WSEQ_EOS86 */
+#define WM8994_WSEQ_DELAY86_MASK 0x000F /* WSEQ_DELAY86 - [3:0] */
+#define WM8994_WSEQ_DELAY86_SHIFT 0 /* WSEQ_DELAY86 - [3:0] */
+#define WM8994_WSEQ_DELAY86_WIDTH 4 /* WSEQ_DELAY86 - [3:0] */
+
+/*
+ * R12636 (0x315C) - Write Sequencer 348
+ */
+#define WM8994_WSEQ_ADDR87_MASK 0x3FFF /* WSEQ_ADDR87 - [13:0] */
+#define WM8994_WSEQ_ADDR87_SHIFT 0 /* WSEQ_ADDR87 - [13:0] */
+#define WM8994_WSEQ_ADDR87_WIDTH 14 /* WSEQ_ADDR87 - [13:0] */
+
+/*
+ * R12637 (0x315D) - Write Sequencer 349
+ */
+#define WM8994_WSEQ_DATA87_MASK 0x00FF /* WSEQ_DATA87 - [7:0] */
+#define WM8994_WSEQ_DATA87_SHIFT 0 /* WSEQ_DATA87 - [7:0] */
+#define WM8994_WSEQ_DATA87_WIDTH 8 /* WSEQ_DATA87 - [7:0] */
+
+/*
+ * R12638 (0x315E) - Write Sequencer 350
+ */
+#define WM8994_WSEQ_DATA_WIDTH87_MASK 0x0700 /* WSEQ_DATA_WIDTH87 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH87_SHIFT 8 /* WSEQ_DATA_WIDTH87 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH87_WIDTH 3 /* WSEQ_DATA_WIDTH87 - [10:8] */
+#define WM8994_WSEQ_DATA_START87_MASK 0x000F /* WSEQ_DATA_START87 - [3:0] */
+#define WM8994_WSEQ_DATA_START87_SHIFT 0 /* WSEQ_DATA_START87 - [3:0] */
+#define WM8994_WSEQ_DATA_START87_WIDTH 4 /* WSEQ_DATA_START87 - [3:0] */
+
+/*
+ * R12639 (0x315F) - Write Sequencer 351
+ */
+#define WM8994_WSEQ_EOS87 0x0100 /* WSEQ_EOS87 */
+#define WM8994_WSEQ_EOS87_MASK 0x0100 /* WSEQ_EOS87 */
+#define WM8994_WSEQ_EOS87_SHIFT 8 /* WSEQ_EOS87 */
+#define WM8994_WSEQ_EOS87_WIDTH 1 /* WSEQ_EOS87 */
+#define WM8994_WSEQ_DELAY87_MASK 0x000F /* WSEQ_DELAY87 - [3:0] */
+#define WM8994_WSEQ_DELAY87_SHIFT 0 /* WSEQ_DELAY87 - [3:0] */
+#define WM8994_WSEQ_DELAY87_WIDTH 4 /* WSEQ_DELAY87 - [3:0] */
+
+/*
+ * R12640 (0x3160) - Write Sequencer 352
+ */
+#define WM8994_WSEQ_ADDR88_MASK 0x3FFF /* WSEQ_ADDR88 - [13:0] */
+#define WM8994_WSEQ_ADDR88_SHIFT 0 /* WSEQ_ADDR88 - [13:0] */
+#define WM8994_WSEQ_ADDR88_WIDTH 14 /* WSEQ_ADDR88 - [13:0] */
+
+/*
+ * R12641 (0x3161) - Write Sequencer 353
+ */
+#define WM8994_WSEQ_DATA88_MASK 0x00FF /* WSEQ_DATA88 - [7:0] */
+#define WM8994_WSEQ_DATA88_SHIFT 0 /* WSEQ_DATA88 - [7:0] */
+#define WM8994_WSEQ_DATA88_WIDTH 8 /* WSEQ_DATA88 - [7:0] */
+
+/*
+ * R12642 (0x3162) - Write Sequencer 354
+ */
+#define WM8994_WSEQ_DATA_WIDTH88_MASK 0x0700 /* WSEQ_DATA_WIDTH88 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH88_SHIFT 8 /* WSEQ_DATA_WIDTH88 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH88_WIDTH 3 /* WSEQ_DATA_WIDTH88 - [10:8] */
+#define WM8994_WSEQ_DATA_START88_MASK 0x000F /* WSEQ_DATA_START88 - [3:0] */
+#define WM8994_WSEQ_DATA_START88_SHIFT 0 /* WSEQ_DATA_START88 - [3:0] */
+#define WM8994_WSEQ_DATA_START88_WIDTH 4 /* WSEQ_DATA_START88 - [3:0] */
+
+/*
+ * R12643 (0x3163) - Write Sequencer 355
+ */
+#define WM8994_WSEQ_EOS88 0x0100 /* WSEQ_EOS88 */
+#define WM8994_WSEQ_EOS88_MASK 0x0100 /* WSEQ_EOS88 */
+#define WM8994_WSEQ_EOS88_SHIFT 8 /* WSEQ_EOS88 */
+#define WM8994_WSEQ_EOS88_WIDTH 1 /* WSEQ_EOS88 */
+#define WM8994_WSEQ_DELAY88_MASK 0x000F /* WSEQ_DELAY88 - [3:0] */
+#define WM8994_WSEQ_DELAY88_SHIFT 0 /* WSEQ_DELAY88 - [3:0] */
+#define WM8994_WSEQ_DELAY88_WIDTH 4 /* WSEQ_DELAY88 - [3:0] */
+
+/*
+ * R12644 (0x3164) - Write Sequencer 356
+ */
+#define WM8994_WSEQ_ADDR89_MASK 0x3FFF /* WSEQ_ADDR89 - [13:0] */
+#define WM8994_WSEQ_ADDR89_SHIFT 0 /* WSEQ_ADDR89 - [13:0] */
+#define WM8994_WSEQ_ADDR89_WIDTH 14 /* WSEQ_ADDR89 - [13:0] */
+
+/*
+ * R12645 (0x3165) - Write Sequencer 357
+ */
+#define WM8994_WSEQ_DATA89_MASK 0x00FF /* WSEQ_DATA89 - [7:0] */
+#define WM8994_WSEQ_DATA89_SHIFT 0 /* WSEQ_DATA89 - [7:0] */
+#define WM8994_WSEQ_DATA89_WIDTH 8 /* WSEQ_DATA89 - [7:0] */
+
+/*
+ * R12646 (0x3166) - Write Sequencer 358
+ */
+#define WM8994_WSEQ_DATA_WIDTH89_MASK 0x0700 /* WSEQ_DATA_WIDTH89 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH89_SHIFT 8 /* WSEQ_DATA_WIDTH89 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH89_WIDTH 3 /* WSEQ_DATA_WIDTH89 - [10:8] */
+#define WM8994_WSEQ_DATA_START89_MASK 0x000F /* WSEQ_DATA_START89 - [3:0] */
+#define WM8994_WSEQ_DATA_START89_SHIFT 0 /* WSEQ_DATA_START89 - [3:0] */
+#define WM8994_WSEQ_DATA_START89_WIDTH 4 /* WSEQ_DATA_START89 - [3:0] */
+
+/*
+ * R12647 (0x3167) - Write Sequencer 359
+ */
+#define WM8994_WSEQ_EOS89 0x0100 /* WSEQ_EOS89 */
+#define WM8994_WSEQ_EOS89_MASK 0x0100 /* WSEQ_EOS89 */
+#define WM8994_WSEQ_EOS89_SHIFT 8 /* WSEQ_EOS89 */
+#define WM8994_WSEQ_EOS89_WIDTH 1 /* WSEQ_EOS89 */
+#define WM8994_WSEQ_DELAY89_MASK 0x000F /* WSEQ_DELAY89 - [3:0] */
+#define WM8994_WSEQ_DELAY89_SHIFT 0 /* WSEQ_DELAY89 - [3:0] */
+#define WM8994_WSEQ_DELAY89_WIDTH 4 /* WSEQ_DELAY89 - [3:0] */
+
+/*
+ * R12648 (0x3168) - Write Sequencer 360
+ */
+#define WM8994_WSEQ_ADDR90_MASK 0x3FFF /* WSEQ_ADDR90 - [13:0] */
+#define WM8994_WSEQ_ADDR90_SHIFT 0 /* WSEQ_ADDR90 - [13:0] */
+#define WM8994_WSEQ_ADDR90_WIDTH 14 /* WSEQ_ADDR90 - [13:0] */
+
+/*
+ * R12649 (0x3169) - Write Sequencer 361
+ */
+#define WM8994_WSEQ_DATA90_MASK 0x00FF /* WSEQ_DATA90 - [7:0] */
+#define WM8994_WSEQ_DATA90_SHIFT 0 /* WSEQ_DATA90 - [7:0] */
+#define WM8994_WSEQ_DATA90_WIDTH 8 /* WSEQ_DATA90 - [7:0] */
+
+/*
+ * R12650 (0x316A) - Write Sequencer 362
+ */
+#define WM8994_WSEQ_DATA_WIDTH90_MASK 0x0700 /* WSEQ_DATA_WIDTH90 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH90_SHIFT 8 /* WSEQ_DATA_WIDTH90 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH90_WIDTH 3 /* WSEQ_DATA_WIDTH90 - [10:8] */
+#define WM8994_WSEQ_DATA_START90_MASK 0x000F /* WSEQ_DATA_START90 - [3:0] */
+#define WM8994_WSEQ_DATA_START90_SHIFT 0 /* WSEQ_DATA_START90 - [3:0] */
+#define WM8994_WSEQ_DATA_START90_WIDTH 4 /* WSEQ_DATA_START90 - [3:0] */
+
+/*
+ * R12651 (0x316B) - Write Sequencer 363
+ */
+#define WM8994_WSEQ_EOS90 0x0100 /* WSEQ_EOS90 */
+#define WM8994_WSEQ_EOS90_MASK 0x0100 /* WSEQ_EOS90 */
+#define WM8994_WSEQ_EOS90_SHIFT 8 /* WSEQ_EOS90 */
+#define WM8994_WSEQ_EOS90_WIDTH 1 /* WSEQ_EOS90 */
+#define WM8994_WSEQ_DELAY90_MASK 0x000F /* WSEQ_DELAY90 - [3:0] */
+#define WM8994_WSEQ_DELAY90_SHIFT 0 /* WSEQ_DELAY90 - [3:0] */
+#define WM8994_WSEQ_DELAY90_WIDTH 4 /* WSEQ_DELAY90 - [3:0] */
+
+/*
+ * R12652 (0x316C) - Write Sequencer 364
+ */
+#define WM8994_WSEQ_ADDR91_MASK 0x3FFF /* WSEQ_ADDR91 - [13:0] */
+#define WM8994_WSEQ_ADDR91_SHIFT 0 /* WSEQ_ADDR91 - [13:0] */
+#define WM8994_WSEQ_ADDR91_WIDTH 14 /* WSEQ_ADDR91 - [13:0] */
+
+/*
+ * R12653 (0x316D) - Write Sequencer 365
+ */
+#define WM8994_WSEQ_DATA91_MASK 0x00FF /* WSEQ_DATA91 - [7:0] */
+#define WM8994_WSEQ_DATA91_SHIFT 0 /* WSEQ_DATA91 - [7:0] */
+#define WM8994_WSEQ_DATA91_WIDTH 8 /* WSEQ_DATA91 - [7:0] */
+
+/*
+ * R12654 (0x316E) - Write Sequencer 366
+ */
+#define WM8994_WSEQ_DATA_WIDTH91_MASK 0x0700 /* WSEQ_DATA_WIDTH91 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH91_SHIFT 8 /* WSEQ_DATA_WIDTH91 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH91_WIDTH 3 /* WSEQ_DATA_WIDTH91 - [10:8] */
+#define WM8994_WSEQ_DATA_START91_MASK 0x000F /* WSEQ_DATA_START91 - [3:0] */
+#define WM8994_WSEQ_DATA_START91_SHIFT 0 /* WSEQ_DATA_START91 - [3:0] */
+#define WM8994_WSEQ_DATA_START91_WIDTH 4 /* WSEQ_DATA_START91 - [3:0] */
+
+/*
+ * R12655 (0x316F) - Write Sequencer 367
+ */
+#define WM8994_WSEQ_EOS91 0x0100 /* WSEQ_EOS91 */
+#define WM8994_WSEQ_EOS91_MASK 0x0100 /* WSEQ_EOS91 */
+#define WM8994_WSEQ_EOS91_SHIFT 8 /* WSEQ_EOS91 */
+#define WM8994_WSEQ_EOS91_WIDTH 1 /* WSEQ_EOS91 */
+#define WM8994_WSEQ_DELAY91_MASK 0x000F /* WSEQ_DELAY91 - [3:0] */
+#define WM8994_WSEQ_DELAY91_SHIFT 0 /* WSEQ_DELAY91 - [3:0] */
+#define WM8994_WSEQ_DELAY91_WIDTH 4 /* WSEQ_DELAY91 - [3:0] */
+
+/*
+ * R12656 (0x3170) - Write Sequencer 368
+ */
+#define WM8994_WSEQ_ADDR92_MASK 0x3FFF /* WSEQ_ADDR92 - [13:0] */
+#define WM8994_WSEQ_ADDR92_SHIFT 0 /* WSEQ_ADDR92 - [13:0] */
+#define WM8994_WSEQ_ADDR92_WIDTH 14 /* WSEQ_ADDR92 - [13:0] */
+
+/*
+ * R12657 (0x3171) - Write Sequencer 369
+ */
+#define WM8994_WSEQ_DATA92_MASK 0x00FF /* WSEQ_DATA92 - [7:0] */
+#define WM8994_WSEQ_DATA92_SHIFT 0 /* WSEQ_DATA92 - [7:0] */
+#define WM8994_WSEQ_DATA92_WIDTH 8 /* WSEQ_DATA92 - [7:0] */
+
+/*
+ * R12658 (0x3172) - Write Sequencer 370
+ */
+#define WM8994_WSEQ_DATA_WIDTH92_MASK 0x0700 /* WSEQ_DATA_WIDTH92 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH92_SHIFT 8 /* WSEQ_DATA_WIDTH92 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH92_WIDTH 3 /* WSEQ_DATA_WIDTH92 - [10:8] */
+#define WM8994_WSEQ_DATA_START92_MASK 0x000F /* WSEQ_DATA_START92 - [3:0] */
+#define WM8994_WSEQ_DATA_START92_SHIFT 0 /* WSEQ_DATA_START92 - [3:0] */
+#define WM8994_WSEQ_DATA_START92_WIDTH 4 /* WSEQ_DATA_START92 - [3:0] */
+
+/*
+ * R12659 (0x3173) - Write Sequencer 371
+ */
+#define WM8994_WSEQ_EOS92 0x0100 /* WSEQ_EOS92 */
+#define WM8994_WSEQ_EOS92_MASK 0x0100 /* WSEQ_EOS92 */
+#define WM8994_WSEQ_EOS92_SHIFT 8 /* WSEQ_EOS92 */
+#define WM8994_WSEQ_EOS92_WIDTH 1 /* WSEQ_EOS92 */
+#define WM8994_WSEQ_DELAY92_MASK 0x000F /* WSEQ_DELAY92 - [3:0] */
+#define WM8994_WSEQ_DELAY92_SHIFT 0 /* WSEQ_DELAY92 - [3:0] */
+#define WM8994_WSEQ_DELAY92_WIDTH 4 /* WSEQ_DELAY92 - [3:0] */
+
+/*
+ * R12660 (0x3174) - Write Sequencer 372
+ */
+#define WM8994_WSEQ_ADDR93_MASK 0x3FFF /* WSEQ_ADDR93 - [13:0] */
+#define WM8994_WSEQ_ADDR93_SHIFT 0 /* WSEQ_ADDR93 - [13:0] */
+#define WM8994_WSEQ_ADDR93_WIDTH 14 /* WSEQ_ADDR93 - [13:0] */
+
+/*
+ * R12661 (0x3175) - Write Sequencer 373
+ */
+#define WM8994_WSEQ_DATA93_MASK 0x00FF /* WSEQ_DATA93 - [7:0] */
+#define WM8994_WSEQ_DATA93_SHIFT 0 /* WSEQ_DATA93 - [7:0] */
+#define WM8994_WSEQ_DATA93_WIDTH 8 /* WSEQ_DATA93 - [7:0] */
+
+/*
+ * R12662 (0x3176) - Write Sequencer 374
+ */
+#define WM8994_WSEQ_DATA_WIDTH93_MASK 0x0700 /* WSEQ_DATA_WIDTH93 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH93_SHIFT 8 /* WSEQ_DATA_WIDTH93 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH93_WIDTH 3 /* WSEQ_DATA_WIDTH93 - [10:8] */
+#define WM8994_WSEQ_DATA_START93_MASK 0x000F /* WSEQ_DATA_START93 - [3:0] */
+#define WM8994_WSEQ_DATA_START93_SHIFT 0 /* WSEQ_DATA_START93 - [3:0] */
+#define WM8994_WSEQ_DATA_START93_WIDTH 4 /* WSEQ_DATA_START93 - [3:0] */
+
+/*
+ * R12663 (0x3177) - Write Sequencer 375
+ */
+#define WM8994_WSEQ_EOS93 0x0100 /* WSEQ_EOS93 */
+#define WM8994_WSEQ_EOS93_MASK 0x0100 /* WSEQ_EOS93 */
+#define WM8994_WSEQ_EOS93_SHIFT 8 /* WSEQ_EOS93 */
+#define WM8994_WSEQ_EOS93_WIDTH 1 /* WSEQ_EOS93 */
+#define WM8994_WSEQ_DELAY93_MASK 0x000F /* WSEQ_DELAY93 - [3:0] */
+#define WM8994_WSEQ_DELAY93_SHIFT 0 /* WSEQ_DELAY93 - [3:0] */
+#define WM8994_WSEQ_DELAY93_WIDTH 4 /* WSEQ_DELAY93 - [3:0] */
+
+/*
+ * R12664 (0x3178) - Write Sequencer 376
+ */
+#define WM8994_WSEQ_ADDR94_MASK 0x3FFF /* WSEQ_ADDR94 - [13:0] */
+#define WM8994_WSEQ_ADDR94_SHIFT 0 /* WSEQ_ADDR94 - [13:0] */
+#define WM8994_WSEQ_ADDR94_WIDTH 14 /* WSEQ_ADDR94 - [13:0] */
+
+/*
+ * R12665 (0x3179) - Write Sequencer 377
+ */
+#define WM8994_WSEQ_DATA94_MASK 0x00FF /* WSEQ_DATA94 - [7:0] */
+#define WM8994_WSEQ_DATA94_SHIFT 0 /* WSEQ_DATA94 - [7:0] */
+#define WM8994_WSEQ_DATA94_WIDTH 8 /* WSEQ_DATA94 - [7:0] */
+
+/*
+ * R12666 (0x317A) - Write Sequencer 378
+ */
+#define WM8994_WSEQ_DATA_WIDTH94_MASK 0x0700 /* WSEQ_DATA_WIDTH94 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH94_SHIFT 8 /* WSEQ_DATA_WIDTH94 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH94_WIDTH 3 /* WSEQ_DATA_WIDTH94 - [10:8] */
+#define WM8994_WSEQ_DATA_START94_MASK 0x000F /* WSEQ_DATA_START94 - [3:0] */
+#define WM8994_WSEQ_DATA_START94_SHIFT 0 /* WSEQ_DATA_START94 - [3:0] */
+#define WM8994_WSEQ_DATA_START94_WIDTH 4 /* WSEQ_DATA_START94 - [3:0] */
+
+/*
+ * R12667 (0x317B) - Write Sequencer 379
+ */
+#define WM8994_WSEQ_EOS94 0x0100 /* WSEQ_EOS94 */
+#define WM8994_WSEQ_EOS94_MASK 0x0100 /* WSEQ_EOS94 */
+#define WM8994_WSEQ_EOS94_SHIFT 8 /* WSEQ_EOS94 */
+#define WM8994_WSEQ_EOS94_WIDTH 1 /* WSEQ_EOS94 */
+#define WM8994_WSEQ_DELAY94_MASK 0x000F /* WSEQ_DELAY94 - [3:0] */
+#define WM8994_WSEQ_DELAY94_SHIFT 0 /* WSEQ_DELAY94 - [3:0] */
+#define WM8994_WSEQ_DELAY94_WIDTH 4 /* WSEQ_DELAY94 - [3:0] */
+
+/*
+ * R12668 (0x317C) - Write Sequencer 380
+ */
+#define WM8994_WSEQ_ADDR95_MASK 0x3FFF /* WSEQ_ADDR95 - [13:0] */
+#define WM8994_WSEQ_ADDR95_SHIFT 0 /* WSEQ_ADDR95 - [13:0] */
+#define WM8994_WSEQ_ADDR95_WIDTH 14 /* WSEQ_ADDR95 - [13:0] */
+
+/*
+ * R12669 (0x317D) - Write Sequencer 381
+ */
+#define WM8994_WSEQ_DATA95_MASK 0x00FF /* WSEQ_DATA95 - [7:0] */
+#define WM8994_WSEQ_DATA95_SHIFT 0 /* WSEQ_DATA95 - [7:0] */
+#define WM8994_WSEQ_DATA95_WIDTH 8 /* WSEQ_DATA95 - [7:0] */
+
+/*
+ * R12670 (0x317E) - Write Sequencer 382
+ */
+#define WM8994_WSEQ_DATA_WIDTH95_MASK 0x0700 /* WSEQ_DATA_WIDTH95 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH95_SHIFT 8 /* WSEQ_DATA_WIDTH95 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH95_WIDTH 3 /* WSEQ_DATA_WIDTH95 - [10:8] */
+#define WM8994_WSEQ_DATA_START95_MASK 0x000F /* WSEQ_DATA_START95 - [3:0] */
+#define WM8994_WSEQ_DATA_START95_SHIFT 0 /* WSEQ_DATA_START95 - [3:0] */
+#define WM8994_WSEQ_DATA_START95_WIDTH 4 /* WSEQ_DATA_START95 - [3:0] */
+
+/*
+ * R12671 (0x317F) - Write Sequencer 383
+ */
+#define WM8994_WSEQ_EOS95 0x0100 /* WSEQ_EOS95 */
+#define WM8994_WSEQ_EOS95_MASK 0x0100 /* WSEQ_EOS95 */
+#define WM8994_WSEQ_EOS95_SHIFT 8 /* WSEQ_EOS95 */
+#define WM8994_WSEQ_EOS95_WIDTH 1 /* WSEQ_EOS95 */
+#define WM8994_WSEQ_DELAY95_MASK 0x000F /* WSEQ_DELAY95 - [3:0] */
+#define WM8994_WSEQ_DELAY95_SHIFT 0 /* WSEQ_DELAY95 - [3:0] */
+#define WM8994_WSEQ_DELAY95_WIDTH 4 /* WSEQ_DELAY95 - [3:0] */
+
+/*
+ * R12672 (0x3180) - Write Sequencer 384
+ */
+#define WM8994_WSEQ_ADDR96_MASK 0x3FFF /* WSEQ_ADDR96 - [13:0] */
+#define WM8994_WSEQ_ADDR96_SHIFT 0 /* WSEQ_ADDR96 - [13:0] */
+#define WM8994_WSEQ_ADDR96_WIDTH 14 /* WSEQ_ADDR96 - [13:0] */
+
+/*
+ * R12673 (0x3181) - Write Sequencer 385
+ */
+#define WM8994_WSEQ_DATA96_MASK 0x00FF /* WSEQ_DATA96 - [7:0] */
+#define WM8994_WSEQ_DATA96_SHIFT 0 /* WSEQ_DATA96 - [7:0] */
+#define WM8994_WSEQ_DATA96_WIDTH 8 /* WSEQ_DATA96 - [7:0] */
+
+/*
+ * R12674 (0x3182) - Write Sequencer 386
+ */
+#define WM8994_WSEQ_DATA_WIDTH96_MASK 0x0700 /* WSEQ_DATA_WIDTH96 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH96_SHIFT 8 /* WSEQ_DATA_WIDTH96 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH96_WIDTH 3 /* WSEQ_DATA_WIDTH96 - [10:8] */
+#define WM8994_WSEQ_DATA_START96_MASK 0x000F /* WSEQ_DATA_START96 - [3:0] */
+#define WM8994_WSEQ_DATA_START96_SHIFT 0 /* WSEQ_DATA_START96 - [3:0] */
+#define WM8994_WSEQ_DATA_START96_WIDTH 4 /* WSEQ_DATA_START96 - [3:0] */
+
+/*
+ * R12675 (0x3183) - Write Sequencer 387
+ */
+#define WM8994_WSEQ_EOS96 0x0100 /* WSEQ_EOS96 */
+#define WM8994_WSEQ_EOS96_MASK 0x0100 /* WSEQ_EOS96 */
+#define WM8994_WSEQ_EOS96_SHIFT 8 /* WSEQ_EOS96 */
+#define WM8994_WSEQ_EOS96_WIDTH 1 /* WSEQ_EOS96 */
+#define WM8994_WSEQ_DELAY96_MASK 0x000F /* WSEQ_DELAY96 - [3:0] */
+#define WM8994_WSEQ_DELAY96_SHIFT 0 /* WSEQ_DELAY96 - [3:0] */
+#define WM8994_WSEQ_DELAY96_WIDTH 4 /* WSEQ_DELAY96 - [3:0] */
+
+/*
+ * R12676 (0x3184) - Write Sequencer 388
+ */
+#define WM8994_WSEQ_ADDR97_MASK 0x3FFF /* WSEQ_ADDR97 - [13:0] */
+#define WM8994_WSEQ_ADDR97_SHIFT 0 /* WSEQ_ADDR97 - [13:0] */
+#define WM8994_WSEQ_ADDR97_WIDTH 14 /* WSEQ_ADDR97 - [13:0] */
+
+/*
+ * R12677 (0x3185) - Write Sequencer 389
+ */
+#define WM8994_WSEQ_DATA97_MASK 0x00FF /* WSEQ_DATA97 - [7:0] */
+#define WM8994_WSEQ_DATA97_SHIFT 0 /* WSEQ_DATA97 - [7:0] */
+#define WM8994_WSEQ_DATA97_WIDTH 8 /* WSEQ_DATA97 - [7:0] */
+
+/*
+ * R12678 (0x3186) - Write Sequencer 390
+ */
+#define WM8994_WSEQ_DATA_WIDTH97_MASK 0x0700 /* WSEQ_DATA_WIDTH97 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH97_SHIFT 8 /* WSEQ_DATA_WIDTH97 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH97_WIDTH 3 /* WSEQ_DATA_WIDTH97 - [10:8] */
+#define WM8994_WSEQ_DATA_START97_MASK 0x000F /* WSEQ_DATA_START97 - [3:0] */
+#define WM8994_WSEQ_DATA_START97_SHIFT 0 /* WSEQ_DATA_START97 - [3:0] */
+#define WM8994_WSEQ_DATA_START97_WIDTH 4 /* WSEQ_DATA_START97 - [3:0] */
+
+/*
+ * R12679 (0x3187) - Write Sequencer 391
+ */
+#define WM8994_WSEQ_EOS97 0x0100 /* WSEQ_EOS97 */
+#define WM8994_WSEQ_EOS97_MASK 0x0100 /* WSEQ_EOS97 */
+#define WM8994_WSEQ_EOS97_SHIFT 8 /* WSEQ_EOS97 */
+#define WM8994_WSEQ_EOS97_WIDTH 1 /* WSEQ_EOS97 */
+#define WM8994_WSEQ_DELAY97_MASK 0x000F /* WSEQ_DELAY97 - [3:0] */
+#define WM8994_WSEQ_DELAY97_SHIFT 0 /* WSEQ_DELAY97 - [3:0] */
+#define WM8994_WSEQ_DELAY97_WIDTH 4 /* WSEQ_DELAY97 - [3:0] */
+
+/*
+ * R12680 (0x3188) - Write Sequencer 392
+ */
+#define WM8994_WSEQ_ADDR98_MASK 0x3FFF /* WSEQ_ADDR98 - [13:0] */
+#define WM8994_WSEQ_ADDR98_SHIFT 0 /* WSEQ_ADDR98 - [13:0] */
+#define WM8994_WSEQ_ADDR98_WIDTH 14 /* WSEQ_ADDR98 - [13:0] */
+
+/*
+ * R12681 (0x3189) - Write Sequencer 393
+ */
+#define WM8994_WSEQ_DATA98_MASK 0x00FF /* WSEQ_DATA98 - [7:0] */
+#define WM8994_WSEQ_DATA98_SHIFT 0 /* WSEQ_DATA98 - [7:0] */
+#define WM8994_WSEQ_DATA98_WIDTH 8 /* WSEQ_DATA98 - [7:0] */
+
+/*
+ * R12682 (0x318A) - Write Sequencer 394
+ */
+#define WM8994_WSEQ_DATA_WIDTH98_MASK 0x0700 /* WSEQ_DATA_WIDTH98 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH98_SHIFT 8 /* WSEQ_DATA_WIDTH98 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH98_WIDTH 3 /* WSEQ_DATA_WIDTH98 - [10:8] */
+#define WM8994_WSEQ_DATA_START98_MASK 0x000F /* WSEQ_DATA_START98 - [3:0] */
+#define WM8994_WSEQ_DATA_START98_SHIFT 0 /* WSEQ_DATA_START98 - [3:0] */
+#define WM8994_WSEQ_DATA_START98_WIDTH 4 /* WSEQ_DATA_START98 - [3:0] */
+
+/*
+ * R12683 (0x318B) - Write Sequencer 395
+ */
+#define WM8994_WSEQ_EOS98 0x0100 /* WSEQ_EOS98 */
+#define WM8994_WSEQ_EOS98_MASK 0x0100 /* WSEQ_EOS98 */
+#define WM8994_WSEQ_EOS98_SHIFT 8 /* WSEQ_EOS98 */
+#define WM8994_WSEQ_EOS98_WIDTH 1 /* WSEQ_EOS98 */
+#define WM8994_WSEQ_DELAY98_MASK 0x000F /* WSEQ_DELAY98 - [3:0] */
+#define WM8994_WSEQ_DELAY98_SHIFT 0 /* WSEQ_DELAY98 - [3:0] */
+#define WM8994_WSEQ_DELAY98_WIDTH 4 /* WSEQ_DELAY98 - [3:0] */
+
+/*
+ * R12684 (0x318C) - Write Sequencer 396
+ */
+#define WM8994_WSEQ_ADDR99_MASK 0x3FFF /* WSEQ_ADDR99 - [13:0] */
+#define WM8994_WSEQ_ADDR99_SHIFT 0 /* WSEQ_ADDR99 - [13:0] */
+#define WM8994_WSEQ_ADDR99_WIDTH 14 /* WSEQ_ADDR99 - [13:0] */
+
+/*
+ * R12685 (0x318D) - Write Sequencer 397
+ */
+#define WM8994_WSEQ_DATA99_MASK 0x00FF /* WSEQ_DATA99 - [7:0] */
+#define WM8994_WSEQ_DATA99_SHIFT 0 /* WSEQ_DATA99 - [7:0] */
+#define WM8994_WSEQ_DATA99_WIDTH 8 /* WSEQ_DATA99 - [7:0] */
+
+/*
+ * R12686 (0x318E) - Write Sequencer 398
+ */
+#define WM8994_WSEQ_DATA_WIDTH99_MASK 0x0700 /* WSEQ_DATA_WIDTH99 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH99_SHIFT 8 /* WSEQ_DATA_WIDTH99 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH99_WIDTH 3 /* WSEQ_DATA_WIDTH99 - [10:8] */
+#define WM8994_WSEQ_DATA_START99_MASK 0x000F /* WSEQ_DATA_START99 - [3:0] */
+#define WM8994_WSEQ_DATA_START99_SHIFT 0 /* WSEQ_DATA_START99 - [3:0] */
+#define WM8994_WSEQ_DATA_START99_WIDTH 4 /* WSEQ_DATA_START99 - [3:0] */
+
+/*
+ * R12687 (0x318F) - Write Sequencer 399
+ */
+#define WM8994_WSEQ_EOS99 0x0100 /* WSEQ_EOS99 */
+#define WM8994_WSEQ_EOS99_MASK 0x0100 /* WSEQ_EOS99 */
+#define WM8994_WSEQ_EOS99_SHIFT 8 /* WSEQ_EOS99 */
+#define WM8994_WSEQ_EOS99_WIDTH 1 /* WSEQ_EOS99 */
+#define WM8994_WSEQ_DELAY99_MASK 0x000F /* WSEQ_DELAY99 - [3:0] */
+#define WM8994_WSEQ_DELAY99_SHIFT 0 /* WSEQ_DELAY99 - [3:0] */
+#define WM8994_WSEQ_DELAY99_WIDTH 4 /* WSEQ_DELAY99 - [3:0] */
+
+/*
+ * R12688 (0x3190) - Write Sequencer 400
+ */
+#define WM8994_WSEQ_ADDR100_MASK 0x3FFF /* WSEQ_ADDR100 - [13:0] */
+#define WM8994_WSEQ_ADDR100_SHIFT 0 /* WSEQ_ADDR100 - [13:0] */
+#define WM8994_WSEQ_ADDR100_WIDTH 14 /* WSEQ_ADDR100 - [13:0] */
+
+/*
+ * R12689 (0x3191) - Write Sequencer 401
+ */
+#define WM8994_WSEQ_DATA100_MASK 0x00FF /* WSEQ_DATA100 - [7:0] */
+#define WM8994_WSEQ_DATA100_SHIFT 0 /* WSEQ_DATA100 - [7:0] */
+#define WM8994_WSEQ_DATA100_WIDTH 8 /* WSEQ_DATA100 - [7:0] */
+
+/*
+ * R12690 (0x3192) - Write Sequencer 402
+ */
+#define WM8994_WSEQ_DATA_WIDTH100_MASK 0x0700 /* WSEQ_DATA_WIDTH100 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH100_SHIFT 8 /* WSEQ_DATA_WIDTH100 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH100_WIDTH 3 /* WSEQ_DATA_WIDTH100 - [10:8] */
+#define WM8994_WSEQ_DATA_START100_MASK 0x000F /* WSEQ_DATA_START100 - [3:0] */
+#define WM8994_WSEQ_DATA_START100_SHIFT 0 /* WSEQ_DATA_START100 - [3:0] */
+#define WM8994_WSEQ_DATA_START100_WIDTH 4 /* WSEQ_DATA_START100 - [3:0] */
+
+/*
+ * R12691 (0x3193) - Write Sequencer 403
+ */
+#define WM8994_WSEQ_EOS100 0x0100 /* WSEQ_EOS100 */
+#define WM8994_WSEQ_EOS100_MASK 0x0100 /* WSEQ_EOS100 */
+#define WM8994_WSEQ_EOS100_SHIFT 8 /* WSEQ_EOS100 */
+#define WM8994_WSEQ_EOS100_WIDTH 1 /* WSEQ_EOS100 */
+#define WM8994_WSEQ_DELAY100_MASK 0x000F /* WSEQ_DELAY100 - [3:0] */
+#define WM8994_WSEQ_DELAY100_SHIFT 0 /* WSEQ_DELAY100 - [3:0] */
+#define WM8994_WSEQ_DELAY100_WIDTH 4 /* WSEQ_DELAY100 - [3:0] */
+
+/*
+ * R12692 (0x3194) - Write Sequencer 404
+ */
+#define WM8994_WSEQ_ADDR101_MASK 0x3FFF /* WSEQ_ADDR101 - [13:0] */
+#define WM8994_WSEQ_ADDR101_SHIFT 0 /* WSEQ_ADDR101 - [13:0] */
+#define WM8994_WSEQ_ADDR101_WIDTH 14 /* WSEQ_ADDR101 - [13:0] */
+
+/*
+ * R12693 (0x3195) - Write Sequencer 405
+ */
+#define WM8994_WSEQ_DATA101_MASK 0x00FF /* WSEQ_DATA101 - [7:0] */
+#define WM8994_WSEQ_DATA101_SHIFT 0 /* WSEQ_DATA101 - [7:0] */
+#define WM8994_WSEQ_DATA101_WIDTH 8 /* WSEQ_DATA101 - [7:0] */
+
+/*
+ * R12694 (0x3196) - Write Sequencer 406
+ */
+#define WM8994_WSEQ_DATA_WIDTH101_MASK 0x0700 /* WSEQ_DATA_WIDTH101 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH101_SHIFT 8 /* WSEQ_DATA_WIDTH101 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH101_WIDTH 3 /* WSEQ_DATA_WIDTH101 - [10:8] */
+#define WM8994_WSEQ_DATA_START101_MASK 0x000F /* WSEQ_DATA_START101 - [3:0] */
+#define WM8994_WSEQ_DATA_START101_SHIFT 0 /* WSEQ_DATA_START101 - [3:0] */
+#define WM8994_WSEQ_DATA_START101_WIDTH 4 /* WSEQ_DATA_START101 - [3:0] */
+
+/*
+ * R12695 (0x3197) - Write Sequencer 407
+ */
+#define WM8994_WSEQ_EOS101 0x0100 /* WSEQ_EOS101 */
+#define WM8994_WSEQ_EOS101_MASK 0x0100 /* WSEQ_EOS101 */
+#define WM8994_WSEQ_EOS101_SHIFT 8 /* WSEQ_EOS101 */
+#define WM8994_WSEQ_EOS101_WIDTH 1 /* WSEQ_EOS101 */
+#define WM8994_WSEQ_DELAY101_MASK 0x000F /* WSEQ_DELAY101 - [3:0] */
+#define WM8994_WSEQ_DELAY101_SHIFT 0 /* WSEQ_DELAY101 - [3:0] */
+#define WM8994_WSEQ_DELAY101_WIDTH 4 /* WSEQ_DELAY101 - [3:0] */
+
+/*
+ * R12696 (0x3198) - Write Sequencer 408
+ */
+#define WM8994_WSEQ_ADDR102_MASK 0x3FFF /* WSEQ_ADDR102 - [13:0] */
+#define WM8994_WSEQ_ADDR102_SHIFT 0 /* WSEQ_ADDR102 - [13:0] */
+#define WM8994_WSEQ_ADDR102_WIDTH 14 /* WSEQ_ADDR102 - [13:0] */
+
+/*
+ * R12697 (0x3199) - Write Sequencer 409
+ */
+#define WM8994_WSEQ_DATA102_MASK 0x00FF /* WSEQ_DATA102 - [7:0] */
+#define WM8994_WSEQ_DATA102_SHIFT 0 /* WSEQ_DATA102 - [7:0] */
+#define WM8994_WSEQ_DATA102_WIDTH 8 /* WSEQ_DATA102 - [7:0] */
+
+/*
+ * R12698 (0x319A) - Write Sequencer 410
+ */
+#define WM8994_WSEQ_DATA_WIDTH102_MASK 0x0700 /* WSEQ_DATA_WIDTH102 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH102_SHIFT 8 /* WSEQ_DATA_WIDTH102 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH102_WIDTH 3 /* WSEQ_DATA_WIDTH102 - [10:8] */
+#define WM8994_WSEQ_DATA_START102_MASK 0x000F /* WSEQ_DATA_START102 - [3:0] */
+#define WM8994_WSEQ_DATA_START102_SHIFT 0 /* WSEQ_DATA_START102 - [3:0] */
+#define WM8994_WSEQ_DATA_START102_WIDTH 4 /* WSEQ_DATA_START102 - [3:0] */
+
+/*
+ * R12699 (0x319B) - Write Sequencer 411
+ */
+#define WM8994_WSEQ_EOS102 0x0100 /* WSEQ_EOS102 */
+#define WM8994_WSEQ_EOS102_MASK 0x0100 /* WSEQ_EOS102 */
+#define WM8994_WSEQ_EOS102_SHIFT 8 /* WSEQ_EOS102 */
+#define WM8994_WSEQ_EOS102_WIDTH 1 /* WSEQ_EOS102 */
+#define WM8994_WSEQ_DELAY102_MASK 0x000F /* WSEQ_DELAY102 - [3:0] */
+#define WM8994_WSEQ_DELAY102_SHIFT 0 /* WSEQ_DELAY102 - [3:0] */
+#define WM8994_WSEQ_DELAY102_WIDTH 4 /* WSEQ_DELAY102 - [3:0] */
+
+/*
+ * R12700 (0x319C) - Write Sequencer 412
+ */
+#define WM8994_WSEQ_ADDR103_MASK 0x3FFF /* WSEQ_ADDR103 - [13:0] */
+#define WM8994_WSEQ_ADDR103_SHIFT 0 /* WSEQ_ADDR103 - [13:0] */
+#define WM8994_WSEQ_ADDR103_WIDTH 14 /* WSEQ_ADDR103 - [13:0] */
+
+/*
+ * R12701 (0x319D) - Write Sequencer 413
+ */
+#define WM8994_WSEQ_DATA103_MASK 0x00FF /* WSEQ_DATA103 - [7:0] */
+#define WM8994_WSEQ_DATA103_SHIFT 0 /* WSEQ_DATA103 - [7:0] */
+#define WM8994_WSEQ_DATA103_WIDTH 8 /* WSEQ_DATA103 - [7:0] */
+
+/*
+ * R12702 (0x319E) - Write Sequencer 414
+ */
+#define WM8994_WSEQ_DATA_WIDTH103_MASK 0x0700 /* WSEQ_DATA_WIDTH103 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH103_SHIFT 8 /* WSEQ_DATA_WIDTH103 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH103_WIDTH 3 /* WSEQ_DATA_WIDTH103 - [10:8] */
+#define WM8994_WSEQ_DATA_START103_MASK 0x000F /* WSEQ_DATA_START103 - [3:0] */
+#define WM8994_WSEQ_DATA_START103_SHIFT 0 /* WSEQ_DATA_START103 - [3:0] */
+#define WM8994_WSEQ_DATA_START103_WIDTH 4 /* WSEQ_DATA_START103 - [3:0] */
+
+/*
+ * R12703 (0x319F) - Write Sequencer 415
+ */
+#define WM8994_WSEQ_EOS103 0x0100 /* WSEQ_EOS103 */
+#define WM8994_WSEQ_EOS103_MASK 0x0100 /* WSEQ_EOS103 */
+#define WM8994_WSEQ_EOS103_SHIFT 8 /* WSEQ_EOS103 */
+#define WM8994_WSEQ_EOS103_WIDTH 1 /* WSEQ_EOS103 */
+#define WM8994_WSEQ_DELAY103_MASK 0x000F /* WSEQ_DELAY103 - [3:0] */
+#define WM8994_WSEQ_DELAY103_SHIFT 0 /* WSEQ_DELAY103 - [3:0] */
+#define WM8994_WSEQ_DELAY103_WIDTH 4 /* WSEQ_DELAY103 - [3:0] */
+
+/*
+ * R12704 (0x31A0) - Write Sequencer 416
+ */
+#define WM8994_WSEQ_ADDR104_MASK 0x3FFF /* WSEQ_ADDR104 - [13:0] */
+#define WM8994_WSEQ_ADDR104_SHIFT 0 /* WSEQ_ADDR104 - [13:0] */
+#define WM8994_WSEQ_ADDR104_WIDTH 14 /* WSEQ_ADDR104 - [13:0] */
+
+/*
+ * R12705 (0x31A1) - Write Sequencer 417
+ */
+#define WM8994_WSEQ_DATA104_MASK 0x00FF /* WSEQ_DATA104 - [7:0] */
+#define WM8994_WSEQ_DATA104_SHIFT 0 /* WSEQ_DATA104 - [7:0] */
+#define WM8994_WSEQ_DATA104_WIDTH 8 /* WSEQ_DATA104 - [7:0] */
+
+/*
+ * R12706 (0x31A2) - Write Sequencer 418
+ */
+#define WM8994_WSEQ_DATA_WIDTH104_MASK 0x0700 /* WSEQ_DATA_WIDTH104 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH104_SHIFT 8 /* WSEQ_DATA_WIDTH104 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH104_WIDTH 3 /* WSEQ_DATA_WIDTH104 - [10:8] */
+#define WM8994_WSEQ_DATA_START104_MASK 0x000F /* WSEQ_DATA_START104 - [3:0] */
+#define WM8994_WSEQ_DATA_START104_SHIFT 0 /* WSEQ_DATA_START104 - [3:0] */
+#define WM8994_WSEQ_DATA_START104_WIDTH 4 /* WSEQ_DATA_START104 - [3:0] */
+
+/*
+ * R12707 (0x31A3) - Write Sequencer 419
+ */
+#define WM8994_WSEQ_EOS104 0x0100 /* WSEQ_EOS104 */
+#define WM8994_WSEQ_EOS104_MASK 0x0100 /* WSEQ_EOS104 */
+#define WM8994_WSEQ_EOS104_SHIFT 8 /* WSEQ_EOS104 */
+#define WM8994_WSEQ_EOS104_WIDTH 1 /* WSEQ_EOS104 */
+#define WM8994_WSEQ_DELAY104_MASK 0x000F /* WSEQ_DELAY104 - [3:0] */
+#define WM8994_WSEQ_DELAY104_SHIFT 0 /* WSEQ_DELAY104 - [3:0] */
+#define WM8994_WSEQ_DELAY104_WIDTH 4 /* WSEQ_DELAY104 - [3:0] */
+
+/*
+ * R12708 (0x31A4) - Write Sequencer 420
+ */
+#define WM8994_WSEQ_ADDR105_MASK 0x3FFF /* WSEQ_ADDR105 - [13:0] */
+#define WM8994_WSEQ_ADDR105_SHIFT 0 /* WSEQ_ADDR105 - [13:0] */
+#define WM8994_WSEQ_ADDR105_WIDTH 14 /* WSEQ_ADDR105 - [13:0] */
+
+/*
+ * R12709 (0x31A5) - Write Sequencer 421
+ */
+#define WM8994_WSEQ_DATA105_MASK 0x00FF /* WSEQ_DATA105 - [7:0] */
+#define WM8994_WSEQ_DATA105_SHIFT 0 /* WSEQ_DATA105 - [7:0] */
+#define WM8994_WSEQ_DATA105_WIDTH 8 /* WSEQ_DATA105 - [7:0] */
+
+/*
+ * R12710 (0x31A6) - Write Sequencer 422
+ */
+#define WM8994_WSEQ_DATA_WIDTH105_MASK 0x0700 /* WSEQ_DATA_WIDTH105 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH105_SHIFT 8 /* WSEQ_DATA_WIDTH105 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH105_WIDTH 3 /* WSEQ_DATA_WIDTH105 - [10:8] */
+#define WM8994_WSEQ_DATA_START105_MASK 0x000F /* WSEQ_DATA_START105 - [3:0] */
+#define WM8994_WSEQ_DATA_START105_SHIFT 0 /* WSEQ_DATA_START105 - [3:0] */
+#define WM8994_WSEQ_DATA_START105_WIDTH 4 /* WSEQ_DATA_START105 - [3:0] */
+
+/*
+ * R12711 (0x31A7) - Write Sequencer 423
+ */
+#define WM8994_WSEQ_EOS105 0x0100 /* WSEQ_EOS105 */
+#define WM8994_WSEQ_EOS105_MASK 0x0100 /* WSEQ_EOS105 */
+#define WM8994_WSEQ_EOS105_SHIFT 8 /* WSEQ_EOS105 */
+#define WM8994_WSEQ_EOS105_WIDTH 1 /* WSEQ_EOS105 */
+#define WM8994_WSEQ_DELAY105_MASK 0x000F /* WSEQ_DELAY105 - [3:0] */
+#define WM8994_WSEQ_DELAY105_SHIFT 0 /* WSEQ_DELAY105 - [3:0] */
+#define WM8994_WSEQ_DELAY105_WIDTH 4 /* WSEQ_DELAY105 - [3:0] */
+
+/*
+ * R12712 (0x31A8) - Write Sequencer 424
+ */
+#define WM8994_WSEQ_ADDR106_MASK 0x3FFF /* WSEQ_ADDR106 - [13:0] */
+#define WM8994_WSEQ_ADDR106_SHIFT 0 /* WSEQ_ADDR106 - [13:0] */
+#define WM8994_WSEQ_ADDR106_WIDTH 14 /* WSEQ_ADDR106 - [13:0] */
+
+/*
+ * R12713 (0x31A9) - Write Sequencer 425
+ */
+#define WM8994_WSEQ_DATA106_MASK 0x00FF /* WSEQ_DATA106 - [7:0] */
+#define WM8994_WSEQ_DATA106_SHIFT 0 /* WSEQ_DATA106 - [7:0] */
+#define WM8994_WSEQ_DATA106_WIDTH 8 /* WSEQ_DATA106 - [7:0] */
+
+/*
+ * R12714 (0x31AA) - Write Sequencer 426
+ */
+#define WM8994_WSEQ_DATA_WIDTH106_MASK 0x0700 /* WSEQ_DATA_WIDTH106 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH106_SHIFT 8 /* WSEQ_DATA_WIDTH106 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH106_WIDTH 3 /* WSEQ_DATA_WIDTH106 - [10:8] */
+#define WM8994_WSEQ_DATA_START106_MASK 0x000F /* WSEQ_DATA_START106 - [3:0] */
+#define WM8994_WSEQ_DATA_START106_SHIFT 0 /* WSEQ_DATA_START106 - [3:0] */
+#define WM8994_WSEQ_DATA_START106_WIDTH 4 /* WSEQ_DATA_START106 - [3:0] */
+
+/*
+ * R12715 (0x31AB) - Write Sequencer 427
+ */
+#define WM8994_WSEQ_EOS106 0x0100 /* WSEQ_EOS106 */
+#define WM8994_WSEQ_EOS106_MASK 0x0100 /* WSEQ_EOS106 */
+#define WM8994_WSEQ_EOS106_SHIFT 8 /* WSEQ_EOS106 */
+#define WM8994_WSEQ_EOS106_WIDTH 1 /* WSEQ_EOS106 */
+#define WM8994_WSEQ_DELAY106_MASK 0x000F /* WSEQ_DELAY106 - [3:0] */
+#define WM8994_WSEQ_DELAY106_SHIFT 0 /* WSEQ_DELAY106 - [3:0] */
+#define WM8994_WSEQ_DELAY106_WIDTH 4 /* WSEQ_DELAY106 - [3:0] */
+
+/*
+ * R12716 (0x31AC) - Write Sequencer 428
+ */
+#define WM8994_WSEQ_ADDR107_MASK 0x3FFF /* WSEQ_ADDR107 - [13:0] */
+#define WM8994_WSEQ_ADDR107_SHIFT 0 /* WSEQ_ADDR107 - [13:0] */
+#define WM8994_WSEQ_ADDR107_WIDTH 14 /* WSEQ_ADDR107 - [13:0] */
+
+/*
+ * R12717 (0x31AD) - Write Sequencer 429
+ */
+#define WM8994_WSEQ_DATA107_MASK 0x00FF /* WSEQ_DATA107 - [7:0] */
+#define WM8994_WSEQ_DATA107_SHIFT 0 /* WSEQ_DATA107 - [7:0] */
+#define WM8994_WSEQ_DATA107_WIDTH 8 /* WSEQ_DATA107 - [7:0] */
+
+/*
+ * R12718 (0x31AE) - Write Sequencer 430
+ */
+#define WM8994_WSEQ_DATA_WIDTH107_MASK 0x0700 /* WSEQ_DATA_WIDTH107 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH107_SHIFT 8 /* WSEQ_DATA_WIDTH107 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH107_WIDTH 3 /* WSEQ_DATA_WIDTH107 - [10:8] */
+#define WM8994_WSEQ_DATA_START107_MASK 0x000F /* WSEQ_DATA_START107 - [3:0] */
+#define WM8994_WSEQ_DATA_START107_SHIFT 0 /* WSEQ_DATA_START107 - [3:0] */
+#define WM8994_WSEQ_DATA_START107_WIDTH 4 /* WSEQ_DATA_START107 - [3:0] */
+
+/*
+ * R12719 (0x31AF) - Write Sequencer 431
+ */
+#define WM8994_WSEQ_EOS107 0x0100 /* WSEQ_EOS107 */
+#define WM8994_WSEQ_EOS107_MASK 0x0100 /* WSEQ_EOS107 */
+#define WM8994_WSEQ_EOS107_SHIFT 8 /* WSEQ_EOS107 */
+#define WM8994_WSEQ_EOS107_WIDTH 1 /* WSEQ_EOS107 */
+#define WM8994_WSEQ_DELAY107_MASK 0x000F /* WSEQ_DELAY107 - [3:0] */
+#define WM8994_WSEQ_DELAY107_SHIFT 0 /* WSEQ_DELAY107 - [3:0] */
+#define WM8994_WSEQ_DELAY107_WIDTH 4 /* WSEQ_DELAY107 - [3:0] */
+
+/*
+ * R12720 (0x31B0) - Write Sequencer 432
+ */
+#define WM8994_WSEQ_ADDR108_MASK 0x3FFF /* WSEQ_ADDR108 - [13:0] */
+#define WM8994_WSEQ_ADDR108_SHIFT 0 /* WSEQ_ADDR108 - [13:0] */
+#define WM8994_WSEQ_ADDR108_WIDTH 14 /* WSEQ_ADDR108 - [13:0] */
+
+/*
+ * R12721 (0x31B1) - Write Sequencer 433
+ */
+#define WM8994_WSEQ_DATA108_MASK 0x00FF /* WSEQ_DATA108 - [7:0] */
+#define WM8994_WSEQ_DATA108_SHIFT 0 /* WSEQ_DATA108 - [7:0] */
+#define WM8994_WSEQ_DATA108_WIDTH 8 /* WSEQ_DATA108 - [7:0] */
+
+/*
+ * R12722 (0x31B2) - Write Sequencer 434
+ */
+#define WM8994_WSEQ_DATA_WIDTH108_MASK 0x0700 /* WSEQ_DATA_WIDTH108 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH108_SHIFT 8 /* WSEQ_DATA_WIDTH108 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH108_WIDTH 3 /* WSEQ_DATA_WIDTH108 - [10:8] */
+#define WM8994_WSEQ_DATA_START108_MASK 0x000F /* WSEQ_DATA_START108 - [3:0] */
+#define WM8994_WSEQ_DATA_START108_SHIFT 0 /* WSEQ_DATA_START108 - [3:0] */
+#define WM8994_WSEQ_DATA_START108_WIDTH 4 /* WSEQ_DATA_START108 - [3:0] */
+
+/*
+ * R12723 (0x31B3) - Write Sequencer 435
+ */
+#define WM8994_WSEQ_EOS108 0x0100 /* WSEQ_EOS108 */
+#define WM8994_WSEQ_EOS108_MASK 0x0100 /* WSEQ_EOS108 */
+#define WM8994_WSEQ_EOS108_SHIFT 8 /* WSEQ_EOS108 */
+#define WM8994_WSEQ_EOS108_WIDTH 1 /* WSEQ_EOS108 */
+#define WM8994_WSEQ_DELAY108_MASK 0x000F /* WSEQ_DELAY108 - [3:0] */
+#define WM8994_WSEQ_DELAY108_SHIFT 0 /* WSEQ_DELAY108 - [3:0] */
+#define WM8994_WSEQ_DELAY108_WIDTH 4 /* WSEQ_DELAY108 - [3:0] */
+
+/*
+ * R12724 (0x31B4) - Write Sequencer 436
+ */
+#define WM8994_WSEQ_ADDR109_MASK 0x3FFF /* WSEQ_ADDR109 - [13:0] */
+#define WM8994_WSEQ_ADDR109_SHIFT 0 /* WSEQ_ADDR109 - [13:0] */
+#define WM8994_WSEQ_ADDR109_WIDTH 14 /* WSEQ_ADDR109 - [13:0] */
+
+/*
+ * R12725 (0x31B5) - Write Sequencer 437
+ */
+#define WM8994_WSEQ_DATA109_MASK 0x00FF /* WSEQ_DATA109 - [7:0] */
+#define WM8994_WSEQ_DATA109_SHIFT 0 /* WSEQ_DATA109 - [7:0] */
+#define WM8994_WSEQ_DATA109_WIDTH 8 /* WSEQ_DATA109 - [7:0] */
+
+/*
+ * R12726 (0x31B6) - Write Sequencer 438
+ */
+#define WM8994_WSEQ_DATA_WIDTH109_MASK 0x0700 /* WSEQ_DATA_WIDTH109 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH109_SHIFT 8 /* WSEQ_DATA_WIDTH109 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH109_WIDTH 3 /* WSEQ_DATA_WIDTH109 - [10:8] */
+#define WM8994_WSEQ_DATA_START109_MASK 0x000F /* WSEQ_DATA_START109 - [3:0] */
+#define WM8994_WSEQ_DATA_START109_SHIFT 0 /* WSEQ_DATA_START109 - [3:0] */
+#define WM8994_WSEQ_DATA_START109_WIDTH 4 /* WSEQ_DATA_START109 - [3:0] */
+
+/*
+ * R12727 (0x31B7) - Write Sequencer 439
+ */
+#define WM8994_WSEQ_EOS109 0x0100 /* WSEQ_EOS109 */
+#define WM8994_WSEQ_EOS109_MASK 0x0100 /* WSEQ_EOS109 */
+#define WM8994_WSEQ_EOS109_SHIFT 8 /* WSEQ_EOS109 */
+#define WM8994_WSEQ_EOS109_WIDTH 1 /* WSEQ_EOS109 */
+#define WM8994_WSEQ_DELAY109_MASK 0x000F /* WSEQ_DELAY109 - [3:0] */
+#define WM8994_WSEQ_DELAY109_SHIFT 0 /* WSEQ_DELAY109 - [3:0] */
+#define WM8994_WSEQ_DELAY109_WIDTH 4 /* WSEQ_DELAY109 - [3:0] */
+
+/*
+ * R12728 (0x31B8) - Write Sequencer 440
+ */
+#define WM8994_WSEQ_ADDR110_MASK 0x3FFF /* WSEQ_ADDR110 - [13:0] */
+#define WM8994_WSEQ_ADDR110_SHIFT 0 /* WSEQ_ADDR110 - [13:0] */
+#define WM8994_WSEQ_ADDR110_WIDTH 14 /* WSEQ_ADDR110 - [13:0] */
+
+/*
+ * R12729 (0x31B9) - Write Sequencer 441
+ */
+#define WM8994_WSEQ_DATA110_MASK 0x00FF /* WSEQ_DATA110 - [7:0] */
+#define WM8994_WSEQ_DATA110_SHIFT 0 /* WSEQ_DATA110 - [7:0] */
+#define WM8994_WSEQ_DATA110_WIDTH 8 /* WSEQ_DATA110 - [7:0] */
+
+/*
+ * R12730 (0x31BA) - Write Sequencer 442
+ */
+#define WM8994_WSEQ_DATA_WIDTH110_MASK 0x0700 /* WSEQ_DATA_WIDTH110 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH110_SHIFT 8 /* WSEQ_DATA_WIDTH110 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH110_WIDTH 3 /* WSEQ_DATA_WIDTH110 - [10:8] */
+#define WM8994_WSEQ_DATA_START110_MASK 0x000F /* WSEQ_DATA_START110 - [3:0] */
+#define WM8994_WSEQ_DATA_START110_SHIFT 0 /* WSEQ_DATA_START110 - [3:0] */
+#define WM8994_WSEQ_DATA_START110_WIDTH 4 /* WSEQ_DATA_START110 - [3:0] */
+
+/*
+ * R12731 (0x31BB) - Write Sequencer 443
+ */
+#define WM8994_WSEQ_EOS110 0x0100 /* WSEQ_EOS110 */
+#define WM8994_WSEQ_EOS110_MASK 0x0100 /* WSEQ_EOS110 */
+#define WM8994_WSEQ_EOS110_SHIFT 8 /* WSEQ_EOS110 */
+#define WM8994_WSEQ_EOS110_WIDTH 1 /* WSEQ_EOS110 */
+#define WM8994_WSEQ_DELAY110_MASK 0x000F /* WSEQ_DELAY110 - [3:0] */
+#define WM8994_WSEQ_DELAY110_SHIFT 0 /* WSEQ_DELAY110 - [3:0] */
+#define WM8994_WSEQ_DELAY110_WIDTH 4 /* WSEQ_DELAY110 - [3:0] */
+
+/*
+ * R12732 (0x31BC) - Write Sequencer 444
+ */
+#define WM8994_WSEQ_ADDR111_MASK 0x3FFF /* WSEQ_ADDR111 - [13:0] */
+#define WM8994_WSEQ_ADDR111_SHIFT 0 /* WSEQ_ADDR111 - [13:0] */
+#define WM8994_WSEQ_ADDR111_WIDTH 14 /* WSEQ_ADDR111 - [13:0] */
+
+/*
+ * R12733 (0x31BD) - Write Sequencer 445
+ */
+#define WM8994_WSEQ_DATA111_MASK 0x00FF /* WSEQ_DATA111 - [7:0] */
+#define WM8994_WSEQ_DATA111_SHIFT 0 /* WSEQ_DATA111 - [7:0] */
+#define WM8994_WSEQ_DATA111_WIDTH 8 /* WSEQ_DATA111 - [7:0] */
+
+/*
+ * R12734 (0x31BE) - Write Sequencer 446
+ */
+#define WM8994_WSEQ_DATA_WIDTH111_MASK 0x0700 /* WSEQ_DATA_WIDTH111 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH111_SHIFT 8 /* WSEQ_DATA_WIDTH111 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH111_WIDTH 3 /* WSEQ_DATA_WIDTH111 - [10:8] */
+#define WM8994_WSEQ_DATA_START111_MASK 0x000F /* WSEQ_DATA_START111 - [3:0] */
+#define WM8994_WSEQ_DATA_START111_SHIFT 0 /* WSEQ_DATA_START111 - [3:0] */
+#define WM8994_WSEQ_DATA_START111_WIDTH 4 /* WSEQ_DATA_START111 - [3:0] */
+
+/*
+ * R12735 (0x31BF) - Write Sequencer 447
+ */
+#define WM8994_WSEQ_EOS111 0x0100 /* WSEQ_EOS111 */
+#define WM8994_WSEQ_EOS111_MASK 0x0100 /* WSEQ_EOS111 */
+#define WM8994_WSEQ_EOS111_SHIFT 8 /* WSEQ_EOS111 */
+#define WM8994_WSEQ_EOS111_WIDTH 1 /* WSEQ_EOS111 */
+#define WM8994_WSEQ_DELAY111_MASK 0x000F /* WSEQ_DELAY111 - [3:0] */
+#define WM8994_WSEQ_DELAY111_SHIFT 0 /* WSEQ_DELAY111 - [3:0] */
+#define WM8994_WSEQ_DELAY111_WIDTH 4 /* WSEQ_DELAY111 - [3:0] */
+
+/*
+ * R12736 (0x31C0) - Write Sequencer 448
+ */
+#define WM8994_WSEQ_ADDR112_MASK 0x3FFF /* WSEQ_ADDR112 - [13:0] */
+#define WM8994_WSEQ_ADDR112_SHIFT 0 /* WSEQ_ADDR112 - [13:0] */
+#define WM8994_WSEQ_ADDR112_WIDTH 14 /* WSEQ_ADDR112 - [13:0] */
+
+/*
+ * R12737 (0x31C1) - Write Sequencer 449
+ */
+#define WM8994_WSEQ_DATA112_MASK 0x00FF /* WSEQ_DATA112 - [7:0] */
+#define WM8994_WSEQ_DATA112_SHIFT 0 /* WSEQ_DATA112 - [7:0] */
+#define WM8994_WSEQ_DATA112_WIDTH 8 /* WSEQ_DATA112 - [7:0] */
+
+/*
+ * R12738 (0x31C2) - Write Sequencer 450
+ */
+#define WM8994_WSEQ_DATA_WIDTH112_MASK 0x0700 /* WSEQ_DATA_WIDTH112 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH112_SHIFT 8 /* WSEQ_DATA_WIDTH112 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH112_WIDTH 3 /* WSEQ_DATA_WIDTH112 - [10:8] */
+#define WM8994_WSEQ_DATA_START112_MASK 0x000F /* WSEQ_DATA_START112 - [3:0] */
+#define WM8994_WSEQ_DATA_START112_SHIFT 0 /* WSEQ_DATA_START112 - [3:0] */
+#define WM8994_WSEQ_DATA_START112_WIDTH 4 /* WSEQ_DATA_START112 - [3:0] */
+
+/*
+ * R12739 (0x31C3) - Write Sequencer 451
+ */
+#define WM8994_WSEQ_EOS112 0x0100 /* WSEQ_EOS112 */
+#define WM8994_WSEQ_EOS112_MASK 0x0100 /* WSEQ_EOS112 */
+#define WM8994_WSEQ_EOS112_SHIFT 8 /* WSEQ_EOS112 */
+#define WM8994_WSEQ_EOS112_WIDTH 1 /* WSEQ_EOS112 */
+#define WM8994_WSEQ_DELAY112_MASK 0x000F /* WSEQ_DELAY112 - [3:0] */
+#define WM8994_WSEQ_DELAY112_SHIFT 0 /* WSEQ_DELAY112 - [3:0] */
+#define WM8994_WSEQ_DELAY112_WIDTH 4 /* WSEQ_DELAY112 - [3:0] */
+
+/*
+ * R12740 (0x31C4) - Write Sequencer 452
+ */
+#define WM8994_WSEQ_ADDR113_MASK 0x3FFF /* WSEQ_ADDR113 - [13:0] */
+#define WM8994_WSEQ_ADDR113_SHIFT 0 /* WSEQ_ADDR113 - [13:0] */
+#define WM8994_WSEQ_ADDR113_WIDTH 14 /* WSEQ_ADDR113 - [13:0] */
+
+/*
+ * R12741 (0x31C5) - Write Sequencer 453
+ */
+#define WM8994_WSEQ_DATA113_MASK 0x00FF /* WSEQ_DATA113 - [7:0] */
+#define WM8994_WSEQ_DATA113_SHIFT 0 /* WSEQ_DATA113 - [7:0] */
+#define WM8994_WSEQ_DATA113_WIDTH 8 /* WSEQ_DATA113 - [7:0] */
+
+/*
+ * R12742 (0x31C6) - Write Sequencer 454
+ */
+#define WM8994_WSEQ_DATA_WIDTH113_MASK 0x0700 /* WSEQ_DATA_WIDTH113 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH113_SHIFT 8 /* WSEQ_DATA_WIDTH113 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH113_WIDTH 3 /* WSEQ_DATA_WIDTH113 - [10:8] */
+#define WM8994_WSEQ_DATA_START113_MASK 0x000F /* WSEQ_DATA_START113 - [3:0] */
+#define WM8994_WSEQ_DATA_START113_SHIFT 0 /* WSEQ_DATA_START113 - [3:0] */
+#define WM8994_WSEQ_DATA_START113_WIDTH 4 /* WSEQ_DATA_START113 - [3:0] */
+
+/*
+ * R12743 (0x31C7) - Write Sequencer 455
+ */
+#define WM8994_WSEQ_EOS113 0x0100 /* WSEQ_EOS113 */
+#define WM8994_WSEQ_EOS113_MASK 0x0100 /* WSEQ_EOS113 */
+#define WM8994_WSEQ_EOS113_SHIFT 8 /* WSEQ_EOS113 */
+#define WM8994_WSEQ_EOS113_WIDTH 1 /* WSEQ_EOS113 */
+#define WM8994_WSEQ_DELAY113_MASK 0x000F /* WSEQ_DELAY113 - [3:0] */
+#define WM8994_WSEQ_DELAY113_SHIFT 0 /* WSEQ_DELAY113 - [3:0] */
+#define WM8994_WSEQ_DELAY113_WIDTH 4 /* WSEQ_DELAY113 - [3:0] */
+
+/*
+ * R12744 (0x31C8) - Write Sequencer 456
+ */
+#define WM8994_WSEQ_ADDR114_MASK 0x3FFF /* WSEQ_ADDR114 - [13:0] */
+#define WM8994_WSEQ_ADDR114_SHIFT 0 /* WSEQ_ADDR114 - [13:0] */
+#define WM8994_WSEQ_ADDR114_WIDTH 14 /* WSEQ_ADDR114 - [13:0] */
+
+/*
+ * R12745 (0x31C9) - Write Sequencer 457
+ */
+#define WM8994_WSEQ_DATA114_MASK 0x00FF /* WSEQ_DATA114 - [7:0] */
+#define WM8994_WSEQ_DATA114_SHIFT 0 /* WSEQ_DATA114 - [7:0] */
+#define WM8994_WSEQ_DATA114_WIDTH 8 /* WSEQ_DATA114 - [7:0] */
+
+/*
+ * R12746 (0x31CA) - Write Sequencer 458
+ */
+#define WM8994_WSEQ_DATA_WIDTH114_MASK 0x0700 /* WSEQ_DATA_WIDTH114 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH114_SHIFT 8 /* WSEQ_DATA_WIDTH114 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH114_WIDTH 3 /* WSEQ_DATA_WIDTH114 - [10:8] */
+#define WM8994_WSEQ_DATA_START114_MASK 0x000F /* WSEQ_DATA_START114 - [3:0] */
+#define WM8994_WSEQ_DATA_START114_SHIFT 0 /* WSEQ_DATA_START114 - [3:0] */
+#define WM8994_WSEQ_DATA_START114_WIDTH 4 /* WSEQ_DATA_START114 - [3:0] */
+
+/*
+ * R12747 (0x31CB) - Write Sequencer 459
+ */
+#define WM8994_WSEQ_EOS114 0x0100 /* WSEQ_EOS114 */
+#define WM8994_WSEQ_EOS114_MASK 0x0100 /* WSEQ_EOS114 */
+#define WM8994_WSEQ_EOS114_SHIFT 8 /* WSEQ_EOS114 */
+#define WM8994_WSEQ_EOS114_WIDTH 1 /* WSEQ_EOS114 */
+#define WM8994_WSEQ_DELAY114_MASK 0x000F /* WSEQ_DELAY114 - [3:0] */
+#define WM8994_WSEQ_DELAY114_SHIFT 0 /* WSEQ_DELAY114 - [3:0] */
+#define WM8994_WSEQ_DELAY114_WIDTH 4 /* WSEQ_DELAY114 - [3:0] */
+
+/*
+ * R12748 (0x31CC) - Write Sequencer 460
+ */
+#define WM8994_WSEQ_ADDR115_MASK 0x3FFF /* WSEQ_ADDR115 - [13:0] */
+#define WM8994_WSEQ_ADDR115_SHIFT 0 /* WSEQ_ADDR115 - [13:0] */
+#define WM8994_WSEQ_ADDR115_WIDTH 14 /* WSEQ_ADDR115 - [13:0] */
+
+/*
+ * R12749 (0x31CD) - Write Sequencer 461
+ */
+#define WM8994_WSEQ_DATA115_MASK 0x00FF /* WSEQ_DATA115 - [7:0] */
+#define WM8994_WSEQ_DATA115_SHIFT 0 /* WSEQ_DATA115 - [7:0] */
+#define WM8994_WSEQ_DATA115_WIDTH 8 /* WSEQ_DATA115 - [7:0] */
+
+/*
+ * R12750 (0x31CE) - Write Sequencer 462
+ */
+#define WM8994_WSEQ_DATA_WIDTH115_MASK 0x0700 /* WSEQ_DATA_WIDTH115 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH115_SHIFT 8 /* WSEQ_DATA_WIDTH115 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH115_WIDTH 3 /* WSEQ_DATA_WIDTH115 - [10:8] */
+#define WM8994_WSEQ_DATA_START115_MASK 0x000F /* WSEQ_DATA_START115 - [3:0] */
+#define WM8994_WSEQ_DATA_START115_SHIFT 0 /* WSEQ_DATA_START115 - [3:0] */
+#define WM8994_WSEQ_DATA_START115_WIDTH 4 /* WSEQ_DATA_START115 - [3:0] */
+
+/*
+ * R12751 (0x31CF) - Write Sequencer 463
+ */
+#define WM8994_WSEQ_EOS115 0x0100 /* WSEQ_EOS115 */
+#define WM8994_WSEQ_EOS115_MASK 0x0100 /* WSEQ_EOS115 */
+#define WM8994_WSEQ_EOS115_SHIFT 8 /* WSEQ_EOS115 */
+#define WM8994_WSEQ_EOS115_WIDTH 1 /* WSEQ_EOS115 */
+#define WM8994_WSEQ_DELAY115_MASK 0x000F /* WSEQ_DELAY115 - [3:0] */
+#define WM8994_WSEQ_DELAY115_SHIFT 0 /* WSEQ_DELAY115 - [3:0] */
+#define WM8994_WSEQ_DELAY115_WIDTH 4 /* WSEQ_DELAY115 - [3:0] */
+
+/*
+ * R12752 (0x31D0) - Write Sequencer 464
+ */
+#define WM8994_WSEQ_ADDR116_MASK 0x3FFF /* WSEQ_ADDR116 - [13:0] */
+#define WM8994_WSEQ_ADDR116_SHIFT 0 /* WSEQ_ADDR116 - [13:0] */
+#define WM8994_WSEQ_ADDR116_WIDTH 14 /* WSEQ_ADDR116 - [13:0] */
+
+/*
+ * R12753 (0x31D1) - Write Sequencer 465
+ */
+#define WM8994_WSEQ_DATA116_MASK 0x00FF /* WSEQ_DATA116 - [7:0] */
+#define WM8994_WSEQ_DATA116_SHIFT 0 /* WSEQ_DATA116 - [7:0] */
+#define WM8994_WSEQ_DATA116_WIDTH 8 /* WSEQ_DATA116 - [7:0] */
+
+/*
+ * R12754 (0x31D2) - Write Sequencer 466
+ */
+#define WM8994_WSEQ_DATA_WIDTH116_MASK 0x0700 /* WSEQ_DATA_WIDTH116 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH116_SHIFT 8 /* WSEQ_DATA_WIDTH116 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH116_WIDTH 3 /* WSEQ_DATA_WIDTH116 - [10:8] */
+#define WM8994_WSEQ_DATA_START116_MASK 0x000F /* WSEQ_DATA_START116 - [3:0] */
+#define WM8994_WSEQ_DATA_START116_SHIFT 0 /* WSEQ_DATA_START116 - [3:0] */
+#define WM8994_WSEQ_DATA_START116_WIDTH 4 /* WSEQ_DATA_START116 - [3:0] */
+
+/*
+ * R12755 (0x31D3) - Write Sequencer 467
+ */
+#define WM8994_WSEQ_EOS116 0x0100 /* WSEQ_EOS116 */
+#define WM8994_WSEQ_EOS116_MASK 0x0100 /* WSEQ_EOS116 */
+#define WM8994_WSEQ_EOS116_SHIFT 8 /* WSEQ_EOS116 */
+#define WM8994_WSEQ_EOS116_WIDTH 1 /* WSEQ_EOS116 */
+#define WM8994_WSEQ_DELAY116_MASK 0x000F /* WSEQ_DELAY116 - [3:0] */
+#define WM8994_WSEQ_DELAY116_SHIFT 0 /* WSEQ_DELAY116 - [3:0] */
+#define WM8994_WSEQ_DELAY116_WIDTH 4 /* WSEQ_DELAY116 - [3:0] */
+
+/*
+ * R12756 (0x31D4) - Write Sequencer 468
+ */
+#define WM8994_WSEQ_ADDR117_MASK 0x3FFF /* WSEQ_ADDR117 - [13:0] */
+#define WM8994_WSEQ_ADDR117_SHIFT 0 /* WSEQ_ADDR117 - [13:0] */
+#define WM8994_WSEQ_ADDR117_WIDTH 14 /* WSEQ_ADDR117 - [13:0] */
+
+/*
+ * R12757 (0x31D5) - Write Sequencer 469
+ */
+#define WM8994_WSEQ_DATA117_MASK 0x00FF /* WSEQ_DATA117 - [7:0] */
+#define WM8994_WSEQ_DATA117_SHIFT 0 /* WSEQ_DATA117 - [7:0] */
+#define WM8994_WSEQ_DATA117_WIDTH 8 /* WSEQ_DATA117 - [7:0] */
+
+/*
+ * R12758 (0x31D6) - Write Sequencer 470
+ */
+#define WM8994_WSEQ_DATA_WIDTH117_MASK 0x0700 /* WSEQ_DATA_WIDTH117 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH117_SHIFT 8 /* WSEQ_DATA_WIDTH117 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH117_WIDTH 3 /* WSEQ_DATA_WIDTH117 - [10:8] */
+#define WM8994_WSEQ_DATA_START117_MASK 0x000F /* WSEQ_DATA_START117 - [3:0] */
+#define WM8994_WSEQ_DATA_START117_SHIFT 0 /* WSEQ_DATA_START117 - [3:0] */
+#define WM8994_WSEQ_DATA_START117_WIDTH 4 /* WSEQ_DATA_START117 - [3:0] */
+
+/*
+ * R12759 (0x31D7) - Write Sequencer 471
+ */
+#define WM8994_WSEQ_EOS117 0x0100 /* WSEQ_EOS117 */
+#define WM8994_WSEQ_EOS117_MASK 0x0100 /* WSEQ_EOS117 */
+#define WM8994_WSEQ_EOS117_SHIFT 8 /* WSEQ_EOS117 */
+#define WM8994_WSEQ_EOS117_WIDTH 1 /* WSEQ_EOS117 */
+#define WM8994_WSEQ_DELAY117_MASK 0x000F /* WSEQ_DELAY117 - [3:0] */
+#define WM8994_WSEQ_DELAY117_SHIFT 0 /* WSEQ_DELAY117 - [3:0] */
+#define WM8994_WSEQ_DELAY117_WIDTH 4 /* WSEQ_DELAY117 - [3:0] */
+
+/*
+ * R12760 (0x31D8) - Write Sequencer 472
+ */
+#define WM8994_WSEQ_ADDR118_MASK 0x3FFF /* WSEQ_ADDR118 - [13:0] */
+#define WM8994_WSEQ_ADDR118_SHIFT 0 /* WSEQ_ADDR118 - [13:0] */
+#define WM8994_WSEQ_ADDR118_WIDTH 14 /* WSEQ_ADDR118 - [13:0] */
+
+/*
+ * R12761 (0x31D9) - Write Sequencer 473
+ */
+#define WM8994_WSEQ_DATA118_MASK 0x00FF /* WSEQ_DATA118 - [7:0] */
+#define WM8994_WSEQ_DATA118_SHIFT 0 /* WSEQ_DATA118 - [7:0] */
+#define WM8994_WSEQ_DATA118_WIDTH 8 /* WSEQ_DATA118 - [7:0] */
+
+/*
+ * R12762 (0x31DA) - Write Sequencer 474
+ */
+#define WM8994_WSEQ_DATA_WIDTH118_MASK 0x0700 /* WSEQ_DATA_WIDTH118 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH118_SHIFT 8 /* WSEQ_DATA_WIDTH118 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH118_WIDTH 3 /* WSEQ_DATA_WIDTH118 - [10:8] */
+#define WM8994_WSEQ_DATA_START118_MASK 0x000F /* WSEQ_DATA_START118 - [3:0] */
+#define WM8994_WSEQ_DATA_START118_SHIFT 0 /* WSEQ_DATA_START118 - [3:0] */
+#define WM8994_WSEQ_DATA_START118_WIDTH 4 /* WSEQ_DATA_START118 - [3:0] */
+
+/*
+ * R12763 (0x31DB) - Write Sequencer 475
+ */
+#define WM8994_WSEQ_EOS118 0x0100 /* WSEQ_EOS118 */
+#define WM8994_WSEQ_EOS118_MASK 0x0100 /* WSEQ_EOS118 */
+#define WM8994_WSEQ_EOS118_SHIFT 8 /* WSEQ_EOS118 */
+#define WM8994_WSEQ_EOS118_WIDTH 1 /* WSEQ_EOS118 */
+#define WM8994_WSEQ_DELAY118_MASK 0x000F /* WSEQ_DELAY118 - [3:0] */
+#define WM8994_WSEQ_DELAY118_SHIFT 0 /* WSEQ_DELAY118 - [3:0] */
+#define WM8994_WSEQ_DELAY118_WIDTH 4 /* WSEQ_DELAY118 - [3:0] */
+
+/*
+ * R12764 (0x31DC) - Write Sequencer 476
+ */
+#define WM8994_WSEQ_ADDR119_MASK 0x3FFF /* WSEQ_ADDR119 - [13:0] */
+#define WM8994_WSEQ_ADDR119_SHIFT 0 /* WSEQ_ADDR119 - [13:0] */
+#define WM8994_WSEQ_ADDR119_WIDTH 14 /* WSEQ_ADDR119 - [13:0] */
+
+/*
+ * R12765 (0x31DD) - Write Sequencer 477
+ */
+#define WM8994_WSEQ_DATA119_MASK 0x00FF /* WSEQ_DATA119 - [7:0] */
+#define WM8994_WSEQ_DATA119_SHIFT 0 /* WSEQ_DATA119 - [7:0] */
+#define WM8994_WSEQ_DATA119_WIDTH 8 /* WSEQ_DATA119 - [7:0] */
+
+/*
+ * R12766 (0x31DE) - Write Sequencer 478
+ */
+#define WM8994_WSEQ_DATA_WIDTH119_MASK 0x0700 /* WSEQ_DATA_WIDTH119 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH119_SHIFT 8 /* WSEQ_DATA_WIDTH119 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH119_WIDTH 3 /* WSEQ_DATA_WIDTH119 - [10:8] */
+#define WM8994_WSEQ_DATA_START119_MASK 0x000F /* WSEQ_DATA_START119 - [3:0] */
+#define WM8994_WSEQ_DATA_START119_SHIFT 0 /* WSEQ_DATA_START119 - [3:0] */
+#define WM8994_WSEQ_DATA_START119_WIDTH 4 /* WSEQ_DATA_START119 - [3:0] */
+
+/*
+ * R12767 (0x31DF) - Write Sequencer 479
+ */
+#define WM8994_WSEQ_EOS119 0x0100 /* WSEQ_EOS119 */
+#define WM8994_WSEQ_EOS119_MASK 0x0100 /* WSEQ_EOS119 */
+#define WM8994_WSEQ_EOS119_SHIFT 8 /* WSEQ_EOS119 */
+#define WM8994_WSEQ_EOS119_WIDTH 1 /* WSEQ_EOS119 */
+#define WM8994_WSEQ_DELAY119_MASK 0x000F /* WSEQ_DELAY119 - [3:0] */
+#define WM8994_WSEQ_DELAY119_SHIFT 0 /* WSEQ_DELAY119 - [3:0] */
+#define WM8994_WSEQ_DELAY119_WIDTH 4 /* WSEQ_DELAY119 - [3:0] */
+
+/*
+ * R12768 (0x31E0) - Write Sequencer 480
+ */
+#define WM8994_WSEQ_ADDR120_MASK 0x3FFF /* WSEQ_ADDR120 - [13:0] */
+#define WM8994_WSEQ_ADDR120_SHIFT 0 /* WSEQ_ADDR120 - [13:0] */
+#define WM8994_WSEQ_ADDR120_WIDTH 14 /* WSEQ_ADDR120 - [13:0] */
+
+/*
+ * R12769 (0x31E1) - Write Sequencer 481
+ */
+#define WM8994_WSEQ_DATA120_MASK 0x00FF /* WSEQ_DATA120 - [7:0] */
+#define WM8994_WSEQ_DATA120_SHIFT 0 /* WSEQ_DATA120 - [7:0] */
+#define WM8994_WSEQ_DATA120_WIDTH 8 /* WSEQ_DATA120 - [7:0] */
+
+/*
+ * R12770 (0x31E2) - Write Sequencer 482
+ */
+#define WM8994_WSEQ_DATA_WIDTH120_MASK 0x0700 /* WSEQ_DATA_WIDTH120 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH120_SHIFT 8 /* WSEQ_DATA_WIDTH120 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH120_WIDTH 3 /* WSEQ_DATA_WIDTH120 - [10:8] */
+#define WM8994_WSEQ_DATA_START120_MASK 0x000F /* WSEQ_DATA_START120 - [3:0] */
+#define WM8994_WSEQ_DATA_START120_SHIFT 0 /* WSEQ_DATA_START120 - [3:0] */
+#define WM8994_WSEQ_DATA_START120_WIDTH 4 /* WSEQ_DATA_START120 - [3:0] */
+
+/*
+ * R12771 (0x31E3) - Write Sequencer 483
+ */
+#define WM8994_WSEQ_EOS120 0x0100 /* WSEQ_EOS120 */
+#define WM8994_WSEQ_EOS120_MASK 0x0100 /* WSEQ_EOS120 */
+#define WM8994_WSEQ_EOS120_SHIFT 8 /* WSEQ_EOS120 */
+#define WM8994_WSEQ_EOS120_WIDTH 1 /* WSEQ_EOS120 */
+#define WM8994_WSEQ_DELAY120_MASK 0x000F /* WSEQ_DELAY120 - [3:0] */
+#define WM8994_WSEQ_DELAY120_SHIFT 0 /* WSEQ_DELAY120 - [3:0] */
+#define WM8994_WSEQ_DELAY120_WIDTH 4 /* WSEQ_DELAY120 - [3:0] */
+
+/*
+ * R12772 (0x31E4) - Write Sequencer 484
+ */
+#define WM8994_WSEQ_ADDR121_MASK 0x3FFF /* WSEQ_ADDR121 - [13:0] */
+#define WM8994_WSEQ_ADDR121_SHIFT 0 /* WSEQ_ADDR121 - [13:0] */
+#define WM8994_WSEQ_ADDR121_WIDTH 14 /* WSEQ_ADDR121 - [13:0] */
+
+/*
+ * R12773 (0x31E5) - Write Sequencer 485
+ */
+#define WM8994_WSEQ_DATA121_MASK 0x00FF /* WSEQ_DATA121 - [7:0] */
+#define WM8994_WSEQ_DATA121_SHIFT 0 /* WSEQ_DATA121 - [7:0] */
+#define WM8994_WSEQ_DATA121_WIDTH 8 /* WSEQ_DATA121 - [7:0] */
+
+/*
+ * R12774 (0x31E6) - Write Sequencer 486
+ */
+#define WM8994_WSEQ_DATA_WIDTH121_MASK 0x0700 /* WSEQ_DATA_WIDTH121 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH121_SHIFT 8 /* WSEQ_DATA_WIDTH121 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH121_WIDTH 3 /* WSEQ_DATA_WIDTH121 - [10:8] */
+#define WM8994_WSEQ_DATA_START121_MASK 0x000F /* WSEQ_DATA_START121 - [3:0] */
+#define WM8994_WSEQ_DATA_START121_SHIFT 0 /* WSEQ_DATA_START121 - [3:0] */
+#define WM8994_WSEQ_DATA_START121_WIDTH 4 /* WSEQ_DATA_START121 - [3:0] */
+
+/*
+ * R12775 (0x31E7) - Write Sequencer 487
+ */
+#define WM8994_WSEQ_EOS121 0x0100 /* WSEQ_EOS121 */
+#define WM8994_WSEQ_EOS121_MASK 0x0100 /* WSEQ_EOS121 */
+#define WM8994_WSEQ_EOS121_SHIFT 8 /* WSEQ_EOS121 */
+#define WM8994_WSEQ_EOS121_WIDTH 1 /* WSEQ_EOS121 */
+#define WM8994_WSEQ_DELAY121_MASK 0x000F /* WSEQ_DELAY121 - [3:0] */
+#define WM8994_WSEQ_DELAY121_SHIFT 0 /* WSEQ_DELAY121 - [3:0] */
+#define WM8994_WSEQ_DELAY121_WIDTH 4 /* WSEQ_DELAY121 - [3:0] */
+
+/*
+ * R12776 (0x31E8) - Write Sequencer 488
+ */
+#define WM8994_WSEQ_ADDR122_MASK 0x3FFF /* WSEQ_ADDR122 - [13:0] */
+#define WM8994_WSEQ_ADDR122_SHIFT 0 /* WSEQ_ADDR122 - [13:0] */
+#define WM8994_WSEQ_ADDR122_WIDTH 14 /* WSEQ_ADDR122 - [13:0] */
+
+/*
+ * R12777 (0x31E9) - Write Sequencer 489
+ */
+#define WM8994_WSEQ_DATA122_MASK 0x00FF /* WSEQ_DATA122 - [7:0] */
+#define WM8994_WSEQ_DATA122_SHIFT 0 /* WSEQ_DATA122 - [7:0] */
+#define WM8994_WSEQ_DATA122_WIDTH 8 /* WSEQ_DATA122 - [7:0] */
+
+/*
+ * R12778 (0x31EA) - Write Sequencer 490
+ */
+#define WM8994_WSEQ_DATA_WIDTH122_MASK 0x0700 /* WSEQ_DATA_WIDTH122 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH122_SHIFT 8 /* WSEQ_DATA_WIDTH122 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH122_WIDTH 3 /* WSEQ_DATA_WIDTH122 - [10:8] */
+#define WM8994_WSEQ_DATA_START122_MASK 0x000F /* WSEQ_DATA_START122 - [3:0] */
+#define WM8994_WSEQ_DATA_START122_SHIFT 0 /* WSEQ_DATA_START122 - [3:0] */
+#define WM8994_WSEQ_DATA_START122_WIDTH 4 /* WSEQ_DATA_START122 - [3:0] */
+
+/*
+ * R12779 (0x31EB) - Write Sequencer 491
+ */
+#define WM8994_WSEQ_EOS122 0x0100 /* WSEQ_EOS122 */
+#define WM8994_WSEQ_EOS122_MASK 0x0100 /* WSEQ_EOS122 */
+#define WM8994_WSEQ_EOS122_SHIFT 8 /* WSEQ_EOS122 */
+#define WM8994_WSEQ_EOS122_WIDTH 1 /* WSEQ_EOS122 */
+#define WM8994_WSEQ_DELAY122_MASK 0x000F /* WSEQ_DELAY122 - [3:0] */
+#define WM8994_WSEQ_DELAY122_SHIFT 0 /* WSEQ_DELAY122 - [3:0] */
+#define WM8994_WSEQ_DELAY122_WIDTH 4 /* WSEQ_DELAY122 - [3:0] */
+
+/*
+ * R12780 (0x31EC) - Write Sequencer 492
+ */
+#define WM8994_WSEQ_ADDR123_MASK 0x3FFF /* WSEQ_ADDR123 - [13:0] */
+#define WM8994_WSEQ_ADDR123_SHIFT 0 /* WSEQ_ADDR123 - [13:0] */
+#define WM8994_WSEQ_ADDR123_WIDTH 14 /* WSEQ_ADDR123 - [13:0] */
+
+/*
+ * R12781 (0x31ED) - Write Sequencer 493
+ */
+#define WM8994_WSEQ_DATA123_MASK 0x00FF /* WSEQ_DATA123 - [7:0] */
+#define WM8994_WSEQ_DATA123_SHIFT 0 /* WSEQ_DATA123 - [7:0] */
+#define WM8994_WSEQ_DATA123_WIDTH 8 /* WSEQ_DATA123 - [7:0] */
+
+/*
+ * R12782 (0x31EE) - Write Sequencer 494
+ */
+#define WM8994_WSEQ_DATA_WIDTH123_MASK 0x0700 /* WSEQ_DATA_WIDTH123 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH123_SHIFT 8 /* WSEQ_DATA_WIDTH123 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH123_WIDTH 3 /* WSEQ_DATA_WIDTH123 - [10:8] */
+#define WM8994_WSEQ_DATA_START123_MASK 0x000F /* WSEQ_DATA_START123 - [3:0] */
+#define WM8994_WSEQ_DATA_START123_SHIFT 0 /* WSEQ_DATA_START123 - [3:0] */
+#define WM8994_WSEQ_DATA_START123_WIDTH 4 /* WSEQ_DATA_START123 - [3:0] */
+
+/*
+ * R12783 (0x31EF) - Write Sequencer 495
+ */
+#define WM8994_WSEQ_EOS123 0x0100 /* WSEQ_EOS123 */
+#define WM8994_WSEQ_EOS123_MASK 0x0100 /* WSEQ_EOS123 */
+#define WM8994_WSEQ_EOS123_SHIFT 8 /* WSEQ_EOS123 */
+#define WM8994_WSEQ_EOS123_WIDTH 1 /* WSEQ_EOS123 */
+#define WM8994_WSEQ_DELAY123_MASK 0x000F /* WSEQ_DELAY123 - [3:0] */
+#define WM8994_WSEQ_DELAY123_SHIFT 0 /* WSEQ_DELAY123 - [3:0] */
+#define WM8994_WSEQ_DELAY123_WIDTH 4 /* WSEQ_DELAY123 - [3:0] */
+
+/*
+ * R12784 (0x31F0) - Write Sequencer 496
+ */
+#define WM8994_WSEQ_ADDR124_MASK 0x3FFF /* WSEQ_ADDR124 - [13:0] */
+#define WM8994_WSEQ_ADDR124_SHIFT 0 /* WSEQ_ADDR124 - [13:0] */
+#define WM8994_WSEQ_ADDR124_WIDTH 14 /* WSEQ_ADDR124 - [13:0] */
+
+/*
+ * R12785 (0x31F1) - Write Sequencer 497
+ */
+#define WM8994_WSEQ_DATA124_MASK 0x00FF /* WSEQ_DATA124 - [7:0] */
+#define WM8994_WSEQ_DATA124_SHIFT 0 /* WSEQ_DATA124 - [7:0] */
+#define WM8994_WSEQ_DATA124_WIDTH 8 /* WSEQ_DATA124 - [7:0] */
+
+/*
+ * R12786 (0x31F2) - Write Sequencer 498
+ */
+#define WM8994_WSEQ_DATA_WIDTH124_MASK 0x0700 /* WSEQ_DATA_WIDTH124 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH124_SHIFT 8 /* WSEQ_DATA_WIDTH124 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH124_WIDTH 3 /* WSEQ_DATA_WIDTH124 - [10:8] */
+#define WM8994_WSEQ_DATA_START124_MASK 0x000F /* WSEQ_DATA_START124 - [3:0] */
+#define WM8994_WSEQ_DATA_START124_SHIFT 0 /* WSEQ_DATA_START124 - [3:0] */
+#define WM8994_WSEQ_DATA_START124_WIDTH 4 /* WSEQ_DATA_START124 - [3:0] */
+
+/*
+ * R12787 (0x31F3) - Write Sequencer 499
+ */
+#define WM8994_WSEQ_EOS124 0x0100 /* WSEQ_EOS124 */
+#define WM8994_WSEQ_EOS124_MASK 0x0100 /* WSEQ_EOS124 */
+#define WM8994_WSEQ_EOS124_SHIFT 8 /* WSEQ_EOS124 */
+#define WM8994_WSEQ_EOS124_WIDTH 1 /* WSEQ_EOS124 */
+#define WM8994_WSEQ_DELAY124_MASK 0x000F /* WSEQ_DELAY124 - [3:0] */
+#define WM8994_WSEQ_DELAY124_SHIFT 0 /* WSEQ_DELAY124 - [3:0] */
+#define WM8994_WSEQ_DELAY124_WIDTH 4 /* WSEQ_DELAY124 - [3:0] */
+
+/*
+ * R12788 (0x31F4) - Write Sequencer 500
+ */
+#define WM8994_WSEQ_ADDR125_MASK 0x3FFF /* WSEQ_ADDR125 - [13:0] */
+#define WM8994_WSEQ_ADDR125_SHIFT 0 /* WSEQ_ADDR125 - [13:0] */
+#define WM8994_WSEQ_ADDR125_WIDTH 14 /* WSEQ_ADDR125 - [13:0] */
+
+/*
+ * R12789 (0x31F5) - Write Sequencer 501
+ */
+#define WM8994_WSEQ_DATA125_MASK 0x00FF /* WSEQ_DATA125 - [7:0] */
+#define WM8994_WSEQ_DATA125_SHIFT 0 /* WSEQ_DATA125 - [7:0] */
+#define WM8994_WSEQ_DATA125_WIDTH 8 /* WSEQ_DATA125 - [7:0] */
+
+/*
+ * R12790 (0x31F6) - Write Sequencer 502
+ */
+#define WM8994_WSEQ_DATA_WIDTH125_MASK 0x0700 /* WSEQ_DATA_WIDTH125 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH125_SHIFT 8 /* WSEQ_DATA_WIDTH125 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH125_WIDTH 3 /* WSEQ_DATA_WIDTH125 - [10:8] */
+#define WM8994_WSEQ_DATA_START125_MASK 0x000F /* WSEQ_DATA_START125 - [3:0] */
+#define WM8994_WSEQ_DATA_START125_SHIFT 0 /* WSEQ_DATA_START125 - [3:0] */
+#define WM8994_WSEQ_DATA_START125_WIDTH 4 /* WSEQ_DATA_START125 - [3:0] */
+
+/*
+ * R12791 (0x31F7) - Write Sequencer 503
+ */
+#define WM8994_WSEQ_EOS125 0x0100 /* WSEQ_EOS125 */
+#define WM8994_WSEQ_EOS125_MASK 0x0100 /* WSEQ_EOS125 */
+#define WM8994_WSEQ_EOS125_SHIFT 8 /* WSEQ_EOS125 */
+#define WM8994_WSEQ_EOS125_WIDTH 1 /* WSEQ_EOS125 */
+#define WM8994_WSEQ_DELAY125_MASK 0x000F /* WSEQ_DELAY125 - [3:0] */
+#define WM8994_WSEQ_DELAY125_SHIFT 0 /* WSEQ_DELAY125 - [3:0] */
+#define WM8994_WSEQ_DELAY125_WIDTH 4 /* WSEQ_DELAY125 - [3:0] */
+
+/*
+ * R12792 (0x31F8) - Write Sequencer 504
+ */
+#define WM8994_WSEQ_ADDR126_MASK 0x3FFF /* WSEQ_ADDR126 - [13:0] */
+#define WM8994_WSEQ_ADDR126_SHIFT 0 /* WSEQ_ADDR126 - [13:0] */
+#define WM8994_WSEQ_ADDR126_WIDTH 14 /* WSEQ_ADDR126 - [13:0] */
+
+/*
+ * R12793 (0x31F9) - Write Sequencer 505
+ */
+#define WM8994_WSEQ_DATA126_MASK 0x00FF /* WSEQ_DATA126 - [7:0] */
+#define WM8994_WSEQ_DATA126_SHIFT 0 /* WSEQ_DATA126 - [7:0] */
+#define WM8994_WSEQ_DATA126_WIDTH 8 /* WSEQ_DATA126 - [7:0] */
+
+/*
+ * R12794 (0x31FA) - Write Sequencer 506
+ */
+#define WM8994_WSEQ_DATA_WIDTH126_MASK 0x0700 /* WSEQ_DATA_WIDTH126 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH126_SHIFT 8 /* WSEQ_DATA_WIDTH126 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH126_WIDTH 3 /* WSEQ_DATA_WIDTH126 - [10:8] */
+#define WM8994_WSEQ_DATA_START126_MASK 0x000F /* WSEQ_DATA_START126 - [3:0] */
+#define WM8994_WSEQ_DATA_START126_SHIFT 0 /* WSEQ_DATA_START126 - [3:0] */
+#define WM8994_WSEQ_DATA_START126_WIDTH 4 /* WSEQ_DATA_START126 - [3:0] */
+
+/*
+ * R12795 (0x31FB) - Write Sequencer 507
+ */
+#define WM8994_WSEQ_EOS126 0x0100 /* WSEQ_EOS126 */
+#define WM8994_WSEQ_EOS126_MASK 0x0100 /* WSEQ_EOS126 */
+#define WM8994_WSEQ_EOS126_SHIFT 8 /* WSEQ_EOS126 */
+#define WM8994_WSEQ_EOS126_WIDTH 1 /* WSEQ_EOS126 */
+#define WM8994_WSEQ_DELAY126_MASK 0x000F /* WSEQ_DELAY126 - [3:0] */
+#define WM8994_WSEQ_DELAY126_SHIFT 0 /* WSEQ_DELAY126 - [3:0] */
+#define WM8994_WSEQ_DELAY126_WIDTH 4 /* WSEQ_DELAY126 - [3:0] */
+
+/*
+ * R12796 (0x31FC) - Write Sequencer 508
+ */
+#define WM8994_WSEQ_ADDR127_MASK 0x3FFF /* WSEQ_ADDR127 - [13:0] */
+#define WM8994_WSEQ_ADDR127_SHIFT 0 /* WSEQ_ADDR127 - [13:0] */
+#define WM8994_WSEQ_ADDR127_WIDTH 14 /* WSEQ_ADDR127 - [13:0] */
+
+/*
+ * R12797 (0x31FD) - Write Sequencer 509
+ */
+#define WM8994_WSEQ_DATA127_MASK 0x00FF /* WSEQ_DATA127 - [7:0] */
+#define WM8994_WSEQ_DATA127_SHIFT 0 /* WSEQ_DATA127 - [7:0] */
+#define WM8994_WSEQ_DATA127_WIDTH 8 /* WSEQ_DATA127 - [7:0] */
+
+/*
+ * R12798 (0x31FE) - Write Sequencer 510
+ */
+#define WM8994_WSEQ_DATA_WIDTH127_MASK 0x0700 /* WSEQ_DATA_WIDTH127 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH127_SHIFT 8 /* WSEQ_DATA_WIDTH127 - [10:8] */
+#define WM8994_WSEQ_DATA_WIDTH127_WIDTH 3 /* WSEQ_DATA_WIDTH127 - [10:8] */
+#define WM8994_WSEQ_DATA_START127_MASK 0x000F /* WSEQ_DATA_START127 - [3:0] */
+#define WM8994_WSEQ_DATA_START127_SHIFT 0 /* WSEQ_DATA_START127 - [3:0] */
+#define WM8994_WSEQ_DATA_START127_WIDTH 4 /* WSEQ_DATA_START127 - [3:0] */
+
+/*
+ * R12799 (0x31FF) - Write Sequencer 511
+ */
+#define WM8994_WSEQ_EOS127 0x0100 /* WSEQ_EOS127 */
+#define WM8994_WSEQ_EOS127_MASK 0x0100 /* WSEQ_EOS127 */
+#define WM8994_WSEQ_EOS127_SHIFT 8 /* WSEQ_EOS127 */
+#define WM8994_WSEQ_EOS127_WIDTH 1 /* WSEQ_EOS127 */
+#define WM8994_WSEQ_DELAY127_MASK 0x000F /* WSEQ_DELAY127 - [3:0] */
+#define WM8994_WSEQ_DELAY127_SHIFT 0 /* WSEQ_DELAY127 - [3:0] */
+#define WM8994_WSEQ_DELAY127_WIDTH 4 /* WSEQ_DELAY127 - [3:0] */
+
diff --git a/sound/soc/codecs/wm8994_herring.c b/sound/soc/codecs/wm8994_herring.c
new file mode 100755
index 0000000..28e2320
--- /dev/null
+++ b/sound/soc/codecs/wm8994_herring.c
@@ -0,0 +1,3988 @@
+/*
+ * wm8994_crespo.c -- WM8994 ALSA Soc Audio driver related Aries
+ *
+ * Copyright (C) 2010 Samsung Electronics.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <plat/gpio-cfg.h>
+#include <plat/map-base.h>
+#include <mach/regs-clock.h>
+#include "wm8994_samsung.h"
+#include "../../../arch/arm/mach-s5pv210/herring.h"
+#ifdef CONFIG_SND_VOODOO
+#include "wm8994_voodoo.h"
+#endif
+
+/*
+ * Debug Feature
+ */
+#define SUBJECT "wm8994_crespo.c"
+
+/*
+ * Definitions of tunning volumes for wm8994
+ */
+
+struct gain_info_t cdma_playback_gain_table[PLAYBACK_GAIN_NUM] = {
+ { /* COMMON */
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_LEFT_VOLUME, /* 610h */
+ .mask = WM8994_DAC1L_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_RIGHT_VOLUME, /* 611h */
+ .mask = WM8994_DAC1R_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_LEFT_VOLUME, /* 402h */
+ .mask = WM8994_AIF1DAC1L_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_RIGHT_VOLUME, /* 403h */
+ .mask = WM8994_AIF1DAC1R_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0
+ }, { /* RCV */
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_OUTPUT_MIXER_5, /* 31h */
+ .mask = WM8994_DACL_MIXOUTL_VOL_MASK,
+ .gain = 0x0 << WM8994_DACL_MIXOUTL_VOL_SHIFT
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_OUTPUT_MIXER_6, /* 32h */
+ .mask = WM8994_DACR_MIXOUTR_VOL_MASK,
+ .gain = 0x0 << WM8994_DACR_MIXOUTR_VOL_SHIFT
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3D
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3D
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_HPOUT2_VOLUME, /* 1Fh */
+ .mask = WM8994_HPOUT2_VOL_MASK,
+ .gain = 0x0 << WM8994_HPOUT2_VOL_SHIFT
+ }, { /* SPK */
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPKMIXL_ATTENUATION, /* 22h */
+ .mask = WM8994_SPKMIXL_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPKMIXR_ATTENUATION, /* 23h */
+ .mask = WM8994_SPKMIXR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E /* +5dB */
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_RIGHT, /* 27h */
+ .mask = WM8994_SPKOUTR_VOL_MASK,
+ .gain = 0
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x05 << WM8994_SPKOUTL_BOOST_SHIFT /* +7.5dB */
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_AIF1_DAC1_LEFT_VOLUME, /* 402h */
+ .mask = WM8994_AIF1DAC1L_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xB8 /* -2.625dB */
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_AIF1_DAC1_RIGHT_VOLUME, /* 403h */
+ .mask = WM8994_AIF1DAC1R_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xB8 /* -2.625dB */
+ }, { /* HP */
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, { /* SPK_HP */
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPKMIXL_ATTENUATION, /* 22h */
+ .mask = WM8994_SPKMIXL_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPKMIXR_ATTENUATION, /* 23h */
+ .mask = WM8994_SPKMIXR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPEAKER_VOLUME_RIGHT, /* 27h */
+ .mask = WM8994_SPKOUTR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x5 << WM8994_SPKOUTL_BOOST_SHIFT
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, { /* RING_SPK */
+ .mode = PLAYBACK_RING_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E
+ }, {
+ .mode = PLAYBACK_RING_SPK,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x5 << WM8994_SPKOUTL_BOOST_SHIFT
+ }, { /* RING_HP */
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x34
+ }, {
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x34
+ }, {
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, { /* RING_SPK_HP */
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E
+ }, {
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x5 << WM8994_SPKOUTL_BOOST_SHIFT
+ }, {
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, {
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, { /* HP_NO_MIC */
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x36 /* -3dB */
+ }, {
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x36 /* -3dB */
+ }, {
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ },
+};
+
+struct gain_info_t cdma_voicecall_gain_table[VOICECALL_GAIN_NUM] = {
+ { /* COMMON */
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_LEFT_VOLUME, /* 610h */
+ .mask = WM8994_DAC1L_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_RIGHT_VOLUME, /* 611h */
+ .mask = WM8994_DAC1R_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_LEFT_VOLUME, /* 402h */
+ .mask = WM8994_AIF1DAC1L_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_RIGHT_VOLUME, /* 403h */
+ .mask = WM8994_AIF1DAC1R_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC2_LEFT_VOLUME, /* 612h */
+ .mask = WM8994_DAC2L_VOL_MASK,
+ .gain = WM8994_DAC2_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC2_RIGHT_VOLUME, /* 613h */
+ .mask = WM8994_DAC2R_VOL_MASK,
+ .gain = WM8994_DAC2_VU | 0xC0 /* 0dB */
+ }, { /* RCV */
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x0C /* +15dB */
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* +30dB */
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_OUTPUT_MIXER_5, /* 31h */
+ .mask = WM8994_DACL_MIXOUTL_VOL_MASK,
+ .gain = 0x0 << WM8994_DACL_MIXOUTL_VOL_SHIFT
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_OUTPUT_MIXER_6, /* 32h */
+ .mask = WM8994_DACR_MIXOUTR_VOL_MASK,
+ .gain = 0x0 << WM8994_DACR_MIXOUTR_VOL_SHIFT
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3F
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3F
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_HPOUT2_VOLUME, /* 1Fh */
+ .mask = WM8994_HPOUT2_VOL_MASK,
+ .gain = 0x0 << WM8994_HPOUT2_VOL_SHIFT
+ }, { /* SPK */
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* Mic +7.5dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x12 /* Mic +30dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPKMIXL_ATTENUATION, /* 22h */
+ .mask = WM8994_SPKMIXL_VOL_MASK,
+ .gain = 0x0 /* Speaker +0dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPKMIXR_ATTENUATION, /* 23h */
+ .mask = WM8994_SPKMIXR_VOL_MASK,
+ .gain = 0x0 /* Speaker +0dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3F /* Left Speaker +3dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_RIGHT, /* 27h */
+ .mask = WM8994_SPKOUTR_VOL_MASK, /* Right Speaker -57dB */
+ .gain = 0x0
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x7 << WM8994_SPKOUTL_BOOST_SHIFT /* Left spaker +12dB */
+ }, { /* HP */
+ .mode = VOICECALL_HP,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x1D
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, { /* HP_NO_MIC */
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x12 /* +10.5dB */
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, { /* TTY_VCO */
+ .mode = VOICECALL_TTY_VCO,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x15 /* +10.5dB */
+ }, {
+ .mode = VOICECALL_TTY_VCO,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x0
+ }, { /* TTY_HCO */
+ .mode = VOICECALL_TTY_HCO,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x13 /* +12dB */
+ }, {
+ .mode = VOICECALL_TTY_HCO,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x0
+ }, { /* TTY_FULL */
+ .mode = VOICECALL_TTY_FULL,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x13 /* +12dB */
+ }, {
+ .mode = VOICECALL_TTY_FULL,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x0
+ },
+};
+
+struct gain_info_t playback_gain_table[PLAYBACK_GAIN_NUM] = {
+ { /* COMMON */
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_LEFT_VOLUME, /* 610h */
+ .mask = WM8994_DAC1L_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_RIGHT_VOLUME, /* 611h */
+ .mask = WM8994_DAC1R_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_LEFT_VOLUME, /* 402h */
+ .mask = WM8994_AIF1DAC1L_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_RIGHT_VOLUME, /* 403h */
+ .mask = WM8994_AIF1DAC1R_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0
+ }, { /* RCV */
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_OUTPUT_MIXER_5, /* 31h */
+ .mask = WM8994_DACL_MIXOUTL_VOL_MASK,
+ .gain = 0x0 << WM8994_DACL_MIXOUTL_VOL_SHIFT
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_OUTPUT_MIXER_6, /* 32h */
+ .mask = WM8994_DACR_MIXOUTR_VOL_MASK,
+ .gain = 0x0 << WM8994_DACR_MIXOUTR_VOL_SHIFT
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3D
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3D
+ }, {
+ .mode = PLAYBACK_RCV,
+ .reg = WM8994_HPOUT2_VOLUME, /* 1Fh */
+ .mask = WM8994_HPOUT2_VOL_MASK,
+ .gain = 0x0 << WM8994_HPOUT2_VOL_SHIFT
+ }, { /* SPK */
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPKMIXL_ATTENUATION, /* 22h */
+ .mask = WM8994_SPKMIXL_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPKMIXR_ATTENUATION, /* 23h */
+ .mask = WM8994_SPKMIXR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E /* +5dB */
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_RIGHT, /* 27h */
+ .mask = WM8994_SPKOUTR_VOL_MASK,
+ .gain = 0
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x05 << WM8994_SPKOUTL_BOOST_SHIFT /* +7.5dB */
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_AIF1_DAC1_LEFT_VOLUME, /* 402h */
+ .mask = WM8994_AIF1DAC1L_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xB8 /* -2.625dB */
+ }, {
+ .mode = PLAYBACK_SPK,
+ .reg = WM8994_AIF1_DAC1_RIGHT_VOLUME, /* 403h */
+ .mask = WM8994_AIF1DAC1R_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xB8 /* -2.625dB */
+ }, { /* HP */
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, { /* SPK_HP */
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPKMIXL_ATTENUATION, /* 22h */
+ .mask = WM8994_SPKMIXL_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPKMIXR_ATTENUATION, /* 23h */
+ .mask = WM8994_SPKMIXR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_SPEAKER_VOLUME_RIGHT, /* 27h */
+ .mask = WM8994_SPKOUTR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x5 << WM8994_SPKOUTL_BOOST_SHIFT
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_SPK_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, { /* RING_SPK */
+ .mode = PLAYBACK_RING_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E
+ }, {
+ .mode = PLAYBACK_RING_SPK,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x5 << WM8994_SPKOUTL_BOOST_SHIFT
+ }, { /* RING_HP */
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x34
+ }, {
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x34
+ }, {
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_RING_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, { /* RING_SPK_HP */
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3E
+ }, {
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x5 << WM8994_SPKOUTL_BOOST_SHIFT
+ }, {
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, {
+ .mode = PLAYBACK_RING_SPK_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x1E
+ }, { /* HP_NO_MIC */
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x36 /* -3dB */
+ }, {
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x36 /* -3dB */
+ }, {
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = PLAYBACK_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ },
+};
+
+struct gain_info_t voicecall_gain_table[VOICECALL_GAIN_NUM] = {
+ { /* COMMON */
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_LEFT_VOLUME, /* 610h */
+ .mask = WM8994_DAC1L_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC1_RIGHT_VOLUME, /* 611h */
+ .mask = WM8994_DAC1R_VOL_MASK,
+ .gain = WM8994_DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_LEFT_VOLUME, /* 402h */
+ .mask = WM8994_AIF1DAC1L_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_AIF1_DAC1_RIGHT_VOLUME, /* 403h */
+ .mask = WM8994_AIF1DAC1R_VOL_MASK,
+ .gain = WM8994_AIF1DAC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC2_LEFT_VOLUME, /* 612h */
+ .mask = WM8994_DAC2L_VOL_MASK,
+ .gain = WM8994_DAC2_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = COMMON_SET_BIT,
+ .reg = WM8994_DAC2_RIGHT_VOLUME, /* 613h */
+ .mask = WM8994_DAC2R_VOL_MASK,
+ .gain = WM8994_DAC2_VU | 0xC0 /* 0dB */
+ }, { /* RCV */
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x15 /* +15dB */
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* +30dB */
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_OUTPUT_MIXER_5, /* 31h */
+ .mask = WM8994_DACL_MIXOUTL_VOL_MASK,
+ .gain = 0x0 << WM8994_DACL_MIXOUTL_VOL_SHIFT
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_OUTPUT_MIXER_6, /* 32h */
+ .mask = WM8994_DACR_MIXOUTR_VOL_MASK,
+ .gain = 0x0 << WM8994_DACR_MIXOUTR_VOL_SHIFT
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3F
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x3F
+ }, {
+ .mode = VOICECALL_RCV,
+ .reg = WM8994_HPOUT2_VOLUME, /* 1Fh */
+ .mask = WM8994_HPOUT2_VOL_MASK,
+ .gain = 0x0 << WM8994_HPOUT2_VOL_SHIFT
+ }, { /* SPK */
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* Mic +7.5dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x12 /* Mic +30dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPKMIXL_ATTENUATION, /* 22h */
+ .mask = WM8994_SPKMIXL_VOL_MASK,
+ .gain = 0x0 /* Speaker +0dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPKMIXR_ATTENUATION, /* 23h */
+ .mask = WM8994_SPKMIXR_VOL_MASK,
+ .gain = 0x0 /* Speaker +0dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3C /* Left Speaker +3dB */
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_SPEAKER_VOLUME_RIGHT, /* 27h */
+ .mask = WM8994_SPKOUTR_VOL_MASK, /* Right Speaker -57dB */
+ .gain = 0x0
+ }, {
+ .mode = VOICECALL_SPK,
+ .reg = WM8994_CLASSD, /* 25h */
+ .mask = WM8994_SPKOUTL_BOOST_MASK,
+ .gain = 0x7 << WM8994_SPKOUTL_BOOST_SHIFT /* Left spaker +12dB */
+ }, { /* HP */
+ .mode = VOICECALL_HP,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x1D
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x0
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, {
+ .mode = VOICECALL_HP,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, { /* HP_NO_MIC */
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x12 /* +10.5dB */
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_LEFT_OPGA_VOLUME, /* 20h */
+ .mask = WM8994_MIXOUTL_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OPGA_VOLUME, /* 21h */
+ .mask = WM8994_MIXOUTR_VOL_MASK,
+ .gain = WM8994_MIXOUT_VU | 0x39
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, {
+ .mode = VOICECALL_HP_NO_MIC,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x30
+ }, { /* TTY_VCO */
+ .mode = VOICECALL_TTY_VCO,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x15 /* +10.5dB */
+ }, {
+ .mode = VOICECALL_TTY_VCO,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x0
+ }, { /* TTY_HCO */
+ .mode = VOICECALL_TTY_HCO,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x13 /* +12dB */
+ }, {
+ .mode = VOICECALL_TTY_HCO,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x0
+ }, { /* TTY_FULL */
+ .mode = VOICECALL_TTY_FULL,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x13 /* +12dB */
+ }, {
+ .mode = VOICECALL_TTY_FULL,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x0
+ },
+};
+
+struct gain_info_t recording_gain_table[RECORDING_GAIN_NUM] = {
+ { /* MAIN */
+ .mode = RECORDING_MAIN,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x12 /* +10.5dB */
+ }, {
+ .mode = RECORDING_MAIN,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* +30dB */
+ }, {
+ .mode = RECORDING_MAIN,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = RECORDING_MAIN,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0 /* 0dB */
+ }, { /* HP */
+ .mode = RECORDING_HP,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x15
+ }, {
+ .mode = RECORDING_HP,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x10
+ }, {
+ .mode = RECORDING_HP,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }, {
+ .mode = RECORDING_HP,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }, { /* RECOGNITION_MAIN */
+ .mode = RECORDING_REC_MAIN,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x0D /* +3dB */
+ }, {
+ .mode = RECORDING_REC_MAIN,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* 30dB */
+ }, {
+ .mode = RECORDING_REC_MAIN,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xc0 /* +0dB */
+ }, {
+ .mode = RECORDING_REC_MAIN,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xc0 /* +0dB */
+ }, { /* RECOGNITION_HP */
+ .mode = RECORDING_REC_HP,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x12 /* +10.5dB */
+ }, {
+ .mode = RECORDING_REC_HP,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x10 /* +30dB */
+ }, {
+ .mode = RECORDING_REC_HP,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }, {
+ .mode = RECORDING_REC_HP,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }, { /* CAMCORDER_MAIN */
+ .mode = RECORDING_CAM_MAIN,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x17 /* +18dB */
+ }, {
+ .mode = RECORDING_CAM_MAIN,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* 30dB */
+ }, {
+ .mode = RECORDING_CAM_MAIN,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0 /* +0dB */
+ }, {
+ .mode = RECORDING_CAM_MAIN,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0 /* +0dB */
+ }, { /* CAMCORDER_HP */
+ .mode = RECORDING_CAM_HP,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x15 /* +15dB */
+ }, {
+ .mode = RECORDING_CAM_HP,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x10 /* +30dB */
+ }, {
+ .mode = RECORDING_CAM_HP,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }, {
+ .mode = RECORDING_CAM_HP,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }, { /* VOICE COMMUNICATION MAIN */
+ .mode = RECORDING_VC_MAIN,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x12 /* +10.5dB */
+ }, {
+ .mode = RECORDING_VC_MAIN,
+ .reg = WM8994_INPUT_MIXER_3, /* 29h */
+ .mask = WM8994_IN1L_MIXINL_VOL_MASK | WM8994_MIXOUTL_MIXINL_VOL_MASK,
+ .gain = 0x10 /* +30dB */
+ }, {
+ .mode = RECORDING_VC_MAIN,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0 /* 0dB */
+ }, {
+ .mode = RECORDING_VC_MAIN,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0 /* 0dB */
+ }, { /* VOICE COMMUNICATION HP */
+ .mode = RECORDING_VC_HP,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x15
+ }, {
+ .mode = RECORDING_VC_HP,
+ .reg = WM8994_INPUT_MIXER_4, /* 2Ah */
+ .mask = WM8994_IN1R_MIXINR_VOL_MASK | WM8994_MIXOUTR_MIXINR_VOL_MASK,
+ .gain = 0x10
+ }, {
+ .mode = RECORDING_VC_HP,
+ .reg = WM8994_AIF1_ADC1_LEFT_VOLUME, /* 400h */
+ .mask = WM8994_AIF1ADC1L_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }, {
+ .mode = RECORDING_VC_HP,
+ .reg = WM8994_AIF1_ADC1_RIGHT_VOLUME, /* 401h */
+ .mask = WM8994_AIF1ADC1R_VOL_MASK,
+ .gain = WM8994_AIF1ADC1_VU | 0xC0
+ }
+};
+
+struct gain_info_t gain_code_table[GAIN_CODE_NUM] = {
+ /* Playback */
+ {/* HP */
+ .mode = PLAYBACK_HP | PLAYBACK_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {
+ .mode = PLAYBACK_HP | PLAYBACK_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {/* HP_NO_MIC */
+ .mode = PLAYBACK_HP_NO_MIC | PLAYBACK_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {
+ .mode = PLAYBACK_HP_NO_MIC | PLAYBACK_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x31 /* -8dB */
+ }, {/* Voicecall RCV */
+ .mode = VOICECALL_RCV | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x14 /* +13.5dB */
+ }, {/* SPK */
+ .mode = VOICECALL_SPK | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x0D /* +3dB */
+ }, {
+ .mode = VOICECALL_SPK | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_SPEAKER_VOLUME_LEFT, /* 26h */
+ .mask = WM8994_SPKOUTL_VOL_MASK,
+ .gain = WM8994_SPKOUT_VU | 0x3A /* +1dB */
+ }, {/* HP */
+ .mode = VOICECALL_HP | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, /* 1Ah */
+ .mask = WM8994_IN1R_VOL_MASK,
+ .gain = WM8994_IN1R_VU | 0x1D /* +27dB */
+ }, {
+ .mode = VOICECALL_HP | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x3a /* +1dB */
+ }, {
+ .mode = VOICECALL_HP | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x3a /* +1dB */
+ }, {/* HP_NO_MIC */
+ .mode = VOICECALL_HP_NO_MIC | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_LEFT_LINE_INPUT_1_2_VOLUME, /* 18h */
+ .mask = WM8994_IN1L_VOL_MASK,
+ .gain = WM8994_IN1L_VU | 0x12 /* +10.5dB */
+ }, {
+ .mode = VOICECALL_HP_NO_MIC | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_LEFT_OUTPUT_VOLUME, /* 1Ch */
+ .mask = WM8994_HPOUT1L_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x3a /* +1dB */
+ }, {
+ .mode = VOICECALL_HP_NO_MIC | VOICECALL_MODE | GAIN_DIVISION_BIT_1,
+ .reg = WM8994_RIGHT_OUTPUT_VOLUME, /* 1Dh */
+ .mask = WM8994_HPOUT1R_VOL_MASK,
+ .gain = WM8994_HPOUT1_VU | 0x3a /* +1dB */
+ },
+};
+
+static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
+{
+ unsigned int reg;
+ int count = 0;
+ unsigned int val, start;
+
+ val = op | WM8994_DCS_ENA_CHAN_0 | WM8994_DCS_ENA_CHAN_1;
+
+ /* Trigger the command */
+ snd_soc_write(codec, WM8994_DC_SERVO_1, val);
+
+ start = jiffies;
+ pr_debug("Waiting for DC servo...\n");
+
+ do {
+ count++;
+ msleep(1);
+ reg = snd_soc_read(codec, WM8994_DC_SERVO_1);
+ pr_debug("DC servo: %x\n", reg);
+ } while (reg & op && count < 400);
+
+ pr_info("DC servo took %dms\n", jiffies_to_msecs(jiffies - start));
+
+ if (reg & op)
+ pr_err("Timed out waiting for DC Servo\n");
+}
+
+/* S5P_SLEEP_CONFIG must be controlled by codec if codec use XUSBTI */
+int wm8994_configure_clock(struct snd_soc_codec *codec, int en)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ if (en) {
+ clk_enable(wm8994->codec_clk);
+ DEBUG_LOG("USBOSC Enabled in Sleep Mode\n");
+ } else {
+ clk_disable(wm8994->codec_clk);
+ DEBUG_LOG("USBOSC disable in Sleep Mode\n");
+ }
+
+ return 0;
+}
+
+void audio_ctrl_mic_bias_gpio(struct wm8994_platform_data *pdata, int enable)
+{
+ DEBUG_LOG("enable = [%d]", enable);
+
+ if (!pdata)
+ pr_err("failed to turn off micbias pin\n");
+ else {
+ if (enable)
+ pdata->set_mic_bias(true);
+ else
+ pdata->set_mic_bias(false);
+ }
+}
+
+static int wm8994_earsel_control(struct wm8994_platform_data *pdata, int en)
+{
+
+ if (!pdata) {
+ pr_err("failed to control wm8994 ear selection\n");
+ return -EINVAL;
+ }
+
+ gpio_set_value(pdata->ear_sel, en);
+
+ return 0;
+
+}
+
+/* Audio Routing routines for the universal board..wm8994 codec*/
+void wm8994_disable_path(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ u16 val;
+ enum audio_path path = wm8994->cur_path;
+
+ DEBUG_LOG("Path = [%d]", path);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+
+ switch (path) {
+ case RCV:
+ /* Disbale the HPOUT2 */
+ val &= ~(WM8994_HPOUT2_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ /* Disable left MIXOUT */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~(WM8994_DAC1L_TO_MIXOUTL_MASK);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val);
+
+ /* Disable right MIXOUT */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~(WM8994_DAC1R_TO_MIXOUTR_MASK);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val);
+
+ /* Disable HPOUT Mixer */
+ val = wm8994_read(codec, WM8994_HPOUT2_MIXER);
+ val &= ~(WM8994_MIXOUTLVOL_TO_HPOUT2_MASK |
+ WM8994_MIXOUTRVOL_TO_HPOUT2_MASK);
+ wm8994_write(codec, WM8994_HPOUT2_MIXER, val);
+
+ /* Disable mixout volume control */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_3);
+ val &= ~(WM8994_MIXOUTLVOL_ENA_MASK |
+ WM8994_MIXOUTRVOL_ENA_MASK |
+ WM8994_MIXOUTL_ENA_MASK |
+ WM8994_MIXOUTR_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, val);
+ break;
+
+ case SPK:
+ /* Disbale the SPKOUTL */
+ val &= ~(WM8994_SPKOUTL_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ /* Disable SPKLVOL */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_3);
+ val &= ~(WM8994_SPKLVOL_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, val);
+
+ /* Disable SPKOUT mixer */
+ val = wm8994_read(codec, WM8994_SPKOUT_MIXERS);
+ val &= ~(WM8994_SPKMIXL_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTR_MASK);
+ wm8994_write(codec, WM8994_SPKOUT_MIXERS, val);
+
+ /* Mute Speaker mixer */
+ val = wm8994_read(codec, WM8994_SPEAKER_MIXER);
+ val &= ~(WM8994_DAC1L_TO_SPKMIXL_MASK);
+ wm8994_write(codec, WM8994_SPEAKER_MIXER, val);
+ break;
+
+ case HP:
+ case HP_NO_MIC:
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(0x02C0);
+ val |= 0x02C0;
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, 0x02C0);
+
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(0x02C0);
+ val |= 0x02C0;
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, 0x02C0);
+
+ val = wm8994_read(codec, WM8994_ANALOGUE_HP_1);
+ val &= ~(0x0022);
+ val |= 0x0022;
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x0022);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~(0x0);
+ val |= 0x0;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, 0x0);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~(0x0);
+ val |= 0x0;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, 0x0);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(0x0300);
+ val |= 0x0300;
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, 0x0300);
+
+ val = wm8994_read(codec, WM8994_CHARGE_PUMP_1);
+ val &= ~(0x1F25);
+ val |= 0x1F25;
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, 0x1F25);
+ break;
+
+ case BT:
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK | WM8994_AIF1DAC1_MONO_MASK);
+ val |= (WM8994_AIF1DAC1_MUTE);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+ break;
+
+ case SPK_HP:
+ val &= ~(WM8994_HPOUT1L_ENA_MASK | WM8994_HPOUT1R_ENA_MASK |
+ WM8994_SPKOUTL_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ /* Disable DAC1L to HPOUT1L path */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~(WM8994_DAC1L_TO_HPOUT1L_MASK |
+ WM8994_DAC1L_TO_MIXOUTL_MASK);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val);
+
+ /* Disable DAC1R to HPOUT1R path */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~(WM8994_DAC1R_TO_HPOUT1R_MASK |
+ WM8994_DAC1R_TO_MIXOUTR_MASK);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val);
+
+ /* Disable Charge Pump */
+ val = wm8994_read(codec, WM8994_CHARGE_PUMP_1);
+ val &= ~WM8994_CP_ENA_MASK;
+ val |= WM8994_CP_ENA_DEFAULT;
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, val);
+
+ /* Intermediate HP settings */
+ val = wm8994_read(codec, WM8994_ANALOGUE_HP_1);
+ val &= ~(WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1R_OUTP_MASK |
+ WM8994_HPOUT1R_RMV_SHORT_MASK | WM8994_HPOUT1L_DLY_MASK |
+ WM8994_HPOUT1L_OUTP_MASK | WM8994_HPOUT1L_RMV_SHORT_MASK);
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, val);
+
+ /* Disable SPKLVOL */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_3);
+ val &= ~(WM8994_SPKLVOL_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, val);
+
+ /* Disable SPKOUT mixer */
+ val = wm8994_read(codec, WM8994_SPKOUT_MIXERS);
+ val &= ~(WM8994_SPKMIXL_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTR_MASK);
+ wm8994_write(codec, WM8994_SPKOUT_MIXERS, val);
+
+ /* Mute Speaker mixer */
+ val = wm8994_read(codec, WM8994_SPEAKER_MIXER);
+ val &= ~(WM8994_DAC1L_TO_SPKMIXL_MASK);
+ wm8994_write(codec, WM8994_SPEAKER_MIXER, val);
+ break;
+
+ default:
+ DEBUG_LOG_ERR("Path[%d] is not invaild!\n", path);
+ return;
+ break;
+ }
+}
+
+void wm8994_disable_rec_path(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ u16 val;
+ enum mic_path mic = wm8994->rec_path;
+
+ wm8994->rec_path = MIC_OFF;
+
+ if (!(wm8994->codec_state & CALL_ACTIVE))
+ audio_ctrl_mic_bias_gpio(wm8994->pdata, 0);
+
+ switch (mic) {
+ case MAIN:
+ DEBUG_LOG("Disabling MAIN Mic Path..\n");
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_2);
+ val &= ~(WM8994_IN1L_ENA_MASK | WM8994_MIXINL_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, val);
+
+ /* Mute IN1L PGA, update volume */
+ val = wm8994_read(codec,
+ WM8994_LEFT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1L_MUTE_MASK | WM8994_IN1L_VOL_MASK);
+ val |= (WM8994_IN1L_VU | WM8994_IN1L_MUTE);
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME,
+ val);
+
+ /*Mute the PGA */
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_3);
+ val &= ~(WM8994_IN1L_TO_MIXINL_MASK |
+ WM8994_IN1L_MIXINL_VOL_MASK |
+ WM8994_MIXOUTL_MIXINL_VOL_MASK);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, val);
+
+ /* Disconnect IN1LN ans IN1LP to the inputs */
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_2);
+ val &= (WM8994_IN1LN_TO_IN1L_MASK | WM8994_IN1LP_TO_IN1L_MASK);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, val);
+
+ /* Digital Paths */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_4);
+ val &= ~(WM8994_ADCL_ENA_MASK | WM8994_AIF1ADC1L_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4, val);
+
+ /* Disable timeslots */
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1L_TO_AIF1ADC1L);
+ wm8994_write(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, val);
+ break;
+
+ case SUB:
+ DEBUG_LOG("Disbaling SUB Mic path..\n");
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_2);
+ val &= ~(WM8994_IN1R_ENA_MASK | WM8994_MIXINR_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, val);
+
+ /* Disable volume,unmute Right Line */
+ val = wm8994_read(codec,
+ WM8994_RIGHT_LINE_INPUT_1_2_VOLUME);
+ val &= ~WM8994_IN1R_MUTE_MASK; /* Unmute IN1R */
+ val |= (WM8994_IN1R_VU | WM8994_IN1R_MUTE);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME,
+ val);
+
+ /* Mute right pga, set volume */
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_4);
+ val &= ~(WM8994_IN1R_TO_MIXINR_MASK |
+ WM8994_IN1R_MIXINR_VOL_MASK |
+ WM8994_MIXOUTR_MIXINR_VOL_MASK);
+ wm8994_write(codec, WM8994_INPUT_MIXER_4, val);
+
+ /* Disconnect in1rn to inr1 and in1rp to inrp */
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_2);
+ val &= ~(WM8994_IN1RN_TO_IN1R_MASK | WM8994_IN1RP_TO_IN1R_MASK);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, val);
+
+ /* Digital Paths */
+ /* Disable right ADC and time slot */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_4);
+ val &= ~(WM8994_ADCR_ENA_MASK | WM8994_AIF1ADC1R_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4, val);
+
+ /* ADC Right mixer routing */
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1R_TO_AIF1ADC1R_MASK);
+ wm8994_write(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, val);
+ break;
+
+ case BT_REC:
+ DEBUG_LOG("Disbaling BT Mic path..\n");
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF2DACL_TO_AIF1ADC1L_MASK |
+ WM8994_ADC1L_TO_AIF1ADC1L_MASK);
+ wm8994_write(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF2DACR_TO_AIF1ADC1R_MASK |
+ WM8994_ADC1R_TO_AIF1ADC1R_MASK);
+ wm8994_write(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_AIF2_DAC_FILTERS_1);
+ val &= ~(WM8994_AIF2DAC_MUTE_MASK);
+ val |= (WM8994_AIF2DAC_MUTE);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, val);
+ break;
+
+ case MIC_OFF:
+ DEBUG_LOG("Mic is already OFF!\n");
+ break;
+
+ default:
+ DEBUG_LOG_ERR("Path[%d] is not invaild!\n", mic);
+ break;
+ }
+}
+
+void wm8994_set_bluetooth_common_setting(struct snd_soc_codec *codec)
+{
+ u32 val;
+
+ wm8994_write(codec, WM8994_GPIO_1, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_2, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_3, 0x0100);
+ wm8994_write(codec, WM8994_GPIO_4, 0x0100);
+ wm8994_write(codec, WM8994_GPIO_5, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_6, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_7, 0x0100);
+ wm8994_write(codec, WM8994_GPIO_8, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_9, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_10, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_11, 0xA101);
+
+ wm8994_write(codec, WM8994_FLL2_CONTROL_2, 0x0700);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_3, 0x3126);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_1,
+ WM8994_FLL2_FRACN_ENA | WM8994_FLL2_ENA);
+
+ val = wm8994_read(codec, WM8994_AIF2_CLOCKING_1);
+ if (!(val & WM8994_AIF2CLK_ENA))
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0018);
+
+ wm8994_write(codec, WM8994_AIF2_RATE, 0x9 << WM8994_AIF2CLK_RATE_SHIFT);
+
+ /* AIF2 Interface - PCM Stereo mode */
+ /* Left Justified, BCLK invert, LRCLK Invert */
+ wm8994_write(codec, WM8994_AIF2_CONTROL_1,
+ WM8994_AIF2ADCR_SRC | WM8994_AIF2_BCLK_INV | 0x18);
+
+ wm8994_write(codec, WM8994_AIF2_BCLK, 0x70);
+ wm8994_write(codec, WM8994_AIF2_CONTROL_2, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_MASTER_SLAVE, WM8994_AIF2_MSTR |
+ WM8994_AIF2_CLK_FRC | WM8994_AIF2_LRCLK_FRC);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
+ WM8994_AIF1DAC1L_ENA_MASK | WM8994_AIF1DAC1R_ENA_MASK |
+ WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK);
+ val |= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
+ WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ /* Clocking */
+ val = wm8994_read(codec, WM8994_CLOCKING_1);
+ val |= (WM8994_DSP_FS2CLK_ENA | WM8994_SYSCLK_SRC);
+ wm8994_write(codec, WM8994_CLOCKING_1, val);
+
+ /* AIF1 & AIF2 Output is connected to DAC1 */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC1L_MASK |
+ WM8994_AIF2DACL_TO_DAC1L_MASK);
+ val |= (WM8994_AIF1DAC1L_TO_DAC1L | WM8994_AIF2DACL_TO_DAC1L);
+ wm8994_write(codec, WM8994_DAC1_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1R_TO_DAC1R_MASK |
+ WM8994_AIF2DACR_TO_DAC1R_MASK);
+ val |= (WM8994_AIF1DAC1R_TO_DAC1R | WM8994_AIF2DACR_TO_DAC1R);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING, val);
+}
+
+void wm8994_record_headset_mic(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ u16 val;
+
+ DEBUG_LOG("Recording through Headset Mic\n");
+
+ wm8994_write(codec, WM8994_ANTIPOP_2, 0x68);
+
+ /* Enable high pass filter to control bounce on startup */
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_FILTERS);
+ val &= ~(WM8994_AIF1ADC1L_HPF_MASK | WM8994_AIF1ADC1R_HPF_MASK);
+ val |= (WM8994_AIF1ADC1R_HPF);
+ wm8994_write(codec, WM8994_AIF1_ADC1_FILTERS, val);
+
+ /* Enable mic bias, vmid, bias generator */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_1);
+ val &= ~(WM8994_INPUTS_CLAMP_MASK);
+ val |= (WM8994_INPUTS_CLAMP);
+ wm8994_write(codec, WM8994_INPUT_MIXER_1, val);
+
+ val = (WM8994_MIXINR_ENA | WM8994_IN1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, val);
+
+
+ val = (WM8994_IN1RN_TO_IN1R | WM8994_IN1RP_TO_IN1R);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_4);
+ val &= ~(WM8994_IN1R_TO_MIXINR_MASK);
+ val |= (WM8994_IN1R_TO_MIXINR);
+ wm8994_write(codec, WM8994_INPUT_MIXER_4 , val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_1);
+ val &= ~(WM8994_INPUTS_CLAMP_MASK);
+ wm8994_write(codec, WM8994_INPUT_MIXER_1, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME);
+ val |= (WM8994_AIF1ADC1_VU);
+ wm8994_write(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_FILTERS);
+ val &= ~(WM8994_AIF1ADC1L_HPF_MASK | WM8994_AIF1ADC1R_HPF_MASK);
+ val |= (WM8994_AIF1ADC1R_HPF | 0x2000);
+ wm8994_write(codec, WM8994_AIF1_ADC1_FILTERS, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_MASTER_SLAVE);
+ val |= (WM8994_AIF1_MSTR | WM8994_AIF1_CLK_FRC | WM8994_AIF1_LRCLK_FRC);
+ wm8994_write(codec, WM8994_AIF1_MASTER_SLAVE, val);
+
+ wm8994_write(codec, WM8994_GPIO_1, 0xA101);
+
+ /* Mixing left channel output to right channel */
+ val = wm8994_read(codec, WM8994_AIF1_CONTROL_1);
+ val &= ~(WM8994_AIF1ADCL_SRC_MASK | WM8994_AIF1ADCR_SRC_MASK);
+ val |= (WM8994_AIF1ADCL_SRC | WM8994_AIF1ADCR_SRC);
+ wm8994_write(codec, WM8994_AIF1_CONTROL_1, val);
+
+ /* Digital Paths */
+ /* Enable right ADC and time slot */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_4);
+ val &= ~(WM8994_ADCR_ENA_MASK | WM8994_AIF1ADC1R_ENA_MASK);
+ val |= (WM8994_AIF1ADC1R_ENA | WM8994_ADCR_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4, val);
+
+
+ /* ADC Right mixer routing */
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1R_TO_AIF1ADC1R_MASK);
+ val |= WM8994_ADC1R_TO_AIF1ADC1R;
+ wm8994_write(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_SPEAKER_MIXER);
+ val &= ~WM8994_MIXINL_TO_SPKMIXL_MASK;
+ wm8994_write(codec, WM8994_SPEAKER_MIXER, val);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~WM8994_MIXINL_TO_MIXOUTL_MASK;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~WM8994_MIXINR_TO_MIXOUTR_MASK;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val);
+
+ val = wm8994_read(codec, WM8994_DAC2_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1_TO_DAC2L_MASK);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1_TO_DAC2R_MASK);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING, val);
+
+ if (wm8994->input_source == RECOGNITION)
+ wm8994_set_codec_gain(codec, RECORDING_MODE, RECORDING_REC_HP);
+ else if (wm8994->input_source == CAMCORDER)
+ wm8994_set_codec_gain(codec, RECORDING_MODE, RECORDING_CAM_HP);
+ else if (wm8994->input_source == VOICE_COMMUNICATION)
+ wm8994_set_codec_gain(codec, RECORDING_MODE, RECORDING_VC_HP);
+ else
+ wm8994_set_codec_gain(codec, RECORDING_MODE, RECORDING_HP);
+
+}
+
+void wm8994_record_main_mic(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ u16 val;
+
+ DEBUG_LOG("Recording through Main Mic\n");
+ audio_ctrl_mic_bias_gpio(wm8994->pdata, 1);
+
+ /* Main mic volume issue fix: requested H/W */
+ wm8994_write(codec, WM8994_ANTIPOP_2, 0x68);
+
+ /* High pass filter to control bounce on enable */
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_FILTERS);
+ val &= ~(WM8994_AIF1ADC1L_HPF_MASK | WM8994_AIF1ADC1R_HPF_MASK);
+ val |= (WM8994_AIF1ADC1L_HPF);
+ wm8994_write(codec, WM8994_AIF1_ADC1_FILTERS, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_1);
+ val &= ~(WM8994_INPUTS_CLAMP_MASK);
+ val |= (WM8994_INPUTS_CLAMP);
+ wm8994_write(codec, WM8994_INPUT_MIXER_1, val);
+
+ val = (WM8994_MIXINL_ENA | WM8994_IN1L_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, val);
+
+ val = (WM8994_IN1LP_TO_IN1L | WM8994_IN1LN_TO_IN1L);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, val);
+
+
+ val = wm8994_read(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_3);
+ val &= ~(WM8994_IN1L_TO_MIXINL_MASK);
+ val |= (WM8994_IN1L_TO_MIXINL);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_1);
+ val &= ~(WM8994_INPUTS_CLAMP_MASK);
+ wm8994_write(codec, WM8994_INPUT_MIXER_1, val);
+
+
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_LEFT_VOLUME);
+ val |= (WM8994_AIF1ADC1_VU);
+ wm8994_write(codec, WM8994_AIF1_ADC1_LEFT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_FILTERS);
+ val &= ~(WM8994_AIF1ADC1L_HPF_MASK | WM8994_AIF1ADC1R_HPF_MASK);
+ val |= (WM8994_AIF1ADC1L_HPF | 0x2000);
+ wm8994_write(codec, WM8994_AIF1_ADC1_FILTERS, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_MASTER_SLAVE);
+ val |= (WM8994_AIF1_MSTR | WM8994_AIF1_CLK_FRC | WM8994_AIF1_LRCLK_FRC);
+ wm8994_write(codec, WM8994_AIF1_MASTER_SLAVE, val);
+
+ wm8994_write(codec, WM8994_GPIO_1, 0xA101);
+
+ val = wm8994_read(codec, WM8994_AIF1_CONTROL_1);
+ val &= ~(WM8994_AIF1ADCL_SRC_MASK | WM8994_AIF1ADCR_SRC_MASK);
+ val |= (WM8994_AIF1ADCR_SRC);
+ wm8994_write(codec, WM8994_AIF1_CONTROL_1, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_4);
+ val &= ~(WM8994_ADCL_ENA_MASK | WM8994_AIF1ADC1L_ENA_MASK);
+ val |= (WM8994_AIF1ADC1L_ENA | WM8994_ADCL_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4, val);
+
+ /* Enable timeslots */
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING);
+ val |= WM8994_ADC1L_TO_AIF1ADC1L;
+ wm8994_write(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_SPEAKER_MIXER);
+ val &= ~WM8994_MIXINL_TO_SPKMIXL_MASK;
+ wm8994_write(codec, WM8994_SPEAKER_MIXER, val);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~WM8994_MIXINL_TO_MIXOUTL_MASK;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~WM8994_MIXINR_TO_MIXOUTR_MASK;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val);
+
+ val = wm8994_read(codec, WM8994_DAC2_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1_TO_DAC2L_MASK);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1_TO_DAC2R_MASK);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING, val);
+
+ if (wm8994->input_source == RECOGNITION)
+ wm8994_set_codec_gain(codec, RECORDING_MODE,
+ RECORDING_REC_MAIN);
+ else if (wm8994->input_source == CAMCORDER)
+ wm8994_set_codec_gain(codec, RECORDING_MODE,
+ RECORDING_CAM_MAIN);
+ else if (wm8994->input_source == VOICE_COMMUNICATION)
+ wm8994_set_codec_gain(codec, RECORDING_MODE,
+ RECORDING_VC_MAIN);
+ else
+ wm8994_set_codec_gain(codec, RECORDING_MODE, RECORDING_MAIN);
+
+}
+
+void wm8994_record_bluetooth(struct snd_soc_codec *codec)
+{
+ u16 val;
+
+ DEBUG_LOG("BT Record Path for Voice Command\n");
+
+ wm8994_set_bluetooth_common_setting(codec);
+
+ val = wm8994_read(codec, WM8994_DAC2_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1_TO_DAC2L_MASK);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_ADC1_TO_DAC2R_MASK);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, 0x0000);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, 0x0000);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_4);
+ val &= ~(WM8994_AIF1ADC1L_ENA_MASK | WM8994_AIF1ADC1R_ENA_MASK);
+ val |= (WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4 , val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK);
+ val |= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_6);
+ val &= ~(WM8994_AIF3_ADCDAT_SRC_MASK | WM8994_AIF2_DACDAT_SRC_MASK);
+ val |= (0x1 << WM8994_AIF3_ADCDAT_SRC_SHIFT | WM8994_AIF2_DACDAT_SRC);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_6, val);
+
+ val = wm8994_read(codec, WM8994_AIF2_DAC_FILTERS_1);
+ val &= ~(WM8994_AIF2DAC_MUTE_MASK);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF2DACL_TO_AIF1ADC1L_MASK);
+ val |= (WM8994_AIF2DACL_TO_AIF1ADC1L);
+ wm8994_write(codec, WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF2DACR_TO_AIF1ADC1R_MASK);
+ val |= (WM8994_AIF2DACR_TO_AIF1ADC1R);
+ wm8994_write(codec, WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, val);
+
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ wm8994_write(codec, WM8994_OVERSAMPLING, 0X0000);
+
+ wm8994_write(codec, WM8994_GPIO_8, WM8994_GP8_DIR | WM8994_GP8_DB);
+ wm8994_write(codec, WM8994_GPIO_9, WM8994_GP9_DB);
+ wm8994_write(codec, WM8994_GPIO_10, WM8994_GP10_DB);
+ wm8994_write(codec, WM8994_GPIO_11, WM8994_GP11_DB);
+}
+void wm8994_set_playback_receiver(struct snd_soc_codec *codec)
+{
+ u16 val;
+
+ DEBUG_LOG("");
+
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_HPOUT2_VOLUME);
+ val &= ~(WM8994_HPOUT2_MUTE_MASK);
+ wm8994_write(codec, WM8994_HPOUT2_VOLUME, val);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~(WM8994_DAC1L_TO_MIXOUTL_MASK);
+ val |= (WM8994_DAC1L_TO_MIXOUTL);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val);
+
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~(WM8994_DAC1R_TO_MIXOUTR_MASK);
+ val |= (WM8994_DAC1R_TO_MIXOUTR);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val);
+
+ val = wm8994_read(codec, WM8994_HPOUT2_MIXER);
+ val &= ~(WM8994_MIXOUTLVOL_TO_HPOUT2_MASK |
+ WM8994_MIXOUTRVOL_TO_HPOUT2_MASK);
+ val |= (WM8994_MIXOUTRVOL_TO_HPOUT2 | WM8994_MIXOUTLVOL_TO_HPOUT2);
+ wm8994_write(codec, WM8994_HPOUT2_MIXER, val);
+
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE, PLAYBACK_RCV);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_DAC1R_ENA_MASK | WM8994_DAC1L_ENA_MASK |
+ WM8994_AIF1DAC1R_ENA_MASK | WM8994_AIF1DAC1L_ENA_MASK);
+ val |= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC1L_MASK);
+ val |= (WM8994_AIF1DAC1L_TO_DAC1L);
+ wm8994_write(codec, WM8994_DAC1_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1R_TO_DAC1R_MASK);
+ val |= (WM8994_AIF1DAC1R_TO_DAC1R);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_CLOCKING_1);
+ val &= ~(WM8994_DSP_FS1CLK_ENA_MASK | WM8994_DSP_FSINTCLK_ENA_MASK);
+ val |= (WM8994_DSP_FS1CLK_ENA | WM8994_DSP_FSINTCLK_ENA);
+ wm8994_write(codec, WM8994_CLOCKING_1, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_3);
+ val &= ~(WM8994_MIXOUTLVOL_ENA_MASK | WM8994_MIXOUTRVOL_ENA_MASK |
+ WM8994_MIXOUTL_ENA_MASK | WM8994_MIXOUTR_ENA_MASK);
+ val |= (WM8994_MIXOUTL_ENA | WM8994_MIXOUTR_ENA |
+ WM8994_MIXOUTRVOL_ENA | WM8994_MIXOUTLVOL_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK |
+ WM8994_HPOUT2_ENA_MASK | WM8994_HPOUT1L_ENA_MASK |
+ WM8994_HPOUT1R_ENA_MASK | WM8994_SPKOUTL_ENA_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL | WM8994_HPOUT2_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK | WM8994_AIF1DAC1_MONO_MASK);
+ val |= (WM8994_AIF1DAC1_UNMUTE | WM8994_AIF1DAC1_MONO);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+
+}
+
+void wm8994_set_playback_headset(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ u16 val;
+
+ u16 testreturn1 = 0;
+ u16 testreturn2 = 0;
+ u16 testlow1 = 0;
+ u16 testhigh1 = 0;
+ u8 testlow = 0;
+ u8 testhigh = 0;
+
+ DEBUG_LOG("");
+
+ wm8994_earsel_control(wm8994->pdata, 0);
+
+ /* Enable the Timeslot0 to DAC1L */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC1L_MASK);
+ val |= WM8994_AIF1DAC1L_TO_DAC1L;
+ wm8994_write(codec, WM8994_DAC1_LEFT_MIXER_ROUTING, val);
+
+ /* Enable the Timeslot0 to DAC1R */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1R_TO_DAC1R_MASK);
+ val |= WM8994_AIF1DAC1R_TO_DAC1R;
+ wm8994_write(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, 0x56);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x56, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0000);
+ val = 0x0000;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, WM8994_CLASS_W_1);
+ val &= ~(0x0005);
+ val |= 0x0005;
+ wm8994_write(codec, WM8994_CLASS_W_1, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1L_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1R_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1R_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ if (wm8994->ringtone_active)
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE, PLAYBACK_RING_HP);
+ else if (wm8994->cur_path == HP_NO_MIC)
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE, PLAYBACK_HP_NO_MIC);
+ else
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE, PLAYBACK_HP);
+
+ val = wm8994_read(codec, WM8994_DC_SERVO_2);
+ val &= ~(0x03E0);
+ val = 0x03E0;
+ wm8994_write(codec, WM8994_DC_SERVO_2, val);
+
+ /* Enable vmid,bias, hp left and right */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK |
+ WM8994_HPOUT1L_ENA_MASK | WM8994_HPOUT1R_ENA_MASK |
+ WM8994_SPKOUTR_ENA_MASK | WM8994_SPKOUTL_ENA_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL |
+ WM8994_HPOUT1R_ENA | WM8994_HPOUT1L_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ val = wm8994_read(codec, WM8994_ANALOGUE_HP_1);
+ val &= ~(0x0022);
+ val = 0x0022;
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, val);
+
+ /* Enable Charge Pump */
+ /* this is from wolfson */
+ val = wm8994_read(codec, WM8994_CHARGE_PUMP_1);
+ val &= ~WM8994_CP_ENA_MASK ;
+ val |= WM8994_CP_ENA | WM8994_CP_ENA_DEFAULT;
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, val);
+
+ msleep(5);
+
+ /* Enable Dac1 and DAC2 and the Timeslot0 for AIF1 */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_DAC1R_ENA_MASK | WM8994_DAC1L_ENA_MASK |
+ WM8994_AIF1DAC1R_ENA_MASK | WM8994_AIF1DAC1L_ENA_MASK);
+ val |= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ /* Enable DAC1L to HPOUT1L path */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~(WM8994_DAC1L_TO_HPOUT1L_MASK | WM8994_DAC1L_TO_MIXOUTL_MASK);
+ val |= WM8994_DAC1L_TO_MIXOUTL;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val);
+
+ /* Enable DAC1R to HPOUT1R path */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~(WM8994_DAC1R_TO_HPOUT1R_MASK | WM8994_DAC1R_TO_MIXOUTR_MASK);
+ val |= WM8994_DAC1R_TO_MIXOUTR;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_3);
+ val &= ~(WM8994_MIXOUTLVOL_ENA_MASK | WM8994_MIXOUTRVOL_ENA_MASK |
+ WM8994_MIXOUTL_ENA_MASK | WM8994_MIXOUTR_ENA_MASK |
+ WM8994_SPKRVOL_ENA_MASK | WM8994_SPKLVOL_ENA_MASK);
+ val |= (WM8994_MIXOUTLVOL_ENA | WM8994_MIXOUTRVOL_ENA |
+ WM8994_MIXOUTL_ENA | WM8994_MIXOUTR_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, 0x0030);
+
+ if (!wm8994->dc_servo[DCS_MEDIA]) {
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_SERIES_0 |
+ WM8994_DCS_TRIG_SERIES_1);
+
+ testreturn1 = wm8994_read(codec, WM8994_DC_SERVO_4);
+
+ testlow = (signed char)(testreturn1 & 0xff);
+ testhigh = (signed char)((testreturn1>>8) & 0xff);
+
+ testlow1 = ((signed short)(testlow-5)) & 0x00ff;
+ testhigh1 = (((signed short)(testhigh-5)<<8) & 0xff00);
+ testreturn2 = testlow1|testhigh1;
+ } else {
+ testreturn2 = wm8994->dc_servo[DCS_MEDIA];
+ }
+
+ wm8994_write(codec, WM8994_DC_SERVO_4, testreturn2);
+ wm8994->dc_servo[DCS_MEDIA] = testreturn2;
+
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_DAC_WR_0 | WM8994_DCS_TRIG_DAC_WR_1);
+
+ /* Intermediate HP settings */
+ val = wm8994_read(codec, WM8994_ANALOGUE_HP_1);
+ val &= ~(WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1R_OUTP_MASK |
+ WM8994_HPOUT1R_RMV_SHORT_MASK | WM8994_HPOUT1L_DLY_MASK |
+ WM8994_HPOUT1L_OUTP_MASK | WM8994_HPOUT1L_RMV_SHORT_MASK);
+ val = (WM8994_HPOUT1L_RMV_SHORT | WM8994_HPOUT1L_OUTP|
+ WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_RMV_SHORT |
+ WM8994_HPOUT1R_OUTP | WM8994_HPOUT1R_DLY);
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, val);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ /* Unmute the AF1DAC1 */
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK | WM8994_AIF1DAC1_MONO_MASK);
+ val |= WM8994_AIF1DAC1_UNMUTE;
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+
+}
+
+void wm8994_set_playback_speaker(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ u16 val;
+
+ DEBUG_LOG("");
+
+ /* Disable end point for preventing pop up noise.*/
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_SPKOUTL_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_3);
+ val &= ~(WM8994_MIXOUTLVOL_ENA_MASK | WM8994_MIXOUTRVOL_ENA_MASK |
+ WM8994_MIXOUTL_ENA_MASK | WM8994_MIXOUTR_ENA_MASK |
+ WM8994_SPKRVOL_ENA_MASK | WM8994_SPKLVOL_ENA_MASK);
+ val |= WM8994_SPKLVOL_ENA;
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, val);
+
+ /* Speaker Volume Control */
+ /* Unmute the SPKMIXVOLUME */
+ val = wm8994_read(codec, WM8994_SPEAKER_VOLUME_LEFT);
+ val &= ~(WM8994_SPKOUTL_MUTE_N_MASK);
+ val |= (WM8994_SPKOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_SPEAKER_VOLUME_LEFT, val);
+
+ val = wm8994_read(codec, WM8994_SPEAKER_VOLUME_RIGHT);
+ val &= ~(WM8994_SPKOUTR_MUTE_N_MASK);
+ wm8994_write(codec, WM8994_SPEAKER_VOLUME_RIGHT, val);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_SPKOUT_MIXERS);
+ val &= ~(WM8994_SPKMIXL_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTR_MASK);
+ val |= WM8994_SPKMIXL_TO_SPKOUTL;
+ wm8994_write(codec, WM8994_SPKOUT_MIXERS, val);
+
+ /* Unmute the DAC path */
+ val = wm8994_read(codec, WM8994_SPEAKER_MIXER);
+ val &= ~(WM8994_DAC1L_TO_SPKMIXL_MASK);
+ val |= WM8994_DAC1L_TO_SPKMIXL;
+ wm8994_write(codec, WM8994_SPEAKER_MIXER, val);
+
+ /* Eable DAC1 Left and timeslot left */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_DAC1L_ENA_MASK | WM8994_AIF1DAC1R_ENA_MASK |
+ WM8994_AIF1DAC1L_ENA_MASK);
+ val |= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA | WM8994_DAC1L_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ /* DRC setting */
+ wm8994_write(codec, WM8994_AIF1_DRC1_1, 0x00BC);
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, 0x0028);
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, 0x0186);
+
+ /* EQ AIF1 setting */
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_1, 0x0019);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_2, 0x6280);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_A, 0x0FC3);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_B, 0x03FD);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_PG, 0x00F4);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_A, 0x1F30);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_B, 0xF0CD);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_C, 0x040A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_PG, 0x032C);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_A, 0x1C52);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_B, 0xF379);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_C, 0x040A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_PG, 0x0DC1);
+
+ if (wm8994->ringtone_active)
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE, PLAYBACK_RING_SPK);
+ else
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE, PLAYBACK_SPK);
+
+ /* enable timeslot0 to left dac */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC1L_MASK);
+ val |= WM8994_AIF1DAC1L_TO_DAC1L;
+ wm8994_write(codec, WM8994_DAC1_LEFT_MIXER_ROUTING, val);
+
+#ifdef CONFIG_SND_VOODOO
+ voodoo_hook_playback_speaker();
+#endif
+
+ /* Enbale bias,vmid and Left speaker */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK |
+ WM8994_HPOUT1L_ENA_MASK | WM8994_HPOUT1R_ENA_MASK |
+ WM8994_SPKOUTR_ENA_MASK | WM8994_SPKOUTL_ENA_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL | WM8994_SPKOUTL_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ /* Unmute */
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK | WM8994_AIF1DAC1_MONO_MASK);
+ val |= (WM8994_AIF1DAC1_UNMUTE | WM8994_AIF1DAC1_MONO);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+
+}
+
+void wm8994_set_playback_speaker_headset(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ u16 val;
+
+ u16 nreadservo4val = 0;
+ u16 ncompensationresult = 0;
+ u16 ncompensationresultlow = 0;
+ u16 ncompensationresulthigh = 0;
+ u8 nservo4low = 0;
+ u8 nservo4high = 0;
+
+ wm8994_earsel_control(wm8994->pdata, 0);
+
+ /* Enable the Timeslot0 to DAC1L */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC1L_MASK);
+ val |= WM8994_AIF1DAC1L_TO_DAC1L;
+ wm8994_write(codec, WM8994_DAC1_LEFT_MIXER_ROUTING, val);
+
+ /* Enable the Timeslot0 to DAC1R */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1R_TO_DAC1R_MASK);
+ val |= WM8994_AIF1DAC1R_TO_DAC1R;
+ wm8994_write(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING, val);
+
+ /* Speaker Volume Control */
+ val = wm8994_read(codec, WM8994_SPEAKER_VOLUME_LEFT);
+ val &= ~(WM8994_SPKOUTL_MUTE_N_MASK);
+ val |= (WM8994_SPKOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_SPEAKER_VOLUME_LEFT, val);
+
+ val = wm8994_read(codec, WM8994_SPEAKER_VOLUME_RIGHT);
+ val &= ~(WM8994_SPKOUTR_MUTE_N_MASK);
+ wm8994_write(codec, WM8994_SPEAKER_VOLUME_RIGHT, val);
+
+ val = wm8994_read(codec, WM8994_SPKOUT_MIXERS);
+ val &= ~(WM8994_SPKMIXL_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTR_MASK);
+ val |= WM8994_SPKMIXL_TO_SPKOUTL;
+ wm8994_write(codec, WM8994_SPKOUT_MIXERS, val);
+
+ /* Unmute the DAC path */
+ val = wm8994_read(codec, WM8994_SPEAKER_MIXER);
+ val &= ~(WM8994_DAC1L_TO_SPKMIXL_MASK);
+ val |= WM8994_DAC1L_TO_SPKMIXL;
+ wm8994_write(codec, WM8994_SPEAKER_MIXER, val);
+
+ /* Configuring the Digital Paths */
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, 0x56);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x56, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0000);
+ val = 0x0000;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, WM8994_CLASS_W_1);
+ val &= ~(0x0005);
+ val = 0x0005;
+ wm8994_write(codec, WM8994_CLASS_W_1, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1L_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1R_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1R_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+
+ /* DC Servo Series Count */
+ val = 0x03E0;
+ wm8994_write(codec, WM8994_DC_SERVO_2, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK |
+ WM8994_HPOUT1L_ENA_MASK | WM8994_HPOUT1R_ENA_MASK |
+ WM8994_SPKOUTL_ENA_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL |
+ WM8994_HPOUT1R_ENA | WM8994_HPOUT1L_ENA |
+ WM8994_SPKOUTL_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ val = (WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, val);
+
+ /* Enable Charge Pump */
+ /* this is from wolfson */
+ val = wm8994_read(codec, WM8994_CHARGE_PUMP_1);
+ val &= ~WM8994_CP_ENA_MASK ;
+ val |= WM8994_CP_ENA | WM8994_CP_ENA_DEFAULT;
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, val);
+
+ msleep(5);
+
+ /* Enable DAC1 and DAC2 and the Timeslot0 for AIF1 */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_DAC1R_ENA_MASK | WM8994_DAC1L_ENA_MASK |
+ WM8994_AIF1DAC1R_ENA_MASK | WM8994_AIF1DAC1L_ENA_MASK);
+ val |= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ /* Enbale DAC1L to HPOUT1L path */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_1);
+ val &= ~(WM8994_DAC1L_TO_HPOUT1L_MASK | WM8994_DAC1L_TO_MIXOUTL_MASK);
+ val |= WM8994_DAC1L_TO_MIXOUTL;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val);
+
+ /* Enbale DAC1R to HPOUT1R path */
+ val = wm8994_read(codec, WM8994_OUTPUT_MIXER_2);
+ val &= ~(WM8994_DAC1R_TO_HPOUT1R_MASK | WM8994_DAC1R_TO_MIXOUTR_MASK);
+ val |= WM8994_DAC1R_TO_MIXOUTR;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val);
+
+ /* Enbale bias,vmid, hp left and right and Left speaker */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_3);
+ val &= ~(WM8994_MIXOUTLVOL_ENA_MASK | WM8994_MIXOUTRVOL_ENA_MASK |
+ WM8994_MIXOUTL_ENA_MASK | WM8994_MIXOUTR_ENA_MASK |
+ WM8994_SPKLVOL_ENA_MASK);
+ val |= (WM8994_MIXOUTL_ENA | WM8994_MIXOUTR_ENA | WM8994_SPKLVOL_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, val);
+
+ /* DC Servo */
+ if (!wm8994->dc_servo[DCS_SPK_HP]) {
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_SERIES_0 |
+ WM8994_DCS_TRIG_SERIES_1);
+
+ nreadservo4val = wm8994_read(codec, WM8994_DC_SERVO_4);
+ nservo4low = (signed char)(nreadservo4val & 0xff);
+ nservo4high = (signed char)((nreadservo4val>>8) & 0xff);
+
+ ncompensationresultlow = ((signed short)nservo4low - 5)
+ & 0x00ff;
+ ncompensationresulthigh = ((signed short)(nservo4high - 5)<<8)
+ & 0xff00;
+ ncompensationresult = ncompensationresultlow |
+ ncompensationresulthigh;
+ } else {
+ ncompensationresult = wm8994->dc_servo[DCS_SPK_HP];
+ }
+
+ wm8994_write(codec, WM8994_DC_SERVO_4, ncompensationresult);
+ wm8994->dc_servo[DCS_SPK_HP] = ncompensationresult;
+
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_DAC_WR_1 | WM8994_DCS_TRIG_DAC_WR_0);
+
+ val = wm8994_read(codec, WM8994_ANALOGUE_HP_1);
+ val &= ~(WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1R_OUTP_MASK |
+ WM8994_HPOUT1R_RMV_SHORT_MASK | WM8994_HPOUT1L_DLY_MASK |
+ WM8994_HPOUT1L_OUTP_MASK | WM8994_HPOUT1L_RMV_SHORT_MASK);
+ val |= (WM8994_HPOUT1L_RMV_SHORT | WM8994_HPOUT1L_OUTP |
+ WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_RMV_SHORT |
+ WM8994_HPOUT1R_OUTP | WM8994_HPOUT1R_DLY);
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, val);
+
+ if (wm8994->ringtone_active)
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE,
+ PLAYBACK_RING_SPK_HP);
+ else
+ wm8994_set_codec_gain(codec, PLAYBACK_MODE, PLAYBACK_SPK_HP);
+
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK | WM8994_AIF1DAC1_MONO_MASK);
+ val |= (WM8994_AIF1DAC1_UNMUTE | WM8994_AIF1DAC1_MONO);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+
+}
+
+void wm8994_set_playback_bluetooth(struct snd_soc_codec *codec)
+{
+ u16 val;
+
+ DEBUG_LOG("BT Playback Path for SCO\n");
+
+ wm8994_set_bluetooth_common_setting(codec);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_BIAS_ENA_MASK | WM8994_VMID_SEL_MASK);
+ val |= (WM8994_BIAS_ENA | WM8994_VMID_SEL_NORMAL);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, 0x0000);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, 0x0000);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_4);
+ val &= ~(WM8994_AIF2ADCL_ENA_MASK | WM8994_AIF2ADCR_ENA_MASK);
+ val |= (WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
+ WM8994_AIF1DAC1L_ENA_MASK | WM8994_AIF1DAC1R_ENA_MASK |
+ WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK);
+ val |= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
+ WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_6);
+ val &= ~(WM8994_AIF3_ADCDAT_SRC_MASK);
+ val |= (0x0001 << WM8994_AIF3_ADCDAT_SRC_SHIFT);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_6, val);
+
+ /* Mixer Routing*/
+ val = wm8994_read(codec, WM8994_DAC2_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC2L_MASK);
+ val |= (WM8994_AIF1DAC1L_TO_DAC2L);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1R_TO_DAC2R_MASK);
+ val |= (WM8994_AIF1DAC1R_TO_DAC2R);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING, val);
+
+ /* Volume*/
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_VOLUME, 0x01C0);
+
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ wm8994_write(codec, WM8994_OVERSAMPLING, 0X0000);
+
+ /* GPIO Configuration*/
+ wm8994_write(codec, WM8994_GPIO_8, WM8994_GP8_DIR | WM8994_GP8_DB);
+ wm8994_write(codec, WM8994_GPIO_9, WM8994_GP9_DB);
+ wm8994_write(codec, WM8994_GPIO_10, WM8994_GP10_DB);
+ wm8994_write(codec, WM8994_GPIO_11, WM8994_GP11_DB);
+
+ /* Un-Mute*/
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK | WM8994_AIF1DAC1_MONO_MASK);
+ val |= (WM8994_AIF1DAC1_UNMUTE);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+
+}
+
+static void wm8994_set_cdma_voicecall_common_setting(struct snd_soc_codec *codec)
+{
+ int val;
+
+ wm8994_write(codec, WM8994_ANTIPOP_2, 0x0068);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, 0x0003);
+ msleep(50);
+ /* GPIO Configuration */
+ wm8994_write(codec, WM8994_GPIO_1, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_2, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_3, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_4, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_5, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_6, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_7, 0x0100);
+ wm8994_write(codec, WM8994_GPIO_8, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_9, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_10, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_11, 0xA101);
+
+ wm8994_write(codec, WM8994_FLL2_CONTROL_2, 0x2F00);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_3, 0x3126);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_4, 0x0600);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_5, 0x0C81);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_1, 0x0001);
+
+ val = wm8994_read(codec, WM8994_AIF2_CLOCKING_1);
+ if (!(val & WM8994_AIF2CLK_ENA))
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+
+ wm8994_write(codec, WM8994_AIF2_RATE, 0x0003);
+
+ /* AIF2 Interface - PCM Stereo mode */
+ /* Left Justified, BCLK invert, LRCLK Invert */
+ wm8994_write(codec, WM8994_AIF2_CONTROL_1, 0x4118);
+
+ wm8994_write(codec, WM8994_AIF2_BCLK, 0x70);
+ wm8994_write(codec, WM8994_AIF2_CONTROL_2, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_MASTER_SLAVE, 0);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
+ WM8994_AIF1DAC1L_ENA_MASK | WM8994_AIF1DAC1R_ENA_MASK |
+ WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK);
+ val |= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
+ WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ /* Clocking */
+ val = wm8994_read(codec, WM8994_CLOCKING_1);
+ val |= (WM8994_DSP_FS2CLK_ENA);
+ wm8994_write(codec, WM8994_CLOCKING_1, 0x000F);
+
+ /* AIF1 & AIF2 Output is connected to DAC1 */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC1L_MASK |
+ WM8994_AIF2DACL_TO_DAC1L_MASK);
+ val |= (WM8994_AIF1DAC1L_TO_DAC1L | WM8994_AIF2DACL_TO_DAC1L);
+ wm8994_write(codec, WM8994_DAC1_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1R_TO_DAC1R_MASK |
+ WM8994_AIF2DACR_TO_DAC1R_MASK);
+ val |= (WM8994_AIF1DAC1R_TO_DAC1R | WM8994_AIF2DACR_TO_DAC1R);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING, val);
+
+ wm8994_write(codec, 0x6, 0x0);
+}
+
+static void wm8994_set_gsm_voicecall_common_setting(struct snd_soc_codec *codec)
+{
+ int val;
+
+ /* GPIO Configuration */
+ wm8994_write(codec, WM8994_GPIO_1, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_2, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_3, 0x0100);
+ wm8994_write(codec, WM8994_GPIO_4, 0x0100);
+ wm8994_write(codec, WM8994_GPIO_5, 0x8100);
+ wm8994_write(codec, WM8994_GPIO_6, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_7, 0x0100);
+ wm8994_write(codec, WM8994_GPIO_8, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_9, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_10, 0xA101);
+ wm8994_write(codec, WM8994_GPIO_11, 0xA101);
+
+ wm8994_write(codec, WM8994_FLL2_CONTROL_2, 0x2F00);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_3, 0x3126);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL2_CONTROL_1,
+ WM8994_FLL2_FRACN_ENA | WM8994_FLL2_ENA);
+
+ val = wm8994_read(codec, WM8994_AIF2_CLOCKING_1);
+ if (!(val & WM8994_AIF2CLK_ENA))
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0018);
+
+ wm8994_write(codec, WM8994_AIF2_RATE, 0x3 << WM8994_AIF2CLK_RATE_SHIFT);
+
+ /* AIF2 Interface - PCM Stereo mode */
+ /* Left Justified, BCLK invert, LRCLK Invert */
+ wm8994_write(codec, WM8994_AIF2_CONTROL_1,
+ WM8994_AIF2ADCR_SRC | WM8994_AIF2_BCLK_INV | 0x18);
+
+ wm8994_write(codec, WM8994_AIF2_BCLK, 0x70);
+ wm8994_write(codec, WM8994_AIF2_CONTROL_2, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_MASTER_SLAVE, WM8994_AIF2_MSTR |
+ WM8994_AIF2_CLK_FRC | WM8994_AIF2_LRCLK_FRC);
+
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_5);
+ val &= ~(WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
+ WM8994_AIF1DAC1L_ENA_MASK | WM8994_AIF1DAC1R_ENA_MASK |
+ WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK);
+ val |= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
+ WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_5, val);
+
+ /* Clocking */
+ val = wm8994_read(codec, WM8994_CLOCKING_1);
+ val |= (WM8994_DSP_FS2CLK_ENA);
+ wm8994_write(codec, WM8994_CLOCKING_1, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_6, 0x0);
+
+ /* AIF1 & AIF2 Output is connected to DAC1 */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1L_TO_DAC1L_MASK |
+ WM8994_AIF2DACL_TO_DAC1L_MASK);
+ val |= (WM8994_AIF1DAC1L_TO_DAC1L | WM8994_AIF2DACL_TO_DAC1L);
+ wm8994_write(codec, WM8994_DAC1_LEFT_MIXER_ROUTING, val);
+
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
+ val &= ~(WM8994_AIF1DAC1R_TO_DAC1R_MASK |
+ WM8994_AIF2DACR_TO_DAC1R_MASK);
+ val |= (WM8994_AIF1DAC1R_TO_DAC1R | WM8994_AIF2DACR_TO_DAC1R);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING, val);
+
+ wm8994_write(codec, 0x6, 0x0);
+}
+
+
+void wm8994_set_voicecall_common_setting(struct snd_soc_codec *codec)
+{
+ if (herring_is_cdma_wimax_dev())
+ wm8994_set_cdma_voicecall_common_setting(codec);
+ else
+ wm8994_set_gsm_voicecall_common_setting(codec);
+
+#ifdef CONFIG_SND_VOODOO_RECORD_PRESETS
+ voodoo_hook_record_main_mic();
+#endif
+}
+
+static void wm8994_set_cdma_voicecall_receiver(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ DEBUG_LOG("");
+
+ audio_ctrl_mic_bias_gpio(wm8994->pdata, 1);
+
+ wm8994_write(codec, 0x0039, 0x0068); /* Anti Pop2 */
+ wm8994_write(codec, 0x0001, 0x0003); /* Power Management 1 */
+ msleep(50);
+ wm8994_write(codec, 0x0015, 0x0040);
+ wm8994_write(codec, 0x0702, 0x8100); /* GPIO 3. Speech PCM Clock */
+ wm8994_write(codec, 0x0703, 0x8100); /* GPIO 4. Speech PCM Sync */
+ /* GPIO 5. Speech PCM Data Out */
+ wm8994_write(codec, 0x0704, 0x8100);
+ /* GPIO 7. Speech PCM Data Input */
+ wm8994_write(codec, 0x0706, 0x0100);
+ wm8994_write(codec, 0x0244, 0x0C81); /* FLL2 Control 5 */
+ wm8994_write(codec, 0x0241, 0x2F00); /* FLL2 Control 2 */
+ wm8994_write(codec, 0x0243, 0x0600); /* FLL2 Control 4 */
+ wm8994_write(codec, 0x0240, 0x0001); /* FLL2 Control 1 */
+ msleep(3);
+
+ /* AIF2 Clocking 1. Clock Source Select */
+ wm8994_write(codec, 0x0204, 0x0008);
+
+ /* Clocking 1. '0x000A' is added for a playback. (original = 0x0007) */
+ wm8994_write(codec, 0x0208, 0x000F);
+
+ wm8994_write(codec, 0x0620, 0x0000); /* Oversampling */
+ wm8994_write(codec, 0x0211, 0x0003); /* AIF2 Rate */
+ wm8994_write(codec, 0x0310, 0x4118); /* AIF2 Control 1 */
+ /* AIF2 Control 2 pcm format is changed ulaw to linear */
+ wm8994_write(codec, 0x0311, 0x0000);
+ wm8994_write(codec, 0x0520, 0x0000); /* AIF2 DAC Filter 1 */
+ /* AIF2 Clocking 1. AIF2 Clock Enable */
+ wm8994_write(codec, 0x0204, 0x0009);
+
+ wm8994_write(codec, 0x0601, 0x0005); /* DAC1 Left Mixer Routing */
+ /* DAC1 Right Mixer Routing(Playback) */
+ wm8994_write(codec, 0x0602, 0x0001);
+ wm8994_write(codec, 0x0603, 0x018C); /* DAC2 Mixer Volumes */
+ wm8994_write(codec, 0x0604, 0x0030); /* DAC2 Left Mixer Routing */
+ wm8994_write(codec, 0x0605, 0x0010); /* DAC2 Right Mixer Routing */
+ wm8994_write(codec, 0x0621, 0x01C0); /* Sidetone */
+ wm8994_write(codec, 0x0002, 0x6240); /* Power Management 2 */
+ wm8994_write(codec, 0x0028, 0x0030); /* Input Mixer 2 */
+ wm8994_write(codec, 0x0018, 0x010A);
+
+ /* Output Mixer 5 */
+ val = wm8994_read(codec, 0x0031);
+ val &= ~(WM8994_DACL_MIXOUTL_VOL_MASK);
+ val |= 0x0000 << 0x0009;
+ wm8994_write(codec, 0x0031, val);
+
+ /* Output Mixer 6 */
+ val = wm8994_read(codec, 0x0032);
+ val &= ~(WM8994_DACR_MIXOUTR_VOL_MASK);
+ val |= 0x0000 << 0x0009;
+ wm8994_write(codec, 0x0032, val);
+
+ /* Left OPGA Volume */
+ val = wm8994_read(codec, 0x0020);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK | WM8994_MIXOUTL_VOL_MASK);
+ val |= (0x0100 | 0x0040 | 0x3D);
+ /* 05.24 Maximum ´ëºñ -6dB HAC ¿ë test -2 3B -> 39 */
+ wm8994_write(codec, 0x0020, 0x01F9);
+
+ /* Right OPGA Volume */
+ val = wm8994_read(codec, 0x0021);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK | WM8994_MIXOUTR_VOL_MASK);
+ val |= (0x0100 | 0x0040 | 0x3D);
+ wm8994_write(codec, 0x0021, 0x01F9);
+
+ wm8994_write(codec, 0x0312, 0x0000); /* Slave */
+ /* sub mic */
+ wm8994_write(codec, 0x0029, 0x0030); /* Input Mixer 3 */
+
+ wm8994_write(codec, 0x0015, 0x0000);
+ wm8994_write(codec, 0x0500, 0x0100); /* AIF2 ADC Left Volume */
+ wm8994_write(codec, 0x0004, 0x2002); /* Power Management 4 */
+ /* Power Management 5.'0x0303' added for a playback.(Original=0x2002) */
+ wm8994_write(codec, 0x0005, 0x2303);
+ /* Power Management 3.'0x00F0' added for a playback.(Original=0x00A0) */
+ wm8994_write(codec, 0x0003, 0x00F0);
+ wm8994_write(codec, 0x002D, 0x0001); /* Output Mixer 1 */
+ wm8994_write(codec, 0x002E, 0x0001); /* Output Mixer 2(Playback) */
+ /* HPOUT2 Mixer. '0x0008' added for a playback.(Original=0x0010) */
+ wm8994_write(codec, 0x0033, 0x0018);
+ wm8994_write(codec, 0x0038, 0x0040); /* Anti Pop 1 */
+ wm8994_write(codec, 0x0420, 0x0080); /* AIF1 DAC1 FIlter(Playback) */
+
+ /* HPOUT2 Volume */
+ wm8994_write(codec, 0x001F, 0x0000); /* HPOUT2 Volume */
+
+ wm8994_write(codec, 0x0001, 0x0803); /* Power Management 1 */
+
+ /* DAC1 Left Volume */
+ val = wm8994_read(codec, 0x0610);
+ val &= ~(WM8994_DAC1L_MUTE_MASK | WM8994_DAC1L_VOL_MASK);
+ val |= 0xC0;
+ wm8994_write(codec, 0x0610, 0x01C0);
+
+ /* DAC1 Right Volume */
+ val = wm8994_read(codec, 0x0611);
+ val &= ~(WM8994_DAC1R_MUTE_MASK | WM8994_DAC1R_VOL_MASK);
+ val |= 0xC0;
+ wm8994_write(codec, 0x0611, 0x01C0);
+
+ /* Power Management 3(Playback) */
+ wm8994_write(codec, 0x0003, 0x00F0);
+
+ wm8994_write(codec, 0x06, 0x0000);
+ wm8994_write(codec, 0x0612, 0x01C0); /* DAC2 Left Volume */
+ wm8994_write(codec, 0x0613, 0x01C0); /* DAC2 Right Volume */
+ wm8994_write(codec, 0x0500, 0x01C0); /* AIF2 ADC Left Volume */
+}
+
+static void wm8994_set_gsm_voicecall_receiver(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ DEBUG_LOG("");
+
+ audio_ctrl_mic_bias_gpio(wm8994->pdata, 1);
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_DEFAULT);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2,
+ WM8994_TSHUT_ENA | WM8994_TSHUT_OPDIS | WM8994_MIXINL_ENA |
+ WM8994_IN1L_ENA);
+
+ wm8994_write(codec, WM8994_INPUT_MIXER_2,
+ WM8994_IN1LP_TO_IN1L | WM8994_IN1LN_TO_IN1L);
+
+ /* Digital Path Enables and Unmutes */
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4,
+ WM8994_AIF2ADCL_ENA | WM8994_ADCL_ENA);
+
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x000C);
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_VOLUME, 0x01C0);
+
+ /* Tx -> AIF2 Path */
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2L);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2R);
+
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ /* Unmute IN1L PGA, update volume */
+ val = wm8994_read(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, val);
+
+ /* Unmute the PGA */
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_3);
+ val &= ~(WM8994_IN1L_TO_MIXINL_MASK);
+ val |= (WM8994_IN1L_TO_MIXINL);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, val);
+
+ /* Volume Control - Output */
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_HPOUT2_VOLUME);
+ val &= ~(WM8994_HPOUT2_MUTE_MASK);
+ wm8994_write(codec, WM8994_HPOUT2_VOLUME, val);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_RCV);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ /* Output Mixing */
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, WM8994_DAC1L_TO_MIXOUTL);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, WM8994_DAC1R_TO_MIXOUTR);
+
+ /* Analogue Output Configuration */
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3,
+ WM8994_MIXOUTLVOL_ENA | WM8994_MIXOUTRVOL_ENA |
+ WM8994_MIXOUTL_ENA | WM8994_MIXOUTR_ENA);
+ wm8994_write(codec, WM8994_HPOUT2_MIXER, WM8994_MIXOUTLVOL_TO_HPOUT2 |
+ WM8994_MIXOUTRVOL_TO_HPOUT2);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_HPOUT2_ENA | WM8994_VMID_SEL_NORMAL | WM8994_BIAS_ENA);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0000);
+
+}
+
+
+void wm8994_set_voicecall_receiver(struct snd_soc_codec *codec)
+{
+ if (herring_is_cdma_wimax_dev())
+ wm8994_set_cdma_voicecall_receiver(codec);
+ else
+ wm8994_set_gsm_voicecall_receiver(codec);
+}
+
+void wm8994_set_voicecall_headset(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ u16 testreturn1 = 0;
+ u16 testreturn2 = 0;
+ u16 testlow1 = 0;
+ u16 testhigh1 = 0;
+ u8 testlow = 0;
+ u8 testhigh = 0;
+
+ DEBUG_LOG("");
+
+ wm8994_earsel_control(wm8994->pdata, 1);
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ /* Digital Path Enables and Unmutes */
+ if (wm8994->hw_version == 3) { /* H/W Rev D */
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC2_TO_DAC2L);
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x0180);
+ wm8994_write(codec, WM8994_SIDETONE, 0x01C0);
+ } else { /* H/W Rev B */
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x000C);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2L);
+ wm8994_write(codec, WM8994_SIDETONE, 0x01C1);
+ }
+
+ /* Analogue Input Configuration */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_2);
+ val &= ~(WM8994_TSHUT_ENA_MASK | WM8994_TSHUT_OPDIS_MASK |
+ WM8994_MIXINR_ENA_MASK | WM8994_IN1R_ENA_MASK);
+ val |= (WM8994_TSHUT_ENA | WM8994_TSHUT_OPDIS |
+ WM8994_MIXINR_ENA | WM8994_IN1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, 0x6110);
+
+ val = wm8994_read(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_4);
+ val &= ~(WM8994_IN1R_TO_MIXINR_MASK);
+ val |= (WM8994_IN1R_TO_MIXINR);
+ wm8994_write(codec, WM8994_INPUT_MIXER_4, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_2);
+ val &= ~(WM8994_IN1RP_TO_IN1R_MASK | WM8994_IN1RN_TO_IN1R_MASK);
+ val |= (WM8994_IN1RP_TO_IN1R | WM8994_IN1RN_TO_IN1R);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, 0x0003);
+
+ /* Unmute*/
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4, 0x2001);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, 0x56);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x56, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0000);
+ val = 0x0000;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, WM8994_CLASS_W_1);
+ val &= ~(0x0005);
+ val |= 0x0005;
+ wm8994_write(codec, WM8994_CLASS_W_1, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1L_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1R_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1R_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_DC_SERVO_2);
+ val &= ~(0x03E0);
+ val = 0x03E0;
+ wm8994_write(codec, WM8994_DC_SERVO_2, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, 0x0303);
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x0022);
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, 0x9F25);
+
+ msleep(5);
+
+ /* Analogue Output Configuration */
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, 0x0001);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, 0x0001);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, 0x0030);
+
+ if (herring_is_cdma_wimax_dev())
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+ else
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ if (!wm8994->dc_servo[DCS_VOICE]) {
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_SERIES_0 |
+ WM8994_DCS_TRIG_SERIES_1);
+
+ testreturn1 = wm8994_read(codec, WM8994_DC_SERVO_4);
+
+ testlow = (signed char)(testreturn1 & 0xff);
+ testhigh = (signed char)((testreturn1>>8) & 0xff);
+
+ testlow1 = ((signed short)testlow - 5) & 0x00ff;
+ testhigh1 = (((signed short)(testhigh - 5)<<8) & 0xff00);
+ testreturn2 = testlow1|testhigh1;
+ } else {
+ testreturn2 = wm8994->dc_servo[DCS_VOICE];
+ }
+
+ wm8994_write(codec, WM8994_DC_SERVO_4, testreturn2);
+
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_DAC_WR_0 | WM8994_DCS_TRIG_DAC_WR_1);
+
+ wm8994->dc_servo[DCS_VOICE] = testreturn2;
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x00EE);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_HP);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0000);
+
+}
+
+void wm8994_set_voicecall_headphone(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ u16 testreturn1 = 0;
+ u16 testreturn2 = 0;
+ u16 testlow1 = 0;
+ u16 testhigh1 = 0;
+ u8 testlow = 0;
+ u8 testhigh = 0;
+
+ DEBUG_LOG("");
+ audio_ctrl_mic_bias_gpio(wm8994->pdata, 1);
+
+ wm8994_earsel_control(wm8994->pdata, 1);
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ /* Digital Path Enables and Unmutes */
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x000C);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2L);
+
+ /* Analogue Input Configuration */
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2,
+ WM8994_TSHUT_ENA | WM8994_TSHUT_OPDIS | WM8994_MIXINL_ENA |
+ WM8994_IN1L_ENA);
+
+ /* Unmute IN1L PGA, update volume */
+ val = wm8994_read(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, val);
+
+ /* Unmute the PGA */
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_3);
+ val &= ~(WM8994_IN1L_TO_MIXINL_MASK);
+ val |= (WM8994_IN1L_TO_MIXINL);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, val);
+
+ wm8994_write(codec, WM8994_INPUT_MIXER_2,
+ WM8994_IN1LP_TO_IN1L | WM8994_IN1LN_TO_IN1L);
+
+ /* Unmute*/
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ /* Digital Path Enables and Unmutes */
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4,
+ WM8994_AIF2ADCL_ENA | WM8994_ADCL_ENA);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, 0x56);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x56, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0000);
+ val = 0x0000;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, WM8994_CLASS_W_1);
+ val &= ~(0x0005);
+ val |= 0x0005;
+ wm8994_write(codec, WM8994_CLASS_W_1, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1L_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1R_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1R_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_DC_SERVO_2);
+ val &= ~(0x03E0);
+ val = 0x03E0;
+ wm8994_write(codec, WM8994_DC_SERVO_2, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, 0x0303);
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x0022);
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, 0x9F25);
+
+ msleep(5);
+
+ /* Analogue Output Configuration */
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, 0x0001);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, 0x0001);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, 0x0030);
+
+ if (herring_is_cdma_wimax_dev())
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+ else
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ if (!wm8994->dc_servo[DCS_VOICE]) {
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_SERIES_0 |
+ WM8994_DCS_TRIG_SERIES_1);
+
+ testreturn1 = wm8994_read(codec, WM8994_DC_SERVO_4);
+
+ testlow = (signed char)(testreturn1 & 0xff);
+ testhigh = (signed char)((testreturn1>>8) & 0xff);
+
+ testlow1 = ((signed short)testlow - 5) & 0x00ff;
+ testhigh1 = (((signed short)(testhigh - 5)<<8) & 0xff00);
+ testreturn2 = testlow1|testhigh1;
+ } else {
+ testreturn2 = wm8994->dc_servo[DCS_VOICE];
+ }
+
+ wm8994_write(codec, WM8994_DC_SERVO_4, testreturn2);
+
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_DAC_WR_0 | WM8994_DCS_TRIG_DAC_WR_1);
+
+ wm8994->dc_servo[DCS_VOICE] = testreturn2;
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x00EE);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_HP_NO_MIC);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0000);
+
+}
+
+void wm8994_set_voicecall_speaker(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ DEBUG_LOG("");
+
+ audio_ctrl_mic_bias_gpio(wm8994->pdata, 1);
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ wm8994_write(codec, 0x601, 0x0005);
+ wm8994_write(codec, 0x602, 0x0005);
+ wm8994_write(codec, 0x603, 0x000C);
+ /* Tx -> AIF2 Path */
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2L);
+
+ /* Analogue Input Configuration*/
+ wm8994_write(codec, 0x02, 0x6240);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, WM8994_IN1LP_TO_IN1L |
+ WM8994_IN1LN_TO_IN1L);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_3);
+ val &= ~(WM8994_IN1L_TO_MIXINL_MASK);
+ val |= (WM8994_IN1L_TO_MIXINL);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, val);
+
+ /* Analogue Output Configuration*/
+ wm8994_write(codec, 0x03, 0x0300);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4,
+ WM8994_AIF2ADCL_ENA | WM8994_ADCL_ENA);
+
+ if (herring_is_cdma_wimax_dev())
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+ else
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ val = wm8994_read(codec, WM8994_SPEAKER_VOLUME_LEFT);
+ val &= ~(WM8994_SPKOUTL_MUTE_N_MASK);
+ val |= (WM8994_SPKOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_SPEAKER_VOLUME_LEFT, val);
+
+ val = wm8994_read(codec, WM8994_SPEAKER_VOLUME_RIGHT);
+ val &= ~(WM8994_SPKOUTR_MUTE_N_MASK | WM8994_SPKOUTR_VOL_MASK);
+ wm8994_write(codec, WM8994_SPEAKER_VOLUME_RIGHT, val);
+
+ val = wm8994_read(codec, WM8994_SPKOUT_MIXERS);
+ val &= ~(WM8994_SPKMIXL_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTL_MASK |
+ WM8994_SPKMIXR_TO_SPKOUTR_MASK);
+ val |= WM8994_SPKMIXL_TO_SPKOUTL;
+ wm8994_write(codec, WM8994_SPKOUT_MIXERS, val);
+
+ wm8994_write(codec, 0x36, 0x0003);
+ /* Digital Path Enables and Unmutes*/
+
+ wm8994_write(codec, WM8994_SIDETONE, 0x01C0);
+
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x0000);
+ wm8994_write(codec, WM8994_DC_SERVO_1, 0x0000);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_SPKOUTL_ENA | WM8994_VMID_SEL_NORMAL | WM8994_BIAS_ENA);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_SPK);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, WM8994_AIF1DAC1_UNMUTE);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, WM8994_AIF1DAC2_UNMUTE);
+}
+
+void wm8994_set_voicecall_bluetooth(struct snd_soc_codec *codec)
+{
+ int val;
+
+ DEBUG_LOG("");
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ /* GPIO Configuration */
+ wm8994_write(codec, WM8994_GPIO_8, WM8994_GP8_DIR | WM8994_GP8_DB);
+ wm8994_write(codec, WM8994_GPIO_9, WM8994_GP9_DB);
+ wm8994_write(codec, WM8994_GPIO_10, WM8994_GP10_DB);
+ wm8994_write(codec, WM8994_GPIO_11, WM8994_GP11_DB);
+
+ /* Digital Path Enables and Unmutes */
+ val = wm8994_read(codec, WM8994_POWER_MANAGEMENT_1);
+ val &= ~(WM8994_SPKOUTL_ENA_MASK | WM8994_HPOUT2_ENA_MASK |
+ WM8994_HPOUT1L_ENA_MASK | WM8994_HPOUT1R_ENA_MASK);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4,
+ WM8994_AIF2ADCL_ENA | WM8994_ADCL_ENA);
+
+ /* If Input MIC is enabled, bluetooth Rx is muted. */
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME,
+ WM8994_IN1L_MUTE);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME,
+ WM8994_IN1R_MUTE);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, 0x00);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, 0x00);
+ wm8994_write(codec, WM8994_INPUT_MIXER_4, 0x00);
+
+ /*
+ * for BT DTMF Play
+ * Rx Path: AIF2ADCDAT2 select
+ * CP(CALL) Path:GPIO5/DACDAT2 select
+ * AP(DTMF) Path: DACDAT1 select
+ * Tx Path: GPIO8/DACDAT3 select
+ */
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_6, 0x000C);
+
+ /* AIF1 & AIF2 Output is connected to DAC1 */
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_AIF2DACL_TO_DAC2L | WM8994_AIF1DAC1L_TO_DAC2L);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_MIXER_ROUTING,
+ WM8994_AIF2DACR_TO_DAC2R | WM8994_AIF1DAC1R_TO_DAC2R);
+
+ if (herring_is_cdma_wimax_dev())
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+ else
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x000C);
+
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+ wm8994_write(codec, WM8994_DAC2_RIGHT_VOLUME, 0x01C0);
+
+ wm8994_write(codec, WM8994_OVERSAMPLING, 0X0000);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_BT);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0000);
+}
+
+void wm8994_set_voicecall_tty_vco(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ u16 testreturn1 = 0;
+ u16 testreturn2 = 0;
+ u16 testlow1 = 0;
+ u16 testhigh1 = 0;
+ u8 testlow = 0;
+ u8 testhigh = 0;
+
+ DEBUG_LOG("");
+ audio_ctrl_mic_bias_gpio(wm8994->pdata, 1);
+
+ wm8994_earsel_control(wm8994->pdata, 1);
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ /* Digital Path Enables and Unmutes */
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x000C);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2L);
+
+ /* Analogue Input Configuration */
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2,
+ WM8994_TSHUT_ENA | WM8994_TSHUT_OPDIS | WM8994_MIXINL_ENA |
+ WM8994_IN1L_ENA);
+
+ /* Unmute IN1L PGA, update volume */
+ val = wm8994_read(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, val);
+
+ /* Unmute the PGA */
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_3);
+ val &= ~(WM8994_IN1L_TO_MIXINL_MASK);
+ val |= (WM8994_IN1L_TO_MIXINL);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, val);
+
+ wm8994_write(codec, WM8994_INPUT_MIXER_2,
+ WM8994_IN1LP_TO_IN1L | WM8994_IN1LN_TO_IN1L);
+
+ /* Unmute*/
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ /* Digital Path Enables and Unmutes */
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4,
+ WM8994_AIF2ADCL_ENA | WM8994_ADCL_ENA);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, 0x56);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x56, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0000);
+ val = 0x0000;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, WM8994_CLASS_W_1);
+ val &= ~(0x0005);
+ val |= 0x0005;
+ wm8994_write(codec, WM8994_CLASS_W_1, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1L_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1R_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1R_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_DC_SERVO_2);
+ val &= ~(0x03E0);
+ val = 0x03E0;
+ wm8994_write(codec, WM8994_DC_SERVO_2, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, 0x0303);
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x0022);
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, 0x9F25);
+
+ msleep(5);
+
+ /* Analogue Output Configuration */
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, 0x0001);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, 0x0001);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, 0x0030);
+
+ if (herring_is_cdma_wimax_dev())
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+ else
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ if (!wm8994->dc_servo[DCS_VOICE]) {
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_SERIES_0 |
+ WM8994_DCS_TRIG_SERIES_1);
+
+ testreturn1 = wm8994_read(codec, WM8994_DC_SERVO_4);
+
+ testlow = (signed char)(testreturn1 & 0xff);
+ testhigh = (signed char)((testreturn1>>8) & 0xff);
+
+ testlow1 = ((signed short)testlow - 5) & 0x00ff;
+ testhigh1 = (((signed short)(testhigh - 5)<<8) & 0xff00);
+ testreturn2 = testlow1|testhigh1;
+ } else {
+ testreturn2 = wm8994->dc_servo[DCS_VOICE];
+ }
+
+ wm8994_write(codec, WM8994_DC_SERVO_4, testreturn2);
+
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_DAC_WR_0 | WM8994_DCS_TRIG_DAC_WR_1);
+
+ wm8994->dc_servo[DCS_VOICE] = testreturn2;
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x00EE);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_TTY_VCO);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0000);
+
+}
+
+void wm8994_set_voicecall_tty_hco(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ u16 testreturn1 = 0;
+ u16 testreturn2 = 0;
+ u16 testlow1 = 0;
+ u16 testhigh1 = 0;
+ u8 testlow = 0;
+ u8 testhigh = 0;
+
+ DEBUG_LOG("");
+
+ wm8994_earsel_control(wm8994->pdata, 1);
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ /* Digital Path Enables and Unmutes */
+ if (wm8994->hw_version == 3) { /* H/W Rev D */
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC2_TO_DAC2L);
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x0180);
+ wm8994_write(codec, WM8994_SIDETONE, 0x01C0);
+ } else { /* H/W Rev B */
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x000C);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2L);
+ wm8994_write(codec, WM8994_SIDETONE, 0x01C1);
+ }
+
+ /* Analogue Input Configuration */
+ val = (WM8994_TSHUT_ENA | WM8994_TSHUT_OPDIS |
+ WM8994_MIXINR_ENA | WM8994_IN1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_4);
+ val &= ~(WM8994_IN1R_TO_MIXINR_MASK);
+ val |= (WM8994_IN1R_TO_MIXINR);
+ wm8994_write(codec, WM8994_INPUT_MIXER_4, val);
+
+ val = (WM8994_IN1RP_TO_IN1R | WM8994_IN1RN_TO_IN1R);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, val);
+
+ /* Unmute*/
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4,
+ WM8994_AIF2ADCL_ENA | WM8994_ADCR_ENA);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, 0x56);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x56, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0000);
+ val = 0x0000;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, WM8994_CLASS_W_1);
+ val &= ~(0x0005);
+ val |= 0x0005;
+ wm8994_write(codec, WM8994_CLASS_W_1, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1L_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1R_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1R_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_DC_SERVO_2);
+ val &= ~(0x03E0);
+ val = 0x03E0;
+ wm8994_write(codec, WM8994_DC_SERVO_2, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_HPOUT2_ENA | WM8994_VMID_SEL_NORMAL | WM8994_BIAS_ENA);
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x0022);
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, 0x9F25);
+
+ msleep(5);
+
+ /* Analogue Output Configuration */
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, 0x0001);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, 0x0001);
+ wm8994_write(codec, WM8994_HPOUT2_MIXER, WM8994_MIXOUTLVOL_TO_HPOUT2 |
+ WM8994_MIXOUTRVOL_TO_HPOUT2);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3,
+ WM8994_MIXOUTLVOL_ENA | WM8994_MIXOUTRVOL_ENA |
+ WM8994_MIXOUTL_ENA | WM8994_MIXOUTR_ENA);
+
+ if (herring_is_cdma_wimax_dev())
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+ else
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ if (!wm8994->dc_servo[DCS_VOICE]) {
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_SERIES_0 |
+ WM8994_DCS_TRIG_SERIES_1);
+
+ testreturn1 = wm8994_read(codec, WM8994_DC_SERVO_4);
+
+ testlow = (signed char)(testreturn1 & 0xff);
+ testhigh = (signed char)((testreturn1>>8) & 0xff);
+
+ testlow1 = ((signed short)testlow - 5) & 0x00ff;
+ testhigh1 = (((signed short)(testhigh - 5)<<8) & 0xff00);
+ testreturn2 = testlow1|testhigh1;
+ } else {
+ testreturn2 = wm8994->dc_servo[DCS_VOICE];
+ }
+
+ wm8994_write(codec, WM8994_DC_SERVO_4, testreturn2);
+
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_DAC_WR_0 | WM8994_DCS_TRIG_DAC_WR_1);
+
+ wm8994->dc_servo[DCS_VOICE] = testreturn2;
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x00EE);
+
+ val = wm8994_read(codec, WM8994_HPOUT2_VOLUME);
+ val &= ~(WM8994_HPOUT2_MUTE_MASK);
+ wm8994_write(codec, WM8994_HPOUT2_VOLUME, val);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_TTY_HCO);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0000);
+
+}
+
+void wm8994_set_voicecall_tty_full(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int val;
+
+ u16 testreturn1 = 0;
+ u16 testreturn2 = 0;
+ u16 testlow1 = 0;
+ u16 testhigh1 = 0;
+ u8 testlow = 0;
+ u8 testhigh = 0;
+
+ DEBUG_LOG("");
+
+ wm8994_earsel_control(wm8994->pdata, 1);
+
+ wm8994_set_voicecall_common_setting(codec);
+
+ /* Digital Path Enables and Unmutes */
+ if (wm8994->hw_version == 3) { /* H/W Rev D */
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC2_TO_DAC2L);
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x0180);
+ wm8994_write(codec, WM8994_SIDETONE, 0x01C0);
+ } else { /* H/W Rev B */
+ wm8994_write(codec, WM8994_DAC2_MIXER_VOLUMES, 0x000C);
+ wm8994_write(codec, WM8994_DAC2_LEFT_MIXER_ROUTING,
+ WM8994_ADC1_TO_DAC2L);
+ wm8994_write(codec, WM8994_SIDETONE, 0x01C1);
+ }
+
+ /* Analogue Input Configuration */
+ val = (WM8994_TSHUT_ENA | WM8994_TSHUT_OPDIS |
+ WM8994_MIXINR_ENA | WM8994_IN1R_ENA);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_2, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME);
+ val &= ~(WM8994_IN1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_INPUT_MIXER_4);
+ val &= ~(WM8994_IN1R_TO_MIXINR_MASK);
+ val |= (WM8994_IN1R_TO_MIXINR);
+ wm8994_write(codec, WM8994_INPUT_MIXER_4, val);
+
+ val = (WM8994_IN1RP_TO_IN1R | WM8994_IN1RN_TO_IN1R);
+ wm8994_write(codec, WM8994_INPUT_MIXER_2, val);
+
+ /* Unmute*/
+ val = wm8994_read(codec, WM8994_LEFT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTL_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTL_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OPGA_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OPGA_VOLUME);
+ val &= ~(WM8994_MIXOUTR_MUTE_N_MASK);
+ val |= (WM8994_MIXOUTR_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OPGA_VOLUME, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_4, 0x2001);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, 0x56);
+ val &= ~(0x0003);
+ val = 0x0003;
+ wm8994_write(codec, 0x56, val);
+
+ val = wm8994_read(codec, 0x102);
+ val &= ~(0x0000);
+ val = 0x0000;
+ wm8994_write(codec, 0x102, val);
+
+ val = wm8994_read(codec, WM8994_CLASS_W_1);
+ val &= ~(0x0005);
+ val |= 0x0005;
+ wm8994_write(codec, WM8994_CLASS_W_1, val);
+
+ val = wm8994_read(codec, WM8994_LEFT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1L_MUTE_N);
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_RIGHT_OUTPUT_VOLUME);
+ val &= ~(WM8994_HPOUT1R_MUTE_N_MASK);
+ val |= (WM8994_HPOUT1R_MUTE_N);
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+
+ val = wm8994_read(codec, WM8994_DC_SERVO_2);
+ val &= ~(0x03E0);
+ val = 0x03E0;
+ wm8994_write(codec, WM8994_DC_SERVO_2, val);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1, 0x0303);
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x0022);
+ wm8994_write(codec, WM8994_CHARGE_PUMP_1, 0x9F25);
+
+ msleep(5);
+
+ /* Analogue Output Configuration */
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, 0x0001);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, 0x0001);
+
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_3, 0x0030);
+
+ if (herring_is_cdma_wimax_dev())
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0009);
+ else
+ wm8994_write(codec, WM8994_AIF2_CLOCKING_1, 0x0019);
+
+ if (!wm8994->dc_servo[DCS_VOICE]) {
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_SERIES_0 |
+ WM8994_DCS_TRIG_SERIES_1);
+
+ testreturn1 = wm8994_read(codec, WM8994_DC_SERVO_4);
+
+ testlow = (signed char)(testreturn1 & 0xff);
+ testhigh = (signed char)((testreturn1>>8) & 0xff);
+
+ testlow1 = ((signed short)testlow - 5) & 0x00ff;
+ testhigh1 = (((signed short)(testhigh - 5)<<8) & 0xff00);
+ testreturn2 = testlow1|testhigh1;
+ } else {
+ testreturn2 = wm8994->dc_servo[DCS_VOICE];
+ }
+
+ wm8994_write(codec, WM8994_DC_SERVO_4, testreturn2);
+
+ wait_for_dc_servo(codec,
+ WM8994_DCS_TRIG_DAC_WR_0 | WM8994_DCS_TRIG_DAC_WR_1);
+
+ wm8994->dc_servo[DCS_VOICE] = testreturn2;
+
+ wm8994_write(codec, WM8994_ANALOGUE_HP_1, 0x00EE);
+
+ wm8994_set_codec_gain(codec, VOICECALL_MODE, VOICECALL_TTY_FULL);
+
+ /* Unmute DAC1 left */
+ val = wm8994_read(codec, WM8994_DAC1_LEFT_VOLUME);
+ val &= ~(WM8994_DAC1L_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_LEFT_VOLUME, val);
+
+ /* Unmute and volume ctrl RightDAC */
+ val = wm8994_read(codec, WM8994_DAC1_RIGHT_VOLUME);
+ val &= ~(WM8994_DAC1R_MUTE_MASK);
+ wm8994_write(codec, WM8994_DAC1_RIGHT_VOLUME, val);
+
+ wm8994_write(codec, WM8994_DAC2_LEFT_VOLUME, 0x01C0);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0000);
+
+}
+
+int wm8994_set_codec_gain(struct snd_soc_codec *codec, u16 mode, u16 device)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+ int i;
+ u32 gain_set_bits = COMMON_SET_BIT;
+ u16 val;
+ struct gain_info_t *default_gain_table_p = NULL;
+ int table_num = 0;
+
+ if (mode == PLAYBACK_MODE) {
+
+ if (herring_is_cdma_wimax_dev())
+ default_gain_table_p = cdma_playback_gain_table;
+ else
+ default_gain_table_p = playback_gain_table;
+
+ table_num = PLAYBACK_GAIN_NUM;
+
+ switch (device) {
+ case PLAYBACK_RCV:
+ gain_set_bits |= PLAYBACK_RCV;
+ break;
+ case PLAYBACK_SPK:
+ gain_set_bits |= PLAYBACK_SPK;
+ break;
+ case PLAYBACK_HP:
+ gain_set_bits |= PLAYBACK_HP;
+ break;
+ case PLAYBACK_BT:
+ gain_set_bits |= PLAYBACK_BT;
+ break;
+ case PLAYBACK_SPK_HP:
+ gain_set_bits |= PLAYBACK_SPK_HP;
+ break;
+ case PLAYBACK_RING_SPK:
+ gain_set_bits |= (PLAYBACK_SPK | PLAYBACK_RING_SPK);
+ break;
+ case PLAYBACK_RING_HP:
+ gain_set_bits |= (PLAYBACK_HP | PLAYBACK_RING_HP);
+ break;
+ case PLAYBACK_RING_SPK_HP:
+ gain_set_bits |= (PLAYBACK_SPK_HP |
+ PLAYBACK_RING_SPK_HP);
+ break;
+ case PLAYBACK_HP_NO_MIC:
+ gain_set_bits |= PLAYBACK_HP_NO_MIC;
+ break;
+ default:
+ pr_err("playback modo gain flag is wrong\n");
+ break;
+ }
+ } else if (mode == VOICECALL_MODE) {
+ if (herring_is_cdma_wimax_dev())
+ default_gain_table_p = cdma_voicecall_gain_table;
+ else
+ default_gain_table_p = voicecall_gain_table;
+ table_num = VOICECALL_GAIN_NUM;
+
+ switch (device) {
+ case VOICECALL_RCV:
+ gain_set_bits |= VOICECALL_RCV;
+ break;
+ case VOICECALL_SPK:
+ gain_set_bits |= VOICECALL_SPK;
+ break;
+ case VOICECALL_HP:
+ gain_set_bits |= VOICECALL_HP;
+ break;
+ case VOICECALL_HP_NO_MIC:
+ gain_set_bits |= VOICECALL_HP_NO_MIC;
+ break;
+ case VOICECALL_BT:
+ gain_set_bits |= VOICECALL_BT;
+ break;
+ case VOICECALL_TTY_VCO:
+ gain_set_bits |= (VOICECALL_HP_NO_MIC | VOICECALL_TTY_VCO);
+ break;
+ case VOICECALL_TTY_HCO:
+ gain_set_bits |= (VOICECALL_RCV | VOICECALL_TTY_HCO);
+ break;
+ case VOICECALL_TTY_FULL:
+ gain_set_bits |= (VOICECALL_HP | VOICECALL_TTY_FULL);
+ break;
+ default:
+ pr_err("voicemode gain flag is wrong\n");
+ }
+ } else if (mode == RECORDING_MODE) {
+ default_gain_table_p = recording_gain_table;
+ table_num = RECORDING_GAIN_NUM;
+
+ switch (device) {
+ case RECORDING_MAIN:
+ gain_set_bits |= RECORDING_MAIN;
+ break;
+ case RECORDING_HP:
+ gain_set_bits |= RECORDING_HP;
+ break;
+ case RECORDING_BT:
+ gain_set_bits |= RECORDING_BT;
+ break;
+ case RECORDING_REC_MAIN:
+ gain_set_bits |= RECORDING_REC_MAIN;
+ break;
+ case RECORDING_REC_HP:
+ gain_set_bits |= RECORDING_REC_HP;
+ break;
+ case RECORDING_REC_BT:
+ gain_set_bits |= RECORDING_REC_BT;
+ break;
+ case RECORDING_CAM_MAIN:
+ gain_set_bits |= RECORDING_CAM_MAIN;
+ break;
+ case RECORDING_CAM_HP:
+ gain_set_bits |= RECORDING_CAM_HP;
+ break;
+ case RECORDING_CAM_BT:
+ gain_set_bits |= RECORDING_CAM_BT;
+ break;
+ case RECORDING_VC_MAIN:
+ gain_set_bits |= RECORDING_VC_MAIN;
+ break;
+ case RECORDING_VC_HP:
+ gain_set_bits |= RECORDING_VC_HP;
+ break;
+ case RECORDING_VC_BT:
+ gain_set_bits |= RECORDING_VC_BT;
+ break;
+ default:
+ pr_err("recording gain flag is wrong\n");
+ }
+
+ }
+
+ DEBUG_LOG("Set gain mode = 0x%x, device = 0x%x, gain_bits = 0x%x,\
+ table_num=%d, gain_code = %d\n",
+ mode, device, gain_set_bits, table_num, wm8994->gain_code);
+
+ /* default gain table setting */
+ for (i = 0; i < table_num; i++) {
+ if ((default_gain_table_p + i)->mode & gain_set_bits) {
+ val = wm8994_read(codec, (default_gain_table_p + i)->reg);
+ val &= ~((default_gain_table_p + i)->mask);
+ val |= (default_gain_table_p + i)->gain;
+ wm8994_write(codec, (default_gain_table_p + i)->reg, val);
+ }
+ }
+
+ if (wm8994->gain_code) {
+ gain_set_bits &= ~(COMMON_SET_BIT);
+
+ switch (wm8994->gain_code) {
+ case 1:
+ gain_set_bits |= (mode | GAIN_DIVISION_BIT_1);
+ break;
+ case 2:
+ gain_set_bits |= (mode | GAIN_DIVISION_BIT_2);
+ break;
+ case 3:
+ /* eur and eur tft device are same gain values currently
+ * but gain code is different because of modem.
+ */
+ gain_set_bits |= (mode | GAIN_DIVISION_BIT_1);
+ break;
+ default:
+ DEBUG_LOG_ERR("gain_code(%d) isn't support", wm8994->gain_code);
+ return 0;
+ }
+
+ default_gain_table_p = gain_code_table;
+ table_num = GAIN_CODE_NUM;
+
+ for (i = 0; i < table_num; i++) {
+ if ((default_gain_table_p + i)->mode == gain_set_bits) {
+ val = wm8994_read(codec, (default_gain_table_p + i)->reg);
+ val &= ~((default_gain_table_p + i)->mask);
+ val |= (default_gain_table_p + i)->gain;
+ wm8994_write(codec, (default_gain_table_p + i)->reg, val);
+ }
+ }
+
+ }
+ return 0;
+
+}
+
diff --git a/sound/soc/codecs/wm8994_samsung.c b/sound/soc/codecs/wm8994_samsung.c
new file mode 100755
index 0000000..4b646e0
--- /dev/null
+++ b/sound/soc/codecs/wm8994_samsung.c
@@ -0,0 +1,3219 @@
+/*
+ * wm8994_samsung.c -- WM8994 ALSA Soc Audio driver
+ *
+ * Copyright 2010 Wolfson Microelectronics PLC.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Notes:
+ * The WM8994 is a multichannel codec with S/PDIF support, featuring six
+ * DAC channels and two ADC channels.
+ *
+ * Currently only the primary audio interface is supported - S/PDIF and
+ * the secondary audio interfaces are not.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+#include <sound/initval.h>
+#include <asm/div64.h>
+#include <linux/io.h>
+#include <plat/map-base.h>
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <mach/regs-clock.h>
+#include "wm8994_samsung.h"
+#include "../../../arch/arm/mach-s5pv210/herring.h"
+#ifdef CONFIG_SND_VOODOO
+#include "wm8994_voodoo.h"
+#endif
+
+#define WM8994_VERSION "0.1"
+#define SUBJECT "wm8994_samsung.c"
+
+#if defined(CONFIG_VIDEO_TV20) && defined(CONFIG_SND_S5P_WM8994_MASTER)
+#define HDMI_USE_AUDIO
+#endif
+
+//extern const u16 wm8994_reg_defaults[WM8994_CACHE_SIZE];
+
+/*
+ *Definitions of clock related.
+*/
+
+static struct {
+ int ratio;
+ int clk_sys_rate;
+} clk_sys_rates[] = {
+ { 64, 0 },
+ { 128, 1 },
+ { 192, 2 },
+ { 256, 3 },
+ { 384, 4 },
+ { 512, 5 },
+ { 768, 6 },
+ { 1024, 7 },
+ { 1408, 8 },
+ { 1536, 9 },
+};
+
+static struct {
+ int rate;
+ int sample_rate;
+} sample_rates[] = {
+ { 8000, 0 },
+ { 11025, 1 },
+ { 12000, 2 },
+ { 16000, 3 },
+ { 22050, 4 },
+ { 24000, 5 },
+ { 32000, 6 },
+ { 44100, 7 },
+ { 48000, 8 },
+ { 88200, 9 },
+ { 96000, 10 },
+};
+
+static struct {
+ int div;
+ int bclk_div;
+} bclk_divs[] = {
+ { 1, 0 },
+ { 2, 1 },
+ { 4, 2 },
+ { 6, 3 },
+ { 8, 4 },
+ { 12, 5 },
+ { 16, 6 },
+ { 24, 7 },
+ { 32, 8 },
+ { 48, 9 },
+};
+
+//struct snd_soc_dai wm8994_dai;
+//EXPORT_SYMBOL_GPL(wm8994_dai);
+
+//struct snd_soc_codec_device soc_codec_dev_pcm_wm8994;
+//EXPORT_SYMBOL_GPL(soc_codec_dev_pcm_wm8994);
+
+//struct snd_soc_codec_device soc_codec_dev_wm8994;
+//EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
+
+/*
+ * Definitions of sound path
+ */
+select_route universal_wm8994_playback_paths[] = {
+ wm8994_disable_path, wm8994_set_playback_receiver,
+ wm8994_set_playback_speaker, wm8994_set_playback_headset,
+ wm8994_set_playback_headset, wm8994_set_playback_bluetooth,
+ wm8994_set_playback_speaker_headset
+};
+
+select_route universal_wm8994_voicecall_paths[] = {
+ wm8994_disable_path, wm8994_set_voicecall_receiver,
+ wm8994_set_voicecall_speaker, wm8994_set_voicecall_headset,
+ wm8994_set_voicecall_headphone, wm8994_set_voicecall_bluetooth,
+ wm8994_set_voicecall_tty_vco, wm8994_set_voicecall_tty_hco,
+ wm8994_set_voicecall_tty_full,
+};
+
+select_mic_route universal_wm8994_mic_paths[] = {
+ wm8994_record_main_mic,
+ wm8994_record_headset_mic,
+ wm8994_record_bluetooth,
+};
+
+select_clock_control universal_clock_controls = wm8994_configure_clock;
+
+int gain_code;
+
+/*
+ * Implementation of I2C functions
+ */
+static unsigned int wm8994_read_hw(struct snd_soc_codec *codec, u16 reg)
+{
+ struct i2c_msg xfer[2];
+ u16 data;
+ int ret;
+ struct i2c_client *i2c = codec->control_data;
+
+ data = ((reg & 0xff00) >> 8) | ((reg & 0xff) << 8);
+
+ xfer[0].addr = i2c->addr;
+ xfer[0].flags = 0;
+ xfer[0].len = 2;
+ xfer[0].buf = (void *)&data;
+
+ xfer[1].addr = i2c->addr;
+ xfer[1].flags = I2C_M_RD;
+ xfer[1].len = 2;
+ xfer[1].buf = (u8 *)&data;
+ ret = i2c_transfer(i2c->adapter, xfer, 2);
+ if (ret != 2) {
+ dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret);
+ return 0;
+ }
+
+ return (data >> 8) | ((data & 0xff) << 8);
+}
+
+int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
+{
+ u8 data[4];
+ int ret;
+
+#ifdef CONFIG_SND_VOODOO
+ value = voodoo_hook_wm8994_write(codec, reg, value);
+#endif
+
+ /* data is
+ * D15..D9 WM8993 register offset
+ * D8...D0 register data
+ */
+ data[0] = (reg & 0xff00) >> 8;
+ data[1] = reg & 0x00ff;
+ data[2] = value >> 8;
+ data[3] = value & 0x00ff;
+ ret = codec->hw_write(codec->control_data, data, 4);
+
+ if (ret == 4)
+ return 0;
+ else {
+ pr_err("i2c write problem occured\n");
+ return ret;
+ }
+}
+
+unsigned int wm8994_read(struct snd_soc_codec *codec, unsigned int reg)
+{
+ return wm8994_read_hw(codec, reg);
+}
+
+static int wm8994_ldo_control(struct wm8994_platform_data *pdata, int en)
+{
+
+ if (!pdata) {
+ pr_err("failed to control wm8994 ldo\n");
+ return -EINVAL;
+ }
+
+ gpio_set_value(pdata->ldo, en);
+
+ if (en)
+ msleep(10);
+ else
+ msleep(125);
+
+ return 0;
+
+}
+
+/*
+ * Functions related volume.
+ */
+static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
+
+static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int ret;
+ u16 val;
+
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ int reg = mc->reg;
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ DEBUG_LOG("");
+
+ ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
+ if (ret < 0)
+ return ret;
+
+ /* Volume changes in the headphone path mean we need to
+ * recallibrate DC servo */
+ if (strcmp(kcontrol->id.name, "Playback Spkr Volume") == 0 ||
+ strcmp(kcontrol->id.name, "Playback Volume") == 0)
+ memset(wm8994->dc_servo, 0, sizeof(wm8994->dc_servo));
+
+ val = wm8994_read(codec, reg);
+
+ return wm8994_write(codec, reg, val | 0x0100);
+}
+
+static int wm899x_inpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kcontrol->private_value;
+ int reg = mc->reg;
+ int ret;
+ u16 val;
+
+ ret = snd_soc_put_volsw(kcontrol, ucontrol);
+
+ if (ret < 0)
+ return ret;
+
+ val = wm8994_read(codec, reg);
+
+ return wm8994_write(codec, reg, val | 0x0100);
+
+}
+
+/*
+ * Implementation of sound path
+ */
+#define MAX_PLAYBACK_PATHS 10
+#define MAX_VOICECALL_PATH 8
+static const char *playback_path[] = {
+ "OFF", "RCV", "SPK", "HP", "HP_NO_MIC", "BT", "SPK_HP",
+ "RING_SPK", "RING_HP", "RING_NO_MIC", "RING_SPK_HP"
+};
+static const char *voicecall_path[] = { "OFF", "RCV", "SPK", "HP",
+ "HP_NO_MIC", "BT", "TTY_VCO",
+ "TTY_HCO", "TTY_FULL"};
+static const char *mic_path[] = { "Main Mic", "Hands Free Mic",
+ "BT Sco Mic", "MIC OFF" };
+static const char *input_source_state[] = { "Default", "Voice Recognition",
+ "Camcorder", "Voice Communication"};
+
+static int wm8994_get_mic_path(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = wm8994->rec_path;
+
+ return 0;
+}
+
+static int wm8994_set_mic_path(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ DEBUG_LOG("");
+
+ wm8994->codec_state |= CAPTURE_ACTIVE;
+
+ switch (ucontrol->value.integer.value[0]) {
+ case 0:
+ wm8994->rec_path = MAIN;
+ break;
+ case 1:
+ wm8994->rec_path = SUB;
+ break;
+ case 2:
+ wm8994->rec_path = BT_REC;
+ break;
+ case 3:
+ wm8994_disable_rec_path(codec);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+
+ wm8994->universal_mic_path[wm8994->rec_path] (codec);
+
+ return 0;
+}
+
+static int wm8994_get_path(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = wm8994->cur_path;
+
+ return 0;
+}
+
+static int wm8994_set_path(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+ struct soc_enum *mc = (struct soc_enum *)kcontrol->private_value;
+ int val;
+ int path_num = ucontrol->value.integer.value[0];
+
+ if (strcmp(mc->texts[path_num], playback_path[path_num])) {
+ DEBUG_LOG_ERR("Unknown path %s\n", mc->texts[path_num]);
+ return -ENODEV;
+ }
+
+ if (path_num > MAX_PLAYBACK_PATHS) {
+ DEBUG_LOG_ERR("Unknown Path\n");
+ return -ENODEV;
+ }
+
+ switch (path_num) {
+ case OFF:
+ DEBUG_LOG("Switching off output path\n");
+ break;
+ case RCV:
+ case SPK:
+ case HP:
+ case HP_NO_MIC:
+ case BT:
+ case SPK_HP:
+ DEBUG_LOG("routing to %s\n", mc->texts[path_num]);
+ wm8994->ringtone_active = RING_OFF;
+ break;
+ case RING_SPK:
+ case RING_HP:
+ case RING_NO_MIC:
+ DEBUG_LOG("routing to %s\n", mc->texts[path_num]);
+ wm8994->ringtone_active = RING_ON;
+ path_num -= 5;
+ break;
+ case RING_SPK_HP:
+ DEBUG_LOG("routing to %s\n", mc->texts[path_num]);
+ wm8994->ringtone_active = RING_ON;
+ path_num -= 4;
+ break;
+ default:
+ DEBUG_LOG_ERR("audio path[%d] does not exists!!\n", path_num);
+ return -ENODEV;
+ break;
+ }
+
+ wm8994->codec_state |= PLAYBACK_ACTIVE;
+
+ if (wm8994->codec_state & CALL_ACTIVE) {
+ wm8994->codec_state &= ~(CALL_ACTIVE);
+
+ val = wm8994_read(codec, WM8994_CLOCKING_1);
+ val &= ~(WM8994_DSP_FS2CLK_ENA_MASK | WM8994_SYSCLK_SRC_MASK);
+ wm8994_write(codec, WM8994_CLOCKING_1, val);
+ }
+
+ wm8994->cur_path = path_num;
+ wm8994->universal_playback_path[wm8994->cur_path] (codec);
+
+ return 0;
+}
+
+static int wm8994_get_voice_path(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = wm8994->cur_path;
+
+ return 0;
+}
+
+static int wm8994_set_voice_path(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+ struct soc_enum *mc = (struct soc_enum *)kcontrol->private_value;
+
+ int path_num = ucontrol->value.integer.value[0];
+
+ if (strcmp(mc->texts[path_num], voicecall_path[path_num])) {
+ DEBUG_LOG_ERR("Unknown path %s\n", mc->texts[path_num]);
+ return -ENODEV;
+ }
+
+ switch (path_num) {
+ case CALL_OFF:
+ DEBUG_LOG("Switching off output path\n");
+ break;
+ case CALL_RCV:
+ case CALL_SPK:
+ case CALL_HP:
+ case CALL_HP_NO_MIC:
+ case CALL_BT:
+ case CALL_TTY_VCO:
+ case CALL_TTY_HCO:
+ case CALL_TTY_FULL:
+ DEBUG_LOG("routing voice path to %s\n", mc->texts[path_num]);
+ break;
+ default:
+ DEBUG_LOG_ERR("path[%d] does not exists!\n", path_num);
+ return -ENODEV;
+ break;
+ }
+
+ if (wm8994->cur_path != path_num ||
+ !(wm8994->codec_state & CALL_ACTIVE)) {
+ wm8994->codec_state |= CALL_ACTIVE;
+ wm8994->cur_path = path_num;
+ wm8994->universal_voicecall_path[wm8994->cur_path] (codec);
+ } else {
+ int val;
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK);
+ val |= (WM8994_AIF1DAC1_UNMUTE);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+ }
+
+ return 0;
+}
+
+static int wm8994_get_input_source(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ DEBUG_LOG("input_source_state = [%d]", wm8994->input_source);
+
+ return wm8994->input_source;
+}
+
+static int wm8994_set_input_source(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ int control_flag = ucontrol->value.integer.value[0];
+
+ DEBUG_LOG("Changed input_source state [%d] => [%d]",
+ wm8994->input_source, control_flag);
+
+ wm8994->input_source = control_flag;
+
+ return 0;
+}
+
+#define SOC_WM899X_OUTPGA_DOUBLE_R_TLV(xname, reg_left, reg_right,\
+ xshift, xmax, xinvert, tlv_array) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
+ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+ SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+ .tlv.p = (tlv_array), \
+ .info = snd_soc_info_volsw_2r, \
+ .get = snd_soc_get_volsw_2r, .put = wm899x_outpga_put_volsw_vu, \
+ .private_value = (unsigned long)&(struct soc_mixer_control) \
+ {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
+ .max = xmax, .invert = xinvert} }
+
+#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
+ tlv_array) {\
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+ SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+ .tlv.p = (tlv_array), \
+ .info = snd_soc_info_volsw, \
+ .get = snd_soc_get_volsw, .put = wm899x_inpga_put_volsw_vu, \
+ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
+
+static const DECLARE_TLV_DB_SCALE(digital_tlv, -7162, 37, 1);
+static const DECLARE_TLV_DB_LINEAR(digital_tlv_spkr, -5700, 600);
+static const DECLARE_TLV_DB_LINEAR(digital_tlv_rcv, -5700, 600);
+static const DECLARE_TLV_DB_LINEAR(digital_tlv_headphone, -5700, 600);
+static const DECLARE_TLV_DB_LINEAR(digital_tlv_mic, -7162, 7162);
+
+static const struct soc_enum path_control_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(playback_path), playback_path),
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(voicecall_path), voicecall_path),
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mic_path), mic_path),
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(input_source_state), input_source_state),
+};
+
+static const struct snd_kcontrol_new wm8994_snd_controls[] = {
+ SOC_WM899X_OUTPGA_DOUBLE_R_TLV("Playback Volume",
+ WM8994_LEFT_OPGA_VOLUME,
+ WM8994_RIGHT_OPGA_VOLUME, 0, 0x3F, 0,
+ digital_tlv_rcv),
+ SOC_WM899X_OUTPGA_DOUBLE_R_TLV("Playback Spkr Volume",
+ WM8994_SPEAKER_VOLUME_LEFT,
+ WM8994_SPEAKER_VOLUME_RIGHT, 1, 0x3F, 0,
+ digital_tlv_spkr),
+ SOC_WM899X_OUTPGA_DOUBLE_R_TLV("Playback Headset Volume",
+ WM8994_LEFT_OUTPUT_VOLUME,
+ WM8994_RIGHT_OUTPUT_VOLUME, 1, 0x3F, 0,
+ digital_tlv_headphone),
+ SOC_WM899X_OUTPGA_SINGLE_R_TLV("Capture Volume",
+ WM8994_AIF1_ADC1_LEFT_VOLUME,
+ 0, 0xEF, 0, digital_tlv_mic),
+ /* Path Control */
+ SOC_ENUM_EXT("Playback Path", path_control_enum[0],
+ wm8994_get_path, wm8994_set_path),
+
+ SOC_ENUM_EXT("Voice Call Path", path_control_enum[1],
+ wm8994_get_voice_path, wm8994_set_voice_path),
+
+ SOC_ENUM_EXT("Capture MIC Path", path_control_enum[2],
+ wm8994_get_mic_path, wm8994_set_mic_path),
+
+#if defined USE_INFINIEON_EC_FOR_VT
+ SOC_ENUM_EXT("Clock Control", clock_control_enum[0],
+ s3c_pcmdev_get_clock, s3c_pcmdev_set_clock),
+#endif
+ SOC_ENUM_EXT("Input Source", path_control_enum[3],
+ wm8994_get_input_source, wm8994_set_input_source),
+
+};
+
+/* Add non-DAPM controls */
+static int wm8994_add_controls(struct snd_soc_codec *codec)
+{
+ return snd_soc_add_controls(codec, wm8994_snd_controls,
+ ARRAY_SIZE(wm8994_snd_controls));
+}
+static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+};
+
+static int wm8994_add_widgets(struct snd_soc_codec *codec)
+{
+ snd_soc_dapm_new_controls(&codec->dapm, wm8994_dapm_widgets,
+ ARRAY_SIZE(wm8994_dapm_widgets));
+
+ snd_soc_dapm_add_routes(&codec->dapm, audio_map, ARRAY_SIZE(audio_map));
+
+ snd_soc_dapm_new_widgets(&codec->dapm);
+ return 0;
+}
+
+static int configure_clock(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+ unsigned int reg;
+
+ DEBUG_LOG("");
+
+ if (wm8994->codec_state != DEACTIVE) {
+ DEBUG_LOG("Codec is already actvied. Skip clock setting.");
+ return 0;
+ }
+
+ reg = wm8994_read(codec, WM8994_AIF1_CLOCKING_1);
+ reg &= ~WM8994_AIF1CLK_ENA;
+ reg &= ~WM8994_AIF1CLK_SRC_MASK;
+ wm8994_write(codec, WM8994_AIF1_CLOCKING_1, reg);
+
+ switch (wm8994->sysclk_source) {
+ case WM8994_SYSCLK_MCLK:
+ dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8994->mclk_rate);
+
+ reg = wm8994_read(codec, WM8994_AIF1_CLOCKING_1);
+ reg &= ~WM8994_AIF1CLK_ENA;
+ wm8994_write(codec, WM8994_AIF1_CLOCKING_1, reg);
+
+ reg = wm8994_read(codec, WM8994_AIF1_CLOCKING_1);
+ reg &= 0x07;
+
+ if (wm8994->mclk_rate > 13500000) {
+ reg |= WM8994_AIF1CLK_DIV;
+ wm8994->sysclk_rate = wm8994->mclk_rate / 2;
+ } else {
+ reg &= ~WM8994_AIF1CLK_DIV;
+ wm8994->sysclk_rate = wm8994->mclk_rate;
+ }
+ reg |= WM8994_AIF1CLK_ENA;
+ wm8994_write(codec, WM8994_AIF1_CLOCKING_1, reg);
+
+ /* Enable clocks to the Audio core and sysclk of wm8994 */
+ reg = wm8994_read(codec, WM8994_CLOCKING_1);
+ reg &= ~(WM8994_SYSCLK_SRC_MASK | WM8994_DSP_FSINTCLK_ENA_MASK
+ | WM8994_DSP_FS1CLK_ENA_MASK);
+ reg |= (WM8994_DSP_FS1CLK_ENA | WM8994_DSP_FSINTCLK_ENA);
+ wm8994_write(codec, WM8994_CLOCKING_1, reg);
+ break;
+
+ case WM8994_SYSCLK_FLL:
+ switch (wm8994->fs) {
+ case 8000:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x2F00);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0x3126);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 11025:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x1F00);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0x86C2);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x00e0);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 12000:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x1F00);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0x3126);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 16000:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x1900);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0xE23E);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 22050:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x0F00);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0x86C2);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x00E0);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 24000:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x0F00);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0x3126);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 32000:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x0C00);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0xE23E);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 44100:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x0700);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0x86C2);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x00E0);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ case 48000:
+ wm8994_write(codec, WM8994_FLL1_CONTROL_2, 0x0700);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_3, 0x3126);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_5, 0x0C88);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, 0x0100);
+ wm8994_write(codec, WM8994_FLL1_CONTROL_1,
+ WM8994_FLL1_FRACN_ENA | WM8994_FLL1_ENA);
+ break;
+
+ default:
+ DEBUG_LOG_ERR("Unsupported Frequency\n");
+ break;
+ }
+
+ reg = wm8994_read(codec, WM8994_AIF1_CLOCKING_1);
+ reg |= WM8994_AIF1CLK_ENA;
+ reg |= WM8994_AIF1CLK_SRC_FLL1;
+ wm8994_write(codec, WM8994_AIF1_CLOCKING_1, reg);
+
+ /* Enable clocks to the Audio core and sysclk of wm8994*/
+ reg = wm8994_read(codec, WM8994_CLOCKING_1);
+ reg &= ~(WM8994_SYSCLK_SRC_MASK | WM8994_DSP_FSINTCLK_ENA_MASK |
+ WM8994_DSP_FS1CLK_ENA_MASK);
+ reg |= (WM8994_DSP_FS1CLK_ENA | WM8994_DSP_FSINTCLK_ENA);
+ wm8994_write(codec, WM8994_CLOCKING_1, reg);
+ break;
+
+ default:
+ dev_err(codec->dev, "System clock not configured\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8994->sysclk_rate);
+
+ return 0;
+}
+
+static int wm8994_set_bias_level(struct snd_soc_codec *codec,
+ enum snd_soc_bias_level level)
+{
+ DEBUG_LOG("");
+
+ switch (level) {
+ case SND_SOC_BIAS_ON:
+ case SND_SOC_BIAS_PREPARE:
+ /* VMID=2*40k */
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_MASK, 0x2);
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
+ WM8994_TSHUT_ENA, WM8994_TSHUT_ENA);
+ break;
+
+ case SND_SOC_BIAS_STANDBY:
+ if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+ /* Bring up VMID with fast soft start */
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
+ WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ WM8994_VMID_RAMP_MASK |
+ WM8994_BIAS_SRC,
+ WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ WM8994_VMID_RAMP_MASK |
+ WM8994_BIAS_SRC);
+ /* VMID=2*40k */
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_MASK |
+ WM8994_BIAS_ENA,
+ WM8994_BIAS_ENA | 0x2);
+
+ /* Switch to normal bias */
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
+ WM8994_BIAS_SRC |
+ WM8994_STARTUP_BIAS_ENA, 0);
+ }
+
+ /* VMID=2*240k */
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_MASK, 0x4);
+
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
+ WM8994_TSHUT_ENA, 0);
+ break;
+
+ case SND_SOC_BIAS_OFF:
+ snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
+ WM8994_LINEOUT_VMID_BUF_ENA, 0);
+
+ snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA, 0);
+ break;
+ }
+
+ codec->dapm.bias_level = level;
+
+ return 0;
+}
+
+static int wm8994_set_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ DEBUG_LOG("clk_id =%d ", clk_id);
+
+ switch (clk_id) {
+ case WM8994_SYSCLK_MCLK:
+ wm8994->mclk_rate = freq;
+ wm8994->sysclk_source = clk_id;
+ break;
+ case WM8994_SYSCLK_FLL:
+ wm8994->sysclk_rate = freq;
+ wm8994->sysclk_source = clk_id;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ unsigned int aif1 = wm8994_read(codec, WM8994_AIF1_CONTROL_1);
+ unsigned int aif2 = wm8994_read(codec, WM8994_AIF1_MASTER_SLAVE);
+
+ DEBUG_LOG("");
+
+ aif1 &= ~(WM8994_AIF1_LRCLK_INV | WM8994_AIF1_BCLK_INV |
+ WM8994_AIF1_WL_MASK | WM8994_AIF1_FMT_MASK);
+
+ aif2 &= ~(WM8994_AIF1_LRCLK_FRC_MASK |
+ WM8994_AIF1_CLK_FRC | WM8994_AIF1_MSTR);
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ wm8994->master = 0;
+ break;
+ case SND_SOC_DAIFMT_CBS_CFM:
+ aif2 |= (WM8994_AIF1_MSTR | WM8994_AIF1_LRCLK_FRC);
+ wm8994->master = 1;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFS:
+ aif2 |= (WM8994_AIF1_MSTR | WM8994_AIF1_CLK_FRC);
+ wm8994->master = 1;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ aif2 |= (WM8994_AIF1_MSTR | WM8994_AIF1_CLK_FRC |
+ WM8994_AIF1_LRCLK_FRC);
+ wm8994->master = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_B:
+ aif1 |= WM8994_AIF1_LRCLK_INV;
+ case SND_SOC_DAIFMT_DSP_A:
+ aif1 |= 0x18;
+ break;
+ case SND_SOC_DAIFMT_I2S:
+ aif1 |= 0x10;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ aif1 |= 0x8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ aif1 |= WM8994_AIF1_BCLK_INV;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ case SND_SOC_DAIFMT_LEFT_J:
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ aif1 |= WM8994_AIF1_BCLK_INV;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ aif1 |= WM8994_AIF1_LRCLK_INV;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ aif1 |= 0x4000;
+ wm8994_write(codec, WM8994_AIF1_CONTROL_1, aif1);
+ wm8994_write(codec, WM8994_AIF1_MASTER_SLAVE, aif2);
+ wm8994_write(codec, WM8994_AIF1_CONTROL_2, 0x4000);
+
+ return 0;
+}
+
+static int wm8994_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+ int ret, i, best, best_val, cur_val;
+ unsigned int clocking1, clocking3, aif1, aif4, aif5;
+
+ DEBUG_LOG("");
+
+ clocking1 = wm8994_read(codec, WM8994_AIF1_BCLK);
+ clocking1 &= ~WM8994_AIF1_BCLK_DIV_MASK;
+
+ clocking3 = wm8994_read(codec, WM8994_AIF1_RATE);
+ clocking3 &= ~(WM8994_AIF1_SR_MASK | WM8994_AIF1CLK_RATE_MASK);
+
+ aif1 = wm8994_read(codec, WM8994_AIF1_CONTROL_1);
+ aif1 &= ~WM8994_AIF1_WL_MASK;
+ aif4 = wm8994_read(codec, WM8994_AIF1ADC_LRCLK);
+ aif4 &= ~WM8994_AIF1ADC_LRCLK_DIR;
+ aif5 = wm8994_read(codec, WM8994_AIF1DAC_LRCLK);
+ aif5 &= ~WM8994_AIF1DAC_LRCLK_DIR_MASK;
+
+ wm8994->fs = params_rate(params);
+ wm8994->bclk = 2 * wm8994->fs;
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ wm8994->bclk *= 16;
+ break;
+
+ case SNDRV_PCM_FORMAT_S20_3LE:
+ wm8994->bclk *= 20;
+ aif1 |= (0x01 << WM8994_AIF1_WL_SHIFT);
+ break;
+
+ case SNDRV_PCM_FORMAT_S24_LE:
+ wm8994->bclk *= 24;
+ aif1 |= (0x10 << WM8994_AIF1_WL_SHIFT);
+ break;
+
+ case SNDRV_PCM_FORMAT_S32_LE:
+ wm8994->bclk *= 32;
+ aif1 |= (0x11 << WM8994_AIF1_WL_SHIFT);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ ret = configure_clock(codec);
+ if (ret != 0)
+ return ret;
+
+ dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8994->bclk);
+
+ /* Select nearest CLK_SYS_RATE */
+ if (wm8994->fs == 8000)
+ best = 3;
+ else {
+ best = 0;
+ best_val = abs((wm8994->sysclk_rate / clk_sys_rates[0].ratio)
+ - wm8994->fs);
+
+ for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
+ cur_val = abs((wm8994->sysclk_rate /
+ clk_sys_rates[i].ratio) - wm8994->fs);
+
+ if (cur_val < best_val) {
+ best = i;
+ best_val = cur_val;
+ }
+ }
+ dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
+ clk_sys_rates[best].ratio);
+ }
+
+ clocking3 |= (clk_sys_rates[best].clk_sys_rate
+ << WM8994_AIF1CLK_RATE_SHIFT);
+
+ /* Sampling rate */
+ best = 0;
+ best_val = abs(wm8994->fs - sample_rates[0].rate);
+ for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
+ cur_val = abs(wm8994->fs - sample_rates[i].rate);
+ if (cur_val < best_val) {
+ best = i;
+ best_val = cur_val;
+ }
+ }
+ dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
+ sample_rates[best].rate);
+
+ clocking3 |= (sample_rates[best].sample_rate << WM8994_AIF1_SR_SHIFT);
+
+ /* BCLK_DIV */
+ best = 0;
+ best_val = INT_MAX;
+ for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+ cur_val = ((wm8994->sysclk_rate) / bclk_divs[i].div)
+ - wm8994->bclk;
+ if (cur_val < 0)
+ break;
+ if (cur_val < best_val) {
+ best = i;
+ best_val = cur_val;
+ }
+ }
+ wm8994->bclk = (wm8994->sysclk_rate) / bclk_divs[best].div;
+
+ dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
+ bclk_divs[best].div, wm8994->bclk);
+
+ clocking1 |= bclk_divs[best].bclk_div << WM8994_AIF1_BCLK_DIV_SHIFT;
+
+ /* LRCLK is a simple fraction of BCLK */
+ dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8994->bclk / wm8994->fs);
+
+ aif4 |= wm8994->bclk / wm8994->fs;
+ aif5 |= wm8994->bclk / wm8994->fs;
+
+#ifdef HDMI_USE_AUDIO
+ /* set bclk to 32fs for 44.1kHz 16 bit playback.*/
+ if (wm8994->fs == 44100)
+ wm8994_write(codec, WM8994_AIF1_BCLK, 0x70);
+#endif
+
+ wm8994_write(codec, WM8994_AIF1_RATE, clocking3);
+ wm8994_write(codec, WM8994_AIF1_CONTROL_1, aif1);
+
+ return 0;
+}
+
+static int wm8994_digital_mute(struct snd_soc_dai *codec_dai, int mute)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ int mute_reg;
+ int reg;
+
+ switch (codec_dai->id) {
+ case 1:
+ mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
+ break;
+ case 2:
+ mute_reg = WM8994_AIF2_DAC_FILTERS_1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mute)
+ reg = WM8994_AIF1DAC1_MUTE;
+ else
+ reg = 0;
+
+ snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
+
+ return 0;
+}
+
+static int wm8994_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *codec_dai)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ wm8994->stream_state |= PCM_STREAM_PLAYBACK;
+ else
+ wm8994->stream_state |= PCM_STREAM_CAPTURE;
+
+
+ if (wm8994->power_state == CODEC_OFF) {
+ wm8994->power_state = CODEC_ON;
+ DEBUG_LOG("Turn on codec!! Power state =[%d]",
+ wm8994->power_state);
+
+ /* For initialize codec */
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1,
+ 0x3 << WM8994_VMID_SEL_SHIFT | WM8994_BIAS_ENA);
+ msleep(50);
+ wm8994_write(codec, WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_NORMAL | WM8994_BIAS_ENA);
+ wm8994_write(codec, WM8994_OVERSAMPLING, 0x0000);
+ } else
+ DEBUG_LOG("Already turned on codec!!");
+
+ return 0;
+}
+
+static void wm8994_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *codec_dai)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ DEBUG_LOG("Stream_state = [0x%X], Codec State = [0x%X]",
+ wm8994->stream_state, wm8994->codec_state);
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ wm8994->stream_state &= ~(PCM_STREAM_CAPTURE);
+ wm8994->codec_state &= ~(CAPTURE_ACTIVE);
+ } else {
+ wm8994->codec_state &= ~(PLAYBACK_ACTIVE);
+ wm8994->stream_state &= ~(PCM_STREAM_PLAYBACK);
+ }
+
+ if ((wm8994->codec_state == DEACTIVE) &&
+ (wm8994->stream_state == PCM_STREAM_DEACTIVE)) {
+ DEBUG_LOG("Turn off Codec!!");
+ wm8994->pdata->set_mic_bias(false);
+ wm8994->power_state = CODEC_OFF;
+ wm8994->cur_path = OFF;
+ wm8994->rec_path = MIC_OFF;
+ wm8994->ringtone_active = RING_OFF;
+ wm8994_write(codec, WM8994_SOFTWARE_RESET, 0x0000);
+ return;
+ }
+
+ DEBUG_LOG("Preserve codec state = [0x%X], Stream State = [0x%X]",
+ wm8994->codec_state, wm8994->stream_state);
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ wm8994_disable_rec_path(codec);
+ wm8994->codec_state &= ~(CAPTURE_ACTIVE);
+ } else {
+ if (wm8994->codec_state & CALL_ACTIVE) {
+ int val;
+
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_1);
+ val &= ~(WM8994_AIF1DAC1_MUTE_MASK);
+ val |= (WM8994_AIF1DAC1_MUTE);
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val);
+ } else
+ wm8994_disable_path(codec);
+ }
+}
+
+//static struct snd_soc_device *wm8994_socdev;
+static struct snd_soc_codec *wm8994_codec;
+
+#define WM8994_RATES SNDRV_PCM_RATE_44100
+#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+static struct snd_soc_dai_ops wm8994_ops = {
+ .startup = wm8994_startup,
+ .shutdown = wm8994_shutdown,
+ .set_sysclk = wm8994_set_sysclk,
+ .set_fmt = wm8994_set_dai_fmt,
+ .hw_params = wm8994_hw_params,
+ .digital_mute = NULL,
+};
+
+struct snd_soc_dai_driver wm8994_dai[] = {
+ {
+ .name = "WM8994 PAIFRX",
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 1,
+ .channels_max = 6,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = WM8994_RATES,
+ .formats = WM8994_FORMATS,
+ },
+ .ops = &wm8994_ops,
+ },
+};
+
+/* gain_code range : integer 0~3 */
+static int is_valid_gain_code(char *str)
+{
+ if ((*str >= 0x30) && (*str <= 0x33))
+ return 1;
+ else {
+ DEBUG_LOG_ERR("gain code is invalid (%d)", *str);
+ return 0;
+ }
+}
+
+static int __init gain_code_setup(char *str)
+{
+
+ gain_code = 0;
+
+ if (!strcmp(str, "")) {
+ pr_info("gain_code field is empty. use default value\n");
+ return 0;
+ }
+
+ if (is_valid_gain_code(str)) {
+ gain_code = *str - 0x30;
+ DEBUG_LOG("gain_code : %d", gain_code);
+ } else
+ DEBUG_LOG_ERR("gain code is invalid and so use default value");
+
+ return 0;
+}
+__setup("gain_code=", gain_code_setup);
+
+int gain_code_check(void)
+{
+ return gain_code;
+}
+
+static const struct {
+ unsigned short readable; /* Mask of readable bits */
+ unsigned short writable; /* Mask of writable bits */
+} access_masks[] = {
+ { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */
+ { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */
+ { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */
+ { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */
+ { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */
+ { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */
+ { 0x003F, 0x003F }, /* R6 - Power Management (6) */
+ { 0x0000, 0x0000 }, /* R7 */
+ { 0x0000, 0x0000 }, /* R8 */
+ { 0x0000, 0x0000 }, /* R9 */
+ { 0x0000, 0x0000 }, /* R10 */
+ { 0x0000, 0x0000 }, /* R11 */
+ { 0x0000, 0x0000 }, /* R12 */
+ { 0x0000, 0x0000 }, /* R13 */
+ { 0x0000, 0x0000 }, /* R14 */
+ { 0x0000, 0x0000 }, /* R15 */
+ { 0x0000, 0x0000 }, /* R16 */
+ { 0x0000, 0x0000 }, /* R17 */
+ { 0x0000, 0x0000 }, /* R18 */
+ { 0x0000, 0x0000 }, /* R19 */
+ { 0x0000, 0x0000 }, /* R20 */
+ { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */
+ { 0x0000, 0x0000 }, /* R22 */
+ { 0x0000, 0x0000 }, /* R23 */
+ { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */
+ { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */
+ { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */
+ { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */
+ { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */
+ { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */
+ { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */
+ { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */
+ { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */
+ { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */
+ { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */
+ { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */
+ { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */
+ { 0x003F, 0x003F }, /* R37 - ClassD */
+ { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */
+ { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */
+ { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */
+ { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */
+ { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */
+ { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */
+ { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */
+ { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */
+ { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */
+ { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */
+ { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */
+ { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */
+ { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */
+ { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */
+ { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */
+ { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */
+ { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */
+ { 0x00C1, 0x00C1 }, /* R55 - Additional Control */
+ { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */
+ { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */
+ { 0x00FF, 0x00FF }, /* R58 - MICBIAS */
+ { 0x000F, 0x000F }, /* R59 - LDO 1 */
+ { 0x0007, 0x0007 }, /* R60 - LDO 2 */
+ { 0x0000, 0x0000 }, /* R61 */
+ { 0x0000, 0x0000 }, /* R62 */
+ { 0x0000, 0x0000 }, /* R63 */
+ { 0x0000, 0x0000 }, /* R64 */
+ { 0x0000, 0x0000 }, /* R65 */
+ { 0x0000, 0x0000 }, /* R66 */
+ { 0x0000, 0x0000 }, /* R67 */
+ { 0x0000, 0x0000 }, /* R68 */
+ { 0x0000, 0x0000 }, /* R69 */
+ { 0x0000, 0x0000 }, /* R70 */
+ { 0x0000, 0x0000 }, /* R71 */
+ { 0x0000, 0x0000 }, /* R72 */
+ { 0x0000, 0x0000 }, /* R73 */
+ { 0x0000, 0x0000 }, /* R74 */
+ { 0x0000, 0x0000 }, /* R75 */
+ { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */
+ { 0x0000, 0x0000 }, /* R77 */
+ { 0x0000, 0x0000 }, /* R78 */
+ { 0x0000, 0x0000 }, /* R79 */
+ { 0x0000, 0x0000 }, /* R80 */
+ { 0x0301, 0x0301 }, /* R81 - Class W (1) */
+ { 0x0000, 0x0000 }, /* R82 */
+ { 0x0000, 0x0000 }, /* R83 */
+ { 0x333F, 0x333F }, /* R84 - DC Servo (1) */
+ { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */
+ { 0x0000, 0x0000 }, /* R86 */
+ { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */
+ { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */
+ { 0x0000, 0x0000 }, /* R89 */
+ { 0x0000, 0x0000 }, /* R90 */
+ { 0x0000, 0x0000 }, /* R91 */
+ { 0x0000, 0x0000 }, /* R92 */
+ { 0x0000, 0x0000 }, /* R93 */
+ { 0x0000, 0x0000 }, /* R94 */
+ { 0x0000, 0x0000 }, /* R95 */
+ { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */
+ { 0x0000, 0x0000 }, /* R97 */
+ { 0x0000, 0x0000 }, /* R98 */
+ { 0x0000, 0x0000 }, /* R99 */
+ { 0x0000, 0x0000 }, /* R100 */
+ { 0x0000, 0x0000 }, /* R101 */
+ { 0x0000, 0x0000 }, /* R102 */
+ { 0x0000, 0x0000 }, /* R103 */
+ { 0x0000, 0x0000 }, /* R104 */
+ { 0x0000, 0x0000 }, /* R105 */
+ { 0x0000, 0x0000 }, /* R106 */
+ { 0x0000, 0x0000 }, /* R107 */
+ { 0x0000, 0x0000 }, /* R108 */
+ { 0x0000, 0x0000 }, /* R109 */
+ { 0x0000, 0x0000 }, /* R110 */
+ { 0x0000, 0x0000 }, /* R111 */
+ { 0x0000, 0x0000 }, /* R112 */
+ { 0x0000, 0x0000 }, /* R113 */
+ { 0x0000, 0x0000 }, /* R114 */
+ { 0x0000, 0x0000 }, /* R115 */
+ { 0x0000, 0x0000 }, /* R116 */
+ { 0x0000, 0x0000 }, /* R117 */
+ { 0x0000, 0x0000 }, /* R118 */
+ { 0x0000, 0x0000 }, /* R119 */
+ { 0x0000, 0x0000 }, /* R120 */
+ { 0x0000, 0x0000 }, /* R121 */
+ { 0x0000, 0x0000 }, /* R122 */
+ { 0x0000, 0x0000 }, /* R123 */
+ { 0x0000, 0x0000 }, /* R124 */
+ { 0x0000, 0x0000 }, /* R125 */
+ { 0x0000, 0x0000 }, /* R126 */
+ { 0x0000, 0x0000 }, /* R127 */
+ { 0x0000, 0x0000 }, /* R128 */
+ { 0x0000, 0x0000 }, /* R129 */
+ { 0x0000, 0x0000 }, /* R130 */
+ { 0x0000, 0x0000 }, /* R131 */
+ { 0x0000, 0x0000 }, /* R132 */
+ { 0x0000, 0x0000 }, /* R133 */
+ { 0x0000, 0x0000 }, /* R134 */
+ { 0x0000, 0x0000 }, /* R135 */
+ { 0x0000, 0x0000 }, /* R136 */
+ { 0x0000, 0x0000 }, /* R137 */
+ { 0x0000, 0x0000 }, /* R138 */
+ { 0x0000, 0x0000 }, /* R139 */
+ { 0x0000, 0x0000 }, /* R140 */
+ { 0x0000, 0x0000 }, /* R141 */
+ { 0x0000, 0x0000 }, /* R142 */
+ { 0x0000, 0x0000 }, /* R143 */
+ { 0x0000, 0x0000 }, /* R144 */
+ { 0x0000, 0x0000 }, /* R145 */
+ { 0x0000, 0x0000 }, /* R146 */
+ { 0x0000, 0x0000 }, /* R147 */
+ { 0x0000, 0x0000 }, /* R148 */
+ { 0x0000, 0x0000 }, /* R149 */
+ { 0x0000, 0x0000 }, /* R150 */
+ { 0x0000, 0x0000 }, /* R151 */
+ { 0x0000, 0x0000 }, /* R152 */
+ { 0x0000, 0x0000 }, /* R153 */
+ { 0x0000, 0x0000 }, /* R154 */
+ { 0x0000, 0x0000 }, /* R155 */
+ { 0x0000, 0x0000 }, /* R156 */
+ { 0x0000, 0x0000 }, /* R157 */
+ { 0x0000, 0x0000 }, /* R158 */
+ { 0x0000, 0x0000 }, /* R159 */
+ { 0x0000, 0x0000 }, /* R160 */
+ { 0x0000, 0x0000 }, /* R161 */
+ { 0x0000, 0x0000 }, /* R162 */
+ { 0x0000, 0x0000 }, /* R163 */
+ { 0x0000, 0x0000 }, /* R164 */
+ { 0x0000, 0x0000 }, /* R165 */
+ { 0x0000, 0x0000 }, /* R166 */
+ { 0x0000, 0x0000 }, /* R167 */
+ { 0x0000, 0x0000 }, /* R168 */
+ { 0x0000, 0x0000 }, /* R169 */
+ { 0x0000, 0x0000 }, /* R170 */
+ { 0x0000, 0x0000 }, /* R171 */
+ { 0x0000, 0x0000 }, /* R172 */
+ { 0x0000, 0x0000 }, /* R173 */
+ { 0x0000, 0x0000 }, /* R174 */
+ { 0x0000, 0x0000 }, /* R175 */
+ { 0x0000, 0x0000 }, /* R176 */
+ { 0x0000, 0x0000 }, /* R177 */
+ { 0x0000, 0x0000 }, /* R178 */
+ { 0x0000, 0x0000 }, /* R179 */
+ { 0x0000, 0x0000 }, /* R180 */
+ { 0x0000, 0x0000 }, /* R181 */
+ { 0x0000, 0x0000 }, /* R182 */
+ { 0x0000, 0x0000 }, /* R183 */
+ { 0x0000, 0x0000 }, /* R184 */
+ { 0x0000, 0x0000 }, /* R185 */
+ { 0x0000, 0x0000 }, /* R186 */
+ { 0x0000, 0x0000 }, /* R187 */
+ { 0x0000, 0x0000 }, /* R188 */
+ { 0x0000, 0x0000 }, /* R189 */
+ { 0x0000, 0x0000 }, /* R190 */
+ { 0x0000, 0x0000 }, /* R191 */
+ { 0x0000, 0x0000 }, /* R192 */
+ { 0x0000, 0x0000 }, /* R193 */
+ { 0x0000, 0x0000 }, /* R194 */
+ { 0x0000, 0x0000 }, /* R195 */
+ { 0x0000, 0x0000 }, /* R196 */
+ { 0x0000, 0x0000 }, /* R197 */
+ { 0x0000, 0x0000 }, /* R198 */
+ { 0x0000, 0x0000 }, /* R199 */
+ { 0x0000, 0x0000 }, /* R200 */
+ { 0x0000, 0x0000 }, /* R201 */
+ { 0x0000, 0x0000 }, /* R202 */
+ { 0x0000, 0x0000 }, /* R203 */
+ { 0x0000, 0x0000 }, /* R204 */
+ { 0x0000, 0x0000 }, /* R205 */
+ { 0x0000, 0x0000 }, /* R206 */
+ { 0x0000, 0x0000 }, /* R207 */
+ { 0x0000, 0x0000 }, /* R208 */
+ { 0x0000, 0x0000 }, /* R209 */
+ { 0x0000, 0x0000 }, /* R210 */
+ { 0x0000, 0x0000 }, /* R211 */
+ { 0x0000, 0x0000 }, /* R212 */
+ { 0x0000, 0x0000 }, /* R213 */
+ { 0x0000, 0x0000 }, /* R214 */
+ { 0x0000, 0x0000 }, /* R215 */
+ { 0x0000, 0x0000 }, /* R216 */
+ { 0x0000, 0x0000 }, /* R217 */
+ { 0x0000, 0x0000 }, /* R218 */
+ { 0x0000, 0x0000 }, /* R219 */
+ { 0x0000, 0x0000 }, /* R220 */
+ { 0x0000, 0x0000 }, /* R221 */
+ { 0x0000, 0x0000 }, /* R222 */
+ { 0x0000, 0x0000 }, /* R223 */
+ { 0x0000, 0x0000 }, /* R224 */
+ { 0x0000, 0x0000 }, /* R225 */
+ { 0x0000, 0x0000 }, /* R226 */
+ { 0x0000, 0x0000 }, /* R227 */
+ { 0x0000, 0x0000 }, /* R228 */
+ { 0x0000, 0x0000 }, /* R229 */
+ { 0x0000, 0x0000 }, /* R230 */
+ { 0x0000, 0x0000 }, /* R231 */
+ { 0x0000, 0x0000 }, /* R232 */
+ { 0x0000, 0x0000 }, /* R233 */
+ { 0x0000, 0x0000 }, /* R234 */
+ { 0x0000, 0x0000 }, /* R235 */
+ { 0x0000, 0x0000 }, /* R236 */
+ { 0x0000, 0x0000 }, /* R237 */
+ { 0x0000, 0x0000 }, /* R238 */
+ { 0x0000, 0x0000 }, /* R239 */
+ { 0x0000, 0x0000 }, /* R240 */
+ { 0x0000, 0x0000 }, /* R241 */
+ { 0x0000, 0x0000 }, /* R242 */
+ { 0x0000, 0x0000 }, /* R243 */
+ { 0x0000, 0x0000 }, /* R244 */
+ { 0x0000, 0x0000 }, /* R245 */
+ { 0x0000, 0x0000 }, /* R246 */
+ { 0x0000, 0x0000 }, /* R247 */
+ { 0x0000, 0x0000 }, /* R248 */
+ { 0x0000, 0x0000 }, /* R249 */
+ { 0x0000, 0x0000 }, /* R250 */
+ { 0x0000, 0x0000 }, /* R251 */
+ { 0x0000, 0x0000 }, /* R252 */
+ { 0x0000, 0x0000 }, /* R253 */
+ { 0x0000, 0x0000 }, /* R254 */
+ { 0x0000, 0x0000 }, /* R255 */
+ { 0x000F, 0x0000 }, /* R256 - Chip Revision */
+ { 0x0074, 0x0074 }, /* R257 - Control Interface */
+ { 0x0000, 0x0000 }, /* R258 */
+ { 0x0000, 0x0000 }, /* R259 */
+ { 0x0000, 0x0000 }, /* R260 */
+ { 0x0000, 0x0000 }, /* R261 */
+ { 0x0000, 0x0000 }, /* R262 */
+ { 0x0000, 0x0000 }, /* R263 */
+ { 0x0000, 0x0000 }, /* R264 */
+ { 0x0000, 0x0000 }, /* R265 */
+ { 0x0000, 0x0000 }, /* R266 */
+ { 0x0000, 0x0000 }, /* R267 */
+ { 0x0000, 0x0000 }, /* R268 */
+ { 0x0000, 0x0000 }, /* R269 */
+ { 0x0000, 0x0000 }, /* R270 */
+ { 0x0000, 0x0000 }, /* R271 */
+ { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */
+ { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
+ { 0x0000, 0x0000 }, /* R274 */
+ { 0x0000, 0x0000 }, /* R275 */
+ { 0x0000, 0x0000 }, /* R276 */
+ { 0x0000, 0x0000 }, /* R277 */
+ { 0x0000, 0x0000 }, /* R278 */
+ { 0x0000, 0x0000 }, /* R279 */
+ { 0x0000, 0x0000 }, /* R280 */
+ { 0x0000, 0x0000 }, /* R281 */
+ { 0x0000, 0x0000 }, /* R282 */
+ { 0x0000, 0x0000 }, /* R283 */
+ { 0x0000, 0x0000 }, /* R284 */
+ { 0x0000, 0x0000 }, /* R285 */
+ { 0x0000, 0x0000 }, /* R286 */
+ { 0x0000, 0x0000 }, /* R287 */
+ { 0x0000, 0x0000 }, /* R288 */
+ { 0x0000, 0x0000 }, /* R289 */
+ { 0x0000, 0x0000 }, /* R290 */
+ { 0x0000, 0x0000 }, /* R291 */
+ { 0x0000, 0x0000 }, /* R292 */
+ { 0x0000, 0x0000 }, /* R293 */
+ { 0x0000, 0x0000 }, /* R294 */
+ { 0x0000, 0x0000 }, /* R295 */
+ { 0x0000, 0x0000 }, /* R296 */
+ { 0x0000, 0x0000 }, /* R297 */
+ { 0x0000, 0x0000 }, /* R298 */
+ { 0x0000, 0x0000 }, /* R299 */
+ { 0x0000, 0x0000 }, /* R300 */
+ { 0x0000, 0x0000 }, /* R301 */
+ { 0x0000, 0x0000 }, /* R302 */
+ { 0x0000, 0x0000 }, /* R303 */
+ { 0x0000, 0x0000 }, /* R304 */
+ { 0x0000, 0x0000 }, /* R305 */
+ { 0x0000, 0x0000 }, /* R306 */
+ { 0x0000, 0x0000 }, /* R307 */
+ { 0x0000, 0x0000 }, /* R308 */
+ { 0x0000, 0x0000 }, /* R309 */
+ { 0x0000, 0x0000 }, /* R310 */
+ { 0x0000, 0x0000 }, /* R311 */
+ { 0x0000, 0x0000 }, /* R312 */
+ { 0x0000, 0x0000 }, /* R313 */
+ { 0x0000, 0x0000 }, /* R314 */
+ { 0x0000, 0x0000 }, /* R315 */
+ { 0x0000, 0x0000 }, /* R316 */
+ { 0x0000, 0x0000 }, /* R317 */
+ { 0x0000, 0x0000 }, /* R318 */
+ { 0x0000, 0x0000 }, /* R319 */
+ { 0x0000, 0x0000 }, /* R320 */
+ { 0x0000, 0x0000 }, /* R321 */
+ { 0x0000, 0x0000 }, /* R322 */
+ { 0x0000, 0x0000 }, /* R323 */
+ { 0x0000, 0x0000 }, /* R324 */
+ { 0x0000, 0x0000 }, /* R325 */
+ { 0x0000, 0x0000 }, /* R326 */
+ { 0x0000, 0x0000 }, /* R327 */
+ { 0x0000, 0x0000 }, /* R328 */
+ { 0x0000, 0x0000 }, /* R329 */
+ { 0x0000, 0x0000 }, /* R330 */
+ { 0x0000, 0x0000 }, /* R331 */
+ { 0x0000, 0x0000 }, /* R332 */
+ { 0x0000, 0x0000 }, /* R333 */
+ { 0x0000, 0x0000 }, /* R334 */
+ { 0x0000, 0x0000 }, /* R335 */
+ { 0x0000, 0x0000 }, /* R336 */
+ { 0x0000, 0x0000 }, /* R337 */
+ { 0x0000, 0x0000 }, /* R338 */
+ { 0x0000, 0x0000 }, /* R339 */
+ { 0x0000, 0x0000 }, /* R340 */
+ { 0x0000, 0x0000 }, /* R341 */
+ { 0x0000, 0x0000 }, /* R342 */
+ { 0x0000, 0x0000 }, /* R343 */
+ { 0x0000, 0x0000 }, /* R344 */
+ { 0x0000, 0x0000 }, /* R345 */
+ { 0x0000, 0x0000 }, /* R346 */
+ { 0x0000, 0x0000 }, /* R347 */
+ { 0x0000, 0x0000 }, /* R348 */
+ { 0x0000, 0x0000 }, /* R349 */
+ { 0x0000, 0x0000 }, /* R350 */
+ { 0x0000, 0x0000 }, /* R351 */
+ { 0x0000, 0x0000 }, /* R352 */
+ { 0x0000, 0x0000 }, /* R353 */
+ { 0x0000, 0x0000 }, /* R354 */
+ { 0x0000, 0x0000 }, /* R355 */
+ { 0x0000, 0x0000 }, /* R356 */
+ { 0x0000, 0x0000 }, /* R357 */
+ { 0x0000, 0x0000 }, /* R358 */
+ { 0x0000, 0x0000 }, /* R359 */
+ { 0x0000, 0x0000 }, /* R360 */
+ { 0x0000, 0x0000 }, /* R361 */
+ { 0x0000, 0x0000 }, /* R362 */
+ { 0x0000, 0x0000 }, /* R363 */
+ { 0x0000, 0x0000 }, /* R364 */
+ { 0x0000, 0x0000 }, /* R365 */
+ { 0x0000, 0x0000 }, /* R366 */
+ { 0x0000, 0x0000 }, /* R367 */
+ { 0x0000, 0x0000 }, /* R368 */
+ { 0x0000, 0x0000 }, /* R369 */
+ { 0x0000, 0x0000 }, /* R370 */
+ { 0x0000, 0x0000 }, /* R371 */
+ { 0x0000, 0x0000 }, /* R372 */
+ { 0x0000, 0x0000 }, /* R373 */
+ { 0x0000, 0x0000 }, /* R374 */
+ { 0x0000, 0x0000 }, /* R375 */
+ { 0x0000, 0x0000 }, /* R376 */
+ { 0x0000, 0x0000 }, /* R377 */
+ { 0x0000, 0x0000 }, /* R378 */
+ { 0x0000, 0x0000 }, /* R379 */
+ { 0x0000, 0x0000 }, /* R380 */
+ { 0x0000, 0x0000 }, /* R381 */
+ { 0x0000, 0x0000 }, /* R382 */
+ { 0x0000, 0x0000 }, /* R383 */
+ { 0x0000, 0x0000 }, /* R384 */
+ { 0x0000, 0x0000 }, /* R385 */
+ { 0x0000, 0x0000 }, /* R386 */
+ { 0x0000, 0x0000 }, /* R387 */
+ { 0x0000, 0x0000 }, /* R388 */
+ { 0x0000, 0x0000 }, /* R389 */
+ { 0x0000, 0x0000 }, /* R390 */
+ { 0x0000, 0x0000 }, /* R391 */
+ { 0x0000, 0x0000 }, /* R392 */
+ { 0x0000, 0x0000 }, /* R393 */
+ { 0x0000, 0x0000 }, /* R394 */
+ { 0x0000, 0x0000 }, /* R395 */
+ { 0x0000, 0x0000 }, /* R396 */
+ { 0x0000, 0x0000 }, /* R397 */
+ { 0x0000, 0x0000 }, /* R398 */
+ { 0x0000, 0x0000 }, /* R399 */
+ { 0x0000, 0x0000 }, /* R400 */
+ { 0x0000, 0x0000 }, /* R401 */
+ { 0x0000, 0x0000 }, /* R402 */
+ { 0x0000, 0x0000 }, /* R403 */
+ { 0x0000, 0x0000 }, /* R404 */
+ { 0x0000, 0x0000 }, /* R405 */
+ { 0x0000, 0x0000 }, /* R406 */
+ { 0x0000, 0x0000 }, /* R407 */
+ { 0x0000, 0x0000 }, /* R408 */
+ { 0x0000, 0x0000 }, /* R409 */
+ { 0x0000, 0x0000 }, /* R410 */
+ { 0x0000, 0x0000 }, /* R411 */
+ { 0x0000, 0x0000 }, /* R412 */
+ { 0x0000, 0x0000 }, /* R413 */
+ { 0x0000, 0x0000 }, /* R414 */
+ { 0x0000, 0x0000 }, /* R415 */
+ { 0x0000, 0x0000 }, /* R416 */
+ { 0x0000, 0x0000 }, /* R417 */
+ { 0x0000, 0x0000 }, /* R418 */
+ { 0x0000, 0x0000 }, /* R419 */
+ { 0x0000, 0x0000 }, /* R420 */
+ { 0x0000, 0x0000 }, /* R421 */
+ { 0x0000, 0x0000 }, /* R422 */
+ { 0x0000, 0x0000 }, /* R423 */
+ { 0x0000, 0x0000 }, /* R424 */
+ { 0x0000, 0x0000 }, /* R425 */
+ { 0x0000, 0x0000 }, /* R426 */
+ { 0x0000, 0x0000 }, /* R427 */
+ { 0x0000, 0x0000 }, /* R428 */
+ { 0x0000, 0x0000 }, /* R429 */
+ { 0x0000, 0x0000 }, /* R430 */
+ { 0x0000, 0x0000 }, /* R431 */
+ { 0x0000, 0x0000 }, /* R432 */
+ { 0x0000, 0x0000 }, /* R433 */
+ { 0x0000, 0x0000 }, /* R434 */
+ { 0x0000, 0x0000 }, /* R435 */
+ { 0x0000, 0x0000 }, /* R436 */
+ { 0x0000, 0x0000 }, /* R437 */
+ { 0x0000, 0x0000 }, /* R438 */
+ { 0x0000, 0x0000 }, /* R439 */
+ { 0x0000, 0x0000 }, /* R440 */
+ { 0x0000, 0x0000 }, /* R441 */
+ { 0x0000, 0x0000 }, /* R442 */
+ { 0x0000, 0x0000 }, /* R443 */
+ { 0x0000, 0x0000 }, /* R444 */
+ { 0x0000, 0x0000 }, /* R445 */
+ { 0x0000, 0x0000 }, /* R446 */
+ { 0x0000, 0x0000 }, /* R447 */
+ { 0x0000, 0x0000 }, /* R448 */
+ { 0x0000, 0x0000 }, /* R449 */
+ { 0x0000, 0x0000 }, /* R450 */
+ { 0x0000, 0x0000 }, /* R451 */
+ { 0x0000, 0x0000 }, /* R452 */
+ { 0x0000, 0x0000 }, /* R453 */
+ { 0x0000, 0x0000 }, /* R454 */
+ { 0x0000, 0x0000 }, /* R455 */
+ { 0x0000, 0x0000 }, /* R456 */
+ { 0x0000, 0x0000 }, /* R457 */
+ { 0x0000, 0x0000 }, /* R458 */
+ { 0x0000, 0x0000 }, /* R459 */
+ { 0x0000, 0x0000 }, /* R460 */
+ { 0x0000, 0x0000 }, /* R461 */
+ { 0x0000, 0x0000 }, /* R462 */
+ { 0x0000, 0x0000 }, /* R463 */
+ { 0x0000, 0x0000 }, /* R464 */
+ { 0x0000, 0x0000 }, /* R465 */
+ { 0x0000, 0x0000 }, /* R466 */
+ { 0x0000, 0x0000 }, /* R467 */
+ { 0x0000, 0x0000 }, /* R468 */
+ { 0x0000, 0x0000 }, /* R469 */
+ { 0x0000, 0x0000 }, /* R470 */
+ { 0x0000, 0x0000 }, /* R471 */
+ { 0x0000, 0x0000 }, /* R472 */
+ { 0x0000, 0x0000 }, /* R473 */
+ { 0x0000, 0x0000 }, /* R474 */
+ { 0x0000, 0x0000 }, /* R475 */
+ { 0x0000, 0x0000 }, /* R476 */
+ { 0x0000, 0x0000 }, /* R477 */
+ { 0x0000, 0x0000 }, /* R478 */
+ { 0x0000, 0x0000 }, /* R479 */
+ { 0x0000, 0x0000 }, /* R480 */
+ { 0x0000, 0x0000 }, /* R481 */
+ { 0x0000, 0x0000 }, /* R482 */
+ { 0x0000, 0x0000 }, /* R483 */
+ { 0x0000, 0x0000 }, /* R484 */
+ { 0x0000, 0x0000 }, /* R485 */
+ { 0x0000, 0x0000 }, /* R486 */
+ { 0x0000, 0x0000 }, /* R487 */
+ { 0x0000, 0x0000 }, /* R488 */
+ { 0x0000, 0x0000 }, /* R489 */
+ { 0x0000, 0x0000 }, /* R490 */
+ { 0x0000, 0x0000 }, /* R491 */
+ { 0x0000, 0x0000 }, /* R492 */
+ { 0x0000, 0x0000 }, /* R493 */
+ { 0x0000, 0x0000 }, /* R494 */
+ { 0x0000, 0x0000 }, /* R495 */
+ { 0x0000, 0x0000 }, /* R496 */
+ { 0x0000, 0x0000 }, /* R497 */
+ { 0x0000, 0x0000 }, /* R498 */
+ { 0x0000, 0x0000 }, /* R499 */
+ { 0x0000, 0x0000 }, /* R500 */
+ { 0x0000, 0x0000 }, /* R501 */
+ { 0x0000, 0x0000 }, /* R502 */
+ { 0x0000, 0x0000 }, /* R503 */
+ { 0x0000, 0x0000 }, /* R504 */
+ { 0x0000, 0x0000 }, /* R505 */
+ { 0x0000, 0x0000 }, /* R506 */
+ { 0x0000, 0x0000 }, /* R507 */
+ { 0x0000, 0x0000 }, /* R508 */
+ { 0x0000, 0x0000 }, /* R509 */
+ { 0x0000, 0x0000 }, /* R510 */
+ { 0x0000, 0x0000 }, /* R511 */
+ { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */
+ { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */
+ { 0x0000, 0x0000 }, /* R514 */
+ { 0x0000, 0x0000 }, /* R515 */
+ { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */
+ { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */
+ { 0x0000, 0x0000 }, /* R518 */
+ { 0x0000, 0x0000 }, /* R519 */
+ { 0x001F, 0x001F }, /* R520 - Clocking (1) */
+ { 0x0777, 0x0777 }, /* R521 - Clocking (2) */
+ { 0x0000, 0x0000 }, /* R522 */
+ { 0x0000, 0x0000 }, /* R523 */
+ { 0x0000, 0x0000 }, /* R524 */
+ { 0x0000, 0x0000 }, /* R525 */
+ { 0x0000, 0x0000 }, /* R526 */
+ { 0x0000, 0x0000 }, /* R527 */
+ { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */
+ { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */
+ { 0x000F, 0x0000 }, /* R530 - Rate Status */
+ { 0x0000, 0x0000 }, /* R531 */
+ { 0x0000, 0x0000 }, /* R532 */
+ { 0x0000, 0x0000 }, /* R533 */
+ { 0x0000, 0x0000 }, /* R534 */
+ { 0x0000, 0x0000 }, /* R535 */
+ { 0x0000, 0x0000 }, /* R536 */
+ { 0x0000, 0x0000 }, /* R537 */
+ { 0x0000, 0x0000 }, /* R538 */
+ { 0x0000, 0x0000 }, /* R539 */
+ { 0x0000, 0x0000 }, /* R540 */
+ { 0x0000, 0x0000 }, /* R541 */
+ { 0x0000, 0x0000 }, /* R542 */
+ { 0x0000, 0x0000 }, /* R543 */
+ { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */
+ { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */
+ { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */
+ { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */
+ { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */
+ { 0x0000, 0x0000 }, /* R549 */
+ { 0x0000, 0x0000 }, /* R550 */
+ { 0x0000, 0x0000 }, /* R551 */
+ { 0x0000, 0x0000 }, /* R552 */
+ { 0x0000, 0x0000 }, /* R553 */
+ { 0x0000, 0x0000 }, /* R554 */
+ { 0x0000, 0x0000 }, /* R555 */
+ { 0x0000, 0x0000 }, /* R556 */
+ { 0x0000, 0x0000 }, /* R557 */
+ { 0x0000, 0x0000 }, /* R558 */
+ { 0x0000, 0x0000 }, /* R559 */
+ { 0x0000, 0x0000 }, /* R560 */
+ { 0x0000, 0x0000 }, /* R561 */
+ { 0x0000, 0x0000 }, /* R562 */
+ { 0x0000, 0x0000 }, /* R563 */
+ { 0x0000, 0x0000 }, /* R564 */
+ { 0x0000, 0x0000 }, /* R565 */
+ { 0x0000, 0x0000 }, /* R566 */
+ { 0x0000, 0x0000 }, /* R567 */
+ { 0x0000, 0x0000 }, /* R568 */
+ { 0x0000, 0x0000 }, /* R569 */
+ { 0x0000, 0x0000 }, /* R570 */
+ { 0x0000, 0x0000 }, /* R571 */
+ { 0x0000, 0x0000 }, /* R572 */
+ { 0x0000, 0x0000 }, /* R573 */
+ { 0x0000, 0x0000 }, /* R574 */
+ { 0x0000, 0x0000 }, /* R575 */
+ { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */
+ { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */
+ { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */
+ { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */
+ { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */
+ { 0x0000, 0x0000 }, /* R581 */
+ { 0x0000, 0x0000 }, /* R582 */
+ { 0x0000, 0x0000 }, /* R583 */
+ { 0x0000, 0x0000 }, /* R584 */
+ { 0x0000, 0x0000 }, /* R585 */
+ { 0x0000, 0x0000 }, /* R586 */
+ { 0x0000, 0x0000 }, /* R587 */
+ { 0x0000, 0x0000 }, /* R588 */
+ { 0x0000, 0x0000 }, /* R589 */
+ { 0x0000, 0x0000 }, /* R590 */
+ { 0x0000, 0x0000 }, /* R591 */
+ { 0x0000, 0x0000 }, /* R592 */
+ { 0x0000, 0x0000 }, /* R593 */
+ { 0x0000, 0x0000 }, /* R594 */
+ { 0x0000, 0x0000 }, /* R595 */
+ { 0x0000, 0x0000 }, /* R596 */
+ { 0x0000, 0x0000 }, /* R597 */
+ { 0x0000, 0x0000 }, /* R598 */
+ { 0x0000, 0x0000 }, /* R599 */
+ { 0x0000, 0x0000 }, /* R600 */
+ { 0x0000, 0x0000 }, /* R601 */
+ { 0x0000, 0x0000 }, /* R602 */
+ { 0x0000, 0x0000 }, /* R603 */
+ { 0x0000, 0x0000 }, /* R604 */
+ { 0x0000, 0x0000 }, /* R605 */
+ { 0x0000, 0x0000 }, /* R606 */
+ { 0x0000, 0x0000 }, /* R607 */
+ { 0x0000, 0x0000 }, /* R608 */
+ { 0x0000, 0x0000 }, /* R609 */
+ { 0x0000, 0x0000 }, /* R610 */
+ { 0x0000, 0x0000 }, /* R611 */
+ { 0x0000, 0x0000 }, /* R612 */
+ { 0x0000, 0x0000 }, /* R613 */
+ { 0x0000, 0x0000 }, /* R614 */
+ { 0x0000, 0x0000 }, /* R615 */
+ { 0x0000, 0x0000 }, /* R616 */
+ { 0x0000, 0x0000 }, /* R617 */
+ { 0x0000, 0x0000 }, /* R618 */
+ { 0x0000, 0x0000 }, /* R619 */
+ { 0x0000, 0x0000 }, /* R620 */
+ { 0x0000, 0x0000 }, /* R621 */
+ { 0x0000, 0x0000 }, /* R622 */
+ { 0x0000, 0x0000 }, /* R623 */
+ { 0x0000, 0x0000 }, /* R624 */
+ { 0x0000, 0x0000 }, /* R625 */
+ { 0x0000, 0x0000 }, /* R626 */
+ { 0x0000, 0x0000 }, /* R627 */
+ { 0x0000, 0x0000 }, /* R628 */
+ { 0x0000, 0x0000 }, /* R629 */
+ { 0x0000, 0x0000 }, /* R630 */
+ { 0x0000, 0x0000 }, /* R631 */
+ { 0x0000, 0x0000 }, /* R632 */
+ { 0x0000, 0x0000 }, /* R633 */
+ { 0x0000, 0x0000 }, /* R634 */
+ { 0x0000, 0x0000 }, /* R635 */
+ { 0x0000, 0x0000 }, /* R636 */
+ { 0x0000, 0x0000 }, /* R637 */
+ { 0x0000, 0x0000 }, /* R638 */
+ { 0x0000, 0x0000 }, /* R639 */
+ { 0x0000, 0x0000 }, /* R640 */
+ { 0x0000, 0x0000 }, /* R641 */
+ { 0x0000, 0x0000 }, /* R642 */
+ { 0x0000, 0x0000 }, /* R643 */
+ { 0x0000, 0x0000 }, /* R644 */
+ { 0x0000, 0x0000 }, /* R645 */
+ { 0x0000, 0x0000 }, /* R646 */
+ { 0x0000, 0x0000 }, /* R647 */
+ { 0x0000, 0x0000 }, /* R648 */
+ { 0x0000, 0x0000 }, /* R649 */
+ { 0x0000, 0x0000 }, /* R650 */
+ { 0x0000, 0x0000 }, /* R651 */
+ { 0x0000, 0x0000 }, /* R652 */
+ { 0x0000, 0x0000 }, /* R653 */
+ { 0x0000, 0x0000 }, /* R654 */
+ { 0x0000, 0x0000 }, /* R655 */
+ { 0x0000, 0x0000 }, /* R656 */
+ { 0x0000, 0x0000 }, /* R657 */
+ { 0x0000, 0x0000 }, /* R658 */
+ { 0x0000, 0x0000 }, /* R659 */
+ { 0x0000, 0x0000 }, /* R660 */
+ { 0x0000, 0x0000 }, /* R661 */
+ { 0x0000, 0x0000 }, /* R662 */
+ { 0x0000, 0x0000 }, /* R663 */
+ { 0x0000, 0x0000 }, /* R664 */
+ { 0x0000, 0x0000 }, /* R665 */
+ { 0x0000, 0x0000 }, /* R666 */
+ { 0x0000, 0x0000 }, /* R667 */
+ { 0x0000, 0x0000 }, /* R668 */
+ { 0x0000, 0x0000 }, /* R669 */
+ { 0x0000, 0x0000 }, /* R670 */
+ { 0x0000, 0x0000 }, /* R671 */
+ { 0x0000, 0x0000 }, /* R672 */
+ { 0x0000, 0x0000 }, /* R673 */
+ { 0x0000, 0x0000 }, /* R674 */
+ { 0x0000, 0x0000 }, /* R675 */
+ { 0x0000, 0x0000 }, /* R676 */
+ { 0x0000, 0x0000 }, /* R677 */
+ { 0x0000, 0x0000 }, /* R678 */
+ { 0x0000, 0x0000 }, /* R679 */
+ { 0x0000, 0x0000 }, /* R680 */
+ { 0x0000, 0x0000 }, /* R681 */
+ { 0x0000, 0x0000 }, /* R682 */
+ { 0x0000, 0x0000 }, /* R683 */
+ { 0x0000, 0x0000 }, /* R684 */
+ { 0x0000, 0x0000 }, /* R685 */
+ { 0x0000, 0x0000 }, /* R686 */
+ { 0x0000, 0x0000 }, /* R687 */
+ { 0x0000, 0x0000 }, /* R688 */
+ { 0x0000, 0x0000 }, /* R689 */
+ { 0x0000, 0x0000 }, /* R690 */
+ { 0x0000, 0x0000 }, /* R691 */
+ { 0x0000, 0x0000 }, /* R692 */
+ { 0x0000, 0x0000 }, /* R693 */
+ { 0x0000, 0x0000 }, /* R694 */
+ { 0x0000, 0x0000 }, /* R695 */
+ { 0x0000, 0x0000 }, /* R696 */
+ { 0x0000, 0x0000 }, /* R697 */
+ { 0x0000, 0x0000 }, /* R698 */
+ { 0x0000, 0x0000 }, /* R699 */
+ { 0x0000, 0x0000 }, /* R700 */
+ { 0x0000, 0x0000 }, /* R701 */
+ { 0x0000, 0x0000 }, /* R702 */
+ { 0x0000, 0x0000 }, /* R703 */
+ { 0x0000, 0x0000 }, /* R704 */
+ { 0x0000, 0x0000 }, /* R705 */
+ { 0x0000, 0x0000 }, /* R706 */
+ { 0x0000, 0x0000 }, /* R707 */
+ { 0x0000, 0x0000 }, /* R708 */
+ { 0x0000, 0x0000 }, /* R709 */
+ { 0x0000, 0x0000 }, /* R710 */
+ { 0x0000, 0x0000 }, /* R711 */
+ { 0x0000, 0x0000 }, /* R712 */
+ { 0x0000, 0x0000 }, /* R713 */
+ { 0x0000, 0x0000 }, /* R714 */
+ { 0x0000, 0x0000 }, /* R715 */
+ { 0x0000, 0x0000 }, /* R716 */
+ { 0x0000, 0x0000 }, /* R717 */
+ { 0x0000, 0x0000 }, /* R718 */
+ { 0x0000, 0x0000 }, /* R719 */
+ { 0x0000, 0x0000 }, /* R720 */
+ { 0x0000, 0x0000 }, /* R721 */
+ { 0x0000, 0x0000 }, /* R722 */
+ { 0x0000, 0x0000 }, /* R723 */
+ { 0x0000, 0x0000 }, /* R724 */
+ { 0x0000, 0x0000 }, /* R725 */
+ { 0x0000, 0x0000 }, /* R726 */
+ { 0x0000, 0x0000 }, /* R727 */
+ { 0x0000, 0x0000 }, /* R728 */
+ { 0x0000, 0x0000 }, /* R729 */
+ { 0x0000, 0x0000 }, /* R730 */
+ { 0x0000, 0x0000 }, /* R731 */
+ { 0x0000, 0x0000 }, /* R732 */
+ { 0x0000, 0x0000 }, /* R733 */
+ { 0x0000, 0x0000 }, /* R734 */
+ { 0x0000, 0x0000 }, /* R735 */
+ { 0x0000, 0x0000 }, /* R736 */
+ { 0x0000, 0x0000 }, /* R737 */
+ { 0x0000, 0x0000 }, /* R738 */
+ { 0x0000, 0x0000 }, /* R739 */
+ { 0x0000, 0x0000 }, /* R740 */
+ { 0x0000, 0x0000 }, /* R741 */
+ { 0x0000, 0x0000 }, /* R742 */
+ { 0x0000, 0x0000 }, /* R743 */
+ { 0x0000, 0x0000 }, /* R744 */
+ { 0x0000, 0x0000 }, /* R745 */
+ { 0x0000, 0x0000 }, /* R746 */
+ { 0x0000, 0x0000 }, /* R747 */
+ { 0x0000, 0x0000 }, /* R748 */
+ { 0x0000, 0x0000 }, /* R749 */
+ { 0x0000, 0x0000 }, /* R750 */
+ { 0x0000, 0x0000 }, /* R751 */
+ { 0x0000, 0x0000 }, /* R752 */
+ { 0x0000, 0x0000 }, /* R753 */
+ { 0x0000, 0x0000 }, /* R754 */
+ { 0x0000, 0x0000 }, /* R755 */
+ { 0x0000, 0x0000 }, /* R756 */
+ { 0x0000, 0x0000 }, /* R757 */
+ { 0x0000, 0x0000 }, /* R758 */
+ { 0x0000, 0x0000 }, /* R759 */
+ { 0x0000, 0x0000 }, /* R760 */
+ { 0x0000, 0x0000 }, /* R761 */
+ { 0x0000, 0x0000 }, /* R762 */
+ { 0x0000, 0x0000 }, /* R763 */
+ { 0x0000, 0x0000 }, /* R764 */
+ { 0x0000, 0x0000 }, /* R765 */
+ { 0x0000, 0x0000 }, /* R766 */
+ { 0x0000, 0x0000 }, /* R767 */
+ { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */
+ { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */
+ { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */
+ { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */
+ { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */
+ { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */
+ { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */
+ { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */
+ { 0x0000, 0x0000 }, /* R776 */
+ { 0x0000, 0x0000 }, /* R777 */
+ { 0x0000, 0x0000 }, /* R778 */
+ { 0x0000, 0x0000 }, /* R779 */
+ { 0x0000, 0x0000 }, /* R780 */
+ { 0x0000, 0x0000 }, /* R781 */
+ { 0x0000, 0x0000 }, /* R782 */
+ { 0x0000, 0x0000 }, /* R783 */
+ { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */
+ { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */
+ { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */
+ { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */
+ { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */
+ { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */
+ { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */
+ { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */
+ { 0x0000, 0x0000 }, /* R792 */
+ { 0x0000, 0x0000 }, /* R793 */
+ { 0x0000, 0x0000 }, /* R794 */
+ { 0x0000, 0x0000 }, /* R795 */
+ { 0x0000, 0x0000 }, /* R796 */
+ { 0x0000, 0x0000 }, /* R797 */
+ { 0x0000, 0x0000 }, /* R798 */
+ { 0x0000, 0x0000 }, /* R799 */
+ { 0x0000, 0x0000 }, /* R800 */
+ { 0x0000, 0x0000 }, /* R801 */
+ { 0x0000, 0x0000 }, /* R802 */
+ { 0x0000, 0x0000 }, /* R803 */
+ { 0x0000, 0x0000 }, /* R804 */
+ { 0x0000, 0x0000 }, /* R805 */
+ { 0x0000, 0x0000 }, /* R806 */
+ { 0x0000, 0x0000 }, /* R807 */
+ { 0x0000, 0x0000 }, /* R808 */
+ { 0x0000, 0x0000 }, /* R809 */
+ { 0x0000, 0x0000 }, /* R810 */
+ { 0x0000, 0x0000 }, /* R811 */
+ { 0x0000, 0x0000 }, /* R812 */
+ { 0x0000, 0x0000 }, /* R813 */
+ { 0x0000, 0x0000 }, /* R814 */
+ { 0x0000, 0x0000 }, /* R815 */
+ { 0x0000, 0x0000 }, /* R816 */
+ { 0x0000, 0x0000 }, /* R817 */
+ { 0x0000, 0x0000 }, /* R818 */
+ { 0x0000, 0x0000 }, /* R819 */
+ { 0x0000, 0x0000 }, /* R820 */
+ { 0x0000, 0x0000 }, /* R821 */
+ { 0x0000, 0x0000 }, /* R822 */
+ { 0x0000, 0x0000 }, /* R823 */
+ { 0x0000, 0x0000 }, /* R824 */
+ { 0x0000, 0x0000 }, /* R825 */
+ { 0x0000, 0x0000 }, /* R826 */
+ { 0x0000, 0x0000 }, /* R827 */
+ { 0x0000, 0x0000 }, /* R828 */
+ { 0x0000, 0x0000 }, /* R829 */
+ { 0x0000, 0x0000 }, /* R830 */
+ { 0x0000, 0x0000 }, /* R831 */
+ { 0x0000, 0x0000 }, /* R832 */
+ { 0x0000, 0x0000 }, /* R833 */
+ { 0x0000, 0x0000 }, /* R834 */
+ { 0x0000, 0x0000 }, /* R835 */
+ { 0x0000, 0x0000 }, /* R836 */
+ { 0x0000, 0x0000 }, /* R837 */
+ { 0x0000, 0x0000 }, /* R838 */
+ { 0x0000, 0x0000 }, /* R839 */
+ { 0x0000, 0x0000 }, /* R840 */
+ { 0x0000, 0x0000 }, /* R841 */
+ { 0x0000, 0x0000 }, /* R842 */
+ { 0x0000, 0x0000 }, /* R843 */
+ { 0x0000, 0x0000 }, /* R844 */
+ { 0x0000, 0x0000 }, /* R845 */
+ { 0x0000, 0x0000 }, /* R846 */
+ { 0x0000, 0x0000 }, /* R847 */
+ { 0x0000, 0x0000 }, /* R848 */
+ { 0x0000, 0x0000 }, /* R849 */
+ { 0x0000, 0x0000 }, /* R850 */
+ { 0x0000, 0x0000 }, /* R851 */
+ { 0x0000, 0x0000 }, /* R852 */
+ { 0x0000, 0x0000 }, /* R853 */
+ { 0x0000, 0x0000 }, /* R854 */
+ { 0x0000, 0x0000 }, /* R855 */
+ { 0x0000, 0x0000 }, /* R856 */
+ { 0x0000, 0x0000 }, /* R857 */
+ { 0x0000, 0x0000 }, /* R858 */
+ { 0x0000, 0x0000 }, /* R859 */
+ { 0x0000, 0x0000 }, /* R860 */
+ { 0x0000, 0x0000 }, /* R861 */
+ { 0x0000, 0x0000 }, /* R862 */
+ { 0x0000, 0x0000 }, /* R863 */
+ { 0x0000, 0x0000 }, /* R864 */
+ { 0x0000, 0x0000 }, /* R865 */
+ { 0x0000, 0x0000 }, /* R866 */
+ { 0x0000, 0x0000 }, /* R867 */
+ { 0x0000, 0x0000 }, /* R868 */
+ { 0x0000, 0x0000 }, /* R869 */
+ { 0x0000, 0x0000 }, /* R870 */
+ { 0x0000, 0x0000 }, /* R871 */
+ { 0x0000, 0x0000 }, /* R872 */
+ { 0x0000, 0x0000 }, /* R873 */
+ { 0x0000, 0x0000 }, /* R874 */
+ { 0x0000, 0x0000 }, /* R875 */
+ { 0x0000, 0x0000 }, /* R876 */
+ { 0x0000, 0x0000 }, /* R877 */
+ { 0x0000, 0x0000 }, /* R878 */
+ { 0x0000, 0x0000 }, /* R879 */
+ { 0x0000, 0x0000 }, /* R880 */
+ { 0x0000, 0x0000 }, /* R881 */
+ { 0x0000, 0x0000 }, /* R882 */
+ { 0x0000, 0x0000 }, /* R883 */
+ { 0x0000, 0x0000 }, /* R884 */
+ { 0x0000, 0x0000 }, /* R885 */
+ { 0x0000, 0x0000 }, /* R886 */
+ { 0x0000, 0x0000 }, /* R887 */
+ { 0x0000, 0x0000 }, /* R888 */
+ { 0x0000, 0x0000 }, /* R889 */
+ { 0x0000, 0x0000 }, /* R890 */
+ { 0x0000, 0x0000 }, /* R891 */
+ { 0x0000, 0x0000 }, /* R892 */
+ { 0x0000, 0x0000 }, /* R893 */
+ { 0x0000, 0x0000 }, /* R894 */
+ { 0x0000, 0x0000 }, /* R895 */
+ { 0x0000, 0x0000 }, /* R896 */
+ { 0x0000, 0x0000 }, /* R897 */
+ { 0x0000, 0x0000 }, /* R898 */
+ { 0x0000, 0x0000 }, /* R899 */
+ { 0x0000, 0x0000 }, /* R900 */
+ { 0x0000, 0x0000 }, /* R901 */
+ { 0x0000, 0x0000 }, /* R902 */
+ { 0x0000, 0x0000 }, /* R903 */
+ { 0x0000, 0x0000 }, /* R904 */
+ { 0x0000, 0x0000 }, /* R905 */
+ { 0x0000, 0x0000 }, /* R906 */
+ { 0x0000, 0x0000 }, /* R907 */
+ { 0x0000, 0x0000 }, /* R908 */
+ { 0x0000, 0x0000 }, /* R909 */
+ { 0x0000, 0x0000 }, /* R910 */
+ { 0x0000, 0x0000 }, /* R911 */
+ { 0x0000, 0x0000 }, /* R912 */
+ { 0x0000, 0x0000 }, /* R913 */
+ { 0x0000, 0x0000 }, /* R914 */
+ { 0x0000, 0x0000 }, /* R915 */
+ { 0x0000, 0x0000 }, /* R916 */
+ { 0x0000, 0x0000 }, /* R917 */
+ { 0x0000, 0x0000 }, /* R918 */
+ { 0x0000, 0x0000 }, /* R919 */
+ { 0x0000, 0x0000 }, /* R920 */
+ { 0x0000, 0x0000 }, /* R921 */
+ { 0x0000, 0x0000 }, /* R922 */
+ { 0x0000, 0x0000 }, /* R923 */
+ { 0x0000, 0x0000 }, /* R924 */
+ { 0x0000, 0x0000 }, /* R925 */
+ { 0x0000, 0x0000 }, /* R926 */
+ { 0x0000, 0x0000 }, /* R927 */
+ { 0x0000, 0x0000 }, /* R928 */
+ { 0x0000, 0x0000 }, /* R929 */
+ { 0x0000, 0x0000 }, /* R930 */
+ { 0x0000, 0x0000 }, /* R931 */
+ { 0x0000, 0x0000 }, /* R932 */
+ { 0x0000, 0x0000 }, /* R933 */
+ { 0x0000, 0x0000 }, /* R934 */
+ { 0x0000, 0x0000 }, /* R935 */
+ { 0x0000, 0x0000 }, /* R936 */
+ { 0x0000, 0x0000 }, /* R937 */
+ { 0x0000, 0x0000 }, /* R938 */
+ { 0x0000, 0x0000 }, /* R939 */
+ { 0x0000, 0x0000 }, /* R940 */
+ { 0x0000, 0x0000 }, /* R941 */
+ { 0x0000, 0x0000 }, /* R942 */
+ { 0x0000, 0x0000 }, /* R943 */
+ { 0x0000, 0x0000 }, /* R944 */
+ { 0x0000, 0x0000 }, /* R945 */
+ { 0x0000, 0x0000 }, /* R946 */
+ { 0x0000, 0x0000 }, /* R947 */
+ { 0x0000, 0x0000 }, /* R948 */
+ { 0x0000, 0x0000 }, /* R949 */
+ { 0x0000, 0x0000 }, /* R950 */
+ { 0x0000, 0x0000 }, /* R951 */
+ { 0x0000, 0x0000 }, /* R952 */
+ { 0x0000, 0x0000 }, /* R953 */
+ { 0x0000, 0x0000 }, /* R954 */
+ { 0x0000, 0x0000 }, /* R955 */
+ { 0x0000, 0x0000 }, /* R956 */
+ { 0x0000, 0x0000 }, /* R957 */
+ { 0x0000, 0x0000 }, /* R958 */
+ { 0x0000, 0x0000 }, /* R959 */
+ { 0x0000, 0x0000 }, /* R960 */
+ { 0x0000, 0x0000 }, /* R961 */
+ { 0x0000, 0x0000 }, /* R962 */
+ { 0x0000, 0x0000 }, /* R963 */
+ { 0x0000, 0x0000 }, /* R964 */
+ { 0x0000, 0x0000 }, /* R965 */
+ { 0x0000, 0x0000 }, /* R966 */
+ { 0x0000, 0x0000 }, /* R967 */
+ { 0x0000, 0x0000 }, /* R968 */
+ { 0x0000, 0x0000 }, /* R969 */
+ { 0x0000, 0x0000 }, /* R970 */
+ { 0x0000, 0x0000 }, /* R971 */
+ { 0x0000, 0x0000 }, /* R972 */
+ { 0x0000, 0x0000 }, /* R973 */
+ { 0x0000, 0x0000 }, /* R974 */
+ { 0x0000, 0x0000 }, /* R975 */
+ { 0x0000, 0x0000 }, /* R976 */
+ { 0x0000, 0x0000 }, /* R977 */
+ { 0x0000, 0x0000 }, /* R978 */
+ { 0x0000, 0x0000 }, /* R979 */
+ { 0x0000, 0x0000 }, /* R980 */
+ { 0x0000, 0x0000 }, /* R981 */
+ { 0x0000, 0x0000 }, /* R982 */
+ { 0x0000, 0x0000 }, /* R983 */
+ { 0x0000, 0x0000 }, /* R984 */
+ { 0x0000, 0x0000 }, /* R985 */
+ { 0x0000, 0x0000 }, /* R986 */
+ { 0x0000, 0x0000 }, /* R987 */
+ { 0x0000, 0x0000 }, /* R988 */
+ { 0x0000, 0x0000 }, /* R989 */
+ { 0x0000, 0x0000 }, /* R990 */
+ { 0x0000, 0x0000 }, /* R991 */
+ { 0x0000, 0x0000 }, /* R992 */
+ { 0x0000, 0x0000 }, /* R993 */
+ { 0x0000, 0x0000 }, /* R994 */
+ { 0x0000, 0x0000 }, /* R995 */
+ { 0x0000, 0x0000 }, /* R996 */
+ { 0x0000, 0x0000 }, /* R997 */
+ { 0x0000, 0x0000 }, /* R998 */
+ { 0x0000, 0x0000 }, /* R999 */
+ { 0x0000, 0x0000 }, /* R1000 */
+ { 0x0000, 0x0000 }, /* R1001 */
+ { 0x0000, 0x0000 }, /* R1002 */
+ { 0x0000, 0x0000 }, /* R1003 */
+ { 0x0000, 0x0000 }, /* R1004 */
+ { 0x0000, 0x0000 }, /* R1005 */
+ { 0x0000, 0x0000 }, /* R1006 */
+ { 0x0000, 0x0000 }, /* R1007 */
+ { 0x0000, 0x0000 }, /* R1008 */
+ { 0x0000, 0x0000 }, /* R1009 */
+ { 0x0000, 0x0000 }, /* R1010 */
+ { 0x0000, 0x0000 }, /* R1011 */
+ { 0x0000, 0x0000 }, /* R1012 */
+ { 0x0000, 0x0000 }, /* R1013 */
+ { 0x0000, 0x0000 }, /* R1014 */
+ { 0x0000, 0x0000 }, /* R1015 */
+ { 0x0000, 0x0000 }, /* R1016 */
+ { 0x0000, 0x0000 }, /* R1017 */
+ { 0x0000, 0x0000 }, /* R1018 */
+ { 0x0000, 0x0000 }, /* R1019 */
+ { 0x0000, 0x0000 }, /* R1020 */
+ { 0x0000, 0x0000 }, /* R1021 */
+ { 0x0000, 0x0000 }, /* R1022 */
+ { 0x0000, 0x0000 }, /* R1023 */
+ { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */
+ { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */
+ { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */
+ { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */
+ { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */
+ { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */
+ { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */
+ { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */
+ { 0x0000, 0x0000 }, /* R1032 */
+ { 0x0000, 0x0000 }, /* R1033 */
+ { 0x0000, 0x0000 }, /* R1034 */
+ { 0x0000, 0x0000 }, /* R1035 */
+ { 0x0000, 0x0000 }, /* R1036 */
+ { 0x0000, 0x0000 }, /* R1037 */
+ { 0x0000, 0x0000 }, /* R1038 */
+ { 0x0000, 0x0000 }, /* R1039 */
+ { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */
+ { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */
+ { 0x0000, 0x0000 }, /* R1042 */
+ { 0x0000, 0x0000 }, /* R1043 */
+ { 0x0000, 0x0000 }, /* R1044 */
+ { 0x0000, 0x0000 }, /* R1045 */
+ { 0x0000, 0x0000 }, /* R1046 */
+ { 0x0000, 0x0000 }, /* R1047 */
+ { 0x0000, 0x0000 }, /* R1048 */
+ { 0x0000, 0x0000 }, /* R1049 */
+ { 0x0000, 0x0000 }, /* R1050 */
+ { 0x0000, 0x0000 }, /* R1051 */
+ { 0x0000, 0x0000 }, /* R1052 */
+ { 0x0000, 0x0000 }, /* R1053 */
+ { 0x0000, 0x0000 }, /* R1054 */
+ { 0x0000, 0x0000 }, /* R1055 */
+ { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */
+ { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */
+ { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */
+ { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */
+ { 0x0000, 0x0000 }, /* R1060 */
+ { 0x0000, 0x0000 }, /* R1061 */
+ { 0x0000, 0x0000 }, /* R1062 */
+ { 0x0000, 0x0000 }, /* R1063 */
+ { 0x0000, 0x0000 }, /* R1064 */
+ { 0x0000, 0x0000 }, /* R1065 */
+ { 0x0000, 0x0000 }, /* R1066 */
+ { 0x0000, 0x0000 }, /* R1067 */
+ { 0x0000, 0x0000 }, /* R1068 */
+ { 0x0000, 0x0000 }, /* R1069 */
+ { 0x0000, 0x0000 }, /* R1070 */
+ { 0x0000, 0x0000 }, /* R1071 */
+ { 0x0000, 0x0000 }, /* R1072 */
+ { 0x0000, 0x0000 }, /* R1073 */
+ { 0x0000, 0x0000 }, /* R1074 */
+ { 0x0000, 0x0000 }, /* R1075 */
+ { 0x0000, 0x0000 }, /* R1076 */
+ { 0x0000, 0x0000 }, /* R1077 */
+ { 0x0000, 0x0000 }, /* R1078 */
+ { 0x0000, 0x0000 }, /* R1079 */
+ { 0x0000, 0x0000 }, /* R1080 */
+ { 0x0000, 0x0000 }, /* R1081 */
+ { 0x0000, 0x0000 }, /* R1082 */
+ { 0x0000, 0x0000 }, /* R1083 */
+ { 0x0000, 0x0000 }, /* R1084 */
+ { 0x0000, 0x0000 }, /* R1085 */
+ { 0x0000, 0x0000 }, /* R1086 */
+ { 0x0000, 0x0000 }, /* R1087 */
+ { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */
+ { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */
+ { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */
+ { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */
+ { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */
+ { 0x0000, 0x0000 }, /* R1093 */
+ { 0x0000, 0x0000 }, /* R1094 */
+ { 0x0000, 0x0000 }, /* R1095 */
+ { 0x0000, 0x0000 }, /* R1096 */
+ { 0x0000, 0x0000 }, /* R1097 */
+ { 0x0000, 0x0000 }, /* R1098 */
+ { 0x0000, 0x0000 }, /* R1099 */
+ { 0x0000, 0x0000 }, /* R1100 */
+ { 0x0000, 0x0000 }, /* R1101 */
+ { 0x0000, 0x0000 }, /* R1102 */
+ { 0x0000, 0x0000 }, /* R1103 */
+ { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */
+ { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */
+ { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */
+ { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */
+ { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */
+ { 0x0000, 0x0000 }, /* R1109 */
+ { 0x0000, 0x0000 }, /* R1110 */
+ { 0x0000, 0x0000 }, /* R1111 */
+ { 0x0000, 0x0000 }, /* R1112 */
+ { 0x0000, 0x0000 }, /* R1113 */
+ { 0x0000, 0x0000 }, /* R1114 */
+ { 0x0000, 0x0000 }, /* R1115 */
+ { 0x0000, 0x0000 }, /* R1116 */
+ { 0x0000, 0x0000 }, /* R1117 */
+ { 0x0000, 0x0000 }, /* R1118 */
+ { 0x0000, 0x0000 }, /* R1119 */
+ { 0x0000, 0x0000 }, /* R1120 */
+ { 0x0000, 0x0000 }, /* R1121 */
+ { 0x0000, 0x0000 }, /* R1122 */
+ { 0x0000, 0x0000 }, /* R1123 */
+ { 0x0000, 0x0000 }, /* R1124 */
+ { 0x0000, 0x0000 }, /* R1125 */
+ { 0x0000, 0x0000 }, /* R1126 */
+ { 0x0000, 0x0000 }, /* R1127 */
+ { 0x0000, 0x0000 }, /* R1128 */
+ { 0x0000, 0x0000 }, /* R1129 */
+ { 0x0000, 0x0000 }, /* R1130 */
+ { 0x0000, 0x0000 }, /* R1131 */
+ { 0x0000, 0x0000 }, /* R1132 */
+ { 0x0000, 0x0000 }, /* R1133 */
+ { 0x0000, 0x0000 }, /* R1134 */
+ { 0x0000, 0x0000 }, /* R1135 */
+ { 0x0000, 0x0000 }, /* R1136 */
+ { 0x0000, 0x0000 }, /* R1137 */
+ { 0x0000, 0x0000 }, /* R1138 */
+ { 0x0000, 0x0000 }, /* R1139 */
+ { 0x0000, 0x0000 }, /* R1140 */
+ { 0x0000, 0x0000 }, /* R1141 */
+ { 0x0000, 0x0000 }, /* R1142 */
+ { 0x0000, 0x0000 }, /* R1143 */
+ { 0x0000, 0x0000 }, /* R1144 */
+ { 0x0000, 0x0000 }, /* R1145 */
+ { 0x0000, 0x0000 }, /* R1146 */
+ { 0x0000, 0x0000 }, /* R1147 */
+ { 0x0000, 0x0000 }, /* R1148 */
+ { 0x0000, 0x0000 }, /* R1149 */
+ { 0x0000, 0x0000 }, /* R1150 */
+ { 0x0000, 0x0000 }, /* R1151 */
+ { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
+ { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
+ { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
+ { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
+ { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
+ { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
+ { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
+ { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
+ { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
+ { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
+ { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
+ { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
+ { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
+ { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
+ { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
+ { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
+ { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
+ { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
+ { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
+ { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
+ { 0x0000, 0x0000 }, /* R1172 */
+ { 0x0000, 0x0000 }, /* R1173 */
+ { 0x0000, 0x0000 }, /* R1174 */
+ { 0x0000, 0x0000 }, /* R1175 */
+ { 0x0000, 0x0000 }, /* R1176 */
+ { 0x0000, 0x0000 }, /* R1177 */
+ { 0x0000, 0x0000 }, /* R1178 */
+ { 0x0000, 0x0000 }, /* R1179 */
+ { 0x0000, 0x0000 }, /* R1180 */
+ { 0x0000, 0x0000 }, /* R1181 */
+ { 0x0000, 0x0000 }, /* R1182 */
+ { 0x0000, 0x0000 }, /* R1183 */
+ { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
+ { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
+ { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
+ { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
+ { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
+ { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
+ { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
+ { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
+ { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
+ { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
+ { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
+ { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
+ { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
+ { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
+ { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
+ { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
+ { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
+ { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
+ { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
+ { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
+ { 0x0000, 0x0000 }, /* R1204 */
+ { 0x0000, 0x0000 }, /* R1205 */
+ { 0x0000, 0x0000 }, /* R1206 */
+ { 0x0000, 0x0000 }, /* R1207 */
+ { 0x0000, 0x0000 }, /* R1208 */
+ { 0x0000, 0x0000 }, /* R1209 */
+ { 0x0000, 0x0000 }, /* R1210 */
+ { 0x0000, 0x0000 }, /* R1211 */
+ { 0x0000, 0x0000 }, /* R1212 */
+ { 0x0000, 0x0000 }, /* R1213 */
+ { 0x0000, 0x0000 }, /* R1214 */
+ { 0x0000, 0x0000 }, /* R1215 */
+ { 0x0000, 0x0000 }, /* R1216 */
+ { 0x0000, 0x0000 }, /* R1217 */
+ { 0x0000, 0x0000 }, /* R1218 */
+ { 0x0000, 0x0000 }, /* R1219 */
+ { 0x0000, 0x0000 }, /* R1220 */
+ { 0x0000, 0x0000 }, /* R1221 */
+ { 0x0000, 0x0000 }, /* R1222 */
+ { 0x0000, 0x0000 }, /* R1223 */
+ { 0x0000, 0x0000 }, /* R1224 */
+ { 0x0000, 0x0000 }, /* R1225 */
+ { 0x0000, 0x0000 }, /* R1226 */
+ { 0x0000, 0x0000 }, /* R1227 */
+ { 0x0000, 0x0000 }, /* R1228 */
+ { 0x0000, 0x0000 }, /* R1229 */
+ { 0x0000, 0x0000 }, /* R1230 */
+ { 0x0000, 0x0000 }, /* R1231 */
+ { 0x0000, 0x0000 }, /* R1232 */
+ { 0x0000, 0x0000 }, /* R1233 */
+ { 0x0000, 0x0000 }, /* R1234 */
+ { 0x0000, 0x0000 }, /* R1235 */
+ { 0x0000, 0x0000 }, /* R1236 */
+ { 0x0000, 0x0000 }, /* R1237 */
+ { 0x0000, 0x0000 }, /* R1238 */
+ { 0x0000, 0x0000 }, /* R1239 */
+ { 0x0000, 0x0000 }, /* R1240 */
+ { 0x0000, 0x0000 }, /* R1241 */
+ { 0x0000, 0x0000 }, /* R1242 */
+ { 0x0000, 0x0000 }, /* R1243 */
+ { 0x0000, 0x0000 }, /* R1244 */
+ { 0x0000, 0x0000 }, /* R1245 */
+ { 0x0000, 0x0000 }, /* R1246 */
+ { 0x0000, 0x0000 }, /* R1247 */
+ { 0x0000, 0x0000 }, /* R1248 */
+ { 0x0000, 0x0000 }, /* R1249 */
+ { 0x0000, 0x0000 }, /* R1250 */
+ { 0x0000, 0x0000 }, /* R1251 */
+ { 0x0000, 0x0000 }, /* R1252 */
+ { 0x0000, 0x0000 }, /* R1253 */
+ { 0x0000, 0x0000 }, /* R1254 */
+ { 0x0000, 0x0000 }, /* R1255 */
+ { 0x0000, 0x0000 }, /* R1256 */
+ { 0x0000, 0x0000 }, /* R1257 */
+ { 0x0000, 0x0000 }, /* R1258 */
+ { 0x0000, 0x0000 }, /* R1259 */
+ { 0x0000, 0x0000 }, /* R1260 */
+ { 0x0000, 0x0000 }, /* R1261 */
+ { 0x0000, 0x0000 }, /* R1262 */
+ { 0x0000, 0x0000 }, /* R1263 */
+ { 0x0000, 0x0000 }, /* R1264 */
+ { 0x0000, 0x0000 }, /* R1265 */
+ { 0x0000, 0x0000 }, /* R1266 */
+ { 0x0000, 0x0000 }, /* R1267 */
+ { 0x0000, 0x0000 }, /* R1268 */
+ { 0x0000, 0x0000 }, /* R1269 */
+ { 0x0000, 0x0000 }, /* R1270 */
+ { 0x0000, 0x0000 }, /* R1271 */
+ { 0x0000, 0x0000 }, /* R1272 */
+ { 0x0000, 0x0000 }, /* R1273 */
+ { 0x0000, 0x0000 }, /* R1274 */
+ { 0x0000, 0x0000 }, /* R1275 */
+ { 0x0000, 0x0000 }, /* R1276 */
+ { 0x0000, 0x0000 }, /* R1277 */
+ { 0x0000, 0x0000 }, /* R1278 */
+ { 0x0000, 0x0000 }, /* R1279 */
+ { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */
+ { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */
+ { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */
+ { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */
+ { 0x0000, 0x0000 }, /* R1284 */
+ { 0x0000, 0x0000 }, /* R1285 */
+ { 0x0000, 0x0000 }, /* R1286 */
+ { 0x0000, 0x0000 }, /* R1287 */
+ { 0x0000, 0x0000 }, /* R1288 */
+ { 0x0000, 0x0000 }, /* R1289 */
+ { 0x0000, 0x0000 }, /* R1290 */
+ { 0x0000, 0x0000 }, /* R1291 */
+ { 0x0000, 0x0000 }, /* R1292 */
+ { 0x0000, 0x0000 }, /* R1293 */
+ { 0x0000, 0x0000 }, /* R1294 */
+ { 0x0000, 0x0000 }, /* R1295 */
+ { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */
+ { 0x0000, 0x0000 }, /* R1297 */
+ { 0x0000, 0x0000 }, /* R1298 */
+ { 0x0000, 0x0000 }, /* R1299 */
+ { 0x0000, 0x0000 }, /* R1300 */
+ { 0x0000, 0x0000 }, /* R1301 */
+ { 0x0000, 0x0000 }, /* R1302 */
+ { 0x0000, 0x0000 }, /* R1303 */
+ { 0x0000, 0x0000 }, /* R1304 */
+ { 0x0000, 0x0000 }, /* R1305 */
+ { 0x0000, 0x0000 }, /* R1306 */
+ { 0x0000, 0x0000 }, /* R1307 */
+ { 0x0000, 0x0000 }, /* R1308 */
+ { 0x0000, 0x0000 }, /* R1309 */
+ { 0x0000, 0x0000 }, /* R1310 */
+ { 0x0000, 0x0000 }, /* R1311 */
+ { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */
+ { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */
+ { 0x0000, 0x0000 }, /* R1314 */
+ { 0x0000, 0x0000 }, /* R1315 */
+ { 0x0000, 0x0000 }, /* R1316 */
+ { 0x0000, 0x0000 }, /* R1317 */
+ { 0x0000, 0x0000 }, /* R1318 */
+ { 0x0000, 0x0000 }, /* R1319 */
+ { 0x0000, 0x0000 }, /* R1320 */
+ { 0x0000, 0x0000 }, /* R1321 */
+ { 0x0000, 0x0000 }, /* R1322 */
+ { 0x0000, 0x0000 }, /* R1323 */
+ { 0x0000, 0x0000 }, /* R1324 */
+ { 0x0000, 0x0000 }, /* R1325 */
+ { 0x0000, 0x0000 }, /* R1326 */
+ { 0x0000, 0x0000 }, /* R1327 */
+ { 0x0000, 0x0000 }, /* R1328 */
+ { 0x0000, 0x0000 }, /* R1329 */
+ { 0x0000, 0x0000 }, /* R1330 */
+ { 0x0000, 0x0000 }, /* R1331 */
+ { 0x0000, 0x0000 }, /* R1332 */
+ { 0x0000, 0x0000 }, /* R1333 */
+ { 0x0000, 0x0000 }, /* R1334 */
+ { 0x0000, 0x0000 }, /* R1335 */
+ { 0x0000, 0x0000 }, /* R1336 */
+ { 0x0000, 0x0000 }, /* R1337 */
+ { 0x0000, 0x0000 }, /* R1338 */
+ { 0x0000, 0x0000 }, /* R1339 */
+ { 0x0000, 0x0000 }, /* R1340 */
+ { 0x0000, 0x0000 }, /* R1341 */
+ { 0x0000, 0x0000 }, /* R1342 */
+ { 0x0000, 0x0000 }, /* R1343 */
+ { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */
+ { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */
+ { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */
+ { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */
+ { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */
+ { 0x0000, 0x0000 }, /* R1349 */
+ { 0x0000, 0x0000 }, /* R1350 */
+ { 0x0000, 0x0000 }, /* R1351 */
+ { 0x0000, 0x0000 }, /* R1352 */
+ { 0x0000, 0x0000 }, /* R1353 */
+ { 0x0000, 0x0000 }, /* R1354 */
+ { 0x0000, 0x0000 }, /* R1355 */
+ { 0x0000, 0x0000 }, /* R1356 */
+ { 0x0000, 0x0000 }, /* R1357 */
+ { 0x0000, 0x0000 }, /* R1358 */
+ { 0x0000, 0x0000 }, /* R1359 */
+ { 0x0000, 0x0000 }, /* R1360 */
+ { 0x0000, 0x0000 }, /* R1361 */
+ { 0x0000, 0x0000 }, /* R1362 */
+ { 0x0000, 0x0000 }, /* R1363 */
+ { 0x0000, 0x0000 }, /* R1364 */
+ { 0x0000, 0x0000 }, /* R1365 */
+ { 0x0000, 0x0000 }, /* R1366 */
+ { 0x0000, 0x0000 }, /* R1367 */
+ { 0x0000, 0x0000 }, /* R1368 */
+ { 0x0000, 0x0000 }, /* R1369 */
+ { 0x0000, 0x0000 }, /* R1370 */
+ { 0x0000, 0x0000 }, /* R1371 */
+ { 0x0000, 0x0000 }, /* R1372 */
+ { 0x0000, 0x0000 }, /* R1373 */
+ { 0x0000, 0x0000 }, /* R1374 */
+ { 0x0000, 0x0000 }, /* R1375 */
+ { 0x0000, 0x0000 }, /* R1376 */
+ { 0x0000, 0x0000 }, /* R1377 */
+ { 0x0000, 0x0000 }, /* R1378 */
+ { 0x0000, 0x0000 }, /* R1379 */
+ { 0x0000, 0x0000 }, /* R1380 */
+ { 0x0000, 0x0000 }, /* R1381 */
+ { 0x0000, 0x0000 }, /* R1382 */
+ { 0x0000, 0x0000 }, /* R1383 */
+ { 0x0000, 0x0000 }, /* R1384 */
+ { 0x0000, 0x0000 }, /* R1385 */
+ { 0x0000, 0x0000 }, /* R1386 */
+ { 0x0000, 0x0000 }, /* R1387 */
+ { 0x0000, 0x0000 }, /* R1388 */
+ { 0x0000, 0x0000 }, /* R1389 */
+ { 0x0000, 0x0000 }, /* R1390 */
+ { 0x0000, 0x0000 }, /* R1391 */
+ { 0x0000, 0x0000 }, /* R1392 */
+ { 0x0000, 0x0000 }, /* R1393 */
+ { 0x0000, 0x0000 }, /* R1394 */
+ { 0x0000, 0x0000 }, /* R1395 */
+ { 0x0000, 0x0000 }, /* R1396 */
+ { 0x0000, 0x0000 }, /* R1397 */
+ { 0x0000, 0x0000 }, /* R1398 */
+ { 0x0000, 0x0000 }, /* R1399 */
+ { 0x0000, 0x0000 }, /* R1400 */
+ { 0x0000, 0x0000 }, /* R1401 */
+ { 0x0000, 0x0000 }, /* R1402 */
+ { 0x0000, 0x0000 }, /* R1403 */
+ { 0x0000, 0x0000 }, /* R1404 */
+ { 0x0000, 0x0000 }, /* R1405 */
+ { 0x0000, 0x0000 }, /* R1406 */
+ { 0x0000, 0x0000 }, /* R1407 */
+ { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */
+ { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */
+ { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */
+ { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */
+ { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */
+ { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */
+ { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */
+ { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */
+ { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */
+ { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */
+ { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */
+ { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */
+ { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */
+ { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */
+ { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */
+ { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */
+ { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */
+ { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */
+ { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */
+ { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */
+ { 0x0000, 0x0000 }, /* R1428 */
+ { 0x0000, 0x0000 }, /* R1429 */
+ { 0x0000, 0x0000 }, /* R1430 */
+ { 0x0000, 0x0000 }, /* R1431 */
+ { 0x0000, 0x0000 }, /* R1432 */
+ { 0x0000, 0x0000 }, /* R1433 */
+ { 0x0000, 0x0000 }, /* R1434 */
+ { 0x0000, 0x0000 }, /* R1435 */
+ { 0x0000, 0x0000 }, /* R1436 */
+ { 0x0000, 0x0000 }, /* R1437 */
+ { 0x0000, 0x0000 }, /* R1438 */
+ { 0x0000, 0x0000 }, /* R1439 */
+ { 0x0000, 0x0000 }, /* R1440 */
+ { 0x0000, 0x0000 }, /* R1441 */
+ { 0x0000, 0x0000 }, /* R1442 */
+ { 0x0000, 0x0000 }, /* R1443 */
+ { 0x0000, 0x0000 }, /* R1444 */
+ { 0x0000, 0x0000 }, /* R1445 */
+ { 0x0000, 0x0000 }, /* R1446 */
+ { 0x0000, 0x0000 }, /* R1447 */
+ { 0x0000, 0x0000 }, /* R1448 */
+ { 0x0000, 0x0000 }, /* R1449 */
+ { 0x0000, 0x0000 }, /* R1450 */
+ { 0x0000, 0x0000 }, /* R1451 */
+ { 0x0000, 0x0000 }, /* R1452 */
+ { 0x0000, 0x0000 }, /* R1453 */
+ { 0x0000, 0x0000 }, /* R1454 */
+ { 0x0000, 0x0000 }, /* R1455 */
+ { 0x0000, 0x0000 }, /* R1456 */
+ { 0x0000, 0x0000 }, /* R1457 */
+ { 0x0000, 0x0000 }, /* R1458 */
+ { 0x0000, 0x0000 }, /* R1459 */
+ { 0x0000, 0x0000 }, /* R1460 */
+ { 0x0000, 0x0000 }, /* R1461 */
+ { 0x0000, 0x0000 }, /* R1462 */
+ { 0x0000, 0x0000 }, /* R1463 */
+ { 0x0000, 0x0000 }, /* R1464 */
+ { 0x0000, 0x0000 }, /* R1465 */
+ { 0x0000, 0x0000 }, /* R1466 */
+ { 0x0000, 0x0000 }, /* R1467 */
+ { 0x0000, 0x0000 }, /* R1468 */
+ { 0x0000, 0x0000 }, /* R1469 */
+ { 0x0000, 0x0000 }, /* R1470 */
+ { 0x0000, 0x0000 }, /* R1471 */
+ { 0x0000, 0x0000 }, /* R1472 */
+ { 0x0000, 0x0000 }, /* R1473 */
+ { 0x0000, 0x0000 }, /* R1474 */
+ { 0x0000, 0x0000 }, /* R1475 */
+ { 0x0000, 0x0000 }, /* R1476 */
+ { 0x0000, 0x0000 }, /* R1477 */
+ { 0x0000, 0x0000 }, /* R1478 */
+ { 0x0000, 0x0000 }, /* R1479 */
+ { 0x0000, 0x0000 }, /* R1480 */
+ { 0x0000, 0x0000 }, /* R1481 */
+ { 0x0000, 0x0000 }, /* R1482 */
+ { 0x0000, 0x0000 }, /* R1483 */
+ { 0x0000, 0x0000 }, /* R1484 */
+ { 0x0000, 0x0000 }, /* R1485 */
+ { 0x0000, 0x0000 }, /* R1486 */
+ { 0x0000, 0x0000 }, /* R1487 */
+ { 0x0000, 0x0000 }, /* R1488 */
+ { 0x0000, 0x0000 }, /* R1489 */
+ { 0x0000, 0x0000 }, /* R1490 */
+ { 0x0000, 0x0000 }, /* R1491 */
+ { 0x0000, 0x0000 }, /* R1492 */
+ { 0x0000, 0x0000 }, /* R1493 */
+ { 0x0000, 0x0000 }, /* R1494 */
+ { 0x0000, 0x0000 }, /* R1495 */
+ { 0x0000, 0x0000 }, /* R1496 */
+ { 0x0000, 0x0000 }, /* R1497 */
+ { 0x0000, 0x0000 }, /* R1498 */
+ { 0x0000, 0x0000 }, /* R1499 */
+ { 0x0000, 0x0000 }, /* R1500 */
+ { 0x0000, 0x0000 }, /* R1501 */
+ { 0x0000, 0x0000 }, /* R1502 */
+ { 0x0000, 0x0000 }, /* R1503 */
+ { 0x0000, 0x0000 }, /* R1504 */
+ { 0x0000, 0x0000 }, /* R1505 */
+ { 0x0000, 0x0000 }, /* R1506 */
+ { 0x0000, 0x0000 }, /* R1507 */
+ { 0x0000, 0x0000 }, /* R1508 */
+ { 0x0000, 0x0000 }, /* R1509 */
+ { 0x0000, 0x0000 }, /* R1510 */
+ { 0x0000, 0x0000 }, /* R1511 */
+ { 0x0000, 0x0000 }, /* R1512 */
+ { 0x0000, 0x0000 }, /* R1513 */
+ { 0x0000, 0x0000 }, /* R1514 */
+ { 0x0000, 0x0000 }, /* R1515 */
+ { 0x0000, 0x0000 }, /* R1516 */
+ { 0x0000, 0x0000 }, /* R1517 */
+ { 0x0000, 0x0000 }, /* R1518 */
+ { 0x0000, 0x0000 }, /* R1519 */
+ { 0x0000, 0x0000 }, /* R1520 */
+ { 0x0000, 0x0000 }, /* R1521 */
+ { 0x0000, 0x0000 }, /* R1522 */
+ { 0x0000, 0x0000 }, /* R1523 */
+ { 0x0000, 0x0000 }, /* R1524 */
+ { 0x0000, 0x0000 }, /* R1525 */
+ { 0x0000, 0x0000 }, /* R1526 */
+ { 0x0000, 0x0000 }, /* R1527 */
+ { 0x0000, 0x0000 }, /* R1528 */
+ { 0x0000, 0x0000 }, /* R1529 */
+ { 0x0000, 0x0000 }, /* R1530 */
+ { 0x0000, 0x0000 }, /* R1531 */
+ { 0x0000, 0x0000 }, /* R1532 */
+ { 0x0000, 0x0000 }, /* R1533 */
+ { 0x0000, 0x0000 }, /* R1534 */
+ { 0x0000, 0x0000 }, /* R1535 */
+ { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */
+ { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */
+ { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */
+ { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */
+ { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */
+ { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */
+ { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
+ { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
+ { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
+ { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
+ { 0x0000, 0x0000 }, /* R1546 */
+ { 0x0000, 0x0000 }, /* R1547 */
+ { 0x0000, 0x0000 }, /* R1548 */
+ { 0x0000, 0x0000 }, /* R1549 */
+ { 0x0000, 0x0000 }, /* R1550 */
+ { 0x0000, 0x0000 }, /* R1551 */
+ { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */
+ { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */
+ { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */
+ { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */
+ { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */
+ { 0x0000, 0x0000 }, /* R1557 */
+ { 0x0000, 0x0000 }, /* R1558 */
+ { 0x0000, 0x0000 }, /* R1559 */
+ { 0x0000, 0x0000 }, /* R1560 */
+ { 0x0000, 0x0000 }, /* R1561 */
+ { 0x0000, 0x0000 }, /* R1562 */
+ { 0x0000, 0x0000 }, /* R1563 */
+ { 0x0000, 0x0000 }, /* R1564 */
+ { 0x0000, 0x0000 }, /* R1565 */
+ { 0x0000, 0x0000 }, /* R1566 */
+ { 0x0000, 0x0000 }, /* R1567 */
+ { 0x0003, 0x0003 }, /* R1568 - Oversampling */
+ { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */
+};
+
+static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
+{
+ switch (reg) {
+ case WM8994_GPIO_1:
+ case WM8994_GPIO_2:
+ case WM8994_GPIO_3:
+ case WM8994_GPIO_4:
+ case WM8994_GPIO_5:
+ case WM8994_GPIO_6:
+ case WM8994_GPIO_7:
+ case WM8994_GPIO_8:
+ case WM8994_GPIO_9:
+ case WM8994_GPIO_10:
+ case WM8994_GPIO_11:
+ case WM8994_INTERRUPT_STATUS_1:
+ case WM8994_INTERRUPT_STATUS_2:
+ return 1;
+ default:
+ break;
+ }
+
+ if (reg >= ARRAY_SIZE(access_masks))
+ return 0;
+ return access_masks[reg].readable != 0;
+}
+
+static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
+{
+ //if (reg >= WM8994_CACHE_SIZE)
+ // return 1;
+
+ switch (reg) {
+ case WM8994_SOFTWARE_RESET:
+ case WM8994_CHIP_REVISION:
+ case WM8994_DC_SERVO_1:
+ case WM8994_DC_SERVO_READBACK:
+ case WM8994_RATE_STATUS:
+ case WM8994_LDO_1:
+ case WM8994_LDO_2:
+ case WM8958_DSP2_EXECCONTROL:
+ case WM8958_MIC_DETECT_3:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+/*
+ * initialise the WM8994 driver
+ * register the mixer and dsp interfaces with the kernel
+ */
+static int wm8994_init(struct wm8994_priv *wm8994_private,
+ struct wm8994_platform_data *pdata)
+{
+ struct snd_soc_codec *codec = wm8994_private->codec;
+ struct wm8994_priv *wm8994;
+ int ret = 0;
+ DEBUG_LOG("");
+ wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
+ if (wm8994 == NULL)
+ return -ENOMEM;
+
+ snd_soc_codec_set_drvdata(codec, wm8994);
+
+#if 0
+ mutex_init(&codec->mutex);
+ INIT_LIST_HEAD(&codec->dapm_widgets);
+ INIT_LIST_HEAD(&codec->dapm_paths);
+ codec->name = "WM8994";
+ codec->owner = THIS_MODULE;
+ codec->read = wm8994_read;
+ codec->write = wm8994_write;
+ codec->readable_register = wm8994_readable_register;
+ codec->reg_cache_size = WM8994_IRQ_POLARITY; /* Skip write sequencer */
+ codec->set_bias_level = NULL;
+ codec->dai = &wm8994_dai;
+ codec->num_dai = 1;
+#endif
+ wm8994->universal_playback_path = universal_wm8994_playback_paths;
+ wm8994->universal_voicecall_path = universal_wm8994_voicecall_paths;
+ wm8994->universal_mic_path = universal_wm8994_mic_paths;
+ wm8994->universal_clock_control = universal_clock_controls;
+ wm8994->stream_state = PCM_STREAM_DEACTIVE;
+ wm8994->cur_path = OFF;
+ wm8994->rec_path = MIC_OFF;
+ wm8994->power_state = CODEC_OFF;
+ wm8994->input_source = DEFAULT;
+ wm8994->ringtone_active = RING_OFF;
+ wm8994->pdata = pdata;
+
+ wm8994->gain_code = gain_code_check();
+
+ wm8994->codec_clk = clk_get(NULL, "usb_osc");
+
+ wm8994->universal_clock_control(codec, CODEC_ON);
+
+ if (IS_ERR(wm8994->codec_clk)) {
+ pr_err("failed to get MCLK clock from AP\n");
+ ret = PTR_ERR(wm8994->codec_clk);
+ goto card_err;
+ }
+
+ wm8994_write(codec, WM8994_SOFTWARE_RESET, 0x0000);
+
+ wm8994->hw_version = wm8994_read(codec, 0x100);
+
+ //wm8994_socdev->card->codec = codec;
+ wm8994_codec = codec;
+
+#if 0
+ ret = snd_soc_new_pcms(wm8994_socdev, SNDRV_DEFAULT_IDX1,
+ SNDRV_DEFAULT_STR1);
+ if (ret < 0) {
+ DEBUG_LOG_ERR("failed to create pcms\n");
+ goto pcm_err;
+ }
+#endif
+
+ wm8994_add_controls(codec);
+ wm8994_add_widgets(codec);
+
+ return ret;
+
+card_err:
+ //snd_soc_free_pcms(wm8994_socdev);
+ //snd_soc_dapm_free(wm8994_socdev);
+pcm_err:
+
+ return ret;
+}
+
+/* If the i2c layer weren't so broken, we could pass this kind of data
+ around */
+
+static int wm8994_codec_probe(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994_priv;
+ int ret = -ENODEV;
+ struct wm8994_platform_data *pdata;
+
+ DEBUG_LOG("");
+ pr_info("WM8994 Audio Codec %s\n", WM8994_VERSION);
+
+ wm8994_priv = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
+ if (wm8994_priv == NULL)
+ return -ENOMEM;
+
+ wm8994_priv->codec = codec;
+#ifdef PM_DEBUG
+ pm_codec = codec;
+#endif
+
+ pdata = dev_get_platdata(codec->dev);
+
+ if (!pdata) {
+ dev_err(codec->dev, "failed to initialize WM8994\n");
+ goto err_bad_pdata;
+ }
+
+ if (!pdata->set_mic_bias) {
+ dev_err(codec->dev, "bad pdata WM8994\n");
+ goto err_bad_pdata;
+ }
+
+ /* CODEC LDO SETTING */
+ if (gpio_is_valid(pdata->ldo)) {
+ ret = gpio_request(pdata->ldo, "WM8994 LDO");
+ if (ret) {
+ pr_err("Failed to request CODEC_LDO_EN!\n");
+ goto err_ldo;
+ }
+ gpio_direction_output(pdata->ldo, 0);
+ }
+
+ s3c_gpio_setpull(pdata->ldo, S3C_GPIO_PULL_NONE);
+
+ /* For preserving output of codec related pins */
+ s3c_gpio_slp_cfgpin(pdata->ldo, S3C_GPIO_SLP_PREV);
+ s3c_gpio_slp_setpull_updown(pdata->ldo, S3C_GPIO_PULL_NONE);
+
+ /* EAR_SEL SETTING(only crespo HW) */
+ if (gpio_is_valid(pdata->ear_sel)) {
+ ret = gpio_request(pdata->ear_sel, "EAR SEL");
+ if (ret) {
+ pr_err("Failed to request EAR_SEL!\n");
+ goto err_earsel;
+ }
+ gpio_direction_output(pdata->ear_sel, 0);
+ }
+ if (!herring_is_cdma_wimax_dev()) {
+ s3c_gpio_setpull(pdata->ear_sel, S3C_GPIO_PULL_NONE);
+
+ s3c_gpio_slp_cfgpin(pdata->ear_sel, S3C_GPIO_SLP_PREV);
+ s3c_gpio_slp_setpull_updown(pdata->ear_sel, S3C_GPIO_PULL_NONE);
+ }
+ wm8994_ldo_control(pdata, 1);
+
+ codec->hw_write = (hw_write_t) i2c_master_send;
+ //i2c_set_clientdata(i2c, wm8994_priv);
+ //codec->control_data = i2c;
+ codec->control_data = to_i2c_client(codec->dev);
+ //codec->dev = &i2c->dev;
+
+ ret = wm8994_init(wm8994_priv, pdata);
+#ifdef CONFIG_SND_VOODOO
+ voodoo_hook_wm8994_pcm_probe(codec);
+#endif
+ if (ret) {
+ dev_err(codec->dev, "failed to initialize WM8994\n");
+ goto err_init;
+ }
+
+ return ret;
+
+err_init:
+ gpio_free(pdata->ear_sel);
+err_earsel:
+ gpio_free(pdata->ldo);
+err_ldo:
+err_bad_pdata:
+ kfree(wm8994_priv);
+ return ret;
+}
+
+static int wm8994_codec_remove(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994_priv = snd_soc_codec_get_drvdata(codec);
+
+ gpio_free(wm8994_priv->pdata->ldo);
+ gpio_free(wm8994_priv->pdata->ear_sel);
+
+ kfree(wm8994_priv);
+ return 0;
+}
+
+#if 0
+/* power down chip */
+static int wm8994_remove(struct platform_device *pdev)
+{
+ //struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+ struct snd_soc_codec *codec = wm8994_codec;
+
+ //snd_soc_free_pcms(socdev);
+ //snd_soc_dapm_free(socdev);
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+ i2c_unregister_device(codec->control_data);
+ i2c_del_driver(&wm8994_i2c_driver);
+#endif
+
+ //kfree(codec->drvdata);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PM
+static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ DEBUG_LOG("Codec State = [0x%X], Stream State = [0x%X]",
+ wm8994->codec_state, wm8994->stream_state);
+
+ if (wm8994->codec_state == DEACTIVE &&
+ wm8994->stream_state == PCM_STREAM_DEACTIVE) {
+ wm8994->power_state = CODEC_OFF;
+ wm8994_write(codec, WM8994_SOFTWARE_RESET, 0x0000);
+ wm8994_ldo_control(wm8994->pdata, 0);
+ wm8994->universal_clock_control(codec, CODEC_OFF);
+ }
+
+ return 0;
+}
+
+static int wm8994_resume(struct snd_soc_codec *codec)
+{
+ struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+ DEBUG_LOG("%s..", __func__);
+ DEBUG_LOG_ERR("------WM8994 Revision = [%d]-------",
+ wm8994->hw_version);
+
+ if (wm8994->power_state == CODEC_OFF) {
+ /* Turn on sequence by recommend Wolfson.*/
+ wm8994_ldo_control(wm8994->pdata, 1);
+ wm8994->universal_clock_control(codec, CODEC_ON);
+ }
+ return 0;
+}
+#endif
+
+#if 0
+struct snd_soc_codec_device soc_codec_dev_wm8994 = {
+ .probe = wm8994_probe,
+ .remove = wm8994_remove,
+#ifdef CONFIG_PM
+ .suspend = wm8994_suspend,
+ .resume = wm8994_resume,
+#endif
+};
+#endif
+
+#if 0
+static int __init wm8994_modinit(void)
+{
+ int ret;
+ ret = snd_soc_register_dai(&wm8994_dai);
+ if (ret)
+ pr_err("..dai registration failed..\n");
+
+ return ret;
+}
+
+module_init(wm8994_modinit);
+
+static void __exit wm8994_exit(void)
+{
+ snd_soc_unregister_dai(&wm8994_dai);
+}
+
+module_exit(wm8994_exit);
+#endif
+
+static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
+ .probe = wm8994_codec_probe,
+ .remove = wm8994_codec_remove,
+ .suspend = wm8994_suspend,
+ .resume = wm8994_resume,
+ .read = wm8994_read,
+ .write = wm8994_write,
+ .readable_register = wm8994_readable,
+ .volatile_register = wm8994_volatile,
+ //.set_bias_level = wm8994_set_bias_level,
+
+ .reg_cache_size = WM8994_IRQ_POLARITY,
+ //.reg_cache_size = WM8994_CACHE_SIZE,
+ //.reg_cache_default = wm8994_reg_defaults,
+ .reg_word_size = 2,
+ .compress_type = SND_SOC_RBTREE_COMPRESSION,
+};
+
+static int wm8994_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ return snd_soc_register_codec(&client->dev, &soc_codec_dev_wm8994,
+ wm8994_dai, ARRAY_SIZE(wm8994_dai));
+}
+
+static int wm8994_i2c_remove(struct i2c_client *client)
+{
+ snd_soc_unregister_codec(&client->dev);
+ return 0;
+}
+
+
+static const struct i2c_device_id wm8994_i2c_id[] = {
+ {"wm8994-samsung", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
+
+static struct i2c_driver wm8994_i2c_driver = {
+ .driver = {
+ .name = "wm8994-samsung-codec",
+ .owner = THIS_MODULE,
+ },
+ .probe = wm8994_i2c_probe,
+ .remove = wm8994_i2c_remove,
+ .id_table = wm8994_i2c_id,
+};
+
+static __init int wm8994_driver_init(void)
+{
+ return i2c_add_driver(&wm8994_i2c_driver);
+}
+module_init(wm8994_driver_init);
+
+static __exit void wm8994_driver_exit(void)
+{
+ i2c_del_driver(&wm8994_i2c_driver);
+}
+module_exit(wm8994_driver_exit);
+
+MODULE_DESCRIPTION("ASoC WM8994 driver");
+MODULE_AUTHOR("Shaju Abraham shaju.abraham@samsung.com");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8994_samsung.h b/sound/soc/codecs/wm8994_samsung.h
new file mode 100755
index 0000000..fa4fc3f
--- /dev/null
+++ b/sound/soc/codecs/wm8994_samsung.h
@@ -0,0 +1,207 @@
+/*
+ * wm8994_samsung.h -- WM8994 Soc Audio driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8994_SAMSUNG_H
+#define _WM8994_SAMSUNG_H
+
+#include <sound/soc.h>
+#include <linux/mfd/wm8994/wm8994_pdata.h>
+
+/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
+#define WM8994_SYSCLK_MCLK1 1
+#define WM8994_SYSCLK_MCLK2 2
+#define WM8994_SYSCLK_FLL1 3
+#define WM8994_SYSCLK_FLL2 4
+
+#define WM8994_FLL1 1
+#define WM8994_FLL2 2
+
+/* Added belows codes by Samsung Electronics.*/
+
+#include "wm8994_def.h"
+
+#define WM8994_SYSCLK_MCLK 1
+#define WM8994_SYSCLK_FLL 2
+
+//#define WM8994_CACHE_SIZE 1570
+
+#define AUDIO_COMMON_DEBUG 0
+
+#define DEACTIVE 0x00
+#define PLAYBACK_ACTIVE 0x01
+#define CAPTURE_ACTIVE 0x02
+#define CALL_ACTIVE 0x04
+
+#define PCM_STREAM_DEACTIVE 0x00
+#define PCM_STREAM_PLAYBACK 0x01
+#define PCM_STREAM_CAPTURE 0x02
+
+/*
+Codec Output Path BIT
+[0:11] : For output device
+[12:15] : For mode
+[16] : For gain code
+*/
+#define PLAYBACK_MODE (0x01 << 12)
+#define VOICECALL_MODE (0x01 << 13)
+#define RECORDING_MODE (0x01 << 14)
+#define FMRADIO_MODE (0x01 << 15)
+
+/*
+ * devide codec gain table
+ * GAIN_DIVISION_BIT_1 : EUR
+ * GAIN_DIVISION_BIT_2 : AT&T
+ * GAIN_DIVISION_BIT_3 : EUR_T
+ */
+
+#define GAIN_DIVISION_BIT_1 (0x01 << 16)
+#define GAIN_DIVISION_BIT_2 (0x01 << 17)
+#define GAIN_DIVISION_BIT_3 (0x01 << 18)
+
+#define COMMON_SET_BIT (0x01 << 0)
+#define PLAYBACK_RCV (0x01 << 1)
+#define PLAYBACK_SPK (0x01 << 2)
+#define PLAYBACK_HP (0x01 << 3)
+#define PLAYBACK_BT (0x01 << 4)
+#define PLAYBACK_SPK_HP (0x01 << 5)
+#define PLAYBACK_RING_SPK (0x01 << 6)
+#define PLAYBACK_RING_HP (0x01 << 7)
+#define PLAYBACK_RING_SPK_HP (0x01 << 8)
+#define PLAYBACK_HP_NO_MIC (0x01 << 9)
+
+#define VOICECALL_RCV (0x01 << 1)
+#define VOICECALL_SPK (0x01 << 2)
+#define VOICECALL_HP (0x01 << 3)
+#define VOICECALL_HP_NO_MIC (0x01 << 4)
+#define VOICECALL_BT (0x01 << 5)
+#define VOICECALL_TTY_VCO (0x01 << 6)
+#define VOICECALL_TTY_HCO (0x01 << 7)
+#define VOICECALL_TTY_FULL (0x01 << 8)
+
+#define RECORDING_MAIN (0x01 << 1)
+#define RECORDING_HP (0x01 << 2)
+#define RECORDING_BT (0x01 << 3)
+#define RECORDING_REC_MAIN (0x01 << 4)
+#define RECORDING_REC_HP (0x01 << 5)
+#define RECORDING_REC_BT (0x01 << 6)
+#define RECORDING_CAM_MAIN (0x01 << 7)
+#define RECORDING_CAM_HP (0x01 << 8)
+#define RECORDING_CAM_BT (0x01 << 9)
+#define RECORDING_VC_MAIN (0x01 << 10)
+#define RECORDING_VC_HP (0x01 << 11)
+#define RECORDING_VC_BT (0x01 << 12)
+
+#define PLAYBACK_GAIN_NUM 43
+#define VOICECALL_GAIN_NUM 38
+#define RECORDING_GAIN_NUM 32
+#define GAIN_CODE_NUM 13
+/*
+ * Definitions of enum type
+ */
+enum audio_path {
+ OFF, RCV, SPK, HP, HP_NO_MIC, BT, SPK_HP,
+ RING_SPK, RING_HP, RING_NO_MIC, RING_SPK_HP
+};
+enum call_path {
+ CALL_OFF, CALL_RCV, CALL_SPK, CALL_HP,
+ CALL_HP_NO_MIC, CALL_BT, CALL_TTY_VCO,
+ CALL_TTY_HCO, CALL_TTY_FULL
+};
+enum mic_path {MAIN, SUB, BT_REC, MIC_OFF};
+enum power_state {CODEC_OFF, CODEC_ON };
+enum ringtone_state {RING_OFF, RING_ON};
+enum input_source_state {DEFAULT, RECOGNITION, CAMCORDER, VOICE_COMMUNICATION};
+
+typedef void (*select_route)(struct snd_soc_codec *);
+typedef void (*select_mic_route)(struct snd_soc_codec *);
+typedef int (*select_clock_control)(struct snd_soc_codec *, int);
+
+
+struct wm8994_setup_data {
+ int i2c_bus;
+ unsigned short i2c_address;
+};
+
+enum wm8994_dc_servo_slots {
+ DCS_MEDIA = 0,
+ DCS_VOICE = 1,
+ DCS_SPK_HP = 2,
+};
+
+struct wm8994_priv {
+ struct snd_soc_codec *codec;
+ int master;
+ int sysclk_source;
+ unsigned int mclk_rate;
+ unsigned int sysclk_rate;
+ unsigned int fs;
+ unsigned int bclk;
+ unsigned int hw_version;
+ unsigned int codec_state;
+ unsigned int stream_state;
+ enum audio_path cur_path;
+ enum mic_path rec_path;
+ enum power_state power_state;
+ enum input_source_state input_source;
+ enum ringtone_state ringtone_active;
+ select_route *universal_playback_path;
+ select_route *universal_voicecall_path;
+ select_mic_route *universal_mic_path;
+ select_clock_control universal_clock_control;
+ struct wm8994_platform_data *pdata;
+ struct clk *codec_clk;
+ int gain_code;
+ u16 dc_servo[3];
+};
+
+struct gain_info_t {
+ int mode;
+ int reg;
+ int mask;
+ int gain;
+};
+
+#if AUDIO_COMMON_DEBUG
+#define DEBUG_LOG(format, ...)\
+ printk(KERN_INFO "[ "SUBJECT " (%s,%d) ] " format "\n", \
+ __func__, __LINE__, ## __VA_ARGS__);
+#else
+#define DEBUG_LOG(format, ...)
+#endif
+
+#define DEBUG_LOG_ERR(format, ...)\
+ printk(KERN_ERR "[ "SUBJECT " (%s,%d) ] " format "\n", \
+ __func__, __LINE__, ## __VA_ARGS__);
+
+/* Definitions of function prototype. */
+unsigned int wm8994_read(struct snd_soc_codec *codec, unsigned int reg);
+int wm8994_write(struct snd_soc_codec *codec,
+ unsigned int reg, unsigned int value);
+int wm8994_configure_clock(struct snd_soc_codec *codec, int en);
+void wm8994_disable_path(struct snd_soc_codec *codec);
+void wm8994_disable_rec_path(struct snd_soc_codec *codec);
+void wm8994_record_main_mic(struct snd_soc_codec *codec);
+void wm8994_record_headset_mic(struct snd_soc_codec *codec);
+void wm8994_record_bluetooth(struct snd_soc_codec *codec);
+void wm8994_set_playback_receiver(struct snd_soc_codec *codec);
+void wm8994_set_playback_headset(struct snd_soc_codec *codec);
+void wm8994_set_playback_speaker(struct snd_soc_codec *codec);
+void wm8994_set_playback_bluetooth(struct snd_soc_codec *codec);
+void wm8994_set_playback_speaker_headset(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_common_setting(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_receiver(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_headset(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_headphone(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_speaker(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_bluetooth(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_tty_vco(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_tty_hco(struct snd_soc_codec *codec);
+void wm8994_set_voicecall_tty_full(struct snd_soc_codec *codec);
+int wm8994_set_codec_gain(struct snd_soc_codec *codec, u16 mode, u16 device);
+extern int gain_code_check(void);
+#endif
diff --git a/sound/soc/codecs/wm8994_voodoo.c b/sound/soc/codecs/wm8994_voodoo.c
new file mode 100644
index 0000000..750702f
--- /dev/null
+++ b/sound/soc/codecs/wm8994_voodoo.c
@@ -0,0 +1,1872 @@
+/*
+ * voodoo_sound.c -- WM8994 ALSA Soc Audio driver related
+ *
+ * Copyright (C) 2010/11 François SIMOND / twitter & XDA-developers @supercurio
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <sound/soc.h>
+#include <linux/delay.h>
+#include <linux/miscdevice.h>
+#include <linux/version.h>
+#include "wm8994_voodoo.h"
+
+#ifndef MODULE
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) && !defined(GALAXY_TAB)
+#include "wm8994_samsung.h"
+#else
+#include "wm8994.h"
+#endif
+#else
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) && !defined(GALAXY_TAB)
+#include "../wm8994_samsung.h"
+#else
+#include "../wm8994.h"
+#endif
+#endif
+
+#define SUBJECT "wm8994_voodoo.c"
+
+#ifdef MODULE
+#include "tegrak_voodoo_sound.h"
+
+// wm8994_write -> tegrak_wm8994_write for dynamic link
+#ifdef wm8994_write
+#undef wm8994_write
+#endif
+
+// wm8994_read -> tegrak_wm8994_read for dynamic link
+#ifdef wm8994_read
+#undef wm8994_read
+#endif
+
+#define wm8994_write(codec, reg, value) tegrak_wm8994_write(codec, reg, value)
+#define wm8994_read(codec, reg) tegrak_wm8994_read(codec, reg)
+#endif
+
+bool bypass_write_hook = false;
+
+short unsigned int debug_log_level = LOG_OFF;
+
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+unsigned short hp_level[2] = { CONFIG_SND_VOODOO_HP_LEVEL,
+ CONFIG_SND_VOODOO_HP_LEVEL };
+#endif
+
+#ifdef CONFIG_SND_VOODOO_FM
+bool fm_radio_headset_restore_bass = true;
+bool fm_radio_headset_restore_highs = true;
+bool fm_radio_headset_normalize_gain = true;
+#endif
+
+#ifdef CONFIG_SND_VOODOO_RECORD_PRESETS
+unsigned short recording_preset = 1;
+unsigned short origin_recgain;
+unsigned short origin_recgain_mixer;
+#endif
+
+#ifdef NEXUS_S
+bool speaker_tuning = false;
+#endif
+
+// global active or kill switch
+bool enable = false;
+
+bool dac_osr128 = true;
+bool adc_osr128 = false;
+#ifndef GALAXY_TAB_TEGRA
+bool fll_tuning = true;
+#endif
+bool dac_direct = true;
+bool mono_downmix = false;
+
+// equalizer
+
+// digital gain value in mili dB
+int digital_gain = 0;
+
+bool headphone_eq = false;
+short eq_gains[5] = { 0, 0, 0, 0, 0 };
+short eq_bands[5] = { 3, 4, 4, 4, 3 };
+char eq_band_coef_names[][2] = { "A", "B", "C", "PG" };
+
+unsigned int eq_band_values[5][4] = {
+ {0x0FCA, 0x0400, 0x00D8},
+ {0x1EB5, 0xF145, 0x0B75, 0x01C5},
+ {0x1C58, 0xF373, 0x0A54, 0x0558},
+ {0x168E, 0xF829, 0x07AD, 0x1103},
+ {0x0564, 0x0559, 0x4000}
+};
+
+// 3D effect
+bool stereo_expansion = false;
+short unsigned int stereo_expansion_gain = 16;
+
+// keep here a pointer to the codec structure
+static struct snd_soc_codec *codec;
+
+#define DECLARE_BOOL_SHOW(name) \
+static ssize_t name##_show(struct device *dev, \
+struct device_attribute *attr, char *buf) \
+{ \
+ return sprintf(buf,"%u\n",(name ? 1 : 0)); \
+}
+
+#define DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(name, updater, with_mute) \
+static ssize_t name##_store(struct device *dev, struct device_attribute *attr, \
+ const char *buf, size_t size) \
+{ \
+ unsigned short state; \
+ if (sscanf(buf, "%hu", &state) == 1) { \
+ name = state == 0 ? false : true; \
+ if (debug_log(LOG_INFOS)) \
+ printk("Voodoo sound: %s: %u\n", #updater, state); \
+ updater(with_mute); \
+ } \
+ return size; \
+}
+
+#define DECLARE_EQ_GAIN_SHOW(band) \
+static ssize_t headphone_eq_b##band##_gain_show(struct device *dev, \
+ struct device_attribute *attr, \
+ char *buf) \
+{ \
+ return sprintf(buf, "%d\n", eq_gains[band - 1]); \
+}
+
+#define DECLARE_EQ_GAIN_STORE(band) \
+static ssize_t headphone_eq_b##band##_gain_store(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t size) \
+{ \
+ short new_gain; \
+ if (sscanf(buf, "%hd", &new_gain) == 1) { \
+ if (new_gain >= -12 && new_gain <= 12) { \
+ smooth_apply_eq_band_gain(band - 1, \
+ eq_gains[band - 1], \
+ new_gain, \
+ headphone_eq); \
+ eq_gains[band - 1] = new_gain; \
+ } \
+ } \
+ return size; \
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+#define DECLARE_WM8994(codec) struct wm8994_priv *wm8994 = \
+ snd_soc_codec_get_drvdata(codec);
+#else
+#define DECLARE_WM8994(codec) struct wm8994_priv *wm8994 = codec->private_data;
+#endif
+
+bool debug_log(short unsigned int level)
+{
+ if (debug_log_level >= level)
+ return true;
+
+ return false;
+}
+
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+int hpvol(int channel)
+{
+ int vol;
+
+ vol = hp_level[channel];
+
+ if (is_path_media_or_fm_no_call_no_record()) {
+ // negative digital gain compensation
+ if (digital_gain < 0)
+ vol = (vol - ((digital_gain / 100) + 5) / 10);
+
+ if (vol > 62)
+ return 62;
+ }
+
+ return vol;
+}
+
+void write_hpvol(unsigned short l, unsigned short r)
+{
+ unsigned short val;
+
+ // we don't need the Volume Update flag when sending the first volume
+ val = (WM8994_HPOUT1L_MUTE_N | l);
+ val |= WM8994_HPOUT1L_ZC;
+ wm8994_write(codec, WM8994_LEFT_OUTPUT_VOLUME, val);
+
+ // this time we write the right volume plus the Volume Update flag.
+ // This way, both volume are set at the same time
+ val = (WM8994_HPOUT1_VU | WM8994_HPOUT1R_MUTE_N | r);
+ val |= WM8994_HPOUT1L_ZC;
+ wm8994_write(codec, WM8994_RIGHT_OUTPUT_VOLUME, val);
+}
+
+void update_hpvol(bool with_fade)
+{
+ unsigned short val;
+ unsigned short i;
+ short steps;
+ int hp_level_old[2];
+ unsigned short hp_level_registers[2] = { WM8994_LEFT_OUTPUT_VOLUME,
+ WM8994_RIGHT_OUTPUT_VOLUME };
+
+ DECLARE_WM8994(codec);
+
+ // don't affect headphone amplifier volume
+ // when not on heapdhones or if call is active
+ if (!is_path(HEADPHONES)
+ || (wm8994->codec_state & CALL_ACTIVE))
+ return;
+
+
+ if (!with_fade) {
+ bypass_write_hook = true;
+ write_hpvol(hpvol(0), hpvol(1));
+ bypass_write_hook = false;
+ return;
+ }
+
+ // read previous levels
+ for (i = 0; i < 2; i++) {
+ val = wm8994_read(codec, hp_level_registers[i]);
+ val &= ~(WM8994_HPOUT1_VU_MASK);
+ val &= ~(WM8994_HPOUT1L_ZC_MASK);
+ val &= ~(WM8994_HPOUT1L_MUTE_N_MASK);
+ hp_level_old[i] = val + (digital_gain / 1000);
+
+ if (hp_level_old[i] < 0)
+ hp_level_old[i] = 0;
+
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: previous hp_level[%hu]: %d\n",
+ i, hp_level_old[i]);
+ }
+
+ // calculate number of steps for volume fade
+ steps = hp_level[0] - hp_level_old[0];
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: volume change steps: %hd "
+ "start: %hu, end: %hu\n",
+ steps,
+ hp_level_old[0],
+ hp_level[0]);
+
+ while (steps != 0) {
+ if (hp_level[0] < hp_level_old[0])
+ steps++;
+ else
+ steps--;
+
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: volume: %hu\n",
+ (hpvol(0) - steps));
+
+ bypass_write_hook = true;
+ write_hpvol(hpvol(0) - steps, hpvol(1) - steps);
+ bypass_write_hook = false;
+
+ if (steps != 0)
+ udelay(1000);
+ }
+
+}
+#endif
+
+#ifdef CONFIG_SND_VOODOO_FM
+void update_fm_radio_headset_restore_freqs(bool with_mute)
+{
+ unsigned short val;
+ DECLARE_WM8994(codec);
+
+ bypass_write_hook = true;
+ // apply only when FM radio is active
+ if (wm8994->fmradio_path == FMR_OFF)
+ return;
+
+ if (with_mute) {
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1,
+ WM8994_AIF2DAC_MUTE |
+ WM8994_AIF2DAC_MUTERATE |
+ WM8994_AIF2DAC_UNMUTE_RAMP |
+ WM8994_AIF2DAC_DEEMP_MASK);
+ msleep(180);
+ }
+
+ if (fm_radio_headset_restore_bass) {
+ // disable Sidetone high-pass filter
+ // was designed for voice and not FM radio
+ wm8994_write(codec, WM8994_SIDETONE, 0x0000);
+ // disable 4FS ultrasonic mode and
+ // restore the hi-fi <4Hz hi pass filter
+ wm8994_write(codec, WM8994_AIF2_ADC_FILTERS,
+ WM8994_AIF2ADCL_HPF |
+ WM8994_AIF2ADCR_HPF);
+ } else {
+ // default settings in GT-I9000 Froyo XXJPX kernel sources
+ wm8994_write(codec, WM8994_SIDETONE, 0x01c0);
+ wm8994_write(codec, WM8994_AIF2_ADC_FILTERS, 0xF800);
+ }
+
+ if (fm_radio_headset_restore_highs) {
+ val = wm8994_read(codec, WM8994_AIF2_DAC_FILTERS_1);
+ val &= ~(WM8994_AIF2DAC_DEEMP_MASK);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, val);
+ } else {
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, 0x0036);
+ }
+
+ // un-mute
+ if (with_mute) {
+ val = wm8994_read(codec, WM8994_AIF2_DAC_FILTERS_1);
+ val &= ~(WM8994_AIF2DAC_MUTE_MASK);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, val);
+ }
+ bypass_write_hook = false;
+}
+
+void update_fm_radio_headset_normalize_gain(bool with_mute)
+{
+ DECLARE_WM8994(codec);
+
+ bypass_write_hook = true;
+ // apply only when FM radio is active
+ if (wm8994->fmradio_path == FMR_OFF)
+ return;
+
+ if (fm_radio_headset_normalize_gain) {
+ // Bumped volume, change with Zero Cross
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_3_4_VOLUME, 0x52);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, 0x152);
+ wm8994_write(codec, WM8994_AIF2_DRC_2, 0x0840);
+ wm8994_write(codec, WM8994_AIF2_DRC_3, 0x2408);
+ wm8994_write(codec, WM8994_AIF2_DRC_4, 0x0082);
+ wm8994_write(codec, WM8994_AIF2_DRC_5, 0x0100);
+ wm8994_write(codec, WM8994_AIF2_DRC_1, 0x019C);
+ } else {
+ // Original volume, change with Zero Cross
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_3_4_VOLUME, 0x4B);
+ wm8994_write(codec, WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, 0x14B);
+ wm8994_write(codec, WM8994_AIF2_DRC_2, 0x0840);
+ wm8994_write(codec, WM8994_AIF2_DRC_3, 0x2400);
+ wm8994_write(codec, WM8994_AIF2_DRC_4, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DRC_5, 0x0000);
+ wm8994_write(codec, WM8994_AIF2_DRC_1, 0x019C);
+ }
+ bypass_write_hook = false;
+}
+#endif
+
+#ifdef CONFIG_SND_VOODOO_RECORD_PRESETS
+void update_recording_preset(bool with_mute)
+{
+ if (!is_path(MAIN_MICROPHONE))
+ return;
+
+ switch (recording_preset) {
+ case 0:
+ // Original:
+ // On Galaxy S: IN1L_VOL1=11000 (+19.5 dB)
+ // On Nexus S: variable value
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME,
+ WM8994_IN1L_VU | origin_recgain);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3, origin_recgain_mixer);
+ // DRC disabled
+ wm8994_write(codec, WM8994_AIF1_DRC1_1, 0x0080);
+ break;
+ case 2:
+ // High sensitivy:
+ // Original - 4.5 dB, IN1L_VOL1=10101 (+15 dB)
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, 0x0115);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3,
+ WM8994_IN1L_TO_MIXINL |
+ WM8994_IN1L_MIXINL_VOL);
+ // DRC Input: -6dB, Ouptut -3.75dB
+ // Above knee 1/8, Below knee 1/2
+ // Max gain 24 / Min gain -12
+ wm8994_write(codec, WM8994_AIF1_DRC1_1,
+ WM8994_AIF1DRC1_SIG_DET_MODE |
+ WM8994_AIF1DRC1_QR |
+ WM8994_AIF1DRC1_ANTICLIP |
+ WM8994_AIF1ADC1L_DRC_ENA);
+ wm8994_write(codec, WM8994_AIF1_DRC1_2, 0x0426);
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, 0x0019);
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, 0x0105);
+ break;
+ case 3:
+ // Concert new: IN1L_VOL1=10110 (+4.5 dB)
+ // +30dB input mixer gain deactivated
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, 0x010F);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3,
+ WM8994_IN1L_TO_MIXINL);
+ // DRC Input: -4.5dB, Ouptut -6.75dB
+ // Above knee 1/4, Below knee 1/2
+ // Max gain 24 / Min gain -12
+ wm8994_write(codec, WM8994_AIF1_DRC1_1,
+ WM8994_AIF1DRC1_SIG_DET_MODE |
+ WM8994_AIF1DRC1_QR |
+ WM8994_AIF1DRC1_ANTICLIP |
+ WM8994_AIF1ADC1L_DRC_ENA);
+ wm8994_write(codec, WM8994_AIF1_DRC1_2, 0x0846);
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, 0x0011);
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, 0x00C9);
+ break;
+ case 4:
+ // ULTRA LOUD:
+ // Original - 36 dB - 30 dB IN1L_VOL1=00000 (-16.5 dB)
+ // +30dB input mixer gain deactivated
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, 0x0100);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3,
+ WM8994_IN1L_TO_MIXINL);
+ // DRC Input: -7.5dB, Ouptut -6dB
+ // Above knee 1/8, Below knee 1/4
+ // Max gain 36 / Min gain -12
+ wm8994_write(codec, WM8994_AIF1_DRC1_1,
+ WM8994_AIF1DRC1_SIG_DET_MODE |
+ WM8994_AIF1DRC1_QR |
+ WM8994_AIF1DRC1_ANTICLIP |
+ WM8994_AIF1ADC1L_DRC_ENA);
+ wm8994_write(codec, WM8994_AIF1_DRC1_2, 0x0847);
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, 0x001A);
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, 0x00C9);
+ break;
+ default:
+ // make sure recording_preset is the default
+ recording_preset = 1;
+ // New Balanced: Original - 16.5 dB
+ // IN1L_VOL1=01101 (+27 dB)
+ // +30dB input mixer gain deactivated
+ wm8994_write(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME, 0x055D);
+ wm8994_write(codec, WM8994_INPUT_MIXER_3,
+ WM8994_IN1L_TO_MIXINL);
+ // DRC Input: -18.5dB, Ouptut -9dB
+ // Above knee 1/8, Below knee 1/2
+ // Max gain 18 / Min gain -12
+ wm8994_write(codec, WM8994_AIF1_DRC1_1,
+ WM8994_AIF1DRC1_SIG_DET_MODE |
+ WM8994_AIF1DRC1_QR |
+ WM8994_AIF1DRC1_ANTICLIP |
+ WM8994_AIF1ADC1L_DRC_ENA);
+ wm8994_write(codec, WM8994_AIF1_DRC1_2, 0x0845);
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, 0x0019);
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, 0x030C);
+ break;
+ }
+}
+#endif
+
+bool is_path(int unified_path)
+{
+ DECLARE_WM8994(codec);
+
+ switch (unified_path) {
+ // speaker
+ case SPEAKER:
+#ifdef GALAXY_TAB
+ return (wm8994->cur_path == SPK
+ || wm8994->cur_path == RING_SPK
+ || wm8994->fmradio_path == FMR_SPK
+ || wm8994->fmradio_path == FMR_SPK_MIX);
+#else
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+ return (wm8994->cur_path == SPK
+ || wm8994->cur_path == SPK_HP);
+#else
+ return (wm8994->cur_path == SPK
+ || wm8994->cur_path == RING_SPK);
+#endif
+#endif
+
+ // headphones
+ case HEADPHONES:
+
+#ifdef NEXUS_S
+ return (wm8994->cur_path == HP
+ || wm8994->cur_path == HP_NO_MIC);
+#else
+#ifdef GALAXY_TAB
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+ return (wm8994->cur_path == HP
+ || wm8994->cur_path == HP_NO_MIC);
+#else
+ return (wm8994->cur_path == HP3P
+ || wm8994->cur_path == HP4P
+ || wm8994->fmradio_path == FMR_HP);
+#endif
+#else
+#ifdef M110S
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+ return (wm8994->cur_path == HP
+ || wm8994->cur_path == HP_NO_MIC);
+#else
+ return (wm8994->cur_path == HP);
+#endif
+#else
+#ifdef GALAXY_TAB_TEGRA
+ return (wm8994->cur_path == HP
+ || wm8994->cur_path == HP_NO_MIC);
+#else
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+ return (wm8994->cur_path == HP
+ || wm8994->cur_path == HP_NO_MIC
+ || wm8994->fmradio_path == FMR_HP);
+#else
+ return (wm8994->cur_path == HP
+ || wm8994->fmradio_path == FMR_HP);
+#endif
+#endif
+#endif
+#endif
+#endif
+
+ // FM Radio on headphones
+ case RADIO_HEADPHONES:
+#ifdef NEXUS_S
+ return false;
+#else
+#ifdef M110S
+ return false;
+#else
+#ifdef GALAXY_TAB_TEGRA
+ return false;
+#else
+#ifdef GALAXY_TAB
+ return false;
+#else
+ return (wm8994->codec_state & FMRADIO_ACTIVE)
+ && (wm8994->fmradio_path == FMR_HP);
+#endif
+#endif
+#endif
+#endif
+
+ // Standard recording presets
+ // for M110S Gingerbread: added check non call
+ case MAIN_MICROPHONE:
+ return (wm8994->codec_state & CAPTURE_ACTIVE)
+ && (wm8994->rec_path == MAIN)
+ && !(wm8994->codec_state & CALL_ACTIVE);
+
+ }
+ return false;
+}
+
+bool is_path_media_or_fm_no_call_no_record()
+{
+
+ DECLARE_WM8994(codec);
+
+ if ((is_path(HEADPHONES)
+ && (wm8994->codec_state & PLAYBACK_ACTIVE)
+ && (wm8994->stream_state & PCM_STREAM_PLAYBACK)
+ && !(wm8994->codec_state & CALL_ACTIVE)
+ && (wm8994->rec_path == MIC_OFF)
+ ) || is_path(RADIO_HEADPHONES))
+ return true;
+
+ return false;
+}
+
+#ifdef NEXUS_S
+void update_speaker_tuning(bool with_mute)
+{
+ DECLARE_WM8994(codec);
+
+ if (!(is_path(SPEAKER) || (wm8994->codec_state & CALL_ACTIVE)))
+ return;
+
+ if (speaker_tuning) {
+ // DRC settings
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, 0x0010);
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, 0x00EB);
+
+ // hardware EQ
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_1, 0x041D);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_2, 0x4C00);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_A, 0x0FE3);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_B, 0x0403);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_PG, 0x0074);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_A, 0x1F03);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_B, 0xF0F9);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_C, 0x040A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_PG, 0x03DA);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_A, 0x1ED2);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_B, 0xF11A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_C, 0x040A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_PG, 0x045D);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_4_A, 0x0E76);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_4_B, 0xFCE4);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_4_C, 0x040A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_4_PG, 0x330D);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_5_A, 0xFC8F);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_5_B, 0x0400);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_5_PG, 0x323C);
+
+ // Speaker Boost tuning
+ wm8994_write(codec, WM8994_CLASSD, 0x0170);
+ } else {
+ // DRC settings
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, 0x0028);
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, 0x0186);
+
+ // hardware EQ
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_1, 0x0019);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_2, 0x6280);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_A, 0x0FC3);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_B, 0x03FD);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_1_PG, 0x00F4);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_A, 0x1F30);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_B, 0xF0CD);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_C, 0x040A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_2_PG, 0x032C);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_A, 0x1C52);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_B, 0xF379);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_C, 0x040A);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_BAND_3_PG, 0x0DC1);
+ wm8994_write(codec, WM8994_CLASSD, 0x0170);
+
+ // Speaker Boost tuning
+ wm8994_write(codec, WM8994_CLASSD, 0x0168);
+ }
+}
+#endif
+
+unsigned short osr128_get_value(unsigned short val)
+{
+ if (dac_osr128 == 1)
+ val |= WM8994_DAC_OSR128;
+ else
+ val &= ~WM8994_DAC_OSR128;
+
+ if (adc_osr128 == 1)
+ val |= WM8994_ADC_OSR128;
+ else
+ val &= ~WM8994_ADC_OSR128;
+
+ return val;
+}
+
+void update_osr128(bool with_mute)
+{
+ unsigned short val;
+ val = osr128_get_value(wm8994_read(codec, WM8994_OVERSAMPLING));
+ bypass_write_hook = true;
+ wm8994_write(codec, WM8994_OVERSAMPLING, val);
+ bypass_write_hook = false;
+}
+
+#ifndef GALAXY_TAB_TEGRA
+unsigned short fll_tuning_get_value(unsigned short val)
+{
+ val = (val >> WM8994_FLL1_GAIN_WIDTH << WM8994_FLL1_GAIN_WIDTH);
+ if (fll_tuning == 1)
+ val |= 5;
+
+ return val;
+}
+
+void update_fll_tuning(bool with_mute)
+{
+ unsigned short val;
+ val = fll_tuning_get_value(wm8994_read(codec, WM8994_FLL1_CONTROL_4));
+ bypass_write_hook = true;
+ wm8994_write(codec, WM8994_FLL1_CONTROL_4, val);
+ bypass_write_hook = false;
+}
+#endif
+
+unsigned short mono_downmix_get_value(unsigned short val, bool can_reverse)
+{
+ DECLARE_WM8994(codec);
+
+ // Takes care not switching to Stereo on speaker or during a call
+ if (!is_path(SPEAKER) && !(wm8994->codec_state & CALL_ACTIVE)) {
+ if (mono_downmix) {
+ val |= WM8994_AIF1DAC1_MONO;
+ } else {
+ if (can_reverse)
+ val &= ~WM8994_AIF1DAC1_MONO;
+ }
+ }
+
+ return val;
+}
+
+void update_mono_downmix(bool with_mute)
+{
+ unsigned short val1, val2, val3;
+ val1 = mono_downmix_get_value(wm8994_read
+ (codec, WM8994_AIF1_DAC1_FILTERS_1),
+ true);
+ val2 = mono_downmix_get_value(wm8994_read
+ (codec, WM8994_AIF1_DAC2_FILTERS_1),
+ true);
+ val3 = mono_downmix_get_value(wm8994_read
+ (codec, WM8994_AIF2_DAC_FILTERS_1),
+ true);
+
+ bypass_write_hook = true;
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_1, val1);
+ wm8994_write(codec, WM8994_AIF1_DAC2_FILTERS_1, val2);
+ wm8994_write(codec, WM8994_AIF2_DAC_FILTERS_1, val3);
+ bypass_write_hook = false;
+}
+
+unsigned short dac_direct_get_value(unsigned short val, bool can_reverse)
+{
+ if (is_path_media_or_fm_no_call_no_record()) {
+
+ if (dac_direct) {
+ if (val == WM8994_DAC1L_TO_MIXOUTL)
+ return WM8994_DAC1L_TO_HPOUT1L;
+ } else {
+ if (val == WM8994_DAC1L_TO_HPOUT1L && can_reverse)
+ return WM8994_DAC1L_TO_MIXOUTL;
+ }
+ }
+
+ return val;
+}
+
+void update_dac_direct(bool with_mute)
+{
+ unsigned short val1, val2;
+ val1 = dac_direct_get_value(wm8994_read(codec,
+ WM8994_OUTPUT_MIXER_1), true);
+ val2 = dac_direct_get_value(wm8994_read(codec,
+ WM8994_OUTPUT_MIXER_2), true);
+
+ bypass_write_hook = true;
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_1, val1);
+ wm8994_write(codec, WM8994_OUTPUT_MIXER_2, val2);
+ bypass_write_hook = false;
+}
+
+unsigned short digital_gain_get_value(unsigned short val)
+{
+ // AIF gain to 0dB
+ int aif_gain = 0xC0;
+ int i;
+ int step = -375;
+
+ if (is_path_media_or_fm_no_call_no_record()) {
+
+ if (digital_gain <= 0) {
+ // clear the actual DAC volume for this value
+ val &= ~(WM8994_DAC1R_VOL_MASK);
+
+ // calculation with round
+ i = ((digital_gain * 10 / step) + 5) / 10;
+ aif_gain -= i;
+ val |= aif_gain;
+
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: digital gain: %d mdB, "
+ "%d mdB steps: %d, "
+ "real AIF gain: %d mdB\n",
+ digital_gain, step, i, i * step);
+ }
+ }
+
+ return val;
+}
+
+void update_digital_gain(bool with_mute)
+{
+ unsigned short val1, val2;
+ val1 = digital_gain_get_value(wm8994_read(codec,
+ WM8994_AIF1_DAC1_LEFT_VOLUME));
+ val2 = digital_gain_get_value(wm8994_read(codec,
+ WM8994_AIF1_DAC1_RIGHT_VOLUME));
+
+ bypass_write_hook = true;
+ wm8994_write(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
+ WM8994_DAC1_VU | val1);
+ wm8994_write(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
+ WM8994_DAC1_VU | val2);
+ bypass_write_hook = false;
+}
+
+void update_headphone_eq(bool update_bands)
+{
+ int gains_1;
+ int gains_2;
+
+ if (!is_path_media_or_fm_no_call_no_record()) {
+ // don't apply the EQ
+ return;
+ }
+
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: EQ gains (dB): %hd, %hd, %hd, %hd, %hd\n",
+ eq_gains[0], eq_gains[1], eq_gains[2],
+ eq_gains[3], eq_gains[4]);
+
+ gains_1 =
+ ((eq_gains[0] + 12) << WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT) |
+ ((eq_gains[1] + 12) << WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT) |
+ ((eq_gains[2] + 12) << WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT) |
+ headphone_eq;
+
+ gains_2 =
+ ((eq_gains[3] + 12) << WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT) |
+ ((eq_gains[4] + 12) << WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_1, gains_1);
+ wm8994_write(codec, WM8994_AIF1_DAC1_EQ_GAINS_2, gains_2);
+
+ // don't send EQ configuration if its not enabled
+ if (!headphone_eq)
+ return;
+
+ if (update_bands)
+ update_headphone_eq_bands();
+}
+
+void update_headphone_eq_bands()
+{
+ int i;
+ int j;
+ int k = 0;
+ int first_reg = WM8994_AIF1_DAC1_EQ_BAND_1_A;
+
+ for (i = 0; i < ARRAY_SIZE(eq_band_values); i++) {
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: send EQ Band %d\n", i + 1);
+
+ for (j = 0; j < eq_bands[i]; j++) {
+ wm8994_write(codec,
+ first_reg + k, eq_band_values[i][j]);
+ k++;
+ }
+ }
+}
+
+void smooth_apply_eq_band_gain(int band, int start, int end, bool current_state)
+{
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: EQ smooth transition for Band %d "
+ "from %d to %d\n", band + 1, start, end);
+
+ if (start == end) {
+ if (end != 0)
+ update_headphone_eq(true);
+ else
+ update_headphone_eq(false);
+ return;
+ }
+
+ if (current_state)
+ update_headphone_eq_bands();
+
+ while (start != end) {
+ if (start < end)
+ start++;
+ else
+ start--;
+
+ eq_gains[band] = start;
+ update_headphone_eq(false);
+ }
+}
+
+void update_stereo_expansion(bool with_mute)
+{
+ short unsigned int val;
+
+ val = wm8994_read(codec, WM8994_AIF1_DAC1_FILTERS_2);
+ if (stereo_expansion) {
+ val &= ~(WM8994_AIF1DAC1_3D_GAIN_MASK);
+ val |= (stereo_expansion_gain << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
+ }
+ val &= ~(WM8994_AIF1DAC1_3D_ENA_MASK);
+ val |= (stereo_expansion << WM8994_AIF1DAC1_3D_ENA_SHIFT);
+
+ wm8994_write(codec, WM8994_AIF1_DAC1_FILTERS_2, val);
+}
+
+void load_current_eq_values()
+{
+ int i;
+ int j;
+ int k = 0;
+ int first_reg = WM8994_AIF1_DAC1_EQ_BAND_1_A;
+
+ for (i = 0; i < ARRAY_SIZE(eq_band_values); i++)
+ for (j = 0; j < eq_bands[i]; j++) {
+ eq_band_values[i][j] =
+ wm8994_read(codec, first_reg + k);
+ k++;
+ }
+}
+
+void apply_saturation_prevention_drc()
+{
+ unsigned short val;
+ unsigned short drc_gain = 0;
+ int i;
+ int step = 750;
+
+ // don't apply the limiter if not playing media
+ // (exclude FM radio, it has its own DRC settings)
+ if (!is_path_media_or_fm_no_call_no_record()
+ || is_path(RADIO_HEADPHONES))
+ return;
+
+ // don't apply the limiter without stereo_expansion or headphone_eq
+ // or a positive digital gain
+ if (!(stereo_expansion
+ || headphone_eq
+ || digital_gain >= 0))
+ return;
+
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: apply saturation prevention DRC\n");
+
+ // configure the DRC to avoid saturation: not actually compress signal
+ // gain is unmodified. Should affect only what's higher than 0 dBFS
+
+ // tune Attack & Decacy values
+ val = wm8994_read(codec, WM8994_AIF1_DRC1_2);
+ val &= ~(WM8994_AIF1DRC1_ATK_MASK);
+ val &= ~(WM8994_AIF1DRC1_DCY_MASK);
+ val |= (0x1 << WM8994_AIF1DRC1_ATK_SHIFT);
+ val |= (0x4 << WM8994_AIF1DRC1_DCY_SHIFT);
+
+ // set DRC maximum gain to 36 dB
+ val &= ~(WM8994_AIF1DRC1_MAXGAIN_MASK);
+ val |= (0x3 << WM8994_AIF1DRC1_MAXGAIN_SHIFT);
+
+ wm8994_write(codec, WM8994_AIF1_DRC1_2, val);
+
+ // Above knee: flat (what really avoid the saturation)
+ val = wm8994_read(codec, WM8994_AIF1_DRC1_3);
+ val |= (0x5 << WM8994_AIF1DRC1_HI_COMP_SHIFT);
+ wm8994_write(codec, WM8994_AIF1_DRC1_3, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_DRC1_1);
+ // disable Quick Release and Anti Clip
+ // both do do more harm than good for this particular usage
+ val &= ~(WM8994_AIF1DRC1_QR_MASK);
+ val &= ~(WM8994_AIF1DRC1_ANTICLIP_MASK);
+
+ // enable DRC
+ val &= ~(WM8994_AIF1DAC1_DRC_ENA_MASK);
+ val |= WM8994_AIF1DAC1_DRC_ENA;
+ wm8994_write(codec, WM8994_AIF1_DRC1_1, val);
+
+ val = wm8994_read(codec, WM8994_AIF1_DRC1_4);
+ val &= ~(WM8994_AIF1DRC1_KNEE_IP_MASK);
+
+ if (digital_gain >= 0) {
+ // deal with positive digital gains
+ i = ((digital_gain * 10 / step) + 5) / 10;
+ drc_gain += i;
+ val |= (drc_gain << WM8994_AIF1DRC1_KNEE_IP_SHIFT);
+
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: digital gain: %d mdB, "
+ "%d mdB steps: %d, real DRC gain: %d mdB\n",
+ digital_gain, step, i, i * step);
+
+ }
+ wm8994_write(codec, WM8994_AIF1_DRC1_4, val);
+}
+
+/*
+ *
+ * Declaring the controling misc devices
+ *
+ */
+static ssize_t debug_log_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%u\n", debug_log_level);
+}
+
+static ssize_t debug_log_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ sscanf(buf, "%hu", &debug_log_level);
+ return size;
+}
+
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+static ssize_t headphone_amplifier_level_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ // output median of left and right headphone amplifier volumes
+ return sprintf(buf, "%u\n", (hp_level[0] + hp_level[1]) / 2);
+}
+
+static ssize_t headphone_amplifier_level_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ unsigned short vol;
+ if (sscanf(buf, "%hu", &vol) == 1) {
+
+ // hard limit to 62 because 63 introduces distortions
+ if (vol > 62)
+ vol = 62;
+
+ // left and right are set to the same volumes by this control
+ hp_level[0] = hp_level[1] = vol;
+
+ update_digital_gain(false);
+ update_hpvol(true);
+ }
+ return size;
+}
+#endif
+
+#ifdef NEXUS_S
+DECLARE_BOOL_SHOW(speaker_tuning);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(speaker_tuning,
+ update_speaker_tuning,
+ false);
+#endif
+
+#ifdef CONFIG_SND_VOODOO_FM
+DECLARE_BOOL_SHOW(fm_radio_headset_restore_bass);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(fm_radio_headset_restore_bass,
+ update_fm_radio_headset_restore_freqs,
+ true);
+
+DECLARE_BOOL_SHOW(fm_radio_headset_restore_highs);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(fm_radio_headset_restore_highs,
+ update_fm_radio_headset_restore_freqs,
+ true);
+
+DECLARE_BOOL_SHOW(fm_radio_headset_normalize_gain);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(fm_radio_headset_normalize_gain,
+ update_fm_radio_headset_normalize_gain,
+ false);
+#endif
+
+#ifdef CONFIG_SND_VOODOO_RECORD_PRESETS
+static ssize_t recording_preset_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", recording_preset);
+}
+
+static ssize_t recording_preset_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ unsigned short preset_number;
+ if (sscanf(buf, "%hu", &preset_number) == 1) {
+ recording_preset = preset_number;
+ update_recording_preset(false);
+ }
+ return size;
+}
+#endif
+
+DECLARE_BOOL_SHOW(dac_osr128);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(dac_osr128,
+ update_osr128,
+ false);
+
+DECLARE_BOOL_SHOW(adc_osr128);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(adc_osr128,
+ update_osr128,
+ false);
+
+#ifndef GALAXY_TAB_TEGRA
+DECLARE_BOOL_SHOW(fll_tuning);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(fll_tuning,
+ update_fll_tuning,
+ false);
+#endif
+
+DECLARE_BOOL_SHOW(mono_downmix);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(mono_downmix,
+ update_mono_downmix,
+ false);
+
+DECLARE_BOOL_SHOW(dac_direct);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(dac_direct,
+ update_dac_direct,
+ false);
+
+static ssize_t digital_gain_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", digital_gain);
+}
+
+static ssize_t digital_gain_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ int new_digital_gain;
+ if (sscanf(buf, "%d", &new_digital_gain) == 1) {
+ if (new_digital_gain <= 36000 && new_digital_gain >= -71625) {
+ if (new_digital_gain > digital_gain) {
+ // reduce analog volume first
+ digital_gain = new_digital_gain;
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+ update_hpvol(false);
+#endif
+ update_digital_gain(false);
+ } else {
+ // reduce digital volume first
+ digital_gain = new_digital_gain;
+ update_digital_gain(false);
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+ update_hpvol(false);
+#endif
+ }
+ }
+ apply_saturation_prevention_drc();
+ }
+ return size;
+}
+
+DECLARE_BOOL_SHOW(headphone_eq);
+static ssize_t headphone_eq_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ unsigned short state;
+ bool current_state;
+ int i;
+ short eq_gains_copy[ARRAY_SIZE(eq_gains)];
+
+ if (sscanf(buf, "%hu", &state) == 1) {
+ current_state = state == 0 ? false : true;
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: EQ activation: %u\n", state);
+
+ if (current_state) {
+ // fade from 0dB each EQ band
+ headphone_eq = current_state;
+ for (i = 0; i < ARRAY_SIZE(eq_bands); i++)
+ smooth_apply_eq_band_gain(i, 0, eq_gains[i],
+ current_state);
+ } else {
+ // fade to 0dB each EQ band
+ for (i = 0; i < ARRAY_SIZE(eq_bands); i++) {
+ eq_gains_copy[i] = eq_gains[i];
+ smooth_apply_eq_band_gain(i, eq_gains[i], 0,
+ current_state);
+ }
+ // restore original gains in driver memory not codec
+ for (i = 0; i < ARRAY_SIZE(eq_bands); i++)
+ eq_gains[i] = eq_gains_copy[i];
+ headphone_eq = current_state;
+ }
+ }
+ return size;
+}
+
+DECLARE_EQ_GAIN_SHOW(1);
+DECLARE_EQ_GAIN_STORE(1);
+DECLARE_EQ_GAIN_SHOW(2);
+DECLARE_EQ_GAIN_STORE(2);
+DECLARE_EQ_GAIN_SHOW(3);
+DECLARE_EQ_GAIN_STORE(3);
+DECLARE_EQ_GAIN_SHOW(4);
+DECLARE_EQ_GAIN_STORE(4);
+DECLARE_EQ_GAIN_SHOW(5);
+DECLARE_EQ_GAIN_STORE(5);
+
+static ssize_t headphone_eq_bands_values_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int i;
+ int j;
+ int k = 0;
+ int first_reg = WM8994_AIF1_DAC1_EQ_BAND_1_A;
+ int bands_size = ARRAY_SIZE(eq_bands);
+ char *name;
+
+ for (i = 0; i < bands_size; i++)
+ for (j = 0; j < eq_bands[i]; j++) {
+
+ // display 3-coef bands properly (hi & lo shelf)
+ if (j + 1 == eq_bands[i])
+ name = eq_band_coef_names[3];
+ else
+ name = eq_band_coef_names[j];
+
+ sprintf(buf, "%s%d %s 0x%04X\n", buf,
+ i + 1, name,
+ wm8994_read(codec, first_reg + k));
+ k++;
+ }
+
+ return sprintf(buf, "%s", buf);
+}
+
+static ssize_t headphone_eq_bands_values_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ int i;
+ short unsigned int val;
+ short unsigned int band;
+ char coef_name[2];
+ unsigned int bytes_read = 0;
+
+ while (sscanf(buf, "%hu %s %hx%n",
+ &band, coef_name, &val, &bytes_read) == 3) {
+
+ buf += bytes_read;
+
+ if (band < 1 || band > 5)
+ continue;
+
+ for (i = 0; i < ARRAY_SIZE(eq_band_coef_names); i++) {
+ // loop through band coefficient letters
+ if (strncmp(eq_band_coef_names[i], coef_name, 2) == 0) {
+ if (eq_bands[band - 1] == 3 && i == 3)
+ // deal with high and low shelves
+ eq_band_values[band - 1][2] = val;
+ else
+ // parametric bands
+ eq_band_values[band - 1][i] = val;
+
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: read EQ from "
+ "sysfs: EQ Band %hd %s: 0x%04X\n"
+ , band, coef_name, val);
+ break;
+ }
+ }
+ }
+
+ return size;
+}
+
+DECLARE_BOOL_SHOW(stereo_expansion);
+DECLARE_BOOL_STORE_UPDATE_WITH_MUTE(stereo_expansion,
+ update_stereo_expansion,
+ false);
+
+static ssize_t stereo_expansion_gain_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%u\n", stereo_expansion_gain);
+}
+
+static ssize_t stereo_expansion_gain_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ short unsigned val;
+
+ if (sscanf(buf, "%hu", &val) == 1)
+ if (val >= 0 && val < 32) {
+ stereo_expansion_gain = val;
+ update_stereo_expansion(false);
+ }
+
+ return size;
+}
+
+#ifdef CONFIG_SND_VOODOO_DEVELOPMENT
+static ssize_t show_wm8994_register_dump(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ // modified version of register_dump from wm8994_aries.c
+ // r = wm8994 register
+ int r;
+
+ for (r = 0; r <= 0x6; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x15, wm8994_read(codec, 0x15));
+
+ for (r = 0x18; r <= 0x3C; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x4C, wm8994_read(codec, 0x4C));
+
+ for (r = 0x51; r <= 0x5C; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x60, wm8994_read(codec, 0x60));
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x101, wm8994_read(codec, 0x101));
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x110, wm8994_read(codec, 0x110));
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x111, wm8994_read(codec, 0x111));
+
+ for (r = 0x200; r <= 0x212; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x220; r <= 0x224; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x240; r <= 0x244; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x300; r <= 0x317; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x400; r <= 0x411; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x420; r <= 0x423; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x440; r <= 0x444; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x450; r <= 0x454; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x480; r <= 0x493; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x4A0; r <= 0x4B3; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x500; r <= 0x503; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x510, wm8994_read(codec, 0x510));
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x520, wm8994_read(codec, 0x520));
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x521, wm8994_read(codec, 0x521));
+
+ for (r = 0x540; r <= 0x544; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x580; r <= 0x593; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ for (r = 0x600; r <= 0x614; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x620, wm8994_read(codec, 0x620));
+ sprintf(buf, "%s0x%X 0x%X\n", buf, 0x621, wm8994_read(codec, 0x621));
+
+ for (r = 0x700; r <= 0x70A; r++)
+ sprintf(buf, "%s0x%X 0x%X\n", buf, r, wm8994_read(codec, r));
+
+ return sprintf(buf, "%s", buf);
+}
+
+static ssize_t store_wm8994_write(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ short unsigned int reg = 0;
+ short unsigned int val = 0;
+ int unsigned bytes_read = 0;
+
+ while (sscanf(buf, "%hx %hx%n", &reg, &val, &bytes_read) == 2) {
+ buf += bytes_read;
+ if (debug_log(LOG_INFOS))
+ printk("Voodoo sound: read from sysfs: %X, %X\n",
+ reg, val);
+
+ bypass_write_hook = true;
+ wm8994_write(codec, reg, val);
+ bypass_write_hook = false;
+ }
+ return size;
+}
+#endif
+
+static ssize_t voodoo_sound_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%u\n", VOODOO_SOUND_VERSION);
+}
+
+#ifndef MODULE
+DECLARE_BOOL_SHOW(enable);
+static ssize_t enable_store(struct device *dev,
+ struct device_attribute *attr, const char *buf,
+ size_t size)
+{
+ unsigned short state;
+ bool bool_state;
+ if (sscanf(buf, "%hu", &state) == 1) {
+ bool_state = state == 0 ? false : true;
+ if (state != enable) {
+ enable = bool_state;
+ update_enable();
+ }
+ }
+ return size;
+}
+#endif
+
+static DEVICE_ATTR(debug_log, S_IRUGO | S_IWUGO,
+ debug_log_show,
+ debug_log_store);
+
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+static DEVICE_ATTR(headphone_amplifier_level, S_IRUGO | S_IWUGO,
+ headphone_amplifier_level_show,
+ headphone_amplifier_level_store);
+#endif
+
+#ifdef NEXUS_S
+static DEVICE_ATTR(speaker_tuning, S_IRUGO | S_IWUGO,
+ speaker_tuning_show,
+ speaker_tuning_store);
+#endif
+
+#ifdef CONFIG_SND_VOODOO_FM
+static DEVICE_ATTR(fm_radio_headset_restore_bass, S_IRUGO | S_IWUGO,
+ fm_radio_headset_restore_bass_show,
+ fm_radio_headset_restore_bass_store);
+
+static DEVICE_ATTR(fm_radio_headset_restore_highs, S_IRUGO | S_IWUGO,
+ fm_radio_headset_restore_highs_show,
+ fm_radio_headset_restore_highs_store);
+
+static DEVICE_ATTR(fm_radio_headset_normalize_gain, S_IRUGO | S_IWUGO,
+ fm_radio_headset_normalize_gain_show,
+ fm_radio_headset_normalize_gain_store);
+#endif
+
+#ifdef CONFIG_SND_VOODOO_RECORD_PRESETS
+static DEVICE_ATTR(recording_preset, S_IRUGO | S_IWUGO,
+ recording_preset_show,
+ recording_preset_store);
+#endif
+
+static DEVICE_ATTR(dac_osr128, S_IRUGO | S_IWUGO,
+ dac_osr128_show,
+ dac_osr128_store);
+
+static DEVICE_ATTR(adc_osr128, S_IRUGO | S_IWUGO,
+ adc_osr128_show,
+ adc_osr128_store);
+
+#ifndef GALAXY_TAB_TEGRA
+static DEVICE_ATTR(fll_tuning, S_IRUGO | S_IWUGO,
+ fll_tuning_show,
+ fll_tuning_store);
+#endif
+
+static DEVICE_ATTR(dac_direct, S_IRUGO | S_IWUGO,
+ dac_direct_show,
+ dac_direct_store);
+
+static DEVICE_ATTR(digital_gain, S_IRUGO | S_IWUGO,
+ digital_gain_show,
+ digital_gain_store);
+
+static DEVICE_ATTR(headphone_eq, S_IRUGO | S_IWUGO,
+ headphone_eq_show,
+ headphone_eq_store);
+
+static DEVICE_ATTR(headphone_eq_b1_gain, S_IRUGO | S_IWUGO,
+ headphone_eq_b1_gain_show,
+ headphone_eq_b1_gain_store);
+
+static DEVICE_ATTR(headphone_eq_b2_gain, S_IRUGO | S_IWUGO,
+ headphone_eq_b2_gain_show,
+ headphone_eq_b2_gain_store);
+
+static DEVICE_ATTR(headphone_eq_b3_gain, S_IRUGO | S_IWUGO,
+ headphone_eq_b3_gain_show,
+ headphone_eq_b3_gain_store);
+
+static DEVICE_ATTR(headphone_eq_b4_gain, S_IRUGO | S_IWUGO,
+ headphone_eq_b4_gain_show,
+ headphone_eq_b4_gain_store);
+
+static DEVICE_ATTR(headphone_eq_b5_gain, S_IRUGO | S_IWUGO,
+ headphone_eq_b5_gain_show,
+ headphone_eq_b5_gain_store);
+
+static DEVICE_ATTR(headphone_eq_bands_values, S_IRUGO | S_IWUGO,
+ headphone_eq_bands_values_show,
+ headphone_eq_bands_values_store);
+
+static DEVICE_ATTR(stereo_expansion, S_IRUGO | S_IWUGO,
+ stereo_expansion_show,
+ stereo_expansion_store);
+
+static DEVICE_ATTR(stereo_expansion_gain, S_IRUGO | S_IWUGO,
+ stereo_expansion_gain_show,
+ stereo_expansion_gain_store);
+
+static DEVICE_ATTR(mono_downmix, S_IRUGO | S_IWUGO,
+ mono_downmix_show,
+ mono_downmix_store);
+
+#ifdef CONFIG_SND_VOODOO_DEVELOPMENT
+static DEVICE_ATTR(wm8994_register_dump, S_IRUGO,
+ show_wm8994_register_dump,
+ NULL);
+
+static DEVICE_ATTR(wm8994_write, S_IWUSR,
+ NULL,
+ store_wm8994_write);
+#endif
+
+static DEVICE_ATTR(version, S_IRUGO,
+ voodoo_sound_version,
+ NULL);
+
+#ifndef MODULE
+static DEVICE_ATTR(enable, S_IRUGO | S_IWUGO,
+ enable_show,
+ enable_store);
+#endif
+
+#ifdef MODULE
+static DEVICE_ATTR(module, 0,
+ NULL,
+ NULL);
+#endif
+
+static struct attribute *voodoo_sound_attributes[] = {
+ &dev_attr_debug_log.attr,
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+ &dev_attr_headphone_amplifier_level.attr,
+#endif
+#ifdef NEXUS_S
+ &dev_attr_speaker_tuning.attr,
+#endif
+#ifdef CONFIG_SND_VOODOO_FM
+ &dev_attr_fm_radio_headset_restore_bass.attr,
+ &dev_attr_fm_radio_headset_restore_highs.attr,
+ &dev_attr_fm_radio_headset_normalize_gain.attr,
+#endif
+#ifdef CONFIG_SND_VOODOO_RECORD_PRESETS
+ &dev_attr_recording_preset.attr,
+#endif
+ &dev_attr_dac_osr128.attr,
+ &dev_attr_adc_osr128.attr,
+#ifndef GALAXY_TAB_TEGRA
+ &dev_attr_fll_tuning.attr,
+#endif
+ &dev_attr_dac_direct.attr,
+ &dev_attr_digital_gain.attr,
+ &dev_attr_headphone_eq.attr,
+ &dev_attr_headphone_eq_b1_gain.attr,
+ &dev_attr_headphone_eq_b2_gain.attr,
+ &dev_attr_headphone_eq_b3_gain.attr,
+ &dev_attr_headphone_eq_b4_gain.attr,
+ &dev_attr_headphone_eq_b5_gain.attr,
+ &dev_attr_headphone_eq_bands_values.attr,
+ &dev_attr_stereo_expansion.attr,
+ &dev_attr_stereo_expansion_gain.attr,
+ &dev_attr_mono_downmix.attr,
+#ifdef CONFIG_SND_VOODOO_DEVELOPMENT
+ &dev_attr_wm8994_register_dump.attr,
+ &dev_attr_wm8994_write.attr,
+#endif
+#ifdef MODULE
+ &dev_attr_module.attr,
+#endif
+ &dev_attr_version.attr,
+ NULL
+};
+
+#ifndef MODULE
+static struct attribute *voodoo_sound_control_attributes[] = {
+ &dev_attr_enable.attr,
+ NULL
+};
+#endif
+
+static struct attribute_group voodoo_sound_group = {
+ .attrs = voodoo_sound_attributes,
+};
+
+#ifndef MODULE
+static struct attribute_group voodoo_sound_control_group = {
+ .attrs = voodoo_sound_control_attributes,
+};
+#endif
+
+static struct miscdevice voodoo_sound_device = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = "voodoo_sound",
+};
+
+#ifndef MODULE
+static struct miscdevice voodoo_sound_control_device = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = "voodoo_sound_control",
+};
+#endif
+
+void voodoo_hook_wm8994_pcm_remove()
+{
+ printk("Voodoo sound: removing driver v%d\n", VOODOO_SOUND_VERSION);
+ sysfs_remove_group(&voodoo_sound_device.this_device->kobj,
+ &voodoo_sound_group);
+ misc_deregister(&voodoo_sound_device);
+}
+
+void update_enable()
+{
+ if (enable) {
+ printk("Voodoo sound: initializing driver v%d\n",
+ VOODOO_SOUND_VERSION);
+
+#ifdef CONFIG_SND_VOODOO_DEVELOPMENT
+ printk("Voodoo sound: codec development tools enabled\n");
+#endif
+
+ misc_register(&voodoo_sound_device);
+ if (sysfs_create_group(&voodoo_sound_device.this_device->kobj,
+ &voodoo_sound_group) < 0) {
+ printk("%s sysfs_create_group fail\n", __FUNCTION__);
+ pr_err("Failed to create sysfs group for (%s)!\n",
+ voodoo_sound_device.name);
+ }
+ } else
+ voodoo_hook_wm8994_pcm_remove();
+}
+
+/*
+ *
+ * Driver Hooks
+ *
+ */
+
+#ifdef CONFIG_SND_VOODOO_FM
+void voodoo_hook_fmradio_headset()
+{
+ // global kill switch
+ if (!enable)
+ return;
+
+ if (!fm_radio_headset_restore_bass
+ && !fm_radio_headset_restore_highs
+ && !fm_radio_headset_normalize_gain)
+ return;
+
+ update_fm_radio_headset_restore_freqs(false);
+ update_fm_radio_headset_normalize_gain(false);
+}
+#endif
+
+#ifdef CONFIG_SND_VOODOO_RECORD_PRESETS
+void voodoo_hook_record_main_mic()
+{
+ // global kill switch
+ if (!enable)
+ return;
+
+ if (recording_preset == 0)
+ return;
+
+ origin_recgain = wm8994_read(codec, WM8994_LEFT_LINE_INPUT_1_2_VOLUME);
+ origin_recgain_mixer = wm8994_read(codec, WM8994_INPUT_MIXER_3);
+ update_recording_preset(false);
+}
+#endif
+
+#ifdef NEXUS_S
+void voodoo_hook_playback_speaker()
+{
+ // global kill switch
+ if (!enable)
+ return;
+ if (!speaker_tuning)
+ return;
+
+ update_speaker_tuning(false);
+}
+#endif
+
+unsigned int voodoo_hook_wm8994_write(struct snd_soc_codec *codec_,
+ unsigned int reg, unsigned int value)
+{
+ DECLARE_WM8994(codec_);
+
+ // global kill switch
+ if (!enable)
+ return value;
+
+ // modify some registers before those being written to the codec
+ // be sure our pointer to codec is up to date
+ codec = codec_;
+
+ if (!bypass_write_hook) {
+
+#ifdef CONFIG_SND_VOODOO_HP_LEVEL_CONTROL
+ if (is_path(HEADPHONES)
+ && !(wm8994->codec_state & CALL_ACTIVE)) {
+
+ if (reg == WM8994_LEFT_OUTPUT_VOLUME)
+ value =
+ (WM8994_HPOUT1_VU |
+ WM8994_HPOUT1L_MUTE_N |
+ hpvol(0));
+
+ if (reg == WM8994_RIGHT_OUTPUT_VOLUME)
+ value =
+ (WM8994_HPOUT1_VU |
+ WM8994_HPOUT1R_MUTE_N |
+ hpvol(1));
+ }
+#endif
+
+#ifdef CONFIG_SND_VOODOO_FM
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+ // FM tuning virtual hook for Gingerbread
+ if (is_path(RADIO_HEADPHONES)) {
+ if (reg == WM8994_AIF2_DRC_1
+ || reg == WM8994_AIF2_DAC_FILTERS_1)
+ voodoo_hook_fmradio_headset();
+ }
+#else
+ // FM tuning virtual hook for Froyo
+ if (is_path(RADIO_HEADPHONES)) {
+ if (reg == WM8994_INPUT_MIXER_2
+ || reg == WM8994_AIF2_DRC_1
+ || reg == WM8994_ANALOGUE_HP_1)
+ voodoo_hook_fmradio_headset();
+ }
+#endif
+#endif
+ // global Oversampling tuning
+ if (reg == WM8994_OVERSAMPLING)
+ value = osr128_get_value(value);
+
+#ifndef GALAXY_TAB_TEGRA
+ // global Anti-Jitter tuning
+ if (reg == WM8994_FLL1_CONTROL_4)
+ value = fll_tuning_get_value(value);
+#endif
+
+ // global Mono downmix tuning
+ if (reg == WM8994_AIF1_DAC1_FILTERS_1
+ || reg == WM8994_AIF1_DAC2_FILTERS_1
+ || reg == WM8994_AIF2_DAC_FILTERS_1)
+ value = mono_downmix_get_value(value, false);
+
+ // DAC direct tuning virtual hook
+ if (reg == WM8994_OUTPUT_MIXER_1
+ || reg == WM8994_OUTPUT_MIXER_2)
+ value = dac_direct_get_value(value, false);
+
+ // Digital Headroom virtual hook
+ if (reg == WM8994_AIF1_DAC1_LEFT_VOLUME
+ || reg == WM8994_AIF1_DAC1_RIGHT_VOLUME)
+ value = digital_gain_get_value(value);
+
+ // Headphones EQ & 3D virtual hook
+ if (reg == WM8994_AIF1_DAC1_FILTERS_1
+ || reg == WM8994_AIF1_DAC2_FILTERS_1
+ || reg == WM8994_AIF2_DAC_FILTERS_1) {
+ bypass_write_hook = true;
+ apply_saturation_prevention_drc();
+ update_headphone_eq(true);
+ update_stereo_expansion(false);
+ bypass_write_hook = false;
+ }
+
+ }
+ if (debug_log(LOG_VERBOSE))
+ // log every write to dmesg
+ printk("Voodoo sound: wm8994_write 0x%03X 0x%04X "
+#ifdef NEXUS_S
+ "codec_state=%u, stream_state=%u, "
+ "cur_path=%i, rec_path=%i, "
+ "power_state=%i\n",
+ reg, value,
+ wm8994->codec_state, wm8994->stream_state,
+ wm8994->cur_path, wm8994->rec_path,
+ wm8994->power_state);
+#else
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)
+ "codec_state=%u, stream_state=%u, "
+ "cur_path=%i, rec_path=%i, "
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA)
+ "fmradio_path=%i, fmr_mix_path=%i, "
+#endif
+#ifndef GALAXY_TAB
+ "input_source=%i, "
+#endif
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA) && !defined(GALAXY_TAB)
+ "output_source=%i, "
+#endif
+ "power_state=%i\n",
+ reg, value,
+ wm8994->codec_state, wm8994->stream_state,
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA)
+ wm8994->fmradio_path, wm8994->fmr_mix_path,
+#endif
+ wm8994->cur_path, wm8994->rec_path,
+#ifndef GALAXY_TAB
+ wm8994->input_source,
+#endif
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA) && !defined(GALAXY_TAB)
+ wm8994->output_source,
+#endif
+ wm8994->power_state);
+#else
+ "codec_state=%u, stream_state=%u, "
+ "cur_path=%i, rec_path=%i, "
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA)
+ "fmradio_path=%i, fmr_mix_path=%i, "
+#endif
+#ifdef CONFIG_S5PC110_KEPLER_BOARD
+ "call_record_path=%i, call_record_ch=%i, "
+ "AUDIENCE_state=%i, "
+ "Fac_SUB_MIC_state=%i, TTY_state=%i, "
+#endif
+ "power_state=%i, "
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA)
+ "recognition_active=%i, ringtone_active=%i"
+#endif
+ "\n",
+ reg, value,
+ wm8994->codec_state, wm8994->stream_state,
+ wm8994->cur_path, wm8994->rec_path,
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA)
+ wm8994->fmradio_path, wm8994->fmr_mix_path,
+#endif
+#ifdef CONFIG_S5PC110_KEPLER_BOARD
+ wm8994->call_record_path, wm8994->call_record_ch,
+ wm8994->AUDIENCE_state,
+ wm8994->Fac_SUB_MIC_state, wm8994->TTY_state,
+#endif
+ wm8994->power_state
+#if !defined(M110S) && !defined(GALAXY_TAB_TEGRA)
+ ,wm8994->recognition_active,
+ wm8994->ringtone_active
+#endif
+ );
+#endif
+#endif
+ return value;
+}
+
+void voodoo_hook_wm8994_pcm_probe(struct snd_soc_codec *codec_)
+{
+ enable = true;
+ update_enable();
+
+#ifndef MODULE
+ misc_register(&voodoo_sound_control_device);
+ if (sysfs_create_group(&voodoo_sound_control_device.this_device->kobj,
+ &voodoo_sound_control_group) < 0) {
+ printk("%s sysfs_create_group fail\n", __FUNCTION__);
+ pr_err("Failed to create sysfs group for device (%s)!\n",
+ voodoo_sound_control_device.name);
+ }
+#endif
+
+ // make a copy of the codec pointer
+ codec = codec_;
+
+ // initialize eq_band_values[] from default codec EQ values
+ load_current_eq_values();
+}
diff --git a/sound/soc/codecs/wm8994_voodoo.h b/sound/soc/codecs/wm8994_voodoo.h
new file mode 100644
index 0000000..578f8e8
--- /dev/null
+++ b/sound/soc/codecs/wm8994_voodoo.h
@@ -0,0 +1,67 @@
+/*
+ * wm8994.h -- WM8994 Soc Audio driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define VOODOO_SOUND_VERSION 10
+
+#if defined(CONFIG_MACH_HERRING) || defined (CONFIG_SAMSUNG_GALAXYS) \
+ || defined (CONFIG_SAMSUNG_GALAXYSB) \
+ || defined (CONFIG_SAMSUNG_CAPTIVATE) \
+ || defined (CONFIG_SAMSUNG_VIBRANT) \
+ || defined (CONFIG_SAMSUNG_FASCINATE) \
+ || defined (CONFIG_SAMSUNG_EPIC)
+#define NEXUS_S
+#endif
+
+#if defined(CONFIG_FB_S3C_AMS701KA) || defined(CONFIG_KOR_MODEL_M180S)
+#define GALAXY_TAB
+#endif
+
+#ifdef CONFIG_M110S
+#define M110S
+#endif
+
+#ifdef CONFIG_MACH_SAMSUNG_VARIATION_TEGRA
+#define GALAXY_TAB_TEGRA
+#endif
+
+#ifdef CONFIG_TDMB_T3700
+#define M110S
+#endif
+
+enum debug_log { LOG_OFF, LOG_INFOS, LOG_VERBOSE };
+bool debug_log(short unsigned int level);
+
+enum unified_path { HEADPHONES, RADIO_HEADPHONES, SPEAKER, MAIN_MICROPHONE };
+
+bool is_path(int unified_path);
+bool is_path_media_or_fm_no_call_no_record(void);
+unsigned int voodoo_hook_wm8994_write(struct snd_soc_codec *codec,
+ unsigned int reg, unsigned int value);
+void voodoo_hook_fmradio_headset(void);
+void voodoo_hook_wm8994_pcm_probe(struct snd_soc_codec *codec);
+void voodoo_hook_wm8994_pcm_remove(void);
+void voodoo_hook_record_main_mic(void);
+void voodoo_hook_playback_speaker(void);
+
+void load_current_eq_values(void);
+void apply_saturation_prevention_drc(void);
+
+void update_hpvol(bool with_fade);
+void update_fm_radio_headset_restore_freqs(bool with_mute);
+void update_fm_radio_headset_normalize_gain(bool with_mute);
+void update_recording_preset(bool with_mute);
+void update_full_bitwidth(bool with_mute);
+void update_osr128(bool with_mute);
+void update_fll_tuning(bool with_mute);
+void update_mono_downmix(bool with_mute);
+void update_dac_direct(bool with_mute);
+void update_digital_gain(bool with_mute);
+void update_stereo_expansion(bool with_mute);
+void update_headphone_eq(bool update_bands);
+void update_headphone_eq_bands(void);
+void update_enable(void);
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index d155cbb..8601d70 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -20,6 +20,9 @@ config SND_S3C2412_SOC_I2S
select SND_S3C_I2SV2_SOC
select S3C2410_DMA
+config SND_S5PC1XX_I2S
+ tristate
+
config SND_SAMSUNG_PCM
tristate
@@ -34,6 +37,12 @@ config SND_SAMSUNG_SPDIF
config SND_SAMSUNG_I2S
tristate
+config S5P_INTERNAL_DMA
+ tristate
+
+config SND_S5P_WM8994_MASTER
+ bool
+
config SND_SOC_SAMSUNG_NEO1973_WM8753
tristate "Audio support for Openmoko Neo1973 Smartphones (GTA01/GTA02)"
depends on SND_SOC_SAMSUNG && (MACH_NEO1973_GTA01 || MACH_NEO1973_GTA02)
@@ -125,6 +134,17 @@ config SND_SOC_SAMSUNG_H1940_UDA1380
help
This driver provides audio support for HP iPAQ h1940 PDA.
+config SND_SOC_SAMSUNG_HERRING_WM8994
+ tristate "SoC I2S Audio support for HERRING - WM8994"
+ depends on SND_SOC_SAMSUNG && (MACH_HERRING)
+ select SND_S5PC1XX_I2S
+ select SND_SOC_WM8994_SAMSUNG
+ select S5P_INTERNAL_DMA
+ select SND_S5P_WM8994_MASTER
+ help
+ Say Y if you want to add support for SoC audio on herring
+ with the WM8994.
+
config SND_SOC_SAMSUNG_RX1950_UDA1380
tristate "Audio support for the HP iPAQ RX1950"
depends on SND_SOC_SAMSUNG && MACH_RX1950
diff --git a/sound/soc/samsung/Makefile b/sound/soc/samsung/Makefile
index 683843a..98a007e 100644
--- a/sound/soc/samsung/Makefile
+++ b/sound/soc/samsung/Makefile
@@ -1,7 +1,8 @@
# S3c24XX Platform Support
-snd-soc-s3c24xx-objs := dma.o
+snd-soc-s3c24xx-objs := dma.o s3c-dma-wrapper.o
snd-soc-s3c24xx-i2s-objs := s3c24xx-i2s.o
snd-soc-s3c2412-i2s-objs := s3c2412-i2s.o
+snd-soc-s5pc1xx-i2s-objs := s5pc1xx-i2s.o
snd-soc-ac97-objs := ac97.o
snd-soc-s3c-i2s-v2-objs := s3c-i2s-v2.o
snd-soc-samsung-spdif-objs := spdif.o
@@ -13,9 +14,11 @@ obj-$(CONFIG_SND_S3C24XX_I2S) += snd-soc-s3c24xx-i2s.o
obj-$(CONFIG_SND_SAMSUNG_AC97) += snd-soc-ac97.o
obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd-soc-s3c2412-i2s.o
obj-$(CONFIG_SND_S3C_I2SV2_SOC) += snd-soc-s3c-i2s-v2.o
+obj-$(CONFIG_SND_S5PC1XX_I2S) += snd-soc-s5pc1xx-i2s.o
obj-$(CONFIG_SND_SAMSUNG_SPDIF) += snd-soc-samsung-spdif.o
obj-$(CONFIG_SND_SAMSUNG_PCM) += snd-soc-pcm.o
obj-$(CONFIG_SND_SAMSUNG_I2S) += snd-soc-i2s.o
+obj-$(CONFIG_S5P_INTERNAL_DMA) += s3c-idma.o s5p-i2s_sec.o
# S3C24XX Machine Support
snd-soc-jive-wm8750-objs := jive_wm8750.o
@@ -33,6 +36,7 @@ snd-soc-smdk-wm8994-objs := smdk_wm8994.o
snd-soc-smdk-wm9713-objs := smdk_wm9713.o
snd-soc-s3c64xx-smartq-wm8987-objs := smartq_wm8987.o
snd-soc-goni-wm8994-objs := goni_wm8994.o
+snd-soc-herring-wm8994-objs := herring-wm8994.o
snd-soc-smdk-spdif-objs := smdk_spdif.o
snd-soc-smdk-wm8580pcm-objs := smdk_wm8580pcm.o
snd-soc-speyside-objs := speyside.o
@@ -46,6 +50,7 @@ obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC) += snd-soc-s3c24xx-simtec.o
obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC_HERMES) += snd-soc-s3c24xx-simtec-hermes.o
obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC_TLV320AIC23) += snd-soc-s3c24xx-simtec-tlv320aic23.o
obj-$(CONFIG_SND_SOC_SAMSUNG_H1940_UDA1380) += snd-soc-h1940-uda1380.o
+obj-$(CONFIG_SND_SOC_SAMSUNG_HERRING_WM8994) += snd-soc-herring-wm8994.o
obj-$(CONFIG_SND_SOC_SAMSUNG_RX1950_UDA1380) += snd-soc-rx1950-uda1380.o
obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM8580) += snd-soc-smdk-wm8580.o
obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994) += snd-soc-smdk-wm8994.o
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index 5cb3b88..fc56ed0 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -42,9 +42,9 @@ static const struct snd_pcm_hardware dma_hardware = {
SNDRV_PCM_FMTBIT_S8,
.channels_min = 2,
.channels_max = 2,
- .buffer_bytes_max = 128*1024,
- .period_bytes_min = PAGE_SIZE,
- .period_bytes_max = PAGE_SIZE*2,
+ .buffer_bytes_max = 128 * 1024,
+ .period_bytes_min = 128,
+ .period_bytes_max = 32 * 1024,
.periods_min = 2,
.periods_max = 128,
.fifo_size = 32,
@@ -191,6 +191,11 @@ static int dma_hw_params(struct snd_pcm_substream *substream,
prtd->dma_start = runtime->dma_addr;
prtd->dma_pos = prtd->dma_start;
prtd->dma_end = prtd->dma_start + totbytes;
+
+ pr_debug("DmaAddr=@%x Total=%lubytes PrdSz=%u #Prds=%u dma_area=0x%x\n",
+ prtd->dma_start, totbytes, params_period_bytes(params),
+ params_periods(params), (unsigned int)runtime->dma_area);
+
spin_unlock_irq(&prtd->lock);
return 0;
@@ -408,7 +413,11 @@ static void dma_free_dma_buffers(struct snd_pcm *pcm)
pr_debug("Entered %s\n", __func__);
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ for (stream = 1; stream < 2; stream++) {
+#else
for (stream = 0; stream < 2; stream++) {
+#endif
substream = pcm->streams[stream].substream;
if (!substream)
continue;
@@ -437,13 +446,14 @@ static int dma_new(struct snd_card *card,
if (!card->dev->coherent_dma_mask)
card->dev->coherent_dma_mask = 0xffffffff;
+#ifndef CONFIG_S5P_INTERNAL_DMA
if (dai->driver->playback.channels_min) {
ret = preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_PLAYBACK);
if (ret)
goto out;
}
-
+#endif
if (dai->driver->capture.channels_min) {
ret = preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_CAPTURE);
@@ -454,11 +464,14 @@ out:
return ret;
}
-static struct snd_soc_platform_driver samsung_asoc_platform = {
+struct snd_soc_platform_driver samsung_asoc_platform = {
.ops = &dma_ops,
.pcm_new = dma_new,
.pcm_free = dma_free_dma_buffers,
};
+EXPORT_SYMBOL_GPL(samsung_asoc_platform);
+
+#ifndef CONFIG_S5P_INTERNAL_DMA
static int __devinit samsung_asoc_platform_probe(struct platform_device *pdev)
{
@@ -493,6 +506,8 @@ static void __exit samsung_asoc_exit(void)
}
module_exit(samsung_asoc_exit);
+#endif
+
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_DESCRIPTION("Samsung ASoC DMA Driver");
MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/dma.h b/sound/soc/samsung/dma.h
index c506592..2bb0d44 100644
--- a/sound/soc/samsung/dma.h
+++ b/sound/soc/samsung/dma.h
@@ -19,4 +19,6 @@ struct s3c_dma_params {
int dma_size; /* Size of the DMA transfer */
};
+extern struct snd_soc_platform_driver samsung_asoc_platform;
+
#endif
diff --git a/sound/soc/samsung/herring-wm8994.c b/sound/soc/samsung/herring-wm8994.c
new file mode 100644
index 0000000..5f9dfe2
--- /dev/null
+++ b/sound/soc/samsung/herring-wm8994.c
@@ -0,0 +1,358 @@
+/*
+ * crespo_wm8994.c
+ *
+ * Copyright (C) 2010, Samsung Elect. Ltd. -
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <mach/regs-clock.h>
+#include <plat/regs-iis.h>
+#include "../codecs/wm8994.h"
+#include "s3c-dma.h"
+#include "s5pc1xx-i2s.h"
+//#include "s3c-i2s-v2.h"
+
+#include <linux/io.h>
+
+#define I2S_NUM 0
+#define SRC_CLK 66738000
+
+/* #define CONFIG_SND_DEBUG */
+#ifdef CONFIG_SND_DEBUG
+#define debug_msg(x...) printk(x)
+#else
+#define debug_msg(x...)
+#endif
+
+/* BLC(bits-per-channel) --> BFS(bit clock shud be >= FS*(Bit-per-channel)*2)*/
+/* BFS --> RFS(must be a multiple of BFS) */
+/* RFS & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) */
+int smdkc110_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ int bfs, rfs, ret;
+ u32 ap_codec_clk;
+#ifndef CONFIG_SND_S5P_WM8994_MASTER
+ struct clk *clk_out, *clk_epll;
+ int psr;
+#endif
+ debug_msg("%s\n", __func__);
+
+ /* Choose BFS and RFS values combination that is supported by
+ * both the WM8994 codec as well as the S5P AP
+ *
+ */
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S8:
+ /* Can take any RFS value for AP */
+ bfs = 16;
+ rfs = 256;
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ /* Can take any RFS value for AP */
+ bfs = 32;
+ rfs = 256;
+ break;
+ case SNDRV_PCM_FORMAT_S20_3LE:
+ case SNDRV_PCM_FORMAT_S24_LE:
+ bfs = 48;
+ rfs = 512;
+ break;
+ /* Impossible, as the AP doesn't support 64fs or more BFS */
+ case SNDRV_PCM_FORMAT_S32_LE:
+ default:
+ return -EINVAL;
+ }
+
+#ifdef CONFIG_SND_S5P_WM8994_MASTER
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+
+ if (ret < 0) {
+ printk(KERN_ERR "smdkc110_wm8994_hw_params :\
+ Codec DAI configuration error!\n");
+ return ret;
+ }
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params :\
+ AP DAI configuration error!\n");
+ return ret;
+ }
+
+ /* Select the AP Sysclk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C64XX_CDCLKSRC_EXT,
+ params_rate(params), SND_SOC_CLOCK_IN);
+
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params :\
+ AP sys clock INT setting error!\n");
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C64XX_CLKSRC_I2SEXT,
+ params_rate(params), SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params :\
+ AP sys clock I2SEXT setting error!\n");
+ return ret;
+ }
+
+ switch (params_rate(params)) {
+
+ case 8000:
+ ap_codec_clk = 4096000;
+ break;
+ case 11025:
+ ap_codec_clk = 2822400;
+ break;
+ case 12000:
+ ap_codec_clk = 6144000;
+ break;
+ case 16000:
+ ap_codec_clk = 4096000;
+ break;
+ case 22050:
+ ap_codec_clk = 6144000;
+ break;
+ case 24000:
+ ap_codec_clk = 6144000;
+ break;
+ case 32000:
+ ap_codec_clk = 8192000;
+ break;
+ case 44100:
+ ap_codec_clk = 11289600;
+ break;
+ case 48000:
+ ap_codec_clk = 12288000;
+ break;
+ default:
+ ap_codec_clk = 11289600;
+ break;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL,
+ ap_codec_clk, 0);
+ if (ret < 0)
+ return ret;
+#else
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+
+ if (ret < 0)
+ return ret;
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+
+ if (ret < 0)
+
+ return ret;
+ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C64XX_CLKSRC_CDCLK,
+ params_rate(params), SND_SOC_CLOCK_OUT);
+ if (ret < 0)
+ return ret;
+#ifdef USE_CLKAUDIO
+ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CLKSRC_CLKAUDIO,
+ params_rate(params), SND_SOC_CLOCK_OUT);
+
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params : \
+ AP sys clock setting error!\n");
+ return ret;
+ }
+#endif
+ clk_out = clk_get(NULL, "clk_out");
+ if (IS_ERR(clk_out)) {
+ printk(KERN_ERR
+ "failed to get CLK_OUT\n");
+ return -EBUSY;
+ }
+
+ clk_epll = clk_get(NULL, "fout_epll");
+ if (IS_ERR(clk_epll)) {
+ printk(KERN_ERR
+ "failed to get fout_epll\n");
+ clk_put(clk_out);
+ return -EBUSY;
+ }
+
+ if (clk_set_parent(clk_out, clk_epll)) {
+ printk(KERN_ERR
+ "failed to set CLK_EPLL as parent of CLK_OUT\n");
+ clk_put(clk_out);
+ clk_put(clk_epll);
+ return -EBUSY;
+ }
+
+
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 32000:
+ case 48000:
+ case 64000:
+ case 96000:
+ clk_set_rate(clk_out, 12288000);
+ ap_codec_clk = SRC_CLK/4;
+ break;
+ case 11025:
+ case 22050:
+ case 44100:
+ case 88200:
+ default:
+ clk_set_rate(clk_out, 11289600);
+ ap_codec_clk = SRC_CLK/6;
+ break;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_MCLK,
+ ap_codec_clk, 0);
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params : \
+ Codec sys clock setting error!\n");
+ return ret;
+ }
+
+ /* Calculate Prescalare/PLL values for supported Rates */
+ psr = SRC_CLK / rfs / params_rate(params);
+ ret = SRC_CLK / rfs - psr * params_rate(params);
+ /* round off */
+ if (ret >= params_rate(params)/2)
+ psr += 1;
+
+ psr -= 1;
+ printk(KERN_INFO
+ "SRC_CLK=%d PSR=%d RFS=%d BFS=%d\n", SRC_CLK, psr, rfs, bfs);
+
+ /* Set the AP Prescalar/Pll */
+ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_PRESCALER, psr);
+
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params :\
+ AP prescalar setting error!\n");
+ return ret;
+ }
+
+ /* Set the AP RFS */
+ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_RCLK, rfs);
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params : AP RFS setting error!\n");
+ return ret;
+ }
+
+ /* Set the AP BFS */
+ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_I2SV2_DIV_BCLK, bfs);
+
+ if (ret < 0) {
+ printk(KERN_ERR
+ "smdkc110_wm8994_hw_params : AP BCLK setting error!\n");
+ return ret;
+ }
+
+ clk_put(clk_epll);
+ clk_put(clk_out);
+#endif
+ return 0;
+
+}
+
+/* machine stream operations */
+static struct snd_soc_ops smdkc110_ops = {
+ .hw_params = smdkc110_hw_params,
+};
+
+/* digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link smdkc1xx_dai = {
+ .name = "herring",
+ .stream_name = "WM8994 HiFi Playback",
+ .cpu_dai_name = "samsung-i2s.0",
+ .codec_dai_name = "WM8994 PAIFRX",
+ .platform_name = "samsung-audio",
+ .codec_name = "wm8994-samsung-codec.4-001a",
+ .ops = &smdkc110_ops,
+};
+
+static struct snd_soc_card smdkc100 = {
+ .name = "smdkc110",
+ .dai_link = &smdkc1xx_dai,
+ .num_links = 1,
+};
+
+#if 0
+static struct wm8994_setup_data smdkc110_wm8994_setup = {
+ /*
+ The I2C address of the WM89940 is 0x34. To the I2C driver
+ the address is a 7-bit number hence the right shift .
+ */
+ .i2c_address = 0x34,
+ .i2c_bus = 4,
+};
+
+/* audio subsystem */
+static struct snd_soc_device smdkc1xx_snd_devdata = {
+ .card = &smdkc100,
+ .codec_dev = &soc_codec_dev_wm8994,
+ .codec_data = &smdkc110_wm8994_setup,
+};
+#endif
+
+static struct platform_device *smdkc1xx_snd_device;
+static int __init smdkc110_audio_init(void)
+{
+ int ret;
+
+ debug_msg("%s\n", __func__);
+
+ smdkc1xx_snd_device = platform_device_alloc("soc-audio", 0);
+ if (!smdkc1xx_snd_device)
+ return -ENOMEM;
+
+ platform_set_drvdata(smdkc1xx_snd_device, &smdkc100);
+ ret = platform_device_add(smdkc1xx_snd_device);
+
+ if (ret)
+ platform_device_put(smdkc1xx_snd_device);
+
+ return ret;
+}
+
+static void __exit smdkc110_audio_exit(void)
+{
+ debug_msg("%s\n", __func__);
+
+ platform_device_unregister(smdkc1xx_snd_device);
+}
+
+module_init(smdkc110_audio_init);
+module_exit(smdkc110_audio_exit);
+
+/* Module information */
+MODULE_DESCRIPTION("ALSA SoC SMDKC110 WM8994");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 992a732..a779185 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -14,6 +14,7 @@
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/regulator/consumer.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
@@ -146,6 +147,8 @@ struct i2s_dai {
unsigned rfs, bfs;
/* I2S Controller's core clock */
struct clk *clk;
+ /* I2S Controller's power domain */
+ struct regulator *regulator;
/* Clock for generating I2S signals */
struct clk *op_clk;
/* Array of clock names for op_clk */
@@ -572,9 +575,13 @@ static int i2s_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct i2s_dai *i2s = to_info(dai);
- u32 mod = readl(i2s->addr + I2SMOD);
+ u32 mod;
u32 tmp = 0;
+ dev_info(&i2s->pdev->dev, "base %p\n", i2s->addr);
+
+ mod = readl(i2s->addr + I2SMOD);
+
/* Format is priority */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
@@ -951,6 +958,9 @@ static int i2s_resume(struct snd_soc_dai *dai)
static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
{
+ struct clk *fout_epll, *mout_epll;
+ struct clk *mout_audss = NULL;
+ struct clk *sclk_audio, *iis_clk, *iis_busclk, *iis_ipclk; /* these belong shomewhere else */
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = i2s->pri_dai ? : i2s->sec_dai;
@@ -971,6 +981,59 @@ static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
}
clk_enable(i2s->clk);
+ /* Get i2s power domain regulator */
+ i2s->regulator = regulator_get(&i2s->pdev->dev, "pd");
+ if (IS_ERR(i2s->regulator)) {
+ dev_err(&i2s->pdev->dev, "%s: failed to get resource %s\n",
+ __func__, "i2s");
+ return PTR_ERR(i2s->regulator);
+ }
+
+ /* Enable Power domain */
+ regulator_enable(i2s->regulator);
+
+ fout_epll = clk_get(&i2s->pdev->dev, "fout_epll");
+ if (IS_ERR(fout_epll))
+ dev_err(&i2s->pdev->dev, "failed to get fout_epll\n");
+
+ mout_epll = clk_get(&i2s->pdev->dev, "mout_epll");
+ if (IS_ERR(mout_epll))
+ dev_err(&i2s->pdev->dev, "failed to get mout_epll\n");
+ clk_set_parent(mout_epll, fout_epll);
+
+ sclk_audio = clk_get(&i2s->pdev->dev, "sclk_audio");
+ if (IS_ERR(sclk_audio))
+ dev_err(&i2s->pdev->dev, "failed to get sclk_audio\n");
+ clk_set_parent(sclk_audio, mout_epll);
+
+ /* Need not to enable in general */
+ clk_enable(sclk_audio);
+
+ /* When I2S V5.1 used, initialize audio subsystem clock */
+ /* CLKMUX_ASS */
+ if (&i2s->pdev->id == 0) {
+ mout_audss = clk_get(NULL, "mout_audss");
+ if (IS_ERR(mout_audss))
+ dev_err(&i2s->pdev->dev, "failed to get mout_audss\n");
+ clk_set_parent(mout_audss, fout_epll);
+ /*MUX-I2SA*/
+ iis_clk = clk_get(&i2s->pdev->dev, "audio-bus");
+ if (IS_ERR(iis_clk))
+ dev_err(&i2s->pdev->dev, "failed to get audio-bus\n");
+ clk_set_parent(iis_clk, mout_audss);
+ /*getting AUDIO BUS CLK*/
+ iis_busclk = clk_get(NULL, "dout_audio_bus_clk_i2s");
+ if (IS_ERR(iis_busclk))
+ printk(KERN_ERR "failed to get audss_hclk\n");
+ iis_ipclk = clk_get(&i2s->pdev->dev, "i2s_v50");
+ if (IS_ERR(iis_ipclk))
+ dev_err(&i2s->pdev->dev, "failed to get i2s_v50_clock\n");
+ clk_enable(iis_ipclk);
+ clk_enable(iis_clk);
+ clk_enable(iis_busclk);
+ }
+
+
if (other) {
other->addr = i2s->addr;
other->clk = i2s->clk;
diff --git a/sound/soc/samsung/s3c-dma-wrapper.c b/sound/soc/samsung/s3c-dma-wrapper.c
new file mode 100644
index 0000000..2f87b68
--- /dev/null
+++ b/sound/soc/samsung/s3c-dma-wrapper.c
@@ -0,0 +1,267 @@
+/*
+ * s3c-dma-wrapper.c -- S3C DMA Platform Wrapper Driver
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ * Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <sound/soc.h>
+#include "dma.h"
+#include "s3c-idma.h"
+
+static int s3c_wrpdma_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->hw_params)
+ return platform->ops->hw_params(substream, params);
+ else
+ return 0;
+}
+
+static int s3c_wrpdma_hw_free(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->hw_free)
+ return platform->ops->hw_free(substream);
+ else
+ return 0;
+}
+
+static int s3c_wrpdma_prepare(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->prepare)
+ return platform->ops->prepare(substream);
+ else
+ return 0;
+}
+
+static int s3c_wrpdma_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->trigger)
+ return platform->ops->trigger(substream, cmd);
+ else
+ return 0;
+}
+
+static snd_pcm_uframes_t s3c_wrpdma_pointer(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->pointer)
+ return platform->ops->pointer(substream);
+ else
+ return 0;
+}
+
+static int s3c_wrpdma_open(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->open)
+ return platform->ops->open(substream);
+ else
+ return 0;
+}
+
+static int s3c_wrpdma_close(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->close)
+ return platform->ops->close(substream);
+ else
+ return 0;
+}
+
+static int s3c_wrpdma_ioctl(struct snd_pcm_substream *substream,
+ unsigned int cmd, void *arg)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->ioctl)
+ return platform->ops->ioctl(substream, cmd, arg);
+ else
+ return 0;
+}
+
+static int s3c_wrpdma_mmap(struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ struct snd_soc_platform_driver *platform;
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ platform = &idma_soc_platform;
+ else
+#endif
+ platform = &samsung_asoc_platform;
+
+ if (platform->ops->mmap)
+ return platform->ops->mmap(substream, vma);
+ else
+ return 0;
+}
+
+static struct snd_pcm_ops s3c_wrpdma_ops = {
+ .open = s3c_wrpdma_open,
+ .close = s3c_wrpdma_close,
+ .ioctl = s3c_wrpdma_ioctl,
+ .hw_params = s3c_wrpdma_hw_params,
+ .hw_free = s3c_wrpdma_hw_free,
+ .prepare = s3c_wrpdma_prepare,
+ .trigger = s3c_wrpdma_trigger,
+ .pointer = s3c_wrpdma_pointer,
+ .mmap = s3c_wrpdma_mmap,
+};
+
+static void s3c_wrpdma_pcm_free(struct snd_pcm *pcm)
+{
+ struct snd_soc_platform_driver *gdma_platform;
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ struct snd_soc_platform_driver *idma_platform;
+#endif
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ idma_platform = &idma_soc_platform;
+ if (idma_platform->pcm_free)
+ idma_platform->pcm_free(pcm);
+#endif
+ gdma_platform = &samsung_asoc_platform;
+ if (gdma_platform->pcm_free)
+ gdma_platform->pcm_free(pcm);
+}
+
+static int s3c_wrpdma_pcm_new(struct snd_card *card,
+ struct snd_soc_dai *dai, struct snd_pcm *pcm)
+{
+ struct snd_soc_platform_driver *gdma_platform;
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ struct snd_soc_platform_driver *idma_platform;
+#endif
+
+ /* sec_fifo i/f always use internal h/w buffers
+ * irrespective of the xfer method (iDMA or SysDMA) */
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ idma_platform = &idma_soc_platform;
+ if (idma_platform->pcm_new)
+ idma_platform->pcm_new(card, dai, pcm);
+#endif
+ gdma_platform = &samsung_asoc_platform;
+ if (gdma_platform->pcm_new)
+ gdma_platform->pcm_new(card, dai, pcm);
+
+ return 0;
+}
+
+static struct snd_soc_platform_driver s3c_dma_wrapper = {
+ .ops = &s3c_wrpdma_ops,
+ .pcm_new = s3c_wrpdma_pcm_new,
+ .pcm_free = s3c_wrpdma_pcm_free,
+};
+//EXPORT_SYMBOL_GPL(s3c_dma_wrapper);
+
+static int __devinit s3c_dma_wrapper_platform_probe(struct platform_device *pdev)
+{
+ return snd_soc_register_platform(&pdev->dev, &s3c_dma_wrapper);
+}
+
+static int __devexit s3c_dma_wrapper_platform_remove(struct platform_device *pdev)
+{
+ snd_soc_unregister_platform(&pdev->dev);
+ return 0;
+}
+
+static struct platform_driver s3c_dma_wrapper_driver = {
+ .driver = {
+ .name = "samsung-audio",
+ .owner = THIS_MODULE,
+ },
+
+ .probe = s3c_dma_wrapper_platform_probe,
+ .remove = __devexit_p(s3c_dma_wrapper_platform_remove),
+};
+
+static int __init s3c_dma_wrapper_init(void)
+{
+ return platform_driver_register(&s3c_dma_wrapper_driver);
+}
+module_init(s3c_dma_wrapper_init);
+
+static void __exit s3c_dma_wrapper_exit(void)
+{
+ platform_driver_unregister(&s3c_dma_wrapper_driver);
+}
+module_exit(s3c_dma_wrapper_exit);
+
+MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
+MODULE_DESCRIPTION("Audio DMA wrapper module");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/s3c-dma.c b/sound/soc/samsung/s3c-dma.c
new file mode 100644
index 0000000..8985964
--- /dev/null
+++ b/sound/soc/samsung/s3c-dma.c
@@ -0,0 +1,478 @@
+/*
+ * s3c-dma.c -- ALSA Soc Audio Layer
+ *
+ * (c) 2006 Wolfson Microelectronics PLC.
+ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ * Copyright 2004-2005 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <asm/dma.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
+
+#include "s3c-dma.h"
+
+static const struct snd_pcm_hardware s3c_dma_hardware = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_U16_LE |
+ SNDRV_PCM_FMTBIT_U8 |
+ SNDRV_PCM_FMTBIT_S8,
+ .channels_min = 2,
+ .channels_max = 2,
+ .buffer_bytes_max = 128 * 1024,
+ .period_bytes_min = 128,
+ .period_bytes_max = 32 * 1024,
+ .periods_min = 2,
+ .periods_max = 128,
+ .fifo_size = 32,
+};
+
+struct s3c24xx_runtime_data {
+ spinlock_t lock;
+ int state;
+ unsigned int dma_loaded;
+ unsigned int dma_limit;
+ unsigned int dma_period;
+ dma_addr_t dma_start;
+ dma_addr_t dma_pos;
+ dma_addr_t dma_end;
+ struct s3c_dma_params *params;
+};
+
+/* s3c_dma_enqueue
+ *
+ * place a dma buffer onto the queue for the dma system
+ * to handle.
+*/
+static void s3c_dma_enqueue(struct snd_pcm_substream *substream)
+{
+ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
+ dma_addr_t pos = prtd->dma_pos;
+ unsigned int limit;
+ int ret;
+
+ pr_debug("Entered %s\n", __func__);
+
+ if (s3c_dma_has_circular())
+ limit = (prtd->dma_end - prtd->dma_start) / prtd->dma_period;
+ else
+ limit = prtd->dma_limit;
+
+ pr_debug("%s: loaded %d, limit %d\n",
+ __func__, prtd->dma_loaded, limit);
+
+ while (prtd->dma_loaded < limit) {
+ unsigned long len = prtd->dma_period;
+
+ pr_debug("dma_loaded: %d\n", prtd->dma_loaded);
+
+ if ((pos + len) > prtd->dma_end) {
+ len = prtd->dma_end - pos;
+ pr_debug(KERN_DEBUG "%s: corrected dma len %ld\n",
+ __func__, len);
+ }
+
+ ret = s3c2410_dma_enqueue(prtd->params->channel,
+ substream, pos, len);
+
+ if (ret == 0) {
+ prtd->dma_loaded++;
+ pos += prtd->dma_period;
+ if (pos >= prtd->dma_end)
+ pos = prtd->dma_start;
+ } else
+ break;
+ }
+
+ prtd->dma_pos = pos;
+}
+
+static void s3c24xx_audio_buffdone(struct s3c2410_dma_chan *channel,
+ void *dev_id, int size,
+ enum s3c2410_dma_buffresult result)
+{
+ struct snd_pcm_substream *substream = dev_id;
+ struct s3c24xx_runtime_data *prtd;
+
+ pr_debug("Entered %s\n", __func__);
+
+ if (result == S3C2410_RES_ABORT || result == S3C2410_RES_ERR)
+ return;
+
+ prtd = substream->runtime->private_data;
+
+ if (substream)
+ snd_pcm_period_elapsed(substream);
+
+ spin_lock(&prtd->lock);
+ if (prtd->state & ST_RUNNING && !s3c_dma_has_circular()) {
+ prtd->dma_loaded--;
+ s3c_dma_enqueue(substream);
+ }
+
+ spin_unlock(&prtd->lock);
+}
+
+static int s3c_dma_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct s3c24xx_runtime_data *prtd = runtime->private_data;
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ unsigned long totbytes = params_buffer_bytes(params);
+ struct s3c_dma_params *dma =
+ snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
+ int ret = 0;
+
+
+ pr_debug("Entered %s\n", __func__);
+
+ /* return if this is a bufferless transfer e.g.
+ * codec <--> BT codec or GSM modem -- lg FIXME */
+ if (!dma)
+ return 0;
+
+ /* this may get called several times by oss emulation
+ * with different params -HW */
+ if (prtd->params == NULL) {
+ /* prepare DMA */
+ prtd->params = dma;
+
+ pr_debug("params %p, client %p, channel %d\n", prtd->params,
+ prtd->params->client, prtd->params->channel);
+
+ ret = s3c2410_dma_request(prtd->params->channel,
+ prtd->params->client, NULL);
+
+ if (ret < 0) {
+ printk(KERN_ERR "failed to get dma channel\n");
+ return ret;
+ }
+
+ /* use the circular buffering if we have it available. */
+ if (s3c_dma_has_circular())
+ s3c2410_dma_setflags(prtd->params->channel,
+ S3C2410_DMAF_CIRCULAR);
+ }
+
+ s3c2410_dma_set_buffdone_fn(prtd->params->channel,
+ s3c24xx_audio_buffdone);
+
+ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+
+ runtime->dma_bytes = totbytes;
+
+ spin_lock_irq(&prtd->lock);
+ prtd->dma_loaded = 0;
+ prtd->dma_limit = runtime->hw.periods_min;
+ prtd->dma_period = params_period_bytes(params);
+ prtd->dma_start = runtime->dma_addr;
+ prtd->dma_pos = prtd->dma_start;
+ prtd->dma_end = prtd->dma_start + totbytes;
+
+ pr_debug("DmaAddr=@%x Total=%lubytes PrdSz=%u #Prds=%u dma_area=0x%x\n",
+ prtd->dma_start, totbytes, params_period_bytes(params),
+ params_periods(params), (unsigned int)runtime->dma_area);
+
+ spin_unlock_irq(&prtd->lock);
+
+ return 0;
+}
+
+static int s3c_dma_hw_free(struct snd_pcm_substream *substream)
+{
+ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
+
+ pr_debug("Entered %s\n", __func__);
+
+ /* TODO - do we need to ensure DMA flushed */
+ snd_pcm_set_runtime_buffer(substream, NULL);
+
+ if (prtd->params) {
+ s3c2410_dma_free(prtd->params->channel, prtd->params->client);
+ prtd->params = NULL;
+ }
+
+ return 0;
+}
+
+static int s3c_dma_prepare(struct snd_pcm_substream *substream)
+{
+ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
+ int ret = 0;
+
+ pr_debug("Entered %s\n", __func__);
+
+ /* return if this is a bufferless transfer e.g.
+ * codec <--> BT codec or GSM modem -- lg FIXME */
+ if (!prtd->params)
+ return 0;
+
+ /* channel needs configuring for mem=>device, increment memory addr,
+ * sync to pclk, half-word transfers to the IIS-FIFO. */
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ s3c2410_dma_devconfig(prtd->params->channel,
+ S3C2410_DMASRC_MEM,
+ prtd->params->dma_addr);
+ } else {
+ s3c2410_dma_devconfig(prtd->params->channel,
+ S3C2410_DMASRC_HW,
+ prtd->params->dma_addr);
+ }
+
+ s3c2410_dma_config(prtd->params->channel,
+ prtd->params->dma_size);
+
+ /* flush the DMA channel */
+ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH);
+ prtd->dma_loaded = 0;
+ prtd->dma_pos = prtd->dma_start;
+
+ /* enqueue dma buffers */
+ s3c_dma_enqueue(substream);
+
+ return ret;
+}
+
+static int s3c_dma_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
+ int ret = 0;
+
+ pr_debug("Entered %s\n", __func__);
+
+ spin_lock(&prtd->lock);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ prtd->state |= ST_RUNNING;
+ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_START);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ prtd->state &= ~ST_RUNNING;
+ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_STOP);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ spin_unlock(&prtd->lock);
+
+ return ret;
+}
+
+static snd_pcm_uframes_t
+s3c_dma_pointer(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct s3c24xx_runtime_data *prtd = runtime->private_data;
+ unsigned long res;
+ dma_addr_t src, dst;
+
+ pr_debug("Entered %s\n", __func__);
+
+ spin_lock(&prtd->lock);
+ s3c2410_dma_getposition(prtd->params->channel, &src, &dst);
+
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ res = dst - prtd->dma_start;
+ else
+ res = src - prtd->dma_start;
+
+ spin_unlock(&prtd->lock);
+
+ pr_debug("Pointer %x %x\n", src, dst);
+
+ /* we seem to be getting the odd error from the pcm library due
+ * to out-of-bounds pointers. this is maybe due to the dma engine
+ * not having loaded the new values for the channel before being
+ * callled... (todo - fix )
+ */
+
+ if (res >= snd_pcm_lib_buffer_bytes(substream)) {
+ if (res == snd_pcm_lib_buffer_bytes(substream))
+ res = 0;
+ }
+
+ return bytes_to_frames(substream->runtime, res);
+}
+
+static int s3c_dma_open(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct s3c24xx_runtime_data *prtd;
+
+ pr_debug("Entered %s\n", __func__);
+
+ snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+ snd_soc_set_runtime_hwparams(substream, &s3c_dma_hardware);
+
+ prtd = kzalloc(sizeof(struct s3c24xx_runtime_data), GFP_KERNEL);
+ if (prtd == NULL)
+ return -ENOMEM;
+
+ spin_lock_init(&prtd->lock);
+
+ runtime->private_data = prtd;
+ return 0;
+}
+
+static int s3c_dma_close(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct s3c24xx_runtime_data *prtd = runtime->private_data;
+
+ pr_debug("Entered %s\n", __func__);
+
+ if (!prtd)
+ pr_debug("s3c_dma_close called with prtd == NULL\n");
+
+ kfree(prtd);
+
+ return 0;
+}
+
+static int s3c_dma_mmap(struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+
+ pr_debug("Entered %s\n", __func__);
+
+ return dma_mmap_writecombine(substream->pcm->card->dev, vma,
+ runtime->dma_area,
+ runtime->dma_addr,
+ runtime->dma_bytes);
+}
+
+static struct snd_pcm_ops s3c_dma_ops = {
+ .open = s3c_dma_open,
+ .close = s3c_dma_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = s3c_dma_hw_params,
+ .hw_free = s3c_dma_hw_free,
+ .prepare = s3c_dma_prepare,
+ .trigger = s3c_dma_trigger,
+ .pointer = s3c_dma_pointer,
+ .mmap = s3c_dma_mmap,
+};
+
+static int s3c_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+ struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+ struct snd_dma_buffer *buf = &substream->dma_buffer;
+ size_t size = s3c_dma_hardware.buffer_bytes_max;
+
+ pr_debug("Entered %s\n", __func__);
+ buf->dev.type = SNDRV_DMA_TYPE_DEV;
+ buf->dev.dev = pcm->card->dev;
+ buf->private_data = NULL;
+ buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+ &buf->addr, GFP_KERNEL);
+ if (!buf->area)
+ return -ENOMEM;
+ buf->bytes = size;
+ return 0;
+}
+
+static void s3c_dma_free_dma_buffers(struct snd_pcm *pcm)
+{
+ struct snd_pcm_substream *substream;
+ struct snd_dma_buffer *buf;
+ int stream;
+
+ pr_debug("Entered %s\n", __func__);
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ for (stream = 1; stream < 2; stream++) {
+#else
+ for (stream = 0; stream < 2; stream++) {
+#endif
+ substream = pcm->streams[stream].substream;
+ if (!substream)
+ continue;
+
+ buf = &substream->dma_buffer;
+ if (!buf->area)
+ continue;
+
+ dma_free_writecombine(pcm->card->dev, buf->bytes,
+ buf->area, buf->addr);
+ buf->area = NULL;
+ }
+}
+
+static u64 s3c_dma_mask = DMA_BIT_MASK(32);
+
+static int s3c_dma_new(struct snd_card *card,
+ struct snd_soc_dai *dai, struct snd_pcm *pcm)
+{
+ int ret = 0;
+
+ pr_debug("Entered %s\n", __func__);
+
+ if (!card->dev->dma_mask)
+ card->dev->dma_mask = &s3c_dma_mask;
+ if (!card->dev->coherent_dma_mask)
+ card->dev->coherent_dma_mask = 0xffffffff;
+#ifndef CONFIG_S5P_INTERNAL_DMA
+ if (dai->driver->playback.channels_min) {
+ ret = s3c_preallocate_dma_buffer(pcm,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ if (ret)
+ goto out;
+ }
+#endif
+ if (dai->driver->capture.channels_min) {
+ ret = s3c_preallocate_dma_buffer(pcm,
+ SNDRV_PCM_STREAM_CAPTURE);
+ if (ret)
+ goto out;
+ }
+ out:
+ return ret;
+}
+
+struct snd_soc_platform_driver s3c24xx_soc_platform = {
+ .ops = &s3c_dma_ops,
+ .pcm_new = s3c_dma_new,
+ .pcm_free = s3c_dma_free_dma_buffers,
+};
+EXPORT_SYMBOL_GPL(s3c24xx_soc_platform);
+
+MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
+MODULE_DESCRIPTION("Samsung S3C Audio DMA module");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/s3c-dma.h b/sound/soc/samsung/s3c-dma.h
new file mode 100644
index 0000000..cb869db
--- /dev/null
+++ b/sound/soc/samsung/s3c-dma.h
@@ -0,0 +1,33 @@
+/*
+ * s3c-dma.h --
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * ALSA PCM interface for the Samsung S3C24xx CPU
+ */
+
+#ifndef _S3C_AUDIO_H
+#define _S3C_AUDIO_H
+
+#define ST_RUNNING (1<<0)
+#define ST_OPENED (1<<1)
+
+struct s3c_dma_params {
+ struct s3c2410_dma_client *client; /* stream identifier */
+ int channel; /* Channel ID */
+ dma_addr_t dma_addr;
+ int dma_size; /* Size of the DMA transfer */
+};
+
+#define S3C24XX_DAI_I2S 0
+
+//#define pr_debug(fmt...) printk(fmt)
+/* platform data */
+extern struct snd_soc_platform_driver s3c24xx_soc_platform;
+extern struct snd_soc_platform s3c24xx_pcm_soc_platform;
+extern struct snd_ac97_bus_ops s3c24xx_ac97_ops;
+
+#endif
diff --git a/sound/soc/samsung/s3c-idma.c b/sound/soc/samsung/s3c-idma.c
new file mode 100644
index 0000000..c3b8c74
--- /dev/null
+++ b/sound/soc/samsung/s3c-idma.c
@@ -0,0 +1,533 @@
+/*
+ * s3c-idma.c -- I2S0's Internal Dma driver
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ * Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <plat/regs-iis.h>
+
+#include "s3c-dma.h"
+#include "s3c-idma.h"
+
+/** Debug **/
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#define dump_i2s() do { \
+ printk(KERN_INFO \
+ "%s:%s:%d\n", \
+ __FILE__, __func__, __LINE__); \
+ printk(KERN_INFO \
+ "\tS3C_IISCON : %x", \
+ readl(s3c_idma.regs + S3C2412_IISCON));\
+ printk(KERN_INFO \
+ "\tS3C_IISMOD : %x\n", \
+ readl(s3c_idma.regs + S3C2412_IISMOD));\
+ printk(KERN_INFO \
+ "\tS3C_IISFIC : %x", \
+ readl(s3c_idma.regs + S3C2412_IISFIC));\
+ printk(KERN_INFO \
+ "\tS3C_IISFICS : %x", \
+ readl(s3c_idma.regs + S5P_IISFICS));\
+ printk(KERN_INFO \
+ "\tS3C_IISPSR : %x\n", \
+ readl(s3c_idma.regs + S3C2412_IISPSR));\
+ printk(KERN_INFO \
+ "\tS3C_IISAHB : %x\n", \
+ readl(s3c_idma.regs + S5P_IISAHB));\
+ printk(KERN_INFO \
+ "\tS3C_IISSTR : %x\n", \
+ readl(s3c_idma.regs + S5P_IISSTR));\
+ printk(KERN_INFO \
+ "\tS3C_IISSIZE : %x\n", \
+ readl(s3c_idma.regs + S5P_IISSIZE));\
+ printk(KERN_INFO \
+ "\tS3C_IISADDR0 : %x\n", \
+ readl(s3c_idma.regs + S5P_IISADDR0));\
+ printk(KERN_INFO \
+ "\tS5P_CLKGATE_D20 : %x\n", \
+ readl(S5P_CLKGATE_D20));\
+ printk(KERN_INFO \
+ "\tS5P_LPMP_MODE_SEL : %x\n",\
+ readl(S5P_LPMP_MODE_SEL));\
+ } while (0)
+
+static const struct snd_pcm_hardware s3c_idma_hardware = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_U16_LE |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_U24_LE |
+ SNDRV_PCM_FMTBIT_U8 |
+ SNDRV_PCM_FMTBIT_S8,
+ .channels_min = 2,
+ .channels_max = 2,
+ .buffer_bytes_max = MAX_LP_BUFF,
+ .period_bytes_min = 128,
+ .period_bytes_max = 16 * 1024,
+ .periods_min = 2,
+ .periods_max = 128,
+ .fifo_size = 64,
+};
+
+struct lpam_i2s_pdata {
+ spinlock_t lock;
+ int state;
+ dma_addr_t start;
+ dma_addr_t pos;
+ dma_addr_t end;
+ dma_addr_t period;
+
+};
+
+ /********************
+ * Internal DMA i/f *
+ ********************/
+static struct s3c_idma_info {
+ void __iomem *regs;
+ unsigned int dma_prd;
+ unsigned int dma_end;
+ spinlock_t lock;
+ void *token;
+ void (*cb)(void *dt, int bytes_xfer);
+} s3c_idma;
+
+
+static void s3c_idma_getpos(dma_addr_t *src)
+{
+ *src = LP_TXBUFF_ADDR +
+ (readl(s3c_idma.regs + S5P_IISTRNCNT) & 0xffffff) * 4;
+}
+
+void i2sdma_getpos(dma_addr_t *src)
+{
+ if (audio_clk_gated == 0 && i2s_trigger_stop == 0)
+ *src = LP_TXBUFF_ADDR +
+ (readl(s3c_idma.regs + S5P_IISTRNCNT) & 0xffffff) * 4;
+ else
+ *src = LP_TXBUFF_ADDR;
+
+}
+
+static int s3c_idma_enqueue(void *token)
+{
+ u32 val;
+
+ spin_lock(&s3c_idma.lock);
+ s3c_idma.token = token;
+ spin_unlock(&s3c_idma.lock);
+
+ pr_debug("%s: %x@%x\n", __func__, MAX_LP_BUFF, LP_TXBUFF_ADDR);
+
+ /* Internal DMA Level0 Interrupt Address */
+ val = LP_TXBUFF_ADDR + s3c_idma.dma_prd;
+ writel(val, s3c_idma.regs + S5P_IISADDR0);
+
+ /* Start address0 of I2S internal DMA operation. */
+ val = readl(s3c_idma.regs + S5P_IISSTR);
+ val = LP_TXBUFF_ADDR;
+ writel(val, s3c_idma.regs + S5P_IISSTR);
+
+ /*
+ * Transfer block size for I2S internal DMA.
+ * Should decide transfer size before start dma operation
+ */
+ val = readl(s3c_idma.regs + S5P_IISSIZE);
+ val &= ~(S5P_IISSIZE_TRNMSK << S5P_IISSIZE_SHIFT);
+
+ val |= ((((s3c_idma.dma_end & 0x1ffff) >> 2) &
+ S5P_IISSIZE_TRNMSK) << S5P_IISSIZE_SHIFT);
+ writel(val, s3c_idma.regs + S5P_IISSIZE);
+
+ return 0;
+}
+
+static void s3c_idma_setcallbk(void (*cb)(void *, int), unsigned prd)
+{
+ spin_lock(&s3c_idma.lock);
+ s3c_idma.cb = cb;
+ s3c_idma.dma_prd = prd;
+ spin_unlock(&s3c_idma.lock);
+
+ pr_debug("%s:%d dma_period=%x\n", __func__, __LINE__, s3c_idma.dma_prd);
+}
+
+static void s3c_idma_ctrl(int op)
+{
+ u32 val;
+
+ spin_lock(&s3c_idma.lock);
+
+ val = readl(s3c_idma.regs + S5P_IISAHB);
+
+ switch (op) {
+ case LPAM_DMA_START:
+ val |= (S5P_IISAHB_INTENLVL0 | S5P_IISAHB_DMAEN);
+ break;
+ case LPAM_DMA_STOP:
+ /* Disable LVL Interrupt and DMA Operation */
+ val &= ~(S5P_IISAHB_INTENLVL0 | S5P_IISAHB_DMAEN);
+ break;
+ default:
+ spin_unlock(&s3c_idma.lock);
+ return;
+ }
+
+ writel(val, s3c_idma.regs + S5P_IISAHB);
+
+ spin_unlock(&s3c_idma.lock);
+}
+
+static void s3c_idma_done(void *id, int bytes_xfer)
+{
+ struct snd_pcm_substream *substream = id;
+ struct lpam_i2s_pdata *prtd = substream->runtime->private_data;
+
+ pr_debug("%s:%d\n", __func__, __LINE__);
+
+ if (prtd && (prtd->state & ST_RUNNING))
+ snd_pcm_period_elapsed(substream);
+}
+
+static int s3c_idma_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct lpam_i2s_pdata *prtd = substream->runtime->private_data;
+ unsigned long idma_totbytes;
+
+ pr_debug("Entered %s\n", __func__);
+
+ idma_totbytes = params_buffer_bytes(params);
+ prtd->end = LP_TXBUFF_ADDR + idma_totbytes;
+ prtd->period = params_periods(params);
+ s3c_idma.dma_end = prtd->end;
+
+ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+ memset(runtime->dma_area, 0, idma_totbytes);
+
+ runtime->dma_bytes = idma_totbytes;
+
+ s3c_idma_setcallbk(s3c_idma_done, params_period_bytes(params));
+
+ prtd->start = runtime->dma_addr;
+ prtd->pos = prtd->start;
+ prtd->end = prtd->start + idma_totbytes;
+
+ pr_debug("DmaAddr=@%x Total=%lubytes PrdSz=%u #Prds=%u dma_area=0x%x\n",
+ prtd->start, idma_totbytes, params_period_bytes(params),
+ prtd->period, (unsigned int)runtime->dma_area);
+
+ return 0;
+}
+
+static int s3c_idma_hw_free(struct snd_pcm_substream *substream)
+{
+ pr_debug("Entered %s\n", __func__);
+
+ snd_pcm_set_runtime_buffer(substream, NULL);
+
+ return 0;
+}
+
+static int s3c_idma_prepare(struct snd_pcm_substream *substream)
+{
+ struct lpam_i2s_pdata *prtd = substream->runtime->private_data;
+
+ pr_debug("Entered %s\n", __func__);
+
+ prtd->pos = prtd->start;
+
+ /* flush the DMA channel */
+ s3c_idma_ctrl(LPAM_DMA_STOP);
+ s3c_idma_enqueue((void *)substream);
+
+ return 0;
+}
+
+static int s3c_idma_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+ struct lpam_i2s_pdata *prtd = substream->runtime->private_data;
+ int ret = 0;
+
+ pr_debug("Entered %s\n", __func__);
+
+ spin_lock(&prtd->lock);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ prtd->state |= ST_RUNNING;
+ s3c_idma_ctrl(LPAM_DMA_START);
+ break;
+
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ prtd->state &= ~ST_RUNNING;
+ s3c_idma_ctrl(LPAM_DMA_STOP);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ spin_unlock(&prtd->lock);
+
+ return ret;
+}
+
+static snd_pcm_uframes_t
+ s3c_idma_pointer(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct lpam_i2s_pdata *prtd = runtime->private_data;
+ dma_addr_t src;
+ unsigned long res;
+
+ spin_lock(&prtd->lock);
+
+ s3c_idma_getpos(&src);
+ res = src - prtd->start;
+
+ spin_unlock(&prtd->lock);
+
+ if (res >= snd_pcm_lib_buffer_bytes(substream)) {
+ if (res == snd_pcm_lib_buffer_bytes(substream))
+ res = 0;
+ }
+
+ return bytes_to_frames(substream->runtime, res);
+}
+
+static int s3c_idma_mmap(struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ unsigned long size, offset;
+ int ret;
+
+ pr_debug("Entered %s\n", __func__);
+
+ /* From snd_pcm_lib_mmap_iomem */
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+ vma->vm_flags |= VM_IO;
+ size = vma->vm_end - vma->vm_start;
+ offset = vma->vm_pgoff << PAGE_SHIFT;
+ ret = io_remap_pfn_range(vma, vma->vm_start,
+ (runtime->dma_addr + offset) >> PAGE_SHIFT,
+ size, vma->vm_page_prot);
+
+ return ret;
+}
+
+static irqreturn_t s3c_iis_irq(int irqno, void *dev_id)
+{
+ u32 iiscon, iisahb, val, addr;
+
+ /* dump_i2s(); */
+ iisahb = readl(s3c_idma.regs + S5P_IISAHB);
+ iiscon = readl(s3c_idma.regs + S3C2412_IISCON);
+
+ if (iiscon & (1<<26)) {
+ pr_info("RxFIFO overflow interrupt\n");
+ writel(iiscon | (1<<26), s3c_idma.regs+S3C2412_IISCON);
+ }
+ if (iiscon & S5P_IISCON_FTXSURSTAT) {
+ iiscon |= S5P_IISCON_FTXURSTATUS;
+ writel(iiscon, s3c_idma.regs + S3C2412_IISCON);
+ pr_debug("TX_S underrun interrupt IISCON = 0x%08x\n",
+ readl(s3c_idma.regs + S3C2412_IISCON));
+ }
+
+ if (iiscon & S5P_IISCON_FTXURSTATUS) {
+ iiscon &= ~S5P_IISCON_FTXURINTEN;
+ iiscon |= S5P_IISCON_FTXURSTATUS;
+ writel(iiscon, s3c_idma.regs + S3C2412_IISCON);
+ pr_debug("TX_P underrun interrupt IISCON = 0x%08x\n",
+ readl(s3c_idma.regs + S3C2412_IISCON));
+ }
+
+ /* Check internal DMA level interrupt. */
+ if (iisahb & S5P_IISAHB_LVL0INT)
+ val = S5P_IISAHB_CLRLVL0;
+ else
+ val = 0;
+
+ if (val) {
+ iisahb |= val;
+ writel(iisahb, s3c_idma.regs + S5P_IISAHB);
+
+ addr = readl(s3c_idma.regs + S5P_IISADDR0);
+ addr += s3c_idma.dma_prd;
+
+ if (addr >= s3c_idma.dma_end)
+ addr = LP_TXBUFF_ADDR;
+
+ writel(addr, s3c_idma.regs + S5P_IISADDR0);
+
+ /* Finished dma transfer ? */
+ if (iisahb & S5P_IISLVLINTMASK) {
+ if (s3c_idma.cb)
+ s3c_idma.cb(s3c_idma.token, s3c_idma.dma_prd);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int s3c_idma_open(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct lpam_i2s_pdata *prtd;
+ int ret;
+
+ pr_debug("Entered %s\n", __func__);
+
+ snd_soc_set_runtime_hwparams(substream, &s3c_idma_hardware);
+
+ prtd = kzalloc(sizeof(struct lpam_i2s_pdata), GFP_KERNEL);
+ if (prtd == NULL)
+ return -ENOMEM;
+
+ ret = request_irq(IRQ_I2S0, s3c_iis_irq, 0, "s3c-i2s", prtd);
+ if (ret < 0) {
+ pr_err("fail to claim i2s irq , ret = %d\n", ret);
+ kfree(prtd);
+ return ret;
+ }
+
+ spin_lock_init(&prtd->lock);
+
+ runtime->private_data = prtd;
+
+ return 0;
+}
+
+static int s3c_idma_close(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct lpam_i2s_pdata *prtd = runtime->private_data;
+
+ pr_debug("Entered %s, prtd = %p\n", __func__, prtd);
+
+ free_irq(IRQ_I2S0, prtd);
+
+ if (!prtd)
+ pr_err("s3c_idma_close called with prtd == NULL\n");
+
+ kfree(prtd);
+
+ return 0;
+}
+
+static struct snd_pcm_ops s3c_idma_ops = {
+ .open = s3c_idma_open,
+ .close = s3c_idma_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .trigger = s3c_idma_trigger,
+ .pointer = s3c_idma_pointer,
+ .mmap = s3c_idma_mmap,
+ .hw_params = s3c_idma_hw_params,
+ .hw_free = s3c_idma_hw_free,
+ .prepare = s3c_idma_prepare,
+};
+
+static void s3c_idma_pcm_free(struct snd_pcm *pcm)
+{
+ struct snd_pcm_substream *substream;
+ struct snd_dma_buffer *buf;
+
+ pr_debug("Entered %s\n", __func__);
+
+ substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
+ if (!substream)
+ return;
+
+ buf = &substream->dma_buffer;
+ if (!buf->area)
+ return;;
+
+ iounmap(buf->area);
+
+ buf->area = NULL;
+ buf->addr = 0;
+}
+
+static int s3c_idma_preallocate_buffer(struct snd_pcm *pcm, int stream)
+{
+ struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+ struct snd_dma_buffer *buf = &substream->dma_buffer;
+
+ pr_debug("Entered %s\n", __func__);
+ buf->dev.dev = pcm->card->dev;
+ buf->private_data = NULL;
+
+ /* Assign PCM buffer pointers */
+ buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
+ buf->addr = LP_TXBUFF_ADDR;
+ buf->bytes = s3c_idma_hardware.buffer_bytes_max;
+ buf->area = (unsigned char *)ioremap(buf->addr, buf->bytes);
+ pr_info("%s: VA-%p PA-%X %ubytes\n",
+ __func__, buf->area, buf->addr, buf->bytes);
+
+ return 0;
+}
+
+static u64 s3c_idma_mask = DMA_BIT_MASK(32);
+
+static int s3c_idma_pcm_new(struct snd_card *card,
+ struct snd_soc_dai *dai, struct snd_pcm *pcm)
+{
+ int ret = 0;
+
+ pr_debug("Entered %s\n", __func__);
+
+ if (!card->dev->dma_mask)
+ card->dev->dma_mask = &s3c_idma_mask;
+ if (!card->dev->coherent_dma_mask)
+ card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+
+ if (dai->driver->playback.channels_min)
+ ret = s3c_idma_preallocate_buffer(pcm,
+ SNDRV_PCM_STREAM_PLAYBACK);
+
+ return ret;
+}
+
+struct snd_soc_platform_driver idma_soc_platform = {
+ .ops = &s3c_idma_ops,
+ .pcm_new = s3c_idma_pcm_new,
+ .pcm_free = s3c_idma_pcm_free,
+};
+EXPORT_SYMBOL_GPL(idma_soc_platform);
+
+void s5p_idma_init(void *regs)
+{
+ spin_lock_init(&s3c_idma.lock);
+ s3c_idma.regs = regs;
+}
+
+MODULE_AUTHOR("Jaswinder Singh, jassi.brar@samsung.com");
+MODULE_DESCRIPTION("Samsung S5P LP-Audio DMA module");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/s3c-idma.h b/sound/soc/samsung/s3c-idma.h
new file mode 100644
index 0000000..351c3c3
--- /dev/null
+++ b/sound/soc/samsung/s3c-idma.h
@@ -0,0 +1,37 @@
+/*
+ * s3c-idma.h -- I2S0's Internal Dma driver
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ * Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __S3C_IDMA_H_
+#define __S3C_IDMA_H_
+
+#ifdef CONFIG_ARCH_S5PC1XX /* S5PC100 */
+#define MAX_LP_BUFF (128 * 1024)
+#define LP_DMA_PERIOD (105 * 1024)
+#else
+#define MAX_LP_BUFF (160 * 1024)
+#define LP_DMA_PERIOD (128 * 1024)
+#endif
+
+#define LP_TXBUFF_ADDR (0xC0000000)
+#define S5P_IISLVLINTMASK (0xf<<20)
+
+/* dma_state */
+#define LPAM_DMA_STOP 0
+#define LPAM_DMA_START 1
+
+extern struct snd_soc_platform_driver idma_soc_platform;
+extern int i2s_trigger_stop;
+extern bool audio_clk_gated ;
+void s5p_idma_init(void *regs);
+
+#endif /* __S3C_IDMA_H_ */
diff --git a/sound/soc/samsung/s5p-i2s_sec.c b/sound/soc/samsung/s5p-i2s_sec.c
new file mode 100644
index 0000000..747dd1c
--- /dev/null
+++ b/sound/soc/samsung/s5p-i2s_sec.c
@@ -0,0 +1,355 @@
+/*
+ * s5p-i2s_sec.c -- Secondary Fifo driver for I2S_v5
+ *
+ * (c) 2009 Samsung Electronics Co. Ltd
+ * - Jaswinder Singh Brar <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/regs-iis.h>
+
+#include <mach/regs-audss.h>
+#include <mach/dma.h>
+#include "s3c-dma.h"
+#include "s3c-idma.h"
+#include "s3c-i2s-v2.h"
+
+#define S3C64XX_DIV_BCLK S3C_I2SV2_DIV_BCLK
+#define S3C64XX_DIV_RCLK S3C_I2SV2_DIV_RCLK
+#define S3C64XX_DIV_PRESCALER S3C_I2SV2_DIV_PRESCALER
+
+#define S3C64XX_CLKSRC_PCLK (0)
+#define S3C64XX_CLKSRC_MUX (1)
+#define S3C64XX_CLKSRC_CDCLK (2)
+
+static void __iomem *s5p_i2s0_regs;
+
+static struct s3c2410_dma_client s5p_dma_client_outs = {
+ .name = "I2S_Sec PCM Stereo out"
+};
+
+static struct s3c_dma_params s5p_i2s_sec_pcm_out = {
+ .channel = DMACH_I2S0S_TX,
+ .client = &s5p_dma_client_outs,
+ .dma_size = 4,
+};
+
+static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
+{
+ return snd_soc_dai_get_drvdata(cpu_dai);
+}
+
+static void s5p_snd_rxctrl(int on)
+{
+ u32 fic, con, mod;
+
+ pr_debug("%s(%d)\n", __func__, on);
+
+ fic = readl(s5p_i2s0_regs + S3C2412_IISFIC);
+ con = readl(s5p_i2s0_regs + S3C2412_IISCON);
+ mod = readl(s5p_i2s0_regs + S3C2412_IISMOD);
+
+ pr_debug("%s: On=%d..IIS: CON=%x MOD=%x FIC=%x\n",
+ __func__, on, con, mod, fic);
+
+ if (on) {
+ con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
+ con &= ~S3C2412_IISCON_RXDMA_PAUSE;
+ con &= ~S3C2412_IISCON_RXCH_PAUSE;
+
+ switch (mod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_TXRX:
+ case S3C2412_IISMOD_MODE_RXONLY:
+ /* do nothing, we are in the right mode */
+ break;
+
+ case S3C2412_IISMOD_MODE_TXONLY:
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ mod |= S3C2412_IISMOD_MODE_TXRX;
+ break;
+
+ default:
+ printk(KERN_WARNING
+ "RXEN: Invalid MODE %x in IISMOD\n",
+ mod & S3C2412_IISMOD_MODE_MASK);
+ }
+
+ writel(mod, s5p_i2s0_regs + S3C2412_IISMOD);
+ writel(con, s5p_i2s0_regs + S3C2412_IISCON);
+ } else {
+ /* See txctrl notes on FIFOs. */
+
+ con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
+ con |= S3C2412_IISCON_RXDMA_PAUSE;
+ con |= S3C2412_IISCON_RXCH_PAUSE;
+
+ switch (mod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_RXONLY:
+ con &= ~S3C2412_IISCON_IIS_ACTIVE;
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ break;
+
+ case S3C2412_IISMOD_MODE_TXRX:
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ mod |= S3C2412_IISMOD_MODE_TXONLY;
+ break;
+
+ default:
+ printk(KERN_WARNING
+ "RXDIS: Invalid MODE %x in IISMOD\n",
+ mod & S3C2412_IISMOD_MODE_MASK);
+ }
+
+ writel(con, s5p_i2s0_regs + S3C2412_IISCON);
+ writel(mod, s5p_i2s0_regs + S3C2412_IISMOD);
+ }
+
+ fic = readl(s5p_i2s0_regs + S3C2412_IISFIC);
+ pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
+}
+
+static void s5p_snd_txctrl(int on)
+{
+ u32 iiscon, iismod;
+ iiscon = readl(s5p_i2s0_regs + S3C2412_IISCON);
+ iismod = readl(s5p_i2s0_regs + S3C2412_IISMOD);
+ pr_debug("%s: On=%d . IIS: CON=%x MOD=%x\n",
+ __func__, on, iiscon, iismod);
+
+ if (on) {
+ iiscon |= S3C2412_IISCON_IIS_ACTIVE;
+ iiscon &= ~S3C2412_IISCON_TXCH_PAUSE;
+ iiscon &= ~S5P_IISCON_TXSDMAPAUSE;
+ iiscon |= S5P_IISCON_TXSDMACTIVE;
+
+ switch (iismod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_TXONLY:
+ case S3C2412_IISMOD_MODE_TXRX:
+ /* do nothing, we are in the right mode */
+ break;
+
+ case S3C2412_IISMOD_MODE_RXONLY:
+ iismod &= ~S3C2412_IISMOD_MODE_MASK;
+ iismod |= S3C2412_IISMOD_MODE_TXRX;
+ break;
+
+ default:
+ printk(KERN_WARNING
+ "TXEN: Invalid MODE %x in IISMOD\n",
+ iismod & S3C2412_IISMOD_MODE_MASK);
+ break;
+ }
+
+ writel(iiscon, s5p_i2s0_regs + S3C2412_IISCON);
+ writel(iismod, s5p_i2s0_regs + S3C2412_IISMOD);
+ } else {
+ iiscon |= S5P_IISCON_TXSDMAPAUSE;
+ iiscon &= ~S5P_IISCON_TXSDMACTIVE;
+
+ /* return if primary is active */
+ if (iiscon & S3C2412_IISCON_TXDMA_ACTIVE) {
+ writel(iiscon, s5p_i2s0_regs + S3C2412_IISCON);
+ return;
+ }
+
+ iiscon |= S3C2412_IISCON_TXCH_PAUSE;
+
+ switch (iismod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_TXRX:
+ iismod &= ~S3C2412_IISMOD_MODE_MASK;
+ iismod |= S3C2412_IISMOD_MODE_RXONLY;
+ break;
+
+ case S3C2412_IISMOD_MODE_TXONLY:
+ iismod &= ~S3C2412_IISMOD_MODE_MASK;
+ iiscon &= ~S3C2412_IISCON_IIS_ACTIVE;
+ break;
+
+ default:
+ printk(KERN_WARNING
+ "TXDIS: Invalid MODE %x in IISMOD\n",
+ iismod & S3C2412_IISMOD_MODE_MASK);
+ break;
+ }
+
+
+ writel(iismod, s5p_i2s0_regs + S3C2412_IISMOD);
+ writel(iiscon, s5p_i2s0_regs + S3C2412_IISCON);
+ }
+}
+
+#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
+
+/*
+ * Wait for the LR signal to allow synchronisation to the L/R clock
+ * from the codec. May only be needed for slave mode.
+ */
+static int s5p_snd_lrsync(void)
+{
+ u32 iiscon;
+ unsigned long loops = msecs_to_loops(1);
+
+ pr_debug("Entered %s\n", __func__);
+
+ while (--loops) {
+ iiscon = readl(s5p_i2s0_regs + S3C2412_IISCON);
+ if (iiscon & S3C2412_IISCON_LRINDEX)
+ break;
+
+ cpu_relax();
+ }
+
+ if (!loops) {
+ pr_debug("%s: timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+int s5p_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ u32 iismod;
+
+ snd_soc_dai_set_dma_data(rtd->cpu_dai,
+ substream, &s5p_i2s_sec_pcm_out);
+
+ iismod = readl(s5p_i2s0_regs + S3C2412_IISMOD);
+
+ /* Copy the same bps as Primary */
+ iismod &= ~S5P_IISMOD_BLCSMASK;
+ iismod |= ((iismod & S5P_IISMOD_BLCPMASK) << 2);
+
+ writel(iismod, s5p_i2s0_regs + S3C2412_IISMOD);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s5p_i2s_hw_params);
+
+int s5p_i2s_startup(struct snd_soc_dai *dai)
+{
+ u32 iiscon, iisfic;
+ u32 iismod, iisahb;
+
+ iiscon = readl(s5p_i2s0_regs + S3C2412_IISCON);
+ iismod = readl(s5p_i2s0_regs + S3C2412_IISMOD);
+ iisahb = readl(s5p_i2s0_regs + S5P_IISAHB);
+
+ iisahb |= (S5P_IISAHB_DMARLD | S5P_IISAHB_DISRLDINT);
+ iismod |= S5P_IISMOD_TXSLP;
+
+ writel(iisahb, s5p_i2s0_regs + S5P_IISAHB);
+ writel(iismod, s5p_i2s0_regs + S3C2412_IISMOD);
+
+ s5p_snd_txctrl(0);
+ /*
+ * Don't turn-off RX setting as recording may be
+ * active during playback startup
+ * s5p_snd_rxctrl(0);
+ */
+
+ /* FIFOs must be flushed before enabling PSR
+ * and other MOD bits, so we do it here. */
+ if (iiscon & S5P_IISCON_TXSDMACTIVE)
+ return 0;
+
+ iisfic = readl(s5p_i2s0_regs + S5P_IISFICS);
+ iisfic |= S3C2412_IISFIC_TXFLUSH;
+ writel(iisfic, s5p_i2s0_regs + S5P_IISFICS);
+
+ do {
+ cpu_relax();
+ } while ((__raw_readl(s5p_i2s0_regs + S5P_IISFICS) >> 8) & 0x7f);
+
+ iisfic = readl(s5p_i2s0_regs + S5P_IISFICS);
+ iisfic &= ~S3C2412_IISFIC_TXFLUSH;
+ writel(iisfic, s5p_i2s0_regs + S5P_IISFICS);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s5p_i2s_startup);
+
+int i2s_trigger_stop ;
+EXPORT_SYMBOL_GPL(i2s_trigger_stop);
+int s5p_i2s_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ /* We don't configure clocks from this Sec i/f.
+ * So, we simply wait enough time for LRSYNC to
+ * get synced and not check return 'error'
+ */
+ s5p_snd_lrsync();
+ s5p_snd_txctrl(1);
+ i2s_trigger_stop = 0;
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ i2s_trigger_stop = 1;
+ s5p_snd_txctrl(0);
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s5p_i2s_trigger);
+
+struct snd_soc_dai i2s_sec_fifo_dai = {
+ .name = "i2s-sec-fifo",
+ .id = 0,
+};
+EXPORT_SYMBOL_GPL(i2s_sec_fifo_dai);
+
+
+void s5p_i2s_sec_init(void *regs, dma_addr_t phys_base)
+{
+ u32 val;
+#ifdef CONFIG_ARCH_S5PV210
+ /* We use I2SCLK for rate generation, so set EPLLout as
+ * the parent of I2SCLK.
+ */
+ val = readl(S5P_CLKSRC_AUDSS);
+ val &= ~(0x3<<2);
+ val |= (1<<0);
+ writel(val, S5P_CLKSRC_AUDSS);
+
+ val = readl(S5P_CLKGATE_AUDSS);
+ val |= (0x7f<<0);
+ writel(val, S5P_CLKGATE_AUDSS);
+#else
+ #error INITIALIZE HERE!
+#endif
+
+ s5p_i2s0_regs = regs;
+ s5p_i2s_sec_pcm_out.dma_addr = phys_base + S5P_IISTXDS;
+
+ s5p_snd_rxctrl(0);
+ s5p_snd_txctrl(0);
+ s5p_idma_init(regs);
+}
+
+/* Module information */
+MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
+MODULE_DESCRIPTION("S5P I2S-SecFifo SoC Interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/s5pc1xx-i2s.c b/sound/soc/samsung/s5pc1xx-i2s.c
new file mode 100644
index 0000000..674ccaa
--- /dev/null
+++ b/sound/soc/samsung/s5pc1xx-i2s.c
@@ -0,0 +1,1152 @@
+/* sound/soc/s3c24xx/s5pc1xx-i2s.c
+ *
+ * ALSA SoC Audio Layer - S3C64XX I2S driver
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+
+#include <sound/soc.h>
+#include <sound/pcm_params.h>
+
+#include <plat/regs-iis.h>
+#include <plat/audio.h>
+
+#include <mach/dma.h>
+
+#include <mach/map.h>
+#include <mach/regs-audss.h>
+#include <mach/regs-clock.h>
+#include <linux/wakelock.h>
+#include "s3c-dma.h"
+#include "s5pc1xx-i2s.h"
+
+/*
+ * The value should be set to maximum of the total number
+ * of I2Sv3 controllers that any supported SoC has.
+ */
+#define MAX_I2SV3 2
+
+static struct s3c2410_dma_client s3c64xx_dma_client_out = {
+ .name = "I2S PCM Stereo out"
+};
+
+static struct s3c2410_dma_client s3c64xx_dma_client_in = {
+ .name = "I2S PCM Stereo in"
+};
+
+static struct snd_soc_dai_ops s3c64xx_i2s_dai_ops;
+static struct s3c_dma_params s3c64xx_i2s_pcm_stereo_out[MAX_I2SV3];
+static struct s3c_dma_params s3c64xx_i2s_pcm_stereo_in[MAX_I2SV3];
+static struct s3c_i2sv2_info s3c64xx_i2s[MAX_I2SV3];
+
+static struct snd_soc_dai_driver s3c64xx_i2s_dai_driver[MAX_I2SV3];
+bool audio_clk_gated; /* At first, clock & i2s0_pd is enabled in probe() */
+//EXPORT_SYMBOL_GPL(s3c64xx_i2s_dai);
+
+/* For I2S Clock/Power Gating */
+static int tx_clk_enabled ;
+static int rx_clk_enabled ;
+static int reg_saved_ok ;
+
+void dump_i2s(struct s3c_i2sv2_info *i2s)
+{
+ printk(KERN_INFO "IISMOD=0x%x..IISCON=0x%x..IISPSR=0x%x\
+ IISAHB=0x%x..\n" , readl(i2s->regs + S3C2412_IISMOD),
+ readl(i2s->regs + S3C2412_IISCON),
+ readl(i2s->regs + S3C2412_IISPSR),
+ readl(i2s->regs + S5P_IISAHB));
+ printk(KERN_INFO "..AUDSSRC=0x%x..AUDSSDIV=0x%x..\
+ AUDSSGATE=0x%x..\n" , readl(S5P_CLKSRC_AUDSS),
+ readl(S5P_CLKDIV_AUDSS), readl(S5P_CLKGATE_AUDSS));
+}
+
+#define dump_reg(iis)
+
+static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
+{
+ return snd_soc_dai_get_drvdata(cpu_dai);
+}
+
+struct clk *s3c64xx_i2s_get_clock(struct snd_soc_dai *dai)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+ u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
+
+ if (iismod & S3C64XX_IISMOD_IMS_SYSMUX)
+ return i2s->iis_clk;
+ else
+ return i2s->iis_ipclk;
+}
+EXPORT_SYMBOL_GPL(s3c64xx_i2s_get_clock);
+
+void s5p_i2s_set_clk_enabled(struct snd_soc_dai *dai, bool state)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+
+ pr_debug("..entering %s\n", __func__);
+
+ if (state) {
+ if (audio_clk_gated == 1)
+ regulator_enable(i2s->regulator);
+
+ if (dai->id == 0) { /* I2S V5.1? */
+ clk_enable(i2s->iis_ipclk);
+ clk_enable(i2s->iis_clk);
+ clk_enable(i2s->iis_busclk);
+ }
+ audio_clk_gated = 0;
+ } else {
+ if (dai->id == 0) { /* I2S V5.1? */
+ clk_disable(i2s->iis_busclk);
+ clk_disable(i2s->iis_clk);
+ clk_disable(i2s->iis_ipclk);
+ }
+
+ if (audio_clk_gated == 0)
+ regulator_disable(i2s->regulator);
+
+ audio_clk_gated = 1;
+ }
+}
+
+static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+ u32 iismod;
+
+ pr_debug("Entered %s\n", __func__);
+
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ snd_soc_dai_set_dma_data(dai, substream,
+ i2s->dma_playback);
+ else
+ snd_soc_dai_set_dma_data(dai, substream,
+ i2s->dma_capture);
+
+ /* Working copies of register */
+ iismod = readl(i2s->regs + S3C2412_IISMOD);
+ pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
+
+ switch (params_channels(params)) {
+ case 1:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ i2s->dma_playback->dma_size = 2;
+ else
+ i2s->dma_capture->dma_size = 2;
+ break;
+ case 2:
+ break;
+ default:
+ break;
+ }
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S8:
+ iismod |= S3C2412_IISMOD_8BIT;
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ iismod &= ~S3C2412_IISMOD_8BIT;
+ break;
+ }
+#endif
+
+#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5P)
+ iismod &= ~(S3C64XX_IISMOD_BLC_MASK | S3C2412_IISMOD_BCLK_MASK);
+ /* Sample size */
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S8:
+ /* 8 bit sample, 16fs BCLK */
+ iismod |= (S3C64XX_IISMOD_BLC_8BIT | S3C2412_IISMOD_BCLK_16FS);
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ /* 16 bit sample, 32fs BCLK */
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ /* 24 bit sample, 48fs BCLK */
+ iismod |= (S3C64XX_IISMOD_BLC_24BIT | S3C2412_IISMOD_BCLK_48FS);
+ break;
+ }
+
+ /* Set the IISMOD[25:24](BLC_P) to same value */
+ iismod &= ~(S5P_IISMOD_BLCPMASK);
+ iismod |= ((iismod & S3C64XX_IISMOD_BLC_MASK) << 11);
+#endif
+
+ writel(iismod, i2s->regs + S3C2412_IISMOD);
+ pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
+ return 0;
+}
+
+static int s5p_i2s_wr_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ s5p_i2s_hw_params(substream, params, dai);
+ else
+ s3c2412_i2s_hw_params(substream, params, dai);
+
+#else
+ s3c2412_i2s_hw_params(substream, params, dai);
+#endif
+ return 0;
+}
+
+#define S3C2412_I2S_DEBUG_CON 1
+
+#define bit_set(v, b) (((v) & (b)) ? 1 : 0)
+
+#if S3C2412_I2S_DEBUG_CON
+static void dbg_showcon(const char *fn, u32 con)
+{
+ printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d,\
+ RXFFULL=%d\n", fn,
+ bit_set(con, S3C2412_IISCON_LRINDEX),
+ bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
+ bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
+ bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
+ bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
+
+ printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
+ fn,
+ bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
+ bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
+ bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
+ bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
+ printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
+ bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
+ bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
+ bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
+}
+#else
+static inline void dbg_showcon(const char *fn, u32 con)
+{
+}
+#endif
+
+/* Turn on or off the transmission path. */
+static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
+{
+ void __iomem *regs = i2s->regs;
+ u32 fic, con, mod;
+
+ pr_debug("%s(%d)\n", __func__, on);
+
+ fic = readl(regs + S3C2412_IISFIC);
+ con = readl(regs + S3C2412_IISCON);
+ mod = readl(regs + S3C2412_IISMOD);
+
+ pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
+
+ if (on) {
+ con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
+ con &= ~S3C2412_IISCON_TXDMA_PAUSE;
+ con &= ~S3C2412_IISCON_TXCH_PAUSE;
+
+ switch (mod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_TXONLY:
+ case S3C2412_IISMOD_MODE_TXRX:
+ /* do nothing, we are in the right mode */
+ break;
+
+ case S3C2412_IISMOD_MODE_RXONLY:
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ mod |= S3C2412_IISMOD_MODE_TXRX;
+ break;
+
+ default:
+ dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
+ mod & S3C2412_IISMOD_MODE_MASK);
+ break;
+ }
+
+ writel(con, regs + S3C2412_IISCON);
+ writel(mod, regs + S3C2412_IISMOD);
+ } else {
+ /* Note, we do not have any indication that the FIFO problems
+ * tha the S3C2410/2440 had apply here, so we should be able
+ * to disable the DMA and TX without resetting the FIFOS.
+ */
+
+ con |= S3C2412_IISCON_TXDMA_PAUSE;
+ con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
+ if (con & S5P_IISCON_TXSDMACTIVE) { /* If sec is active */
+ writel(con, regs + S3C2412_IISCON);
+ return;
+ }
+ con |= S3C2412_IISCON_TXCH_PAUSE;
+
+ switch (mod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_TXRX:
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ mod |= S3C2412_IISMOD_MODE_RXONLY;
+ break;
+
+ case S3C2412_IISMOD_MODE_TXONLY:
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ con &= ~S3C2412_IISCON_IIS_ACTIVE;
+ break;
+
+ default:
+ dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
+ mod & S3C2412_IISMOD_MODE_MASK);
+ break;
+ }
+
+ writel(mod, regs + S3C2412_IISMOD);
+ writel(con, regs + S3C2412_IISCON);
+ }
+
+ fic = readl(regs + S3C2412_IISFIC);
+ dbg_showcon(__func__, con);
+ pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
+}
+
+#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
+
+static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
+{
+ void __iomem *regs = i2s->regs;
+ u32 fic, con, mod;
+
+ pr_debug("%s(%d)\n", __func__, on);
+
+ fic = readl(regs + S3C2412_IISFIC);
+ con = readl(regs + S3C2412_IISCON);
+ mod = readl(regs + S3C2412_IISMOD);
+
+ pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
+
+ if (on) {
+ con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
+ con &= ~S3C2412_IISCON_RXDMA_PAUSE;
+ con &= ~S3C2412_IISCON_RXCH_PAUSE;
+
+ switch (mod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_TXRX:
+ case S3C2412_IISMOD_MODE_RXONLY:
+ /* do nothing, we are in the right mode */
+ break;
+
+ case S3C2412_IISMOD_MODE_TXONLY:
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ mod |= S3C2412_IISMOD_MODE_TXRX;
+ break;
+
+ default:
+ dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
+ mod & S3C2412_IISMOD_MODE_MASK);
+ }
+
+ writel(mod, regs + S3C2412_IISMOD);
+ writel(con, regs + S3C2412_IISCON);
+ } else {
+ /* See txctrl notes on FIFOs. */
+
+ con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
+ con |= S3C2412_IISCON_RXDMA_PAUSE;
+ con |= S3C2412_IISCON_RXCH_PAUSE;
+
+ switch (mod & S3C2412_IISMOD_MODE_MASK) {
+ case S3C2412_IISMOD_MODE_RXONLY:
+ con &= ~S3C2412_IISCON_IIS_ACTIVE;
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ break;
+
+ case S3C2412_IISMOD_MODE_TXRX:
+ mod &= ~S3C2412_IISMOD_MODE_MASK;
+ mod |= S3C2412_IISMOD_MODE_TXONLY;
+ break;
+
+ default:
+ dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
+ mod & S3C2412_IISMOD_MODE_MASK);
+ }
+
+ writel(con, regs + S3C2412_IISCON);
+ writel(mod, regs + S3C2412_IISMOD);
+ }
+
+ fic = readl(regs + S3C2412_IISFIC);
+ pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
+}
+
+/*
+ * Wait for the LR signal to allow synchronisation to the L/R clock
+ * from the codec. May only be needed for slave mode.
+ */
+static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
+{
+ u32 iiscon;
+ unsigned long loops = msecs_to_loops(5);
+
+ pr_debug("Entered %s\n", __func__);
+
+ while (--loops) {
+ iiscon = readl(i2s->regs + S3C2412_IISCON);
+ if (iiscon & S3C2412_IISCON_LRINDEX)
+ break;
+
+ cpu_relax();
+ }
+
+ if (!loops) {
+ printk(KERN_ERR "%s: timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+ int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
+ unsigned long irqs;
+ int ret = 0;
+
+ pr_debug("Entered %s\n", __func__);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ if (!i2s->master) {
+ ret = s3c2412_snd_lrsync(i2s);
+ if (ret)
+ goto exit_err;
+ }
+
+ local_irq_save(irqs);
+
+ if (capture)
+ s3c2412_snd_rxctrl(i2s, 1);
+ else
+ s3c2412_snd_txctrl(i2s, 1);
+
+ local_irq_restore(irqs);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ local_irq_save(irqs);
+
+ if (capture)
+ s3c2412_snd_rxctrl(i2s, 0);
+ else
+ s3c2412_snd_txctrl(i2s, 0);
+
+ local_irq_restore(irqs);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+exit_err:
+ return ret;
+}
+
+static int s5p_i2s_wr_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ s5p_i2s_trigger(substream, cmd, dai);
+ else
+ s3c2412_i2s_trigger(substream, cmd, dai);
+
+#else
+ s3c2412_i2s_trigger(substream, cmd, dai);
+#endif
+ return 0;
+}
+
+/*
+ * Set S3C2412 I2S DAI format
+ */
+static int s5p_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
+ unsigned int fmt)
+{
+ struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
+ u32 iismod;
+
+ pr_debug("Entered %s\n", __func__);
+
+ iismod = readl(i2s->regs + S3C2412_IISMOD);
+ pr_debug("hw_params r: IISMOD: %x\n", iismod);
+
+#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5P)
+ /* From Rev1.1 datasheet, we have two master and two slave modes:
+ * IMS[11:10]:
+ * 00 = master mode, fed from PCLK
+ * 01 = master mode, fed from CLKAUDIO
+ * 10 = slave mode, using PCLK
+ * 11 = slave mode, using I2SCLK
+ */
+#define IISMOD_MASTER_MASK (1 << 11)
+#define IISMOD_SLAVE (1 << 11)
+#define IISMOD_MASTER (0 << 11)
+#endif
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBM_CFM:
+ i2s->master = 0;
+ iismod &= ~IISMOD_MASTER_MASK;
+ iismod |= IISMOD_SLAVE;
+ break;
+ case SND_SOC_DAIFMT_CBS_CFS:
+ i2s->master = 1;
+ iismod &= ~IISMOD_MASTER_MASK;
+ iismod |= IISMOD_MASTER;
+ break;
+ default:
+ pr_err("unknwon master/slave format\n");
+ return -EINVAL;
+ }
+
+ iismod &= ~S3C2412_IISMOD_SDF_MASK;
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_RIGHT_J:
+ iismod |= S3C2412_IISMOD_LR_RLOW;
+ iismod |= S3C2412_IISMOD_SDF_MSB;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ iismod |= S3C2412_IISMOD_LR_RLOW;
+ iismod |= S3C2412_IISMOD_SDF_LSB;
+ break;
+ case SND_SOC_DAIFMT_I2S:
+ iismod &= ~S3C2412_IISMOD_LR_RLOW;
+ iismod |= S3C2412_IISMOD_SDF_IIS;
+ break;
+ default:
+ pr_err("Unknown data format\n");
+ return -EINVAL;
+ }
+
+ writel(iismod, i2s->regs + S3C2412_IISMOD);
+ pr_debug("hw_params w: IISMOD: %x\n", iismod);
+ return 0;
+}
+
+static int s5p_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
+ int div_id, int div)
+{
+ struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
+ u32 reg;
+
+ pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
+
+ switch (div_id) {
+ case S3C_I2SV2_DIV_BCLK:
+ if (div > 3) {
+ /* convert value to bit field */
+ switch (div) {
+ case 16:
+ div = S3C2412_IISMOD_BCLK_16FS;
+ break;
+ case 32:
+ div = S3C2412_IISMOD_BCLK_32FS;
+ break;
+ case 24:
+ div = S3C2412_IISMOD_BCLK_24FS;
+ break;
+ case 48:
+ div = S3C2412_IISMOD_BCLK_48FS;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ reg = readl(i2s->regs + S3C2412_IISMOD);
+ reg &= ~S3C2412_IISMOD_BCLK_MASK;
+ writel(reg | div, i2s->regs + S3C2412_IISMOD);
+ pr_debug("%s: MOD=%08x\n", __func__,
+ readl(i2s->regs + S3C2412_IISMOD));
+ break;
+
+ case S3C_I2SV2_DIV_RCLK:
+ if (div > 3) {
+ /* convert value to bit field */
+
+ switch (div) {
+ case 256:
+ div = S3C2412_IISMOD_RCLK_256FS;
+ break;
+ case 384:
+ div = S3C2412_IISMOD_RCLK_384FS;
+ break;
+ case 512:
+ div = S3C2412_IISMOD_RCLK_512FS;
+ break;
+ case 768:
+ div = S3C2412_IISMOD_RCLK_768FS;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ reg = readl(i2s->regs + S3C2412_IISMOD);
+ reg &= ~S3C2412_IISMOD_RCLK_MASK;
+ writel(reg | div, i2s->regs + S3C2412_IISMOD);
+ pr_debug("%s: MOD=%08x\n", __func__,
+ readl(i2s->regs + S3C2412_IISMOD));
+ break;
+
+ case S3C_I2SV2_DIV_PRESCALER:
+ if (div >= 0)
+ writel((div << 8) | S3C2412_IISPSR_PSREN,
+ i2s->regs + S3C2412_IISPSR);
+ else
+ writel(0x0, i2s->regs + S3C2412_IISPSR);
+ pr_debug("%s: PSR=%08x\n", __func__,
+ readl(i2s->regs + S3C2412_IISPSR));
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int s5p_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct clk *clk;
+ struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
+ u32 iismod = readl(i2s->regs + S3C2412_IISMOD);
+
+ switch (clk_id) {
+ case S3C64XX_CLKSRC_PCLK:
+ iismod &= ~S3C64XX_IISMOD_IMS_SYSMUX;
+ break;
+ case S3C64XX_CLKSRC_MUX:
+ iismod |= S3C64XX_IISMOD_IMS_SYSMUX;
+ break;
+
+ case S3C64XX_CLKSRC_CDCLK:
+ switch (dir) {
+ case SND_SOC_CLOCK_IN:
+ iismod |= S3C64XX_IISMOD_CDCLKCON;
+ break;
+ case SND_SOC_CLOCK_OUT:
+ iismod &= ~S3C64XX_IISMOD_CDCLKCON;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+#ifdef USE_CLKAUDIO
+ /* IIS-IP is Master and derives its clocks from I2SCLKD2 */
+ case S3C_CLKSRC_CLKAUDIO:
+ if (!i2s->master)
+ return -EINVAL;
+ iismod &= ~S3C_IISMOD_IMSMASK;
+ iismod |= clk_id;
+ clk = clk_get(NULL, "fout_epll");
+ if (IS_ERR(clk)) {
+ printk(KERN_ERR
+ "failed to get %s\n", "fout_epll");
+ return -EBUSY;
+ }
+ clk_disable(clk);
+ switch (freq) {
+ case 8000:
+ case 16000:
+ case 32000:
+ case 48000:
+ case 64000:
+ case 96000:
+ clk_set_rate(clk, 49152000);
+ break;
+ case 11025:
+ case 22050:
+ case 44100:
+ case 88200:
+ default:
+ clk_set_rate(clk, 67738000);
+ break;
+ }
+ clk_enable(clk);
+ clk_put(clk);
+ break;
+#endif
+ /* IIS-IP is Slave and derives its clocks from the Codec Chip */
+ case S3C64XX_CLKSRC_I2SEXT:
+ iismod &= ~S3C64XX_IISMOD_IMSMASK;
+ iismod |= clk_id;
+ /* Operation clock for I2S logic selected as Audio Bus Clock */
+ iismod |= S3C64XX_IISMOD_OPPCLK;
+
+ clk = clk_get(NULL, "fout_epll");
+ if (IS_ERR(clk)) {
+ printk(KERN_ERR
+ "failed to get %s\n", "fout_epll");
+ return -EBUSY;
+ }
+ clk_disable(clk);
+ clk_set_rate(clk, 67738000);
+ clk_enable(clk);
+ clk_put(clk);
+ break;
+
+ case S3C64XX_CDCLKSRC_EXT:
+ iismod |= S3C64XX_IISMOD_CDCLKCON;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ writel(iismod, i2s->regs + S3C2412_IISMOD);
+
+ return 0;
+}
+
+static int s5p_i2s_wr_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+ u32 iiscon, iisfic;
+
+ if (!tx_clk_enabled && !rx_clk_enabled) {
+ s5p_i2s_set_clk_enabled(dai, 1);
+ if (reg_saved_ok == true) {
+ /* Is this dai for I2Sv5? (I2S0) */
+ if (dai->id == 0) {
+ writel(i2s->suspend_audss_clksrc,
+ S5P_CLKSRC_AUDSS);
+ writel(i2s->suspend_audss_clkdiv,
+ S5P_CLKDIV_AUDSS);
+ writel(i2s->suspend_audss_clkgate,
+ S5P_CLKGATE_AUDSS);
+ }
+ writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
+ writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
+ writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
+ writel(i2s->suspend_iisahb, i2s->regs + S5P_IISAHB);
+ reg_saved_ok = false;
+ pr_debug("I2S Audio Clock enabled and \
+ Registers restored...\n");
+ }
+ }
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ pr_debug("Inside..%s..for playback stream\n" , __func__);
+ tx_clk_enabled = 1;
+ } else {
+ pr_debug("Inside..%s..for capture stream\n" , __func__);
+ rx_clk_enabled = 1;
+ iiscon = readl(i2s->regs + S3C2412_IISCON);
+ if (iiscon & S3C2412_IISCON_RXDMA_ACTIVE)
+ return 0;
+
+ iisfic = readl(i2s->regs + S3C2412_IISFIC);
+ iisfic |= S3C2412_IISFIC_RXFLUSH;
+ writel(iisfic, i2s->regs + S3C2412_IISFIC);
+
+ do {
+ cpu_relax();
+ } while ((__raw_readl(i2s->regs + S3C2412_IISFIC) >> 0) & 0x7f);
+
+ iisfic = readl(i2s->regs + S3C2412_IISFIC);
+ iisfic &= ~S3C2412_IISFIC_RXFLUSH;
+ writel(iisfic, i2s->regs + S3C2412_IISFIC);
+ }
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ s5p_i2s_startup(dai);
+#endif
+ dump_reg(i2s);
+ return 0;
+}
+
+static void s5p_i2s_wr_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ pr_debug("Inside %s for playback stream\n" , __func__);
+ tx_clk_enabled = 0;
+ } else {
+ pr_debug("Inside..%s..for capture stream\n" , __func__);
+ if (readl(i2s->regs + S3C2412_IISCON) & (1<<26)) {
+ pr_debug("\n rx overflow int in %s\n" , __func__);
+ /* clear rxfifo overflow interrupt */
+ writel(readl(i2s->regs + S3C2412_IISCON) | (1<<26),
+ i2s->regs + S3C2412_IISCON);
+ /* flush rx */
+ writel(readl(i2s->regs + S3C2412_IISFIC) | (1<<7) ,
+ i2s->regs + S3C2412_IISFIC);
+ }
+ rx_clk_enabled = 0;
+ }
+
+ if (!tx_clk_enabled && !rx_clk_enabled) {
+ i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
+ i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
+ i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
+ i2s->suspend_iisahb = readl(i2s->regs + S5P_IISAHB);
+ /* Is this dai for I2Sv5? (I2S0) */
+ if (dai->id == 0) {
+ i2s->suspend_audss_clksrc = readl(S5P_CLKSRC_AUDSS);
+ i2s->suspend_audss_clkdiv = readl(S5P_CLKDIV_AUDSS);
+ i2s->suspend_audss_clkgate = readl(S5P_CLKGATE_AUDSS);
+ }
+ reg_saved_ok = true;
+ s5p_i2s_set_clk_enabled(dai, 0);
+ pr_debug("I2S Audio Clock disabled and Registers stored...\n");
+ pr_debug("Inside %s CLkGATE_IP3=0x%x..\n",
+ __func__ , __raw_readl(S5P_CLKGATE_IP3));
+ }
+
+ return;
+}
+
+#define S3C64XX_I2S_RATES \
+ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
+ SNDRV_PCM_RATE_KNOT)
+
+#define S3C64XX_I2S_FMTS \
+ (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+static void s3c64xx_iis_dai_init(struct snd_soc_dai_driver *dai)
+{
+ dai->name = "s5pc1xx-i2s";
+ dai->playback.channels_min = 2;
+ dai->playback.channels_max = 2;
+ dai->playback.rates = S3C64XX_I2S_RATES;
+ dai->playback.formats = S3C64XX_I2S_FMTS;
+ dai->capture.channels_min = 1;
+ dai->capture.channels_max = 2;
+ dai->capture.rates = S3C64XX_I2S_RATES;
+ dai->capture.formats = S3C64XX_I2S_FMTS;
+ dai->ops = &s3c64xx_i2s_dai_ops;
+}
+
+/* suspend/resume are not necessary due to Clock/Pwer gating scheme... */
+#ifdef CONFIG_PM
+static int s5p_i2s_suspend(struct snd_soc_dai *dai)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+
+ if (reg_saved_ok != true) {
+ dump_reg(i2s);
+ i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
+ i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
+ i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
+ i2s->suspend_iisahb = readl(i2s->regs + S5P_IISAHB);
+ if (dai->id == 0) {
+ i2s->suspend_audss_clksrc = readl(S5P_CLKSRC_AUDSS);
+ i2s->suspend_audss_clkdiv = readl(S5P_CLKDIV_AUDSS);
+ i2s->suspend_audss_clkgate = readl(S5P_CLKGATE_AUDSS);
+ }
+ }
+ return 0;
+}
+
+static int s5p_i2s_resume(struct snd_soc_dai *dai)
+{
+ struct s3c_i2sv2_info *i2s = to_info(dai);
+
+ pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
+ dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
+ if (reg_saved_ok != true) {
+ if (dai->id == 0) {
+ writel(i2s->suspend_audss_clksrc, S5P_CLKSRC_AUDSS);
+ writel(i2s->suspend_audss_clkdiv, S5P_CLKDIV_AUDSS);
+ writel(i2s->suspend_audss_clkgate, S5P_CLKGATE_AUDSS);
+ pr_info("Inside %s..@%d\n" , __func__ , __LINE__);
+ }
+ writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
+ writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
+ writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
+ writel(i2s->suspend_iisahb, i2s->regs + S5P_IISAHB);
+ }
+ return 0;
+ /* Is this dai for I2Sv5? */
+ if (dai->id == 0)
+ writel(i2s->suspend_audss_clksrc, S5P_CLKSRC_AUDSS);
+
+ writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
+ i2s->regs + S3C2412_IISFIC);
+
+ ndelay(250);
+ writel(0x0, i2s->regs + S3C2412_IISFIC);
+
+ return 0;
+}
+#else
+#define s3c2412_i2s_suspend NULL
+#define s3c2412_i2s_resume NULL
+#endif /* CONFIG_PM */
+
+int s5p_i2sv5_register_dai(struct device *dev, struct snd_soc_dai_driver *dai)
+{
+ struct snd_soc_dai_ops *ops = dai->ops;
+
+ ops->trigger = s5p_i2s_wr_trigger;
+ ops->hw_params = s5p_i2s_wr_hw_params;
+ ops->set_fmt = s5p_i2s_set_fmt;
+ ops->set_clkdiv = s5p_i2s_set_clkdiv;
+ ops->set_sysclk = s5p_i2s_set_sysclk;
+ ops->startup = s5p_i2s_wr_startup;
+ ops->shutdown = s5p_i2s_wr_shutdown;
+ /* suspend/resume are not necessary due to Clock/Pwer gating scheme */
+ dai->suspend = s5p_i2s_suspend;
+ dai->resume = s5p_i2s_resume;
+ return snd_soc_register_dai(dev, dai);
+}
+
+static __devinit int s3c64xx_iis_dev_probe(struct platform_device *pdev)
+{
+ struct s3c_audio_pdata *i2s_pdata;
+ struct s3c_i2sv2_info *i2s;
+ struct snd_soc_dai_driver *dai;
+ struct resource *res;
+ struct clk *fout_epll, *mout_epll;
+ struct clk *mout_audss = NULL;
+ unsigned long base;
+ unsigned int iismod;
+ int ret = 0;
+ if (pdev->id >= MAX_I2SV3) {
+ dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
+ return -EINVAL;
+ }
+
+ i2s = &s3c64xx_i2s[pdev->id];
+ i2s->dev = &pdev->dev;
+ dai = &s3c64xx_i2s_dai_driver[pdev->id];
+ //dai->dev = &pdev->dev;
+ dai->id = pdev->id;
+ s3c64xx_iis_dai_init(dai);
+
+ i2s->dma_capture = &s3c64xx_i2s_pcm_stereo_in[pdev->id];
+ i2s->dma_playback = &s3c64xx_i2s_pcm_stereo_out[pdev->id];
+
+ res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get I2S-TX dma resource\n");
+ return -ENXIO;
+ }
+ i2s->dma_playback->channel = res->start;
+
+ res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get I2S-RX dma resource\n");
+ return -ENXIO;
+ }
+ i2s->dma_capture->channel = res->start;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get I2S SFR address\n");
+ return -ENXIO;
+ }
+
+ if (!request_mem_region(res->start, resource_size(res),
+ "s3c64xx-i2s")) {
+ dev_err(&pdev->dev, "Unable to request SFR region\n");
+ return -EBUSY;
+ }
+
+ i2s->dma_capture->dma_addr = res->start + S3C2412_IISRXD;
+ i2s->dma_playback->dma_addr = res->start + S3C2412_IISTXD;
+
+ i2s->dma_capture->client = &s3c64xx_dma_client_in;
+ i2s->dma_capture->dma_size = 4;
+ i2s->dma_playback->client = &s3c64xx_dma_client_out;
+ i2s->dma_playback->dma_size = 4;
+
+ i2s_pdata = pdev->dev.platform_data;
+
+ //dai->private_data = i2s;
+ dev_set_drvdata(&pdev->dev, i2s);
+ base = i2s->dma_playback->dma_addr - S3C2412_IISTXD;
+
+ i2s->regs = ioremap(base, 0x100);
+ if (i2s->regs == NULL) {
+ dev_err(&pdev->dev, "cannot ioremap registers\n");
+ return -ENXIO;
+ }
+
+ /* Configure the I2S pins if MUX'ed */
+ if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
+ dev_err(&pdev->dev, "Unable to configure gpio\n");
+ return -EINVAL;
+ }
+
+ /* Get i2s power domain regulator */
+ i2s->regulator = regulator_get(&pdev->dev, "pd");
+ if (IS_ERR(i2s->regulator)) {
+ dev_err(&pdev->dev, "%s: failed to get resource %s\n",
+ __func__, "i2s");
+ return PTR_ERR(i2s->regulator);
+ }
+
+ /* Enable Power domain */
+ regulator_enable(i2s->regulator);
+
+ /* Audio Clock
+ * fout_epll >> mout_epll >> sclk_audio
+ * fout_epll >> mout_audss >> audio-bus(iis_clk)
+ * fout_epll >> dout_audio_bus_clk_i2s(iis_busclk)
+ */
+ fout_epll = clk_get(&pdev->dev, "fout_epll");
+ if (IS_ERR(fout_epll)) {
+ dev_err(&pdev->dev, "failed to get fout_epll\n");
+ goto err;
+ }
+
+ mout_epll = clk_get(&pdev->dev, "mout_epll");
+ if (IS_ERR(mout_epll)) {
+ dev_err(&pdev->dev, "failed to get mout_epll\n");
+ clk_put(fout_epll);
+ goto err;
+ }
+ clk_set_parent(mout_epll, fout_epll);
+
+ i2s->sclk_audio = clk_get(&pdev->dev, "sclk_audio");
+ if (IS_ERR(i2s->sclk_audio)) {
+ dev_err(&pdev->dev, "failed to get sclk_audio\n");
+ ret = PTR_ERR(i2s->sclk_audio);
+ clk_put(i2s->sclk_audio);
+ goto err;
+ }
+ clk_set_parent(i2s->sclk_audio, mout_epll);
+ /* Need not to enable in general */
+ clk_enable(i2s->sclk_audio);
+
+ /* When I2S V5.1 used, initialize audio subsystem clock */
+ /* CLKMUX_ASS */
+ if (pdev->id == 0) {
+ mout_audss = clk_get(NULL, "mout_audss");
+ if (IS_ERR(mout_audss)) {
+ dev_err(&pdev->dev, "failed to get mout_audss\n");
+ goto err1;
+ }
+ clk_set_parent(mout_audss, fout_epll);
+ /*MUX-I2SA*/
+ i2s->iis_clk = clk_get(&pdev->dev, "audio-bus");
+ if (IS_ERR(i2s->iis_clk)) {
+ dev_err(&pdev->dev, "failed to get audio-bus\n");
+ clk_put(mout_audss);
+ goto err2;
+ }
+ clk_set_parent(i2s->iis_clk, mout_audss);
+ /*getting AUDIO BUS CLK*/
+ i2s->iis_busclk = clk_get(NULL, "dout_audio_bus_clk_i2s");
+ if (IS_ERR(i2s->iis_busclk)) {
+ printk(KERN_ERR "failed to get audss_hclk\n");
+ goto err3;
+ }
+ i2s->iis_ipclk = clk_get(&pdev->dev, "i2s_v50");
+ if (IS_ERR(i2s->iis_ipclk)) {
+ dev_err(&pdev->dev, "failed to get i2s_v50_clock\n");
+ goto err4;
+ }
+ }
+
+#if defined(CONFIG_PLAT_S5P)
+ writel(((1<<0)|(1<<31)), i2s->regs + S3C2412_IISCON);
+#endif
+
+ /* Mark ourselves as in TXRX mode so we can run through our cleanup
+ * process without warnings. */
+ iismod = readl(i2s->regs + S3C2412_IISMOD);
+ iismod |= S3C2412_IISMOD_MODE_TXRX;
+ writel(iismod, i2s->regs + S3C2412_IISMOD);
+
+#ifdef CONFIG_S5P_INTERNAL_DMA
+ s5p_i2s_sec_init(i2s->regs, base);
+#endif
+
+ ret = s5p_i2sv5_register_dai(&pdev->dev, dai);
+ if (ret != 0)
+ goto err_i2sv5;
+
+ clk_put(i2s->iis_ipclk);
+ clk_put(i2s->iis_busclk);
+ clk_put(i2s->iis_clk);
+ clk_put(mout_audss);
+ clk_put(mout_epll);
+ clk_put(fout_epll);
+ return 0;
+err4:
+ clk_put(i2s->iis_busclk);
+err3:
+ clk_put(i2s->iis_clk);
+err2:
+ clk_put(mout_audss);
+err1:
+ clk_put(mout_epll);
+ clk_put(fout_epll);
+err_i2sv5:
+ /* Not implemented for I2Sv5 core yet */
+err:
+ iounmap(i2s->regs);
+
+ return ret;
+}
+
+static __devexit int s3c64xx_iis_dev_remove(struct platform_device *pdev)
+{
+ dev_err(&pdev->dev, "Device removal not yet supported\n");
+ return 0;
+}
+
+static struct platform_driver s3c64xx_iis_driver = {
+ .probe = s3c64xx_iis_dev_probe,
+ .remove = s3c64xx_iis_dev_remove,
+ .driver = {
+ .name = "samsung-i2s",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init s3c64xx_i2s_init(void)
+{
+ return platform_driver_register(&s3c64xx_iis_driver);
+}
+module_init(s3c64xx_i2s_init);
+
+static void __exit s3c64xx_i2s_exit(void)
+{
+ platform_driver_unregister(&s3c64xx_iis_driver);
+}
+module_exit(s3c64xx_i2s_exit);
+
+/* Module information */
+MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
+MODULE_DESCRIPTION("S5PC1XX I2S SoC Interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/samsung/s5pc1xx-i2s.h b/sound/soc/samsung/s5pc1xx-i2s.h
new file mode 100644
index 0000000..b754cd5
--- /dev/null
+++ b/sound/soc/samsung/s5pc1xx-i2s.h
@@ -0,0 +1,124 @@
+/* sound/soc/s3c24xx/s3c64xx-i2s.h
+ *
+ * ALSA SoC Audio Layer - S3C64XX I2S driver
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SND_SOC_S3C24XX_S3C64XX_I2S_H
+#define __SND_SOC_S3C24XX_S3C64XX_I2S_H __FILE__
+
+struct clk;
+
+//#include "s3c-i2s-v2.h"
+//==
+
+#define S3C_I2SV2_DIV_BCLK (1)
+#define S3C_I2SV2_DIV_RCLK (2)
+#define S3C_I2SV2_DIV_PRESCALER (3)
+
+/**
+ * struct s3c_i2sv2_info - S3C I2S-V2 information
+ * @dev: The parent device passed to use from the probe.
+ * @regs: The pointer to the device registe block.
+ * @master: True if the I2S core is the I2S bit clock master.
+ * @dma_playback: DMA information for playback channel.
+ * @dma_capture: DMA information for capture channel.
+ * @suspend_iismod: PM save for the IISMOD register.
+ * @suspend_iiscon: PM save for the IISCON register.
+ * @suspend_iispsr: PM save for the IISPSR register.
+ *
+ * This is the private codec state for the hardware associated with an
+ * I2S channel such as the register mappings and clock sources.
+ */
+struct s3c_i2sv2_info {
+ struct device *dev;
+ void __iomem *regs;
+
+ struct clk *sclk_audio;
+ struct clk *iis_ipclk;
+ struct clk *iis_cclk;
+ struct clk *iis_clk;
+ struct clk *iis_busclk;
+ struct regulator *regulator;
+
+ unsigned char master;
+
+ struct s3c_dma_params *dma_playback;
+ struct s3c_dma_params *dma_capture;
+
+ u32 suspend_iismod;
+ u32 suspend_iiscon;
+ u32 suspend_iispsr;
+ u32 suspend_iisahb;
+ u32 suspend_audss_clksrc;
+ u32 suspend_audss_clkdiv;
+ u32 suspend_audss_clkgate;
+};
+
+struct s3c_i2sv2_rate_calc {
+ unsigned int clk_div; /* for prescaler */
+ unsigned int fs_div; /* for root frame clock */
+};
+
+extern int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
+ unsigned int *fstab,
+ unsigned int rate, struct clk *clk);
+
+/**
+ * s3c_i2sv2_probe - probe for i2s device helper
+ * @pdev: The platform device supplied to the original probe.
+ * @dai: The ASoC DAI structure supplied to the original probe.
+ * @i2s: Our local i2s structure to fill in.
+ * @base: The base address for the registers.
+ */
+extern int s3c_i2sv2_probe(struct platform_device *pdev,
+ struct snd_soc_dai *dai,
+ struct s3c_i2sv2_info *i2s,
+ unsigned long base);
+
+/**
+ * s3c_i2sv2_register_dai - register dai with soc core
+ * @dai: The snd_soc_dai structure to register
+ *
+ * Fill in any missing fields and then register the given dai with the
+ * soc core.
+ */
+extern int s3c_i2sv2_register_dai(struct snd_soc_dai *dai);
+extern void s5p_idma_init(void *);
+
+//==
+
+#define USE_CLKAUDIO 1
+
+#define S3C64XX_DIV_BCLK S3C_I2SV2_DIV_BCLK
+#define S3C64XX_DIV_RCLK S3C_I2SV2_DIV_RCLK
+#define S3C64XX_DIV_PRESCALER S3C_I2SV2_DIV_PRESCALER
+
+#define S3C64XX_CLKSRC_PCLK (0)
+#define S3C64XX_CLKSRC_MUX (1)
+#define S3C64XX_CLKSRC_CDCLK (2)
+
+extern struct snd_soc_dai s3c64xx_i2s_dai[];
+
+extern struct snd_soc_dai i2s_sec_fifo_dai;
+extern struct snd_soc_dai i2s_dai;
+extern struct snd_soc_platform s3c_dma_wrapper;
+
+extern struct clk *s3c64xx_i2s_get_clock(struct snd_soc_dai *dai);
+extern int s5p_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai);
+extern int s5p_i2s_startup(struct snd_soc_dai *dai);
+extern int s5p_i2s_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai);
+extern void s5p_i2s_sec_init(void *, dma_addr_t);
+
+#endif /* __SND_SOC_S3C24XX_S3C64XX_I2S_H */
generated by cgit v1.1 at 2025-01-06 08:36:31 +0000