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* OMAP: control: move plat-omap/control.h to mach-omap2/control.hPaul Walmsley2010-10-081-1/+1
| | | | | | | | | | | | | | | | | Only OMAP2+ platforms have the System Control Module (SCM) IP block. In the past, we've kept the SCM header file in plat-omap. This has led to abuse - device drivers including it; includes being added that create implicit dependencies on OMAP2+ builds; etc. In response, move the SCM headers into mach-omap2/. As part of this, remove the direct SCM access from the OMAP UDC driver. It was clearly broken. The UDC code needs an indepth review for use on OMAP2+ chips. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Kyungmin Park <kyungmin.park@samsung.com>
* OMAP3xxx: clock: add clkdev aliases for McBSP fclk source switchingPaul Walmsley2010-10-081-0/+10
| | | | | | | | | | The OMAP3 clock tree already contains the infrastructure to support clock framework-based McBSP functional clock source switching. But it did not contain the clkdev aliases for the McBSP code to refer to the parent clocks in an SoC integration-neutral way. So, add the clkdev aliases for the parent clocks. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP clock: Add uart4_ick/fck definitions for 3630Govindraj.R2010-09-291-0/+22
| | | | | | | | | This is only valid for omap 36xx family of chips. Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* omap: crypto: updates to enable omap aesDmitry Kasatkin2010-09-271-1/+1
| | | | | | | | Updates to enable omap aes Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> [tony@atomide.com: updated to use CONFIG_ARCH_OMAP2/3 instead of old 24XX/34XX] Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP3: Fix a cpu type check problemstanley.miao2010-08-161-7/+7
| | | | | | | | | | | | | | cpu_is_omap3517() and cpu_is_omap3505() are the subgroups of cpu_is_omap34xx(), so we should check cpu_is_omap3517() and cpu_is_omap3505() first, then check cpu_is_omap34xx(). Otherwise, All AM35XX (Sitara) clocks do not get registered and device drivers (ti_hecc, etc...) that depend on those clocks are failing to get the clock and end up with non working device. Signed-off-by: Stanley.Miao <stanley.miao@windriver.com> Tested-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'devel-map-io' into omap-for-linusTony Lindgren2010-08-041-0/+5
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| * ARM: AMBA: Add pclk definition for platforms using primecellsRussell King2010-07-221-0/+5
| | | | | | | | | | | | | | | | Add a dummy clk definition for the APB pclk signal on all platforms using the AMBA bus infrastructure. This ensures that these platforms continue to work when the core amba bus code controls the APB pclk. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | OMAP3: wait on IDLEST after enabling USBTLL fclkAnand Gadiyar2010-07-261-1/+1
|/ | | | | | | | | | | | | | | | | | | We need to wait on the IDLEST bit after the clocks are enabled before attempting to access any register. Currently, the USBTLL i-clock ops uses the clkops_omap2_dflt_wait, while the USBTLL f-clock ops uses clkops_omap2_dflt. If the i-clock is enabled first, the clkops_omap2_dflt_wait is short-circuited as the companion f-clock is not enabled. This can cause a data abort if the IDLEST has not transitioned, and we try to access a USBTLL register. Since the USBTLL i-clock and f-clock could be enabled in any order, this is a bug. Fix it by changing the clkops for the f-clock. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds2010-05-211-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (46 commits) random: simplify fips mode crypto: authenc - Fix cryptlen calculation crypto: talitos - add support for sha224 crypto: talitos - add hash algorithms crypto: talitos - second prepare step for adding ahash algorithms crypto: talitos - prepare for adding ahash algorithms crypto: n2 - Add Niagara2 crypto driver crypto: skcipher - Add ablkcipher_walk interfaces crypto: testmgr - Add testing for async hashing and update/final crypto: tcrypt - Add speed tests for async hashing crypto: scatterwalk - Fix scatterwalk_done() test crypto: hifn_795x - Rename ablkcipher_walk to hifn_cipher_walk padata: Use get_online_cpus/put_online_cpus in padata_free padata: Add some code comments padata: Flush the padata queues actively padata: Use a timer to handle remaining objects in the reorder queues crypto: shash - Remove usage of CRYPTO_MINALIGN crypto: mv_cesa - Use resource_size crypto: omap - OMAP macros corrected padata: Use get_online_cpus/put_online_cpus ... Fix up conflicts in arch/arm/mach-omap2/devices.c
| * Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6Herbert Xu2010-05-031-1/+1
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| * | crypto: omap - Updates omap sham device related platform codeDmitry Kasatkin2010-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | - registration with multi OMAP kernels support - clocks Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | | OMAP3 clock: add support for setting the divider for sys_clkout2 using ↵Laine Walker-Avina2010-05-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_set_rate Add clock framework support for changing the rate of sys_clkout2. Signed-off-by: Laine Walker-Avina <lwalkera@ieee.org> [paul@pwsan.com: added commit message, added .round_rate pointer] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | | OMAP3 clock: remove unnecessary duplicate of dpll4_m2_ck, added for 36xxPaul Walmsley2010-05-201-127/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 678bc9a2eabb7f444ef8ad1cfc5ef394e2bd8bf2 split dpll4_m2_ck, creating a 34xx and a 36xx variant, to handle the additional 16 divider steps provided on the 36xx. This in turn required dynamic rewriting of the clock tree during initialization, which is undesirable. All this seems to be unnecessary, though, since the additional 16 divider steps can simply be marked with RATE_IN_36XX. This patch does so and re-merges the affected structures. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>
* | | OMAP3 clock: rename RATE_IN_343X, RATE_IN_3430ES2 to match realityPaul Walmsley2010-05-201-118/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the RATE_IN_343X clksel_rate.rate flag to be RATE_IN_3XXX, to reflect that these rates are valid on all OMAP3 platforms, not just 343X. Also rename the RATE_IN_OMAP3430ES2 clksel_rate.rate flag to be RATE_IN_OMAP3430ES2PLUS, to reflect that these flags are valid on all OMAP3 platforms after 3430ES2. This patch should not result in any functional changes. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com>
* | | OMAP2+ clock: remove DEFAULT_RATE clksel_rate flagPaul Walmsley2010-05-201-40/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DEFAULT_RATE clksel_rate flag is essentially useless. It was set on some of the lowest divisors, which, when switching to a much higher-rate parent, could have potentially resulted in rates that exceeded the hardware specifications for downstream clocks in the window between the clk_set_parent(), and a subsequent clk_set_rate(). It seems much safer to just remove the flag and always use the highest available divisor (resulting in the lowest possible rate) after the switch, and this patch does so. Ideally, it would be best to first attempt to switch to a divisor that matches the clock's rate with the previous parent, if at all possible. But that is a project for some other day or some other person. The parent changing code is rarely used. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | | OMAP3: clock data: Update name string for EMAC clocksSriram2010-05-201-2/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | The emac driver currently uses Davinci clock names for the module and phy clocks. Updated the omap3xxx_clks table to match the names used by the Davinci emac driver. Note that eventually the EMAC clocks should be renamed to be generic. Signed-off-by: Sriramakrishnan <srk@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> [tony@atomide.com: updated patch description to match the patch] Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP3: clock: fix enable bit used for dpll4_m4x2 clockRanjith Lohithakshan2010-03-311-1/+1
|/ | | | | | | | | | | The enable bit for dpll4_m4x2 clock should be OMAP3430_PWRDN_DSS1_SHIFT. The code erroneously uses OMAP3430_PWRDN_CAM_SHIFT which is meant for dpll4_m5x2 clock. This came into notice during a recent review of the clock tree. Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: clock: add capability to change rate of dpll4_m5_ck_3630Vimarsh Zutshi2010-02-241-0/+2
| | | | | | | | | Add necessary clk_sel definitions to clock framework to allow changing dpll4_m5_ck_3630 rate. This is used by the ISP driver. Signed-off-by: Vimarsh Zutshi <vimarsh.zutshi@nokia.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP clock: drop RATE_FIXED clock flagPaul Walmsley2010-02-241-11/+0
| | | | | | | | | | | | | | | | | | The RATE_FIXED clock flag is pointless. In the OMAP1 clock code, it simply causes the omap1_clk_round_rate() function to return the current rate of the clock. omap1_clk_round_rate(), however, should never be called for a fixed-rate clock, since none of these clocks have a .round_rate function pointer set in their struct clk records. Similarly, in the OMAP2+ clock code, the RATE_FIXED flag just causes the clock code to emit a warning if the OMAP clock maintainer was foolish enough to add a .round_rate function pointer to a fixed-rate clock. "Doctor, it hurts when I pretend that a fixed-rate clock is rate-changeable." "Then don't pretend that a fixed-rate clock is rate-changeable." It has no functional value. This patch drops the RATE_FIXED clock flag, removing it from all clocks that are so marked. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP3/4 clock: split into per-chip family filesPaul Walmsley2010-02-241-0/+3610
clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
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